src/cpu/sparc/vm/assembler_sparc.hpp
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src/cpu/sparc/vm/assembler_sparc.hpp

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rev 1838 : 6961690: load oops from constant table on SPARC
Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
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1601   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1602   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1603   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1604   void stda(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1605 
1606   // pp 97 (v8)
1607 
1608   inline void stc(   int crd, Register s1, Register s2 );
1609   inline void stc(   int crd, Register s1, int simm13a);
1610   inline void stdc(  int crd, Register s1, Register s2 );
1611   inline void stdc(  int crd, Register s1, int simm13a);
1612   inline void stcsr( int crd, Register s1, Register s2 );
1613   inline void stcsr( int crd, Register s1, int simm13a);
1614   inline void stdcq( int crd, Register s1, Register s2 );
1615   inline void stdcq( int crd, Register s1, int simm13a);
1616 
1617   // pp 230
1618 
1619   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1620   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }




1621   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1622   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1623   void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1624   void subc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1625   void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1626   void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1627 
1628   // pp 231
1629 
1630   inline void swap( Register s1, Register s2, Register d );
1631   inline void swap( Register s1, int simm13a, Register d);
1632   inline void swap( Address& a,               Register d, int offset = 0 );
1633 
1634   // pp 232
1635 
1636   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1637   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1638 
1639   // pp 234, note op in book is wrong, see pp 268
1640 


1874   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
1875 public:
1876   void sethi(const AddressLiteral& addrlit, Register d);
1877   void patchable_sethi(const AddressLiteral& addrlit, Register d);
1878 
1879   // compute the size of a sethi/set
1880   static int  size_of_sethi( address a, bool worst_case = false );
1881   static int  worst_case_size_of_set();
1882 
1883   // set may be either setsw or setuw (high 32 bits may be zero or sign)
1884 private:
1885   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
1886 public:
1887   void set(const AddressLiteral& addrlit, Register d);
1888   void set(intptr_t value, Register d);
1889   void set(address addr, Register d, RelocationHolder const& rspec);
1890   void patchable_set(const AddressLiteral& addrlit, Register d);
1891   void patchable_set(intptr_t value, Register d);
1892   void set64(jlong value, Register d, Register tmp);
1893 



1894   // sign-extend 32 to 64
1895   inline void signx( Register s, Register d ) { sra( s, G0, d); }
1896   inline void signx( Register d )             { sra( d, G0, d); }
1897 
1898   inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1899   inline void not1( Register d )             { xnor( d, G0, d ); }
1900 
1901   inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1902   inline void neg( Register d )             { sub( G0, d, d ); }
1903 
1904   inline void cas(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1905   inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1906   // Functions for isolating 64 bit atomic swaps for LP64
1907   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1908   inline void cas_ptr(  Register s1, Register s2, Register d) {
1909 #ifdef _LP64
1910     casx( s1, s2, d );
1911 #else
1912     cas( s1, s2, d );
1913 #endif




1601   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1602   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1603   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1604   void stda(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1605 
1606   // pp 97 (v8)
1607 
1608   inline void stc(   int crd, Register s1, Register s2 );
1609   inline void stc(   int crd, Register s1, int simm13a);
1610   inline void stdc(  int crd, Register s1, Register s2 );
1611   inline void stdc(  int crd, Register s1, int simm13a);
1612   inline void stcsr( int crd, Register s1, Register s2 );
1613   inline void stcsr( int crd, Register s1, int simm13a);
1614   inline void stdcq( int crd, Register s1, Register s2 );
1615   inline void stdcq( int crd, Register s1, int simm13a);
1616 
1617   // pp 230
1618 
1619   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1620   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1621 
1622   // Note: offset is added to s2.
1623   inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1624 
1625   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1626   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1627   void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1628   void subc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1629   void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1630   void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1631 
1632   // pp 231
1633 
1634   inline void swap( Register s1, Register s2, Register d );
1635   inline void swap( Register s1, int simm13a, Register d);
1636   inline void swap( Address& a,               Register d, int offset = 0 );
1637 
1638   // pp 232
1639 
1640   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1641   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1642 
1643   // pp 234, note op in book is wrong, see pp 268
1644 


1878   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
1879 public:
1880   void sethi(const AddressLiteral& addrlit, Register d);
1881   void patchable_sethi(const AddressLiteral& addrlit, Register d);
1882 
1883   // compute the size of a sethi/set
1884   static int  size_of_sethi( address a, bool worst_case = false );
1885   static int  worst_case_size_of_set();
1886 
1887   // set may be either setsw or setuw (high 32 bits may be zero or sign)
1888 private:
1889   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
1890 public:
1891   void set(const AddressLiteral& addrlit, Register d);
1892   void set(intptr_t value, Register d);
1893   void set(address addr, Register d, RelocationHolder const& rspec);
1894   void patchable_set(const AddressLiteral& addrlit, Register d);
1895   void patchable_set(intptr_t value, Register d);
1896   void set64(jlong value, Register d, Register tmp);
1897 
1898   // Compute size of set64.
1899   static int size_of_set64(jlong value);
1900 
1901   // sign-extend 32 to 64
1902   inline void signx( Register s, Register d ) { sra( s, G0, d); }
1903   inline void signx( Register d )             { sra( d, G0, d); }
1904 
1905   inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1906   inline void not1( Register d )             { xnor( d, G0, d ); }
1907 
1908   inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1909   inline void neg( Register d )             { sub( G0, d, d ); }
1910 
1911   inline void cas(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1912   inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1913   // Functions for isolating 64 bit atomic swaps for LP64
1914   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1915   inline void cas_ptr(  Register s1, Register s2, Register d) {
1916 #ifdef _LP64
1917     casx( s1, s2, d );
1918 #else
1919     cas( s1, s2, d );
1920 #endif
src/cpu/sparc/vm/assembler_sparc.hpp
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