1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
26 jint& stub_inst = *(jint*) branch;
27 stub_inst = patched_branch(target - branch, stub_inst, 0);
28 }
29
30 #ifndef PRODUCT
31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
32 jint stub_inst = *(jint*) branch;
33 print_instruction(stub_inst);
34 ::tty->print("%s", " (unresolved)");
35 }
36 #endif // PRODUCT
37
38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
39
40
41 inline int AddressLiteral::low10() const {
42 return Assembler::low10(value());
43 }
44
45
46 // inlines for SPARC assembler -- dmu 5/97
47
48 inline void Assembler::check_delay() {
49 # ifdef CHECK_DELAY
50 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
51 delay_state = no_delay;
52 # endif
53 }
54
55 inline void Assembler::emit_long(int x) {
56 check_delay();
57 AbstractAssembler::emit_long(x);
58 }
59
60 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
61 relocate(rtype);
62 emit_long(x);
63 }
64
65 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
66 relocate(rspec);
67 emit_long(x);
68 }
69
70
71 inline void Assembler::add(Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
72 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
73 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
74
75 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
76 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
77
78 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
79 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
80
81 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
82 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
83
84 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
85 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
86
87 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
88 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
89
90 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
91 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
92
93 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
94 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
95
96 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
97 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
98
99 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
100 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
101
102 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
103 if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
104 else ldf(w, s1, s2.as_constant(), d);
105 }
106
107 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
108 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
109
110 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
111
112 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
113 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
114 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
115 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
116
117 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
118 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
119 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
120 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
121 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
122 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
123
124 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
125 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
126
127 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
128 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
129 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
130 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
131 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
132 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
133 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
134 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
135 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
136 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
137
138 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
139 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
140 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
141 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
142
143 #ifdef _LP64
144 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
145 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
146 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
147 #else
148 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
149 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
150 #endif
151
152 #ifdef ASSERT
153 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
154 # ifdef _LP64
155 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }
156 # else
157 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }
158 # endif
159 #endif
160
161 inline void Assembler::ld( const Address& a, Register d, int offset) {
162 if (a.has_index()) { assert(offset == 0, ""); ld( a.base(), a.index(), d); }
163 else { ld( a.base(), a.disp() + offset, d); }
164 }
165 inline void Assembler::ldsb(const Address& a, Register d, int offset) {
166 if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(), d); }
167 else { ldsb(a.base(), a.disp() + offset, d); }
168 }
169 inline void Assembler::ldsh(const Address& a, Register d, int offset) {
170 if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(), d); }
171 else { ldsh(a.base(), a.disp() + offset, d); }
172 }
173 inline void Assembler::ldsw(const Address& a, Register d, int offset) {
174 if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(), d); }
175 else { ldsw(a.base(), a.disp() + offset, d); }
176 }
177 inline void Assembler::ldub(const Address& a, Register d, int offset) {
178 if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(), d); }
179 else { ldub(a.base(), a.disp() + offset, d); }
180 }
181 inline void Assembler::lduh(const Address& a, Register d, int offset) {
182 if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(), d); }
183 else { lduh(a.base(), a.disp() + offset, d); }
184 }
185 inline void Assembler::lduw(const Address& a, Register d, int offset) {
186 if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(), d); }
187 else { lduw(a.base(), a.disp() + offset, d); }
188 }
189 inline void Assembler::ldd( const Address& a, Register d, int offset) {
190 if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(), d); }
191 else { ldd( a.base(), a.disp() + offset, d); }
192 }
193 inline void Assembler::ldx( const Address& a, Register d, int offset) {
194 if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(), d); }
195 else { ldx( a.base(), a.disp() + offset, d); }
196 }
197
198 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }
199 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }
200 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }
201 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }
202 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }
203 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }
204 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }
205 inline void Assembler::ld( Register s1, RegisterOrConstant s2, Register d) { ld( Address(s1, s2), d); }
206 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }
207
208 // form effective addresses this way:
209 inline void Assembler::add(const Address& a, Register d, int offset) {
210 if (a.has_index()) add(a.base(), a.index(), d);
211 else { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
212 if (offset != 0) add(d, offset, d);
213 }
214 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
215 if (s2.is_register()) add(s1, s2.as_register(), d);
216 else { add(s1, s2.as_constant() + offset, d); offset = 0; }
217 if (offset != 0) add(d, offset, d);
218 }
219
220 inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) {
221 if (s2.is_register()) andn(s1, s2.as_register(), d);
222 else andn(s1, s2.as_constant(), d);
223 }
224
225 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
226 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
227
228
229 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
230 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
231
232 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
233
234
235 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
236 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
237
238 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
239
240 // pp 222
241
242 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {
243 if (s2.is_register()) stf(w, d, s1, s2.as_register());
244 else stf(w, d, s1, s2.as_constant());
245 }
246
247 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
248 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
249
250 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
251
252 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
253 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
254 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
255 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
256
257 // p 226
258
259 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
260 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
261 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
262 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
263 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
264 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
265
266
267 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
268 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
269 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
270 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
271
272 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
273 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
274
275 #ifdef ASSERT
276 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
277 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }
278 #endif
279
280 inline void Assembler::stb(Register d, const Address& a, int offset) {
281 if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index() ); }
282 else { stb(d, a.base(), a.disp() + offset); }
283 }
284 inline void Assembler::sth(Register d, const Address& a, int offset) {
285 if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index() ); }
286 else { sth(d, a.base(), a.disp() + offset); }
287 }
288 inline void Assembler::stw(Register d, const Address& a, int offset) {
289 if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index() ); }
290 else { stw(d, a.base(), a.disp() + offset); }
291 }
292 inline void Assembler::st( Register d, const Address& a, int offset) {
293 if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index() ); }
294 else { st( d, a.base(), a.disp() + offset); }
295 }
296 inline void Assembler::std(Register d, const Address& a, int offset) {
297 if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index() ); }
298 else { std(d, a.base(), a.disp() + offset); }
299 }
300 inline void Assembler::stx(Register d, const Address& a, int offset) {
301 if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index() ); }
302 else { stx(d, a.base(), a.disp() + offset); }
303 }
304
305 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }
306 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }
307 inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }
308 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }
309 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }
310 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }
311
312 // v8 p 99
313
314 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
315 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
316 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
317 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
318 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
319 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
320 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
321 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
322
323
324 // pp 231
325
326 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
327 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
328
329 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
330
331
332 // Use the right loads/stores for the platform
333 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
334 #ifdef _LP64
335 Assembler::ldx(s1, s2, d);
336 #else
337 Assembler::ld( s1, s2, d);
338 #endif
339 }
340
341 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
342 #ifdef _LP64
343 Assembler::ldx(s1, simm13a, d);
344 #else
345 Assembler::ld( s1, simm13a, d);
346 #endif
347 }
348
349 #ifdef ASSERT
350 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
351 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {
352 ld_ptr(s1, in_bytes(simm13a), d);
353 }
354 #endif
355
356 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
357 #ifdef _LP64
358 Assembler::ldx(s1, s2, d);
359 #else
360 Assembler::ld( s1, s2, d);
361 #endif
362 }
363
364 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {
365 #ifdef _LP64
366 Assembler::ldx(a, d, offset);
367 #else
368 Assembler::ld( a, d, offset);
369 #endif
370 }
371
372 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
373 #ifdef _LP64
374 Assembler::stx(d, s1, s2);
375 #else
376 Assembler::st( d, s1, s2);
377 #endif
378 }
379
380 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
381 #ifdef _LP64
382 Assembler::stx(d, s1, simm13a);
383 #else
384 Assembler::st( d, s1, simm13a);
385 #endif
386 }
387
388 #ifdef ASSERT
389 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
390 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {
391 st_ptr(d, s1, in_bytes(simm13a));
392 }
393 #endif
394
395 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
396 #ifdef _LP64
397 Assembler::stx(d, s1, s2);
398 #else
399 Assembler::st( d, s1, s2);
400 #endif
401 }
402
403 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {
404 #ifdef _LP64
405 Assembler::stx(d, a, offset);
406 #else
407 Assembler::st( d, a, offset);
408 #endif
409 }
410
411 // Use the right loads/stores for the platform
412 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
413 #ifdef _LP64
414 Assembler::ldx(s1, s2, d);
415 #else
416 Assembler::ldd(s1, s2, d);
417 #endif
418 }
419
420 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
421 #ifdef _LP64
422 Assembler::ldx(s1, simm13a, d);
423 #else
424 Assembler::ldd(s1, simm13a, d);
425 #endif
426 }
427
428 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
429 #ifdef _LP64
430 Assembler::ldx(s1, s2, d);
431 #else
432 Assembler::ldd(s1, s2, d);
433 #endif
434 }
435
436 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {
437 #ifdef _LP64
438 Assembler::ldx(a, d, offset);
439 #else
440 Assembler::ldd(a, d, offset);
441 #endif
442 }
443
444 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
445 #ifdef _LP64
446 Assembler::stx(d, s1, s2);
447 #else
448 Assembler::std(d, s1, s2);
449 #endif
450 }
451
452 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
453 #ifdef _LP64
454 Assembler::stx(d, s1, simm13a);
455 #else
456 Assembler::std(d, s1, simm13a);
457 #endif
458 }
459
460 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
461 #ifdef _LP64
462 Assembler::stx(d, s1, s2);
463 #else
464 Assembler::std(d, s1, s2);
465 #endif
466 }
467
468 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
469 #ifdef _LP64
470 Assembler::stx(d, a, offset);
471 #else
472 Assembler::std(d, a, offset);
473 #endif
474 }
475
476 // Functions for isolating 64 bit shifts for LP64
477
478 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
479 #ifdef _LP64
480 Assembler::sllx(s1, s2, d);
481 #else
482 Assembler::sll( s1, s2, d);
483 #endif
484 }
485
486 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
487 #ifdef _LP64
488 Assembler::sllx(s1, imm6a, d);
489 #else
490 Assembler::sll( s1, imm6a, d);
491 #endif
492 }
493
494 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
495 #ifdef _LP64
496 Assembler::srlx(s1, s2, d);
497 #else
498 Assembler::srl( s1, s2, d);
499 #endif
500 }
501
502 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
503 #ifdef _LP64
504 Assembler::srlx(s1, imm6a, d);
505 #else
506 Assembler::srl( s1, imm6a, d);
507 #endif
508 }
509
510 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
511 if (s2.is_register()) sll_ptr(s1, s2.as_register(), d);
512 else sll_ptr(s1, s2.as_constant(), d);
513 }
514
515 // Use the right branch for the platform
516
517 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
518 if (VM_Version::v9_instructions_work())
519 Assembler::bp(c, a, icc, p, d, rt);
520 else
521 Assembler::br(c, a, d, rt);
522 }
523
524 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
525 br(c, a, p, target(L));
526 }
527
528
529 // Branch that tests either xcc or icc depending on the
530 // architecture compiled (LP64 or not)
531 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
532 #ifdef _LP64
533 Assembler::bp(c, a, xcc, p, d, rt);
534 #else
535 MacroAssembler::br(c, a, p, d, rt);
536 #endif
537 }
538
539 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
540 brx(c, a, p, target(L));
541 }
542
543 inline void MacroAssembler::ba( bool a, Label& L ) {
544 br(always, a, pt, L);
545 }
546
547 // Warning: V9 only functions
548 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
549 Assembler::bp(c, a, cc, p, d, rt);
550 }
551
552 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
553 Assembler::bp(c, a, cc, p, L);
554 }
555
556 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
557 if (VM_Version::v9_instructions_work())
558 fbp(c, a, fcc0, p, d, rt);
559 else
560 Assembler::fb(c, a, d, rt);
561 }
562
563 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
564 fb(c, a, p, target(L));
565 }
566
567 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
568 Assembler::fbp(c, a, cc, p, d, rt);
569 }
570
571 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
572 Assembler::fbp(c, a, cc, p, L);
573 }
574
575 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
576 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
577
578 // Call with a check to see if we need to deal with the added
579 // expense of relocation and if we overflow the displacement
580 // of the quick call instruction./
581 // Check to see if we have to deal with relocations
582 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
583 #ifdef _LP64
584 intptr_t disp;
585 // NULL is ok because it will be relocated later.
586 // Must change NULL to a reachable address in order to
587 // pass asserts here and in wdisp.
588 if ( d == NULL )
589 d = pc();
590
591 // Is this address within range of the call instruction?
592 // If not, use the expensive instruction sequence
593 disp = (intptr_t)d - (intptr_t)pc();
594 if ( disp != (intptr_t)(int32_t)disp ) {
595 relocate(rt);
596 AddressLiteral dest(d);
597 jumpl_to(dest, O7, O7);
598 }
599 else {
600 Assembler::call( d, rt );
601 }
602 #else
603 Assembler::call( d, rt );
604 #endif
605 }
606
607 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
608 MacroAssembler::call( target(L), rt);
609 }
610
611
612
613 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
614 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
615
616 // prefetch instruction
617 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
618 if (VM_Version::v9_instructions_work())
619 Assembler::bp( never, true, xcc, pt, d, rt );
620 }
621 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
622
623
624 // clobbers o7 on V8!!
625 // returns delta from gotten pc to addr after
626 inline int MacroAssembler::get_pc( Register d ) {
627 int x = offset();
628 if (VM_Version::v9_instructions_work())
629 rdpc(d);
630 else {
631 Label lbl;
632 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
633 if (d == O7) delayed()->nop();
634 else delayed()->mov(O7, d);
635 bind(lbl);
636 }
637 return offset() - x;
638 }
639
640
641 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
642
643
644 // Loads the current PC of the following instruction as an immediate value in
645 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
646 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
647 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
648 #ifdef _LP64
649 Unimplemented();
650 #else
651 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
652 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
653 #endif
654 return thepc;
655 }
656
657
658 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
659 assert_not_delayed();
660 sethi(addrlit, d);
661 ld(d, addrlit.low10() + offset, d);
662 }
663
664
665 inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) {
666 assert_not_delayed();
667 sethi(addrlit, d);
668 ld_ptr(d, addrlit.low10() + offset, d);
669 }
670
671
672 inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
673 assert_not_delayed();
674 sethi(addrlit, temp);
675 st(s, temp, addrlit.low10() + offset);
676 }
677
678
679 inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
680 assert_not_delayed();
681 sethi(addrlit, temp);
682 st_ptr(s, temp, addrlit.low10() + offset);
683 }
684
685
686 // This code sequence is relocatable to any address, even on LP64.
687 inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) {
688 assert_not_delayed();
689 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
690 // variable length instruction streams.
691 patchable_sethi(addrlit, temp);
692 jmpl(temp, addrlit.low10() + offset, d);
693 }
694
695
696 inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) {
697 jumpl_to(addrlit, temp, G0, offset);
698 }
699
700
701 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,
702 int ld_offset, int jmp_offset) {
703 assert_not_delayed();
704 //sethi(al); // sethi is caller responsibility for this one
705 ld_ptr(a, temp, ld_offset);
706 jmp(temp, jmp_offset);
707 }
708
709
710 inline void MacroAssembler::set_oop(jobject obj, Register d) {
711 set_oop(allocate_oop_address(obj), d);
712 }
713
714
715 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
716 set_oop(constant_oop_address(obj), d);
717 }
718
719
720 inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) {
721 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
722 set(obj_addr, d);
723 }
724
725
726 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
727 if (a.is_register())
728 mov(a.as_register(), d);
729 else
730 ld (a.as_address(), d);
731 }
732
733 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
734 if (a.is_register())
735 mov(s, a.as_register());
736 else
737 st_ptr (s, a.as_address()); // ABI says everything is right justified.
738 }
739
740 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
741 if (a.is_register())
742 mov(s, a.as_register());
743 else
744 st_ptr (s, a.as_address());
745 }
746
747
748 #ifdef _LP64
749 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
750 if (a.is_float_register())
751 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
752 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
753 else
754 // Floats are stored in the high half of the stack entry
755 // The low half is undefined per the ABI.
756 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
757 }
758
759 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
760 if (a.is_float_register())
761 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
762 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
763 else
764 stf(FloatRegisterImpl::D, s, a.as_address());
765 }
766
767 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
768 if (a.is_register())
769 mov(s, a.as_register());
770 else
771 stx(s, a.as_address());
772 }
773 #endif
774
775 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
776 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
777 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
778 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
779
780 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
781 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
782 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
783 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
784
785 // returns if membar generates anything, obviously this code should mirror
786 // membar below.
787 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
788 if( !os::is_MP() ) return false; // Not needed on single CPU
789 if( VM_Version::v9_instructions_work() ) {
790 const Membar_mask_bits effective_mask =
791 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
792 return (effective_mask != 0);
793 } else {
794 return true;
795 }
796 }
797
798 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
799 // Uniprocessors do not need memory barriers
800 if (!os::is_MP()) return;
801 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
802 // 8.4.4.3, a.31 and a.50.
803 if( VM_Version::v9_instructions_work() ) {
804 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
805 // of the mmask subfield of const7a that does anything that isn't done
806 // implicitly is StoreLoad.
807 const Membar_mask_bits effective_mask =
808 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
809 if ( effective_mask != 0 ) {
810 Assembler::membar( effective_mask );
811 }
812 } else {
813 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
814 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
815 // which guarantees that all stores behave as if an stbar were issued just after
816 // each one of them. On these machines, stbar ought to be a nop. There doesn't
817 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
818 // it can't be specified by stbar, nor have I come up with a way to simulate it.
819 //
820 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
821 // space. Put one here to be on the safe side.
822 Assembler::ldstub(SP, 0, G0);
823 }
824 }