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rev 1838 : 6961690: load oops from constant table on SPARC
Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
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--- old/src/cpu/sparc/vm/assembler_sparc.inline.hpp
+++ new/src/cpu/sparc/vm/assembler_sparc.inline.hpp
1 1 /*
2 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
26 26 jint& stub_inst = *(jint*) branch;
27 27 stub_inst = patched_branch(target - branch, stub_inst, 0);
28 28 }
29 29
30 30 #ifndef PRODUCT
31 31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
32 32 jint stub_inst = *(jint*) branch;
33 33 print_instruction(stub_inst);
34 34 ::tty->print("%s", " (unresolved)");
35 35 }
36 36 #endif // PRODUCT
37 37
38 38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
39 39
40 40
41 41 inline int AddressLiteral::low10() const {
42 42 return Assembler::low10(value());
43 43 }
44 44
45 45
46 46 // inlines for SPARC assembler -- dmu 5/97
47 47
48 48 inline void Assembler::check_delay() {
49 49 # ifdef CHECK_DELAY
50 50 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
51 51 delay_state = no_delay;
52 52 # endif
53 53 }
54 54
55 55 inline void Assembler::emit_long(int x) {
56 56 check_delay();
57 57 AbstractAssembler::emit_long(x);
58 58 }
59 59
60 60 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
61 61 relocate(rtype);
62 62 emit_long(x);
63 63 }
64 64
65 65 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
66 66 relocate(rspec);
67 67 emit_long(x);
68 68 }
69 69
70 70
71 71 inline void Assembler::add(Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
72 72 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
73 73 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
74 74
75 75 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
76 76 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
77 77
78 78 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
79 79 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
80 80
81 81 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
82 82 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
83 83
84 84 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
85 85 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
86 86
87 87 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
88 88 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
89 89
90 90 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
91 91 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
92 92
93 93 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
94 94 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
95 95
96 96 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
97 97 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
98 98
99 99 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
100 100 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
101 101
102 102 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
103 103 if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
104 104 else ldf(w, s1, s2.as_constant(), d);
105 105 }
106 106
107 107 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
108 108 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
109 109
110 110 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
111 111
112 112 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
113 113 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
114 114 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
115 115 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
116 116
117 117 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
118 118 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
119 119 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
120 120 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
121 121 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
122 122 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
123 123
124 124 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
125 125 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
126 126
127 127 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
128 128 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
129 129 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
130 130 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
131 131 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
132 132 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
133 133 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
134 134 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
135 135 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
136 136 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
137 137
138 138 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
139 139 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
140 140 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
141 141 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
142 142
143 143 #ifdef _LP64
144 144 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
145 145 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
146 146 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
147 147 #else
148 148 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
149 149 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
150 150 #endif
151 151
152 152 #ifdef ASSERT
153 153 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
154 154 # ifdef _LP64
155 155 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }
156 156 # else
157 157 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }
158 158 # endif
159 159 #endif
160 160
161 161 inline void Assembler::ld( const Address& a, Register d, int offset) {
162 162 if (a.has_index()) { assert(offset == 0, ""); ld( a.base(), a.index(), d); }
163 163 else { ld( a.base(), a.disp() + offset, d); }
164 164 }
165 165 inline void Assembler::ldsb(const Address& a, Register d, int offset) {
166 166 if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(), d); }
167 167 else { ldsb(a.base(), a.disp() + offset, d); }
168 168 }
169 169 inline void Assembler::ldsh(const Address& a, Register d, int offset) {
170 170 if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(), d); }
171 171 else { ldsh(a.base(), a.disp() + offset, d); }
172 172 }
173 173 inline void Assembler::ldsw(const Address& a, Register d, int offset) {
174 174 if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(), d); }
175 175 else { ldsw(a.base(), a.disp() + offset, d); }
176 176 }
177 177 inline void Assembler::ldub(const Address& a, Register d, int offset) {
178 178 if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(), d); }
179 179 else { ldub(a.base(), a.disp() + offset, d); }
180 180 }
181 181 inline void Assembler::lduh(const Address& a, Register d, int offset) {
182 182 if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(), d); }
183 183 else { lduh(a.base(), a.disp() + offset, d); }
184 184 }
185 185 inline void Assembler::lduw(const Address& a, Register d, int offset) {
186 186 if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(), d); }
187 187 else { lduw(a.base(), a.disp() + offset, d); }
188 188 }
189 189 inline void Assembler::ldd( const Address& a, Register d, int offset) {
190 190 if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(), d); }
191 191 else { ldd( a.base(), a.disp() + offset, d); }
192 192 }
193 193 inline void Assembler::ldx( const Address& a, Register d, int offset) {
194 194 if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(), d); }
195 195 else { ldx( a.base(), a.disp() + offset, d); }
196 196 }
197 197
198 198 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }
199 199 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }
200 200 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }
201 201 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }
202 202 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }
203 203 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }
204 204 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }
205 205 inline void Assembler::ld( Register s1, RegisterOrConstant s2, Register d) { ld( Address(s1, s2), d); }
206 206 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }
207 207
208 208 // form effective addresses this way:
209 209 inline void Assembler::add(const Address& a, Register d, int offset) {
210 210 if (a.has_index()) add(a.base(), a.index(), d);
211 211 else { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
212 212 if (offset != 0) add(d, offset, d);
213 213 }
214 214 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
215 215 if (s2.is_register()) add(s1, s2.as_register(), d);
216 216 else { add(s1, s2.as_constant() + offset, d); offset = 0; }
217 217 if (offset != 0) add(d, offset, d);
218 218 }
219 219
220 220 inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) {
221 221 if (s2.is_register()) andn(s1, s2.as_register(), d);
222 222 else andn(s1, s2.as_constant(), d);
223 223 }
224 224
225 225 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
226 226 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
227 227
228 228
229 229 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
230 230 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
231 231
232 232 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
233 233
234 234
235 235 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
236 236 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
237 237
238 238 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
239 239
240 240 // pp 222
241 241
242 242 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {
243 243 if (s2.is_register()) stf(w, d, s1, s2.as_register());
244 244 else stf(w, d, s1, s2.as_constant());
245 245 }
246 246
247 247 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
248 248 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
249 249
250 250 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
251 251
252 252 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
253 253 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
254 254 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
255 255 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
256 256
257 257 // p 226
258 258
259 259 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
260 260 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
261 261 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
262 262 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
263 263 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
264 264 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
265 265
266 266
267 267 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
268 268 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
269 269 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
270 270 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
271 271
272 272 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
273 273 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
274 274
275 275 #ifdef ASSERT
276 276 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
277 277 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }
278 278 #endif
279 279
280 280 inline void Assembler::stb(Register d, const Address& a, int offset) {
281 281 if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index() ); }
282 282 else { stb(d, a.base(), a.disp() + offset); }
283 283 }
284 284 inline void Assembler::sth(Register d, const Address& a, int offset) {
285 285 if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index() ); }
286 286 else { sth(d, a.base(), a.disp() + offset); }
287 287 }
288 288 inline void Assembler::stw(Register d, const Address& a, int offset) {
289 289 if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index() ); }
290 290 else { stw(d, a.base(), a.disp() + offset); }
291 291 }
292 292 inline void Assembler::st( Register d, const Address& a, int offset) {
293 293 if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index() ); }
294 294 else { st( d, a.base(), a.disp() + offset); }
295 295 }
296 296 inline void Assembler::std(Register d, const Address& a, int offset) {
297 297 if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index() ); }
298 298 else { std(d, a.base(), a.disp() + offset); }
299 299 }
300 300 inline void Assembler::stx(Register d, const Address& a, int offset) {
301 301 if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index() ); }
302 302 else { stx(d, a.base(), a.disp() + offset); }
303 303 }
304 304
305 305 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }
306 306 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }
307 307 inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }
308 308 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }
309 309 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }
310 310 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }
311 311
312 312 // v8 p 99
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313 313
314 314 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
315 315 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
316 316 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
317 317 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
318 318 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
319 319 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
320 320 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
321 321 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
322 322
323 +inline void Assembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) {
324 + if (s2.is_register()) sub(s1, s2.as_register(), d);
325 + else { sub(s1, s2.as_constant() + offset, d); offset = 0; }
326 + if (offset != 0) sub(d, offset, d);
327 +}
323 328
324 329 // pp 231
325 330
326 331 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
327 332 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
328 333
329 334 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
330 335
331 336
332 337 // Use the right loads/stores for the platform
333 338 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
334 339 #ifdef _LP64
335 340 Assembler::ldx(s1, s2, d);
336 341 #else
337 342 Assembler::ld( s1, s2, d);
338 343 #endif
339 344 }
340 345
341 346 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
342 347 #ifdef _LP64
343 348 Assembler::ldx(s1, simm13a, d);
344 349 #else
345 350 Assembler::ld( s1, simm13a, d);
346 351 #endif
347 352 }
348 353
349 354 #ifdef ASSERT
350 355 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
351 356 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {
352 357 ld_ptr(s1, in_bytes(simm13a), d);
353 358 }
354 359 #endif
355 360
356 361 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
357 362 #ifdef _LP64
358 363 Assembler::ldx(s1, s2, d);
359 364 #else
360 365 Assembler::ld( s1, s2, d);
361 366 #endif
362 367 }
363 368
364 369 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {
365 370 #ifdef _LP64
366 371 Assembler::ldx(a, d, offset);
367 372 #else
368 373 Assembler::ld( a, d, offset);
369 374 #endif
370 375 }
371 376
372 377 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
373 378 #ifdef _LP64
374 379 Assembler::stx(d, s1, s2);
375 380 #else
376 381 Assembler::st( d, s1, s2);
377 382 #endif
378 383 }
379 384
380 385 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
381 386 #ifdef _LP64
382 387 Assembler::stx(d, s1, simm13a);
383 388 #else
384 389 Assembler::st( d, s1, simm13a);
385 390 #endif
386 391 }
387 392
388 393 #ifdef ASSERT
389 394 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
390 395 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {
391 396 st_ptr(d, s1, in_bytes(simm13a));
392 397 }
393 398 #endif
394 399
395 400 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
396 401 #ifdef _LP64
397 402 Assembler::stx(d, s1, s2);
398 403 #else
399 404 Assembler::st( d, s1, s2);
400 405 #endif
401 406 }
402 407
403 408 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {
404 409 #ifdef _LP64
405 410 Assembler::stx(d, a, offset);
406 411 #else
407 412 Assembler::st( d, a, offset);
408 413 #endif
409 414 }
410 415
411 416 // Use the right loads/stores for the platform
412 417 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
413 418 #ifdef _LP64
414 419 Assembler::ldx(s1, s2, d);
415 420 #else
416 421 Assembler::ldd(s1, s2, d);
417 422 #endif
418 423 }
419 424
420 425 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
421 426 #ifdef _LP64
422 427 Assembler::ldx(s1, simm13a, d);
423 428 #else
424 429 Assembler::ldd(s1, simm13a, d);
425 430 #endif
426 431 }
427 432
428 433 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
429 434 #ifdef _LP64
430 435 Assembler::ldx(s1, s2, d);
431 436 #else
432 437 Assembler::ldd(s1, s2, d);
433 438 #endif
434 439 }
435 440
436 441 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {
437 442 #ifdef _LP64
438 443 Assembler::ldx(a, d, offset);
439 444 #else
440 445 Assembler::ldd(a, d, offset);
441 446 #endif
442 447 }
443 448
444 449 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
445 450 #ifdef _LP64
446 451 Assembler::stx(d, s1, s2);
447 452 #else
448 453 Assembler::std(d, s1, s2);
449 454 #endif
450 455 }
451 456
452 457 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
453 458 #ifdef _LP64
454 459 Assembler::stx(d, s1, simm13a);
455 460 #else
456 461 Assembler::std(d, s1, simm13a);
457 462 #endif
458 463 }
459 464
460 465 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
461 466 #ifdef _LP64
462 467 Assembler::stx(d, s1, s2);
463 468 #else
464 469 Assembler::std(d, s1, s2);
465 470 #endif
466 471 }
467 472
468 473 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
469 474 #ifdef _LP64
470 475 Assembler::stx(d, a, offset);
471 476 #else
472 477 Assembler::std(d, a, offset);
473 478 #endif
474 479 }
475 480
476 481 // Functions for isolating 64 bit shifts for LP64
477 482
478 483 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
479 484 #ifdef _LP64
480 485 Assembler::sllx(s1, s2, d);
481 486 #else
482 487 Assembler::sll( s1, s2, d);
483 488 #endif
484 489 }
485 490
486 491 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
487 492 #ifdef _LP64
488 493 Assembler::sllx(s1, imm6a, d);
489 494 #else
490 495 Assembler::sll( s1, imm6a, d);
491 496 #endif
492 497 }
493 498
494 499 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
495 500 #ifdef _LP64
496 501 Assembler::srlx(s1, s2, d);
497 502 #else
498 503 Assembler::srl( s1, s2, d);
499 504 #endif
500 505 }
501 506
502 507 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
503 508 #ifdef _LP64
504 509 Assembler::srlx(s1, imm6a, d);
505 510 #else
506 511 Assembler::srl( s1, imm6a, d);
507 512 #endif
508 513 }
509 514
510 515 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
511 516 if (s2.is_register()) sll_ptr(s1, s2.as_register(), d);
512 517 else sll_ptr(s1, s2.as_constant(), d);
513 518 }
514 519
515 520 // Use the right branch for the platform
516 521
517 522 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
518 523 if (VM_Version::v9_instructions_work())
519 524 Assembler::bp(c, a, icc, p, d, rt);
520 525 else
521 526 Assembler::br(c, a, d, rt);
522 527 }
523 528
524 529 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
525 530 br(c, a, p, target(L));
526 531 }
527 532
528 533
529 534 // Branch that tests either xcc or icc depending on the
530 535 // architecture compiled (LP64 or not)
531 536 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
532 537 #ifdef _LP64
533 538 Assembler::bp(c, a, xcc, p, d, rt);
534 539 #else
535 540 MacroAssembler::br(c, a, p, d, rt);
536 541 #endif
537 542 }
538 543
539 544 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
540 545 brx(c, a, p, target(L));
541 546 }
542 547
543 548 inline void MacroAssembler::ba( bool a, Label& L ) {
544 549 br(always, a, pt, L);
545 550 }
546 551
547 552 // Warning: V9 only functions
548 553 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
549 554 Assembler::bp(c, a, cc, p, d, rt);
550 555 }
551 556
552 557 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
553 558 Assembler::bp(c, a, cc, p, L);
554 559 }
555 560
556 561 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
557 562 if (VM_Version::v9_instructions_work())
558 563 fbp(c, a, fcc0, p, d, rt);
559 564 else
560 565 Assembler::fb(c, a, d, rt);
561 566 }
562 567
563 568 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
564 569 fb(c, a, p, target(L));
565 570 }
566 571
567 572 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
568 573 Assembler::fbp(c, a, cc, p, d, rt);
569 574 }
570 575
571 576 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
572 577 Assembler::fbp(c, a, cc, p, L);
573 578 }
574 579
575 580 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
576 581 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
577 582
578 583 // Call with a check to see if we need to deal with the added
579 584 // expense of relocation and if we overflow the displacement
580 585 // of the quick call instruction./
581 586 // Check to see if we have to deal with relocations
582 587 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
583 588 #ifdef _LP64
584 589 intptr_t disp;
585 590 // NULL is ok because it will be relocated later.
586 591 // Must change NULL to a reachable address in order to
587 592 // pass asserts here and in wdisp.
588 593 if ( d == NULL )
589 594 d = pc();
590 595
591 596 // Is this address within range of the call instruction?
592 597 // If not, use the expensive instruction sequence
593 598 disp = (intptr_t)d - (intptr_t)pc();
594 599 if ( disp != (intptr_t)(int32_t)disp ) {
595 600 relocate(rt);
596 601 AddressLiteral dest(d);
597 602 jumpl_to(dest, O7, O7);
598 603 }
599 604 else {
600 605 Assembler::call( d, rt );
601 606 }
602 607 #else
603 608 Assembler::call( d, rt );
604 609 #endif
605 610 }
606 611
607 612 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
608 613 MacroAssembler::call( target(L), rt);
609 614 }
610 615
611 616
612 617
613 618 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
614 619 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
615 620
616 621 // prefetch instruction
617 622 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
618 623 if (VM_Version::v9_instructions_work())
619 624 Assembler::bp( never, true, xcc, pt, d, rt );
620 625 }
621 626 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
622 627
623 628
624 629 // clobbers o7 on V8!!
625 630 // returns delta from gotten pc to addr after
626 631 inline int MacroAssembler::get_pc( Register d ) {
627 632 int x = offset();
628 633 if (VM_Version::v9_instructions_work())
629 634 rdpc(d);
630 635 else {
631 636 Label lbl;
632 637 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
633 638 if (d == O7) delayed()->nop();
634 639 else delayed()->mov(O7, d);
635 640 bind(lbl);
636 641 }
637 642 return offset() - x;
638 643 }
639 644
640 645
641 646 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
642 647
643 648
644 649 // Loads the current PC of the following instruction as an immediate value in
645 650 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
646 651 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
647 652 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
648 653 #ifdef _LP64
649 654 Unimplemented();
650 655 #else
651 656 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
652 657 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
653 658 #endif
654 659 return thepc;
655 660 }
656 661
657 662
658 663 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
659 664 assert_not_delayed();
660 665 sethi(addrlit, d);
661 666 ld(d, addrlit.low10() + offset, d);
662 667 }
663 668
664 669
665 670 inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) {
666 671 assert_not_delayed();
667 672 sethi(addrlit, d);
668 673 ld_ptr(d, addrlit.low10() + offset, d);
669 674 }
670 675
671 676
672 677 inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
673 678 assert_not_delayed();
674 679 sethi(addrlit, temp);
675 680 st(s, temp, addrlit.low10() + offset);
676 681 }
677 682
678 683
679 684 inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
680 685 assert_not_delayed();
681 686 sethi(addrlit, temp);
682 687 st_ptr(s, temp, addrlit.low10() + offset);
683 688 }
684 689
685 690
686 691 // This code sequence is relocatable to any address, even on LP64.
687 692 inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) {
688 693 assert_not_delayed();
689 694 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
690 695 // variable length instruction streams.
691 696 patchable_sethi(addrlit, temp);
692 697 jmpl(temp, addrlit.low10() + offset, d);
693 698 }
694 699
695 700
696 701 inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) {
697 702 jumpl_to(addrlit, temp, G0, offset);
698 703 }
699 704
700 705
701 706 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,
702 707 int ld_offset, int jmp_offset) {
703 708 assert_not_delayed();
704 709 //sethi(al); // sethi is caller responsibility for this one
705 710 ld_ptr(a, temp, ld_offset);
706 711 jmp(temp, jmp_offset);
707 712 }
708 713
709 714
710 715 inline void MacroAssembler::set_oop(jobject obj, Register d) {
711 716 set_oop(allocate_oop_address(obj), d);
712 717 }
713 718
714 719
715 720 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
716 721 set_oop(constant_oop_address(obj), d);
717 722 }
718 723
719 724
720 725 inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) {
721 726 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
722 727 set(obj_addr, d);
723 728 }
724 729
725 730
726 731 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
727 732 if (a.is_register())
728 733 mov(a.as_register(), d);
729 734 else
730 735 ld (a.as_address(), d);
731 736 }
732 737
733 738 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
734 739 if (a.is_register())
735 740 mov(s, a.as_register());
736 741 else
737 742 st_ptr (s, a.as_address()); // ABI says everything is right justified.
738 743 }
739 744
740 745 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
741 746 if (a.is_register())
742 747 mov(s, a.as_register());
743 748 else
744 749 st_ptr (s, a.as_address());
745 750 }
746 751
747 752
748 753 #ifdef _LP64
749 754 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
750 755 if (a.is_float_register())
751 756 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
752 757 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
753 758 else
754 759 // Floats are stored in the high half of the stack entry
755 760 // The low half is undefined per the ABI.
756 761 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
757 762 }
758 763
759 764 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
760 765 if (a.is_float_register())
761 766 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
762 767 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
763 768 else
764 769 stf(FloatRegisterImpl::D, s, a.as_address());
765 770 }
766 771
767 772 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
768 773 if (a.is_register())
769 774 mov(s, a.as_register());
770 775 else
771 776 stx(s, a.as_address());
772 777 }
773 778 #endif
774 779
775 780 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
776 781 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
777 782 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
778 783 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
779 784
780 785 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
781 786 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
782 787 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
783 788 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
784 789
785 790 // returns if membar generates anything, obviously this code should mirror
786 791 // membar below.
787 792 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
788 793 if( !os::is_MP() ) return false; // Not needed on single CPU
789 794 if( VM_Version::v9_instructions_work() ) {
790 795 const Membar_mask_bits effective_mask =
791 796 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
792 797 return (effective_mask != 0);
793 798 } else {
794 799 return true;
795 800 }
796 801 }
797 802
798 803 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
799 804 // Uniprocessors do not need memory barriers
800 805 if (!os::is_MP()) return;
801 806 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
802 807 // 8.4.4.3, a.31 and a.50.
803 808 if( VM_Version::v9_instructions_work() ) {
804 809 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
805 810 // of the mmask subfield of const7a that does anything that isn't done
806 811 // implicitly is StoreLoad.
807 812 const Membar_mask_bits effective_mask =
808 813 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
809 814 if ( effective_mask != 0 ) {
810 815 Assembler::membar( effective_mask );
811 816 }
812 817 } else {
813 818 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
814 819 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
815 820 // which guarantees that all stores behave as if an stbar were issued just after
816 821 // each one of them. On these machines, stbar ought to be a nop. There doesn't
817 822 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
818 823 // it can't be specified by stbar, nor have I come up with a way to simulate it.
819 824 //
820 825 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
821 826 // space. Put one here to be on the safe side.
822 827 Assembler::ldstub(SP, 0, G0);
823 828 }
824 829 }
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