1 //
2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 // ****************************************************************************
528
529 // REQUIRED FUNCTIONALITY
530
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
535
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 int offset = NativeCall::instruction_size; // call; delay slot
538 if (_method_handle_invoke)
539 offset += 4; // restore SP
540 return offset;
541 }
542
543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 int vtable_index = this->_vtable_index;
545 if (vtable_index < 0) {
546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 return (NativeMovConstReg::instruction_size +
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 } else {
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 int klass_load_size;
555 if (UseCompressedOops) {
556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 if (Universe::narrow_oop_base() == NULL)
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 else
560 klass_load_size = 3*BytesPerInstWord;
561 } else {
562 klass_load_size = 1*BytesPerInstWord;
563 }
564 if( Assembler::is_simm13(v_off) ) {
565 return klass_load_size +
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 NativeCall::instruction_size); // call; delay slot
568 } else {
569 return klass_load_size +
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 }
573 }
574 }
575
576 int MachCallRuntimeNode::ret_addr_offset() {
577 #ifdef _LP64
578 return NativeFarCall::instruction_size; // farcall; delay slot
579 #else
580 return NativeCall::instruction_size; // call; delay slot
581 #endif
582 }
583
584 // Indicate if the safepoint node needs the polling page as an input.
585 // Since Sparc does not have absolute addressing, it does.
586 bool SafePointNode::needs_polling_address_input() {
587 return true;
588 }
589
590 // emit an interrupt that is caught by the debugger (for debugging compiler)
591 void emit_break(CodeBuffer &cbuf) {
592 MacroAssembler _masm(&cbuf);
593 __ breakpoint_trap();
594 }
595
596 #ifndef PRODUCT
597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
598 st->print("TA");
599 }
600 #endif
601
602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 emit_break(cbuf);
604 }
605
606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
607 return MachNode::size(ra_);
608 }
609
610 // Traceable jump
611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
612 MacroAssembler _masm(&cbuf);
613 Register rdest = reg_to_register_object(jump_target);
614 __ JMP(rdest, 0);
615 __ delayed()->nop();
616 }
617
618 // Traceable jump and set exception pc
619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
620 MacroAssembler _masm(&cbuf);
621 Register rdest = reg_to_register_object(jump_target);
622 __ JMP(rdest, 0);
623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
624 }
625
626 void emit_nop(CodeBuffer &cbuf) {
627 MacroAssembler _masm(&cbuf);
628 __ nop();
629 }
630
631 void emit_illtrap(CodeBuffer &cbuf) {
632 MacroAssembler _masm(&cbuf);
633 __ illtrap(0);
634 }
635
636
637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
638 assert(n->rule() != loadUB_rule, "");
639
640 intptr_t offset = 0;
641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
642 const Node* addr = n->get_base_and_disp(offset, adr_type);
643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
644 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
645 assert(addr->bottom_type()->isa_oopptr() == atype, "");
646 atype = atype->add_offset(offset);
647 assert(disp32 == offset, "wrong disp32");
648 return atype->_offset;
649 }
650
651
652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
653 assert(n->rule() != loadUB_rule, "");
654
655 intptr_t offset = 0;
656 Node* addr = n->in(2);
657 assert(addr->bottom_type()->isa_oopptr() == atype, "");
658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
659 Node* a = addr->in(2/*AddPNode::Address*/);
660 Node* o = addr->in(3/*AddPNode::Offset*/);
661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
662 atype = a->bottom_type()->is_ptr()->add_offset(offset);
663 assert(atype->isa_oop_ptr(), "still an oop");
664 }
665 offset = atype->is_ptr()->_offset;
666 if (offset != Type::OffsetBot) offset += disp32;
667 return offset;
668 }
669
670 // Standard Sparc opcode form2 field breakdown
671 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
672 f0 &= (1<<19)-1; // Mask displacement to 19 bits
673 int op = (f30 << 30) |
674 (f29 << 29) |
675 (f25 << 25) |
676 (f22 << 22) |
677 (f20 << 20) |
678 (f19 << 19) |
679 (f0 << 0);
680 cbuf.insts()->emit_int32(op);
681 }
682
683 // Standard Sparc opcode form2 field breakdown
684 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
685 f0 >>= 10; // Drop 10 bits
686 f0 &= (1<<22)-1; // Mask displacement to 22 bits
687 int op = (f30 << 30) |
688 (f25 << 25) |
689 (f22 << 22) |
690 (f0 << 0);
691 cbuf.insts()->emit_int32(op);
692 }
693
694 // Standard Sparc opcode form3 field breakdown
695 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
696 int op = (f30 << 30) |
697 (f25 << 25) |
698 (f19 << 19) |
699 (f14 << 14) |
700 (f5 << 5) |
701 (f0 << 0);
702 cbuf.insts()->emit_int32(op);
703 }
704
705 // Standard Sparc opcode form3 field breakdown
706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
707 simm13 &= (1<<13)-1; // Mask to 13 bits
708 int op = (f30 << 30) |
709 (f25 << 25) |
710 (f19 << 19) |
711 (f14 << 14) |
712 (1 << 13) | // bit to indicate immediate-mode
713 (simm13<<0);
714 cbuf.insts()->emit_int32(op);
715 }
716
717 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
718 simm10 &= (1<<10)-1; // Mask to 10 bits
719 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
720 }
721
722 #ifdef ASSERT
723 // Helper function for VerifyOops in emit_form3_mem_reg
724 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
725 warning("VerifyOops encountered unexpected instruction:");
726 n->dump(2);
727 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
728 }
729 #endif
730
731
732 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
733 int src1_enc, int disp32, int src2_enc, int dst_enc) {
734
735 #ifdef ASSERT
736 // The following code implements the +VerifyOops feature.
737 // It verifies oop values which are loaded into or stored out of
738 // the current method activation. +VerifyOops complements techniques
739 // like ScavengeALot, because it eagerly inspects oops in transit,
740 // as they enter or leave the stack, as opposed to ScavengeALot,
741 // which inspects oops "at rest", in the stack or heap, at safepoints.
742 // For this reason, +VerifyOops can sometimes detect bugs very close
743 // to their point of creation. It can also serve as a cross-check
744 // on the validity of oop maps, when used toegether with ScavengeALot.
745
746 // It would be good to verify oops at other points, especially
747 // when an oop is used as a base pointer for a load or store.
748 // This is presently difficult, because it is hard to know when
749 // a base address is biased or not. (If we had such information,
750 // it would be easy and useful to make a two-argument version of
751 // verify_oop which unbiases the base, and performs verification.)
752
753 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
754 bool is_verified_oop_base = false;
755 bool is_verified_oop_load = false;
756 bool is_verified_oop_store = false;
757 int tmp_enc = -1;
758 if (VerifyOops && src1_enc != R_SP_enc) {
759 // classify the op, mainly for an assert check
760 int st_op = 0, ld_op = 0;
761 switch (primary) {
762 case Assembler::stb_op3: st_op = Op_StoreB; break;
763 case Assembler::sth_op3: st_op = Op_StoreC; break;
764 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
765 case Assembler::stw_op3: st_op = Op_StoreI; break;
766 case Assembler::std_op3: st_op = Op_StoreL; break;
767 case Assembler::stf_op3: st_op = Op_StoreF; break;
768 case Assembler::stdf_op3: st_op = Op_StoreD; break;
769
770 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
771 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
772 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
773 case Assembler::ldx_op3: // may become LoadP or stay LoadI
774 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
775 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
776 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
777 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
778 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
779 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
780 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
781
782 default: ShouldNotReachHere();
783 }
784 if (tertiary == REGP_OP) {
785 if (st_op == Op_StoreI) st_op = Op_StoreP;
786 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
787 else ShouldNotReachHere();
788 if (st_op) {
789 // a store
790 // inputs are (0:control, 1:memory, 2:address, 3:value)
791 Node* n2 = n->in(3);
792 if (n2 != NULL) {
793 const Type* t = n2->bottom_type();
794 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
795 }
796 } else {
797 // a load
798 const Type* t = n->bottom_type();
799 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
800 }
801 }
802
803 if (ld_op) {
804 // a Load
805 // inputs are (0:control, 1:memory, 2:address)
806 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
807 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
808 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
809 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
810 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
811 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
813 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
814 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
815 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
817 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
818 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
819 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
820 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
821 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
822 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
823 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
824 !(n->rule() == loadUB_rule)) {
825 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
826 }
827 } else if (st_op) {
828 // a Store
829 // inputs are (0:control, 1:memory, 2:address, 3:value)
830 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
831 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
832 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
833 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
834 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
835 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
836 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
837 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
838 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
839 verify_oops_warning(n, n->ideal_Opcode(), st_op);
840 }
841 }
842
843 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
844 Node* addr = n->in(2);
845 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
846 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
847 if (atype != NULL) {
848 intptr_t offset = get_offset_from_base(n, atype, disp32);
849 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
850 if (offset != offset_2) {
851 get_offset_from_base(n, atype, disp32);
852 get_offset_from_base_2(n, atype, disp32);
853 }
854 assert(offset == offset_2, "different offsets");
855 if (offset == disp32) {
856 // we now know that src1 is a true oop pointer
857 is_verified_oop_base = true;
858 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
859 if( primary == Assembler::ldd_op3 ) {
860 is_verified_oop_base = false; // Cannot 'ldd' into O7
861 } else {
862 tmp_enc = dst_enc;
863 dst_enc = R_O7_enc; // Load into O7; preserve source oop
864 assert(src1_enc != dst_enc, "");
865 }
866 }
867 }
868 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
869 || offset == oopDesc::mark_offset_in_bytes())) {
870 // loading the mark should not be allowed either, but
871 // we don't check this since it conflicts with InlineObjectHash
872 // usage of LoadINode to get the mark. We could keep the
873 // check if we create a new LoadMarkNode
874 // but do not verify the object before its header is initialized
875 ShouldNotReachHere();
876 }
877 }
878 }
879 }
880 }
881 #endif
882
883 uint instr;
884 instr = (Assembler::ldst_op << 30)
885 | (dst_enc << 25)
886 | (primary << 19)
887 | (src1_enc << 14);
888
889 uint index = src2_enc;
890 int disp = disp32;
891
892 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
893 disp += STACK_BIAS;
894
895 // We should have a compiler bailout here rather than a guarantee.
896 // Better yet would be some mechanism to handle variable-size matches correctly.
897 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
898
899 if( disp == 0 ) {
900 // use reg-reg form
901 // bit 13 is already zero
902 instr |= index;
903 } else {
904 // use reg-imm form
905 instr |= 0x00002000; // set bit 13 to one
906 instr |= disp & 0x1FFF;
907 }
908
909 cbuf.insts()->emit_int32(instr);
910
911 #ifdef ASSERT
912 {
913 MacroAssembler _masm(&cbuf);
914 if (is_verified_oop_base) {
915 __ verify_oop(reg_to_register_object(src1_enc));
916 }
917 if (is_verified_oop_store) {
918 __ verify_oop(reg_to_register_object(dst_enc));
919 }
920 if (tmp_enc != -1) {
921 __ mov(O7, reg_to_register_object(tmp_enc));
922 }
923 if (is_verified_oop_load) {
924 __ verify_oop(reg_to_register_object(dst_enc));
925 }
926 }
927 #endif
928 }
929
930 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
931 // The method which records debug information at every safepoint
932 // expects the call to be the first instruction in the snippet as
933 // it creates a PcDesc structure which tracks the offset of a call
934 // from the start of the codeBlob. This offset is computed as
935 // code_end() - code_begin() of the code which has been emitted
936 // so far.
937 // In this particular case we have skirted around the problem by
938 // putting the "mov" instruction in the delay slot but the problem
939 // may bite us again at some other point and a cleaner/generic
940 // solution using relocations would be needed.
941 MacroAssembler _masm(&cbuf);
942 __ set_inst_mark();
943
944 // We flush the current window just so that there is a valid stack copy
945 // the fact that the current window becomes active again instantly is
946 // not a problem there is nothing live in it.
947
948 #ifdef ASSERT
949 int startpos = __ offset();
950 #endif /* ASSERT */
951
952 #ifdef _LP64
953 // Calls to the runtime or native may not be reachable from compiled code,
954 // so we generate the far call sequence on 64 bit sparc.
955 // This code sequence is relocatable to any address, even on LP64.
956 if ( force_far_call ) {
957 __ relocate(rtype);
958 AddressLiteral dest(entry_point);
959 __ jumpl_to(dest, O7, O7);
960 }
961 else
962 #endif
963 {
964 __ call((address)entry_point, rtype);
965 }
966
967 if (preserve_g2) __ delayed()->mov(G2, L7);
968 else __ delayed()->nop();
969
970 if (preserve_g2) __ mov(L7, G2);
971
972 #ifdef ASSERT
973 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
974 #ifdef _LP64
975 // Trash argument dump slots.
976 __ set(0xb0b8ac0db0b8ac0d, G1);
977 __ mov(G1, G5);
978 __ stx(G1, SP, STACK_BIAS + 0x80);
979 __ stx(G1, SP, STACK_BIAS + 0x88);
980 __ stx(G1, SP, STACK_BIAS + 0x90);
981 __ stx(G1, SP, STACK_BIAS + 0x98);
982 __ stx(G1, SP, STACK_BIAS + 0xA0);
983 __ stx(G1, SP, STACK_BIAS + 0xA8);
984 #else // _LP64
985 // this is also a native call, so smash the first 7 stack locations,
986 // and the various registers
987
988 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
989 // while [SP+0x44..0x58] are the argument dump slots.
990 __ set((intptr_t)0xbaadf00d, G1);
991 __ mov(G1, G5);
992 __ sllx(G1, 32, G1);
993 __ or3(G1, G5, G1);
994 __ mov(G1, G5);
995 __ stx(G1, SP, 0x40);
996 __ stx(G1, SP, 0x48);
997 __ stx(G1, SP, 0x50);
998 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
999 #endif // _LP64
1000 }
1001 #endif /*ASSERT*/
1002 }
1003
1004 //=============================================================================
1005 // REQUIRED FUNCTIONALITY for encoding
1006 void emit_lo(CodeBuffer &cbuf, int val) { }
1007 void emit_hi(CodeBuffer &cbuf, int val) { }
1008
1009
1010 //=============================================================================
1011
1012 #ifndef PRODUCT
1013 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1014 Compile* C = ra_->C;
1015
1016 for (int i = 0; i < OptoPrologueNops; i++) {
1017 st->print_cr("NOP"); st->print("\t");
1018 }
1019
1020 if( VerifyThread ) {
1021 st->print_cr("Verify_Thread"); st->print("\t");
1022 }
1023
1024 size_t framesize = C->frame_slots() << LogBytesPerInt;
1025
1026 // Calls to C2R adapters often do not accept exceptional returns.
1027 // We require that their callers must bang for them. But be careful, because
1028 // some VM calls (such as call site linkage) can use several kilobytes of
1029 // stack. But the stack safety zone should account for that.
1030 // See bugs 4446381, 4468289, 4497237.
1031 if (C->need_stack_bang(framesize)) {
1032 st->print_cr("! stack bang"); st->print("\t");
1033 }
1034
1035 if (Assembler::is_simm13(-framesize)) {
1036 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1037 } else {
1038 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1039 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1040 st->print ("SAVE R_SP,R_G3,R_SP");
1041 }
1042
1043 }
1044 #endif
1045
1046 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1047 Compile* C = ra_->C;
1048 MacroAssembler _masm(&cbuf);
1049
1050 for (int i = 0; i < OptoPrologueNops; i++) {
1051 __ nop();
1052 }
1053
1054 __ verify_thread();
1055
1056 size_t framesize = C->frame_slots() << LogBytesPerInt;
1057 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1058 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1059
1060 // Calls to C2R adapters often do not accept exceptional returns.
1061 // We require that their callers must bang for them. But be careful, because
1062 // some VM calls (such as call site linkage) can use several kilobytes of
1063 // stack. But the stack safety zone should account for that.
1064 // See bugs 4446381, 4468289, 4497237.
1065 if (C->need_stack_bang(framesize)) {
1066 __ generate_stack_overflow_check(framesize);
1067 }
1068
1069 if (Assembler::is_simm13(-framesize)) {
1070 __ save(SP, -framesize, SP);
1071 } else {
1072 __ sethi(-framesize & ~0x3ff, G3);
1073 __ add(G3, -framesize & 0x3ff, G3);
1074 __ save(SP, G3, SP);
1075 }
1076 C->set_frame_complete( __ offset() );
1077 }
1078
1079 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1080 return MachNode::size(ra_);
1081 }
1082
1083 int MachPrologNode::reloc() const {
1084 return 10; // a large enough number
1085 }
1086
1087 //=============================================================================
1088 #ifndef PRODUCT
1089 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1090 Compile* C = ra_->C;
1091
1092 if( do_polling() && ra_->C->is_method_compilation() ) {
1093 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1094 #ifdef _LP64
1095 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1096 #else
1097 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1098 #endif
1099 }
1100
1101 if( do_polling() )
1102 st->print("RET\n\t");
1103
1104 st->print("RESTORE");
1105 }
1106 #endif
1107
1108 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1109 MacroAssembler _masm(&cbuf);
1110 Compile* C = ra_->C;
1111
1112 __ verify_thread();
1113
1114 // If this does safepoint polling, then do it here
1115 if( do_polling() && ra_->C->is_method_compilation() ) {
1116 AddressLiteral polling_page(os::get_polling_page());
1117 __ sethi(polling_page, L0);
1118 __ relocate(relocInfo::poll_return_type);
1119 __ ld_ptr( L0, 0, G0 );
1120 }
1121
1122 // If this is a return, then stuff the restore in the delay slot
1123 if( do_polling() ) {
1124 __ ret();
1125 __ delayed()->restore();
1126 } else {
1127 __ restore();
1128 }
1129 }
1130
1131 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1132 return MachNode::size(ra_);
1133 }
1134
1135 int MachEpilogNode::reloc() const {
1136 return 16; // a large enough number
1137 }
1138
1139 const Pipeline * MachEpilogNode::pipeline() const {
1140 return MachNode::pipeline_class();
1141 }
1142
1143 int MachEpilogNode::safepoint_offset() const {
1144 assert( do_polling(), "no return for this epilog node");
1145 return MacroAssembler::size_of_sethi(os::get_polling_page());
1146 }
1147
1148 //=============================================================================
1149
1150 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1151 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1152 static enum RC rc_class( OptoReg::Name reg ) {
1153 if( !OptoReg::is_valid(reg) ) return rc_bad;
1154 if (OptoReg::is_stack(reg)) return rc_stack;
1155 VMReg r = OptoReg::as_VMReg(reg);
1156 if (r->is_Register()) return rc_int;
1157 assert(r->is_FloatRegister(), "must be");
1158 return rc_float;
1159 }
1160
1161 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1162 if( cbuf ) {
1163 // Better yet would be some mechanism to handle variable-size matches correctly
1164 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1165 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1166 } else {
1167 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1168 }
1169 }
1170 #ifndef PRODUCT
1171 else if( !do_size ) {
1172 if( size != 0 ) st->print("\n\t");
1173 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1174 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1175 }
1176 #endif
1177 return size+4;
1178 }
1179
1180 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1181 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1182 #ifndef PRODUCT
1183 else if( !do_size ) {
1184 if( size != 0 ) st->print("\n\t");
1185 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1186 }
1187 #endif
1188 return size+4;
1189 }
1190
1191 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1192 PhaseRegAlloc *ra_,
1193 bool do_size,
1194 outputStream* st ) const {
1195 // Get registers to move
1196 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1197 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1198 OptoReg::Name dst_second = ra_->get_reg_second(this );
1199 OptoReg::Name dst_first = ra_->get_reg_first(this );
1200
1201 enum RC src_second_rc = rc_class(src_second);
1202 enum RC src_first_rc = rc_class(src_first);
1203 enum RC dst_second_rc = rc_class(dst_second);
1204 enum RC dst_first_rc = rc_class(dst_first);
1205
1206 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1207
1208 // Generate spill code!
1209 int size = 0;
1210
1211 if( src_first == dst_first && src_second == dst_second )
1212 return size; // Self copy, no move
1213
1214 // --------------------------------------
1215 // Check for mem-mem move. Load into unused float registers and fall into
1216 // the float-store case.
1217 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1218 int offset = ra_->reg2offset(src_first);
1219 // Further check for aligned-adjacent pair, so we can use a double load
1220 if( (src_first&1)==0 && src_first+1 == src_second ) {
1221 src_second = OptoReg::Name(R_F31_num);
1222 src_second_rc = rc_float;
1223 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1224 } else {
1225 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1226 }
1227 src_first = OptoReg::Name(R_F30_num);
1228 src_first_rc = rc_float;
1229 }
1230
1231 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1232 int offset = ra_->reg2offset(src_second);
1233 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1234 src_second = OptoReg::Name(R_F31_num);
1235 src_second_rc = rc_float;
1236 }
1237
1238 // --------------------------------------
1239 // Check for float->int copy; requires a trip through memory
1240 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1241 int offset = frame::register_save_words*wordSize;
1242 if( cbuf ) {
1243 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1244 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1245 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1246 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1247 }
1248 #ifndef PRODUCT
1249 else if( !do_size ) {
1250 if( size != 0 ) st->print("\n\t");
1251 st->print( "SUB R_SP,16,R_SP\n");
1252 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1253 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1254 st->print("\tADD R_SP,16,R_SP\n");
1255 }
1256 #endif
1257 size += 16;
1258 }
1259
1260 // --------------------------------------
1261 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1262 // In such cases, I have to do the big-endian swap. For aligned targets, the
1263 // hardware does the flop for me. Doubles are always aligned, so no problem
1264 // there. Misaligned sources only come from native-long-returns (handled
1265 // special below).
1266 #ifndef _LP64
1267 if( src_first_rc == rc_int && // source is already big-endian
1268 src_second_rc != rc_bad && // 64-bit move
1269 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1270 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1271 // Do the big-endian flop.
1272 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1273 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1274 }
1275 #endif
1276
1277 // --------------------------------------
1278 // Check for integer reg-reg copy
1279 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1280 #ifndef _LP64
1281 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1282 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1283 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1284 // operand contains the least significant word of the 64-bit value and vice versa.
1285 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1286 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1287 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1288 if( cbuf ) {
1289 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1290 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1291 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1292 #ifndef PRODUCT
1293 } else if( !do_size ) {
1294 if( size != 0 ) st->print("\n\t");
1295 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1296 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1297 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1298 #endif
1299 }
1300 return size+12;
1301 }
1302 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1303 // returning a long value in I0/I1
1304 // a SpillCopy must be able to target a return instruction's reg_class
1305 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1306 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1307 // operand contains the least significant word of the 64-bit value and vice versa.
1308 OptoReg::Name tdest = dst_first;
1309
1310 if (src_first == dst_first) {
1311 tdest = OptoReg::Name(R_O7_num);
1312 size += 4;
1313 }
1314
1315 if( cbuf ) {
1316 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1317 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1318 // ShrL_reg_imm6
1319 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1320 // ShrR_reg_imm6 src, 0, dst
1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1322 if (tdest != dst_first) {
1323 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1324 }
1325 }
1326 #ifndef PRODUCT
1327 else if( !do_size ) {
1328 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1329 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1330 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1331 if (tdest != dst_first) {
1332 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1333 }
1334 }
1335 #endif // PRODUCT
1336 return size+8;
1337 }
1338 #endif // !_LP64
1339 // Else normal reg-reg copy
1340 assert( src_second != dst_first, "smashed second before evacuating it" );
1341 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1342 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1343 // This moves an aligned adjacent pair.
1344 // See if we are done.
1345 if( src_first+1 == src_second && dst_first+1 == dst_second )
1346 return size;
1347 }
1348
1349 // Check for integer store
1350 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1351 int offset = ra_->reg2offset(dst_first);
1352 // Further check for aligned-adjacent pair, so we can use a double store
1353 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1354 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1355 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1356 }
1357
1358 // Check for integer load
1359 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1360 int offset = ra_->reg2offset(src_first);
1361 // Further check for aligned-adjacent pair, so we can use a double load
1362 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1363 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1364 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1365 }
1366
1367 // Check for float reg-reg copy
1368 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1369 // Further check for aligned-adjacent pair, so we can use a double move
1370 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1371 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1373 }
1374
1375 // Check for float store
1376 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1377 int offset = ra_->reg2offset(dst_first);
1378 // Further check for aligned-adjacent pair, so we can use a double store
1379 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1380 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1381 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1382 }
1383
1384 // Check for float load
1385 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1386 int offset = ra_->reg2offset(src_first);
1387 // Further check for aligned-adjacent pair, so we can use a double load
1388 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1389 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1390 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1391 }
1392
1393 // --------------------------------------------------------------------
1394 // Check for hi bits still needing moving. Only happens for misaligned
1395 // arguments to native calls.
1396 if( src_second == dst_second )
1397 return size; // Self copy; no move
1398 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1399
1400 #ifndef _LP64
1401 // In the LP64 build, all registers can be moved as aligned/adjacent
1402 // pairs, so there's never any need to move the high bits separately.
1403 // The 32-bit builds have to deal with the 32-bit ABI which can force
1404 // all sorts of silly alignment problems.
1405
1406 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1407 // 32-bits of a 64-bit register, but are needed in low bits of another
1408 // register (else it's a hi-bits-to-hi-bits copy which should have
1409 // happened already as part of a 64-bit move)
1410 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1411 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1412 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1413 // Shift src_second down to dst_second's low bits.
1414 if( cbuf ) {
1415 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1416 #ifndef PRODUCT
1417 } else if( !do_size ) {
1418 if( size != 0 ) st->print("\n\t");
1419 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1420 #endif
1421 }
1422 return size+4;
1423 }
1424
1425 // Check for high word integer store. Must down-shift the hi bits
1426 // into a temp register, then fall into the case of storing int bits.
1427 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1428 // Shift src_second down to dst_second's low bits.
1429 if( cbuf ) {
1430 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1431 #ifndef PRODUCT
1432 } else if( !do_size ) {
1433 if( size != 0 ) st->print("\n\t");
1434 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1435 #endif
1436 }
1437 size+=4;
1438 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1439 }
1440
1441 // Check for high word integer load
1442 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1443 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1444
1445 // Check for high word integer store
1446 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1447 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1448
1449 // Check for high word float store
1450 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1451 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1452
1453 #endif // !_LP64
1454
1455 Unimplemented();
1456 }
1457
1458 #ifndef PRODUCT
1459 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1460 implementation( NULL, ra_, false, st );
1461 }
1462 #endif
1463
1464 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1465 implementation( &cbuf, ra_, false, NULL );
1466 }
1467
1468 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1469 return implementation( NULL, ra_, true, NULL );
1470 }
1471
1472 //=============================================================================
1473 #ifndef PRODUCT
1474 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1475 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1476 }
1477 #endif
1478
1479 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1480 MacroAssembler _masm(&cbuf);
1481 for(int i = 0; i < _count; i += 1) {
1482 __ nop();
1483 }
1484 }
1485
1486 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1487 return 4 * _count;
1488 }
1489
1490
1491 //=============================================================================
1492 #ifndef PRODUCT
1493 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1494 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1495 int reg = ra_->get_reg_first(this);
1496 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1497 }
1498 #endif
1499
1500 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 MacroAssembler _masm(&cbuf);
1502 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1503 int reg = ra_->get_encode(this);
1504
1505 if (Assembler::is_simm13(offset)) {
1506 __ add(SP, offset, reg_to_register_object(reg));
1507 } else {
1508 __ set(offset, O7);
1509 __ add(SP, O7, reg_to_register_object(reg));
1510 }
1511 }
1512
1513 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1514 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1515 assert(ra_ == ra_->C->regalloc(), "sanity");
1516 return ra_->C->scratch_emit_size(this);
1517 }
1518
1519 //=============================================================================
1520
1521 // emit call stub, compiled java to interpretor
1522 void emit_java_to_interp(CodeBuffer &cbuf ) {
1523
1524 // Stub is fixed up when the corresponding call is converted from calling
1525 // compiled code to calling interpreted code.
1526 // set (empty), G5
1527 // jmp -1
1528
1529 address mark = cbuf.insts_mark(); // get mark within main instrs section
1530
1531 MacroAssembler _masm(&cbuf);
1532
1533 address base =
1534 __ start_a_stub(Compile::MAX_stubs_size);
1535 if (base == NULL) return; // CodeBuffer::expand failed
1536
1537 // static stub relocation stores the instruction address of the call
1538 __ relocate(static_stub_Relocation::spec(mark));
1539
1540 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1541
1542 __ set_inst_mark();
1543 AddressLiteral addrlit(-1);
1544 __ JUMP(addrlit, G3, 0);
1545
1546 __ delayed()->nop();
1547
1548 // Update current stubs pointer and restore code_end.
1549 __ end_a_stub();
1550 }
1551
1552 // size of call stub, compiled java to interpretor
1553 uint size_java_to_interp() {
1554 // This doesn't need to be accurate but it must be larger or equal to
1555 // the real size of the stub.
1556 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1557 NativeJump::instruction_size + // sethi; jmp; nop
1558 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1559 }
1560 // relocation entries for call stub, compiled java to interpretor
1561 uint reloc_java_to_interp() {
1562 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1563 }
1564
1565
1566 //=============================================================================
1567 #ifndef PRODUCT
1568 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1569 st->print_cr("\nUEP:");
1570 #ifdef _LP64
1571 if (UseCompressedOops) {
1572 assert(Universe::heap() != NULL, "java heap should be initialized");
1573 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1574 st->print_cr("\tSLL R_G5,3,R_G5");
1575 if (Universe::narrow_oop_base() != NULL)
1576 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1577 } else {
1578 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1579 }
1580 st->print_cr("\tCMP R_G5,R_G3" );
1581 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1582 #else // _LP64
1583 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1584 st->print_cr("\tCMP R_G5,R_G3" );
1585 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1586 #endif // _LP64
1587 }
1588 #endif
1589
1590 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1591 MacroAssembler _masm(&cbuf);
1592 Label L;
1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1594 Register temp_reg = G3;
1595 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1596
1597 // Load klass from receiver
1598 __ load_klass(O0, temp_reg);
1599 // Compare against expected klass
1600 __ cmp(temp_reg, G5_ic_reg);
1601 // Branch to miss code, checks xcc or icc depending
1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1603 }
1604
1605 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1606 return MachNode::size(ra_);
1607 }
1608
1609
1610 //=============================================================================
1611
1612 uint size_exception_handler() {
1613 if (TraceJumps) {
1614 return (400); // just a guess
1615 }
1616 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1617 }
1618
1619 uint size_deopt_handler() {
1620 if (TraceJumps) {
1621 return (400); // just a guess
1622 }
1623 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1624 }
1625
1626 // Emit exception handler code.
1627 int emit_exception_handler(CodeBuffer& cbuf) {
1628 Register temp_reg = G3;
1629 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1630 MacroAssembler _masm(&cbuf);
1631
1632 address base =
1633 __ start_a_stub(size_exception_handler());
1634 if (base == NULL) return 0; // CodeBuffer::expand failed
1635
1636 int offset = __ offset();
1637
1638 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1639 __ delayed()->nop();
1640
1641 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1642
1643 __ end_a_stub();
1644
1645 return offset;
1646 }
1647
1648 int emit_deopt_handler(CodeBuffer& cbuf) {
1649 // Can't use any of the current frame's registers as we may have deopted
1650 // at a poll and everything (including G3) can be live.
1651 Register temp_reg = L0;
1652 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1653 MacroAssembler _masm(&cbuf);
1654
1655 address base =
1656 __ start_a_stub(size_deopt_handler());
1657 if (base == NULL) return 0; // CodeBuffer::expand failed
1658
1659 int offset = __ offset();
1660 __ save_frame(0);
1661 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1662 __ delayed()->restore();
1663
1664 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1665
1666 __ end_a_stub();
1667 return offset;
1668
1669 }
1670
1671 // Given a register encoding, produce a Integer Register object
1672 static Register reg_to_register_object(int register_encoding) {
1673 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1674 return as_Register(register_encoding);
1675 }
1676
1677 // Given a register encoding, produce a single-precision Float Register object
1678 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1679 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1680 return as_SingleFloatRegister(register_encoding);
1681 }
1682
1683 // Given a register encoding, produce a double-precision Float Register object
1684 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1685 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1686 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1687 return as_DoubleFloatRegister(register_encoding);
1688 }
1689
1690 const bool Matcher::match_rule_supported(int opcode) {
1691 if (!has_match_rule(opcode))
1692 return false;
1693
1694 switch (opcode) {
1695 case Op_CountLeadingZerosI:
1696 case Op_CountLeadingZerosL:
1697 case Op_CountTrailingZerosI:
1698 case Op_CountTrailingZerosL:
1699 if (!UsePopCountInstruction)
1700 return false;
1701 break;
1702 }
1703
1704 return true; // Per default match rules are supported.
1705 }
1706
1707 int Matcher::regnum_to_fpu_offset(int regnum) {
1708 return regnum - 32; // The FP registers are in the second chunk
1709 }
1710
1711 #ifdef ASSERT
1712 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1713 #endif
1714
1715 // Vector width in bytes
1716 const uint Matcher::vector_width_in_bytes(void) {
1717 return 8;
1718 }
1719
1720 // Vector ideal reg
1721 const uint Matcher::vector_ideal_reg(void) {
1722 return Op_RegD;
1723 }
1724
1725 // USII supports fxtof through the whole range of number, USIII doesn't
1726 const bool Matcher::convL2FSupported(void) {
1727 return VM_Version::has_fast_fxtof();
1728 }
1729
1730 // Is this branch offset short enough that a short branch can be used?
1731 //
1732 // NOTE: If the platform does not provide any short branch variants, then
1733 // this method should return false for offset 0.
1734 bool Matcher::is_short_branch_offset(int rule, int offset) {
1735 return false;
1736 }
1737
1738 const bool Matcher::isSimpleConstant64(jlong value) {
1739 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1740 // Depends on optimizations in MacroAssembler::setx.
1741 int hi = (int)(value >> 32);
1742 int lo = (int)(value & ~0);
1743 return (hi == 0) || (hi == -1) || (lo == 0);
1744 }
1745
1746 // No scaling for the parameter the ClearArray node.
1747 const bool Matcher::init_array_count_is_in_bytes = true;
1748
1749 // Threshold size for cleararray.
1750 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1751
1752 // Should the Matcher clone shifts on addressing modes, expecting them to
1753 // be subsumed into complex addressing expressions or compute them into
1754 // registers? True for Intel but false for most RISCs
1755 const bool Matcher::clone_shift_expressions = false;
1756
1757 bool Matcher::narrow_oop_use_complex_address() {
1758 NOT_LP64(ShouldNotCallThis());
1759 assert(UseCompressedOops, "only for compressed oops code");
1760 return false;
1761 }
1762
1763 // Is it better to copy float constants, or load them directly from memory?
1764 // Intel can load a float constant from a direct address, requiring no
1765 // extra registers. Most RISCs will have to materialize an address into a
1766 // register first, so they would do better to copy the constant from stack.
1767 const bool Matcher::rematerialize_float_constants = false;
1768
1769 // If CPU can load and store mis-aligned doubles directly then no fixup is
1770 // needed. Else we split the double into 2 integer pieces and move it
1771 // piece-by-piece. Only happens when passing doubles into C code as the
1772 // Java calling convention forces doubles to be aligned.
1773 #ifdef _LP64
1774 const bool Matcher::misaligned_doubles_ok = true;
1775 #else
1776 const bool Matcher::misaligned_doubles_ok = false;
1777 #endif
1778
1779 // No-op on SPARC.
1780 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1781 }
1782
1783 // Advertise here if the CPU requires explicit rounding operations
1784 // to implement the UseStrictFP mode.
1785 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1786
1787 // Are floats conerted to double when stored to stack during deoptimization?
1788 // Sparc does not handle callee-save floats.
1789 bool Matcher::float_in_double() { return false; }
1790
1791 // Do ints take an entire long register or just half?
1792 // Note that we if-def off of _LP64.
1793 // The relevant question is how the int is callee-saved. In _LP64
1794 // the whole long is written but de-opt'ing will have to extract
1795 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1796 #ifdef _LP64
1797 const bool Matcher::int_in_long = true;
1798 #else
1799 const bool Matcher::int_in_long = false;
1800 #endif
1801
1802 // Return whether or not this register is ever used as an argument. This
1803 // function is used on startup to build the trampoline stubs in generateOptoStub.
1804 // Registers not mentioned will be killed by the VM call in the trampoline, and
1805 // arguments in those registers not be available to the callee.
1806 bool Matcher::can_be_java_arg( int reg ) {
1807 // Standard sparc 6 args in registers
1808 if( reg == R_I0_num ||
1809 reg == R_I1_num ||
1810 reg == R_I2_num ||
1811 reg == R_I3_num ||
1812 reg == R_I4_num ||
1813 reg == R_I5_num ) return true;
1814 #ifdef _LP64
1815 // 64-bit builds can pass 64-bit pointers and longs in
1816 // the high I registers
1817 if( reg == R_I0H_num ||
1818 reg == R_I1H_num ||
1819 reg == R_I2H_num ||
1820 reg == R_I3H_num ||
1821 reg == R_I4H_num ||
1822 reg == R_I5H_num ) return true;
1823
1824 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1825 return true;
1826 }
1827
1828 #else
1829 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1830 // Longs cannot be passed in O regs, because O regs become I regs
1831 // after a 'save' and I regs get their high bits chopped off on
1832 // interrupt.
1833 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1834 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1835 #endif
1836 // A few float args in registers
1837 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1838
1839 return false;
1840 }
1841
1842 bool Matcher::is_spillable_arg( int reg ) {
1843 return can_be_java_arg(reg);
1844 }
1845
1846 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1847 // Use hardware SDIVX instruction when it is
1848 // faster than a code which use multiply.
1849 return VM_Version::has_fast_idiv();
1850 }
1851
1852 // Register for DIVI projection of divmodI
1853 RegMask Matcher::divI_proj_mask() {
1854 ShouldNotReachHere();
1855 return RegMask();
1856 }
1857
1858 // Register for MODI projection of divmodI
1859 RegMask Matcher::modI_proj_mask() {
1860 ShouldNotReachHere();
1861 return RegMask();
1862 }
1863
1864 // Register for DIVL projection of divmodL
1865 RegMask Matcher::divL_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1869
1870 // Register for MODL projection of divmodL
1871 RegMask Matcher::modL_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1875
1876 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1877 return L7_REGP_mask;
1878 }
1879
1880 %}
1881
1882
1883 // The intptr_t operand types, defined by textual substitution.
1884 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1885 #ifdef _LP64
1886 #define immX immL
1887 #define immX13 immL13
1888 #define immX13m7 immL13m7
1889 #define iRegX iRegL
1890 #define g1RegX g1RegL
1891 #else
1892 #define immX immI
1893 #define immX13 immI13
1894 #define immX13m7 immI13m7
1895 #define iRegX iRegI
1896 #define g1RegX g1RegI
1897 #endif
1898
1899 //----------ENCODING BLOCK-----------------------------------------------------
1900 // This block specifies the encoding classes used by the compiler to output
1901 // byte streams. Encoding classes are parameterized macros used by
1902 // Machine Instruction Nodes in order to generate the bit encoding of the
1903 // instruction. Operands specify their base encoding interface with the
1904 // interface keyword. There are currently supported four interfaces,
1905 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1906 // operand to generate a function which returns its register number when
1907 // queried. CONST_INTER causes an operand to generate a function which
1908 // returns the value of the constant when queried. MEMORY_INTER causes an
1909 // operand to generate four functions which return the Base Register, the
1910 // Index Register, the Scale Value, and the Offset Value of the operand when
1911 // queried. COND_INTER causes an operand to generate six functions which
1912 // return the encoding code (ie - encoding bits for the instruction)
1913 // associated with each basic boolean condition for a conditional instruction.
1914 //
1915 // Instructions specify two basic values for encoding. Again, a function
1916 // is available to check if the constant displacement is an oop. They use the
1917 // ins_encode keyword to specify their encoding classes (which must be
1918 // a sequence of enc_class names, and their parameters, specified in
1919 // the encoding block), and they use the
1920 // opcode keyword to specify, in order, their primary, secondary, and
1921 // tertiary opcode. Only the opcode sections which a particular instruction
1922 // needs for encoding need to be specified.
1923 encode %{
1924 enc_class enc_untested %{
1925 #ifdef ASSERT
1926 MacroAssembler _masm(&cbuf);
1927 __ untested("encoding");
1928 #endif
1929 %}
1930
1931 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1932 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1933 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1934 %}
1935
1936 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1937 emit_form3_mem_reg(cbuf, this, $primary, -1,
1938 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1939 %}
1940
1941 enc_class form3_mem_prefetch_read( memory mem ) %{
1942 emit_form3_mem_reg(cbuf, this, $primary, -1,
1943 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1944 %}
1945
1946 enc_class form3_mem_prefetch_write( memory mem ) %{
1947 emit_form3_mem_reg(cbuf, this, $primary, -1,
1948 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1949 %}
1950
1951 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1952 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1953 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1954 guarantee($mem$$index == R_G0_enc, "double index?");
1955 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1956 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1957 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1958 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1959 %}
1960
1961 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1962 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1963 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1964 guarantee($mem$$index == R_G0_enc, "double index?");
1965 // Load long with 2 instructions
1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1968 %}
1969
1970 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1971 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1972 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1973 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1974 %}
1975
1976 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1977 // Encode a reg-reg copy. If it is useless, then empty encoding.
1978 if( $rs2$$reg != $rd$$reg )
1979 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1980 %}
1981
1982 // Target lo half of long
1983 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1984 // Encode a reg-reg copy. If it is useless, then empty encoding.
1985 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1986 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1987 %}
1988
1989 // Source lo half of long
1990 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1991 // Encode a reg-reg copy. If it is useless, then empty encoding.
1992 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1993 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1994 %}
1995
1996 // Target hi half of long
1997 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1998 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1999 %}
2000
2001 // Source lo half of long, and leave it sign extended.
2002 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2003 // Sign extend low half
2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2005 %}
2006
2007 // Source hi half of long, and leave it sign extended.
2008 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2009 // Shift high half to low half
2010 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2011 %}
2012
2013 // Source hi half of long
2014 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2015 // Encode a reg-reg copy. If it is useless, then empty encoding.
2016 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2017 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2018 %}
2019
2020 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2021 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2022 %}
2023
2024 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2025 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2027 %}
2028
2029 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2030 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2031 // clear if nothing else is happening
2032 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2033 // blt,a,pn done
2034 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2035 // mov dst,-1 in delay slot
2036 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2037 %}
2038
2039 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2040 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2041 %}
2042
2043 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2044 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2045 %}
2046
2047 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2048 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2049 %}
2050
2051 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2052 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2053 %}
2054
2055 enc_class move_return_pc_to_o1() %{
2056 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2057 %}
2058
2059 #ifdef _LP64
2060 /* %%% merge with enc_to_bool */
2061 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2062 MacroAssembler _masm(&cbuf);
2063
2064 Register src_reg = reg_to_register_object($src$$reg);
2065 Register dst_reg = reg_to_register_object($dst$$reg);
2066 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2067 %}
2068 #endif
2069
2070 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2071 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2072 MacroAssembler _masm(&cbuf);
2073
2074 Register p_reg = reg_to_register_object($p$$reg);
2075 Register q_reg = reg_to_register_object($q$$reg);
2076 Register y_reg = reg_to_register_object($y$$reg);
2077 Register tmp_reg = reg_to_register_object($tmp$$reg);
2078
2079 __ subcc( p_reg, q_reg, p_reg );
2080 __ add ( p_reg, y_reg, tmp_reg );
2081 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2082 %}
2083
2084 enc_class form_d2i_helper(regD src, regF dst) %{
2085 // fcmp %fcc0,$src,$src
2086 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2087 // branch %fcc0 not-nan, predict taken
2088 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2089 // fdtoi $src,$dst
2090 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2091 // fitos $dst,$dst (if nan)
2092 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2093 // clear $dst (if nan)
2094 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2095 // carry on here...
2096 %}
2097
2098 enc_class form_d2l_helper(regD src, regD dst) %{
2099 // fcmp %fcc0,$src,$src check for NAN
2100 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2101 // branch %fcc0 not-nan, predict taken
2102 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2103 // fdtox $src,$dst convert in delay slot
2104 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2105 // fxtod $dst,$dst (if nan)
2106 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2107 // clear $dst (if nan)
2108 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2109 // carry on here...
2110 %}
2111
2112 enc_class form_f2i_helper(regF src, regF dst) %{
2113 // fcmps %fcc0,$src,$src
2114 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2115 // branch %fcc0 not-nan, predict taken
2116 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2117 // fstoi $src,$dst
2118 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2119 // fitos $dst,$dst (if nan)
2120 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2121 // clear $dst (if nan)
2122 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2123 // carry on here...
2124 %}
2125
2126 enc_class form_f2l_helper(regF src, regD dst) %{
2127 // fcmps %fcc0,$src,$src
2128 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2129 // branch %fcc0 not-nan, predict taken
2130 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2131 // fstox $src,$dst
2132 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2133 // fxtod $dst,$dst (if nan)
2134 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2135 // clear $dst (if nan)
2136 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2137 // carry on here...
2138 %}
2139
2140 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2141 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2142 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2143 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2144
2145 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2146
2147 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2148 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2149
2150 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2151 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2152 %}
2153
2154 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2155 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2156 %}
2157
2158 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2159 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2160 %}
2161
2162 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2163 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2164 %}
2165
2166 enc_class form3_convI2F(regF rs2, regF rd) %{
2167 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2168 %}
2169
2170 // Encloding class for traceable jumps
2171 enc_class form_jmpl(g3RegP dest) %{
2172 emit_jmpl(cbuf, $dest$$reg);
2173 %}
2174
2175 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2176 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2177 %}
2178
2179 enc_class form2_nop() %{
2180 emit_nop(cbuf);
2181 %}
2182
2183 enc_class form2_illtrap() %{
2184 emit_illtrap(cbuf);
2185 %}
2186
2187
2188 // Compare longs and convert into -1, 0, 1.
2189 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2190 // CMP $src1,$src2
2191 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2192 // blt,a,pn done
2193 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2194 // mov dst,-1 in delay slot
2195 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2196 // bgt,a,pn done
2197 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2198 // mov dst,1 in delay slot
2199 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2200 // CLR $dst
2201 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2202 %}
2203
2204 enc_class enc_PartialSubtypeCheck() %{
2205 MacroAssembler _masm(&cbuf);
2206 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2207 __ delayed()->nop();
2208 %}
2209
2210 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2211 MacroAssembler _masm(&cbuf);
2212 Label &L = *($labl$$label);
2213 Assembler::Predict predict_taken =
2214 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2215
2216 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2217 __ delayed()->nop();
2218 %}
2219
2220 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2221 MacroAssembler _masm(&cbuf);
2222 Label &L = *($labl$$label);
2223 Assembler::Predict predict_taken =
2224 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2225
2226 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2227 __ delayed()->nop();
2228 %}
2229
2230 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2231 MacroAssembler _masm(&cbuf);
2232 Label &L = *($labl$$label);
2233 Assembler::Predict predict_taken =
2234 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2235
2236 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2237 __ delayed()->nop();
2238 %}
2239
2240 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2241 MacroAssembler _masm(&cbuf);
2242 Label &L = *($labl$$label);
2243 Assembler::Predict predict_taken =
2244 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2245
2246 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2247 __ delayed()->nop();
2248 %}
2249
2250 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2251 MacroAssembler _masm(&cbuf);
2252
2253 Register switch_reg = as_Register($switch_val$$reg);
2254 Register table_reg = O7;
2255
2256 address table_base = __ address_table_constant(_index2label);
2257 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2258
2259 // Move table address into a register.
2260 __ set(table_base, table_reg, rspec);
2261
2262 // Jump to base address + switch value
2263 __ ld_ptr(table_reg, switch_reg, table_reg);
2264 __ jmp(table_reg, G0);
2265 __ delayed()->nop();
2266
2267 %}
2268
2269 enc_class enc_ba( Label labl ) %{
2270 MacroAssembler _masm(&cbuf);
2271 Label &L = *($labl$$label);
2272 __ ba(false, L);
2273 __ delayed()->nop();
2274 %}
2275
2276 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2277 MacroAssembler _masm(&cbuf);
2278 Label &L = *$labl$$label;
2279 Assembler::Predict predict_taken =
2280 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2281
2282 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2283 __ delayed()->nop();
2284 %}
2285
2286 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2287 int op = (Assembler::arith_op << 30) |
2288 ($dst$$reg << 25) |
2289 (Assembler::movcc_op3 << 19) |
2290 (1 << 18) | // cc2 bit for 'icc'
2291 ($cmp$$cmpcode << 14) |
2292 (0 << 13) | // select register move
2293 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2294 ($src$$reg << 0);
2295 cbuf.insts()->emit_int32(op);
2296 %}
2297
2298 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2299 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2300 int op = (Assembler::arith_op << 30) |
2301 ($dst$$reg << 25) |
2302 (Assembler::movcc_op3 << 19) |
2303 (1 << 18) | // cc2 bit for 'icc'
2304 ($cmp$$cmpcode << 14) |
2305 (1 << 13) | // select immediate move
2306 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2307 (simm11 << 0);
2308 cbuf.insts()->emit_int32(op);
2309 %}
2310
2311 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2312 int op = (Assembler::arith_op << 30) |
2313 ($dst$$reg << 25) |
2314 (Assembler::movcc_op3 << 19) |
2315 (0 << 18) | // cc2 bit for 'fccX'
2316 ($cmp$$cmpcode << 14) |
2317 (0 << 13) | // select register move
2318 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2319 ($src$$reg << 0);
2320 cbuf.insts()->emit_int32(op);
2321 %}
2322
2323 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2324 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2325 int op = (Assembler::arith_op << 30) |
2326 ($dst$$reg << 25) |
2327 (Assembler::movcc_op3 << 19) |
2328 (0 << 18) | // cc2 bit for 'fccX'
2329 ($cmp$$cmpcode << 14) |
2330 (1 << 13) | // select immediate move
2331 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2332 (simm11 << 0);
2333 cbuf.insts()->emit_int32(op);
2334 %}
2335
2336 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2337 int op = (Assembler::arith_op << 30) |
2338 ($dst$$reg << 25) |
2339 (Assembler::fpop2_op3 << 19) |
2340 (0 << 18) |
2341 ($cmp$$cmpcode << 14) |
2342 (1 << 13) | // select register move
2343 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2344 ($primary << 5) | // select single, double or quad
2345 ($src$$reg << 0);
2346 cbuf.insts()->emit_int32(op);
2347 %}
2348
2349 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2350 int op = (Assembler::arith_op << 30) |
2351 ($dst$$reg << 25) |
2352 (Assembler::fpop2_op3 << 19) |
2353 (0 << 18) |
2354 ($cmp$$cmpcode << 14) |
2355 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2356 ($primary << 5) | // select single, double or quad
2357 ($src$$reg << 0);
2358 cbuf.insts()->emit_int32(op);
2359 %}
2360
2361 // Used by the MIN/MAX encodings. Same as a CMOV, but
2362 // the condition comes from opcode-field instead of an argument.
2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2364 int op = (Assembler::arith_op << 30) |
2365 ($dst$$reg << 25) |
2366 (Assembler::movcc_op3 << 19) |
2367 (1 << 18) | // cc2 bit for 'icc'
2368 ($primary << 14) |
2369 (0 << 13) | // select register move
2370 (0 << 11) | // cc1, cc0 bits for 'icc'
2371 ($src$$reg << 0);
2372 cbuf.insts()->emit_int32(op);
2373 %}
2374
2375 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2376 int op = (Assembler::arith_op << 30) |
2377 ($dst$$reg << 25) |
2378 (Assembler::movcc_op3 << 19) |
2379 (6 << 16) | // cc2 bit for 'xcc'
2380 ($primary << 14) |
2381 (0 << 13) | // select register move
2382 (0 << 11) | // cc1, cc0 bits for 'icc'
2383 ($src$$reg << 0);
2384 cbuf.insts()->emit_int32(op);
2385 %}
2386
2387 // Utility encoding for loading a 64 bit Pointer into a register
2388 // The 64 bit pointer is stored in the generated code stream
2389 enc_class SetPtr( immP src, iRegP rd ) %{
2390 Register dest = reg_to_register_object($rd$$reg);
2391 MacroAssembler _masm(&cbuf);
2392 // [RGV] This next line should be generated from ADLC
2393 if ( _opnds[1]->constant_is_oop() ) {
2394 intptr_t val = $src$$constant;
2395 __ set_oop_constant((jobject)val, dest);
2396 } else { // non-oop pointers, e.g. card mark base, heap top
2397 __ set($src$$constant, dest);
2398 }
2399 %}
2400
2401 enc_class Set13( immI13 src, iRegI rd ) %{
2402 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2403 %}
2404
2405 enc_class SetHi22( immI src, iRegI rd ) %{
2406 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2407 %}
2408
2409 enc_class Set32( immI src, iRegI rd ) %{
2410 MacroAssembler _masm(&cbuf);
2411 __ set($src$$constant, reg_to_register_object($rd$$reg));
2412 %}
2413
2414 enc_class SetNull( iRegI rd ) %{
2415 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2416 %}
2417
2418 enc_class call_epilog %{
2419 if( VerifyStackAtCalls ) {
2420 MacroAssembler _masm(&cbuf);
2421 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2422 Register temp_reg = G3;
2423 __ add(SP, framesize, temp_reg);
2424 __ cmp(temp_reg, FP);
2425 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2426 }
2427 %}
2428
2429 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2430 // to G1 so the register allocator will not have to deal with the misaligned register
2431 // pair.
2432 enc_class adjust_long_from_native_call %{
2433 #ifndef _LP64
2434 if (returns_long()) {
2435 // sllx O0,32,O0
2436 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2437 // srl O1,0,O1
2438 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2439 // or O0,O1,G1
2440 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2441 }
2442 #endif
2443 %}
2444
2445 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2446 // CALL directly to the runtime
2447 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2448 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2449 /*preserve_g2=*/true, /*force far call*/true);
2450 %}
2451
2452 enc_class preserve_SP %{
2453 MacroAssembler _masm(&cbuf);
2454 __ mov(SP, L7_mh_SP_save);
2455 %}
2456
2457 enc_class restore_SP %{
2458 MacroAssembler _masm(&cbuf);
2459 __ mov(L7_mh_SP_save, SP);
2460 %}
2461
2462 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2463 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2464 // who we intended to call.
2465 if ( !_method ) {
2466 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2467 } else if (_optimized_virtual) {
2468 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2469 } else {
2470 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2471 }
2472 if( _method ) { // Emit stub for static call
2473 emit_java_to_interp(cbuf);
2474 }
2475 %}
2476
2477 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2478 MacroAssembler _masm(&cbuf);
2479 __ set_inst_mark();
2480 int vtable_index = this->_vtable_index;
2481 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2482 if (vtable_index < 0) {
2483 // must be invalid_vtable_index, not nonvirtual_vtable_index
2484 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2485 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2486 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2487 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2488 // !!!!!
2489 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2490 // emit_call_dynamic_prologue( cbuf );
2491 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2492
2493 address virtual_call_oop_addr = __ inst_mark();
2494 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2495 // who we intended to call.
2496 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2497 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2498 } else {
2499 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2500 // Just go thru the vtable
2501 // get receiver klass (receiver already checked for non-null)
2502 // If we end up going thru a c2i adapter interpreter expects method in G5
2503 int off = __ offset();
2504 __ load_klass(O0, G3_scratch);
2505 int klass_load_size;
2506 if (UseCompressedOops) {
2507 assert(Universe::heap() != NULL, "java heap should be initialized");
2508 if (Universe::narrow_oop_base() == NULL)
2509 klass_load_size = 2*BytesPerInstWord;
2510 else
2511 klass_load_size = 3*BytesPerInstWord;
2512 } else {
2513 klass_load_size = 1*BytesPerInstWord;
2514 }
2515 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2516 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2517 if( __ is_simm13(v_off) ) {
2518 __ ld_ptr(G3, v_off, G5_method);
2519 } else {
2520 // Generate 2 instructions
2521 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2522 __ or3(G5_method, v_off & 0x3ff, G5_method);
2523 // ld_ptr, set_hi, set
2524 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2525 "Unexpected instruction size(s)");
2526 __ ld_ptr(G3, G5_method, G5_method);
2527 }
2528 // NOTE: for vtable dispatches, the vtable entry will never be null.
2529 // However it may very well end up in handle_wrong_method if the
2530 // method is abstract for the particular class.
2531 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2532 // jump to target (either compiled code or c2iadapter)
2533 __ jmpl(G3_scratch, G0, O7);
2534 __ delayed()->nop();
2535 }
2536 %}
2537
2538 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2539 MacroAssembler _masm(&cbuf);
2540
2541 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2542 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2543 // we might be calling a C2I adapter which needs it.
2544
2545 assert(temp_reg != G5_ic_reg, "conflicting registers");
2546 // Load nmethod
2547 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2548
2549 // CALL to compiled java, indirect the contents of G3
2550 __ set_inst_mark();
2551 __ callr(temp_reg, G0);
2552 __ delayed()->nop();
2553 %}
2554
2555 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2556 MacroAssembler _masm(&cbuf);
2557 Register Rdividend = reg_to_register_object($src1$$reg);
2558 Register Rdivisor = reg_to_register_object($src2$$reg);
2559 Register Rresult = reg_to_register_object($dst$$reg);
2560
2561 __ sra(Rdivisor, 0, Rdivisor);
2562 __ sra(Rdividend, 0, Rdividend);
2563 __ sdivx(Rdividend, Rdivisor, Rresult);
2564 %}
2565
2566 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2567 MacroAssembler _masm(&cbuf);
2568
2569 Register Rdividend = reg_to_register_object($src1$$reg);
2570 int divisor = $imm$$constant;
2571 Register Rresult = reg_to_register_object($dst$$reg);
2572
2573 __ sra(Rdividend, 0, Rdividend);
2574 __ sdivx(Rdividend, divisor, Rresult);
2575 %}
2576
2577 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2578 MacroAssembler _masm(&cbuf);
2579 Register Rsrc1 = reg_to_register_object($src1$$reg);
2580 Register Rsrc2 = reg_to_register_object($src2$$reg);
2581 Register Rdst = reg_to_register_object($dst$$reg);
2582
2583 __ sra( Rsrc1, 0, Rsrc1 );
2584 __ sra( Rsrc2, 0, Rsrc2 );
2585 __ mulx( Rsrc1, Rsrc2, Rdst );
2586 __ srlx( Rdst, 32, Rdst );
2587 %}
2588
2589 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2590 MacroAssembler _masm(&cbuf);
2591 Register Rdividend = reg_to_register_object($src1$$reg);
2592 Register Rdivisor = reg_to_register_object($src2$$reg);
2593 Register Rresult = reg_to_register_object($dst$$reg);
2594 Register Rscratch = reg_to_register_object($scratch$$reg);
2595
2596 assert(Rdividend != Rscratch, "");
2597 assert(Rdivisor != Rscratch, "");
2598
2599 __ sra(Rdividend, 0, Rdividend);
2600 __ sra(Rdivisor, 0, Rdivisor);
2601 __ sdivx(Rdividend, Rdivisor, Rscratch);
2602 __ mulx(Rscratch, Rdivisor, Rscratch);
2603 __ sub(Rdividend, Rscratch, Rresult);
2604 %}
2605
2606 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2607 MacroAssembler _masm(&cbuf);
2608
2609 Register Rdividend = reg_to_register_object($src1$$reg);
2610 int divisor = $imm$$constant;
2611 Register Rresult = reg_to_register_object($dst$$reg);
2612 Register Rscratch = reg_to_register_object($scratch$$reg);
2613
2614 assert(Rdividend != Rscratch, "");
2615
2616 __ sra(Rdividend, 0, Rdividend);
2617 __ sdivx(Rdividend, divisor, Rscratch);
2618 __ mulx(Rscratch, divisor, Rscratch);
2619 __ sub(Rdividend, Rscratch, Rresult);
2620 %}
2621
2622 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2623 MacroAssembler _masm(&cbuf);
2624
2625 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2626 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2627
2628 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2629 %}
2630
2631 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2632 MacroAssembler _masm(&cbuf);
2633
2634 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2635 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2636
2637 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2638 %}
2639
2640 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2641 MacroAssembler _masm(&cbuf);
2642
2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2645
2646 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2647 %}
2648
2649 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2650 MacroAssembler _masm(&cbuf);
2651
2652 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2653 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2654
2655 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2656 %}
2657
2658 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2659 MacroAssembler _masm(&cbuf);
2660
2661 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2662 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2663
2664 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2665 %}
2666
2667 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2668 MacroAssembler _masm(&cbuf);
2669
2670 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2671 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2672
2673 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2674 %}
2675
2676 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2677 MacroAssembler _masm(&cbuf);
2678
2679 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2680 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2681
2682 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2683 %}
2684
2685 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2686 MacroAssembler _masm(&cbuf);
2687
2688 Register Roop = reg_to_register_object($oop$$reg);
2689 Register Rbox = reg_to_register_object($box$$reg);
2690 Register Rscratch = reg_to_register_object($scratch$$reg);
2691 Register Rmark = reg_to_register_object($scratch2$$reg);
2692
2693 assert(Roop != Rscratch, "");
2694 assert(Roop != Rmark, "");
2695 assert(Rbox != Rscratch, "");
2696 assert(Rbox != Rmark, "");
2697
2698 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2699 %}
2700
2701 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2702 MacroAssembler _masm(&cbuf);
2703
2704 Register Roop = reg_to_register_object($oop$$reg);
2705 Register Rbox = reg_to_register_object($box$$reg);
2706 Register Rscratch = reg_to_register_object($scratch$$reg);
2707 Register Rmark = reg_to_register_object($scratch2$$reg);
2708
2709 assert(Roop != Rscratch, "");
2710 assert(Roop != Rmark, "");
2711 assert(Rbox != Rscratch, "");
2712 assert(Rbox != Rmark, "");
2713
2714 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2715 %}
2716
2717 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2718 MacroAssembler _masm(&cbuf);
2719 Register Rmem = reg_to_register_object($mem$$reg);
2720 Register Rold = reg_to_register_object($old$$reg);
2721 Register Rnew = reg_to_register_object($new$$reg);
2722
2723 // casx_under_lock picks 1 of 3 encodings:
2724 // For 32-bit pointers you get a 32-bit CAS
2725 // For 64-bit pointers you get a 64-bit CASX
2726 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2727 __ cmp( Rold, Rnew );
2728 %}
2729
2730 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2731 Register Rmem = reg_to_register_object($mem$$reg);
2732 Register Rold = reg_to_register_object($old$$reg);
2733 Register Rnew = reg_to_register_object($new$$reg);
2734
2735 MacroAssembler _masm(&cbuf);
2736 __ mov(Rnew, O7);
2737 __ casx(Rmem, Rold, O7);
2738 __ cmp( Rold, O7 );
2739 %}
2740
2741 // raw int cas, used for compareAndSwap
2742 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2743 Register Rmem = reg_to_register_object($mem$$reg);
2744 Register Rold = reg_to_register_object($old$$reg);
2745 Register Rnew = reg_to_register_object($new$$reg);
2746
2747 MacroAssembler _masm(&cbuf);
2748 __ mov(Rnew, O7);
2749 __ cas(Rmem, Rold, O7);
2750 __ cmp( Rold, O7 );
2751 %}
2752
2753 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2754 Register Rres = reg_to_register_object($res$$reg);
2755
2756 MacroAssembler _masm(&cbuf);
2757 __ mov(1, Rres);
2758 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2759 %}
2760
2761 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2762 Register Rres = reg_to_register_object($res$$reg);
2763
2764 MacroAssembler _masm(&cbuf);
2765 __ mov(1, Rres);
2766 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2767 %}
2768
2769 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2770 MacroAssembler _masm(&cbuf);
2771 Register Rdst = reg_to_register_object($dst$$reg);
2772 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2773 : reg_to_DoubleFloatRegister_object($src1$$reg);
2774 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2775 : reg_to_DoubleFloatRegister_object($src2$$reg);
2776
2777 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2778 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2779 %}
2780
2781 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2782 MacroAssembler _masm(&cbuf);
2783 Register dest = reg_to_register_object($dst$$reg);
2784 Register temp = reg_to_register_object($tmp$$reg);
2785 __ set64( $src$$constant, dest, temp );
2786 %}
2787
2788 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2789 // Load a constant replicated "count" times with width "width"
2790 int bit_width = $width$$constant * 8;
2791 jlong elt_val = $src$$constant;
2792 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2793 jlong val = elt_val;
2794 for (int i = 0; i < $count$$constant - 1; i++) {
2795 val <<= bit_width;
2796 val |= elt_val;
2797 }
2798 jdouble dval = *(jdouble*)&val; // coerce to double type
2799 MacroAssembler _masm(&cbuf);
2800 address double_address = __ double_constant(dval);
2801 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2802 AddressLiteral addrlit(double_address, rspec);
2803
2804 __ sethi(addrlit, $tmp$$Register);
2805 // XXX This is a quick fix for 6833573.
2806 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2807 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2808 %}
2809
2810 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2811 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2812 MacroAssembler _masm(&cbuf);
2813 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2814 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2815 Register base_pointer_arg = reg_to_register_object($base$$reg);
2816
2817 Label loop;
2818 __ mov(nof_bytes_arg, nof_bytes_tmp);
2819
2820 // Loop and clear, walking backwards through the array.
2821 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2822 __ bind(loop);
2823 __ deccc(nof_bytes_tmp, 8);
2824 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2825 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2826 // %%%% this mini-loop must not cross a cache boundary!
2827 %}
2828
2829
2830 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2831 Label Ldone, Lloop;
2832 MacroAssembler _masm(&cbuf);
2833
2834 Register str1_reg = reg_to_register_object($str1$$reg);
2835 Register str2_reg = reg_to_register_object($str2$$reg);
2836 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2837 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2838 Register result_reg = reg_to_register_object($result$$reg);
2839
2840 assert(result_reg != str1_reg &&
2841 result_reg != str2_reg &&
2842 result_reg != cnt1_reg &&
2843 result_reg != cnt2_reg ,
2844 "need different registers");
2845
2846 // Compute the minimum of the string lengths(str1_reg) and the
2847 // difference of the string lengths (stack)
2848
2849 // See if the lengths are different, and calculate min in str1_reg.
2850 // Stash diff in O7 in case we need it for a tie-breaker.
2851 Label Lskip;
2852 __ subcc(cnt1_reg, cnt2_reg, O7);
2853 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2854 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2855 // cnt2 is shorter, so use its count:
2856 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2857 __ bind(Lskip);
2858
2859 // reallocate cnt1_reg, cnt2_reg, result_reg
2860 // Note: limit_reg holds the string length pre-scaled by 2
2861 Register limit_reg = cnt1_reg;
2862 Register chr2_reg = cnt2_reg;
2863 Register chr1_reg = result_reg;
2864 // str{12} are the base pointers
2865
2866 // Is the minimum length zero?
2867 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2868 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2869 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2870
2871 // Load first characters
2872 __ lduh(str1_reg, 0, chr1_reg);
2873 __ lduh(str2_reg, 0, chr2_reg);
2874
2875 // Compare first characters
2876 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2877 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2878 assert(chr1_reg == result_reg, "result must be pre-placed");
2879 __ delayed()->nop();
2880
2881 {
2882 // Check after comparing first character to see if strings are equivalent
2883 Label LSkip2;
2884 // Check if the strings start at same location
2885 __ cmp(str1_reg, str2_reg);
2886 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2887 __ delayed()->nop();
2888
2889 // Check if the length difference is zero (in O7)
2890 __ cmp(G0, O7);
2891 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2892 __ delayed()->mov(G0, result_reg); // result is zero
2893
2894 // Strings might not be equal
2895 __ bind(LSkip2);
2896 }
2897
2898 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2899 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2900 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2901
2902 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2903 __ add(str1_reg, limit_reg, str1_reg);
2904 __ add(str2_reg, limit_reg, str2_reg);
2905 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2906
2907 // Compare the rest of the characters
2908 __ lduh(str1_reg, limit_reg, chr1_reg);
2909 __ bind(Lloop);
2910 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2911 __ lduh(str2_reg, limit_reg, chr2_reg);
2912 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2913 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2914 assert(chr1_reg == result_reg, "result must be pre-placed");
2915 __ delayed()->inccc(limit_reg, sizeof(jchar));
2916 // annul LDUH if branch is not taken to prevent access past end of string
2917 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2918 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2919
2920 // If strings are equal up to min length, return the length difference.
2921 __ mov(O7, result_reg);
2922
2923 // Otherwise, return the difference between the first mismatched chars.
2924 __ bind(Ldone);
2925 %}
2926
2927 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2928 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2929 MacroAssembler _masm(&cbuf);
2930
2931 Register str1_reg = reg_to_register_object($str1$$reg);
2932 Register str2_reg = reg_to_register_object($str2$$reg);
2933 Register cnt_reg = reg_to_register_object($cnt$$reg);
2934 Register tmp1_reg = O7;
2935 Register result_reg = reg_to_register_object($result$$reg);
2936
2937 assert(result_reg != str1_reg &&
2938 result_reg != str2_reg &&
2939 result_reg != cnt_reg &&
2940 result_reg != tmp1_reg ,
2941 "need different registers");
2942
2943 __ cmp(str1_reg, str2_reg); //same char[] ?
2944 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2945 __ delayed()->add(G0, 1, result_reg);
2946
2947 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2948 __ delayed()->add(G0, 1, result_reg); // count == 0
2949
2950 //rename registers
2951 Register limit_reg = cnt_reg;
2952 Register chr1_reg = result_reg;
2953 Register chr2_reg = tmp1_reg;
2954
2955 //check for alignment and position the pointers to the ends
2956 __ or3(str1_reg, str2_reg, chr1_reg);
2957 __ andcc(chr1_reg, 0x3, chr1_reg);
2958 // notZero means at least one not 4-byte aligned.
2959 // We could optimize the case when both arrays are not aligned
2960 // but it is not frequent case and it requires additional checks.
2961 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2962 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2963
2964 // Compare char[] arrays aligned to 4 bytes.
2965 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2966 chr1_reg, chr2_reg, Ldone);
2967 __ ba(false,Ldone);
2968 __ delayed()->add(G0, 1, result_reg);
2969
2970 // char by char compare
2971 __ bind(Lchar);
2972 __ add(str1_reg, limit_reg, str1_reg);
2973 __ add(str2_reg, limit_reg, str2_reg);
2974 __ neg(limit_reg); //negate count
2975
2976 __ lduh(str1_reg, limit_reg, chr1_reg);
2977 // Lchar_loop
2978 __ bind(Lchar_loop);
2979 __ lduh(str2_reg, limit_reg, chr2_reg);
2980 __ cmp(chr1_reg, chr2_reg);
2981 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2982 __ delayed()->mov(G0, result_reg); //not equal
2983 __ inccc(limit_reg, sizeof(jchar));
2984 // annul LDUH if branch is not taken to prevent access past end of string
2985 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2986 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2987
2988 __ add(G0, 1, result_reg); //equal
2989
2990 __ bind(Ldone);
2991 %}
2992
2993 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2994 Label Lvector, Ldone, Lloop;
2995 MacroAssembler _masm(&cbuf);
2996
2997 Register ary1_reg = reg_to_register_object($ary1$$reg);
2998 Register ary2_reg = reg_to_register_object($ary2$$reg);
2999 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3000 Register tmp2_reg = O7;
3001 Register result_reg = reg_to_register_object($result$$reg);
3002
3003 int length_offset = arrayOopDesc::length_offset_in_bytes();
3004 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3005
3006 // return true if the same array
3007 __ cmp(ary1_reg, ary2_reg);
3008 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3009 __ delayed()->add(G0, 1, result_reg); // equal
3010
3011 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3012 __ delayed()->mov(G0, result_reg); // not equal
3013
3014 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3015 __ delayed()->mov(G0, result_reg); // not equal
3016
3017 //load the lengths of arrays
3018 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3019 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3020
3021 // return false if the two arrays are not equal length
3022 __ cmp(tmp1_reg, tmp2_reg);
3023 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3024 __ delayed()->mov(G0, result_reg); // not equal
3025
3026 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3027 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3028
3029 // load array addresses
3030 __ add(ary1_reg, base_offset, ary1_reg);
3031 __ add(ary2_reg, base_offset, ary2_reg);
3032
3033 // renaming registers
3034 Register chr1_reg = result_reg; // for characters in ary1
3035 Register chr2_reg = tmp2_reg; // for characters in ary2
3036 Register limit_reg = tmp1_reg; // length
3037
3038 // set byte count
3039 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3040
3041 // Compare char[] arrays aligned to 4 bytes.
3042 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3043 chr1_reg, chr2_reg, Ldone);
3044 __ add(G0, 1, result_reg); // equals
3045
3046 __ bind(Ldone);
3047 %}
3048
3049 enc_class enc_rethrow() %{
3050 cbuf.set_insts_mark();
3051 Register temp_reg = G3;
3052 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3053 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3054 MacroAssembler _masm(&cbuf);
3055 #ifdef ASSERT
3056 __ save_frame(0);
3057 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3058 __ sethi(last_rethrow_addrlit, L1);
3059 Address addr(L1, last_rethrow_addrlit.low10());
3060 __ get_pc(L2);
3061 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3062 __ st_ptr(L2, addr);
3063 __ restore();
3064 #endif
3065 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3066 __ delayed()->nop();
3067 %}
3068
3069 enc_class emit_mem_nop() %{
3070 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3071 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3072 %}
3073
3074 enc_class emit_fadd_nop() %{
3075 // Generates the instruction FMOVS f31,f31
3076 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3077 %}
3078
3079 enc_class emit_br_nop() %{
3080 // Generates the instruction BPN,PN .
3081 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3082 %}
3083
3084 enc_class enc_membar_acquire %{
3085 MacroAssembler _masm(&cbuf);
3086 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3087 %}
3088
3089 enc_class enc_membar_release %{
3090 MacroAssembler _masm(&cbuf);
3091 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3092 %}
3093
3094 enc_class enc_membar_volatile %{
3095 MacroAssembler _masm(&cbuf);
3096 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3097 %}
3098
3099 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3100 MacroAssembler _masm(&cbuf);
3101 Register src_reg = reg_to_register_object($src$$reg);
3102 Register dst_reg = reg_to_register_object($dst$$reg);
3103 __ sllx(src_reg, 56, dst_reg);
3104 __ srlx(dst_reg, 8, O7);
3105 __ or3 (dst_reg, O7, dst_reg);
3106 __ srlx(dst_reg, 16, O7);
3107 __ or3 (dst_reg, O7, dst_reg);
3108 __ srlx(dst_reg, 32, O7);
3109 __ or3 (dst_reg, O7, dst_reg);
3110 %}
3111
3112 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3113 MacroAssembler _masm(&cbuf);
3114 Register src_reg = reg_to_register_object($src$$reg);
3115 Register dst_reg = reg_to_register_object($dst$$reg);
3116 __ sll(src_reg, 24, dst_reg);
3117 __ srl(dst_reg, 8, O7);
3118 __ or3(dst_reg, O7, dst_reg);
3119 __ srl(dst_reg, 16, O7);
3120 __ or3(dst_reg, O7, dst_reg);
3121 %}
3122
3123 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3124 MacroAssembler _masm(&cbuf);
3125 Register src_reg = reg_to_register_object($src$$reg);
3126 Register dst_reg = reg_to_register_object($dst$$reg);
3127 __ sllx(src_reg, 48, dst_reg);
3128 __ srlx(dst_reg, 16, O7);
3129 __ or3 (dst_reg, O7, dst_reg);
3130 __ srlx(dst_reg, 32, O7);
3131 __ or3 (dst_reg, O7, dst_reg);
3132 %}
3133
3134 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3135 MacroAssembler _masm(&cbuf);
3136 Register src_reg = reg_to_register_object($src$$reg);
3137 Register dst_reg = reg_to_register_object($dst$$reg);
3138 __ sllx(src_reg, 32, dst_reg);
3139 __ srlx(dst_reg, 32, O7);
3140 __ or3 (dst_reg, O7, dst_reg);
3141 %}
3142
3143 %}
3144
3145 //----------FRAME--------------------------------------------------------------
3146 // Definition of frame structure and management information.
3147 //
3148 // S T A C K L A Y O U T Allocators stack-slot number
3149 // | (to get allocators register number
3150 // G Owned by | | v add VMRegImpl::stack0)
3151 // r CALLER | |
3152 // o | +--------+ pad to even-align allocators stack-slot
3153 // w V | pad0 | numbers; owned by CALLER
3154 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3155 // h ^ | in | 5
3156 // | | args | 4 Holes in incoming args owned by SELF
3157 // | | | | 3
3158 // | | +--------+
3159 // V | | old out| Empty on Intel, window on Sparc
3160 // | old |preserve| Must be even aligned.
3161 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3162 // | | in | 3 area for Intel ret address
3163 // Owned by |preserve| Empty on Sparc.
3164 // SELF +--------+
3165 // | | pad2 | 2 pad to align old SP
3166 // | +--------+ 1
3167 // | | locks | 0
3168 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3169 // | | pad1 | 11 pad to align new SP
3170 // | +--------+
3171 // | | | 10
3172 // | | spills | 9 spills
3173 // V | | 8 (pad0 slot for callee)
3174 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3175 // ^ | out | 7
3176 // | | args | 6 Holes in outgoing args owned by CALLEE
3177 // Owned by +--------+
3178 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3179 // | new |preserve| Must be even-aligned.
3180 // | SP-+--------+----> Matcher::_new_SP, even aligned
3181 // | | |
3182 //
3183 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3184 // known from SELF's arguments and the Java calling convention.
3185 // Region 6-7 is determined per call site.
3186 // Note 2: If the calling convention leaves holes in the incoming argument
3187 // area, those holes are owned by SELF. Holes in the outgoing area
3188 // are owned by the CALLEE. Holes should not be nessecary in the
3189 // incoming area, as the Java calling convention is completely under
3190 // the control of the AD file. Doubles can be sorted and packed to
3191 // avoid holes. Holes in the outgoing arguments may be nessecary for
3192 // varargs C calling conventions.
3193 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3194 // even aligned with pad0 as needed.
3195 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3196 // region 6-11 is even aligned; it may be padded out more so that
3197 // the region from SP to FP meets the minimum stack alignment.
3198
3199 frame %{
3200 // What direction does stack grow in (assumed to be same for native & Java)
3201 stack_direction(TOWARDS_LOW);
3202
3203 // These two registers define part of the calling convention
3204 // between compiled code and the interpreter.
3205 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3206 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3207
3208 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3209 cisc_spilling_operand_name(indOffset);
3210
3211 // Number of stack slots consumed by a Monitor enter
3212 #ifdef _LP64
3213 sync_stack_slots(2);
3214 #else
3215 sync_stack_slots(1);
3216 #endif
3217
3218 // Compiled code's Frame Pointer
3219 frame_pointer(R_SP);
3220
3221 // Stack alignment requirement
3222 stack_alignment(StackAlignmentInBytes);
3223 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3224 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3225
3226 // Number of stack slots between incoming argument block and the start of
3227 // a new frame. The PROLOG must add this many slots to the stack. The
3228 // EPILOG must remove this many slots.
3229 in_preserve_stack_slots(0);
3230
3231 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3232 // for calls to C. Supports the var-args backing area for register parms.
3233 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3234 #ifdef _LP64
3235 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3236 varargs_C_out_slots_killed(12);
3237 #else
3238 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3239 varargs_C_out_slots_killed( 7);
3240 #endif
3241
3242 // The after-PROLOG location of the return address. Location of
3243 // return address specifies a type (REG or STACK) and a number
3244 // representing the register number (i.e. - use a register name) or
3245 // stack slot.
3246 return_addr(REG R_I7); // Ret Addr is in register I7
3247
3248 // Body of function which returns an OptoRegs array locating
3249 // arguments either in registers or in stack slots for calling
3250 // java
3251 calling_convention %{
3252 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3253
3254 %}
3255
3256 // Body of function which returns an OptoRegs array locating
3257 // arguments either in registers or in stack slots for callin
3258 // C.
3259 c_calling_convention %{
3260 // This is obviously always outgoing
3261 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3262 %}
3263
3264 // Location of native (C/C++) and interpreter return values. This is specified to
3265 // be the same as Java. In the 32-bit VM, long values are actually returned from
3266 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3267 // to and from the register pairs is done by the appropriate call and epilog
3268 // opcodes. This simplifies the register allocator.
3269 c_return_value %{
3270 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3271 #ifdef _LP64
3272 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3273 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3274 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3275 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3276 #else // !_LP64
3277 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3278 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3279 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3280 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3281 #endif
3282 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3283 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3284 %}
3285
3286 // Location of compiled Java return values. Same as C
3287 return_value %{
3288 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3289 #ifdef _LP64
3290 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3291 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3292 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3293 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3294 #else // !_LP64
3295 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3296 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3297 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3298 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3299 #endif
3300 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3301 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3302 %}
3303
3304 %}
3305
3306
3307 //----------ATTRIBUTES---------------------------------------------------------
3308 //----------Operand Attributes-------------------------------------------------
3309 op_attrib op_cost(1); // Required cost attribute
3310
3311 //----------Instruction Attributes---------------------------------------------
3312 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3313 ins_attrib ins_size(32); // Required size attribute (in bits)
3314 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3315 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3316 // non-matching short branch variant of some
3317 // long branch?
3318
3319 //----------OPERANDS-----------------------------------------------------------
3320 // Operand definitions must precede instruction definitions for correct parsing
3321 // in the ADLC because operands constitute user defined types which are used in
3322 // instruction definitions.
3323
3324 //----------Simple Operands----------------------------------------------------
3325 // Immediate Operands
3326 // Integer Immediate: 32-bit
3327 operand immI() %{
3328 match(ConI);
3329
3330 op_cost(0);
3331 // formats are generated automatically for constants and base registers
3332 format %{ %}
3333 interface(CONST_INTER);
3334 %}
3335
3336 // Integer Immediate: 8-bit
3337 operand immI8() %{
3338 predicate(Assembler::is_simm(n->get_int(), 8));
3339 match(ConI);
3340 op_cost(0);
3341 format %{ %}
3342 interface(CONST_INTER);
3343 %}
3344
3345 // Integer Immediate: 13-bit
3346 operand immI13() %{
3347 predicate(Assembler::is_simm13(n->get_int()));
3348 match(ConI);
3349 op_cost(0);
3350
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 // Integer Immediate: 13-bit minus 7
3356 operand immI13m7() %{
3357 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3358 match(ConI);
3359 op_cost(0);
3360
3361 format %{ %}
3362 interface(CONST_INTER);
3363 %}
3364
3365 // Integer Immediate: 16-bit
3366 operand immI16() %{
3367 predicate(Assembler::is_simm(n->get_int(), 16));
3368 match(ConI);
3369 op_cost(0);
3370 format %{ %}
3371 interface(CONST_INTER);
3372 %}
3373
3374 // Unsigned (positive) Integer Immediate: 13-bit
3375 operand immU13() %{
3376 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3377 match(ConI);
3378 op_cost(0);
3379
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Integer Immediate: 6-bit
3385 operand immU6() %{
3386 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3387 match(ConI);
3388 op_cost(0);
3389 format %{ %}
3390 interface(CONST_INTER);
3391 %}
3392
3393 // Integer Immediate: 11-bit
3394 operand immI11() %{
3395 predicate(Assembler::is_simm(n->get_int(),11));
3396 match(ConI);
3397 op_cost(0);
3398 format %{ %}
3399 interface(CONST_INTER);
3400 %}
3401
3402 // Integer Immediate: 0-bit
3403 operand immI0() %{
3404 predicate(n->get_int() == 0);
3405 match(ConI);
3406 op_cost(0);
3407
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 // Integer Immediate: the value 10
3413 operand immI10() %{
3414 predicate(n->get_int() == 10);
3415 match(ConI);
3416 op_cost(0);
3417
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3421
3422 // Integer Immediate: the values 0-31
3423 operand immU5() %{
3424 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3425 match(ConI);
3426 op_cost(0);
3427
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
3432 // Integer Immediate: the values 1-31
3433 operand immI_1_31() %{
3434 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3435 match(ConI);
3436 op_cost(0);
3437
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3441
3442 // Integer Immediate: the values 32-63
3443 operand immI_32_63() %{
3444 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3445 match(ConI);
3446 op_cost(0);
3447
3448 format %{ %}
3449 interface(CONST_INTER);
3450 %}
3451
3452 // Immediates for special shifts (sign extend)
3453
3454 // Integer Immediate: the value 16
3455 operand immI_16() %{
3456 predicate(n->get_int() == 16);
3457 match(ConI);
3458 op_cost(0);
3459
3460 format %{ %}
3461 interface(CONST_INTER);
3462 %}
3463
3464 // Integer Immediate: the value 24
3465 operand immI_24() %{
3466 predicate(n->get_int() == 24);
3467 match(ConI);
3468 op_cost(0);
3469
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 // Integer Immediate: the value 255
3475 operand immI_255() %{
3476 predicate( n->get_int() == 255 );
3477 match(ConI);
3478 op_cost(0);
3479
3480 format %{ %}
3481 interface(CONST_INTER);
3482 %}
3483
3484 // Integer Immediate: the value 65535
3485 operand immI_65535() %{
3486 predicate(n->get_int() == 65535);
3487 match(ConI);
3488 op_cost(0);
3489
3490 format %{ %}
3491 interface(CONST_INTER);
3492 %}
3493
3494 // Long Immediate: the value FF
3495 operand immL_FF() %{
3496 predicate( n->get_long() == 0xFFL );
3497 match(ConL);
3498 op_cost(0);
3499
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3503
3504 // Long Immediate: the value FFFF
3505 operand immL_FFFF() %{
3506 predicate( n->get_long() == 0xFFFFL );
3507 match(ConL);
3508 op_cost(0);
3509
3510 format %{ %}
3511 interface(CONST_INTER);
3512 %}
3513
3514 // Pointer Immediate: 32 or 64-bit
3515 operand immP() %{
3516 match(ConP);
3517
3518 op_cost(5);
3519 // formats are generated automatically for constants and base registers
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3523
3524 operand immP13() %{
3525 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3526 match(ConP);
3527 op_cost(0);
3528
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 operand immP0() %{
3534 predicate(n->get_ptr() == 0);
3535 match(ConP);
3536 op_cost(0);
3537
3538 format %{ %}
3539 interface(CONST_INTER);
3540 %}
3541
3542 operand immP_poll() %{
3543 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3544 match(ConP);
3545
3546 // formats are generated automatically for constants and base registers
3547 format %{ %}
3548 interface(CONST_INTER);
3549 %}
3550
3551 // Pointer Immediate
3552 operand immN()
3553 %{
3554 match(ConN);
3555
3556 op_cost(10);
3557 format %{ %}
3558 interface(CONST_INTER);
3559 %}
3560
3561 // NULL Pointer Immediate
3562 operand immN0()
3563 %{
3564 predicate(n->get_narrowcon() == 0);
3565 match(ConN);
3566
3567 op_cost(0);
3568 format %{ %}
3569 interface(CONST_INTER);
3570 %}
3571
3572 operand immL() %{
3573 match(ConL);
3574 op_cost(40);
3575 // formats are generated automatically for constants and base registers
3576 format %{ %}
3577 interface(CONST_INTER);
3578 %}
3579
3580 operand immL0() %{
3581 predicate(n->get_long() == 0L);
3582 match(ConL);
3583 op_cost(0);
3584 // formats are generated automatically for constants and base registers
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 // Long Immediate: 13-bit
3590 operand immL13() %{
3591 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3592 match(ConL);
3593 op_cost(0);
3594
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 // Long Immediate: 13-bit minus 7
3600 operand immL13m7() %{
3601 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3602 match(ConL);
3603 op_cost(0);
3604
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 // Long Immediate: low 32-bit mask
3610 operand immL_32bits() %{
3611 predicate(n->get_long() == 0xFFFFFFFFL);
3612 match(ConL);
3613 op_cost(0);
3614
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 // Double Immediate
3620 operand immD() %{
3621 match(ConD);
3622
3623 op_cost(40);
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 operand immD0() %{
3629 #ifdef _LP64
3630 // on 64-bit architectures this comparision is faster
3631 predicate(jlong_cast(n->getd()) == 0);
3632 #else
3633 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3634 #endif
3635 match(ConD);
3636
3637 op_cost(0);
3638 format %{ %}
3639 interface(CONST_INTER);
3640 %}
3641
3642 // Float Immediate
3643 operand immF() %{
3644 match(ConF);
3645
3646 op_cost(20);
3647 format %{ %}
3648 interface(CONST_INTER);
3649 %}
3650
3651 // Float Immediate: 0
3652 operand immF0() %{
3653 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3654 match(ConF);
3655
3656 op_cost(0);
3657 format %{ %}
3658 interface(CONST_INTER);
3659 %}
3660
3661 // Integer Register Operands
3662 // Integer Register
3663 operand iRegI() %{
3664 constraint(ALLOC_IN_RC(int_reg));
3665 match(RegI);
3666
3667 match(notemp_iRegI);
3668 match(g1RegI);
3669 match(o0RegI);
3670 match(iRegIsafe);
3671
3672 format %{ %}
3673 interface(REG_INTER);
3674 %}
3675
3676 operand notemp_iRegI() %{
3677 constraint(ALLOC_IN_RC(notemp_int_reg));
3678 match(RegI);
3679
3680 match(o0RegI);
3681
3682 format %{ %}
3683 interface(REG_INTER);
3684 %}
3685
3686 operand o0RegI() %{
3687 constraint(ALLOC_IN_RC(o0_regI));
3688 match(iRegI);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 // Pointer Register
3695 operand iRegP() %{
3696 constraint(ALLOC_IN_RC(ptr_reg));
3697 match(RegP);
3698
3699 match(lock_ptr_RegP);
3700 match(g1RegP);
3701 match(g2RegP);
3702 match(g3RegP);
3703 match(g4RegP);
3704 match(i0RegP);
3705 match(o0RegP);
3706 match(o1RegP);
3707 match(l7RegP);
3708
3709 format %{ %}
3710 interface(REG_INTER);
3711 %}
3712
3713 operand sp_ptr_RegP() %{
3714 constraint(ALLOC_IN_RC(sp_ptr_reg));
3715 match(RegP);
3716 match(iRegP);
3717
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3721
3722 operand lock_ptr_RegP() %{
3723 constraint(ALLOC_IN_RC(lock_ptr_reg));
3724 match(RegP);
3725 match(i0RegP);
3726 match(o0RegP);
3727 match(o1RegP);
3728 match(l7RegP);
3729
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3733
3734 operand g1RegP() %{
3735 constraint(ALLOC_IN_RC(g1_regP));
3736 match(iRegP);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 operand g2RegP() %{
3743 constraint(ALLOC_IN_RC(g2_regP));
3744 match(iRegP);
3745
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 operand g3RegP() %{
3751 constraint(ALLOC_IN_RC(g3_regP));
3752 match(iRegP);
3753
3754 format %{ %}
3755 interface(REG_INTER);
3756 %}
3757
3758 operand g1RegI() %{
3759 constraint(ALLOC_IN_RC(g1_regI));
3760 match(iRegI);
3761
3762 format %{ %}
3763 interface(REG_INTER);
3764 %}
3765
3766 operand g3RegI() %{
3767 constraint(ALLOC_IN_RC(g3_regI));
3768 match(iRegI);
3769
3770 format %{ %}
3771 interface(REG_INTER);
3772 %}
3773
3774 operand g4RegI() %{
3775 constraint(ALLOC_IN_RC(g4_regI));
3776 match(iRegI);
3777
3778 format %{ %}
3779 interface(REG_INTER);
3780 %}
3781
3782 operand g4RegP() %{
3783 constraint(ALLOC_IN_RC(g4_regP));
3784 match(iRegP);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 operand i0RegP() %{
3791 constraint(ALLOC_IN_RC(i0_regP));
3792 match(iRegP);
3793
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3797
3798 operand o0RegP() %{
3799 constraint(ALLOC_IN_RC(o0_regP));
3800 match(iRegP);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand o1RegP() %{
3807 constraint(ALLOC_IN_RC(o1_regP));
3808 match(iRegP);
3809
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3813
3814 operand o2RegP() %{
3815 constraint(ALLOC_IN_RC(o2_regP));
3816 match(iRegP);
3817
3818 format %{ %}
3819 interface(REG_INTER);
3820 %}
3821
3822 operand o7RegP() %{
3823 constraint(ALLOC_IN_RC(o7_regP));
3824 match(iRegP);
3825
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3829
3830 operand l7RegP() %{
3831 constraint(ALLOC_IN_RC(l7_regP));
3832 match(iRegP);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand o7RegI() %{
3839 constraint(ALLOC_IN_RC(o7_regI));
3840 match(iRegI);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand iRegN() %{
3847 constraint(ALLOC_IN_RC(int_reg));
3848 match(RegN);
3849
3850 format %{ %}
3851 interface(REG_INTER);
3852 %}
3853
3854 // Long Register
3855 operand iRegL() %{
3856 constraint(ALLOC_IN_RC(long_reg));
3857 match(RegL);
3858
3859 format %{ %}
3860 interface(REG_INTER);
3861 %}
3862
3863 operand o2RegL() %{
3864 constraint(ALLOC_IN_RC(o2_regL));
3865 match(iRegL);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand o7RegL() %{
3872 constraint(ALLOC_IN_RC(o7_regL));
3873 match(iRegL);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand g1RegL() %{
3880 constraint(ALLOC_IN_RC(g1_regL));
3881 match(iRegL);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand g3RegL() %{
3888 constraint(ALLOC_IN_RC(g3_regL));
3889 match(iRegL);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 // Int Register safe
3896 // This is 64bit safe
3897 operand iRegIsafe() %{
3898 constraint(ALLOC_IN_RC(long_reg));
3899
3900 match(iRegI);
3901
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3905
3906 // Condition Code Flag Register
3907 operand flagsReg() %{
3908 constraint(ALLOC_IN_RC(int_flags));
3909 match(RegFlags);
3910
3911 format %{ "ccr" %} // both ICC and XCC
3912 interface(REG_INTER);
3913 %}
3914
3915 // Condition Code Register, unsigned comparisons.
3916 operand flagsRegU() %{
3917 constraint(ALLOC_IN_RC(int_flags));
3918 match(RegFlags);
3919
3920 format %{ "icc_U" %}
3921 interface(REG_INTER);
3922 %}
3923
3924 // Condition Code Register, pointer comparisons.
3925 operand flagsRegP() %{
3926 constraint(ALLOC_IN_RC(int_flags));
3927 match(RegFlags);
3928
3929 #ifdef _LP64
3930 format %{ "xcc_P" %}
3931 #else
3932 format %{ "icc_P" %}
3933 #endif
3934 interface(REG_INTER);
3935 %}
3936
3937 // Condition Code Register, long comparisons.
3938 operand flagsRegL() %{
3939 constraint(ALLOC_IN_RC(int_flags));
3940 match(RegFlags);
3941
3942 format %{ "xcc_L" %}
3943 interface(REG_INTER);
3944 %}
3945
3946 // Condition Code Register, floating comparisons, unordered same as "less".
3947 operand flagsRegF() %{
3948 constraint(ALLOC_IN_RC(float_flags));
3949 match(RegFlags);
3950 match(flagsRegF0);
3951
3952 format %{ %}
3953 interface(REG_INTER);
3954 %}
3955
3956 operand flagsRegF0() %{
3957 constraint(ALLOC_IN_RC(float_flag0));
3958 match(RegFlags);
3959
3960 format %{ %}
3961 interface(REG_INTER);
3962 %}
3963
3964
3965 // Condition Code Flag Register used by long compare
3966 operand flagsReg_long_LTGE() %{
3967 constraint(ALLOC_IN_RC(int_flags));
3968 match(RegFlags);
3969 format %{ "icc_LTGE" %}
3970 interface(REG_INTER);
3971 %}
3972 operand flagsReg_long_EQNE() %{
3973 constraint(ALLOC_IN_RC(int_flags));
3974 match(RegFlags);
3975 format %{ "icc_EQNE" %}
3976 interface(REG_INTER);
3977 %}
3978 operand flagsReg_long_LEGT() %{
3979 constraint(ALLOC_IN_RC(int_flags));
3980 match(RegFlags);
3981 format %{ "icc_LEGT" %}
3982 interface(REG_INTER);
3983 %}
3984
3985
3986 operand regD() %{
3987 constraint(ALLOC_IN_RC(dflt_reg));
3988 match(RegD);
3989
3990 match(regD_low);
3991
3992 format %{ %}
3993 interface(REG_INTER);
3994 %}
3995
3996 operand regF() %{
3997 constraint(ALLOC_IN_RC(sflt_reg));
3998 match(RegF);
3999
4000 format %{ %}
4001 interface(REG_INTER);
4002 %}
4003
4004 operand regD_low() %{
4005 constraint(ALLOC_IN_RC(dflt_low_reg));
4006 match(regD);
4007
4008 format %{ %}
4009 interface(REG_INTER);
4010 %}
4011
4012 // Special Registers
4013
4014 // Method Register
4015 operand inline_cache_regP(iRegP reg) %{
4016 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4017 match(reg);
4018 format %{ %}
4019 interface(REG_INTER);
4020 %}
4021
4022 operand interpreter_method_oop_regP(iRegP reg) %{
4023 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4024 match(reg);
4025 format %{ %}
4026 interface(REG_INTER);
4027 %}
4028
4029
4030 //----------Complex Operands---------------------------------------------------
4031 // Indirect Memory Reference
4032 operand indirect(sp_ptr_RegP reg) %{
4033 constraint(ALLOC_IN_RC(sp_ptr_reg));
4034 match(reg);
4035
4036 op_cost(100);
4037 format %{ "[$reg]" %}
4038 interface(MEMORY_INTER) %{
4039 base($reg);
4040 index(0x0);
4041 scale(0x0);
4042 disp(0x0);
4043 %}
4044 %}
4045
4046 // Indirect with simm13 Offset
4047 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4048 constraint(ALLOC_IN_RC(sp_ptr_reg));
4049 match(AddP reg offset);
4050
4051 op_cost(100);
4052 format %{ "[$reg + $offset]" %}
4053 interface(MEMORY_INTER) %{
4054 base($reg);
4055 index(0x0);
4056 scale(0x0);
4057 disp($offset);
4058 %}
4059 %}
4060
4061 // Indirect with simm13 Offset minus 7
4062 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4063 constraint(ALLOC_IN_RC(sp_ptr_reg));
4064 match(AddP reg offset);
4065
4066 op_cost(100);
4067 format %{ "[$reg + $offset]" %}
4068 interface(MEMORY_INTER) %{
4069 base($reg);
4070 index(0x0);
4071 scale(0x0);
4072 disp($offset);
4073 %}
4074 %}
4075
4076 // Note: Intel has a swapped version also, like this:
4077 //operand indOffsetX(iRegI reg, immP offset) %{
4078 // constraint(ALLOC_IN_RC(int_reg));
4079 // match(AddP offset reg);
4080 //
4081 // op_cost(100);
4082 // format %{ "[$reg + $offset]" %}
4083 // interface(MEMORY_INTER) %{
4084 // base($reg);
4085 // index(0x0);
4086 // scale(0x0);
4087 // disp($offset);
4088 // %}
4089 //%}
4090 //// However, it doesn't make sense for SPARC, since
4091 // we have no particularly good way to embed oops in
4092 // single instructions.
4093
4094 // Indirect with Register Index
4095 operand indIndex(iRegP addr, iRegX index) %{
4096 constraint(ALLOC_IN_RC(ptr_reg));
4097 match(AddP addr index);
4098
4099 op_cost(100);
4100 format %{ "[$addr + $index]" %}
4101 interface(MEMORY_INTER) %{
4102 base($addr);
4103 index($index);
4104 scale(0x0);
4105 disp(0x0);
4106 %}
4107 %}
4108
4109 //----------Special Memory Operands--------------------------------------------
4110 // Stack Slot Operand - This operand is used for loading and storing temporary
4111 // values on the stack where a match requires a value to
4112 // flow through memory.
4113 operand stackSlotI(sRegI reg) %{
4114 constraint(ALLOC_IN_RC(stack_slots));
4115 op_cost(100);
4116 //match(RegI);
4117 format %{ "[$reg]" %}
4118 interface(MEMORY_INTER) %{
4119 base(0xE); // R_SP
4120 index(0x0);
4121 scale(0x0);
4122 disp($reg); // Stack Offset
4123 %}
4124 %}
4125
4126 operand stackSlotP(sRegP reg) %{
4127 constraint(ALLOC_IN_RC(stack_slots));
4128 op_cost(100);
4129 //match(RegP);
4130 format %{ "[$reg]" %}
4131 interface(MEMORY_INTER) %{
4132 base(0xE); // R_SP
4133 index(0x0);
4134 scale(0x0);
4135 disp($reg); // Stack Offset
4136 %}
4137 %}
4138
4139 operand stackSlotF(sRegF reg) %{
4140 constraint(ALLOC_IN_RC(stack_slots));
4141 op_cost(100);
4142 //match(RegF);
4143 format %{ "[$reg]" %}
4144 interface(MEMORY_INTER) %{
4145 base(0xE); // R_SP
4146 index(0x0);
4147 scale(0x0);
4148 disp($reg); // Stack Offset
4149 %}
4150 %}
4151 operand stackSlotD(sRegD reg) %{
4152 constraint(ALLOC_IN_RC(stack_slots));
4153 op_cost(100);
4154 //match(RegD);
4155 format %{ "[$reg]" %}
4156 interface(MEMORY_INTER) %{
4157 base(0xE); // R_SP
4158 index(0x0);
4159 scale(0x0);
4160 disp($reg); // Stack Offset
4161 %}
4162 %}
4163 operand stackSlotL(sRegL reg) %{
4164 constraint(ALLOC_IN_RC(stack_slots));
4165 op_cost(100);
4166 //match(RegL);
4167 format %{ "[$reg]" %}
4168 interface(MEMORY_INTER) %{
4169 base(0xE); // R_SP
4170 index(0x0);
4171 scale(0x0);
4172 disp($reg); // Stack Offset
4173 %}
4174 %}
4175
4176 // Operands for expressing Control Flow
4177 // NOTE: Label is a predefined operand which should not be redefined in
4178 // the AD file. It is generically handled within the ADLC.
4179
4180 //----------Conditional Branch Operands----------------------------------------
4181 // Comparison Op - This is the operation of the comparison, and is limited to
4182 // the following set of codes:
4183 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4184 //
4185 // Other attributes of the comparison, such as unsignedness, are specified
4186 // by the comparison instruction that sets a condition code flags register.
4187 // That result is represented by a flags operand whose subtype is appropriate
4188 // to the unsignedness (etc.) of the comparison.
4189 //
4190 // Later, the instruction which matches both the Comparison Op (a Bool) and
4191 // the flags (produced by the Cmp) specifies the coding of the comparison op
4192 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4193
4194 operand cmpOp() %{
4195 match(Bool);
4196
4197 format %{ "" %}
4198 interface(COND_INTER) %{
4199 equal(0x1);
4200 not_equal(0x9);
4201 less(0x3);
4202 greater_equal(0xB);
4203 less_equal(0x2);
4204 greater(0xA);
4205 %}
4206 %}
4207
4208 // Comparison Op, unsigned
4209 operand cmpOpU() %{
4210 match(Bool);
4211
4212 format %{ "u" %}
4213 interface(COND_INTER) %{
4214 equal(0x1);
4215 not_equal(0x9);
4216 less(0x5);
4217 greater_equal(0xD);
4218 less_equal(0x4);
4219 greater(0xC);
4220 %}
4221 %}
4222
4223 // Comparison Op, pointer (same as unsigned)
4224 operand cmpOpP() %{
4225 match(Bool);
4226
4227 format %{ "p" %}
4228 interface(COND_INTER) %{
4229 equal(0x1);
4230 not_equal(0x9);
4231 less(0x5);
4232 greater_equal(0xD);
4233 less_equal(0x4);
4234 greater(0xC);
4235 %}
4236 %}
4237
4238 // Comparison Op, branch-register encoding
4239 operand cmpOp_reg() %{
4240 match(Bool);
4241
4242 format %{ "" %}
4243 interface(COND_INTER) %{
4244 equal (0x1);
4245 not_equal (0x5);
4246 less (0x3);
4247 greater_equal(0x7);
4248 less_equal (0x2);
4249 greater (0x6);
4250 %}
4251 %}
4252
4253 // Comparison Code, floating, unordered same as less
4254 operand cmpOpF() %{
4255 match(Bool);
4256
4257 format %{ "fl" %}
4258 interface(COND_INTER) %{
4259 equal(0x9);
4260 not_equal(0x1);
4261 less(0x3);
4262 greater_equal(0xB);
4263 less_equal(0xE);
4264 greater(0x6);
4265 %}
4266 %}
4267
4268 // Used by long compare
4269 operand cmpOp_commute() %{
4270 match(Bool);
4271
4272 format %{ "" %}
4273 interface(COND_INTER) %{
4274 equal(0x1);
4275 not_equal(0x9);
4276 less(0xA);
4277 greater_equal(0x2);
4278 less_equal(0xB);
4279 greater(0x3);
4280 %}
4281 %}
4282
4283 //----------OPERAND CLASSES----------------------------------------------------
4284 // Operand Classes are groups of operands that are used to simplify
4285 // instruction definitions by not requiring the AD writer to specify separate
4286 // instructions for every form of operand when the instruction accepts
4287 // multiple operand types with the same basic encoding and format. The classic
4288 // case of this is memory operands.
4289 opclass memory( indirect, indOffset13, indIndex );
4290 opclass indIndexMemory( indIndex );
4291
4292 //----------PIPELINE-----------------------------------------------------------
4293 pipeline %{
4294
4295 //----------ATTRIBUTES---------------------------------------------------------
4296 attributes %{
4297 fixed_size_instructions; // Fixed size instructions
4298 branch_has_delay_slot; // Branch has delay slot following
4299 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4300 instruction_unit_size = 4; // An instruction is 4 bytes long
4301 instruction_fetch_unit_size = 16; // The processor fetches one line
4302 instruction_fetch_units = 1; // of 16 bytes
4303
4304 // List of nop instructions
4305 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4306 %}
4307
4308 //----------RESOURCES----------------------------------------------------------
4309 // Resources are the functional units available to the machine
4310 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4311
4312 //----------PIPELINE DESCRIPTION-----------------------------------------------
4313 // Pipeline Description specifies the stages in the machine's pipeline
4314
4315 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4316
4317 //----------PIPELINE CLASSES---------------------------------------------------
4318 // Pipeline Classes describe the stages in which input and output are
4319 // referenced by the hardware pipeline.
4320
4321 // Integer ALU reg-reg operation
4322 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4323 single_instruction;
4324 dst : E(write);
4325 src1 : R(read);
4326 src2 : R(read);
4327 IALU : R;
4328 %}
4329
4330 // Integer ALU reg-reg long operation
4331 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4332 instruction_count(2);
4333 dst : E(write);
4334 src1 : R(read);
4335 src2 : R(read);
4336 IALU : R;
4337 IALU : R;
4338 %}
4339
4340 // Integer ALU reg-reg long dependent operation
4341 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4342 instruction_count(1); multiple_bundles;
4343 dst : E(write);
4344 src1 : R(read);
4345 src2 : R(read);
4346 cr : E(write);
4347 IALU : R(2);
4348 %}
4349
4350 // Integer ALU reg-imm operaion
4351 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4352 single_instruction;
4353 dst : E(write);
4354 src1 : R(read);
4355 IALU : R;
4356 %}
4357
4358 // Integer ALU reg-reg operation with condition code
4359 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4360 single_instruction;
4361 dst : E(write);
4362 cr : E(write);
4363 src1 : R(read);
4364 src2 : R(read);
4365 IALU : R;
4366 %}
4367
4368 // Integer ALU reg-imm operation with condition code
4369 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4370 single_instruction;
4371 dst : E(write);
4372 cr : E(write);
4373 src1 : R(read);
4374 IALU : R;
4375 %}
4376
4377 // Integer ALU zero-reg operation
4378 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4379 single_instruction;
4380 dst : E(write);
4381 src2 : R(read);
4382 IALU : R;
4383 %}
4384
4385 // Integer ALU zero-reg operation with condition code only
4386 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4387 single_instruction;
4388 cr : E(write);
4389 src : R(read);
4390 IALU : R;
4391 %}
4392
4393 // Integer ALU reg-reg operation with condition code only
4394 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4395 single_instruction;
4396 cr : E(write);
4397 src1 : R(read);
4398 src2 : R(read);
4399 IALU : R;
4400 %}
4401
4402 // Integer ALU reg-imm operation with condition code only
4403 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4404 single_instruction;
4405 cr : E(write);
4406 src1 : R(read);
4407 IALU : R;
4408 %}
4409
4410 // Integer ALU reg-reg-zero operation with condition code only
4411 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4412 single_instruction;
4413 cr : E(write);
4414 src1 : R(read);
4415 src2 : R(read);
4416 IALU : R;
4417 %}
4418
4419 // Integer ALU reg-imm-zero operation with condition code only
4420 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4421 single_instruction;
4422 cr : E(write);
4423 src1 : R(read);
4424 IALU : R;
4425 %}
4426
4427 // Integer ALU reg-reg operation with condition code, src1 modified
4428 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4429 single_instruction;
4430 cr : E(write);
4431 src1 : E(write);
4432 src1 : R(read);
4433 src2 : R(read);
4434 IALU : R;
4435 %}
4436
4437 // Integer ALU reg-imm operation with condition code, src1 modified
4438 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4439 single_instruction;
4440 cr : E(write);
4441 src1 : E(write);
4442 src1 : R(read);
4443 IALU : R;
4444 %}
4445
4446 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4447 multiple_bundles;
4448 dst : E(write)+4;
4449 cr : E(write);
4450 src1 : R(read);
4451 src2 : R(read);
4452 IALU : R(3);
4453 BR : R(2);
4454 %}
4455
4456 // Integer ALU operation
4457 pipe_class ialu_none(iRegI dst) %{
4458 single_instruction;
4459 dst : E(write);
4460 IALU : R;
4461 %}
4462
4463 // Integer ALU reg operation
4464 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4465 single_instruction; may_have_no_code;
4466 dst : E(write);
4467 src : R(read);
4468 IALU : R;
4469 %}
4470
4471 // Integer ALU reg conditional operation
4472 // This instruction has a 1 cycle stall, and cannot execute
4473 // in the same cycle as the instruction setting the condition
4474 // code. We kludge this by pretending to read the condition code
4475 // 1 cycle earlier, and by marking the functional units as busy
4476 // for 2 cycles with the result available 1 cycle later than
4477 // is really the case.
4478 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4479 single_instruction;
4480 op2_out : C(write);
4481 op1 : R(read);
4482 cr : R(read); // This is really E, with a 1 cycle stall
4483 BR : R(2);
4484 MS : R(2);
4485 %}
4486
4487 #ifdef _LP64
4488 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4489 instruction_count(1); multiple_bundles;
4490 dst : C(write)+1;
4491 src : R(read)+1;
4492 IALU : R(1);
4493 BR : E(2);
4494 MS : E(2);
4495 %}
4496 #endif
4497
4498 // Integer ALU reg operation
4499 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4500 single_instruction; may_have_no_code;
4501 dst : E(write);
4502 src : R(read);
4503 IALU : R;
4504 %}
4505 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4506 single_instruction; may_have_no_code;
4507 dst : E(write);
4508 src : R(read);
4509 IALU : R;
4510 %}
4511
4512 // Two integer ALU reg operations
4513 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4514 instruction_count(2);
4515 dst : E(write);
4516 src : R(read);
4517 A0 : R;
4518 A1 : R;
4519 %}
4520
4521 // Two integer ALU reg operations
4522 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4523 instruction_count(2); may_have_no_code;
4524 dst : E(write);
4525 src : R(read);
4526 A0 : R;
4527 A1 : R;
4528 %}
4529
4530 // Integer ALU imm operation
4531 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4532 single_instruction;
4533 dst : E(write);
4534 IALU : R;
4535 %}
4536
4537 // Integer ALU reg-reg with carry operation
4538 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4539 single_instruction;
4540 dst : E(write);
4541 src1 : R(read);
4542 src2 : R(read);
4543 IALU : R;
4544 %}
4545
4546 // Integer ALU cc operation
4547 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4548 single_instruction;
4549 dst : E(write);
4550 cc : R(read);
4551 IALU : R;
4552 %}
4553
4554 // Integer ALU cc / second IALU operation
4555 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4556 instruction_count(1); multiple_bundles;
4557 dst : E(write)+1;
4558 src : R(read);
4559 IALU : R;
4560 %}
4561
4562 // Integer ALU cc / second IALU operation
4563 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4564 instruction_count(1); multiple_bundles;
4565 dst : E(write)+1;
4566 p : R(read);
4567 q : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU hi-lo-reg operation
4572 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4573 instruction_count(1); multiple_bundles;
4574 dst : E(write)+1;
4575 IALU : R(2);
4576 %}
4577
4578 // Float ALU hi-lo-reg operation (with temp)
4579 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4580 instruction_count(1); multiple_bundles;
4581 dst : E(write)+1;
4582 IALU : R(2);
4583 %}
4584
4585 // Long Constant
4586 pipe_class loadConL( iRegL dst, immL src ) %{
4587 instruction_count(2); multiple_bundles;
4588 dst : E(write)+1;
4589 IALU : R(2);
4590 IALU : R(2);
4591 %}
4592
4593 // Pointer Constant
4594 pipe_class loadConP( iRegP dst, immP src ) %{
4595 instruction_count(0); multiple_bundles;
4596 fixed_latency(6);
4597 %}
4598
4599 // Polling Address
4600 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4601 #ifdef _LP64
4602 instruction_count(0); multiple_bundles;
4603 fixed_latency(6);
4604 #else
4605 dst : E(write);
4606 IALU : R;
4607 #endif
4608 %}
4609
4610 // Long Constant small
4611 pipe_class loadConLlo( iRegL dst, immL src ) %{
4612 instruction_count(2);
4613 dst : E(write);
4614 IALU : R;
4615 IALU : R;
4616 %}
4617
4618 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4619 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4620 instruction_count(1); multiple_bundles;
4621 src : R(read);
4622 dst : M(write)+1;
4623 IALU : R;
4624 MS : E;
4625 %}
4626
4627 // Integer ALU nop operation
4628 pipe_class ialu_nop() %{
4629 single_instruction;
4630 IALU : R;
4631 %}
4632
4633 // Integer ALU nop operation
4634 pipe_class ialu_nop_A0() %{
4635 single_instruction;
4636 A0 : R;
4637 %}
4638
4639 // Integer ALU nop operation
4640 pipe_class ialu_nop_A1() %{
4641 single_instruction;
4642 A1 : R;
4643 %}
4644
4645 // Integer Multiply reg-reg operation
4646 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4647 single_instruction;
4648 dst : E(write);
4649 src1 : R(read);
4650 src2 : R(read);
4651 MS : R(5);
4652 %}
4653
4654 // Integer Multiply reg-imm operation
4655 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4656 single_instruction;
4657 dst : E(write);
4658 src1 : R(read);
4659 MS : R(5);
4660 %}
4661
4662 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4663 single_instruction;
4664 dst : E(write)+4;
4665 src1 : R(read);
4666 src2 : R(read);
4667 MS : R(6);
4668 %}
4669
4670 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4671 single_instruction;
4672 dst : E(write)+4;
4673 src1 : R(read);
4674 MS : R(6);
4675 %}
4676
4677 // Integer Divide reg-reg
4678 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4679 instruction_count(1); multiple_bundles;
4680 dst : E(write);
4681 temp : E(write);
4682 src1 : R(read);
4683 src2 : R(read);
4684 temp : R(read);
4685 MS : R(38);
4686 %}
4687
4688 // Integer Divide reg-imm
4689 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4690 instruction_count(1); multiple_bundles;
4691 dst : E(write);
4692 temp : E(write);
4693 src1 : R(read);
4694 temp : R(read);
4695 MS : R(38);
4696 %}
4697
4698 // Long Divide
4699 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4700 dst : E(write)+71;
4701 src1 : R(read);
4702 src2 : R(read)+1;
4703 MS : R(70);
4704 %}
4705
4706 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4707 dst : E(write)+71;
4708 src1 : R(read);
4709 MS : R(70);
4710 %}
4711
4712 // Floating Point Add Float
4713 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4714 single_instruction;
4715 dst : X(write);
4716 src1 : E(read);
4717 src2 : E(read);
4718 FA : R;
4719 %}
4720
4721 // Floating Point Add Double
4722 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4723 single_instruction;
4724 dst : X(write);
4725 src1 : E(read);
4726 src2 : E(read);
4727 FA : R;
4728 %}
4729
4730 // Floating Point Conditional Move based on integer flags
4731 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4732 single_instruction;
4733 dst : X(write);
4734 src : E(read);
4735 cr : R(read);
4736 FA : R(2);
4737 BR : R(2);
4738 %}
4739
4740 // Floating Point Conditional Move based on integer flags
4741 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4742 single_instruction;
4743 dst : X(write);
4744 src : E(read);
4745 cr : R(read);
4746 FA : R(2);
4747 BR : R(2);
4748 %}
4749
4750 // Floating Point Multiply Float
4751 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4752 single_instruction;
4753 dst : X(write);
4754 src1 : E(read);
4755 src2 : E(read);
4756 FM : R;
4757 %}
4758
4759 // Floating Point Multiply Double
4760 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4761 single_instruction;
4762 dst : X(write);
4763 src1 : E(read);
4764 src2 : E(read);
4765 FM : R;
4766 %}
4767
4768 // Floating Point Divide Float
4769 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4770 single_instruction;
4771 dst : X(write);
4772 src1 : E(read);
4773 src2 : E(read);
4774 FM : R;
4775 FDIV : C(14);
4776 %}
4777
4778 // Floating Point Divide Double
4779 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4780 single_instruction;
4781 dst : X(write);
4782 src1 : E(read);
4783 src2 : E(read);
4784 FM : R;
4785 FDIV : C(17);
4786 %}
4787
4788 // Floating Point Move/Negate/Abs Float
4789 pipe_class faddF_reg(regF dst, regF src) %{
4790 single_instruction;
4791 dst : W(write);
4792 src : E(read);
4793 FA : R(1);
4794 %}
4795
4796 // Floating Point Move/Negate/Abs Double
4797 pipe_class faddD_reg(regD dst, regD src) %{
4798 single_instruction;
4799 dst : W(write);
4800 src : E(read);
4801 FA : R;
4802 %}
4803
4804 // Floating Point Convert F->D
4805 pipe_class fcvtF2D(regD dst, regF src) %{
4806 single_instruction;
4807 dst : X(write);
4808 src : E(read);
4809 FA : R;
4810 %}
4811
4812 // Floating Point Convert I->D
4813 pipe_class fcvtI2D(regD dst, regF src) %{
4814 single_instruction;
4815 dst : X(write);
4816 src : E(read);
4817 FA : R;
4818 %}
4819
4820 // Floating Point Convert LHi->D
4821 pipe_class fcvtLHi2D(regD dst, regD src) %{
4822 single_instruction;
4823 dst : X(write);
4824 src : E(read);
4825 FA : R;
4826 %}
4827
4828 // Floating Point Convert L->D
4829 pipe_class fcvtL2D(regD dst, regF src) %{
4830 single_instruction;
4831 dst : X(write);
4832 src : E(read);
4833 FA : R;
4834 %}
4835
4836 // Floating Point Convert L->F
4837 pipe_class fcvtL2F(regD dst, regF src) %{
4838 single_instruction;
4839 dst : X(write);
4840 src : E(read);
4841 FA : R;
4842 %}
4843
4844 // Floating Point Convert D->F
4845 pipe_class fcvtD2F(regD dst, regF src) %{
4846 single_instruction;
4847 dst : X(write);
4848 src : E(read);
4849 FA : R;
4850 %}
4851
4852 // Floating Point Convert I->L
4853 pipe_class fcvtI2L(regD dst, regF src) %{
4854 single_instruction;
4855 dst : X(write);
4856 src : E(read);
4857 FA : R;
4858 %}
4859
4860 // Floating Point Convert D->F
4861 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4862 instruction_count(1); multiple_bundles;
4863 dst : X(write)+6;
4864 src : E(read);
4865 FA : R;
4866 %}
4867
4868 // Floating Point Convert D->L
4869 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4870 instruction_count(1); multiple_bundles;
4871 dst : X(write)+6;
4872 src : E(read);
4873 FA : R;
4874 %}
4875
4876 // Floating Point Convert F->I
4877 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4878 instruction_count(1); multiple_bundles;
4879 dst : X(write)+6;
4880 src : E(read);
4881 FA : R;
4882 %}
4883
4884 // Floating Point Convert F->L
4885 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4886 instruction_count(1); multiple_bundles;
4887 dst : X(write)+6;
4888 src : E(read);
4889 FA : R;
4890 %}
4891
4892 // Floating Point Convert I->F
4893 pipe_class fcvtI2F(regF dst, regF src) %{
4894 single_instruction;
4895 dst : X(write);
4896 src : E(read);
4897 FA : R;
4898 %}
4899
4900 // Floating Point Compare
4901 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4902 single_instruction;
4903 cr : X(write);
4904 src1 : E(read);
4905 src2 : E(read);
4906 FA : R;
4907 %}
4908
4909 // Floating Point Compare
4910 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4911 single_instruction;
4912 cr : X(write);
4913 src1 : E(read);
4914 src2 : E(read);
4915 FA : R;
4916 %}
4917
4918 // Floating Add Nop
4919 pipe_class fadd_nop() %{
4920 single_instruction;
4921 FA : R;
4922 %}
4923
4924 // Integer Store to Memory
4925 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4926 single_instruction;
4927 mem : R(read);
4928 src : C(read);
4929 MS : R;
4930 %}
4931
4932 // Integer Store to Memory
4933 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4934 single_instruction;
4935 mem : R(read);
4936 src : C(read);
4937 MS : R;
4938 %}
4939
4940 // Integer Store Zero to Memory
4941 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4942 single_instruction;
4943 mem : R(read);
4944 MS : R;
4945 %}
4946
4947 // Special Stack Slot Store
4948 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4949 single_instruction;
4950 stkSlot : R(read);
4951 src : C(read);
4952 MS : R;
4953 %}
4954
4955 // Special Stack Slot Store
4956 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4957 instruction_count(2); multiple_bundles;
4958 stkSlot : R(read);
4959 src : C(read);
4960 MS : R(2);
4961 %}
4962
4963 // Float Store
4964 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4965 single_instruction;
4966 mem : R(read);
4967 src : C(read);
4968 MS : R;
4969 %}
4970
4971 // Float Store
4972 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4973 single_instruction;
4974 mem : R(read);
4975 MS : R;
4976 %}
4977
4978 // Double Store
4979 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4980 instruction_count(1);
4981 mem : R(read);
4982 src : C(read);
4983 MS : R;
4984 %}
4985
4986 // Double Store
4987 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4988 single_instruction;
4989 mem : R(read);
4990 MS : R;
4991 %}
4992
4993 // Special Stack Slot Float Store
4994 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4995 single_instruction;
4996 stkSlot : R(read);
4997 src : C(read);
4998 MS : R;
4999 %}
5000
5001 // Special Stack Slot Double Store
5002 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5003 single_instruction;
5004 stkSlot : R(read);
5005 src : C(read);
5006 MS : R;
5007 %}
5008
5009 // Integer Load (when sign bit propagation not needed)
5010 pipe_class iload_mem(iRegI dst, memory mem) %{
5011 single_instruction;
5012 mem : R(read);
5013 dst : C(write);
5014 MS : R;
5015 %}
5016
5017 // Integer Load from stack operand
5018 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5019 single_instruction;
5020 mem : R(read);
5021 dst : C(write);
5022 MS : R;
5023 %}
5024
5025 // Integer Load (when sign bit propagation or masking is needed)
5026 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5027 single_instruction;
5028 mem : R(read);
5029 dst : M(write);
5030 MS : R;
5031 %}
5032
5033 // Float Load
5034 pipe_class floadF_mem(regF dst, memory mem) %{
5035 single_instruction;
5036 mem : R(read);
5037 dst : M(write);
5038 MS : R;
5039 %}
5040
5041 // Float Load
5042 pipe_class floadD_mem(regD dst, memory mem) %{
5043 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5044 mem : R(read);
5045 dst : M(write);
5046 MS : R;
5047 %}
5048
5049 // Float Load
5050 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5051 single_instruction;
5052 stkSlot : R(read);
5053 dst : M(write);
5054 MS : R;
5055 %}
5056
5057 // Float Load
5058 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5059 single_instruction;
5060 stkSlot : R(read);
5061 dst : M(write);
5062 MS : R;
5063 %}
5064
5065 // Memory Nop
5066 pipe_class mem_nop() %{
5067 single_instruction;
5068 MS : R;
5069 %}
5070
5071 pipe_class sethi(iRegP dst, immI src) %{
5072 single_instruction;
5073 dst : E(write);
5074 IALU : R;
5075 %}
5076
5077 pipe_class loadPollP(iRegP poll) %{
5078 single_instruction;
5079 poll : R(read);
5080 MS : R;
5081 %}
5082
5083 pipe_class br(Universe br, label labl) %{
5084 single_instruction_with_delay_slot;
5085 BR : R;
5086 %}
5087
5088 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5089 single_instruction_with_delay_slot;
5090 cr : E(read);
5091 BR : R;
5092 %}
5093
5094 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5095 single_instruction_with_delay_slot;
5096 op1 : E(read);
5097 BR : R;
5098 MS : R;
5099 %}
5100
5101 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5102 single_instruction_with_delay_slot;
5103 cr : E(read);
5104 BR : R;
5105 %}
5106
5107 pipe_class br_nop() %{
5108 single_instruction;
5109 BR : R;
5110 %}
5111
5112 pipe_class simple_call(method meth) %{
5113 instruction_count(2); multiple_bundles; force_serialization;
5114 fixed_latency(100);
5115 BR : R(1);
5116 MS : R(1);
5117 A0 : R(1);
5118 %}
5119
5120 pipe_class compiled_call(method meth) %{
5121 instruction_count(1); multiple_bundles; force_serialization;
5122 fixed_latency(100);
5123 MS : R(1);
5124 %}
5125
5126 pipe_class call(method meth) %{
5127 instruction_count(0); multiple_bundles; force_serialization;
5128 fixed_latency(100);
5129 %}
5130
5131 pipe_class tail_call(Universe ignore, label labl) %{
5132 single_instruction; has_delay_slot;
5133 fixed_latency(100);
5134 BR : R(1);
5135 MS : R(1);
5136 %}
5137
5138 pipe_class ret(Universe ignore) %{
5139 single_instruction; has_delay_slot;
5140 BR : R(1);
5141 MS : R(1);
5142 %}
5143
5144 pipe_class ret_poll(g3RegP poll) %{
5145 instruction_count(3); has_delay_slot;
5146 poll : E(read);
5147 MS : R;
5148 %}
5149
5150 // The real do-nothing guy
5151 pipe_class empty( ) %{
5152 instruction_count(0);
5153 %}
5154
5155 pipe_class long_memory_op() %{
5156 instruction_count(0); multiple_bundles; force_serialization;
5157 fixed_latency(25);
5158 MS : R(1);
5159 %}
5160
5161 // Check-cast
5162 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5163 array : R(read);
5164 match : R(read);
5165 IALU : R(2);
5166 BR : R(2);
5167 MS : R;
5168 %}
5169
5170 // Convert FPU flags into +1,0,-1
5171 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5172 src1 : E(read);
5173 src2 : E(read);
5174 dst : E(write);
5175 FA : R;
5176 MS : R(2);
5177 BR : R(2);
5178 %}
5179
5180 // Compare for p < q, and conditionally add y
5181 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5182 p : E(read);
5183 q : E(read);
5184 y : E(read);
5185 IALU : R(3)
5186 %}
5187
5188 // Perform a compare, then move conditionally in a branch delay slot.
5189 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5190 src2 : E(read);
5191 srcdst : E(read);
5192 IALU : R;
5193 BR : R;
5194 %}
5195
5196 // Define the class for the Nop node
5197 define %{
5198 MachNop = ialu_nop;
5199 %}
5200
5201 %}
5202
5203 //----------INSTRUCTIONS-------------------------------------------------------
5204
5205 //------------Special Stack Slot instructions - no match rules-----------------
5206 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5207 // No match rule to avoid chain rule match.
5208 effect(DEF dst, USE src);
5209 ins_cost(MEMORY_REF_COST);
5210 size(4);
5211 format %{ "LDF $src,$dst\t! stkI to regF" %}
5212 opcode(Assembler::ldf_op3);
5213 ins_encode(simple_form3_mem_reg(src, dst));
5214 ins_pipe(floadF_stk);
5215 %}
5216
5217 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5218 // No match rule to avoid chain rule match.
5219 effect(DEF dst, USE src);
5220 ins_cost(MEMORY_REF_COST);
5221 size(4);
5222 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5223 opcode(Assembler::lddf_op3);
5224 ins_encode(simple_form3_mem_reg(src, dst));
5225 ins_pipe(floadD_stk);
5226 %}
5227
5228 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5229 // No match rule to avoid chain rule match.
5230 effect(DEF dst, USE src);
5231 ins_cost(MEMORY_REF_COST);
5232 size(4);
5233 format %{ "STF $src,$dst\t! regF to stkI" %}
5234 opcode(Assembler::stf_op3);
5235 ins_encode(simple_form3_mem_reg(dst, src));
5236 ins_pipe(fstoreF_stk_reg);
5237 %}
5238
5239 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5240 // No match rule to avoid chain rule match.
5241 effect(DEF dst, USE src);
5242 ins_cost(MEMORY_REF_COST);
5243 size(4);
5244 format %{ "STDF $src,$dst\t! regD to stkL" %}
5245 opcode(Assembler::stdf_op3);
5246 ins_encode(simple_form3_mem_reg(dst, src));
5247 ins_pipe(fstoreD_stk_reg);
5248 %}
5249
5250 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5251 effect(DEF dst, USE src);
5252 ins_cost(MEMORY_REF_COST*2);
5253 size(8);
5254 format %{ "STW $src,$dst.hi\t! long\n\t"
5255 "STW R_G0,$dst.lo" %}
5256 opcode(Assembler::stw_op3);
5257 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5258 ins_pipe(lstoreI_stk_reg);
5259 %}
5260
5261 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5262 // No match rule to avoid chain rule match.
5263 effect(DEF dst, USE src);
5264 ins_cost(MEMORY_REF_COST);
5265 size(4);
5266 format %{ "STX $src,$dst\t! regL to stkD" %}
5267 opcode(Assembler::stx_op3);
5268 ins_encode(simple_form3_mem_reg( dst, src ) );
5269 ins_pipe(istore_stk_reg);
5270 %}
5271
5272 //---------- Chain stack slots between similar types --------
5273
5274 // Load integer from stack slot
5275 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5276 match(Set dst src);
5277 ins_cost(MEMORY_REF_COST);
5278
5279 size(4);
5280 format %{ "LDUW $src,$dst\t!stk" %}
5281 opcode(Assembler::lduw_op3);
5282 ins_encode(simple_form3_mem_reg( src, dst ) );
5283 ins_pipe(iload_mem);
5284 %}
5285
5286 // Store integer to stack slot
5287 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5288 match(Set dst src);
5289 ins_cost(MEMORY_REF_COST);
5290
5291 size(4);
5292 format %{ "STW $src,$dst\t!stk" %}
5293 opcode(Assembler::stw_op3);
5294 ins_encode(simple_form3_mem_reg( dst, src ) );
5295 ins_pipe(istore_mem_reg);
5296 %}
5297
5298 // Load long from stack slot
5299 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5300 match(Set dst src);
5301
5302 ins_cost(MEMORY_REF_COST);
5303 size(4);
5304 format %{ "LDX $src,$dst\t! long" %}
5305 opcode(Assembler::ldx_op3);
5306 ins_encode(simple_form3_mem_reg( src, dst ) );
5307 ins_pipe(iload_mem);
5308 %}
5309
5310 // Store long to stack slot
5311 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5312 match(Set dst src);
5313
5314 ins_cost(MEMORY_REF_COST);
5315 size(4);
5316 format %{ "STX $src,$dst\t! long" %}
5317 opcode(Assembler::stx_op3);
5318 ins_encode(simple_form3_mem_reg( dst, src ) );
5319 ins_pipe(istore_mem_reg);
5320 %}
5321
5322 #ifdef _LP64
5323 // Load pointer from stack slot, 64-bit encoding
5324 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5325 match(Set dst src);
5326 ins_cost(MEMORY_REF_COST);
5327 size(4);
5328 format %{ "LDX $src,$dst\t!ptr" %}
5329 opcode(Assembler::ldx_op3);
5330 ins_encode(simple_form3_mem_reg( src, dst ) );
5331 ins_pipe(iload_mem);
5332 %}
5333
5334 // Store pointer to stack slot
5335 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5336 match(Set dst src);
5337 ins_cost(MEMORY_REF_COST);
5338 size(4);
5339 format %{ "STX $src,$dst\t!ptr" %}
5340 opcode(Assembler::stx_op3);
5341 ins_encode(simple_form3_mem_reg( dst, src ) );
5342 ins_pipe(istore_mem_reg);
5343 %}
5344 #else // _LP64
5345 // Load pointer from stack slot, 32-bit encoding
5346 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5347 match(Set dst src);
5348 ins_cost(MEMORY_REF_COST);
5349 format %{ "LDUW $src,$dst\t!ptr" %}
5350 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5351 ins_encode(simple_form3_mem_reg( src, dst ) );
5352 ins_pipe(iload_mem);
5353 %}
5354
5355 // Store pointer to stack slot
5356 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5357 match(Set dst src);
5358 ins_cost(MEMORY_REF_COST);
5359 format %{ "STW $src,$dst\t!ptr" %}
5360 opcode(Assembler::stw_op3, Assembler::ldst_op);
5361 ins_encode(simple_form3_mem_reg( dst, src ) );
5362 ins_pipe(istore_mem_reg);
5363 %}
5364 #endif // _LP64
5365
5366 //------------Special Nop instructions for bundling - no match rules-----------
5367 // Nop using the A0 functional unit
5368 instruct Nop_A0() %{
5369 ins_cost(0);
5370
5371 format %{ "NOP ! Alu Pipeline" %}
5372 opcode(Assembler::or_op3, Assembler::arith_op);
5373 ins_encode( form2_nop() );
5374 ins_pipe(ialu_nop_A0);
5375 %}
5376
5377 // Nop using the A1 functional unit
5378 instruct Nop_A1( ) %{
5379 ins_cost(0);
5380
5381 format %{ "NOP ! Alu Pipeline" %}
5382 opcode(Assembler::or_op3, Assembler::arith_op);
5383 ins_encode( form2_nop() );
5384 ins_pipe(ialu_nop_A1);
5385 %}
5386
5387 // Nop using the memory functional unit
5388 instruct Nop_MS( ) %{
5389 ins_cost(0);
5390
5391 format %{ "NOP ! Memory Pipeline" %}
5392 ins_encode( emit_mem_nop );
5393 ins_pipe(mem_nop);
5394 %}
5395
5396 // Nop using the floating add functional unit
5397 instruct Nop_FA( ) %{
5398 ins_cost(0);
5399
5400 format %{ "NOP ! Floating Add Pipeline" %}
5401 ins_encode( emit_fadd_nop );
5402 ins_pipe(fadd_nop);
5403 %}
5404
5405 // Nop using the branch functional unit
5406 instruct Nop_BR( ) %{
5407 ins_cost(0);
5408
5409 format %{ "NOP ! Branch Pipeline" %}
5410 ins_encode( emit_br_nop );
5411 ins_pipe(br_nop);
5412 %}
5413
5414 //----------Load/Store/Move Instructions---------------------------------------
5415 //----------Load Instructions--------------------------------------------------
5416 // Load Byte (8bit signed)
5417 instruct loadB(iRegI dst, memory mem) %{
5418 match(Set dst (LoadB mem));
5419 ins_cost(MEMORY_REF_COST);
5420
5421 size(4);
5422 format %{ "LDSB $mem,$dst\t! byte" %}
5423 ins_encode %{
5424 __ ldsb($mem$$Address, $dst$$Register);
5425 %}
5426 ins_pipe(iload_mask_mem);
5427 %}
5428
5429 // Load Byte (8bit signed) into a Long Register
5430 instruct loadB2L(iRegL dst, memory mem) %{
5431 match(Set dst (ConvI2L (LoadB mem)));
5432 ins_cost(MEMORY_REF_COST);
5433
5434 size(4);
5435 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5436 ins_encode %{
5437 __ ldsb($mem$$Address, $dst$$Register);
5438 %}
5439 ins_pipe(iload_mask_mem);
5440 %}
5441
5442 // Load Unsigned Byte (8bit UNsigned) into an int reg
5443 instruct loadUB(iRegI dst, memory mem) %{
5444 match(Set dst (LoadUB mem));
5445 ins_cost(MEMORY_REF_COST);
5446
5447 size(4);
5448 format %{ "LDUB $mem,$dst\t! ubyte" %}
5449 ins_encode %{
5450 __ ldub($mem$$Address, $dst$$Register);
5451 %}
5452 ins_pipe(iload_mem);
5453 %}
5454
5455 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5456 instruct loadUB2L(iRegL dst, memory mem) %{
5457 match(Set dst (ConvI2L (LoadUB mem)));
5458 ins_cost(MEMORY_REF_COST);
5459
5460 size(4);
5461 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5462 ins_encode %{
5463 __ ldub($mem$$Address, $dst$$Register);
5464 %}
5465 ins_pipe(iload_mem);
5466 %}
5467
5468 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5469 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5470 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5471 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5472
5473 size(2*4);
5474 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5475 "AND $dst,$mask,$dst" %}
5476 ins_encode %{
5477 __ ldub($mem$$Address, $dst$$Register);
5478 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5479 %}
5480 ins_pipe(iload_mem);
5481 %}
5482
5483 // Load Short (16bit signed)
5484 instruct loadS(iRegI dst, memory mem) %{
5485 match(Set dst (LoadS mem));
5486 ins_cost(MEMORY_REF_COST);
5487
5488 size(4);
5489 format %{ "LDSH $mem,$dst\t! short" %}
5490 ins_encode %{
5491 __ ldsh($mem$$Address, $dst$$Register);
5492 %}
5493 ins_pipe(iload_mask_mem);
5494 %}
5495
5496 // Load Short (16 bit signed) to Byte (8 bit signed)
5497 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5498 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5499 ins_cost(MEMORY_REF_COST);
5500
5501 size(4);
5502
5503 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5504 ins_encode %{
5505 __ ldsb($mem$$Address, $dst$$Register, 1);
5506 %}
5507 ins_pipe(iload_mask_mem);
5508 %}
5509
5510 // Load Short (16bit signed) into a Long Register
5511 instruct loadS2L(iRegL dst, memory mem) %{
5512 match(Set dst (ConvI2L (LoadS mem)));
5513 ins_cost(MEMORY_REF_COST);
5514
5515 size(4);
5516 format %{ "LDSH $mem,$dst\t! short -> long" %}
5517 ins_encode %{
5518 __ ldsh($mem$$Address, $dst$$Register);
5519 %}
5520 ins_pipe(iload_mask_mem);
5521 %}
5522
5523 // Load Unsigned Short/Char (16bit UNsigned)
5524 instruct loadUS(iRegI dst, memory mem) %{
5525 match(Set dst (LoadUS mem));
5526 ins_cost(MEMORY_REF_COST);
5527
5528 size(4);
5529 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5530 ins_encode %{
5531 __ lduh($mem$$Address, $dst$$Register);
5532 %}
5533 ins_pipe(iload_mem);
5534 %}
5535
5536 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5537 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5538 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5539 ins_cost(MEMORY_REF_COST);
5540
5541 size(4);
5542 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5543 ins_encode %{
5544 __ ldsb($mem$$Address, $dst$$Register, 1);
5545 %}
5546 ins_pipe(iload_mask_mem);
5547 %}
5548
5549 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5550 instruct loadUS2L(iRegL dst, memory mem) %{
5551 match(Set dst (ConvI2L (LoadUS mem)));
5552 ins_cost(MEMORY_REF_COST);
5553
5554 size(4);
5555 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5556 ins_encode %{
5557 __ lduh($mem$$Address, $dst$$Register);
5558 %}
5559 ins_pipe(iload_mem);
5560 %}
5561
5562 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5563 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5564 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5565 ins_cost(MEMORY_REF_COST);
5566
5567 size(4);
5568 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5569 ins_encode %{
5570 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5571 %}
5572 ins_pipe(iload_mem);
5573 %}
5574
5575 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5576 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5577 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5578 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5579
5580 size(2*4);
5581 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5582 "AND $dst,$mask,$dst" %}
5583 ins_encode %{
5584 Register Rdst = $dst$$Register;
5585 __ lduh($mem$$Address, Rdst);
5586 __ and3(Rdst, $mask$$constant, Rdst);
5587 %}
5588 ins_pipe(iload_mem);
5589 %}
5590
5591 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5592 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5593 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5594 effect(TEMP dst, TEMP tmp);
5595 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5596
5597 size((3+1)*4); // set may use two instructions.
5598 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5599 "SET $mask,$tmp\n\t"
5600 "AND $dst,$tmp,$dst" %}
5601 ins_encode %{
5602 Register Rdst = $dst$$Register;
5603 Register Rtmp = $tmp$$Register;
5604 __ lduh($mem$$Address, Rdst);
5605 __ set($mask$$constant, Rtmp);
5606 __ and3(Rdst, Rtmp, Rdst);
5607 %}
5608 ins_pipe(iload_mem);
5609 %}
5610
5611 // Load Integer
5612 instruct loadI(iRegI dst, memory mem) %{
5613 match(Set dst (LoadI mem));
5614 ins_cost(MEMORY_REF_COST);
5615
5616 size(4);
5617 format %{ "LDUW $mem,$dst\t! int" %}
5618 ins_encode %{
5619 __ lduw($mem$$Address, $dst$$Register);
5620 %}
5621 ins_pipe(iload_mem);
5622 %}
5623
5624 // Load Integer to Byte (8 bit signed)
5625 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5626 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5627 ins_cost(MEMORY_REF_COST);
5628
5629 size(4);
5630
5631 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5632 ins_encode %{
5633 __ ldsb($mem$$Address, $dst$$Register, 3);
5634 %}
5635 ins_pipe(iload_mask_mem);
5636 %}
5637
5638 // Load Integer to Unsigned Byte (8 bit UNsigned)
5639 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5640 match(Set dst (AndI (LoadI mem) mask));
5641 ins_cost(MEMORY_REF_COST);
5642
5643 size(4);
5644
5645 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5646 ins_encode %{
5647 __ ldub($mem$$Address, $dst$$Register, 3);
5648 %}
5649 ins_pipe(iload_mask_mem);
5650 %}
5651
5652 // Load Integer to Short (16 bit signed)
5653 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5654 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5655 ins_cost(MEMORY_REF_COST);
5656
5657 size(4);
5658
5659 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5660 ins_encode %{
5661 __ ldsh($mem$$Address, $dst$$Register, 2);
5662 %}
5663 ins_pipe(iload_mask_mem);
5664 %}
5665
5666 // Load Integer to Unsigned Short (16 bit UNsigned)
5667 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5668 match(Set dst (AndI (LoadI mem) mask));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672
5673 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5674 ins_encode %{
5675 __ lduh($mem$$Address, $dst$$Register, 2);
5676 %}
5677 ins_pipe(iload_mask_mem);
5678 %}
5679
5680 // Load Integer into a Long Register
5681 instruct loadI2L(iRegL dst, memory mem) %{
5682 match(Set dst (ConvI2L (LoadI mem)));
5683 ins_cost(MEMORY_REF_COST);
5684
5685 size(4);
5686 format %{ "LDSW $mem,$dst\t! int -> long" %}
5687 ins_encode %{
5688 __ ldsw($mem$$Address, $dst$$Register);
5689 %}
5690 ins_pipe(iload_mask_mem);
5691 %}
5692
5693 // Load Integer with mask 0xFF into a Long Register
5694 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5695 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5696 ins_cost(MEMORY_REF_COST);
5697
5698 size(4);
5699 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5700 ins_encode %{
5701 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5702 %}
5703 ins_pipe(iload_mem);
5704 %}
5705
5706 // Load Integer with mask 0xFFFF into a Long Register
5707 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5708 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5709 ins_cost(MEMORY_REF_COST);
5710
5711 size(4);
5712 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5713 ins_encode %{
5714 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5715 %}
5716 ins_pipe(iload_mem);
5717 %}
5718
5719 // Load Integer with a 13-bit mask into a Long Register
5720 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5721 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5722 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5723
5724 size(2*4);
5725 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5726 "AND $dst,$mask,$dst" %}
5727 ins_encode %{
5728 Register Rdst = $dst$$Register;
5729 __ lduw($mem$$Address, Rdst);
5730 __ and3(Rdst, $mask$$constant, Rdst);
5731 %}
5732 ins_pipe(iload_mem);
5733 %}
5734
5735 // Load Integer with a 32-bit mask into a Long Register
5736 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5737 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5738 effect(TEMP dst, TEMP tmp);
5739 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5740
5741 size((3+1)*4); // set may use two instructions.
5742 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5743 "SET $mask,$tmp\n\t"
5744 "AND $dst,$tmp,$dst" %}
5745 ins_encode %{
5746 Register Rdst = $dst$$Register;
5747 Register Rtmp = $tmp$$Register;
5748 __ lduw($mem$$Address, Rdst);
5749 __ set($mask$$constant, Rtmp);
5750 __ and3(Rdst, Rtmp, Rdst);
5751 %}
5752 ins_pipe(iload_mem);
5753 %}
5754
5755 // Load Unsigned Integer into a Long Register
5756 instruct loadUI2L(iRegL dst, memory mem) %{
5757 match(Set dst (LoadUI2L mem));
5758 ins_cost(MEMORY_REF_COST);
5759
5760 size(4);
5761 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5762 ins_encode %{
5763 __ lduw($mem$$Address, $dst$$Register);
5764 %}
5765 ins_pipe(iload_mem);
5766 %}
5767
5768 // Load Long - aligned
5769 instruct loadL(iRegL dst, memory mem ) %{
5770 match(Set dst (LoadL mem));
5771 ins_cost(MEMORY_REF_COST);
5772
5773 size(4);
5774 format %{ "LDX $mem,$dst\t! long" %}
5775 ins_encode %{
5776 __ ldx($mem$$Address, $dst$$Register);
5777 %}
5778 ins_pipe(iload_mem);
5779 %}
5780
5781 // Load Long - UNaligned
5782 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5783 match(Set dst (LoadL_unaligned mem));
5784 effect(KILL tmp);
5785 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5786 size(16);
5787 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5788 "\tLDUW $mem ,$dst\n"
5789 "\tSLLX #32, $dst, $dst\n"
5790 "\tOR $dst, R_O7, $dst" %}
5791 opcode(Assembler::lduw_op3);
5792 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Aligned Packed Byte into a Double Register
5797 instruct loadA8B(regD dst, memory mem) %{
5798 match(Set dst (Load8B mem));
5799 ins_cost(MEMORY_REF_COST);
5800 size(4);
5801 format %{ "LDDF $mem,$dst\t! packed8B" %}
5802 opcode(Assembler::lddf_op3);
5803 ins_encode(simple_form3_mem_reg( mem, dst ) );
5804 ins_pipe(floadD_mem);
5805 %}
5806
5807 // Load Aligned Packed Char into a Double Register
5808 instruct loadA4C(regD dst, memory mem) %{
5809 match(Set dst (Load4C mem));
5810 ins_cost(MEMORY_REF_COST);
5811 size(4);
5812 format %{ "LDDF $mem,$dst\t! packed4C" %}
5813 opcode(Assembler::lddf_op3);
5814 ins_encode(simple_form3_mem_reg( mem, dst ) );
5815 ins_pipe(floadD_mem);
5816 %}
5817
5818 // Load Aligned Packed Short into a Double Register
5819 instruct loadA4S(regD dst, memory mem) %{
5820 match(Set dst (Load4S mem));
5821 ins_cost(MEMORY_REF_COST);
5822 size(4);
5823 format %{ "LDDF $mem,$dst\t! packed4S" %}
5824 opcode(Assembler::lddf_op3);
5825 ins_encode(simple_form3_mem_reg( mem, dst ) );
5826 ins_pipe(floadD_mem);
5827 %}
5828
5829 // Load Aligned Packed Int into a Double Register
5830 instruct loadA2I(regD dst, memory mem) %{
5831 match(Set dst (Load2I mem));
5832 ins_cost(MEMORY_REF_COST);
5833 size(4);
5834 format %{ "LDDF $mem,$dst\t! packed2I" %}
5835 opcode(Assembler::lddf_op3);
5836 ins_encode(simple_form3_mem_reg( mem, dst ) );
5837 ins_pipe(floadD_mem);
5838 %}
5839
5840 // Load Range
5841 instruct loadRange(iRegI dst, memory mem) %{
5842 match(Set dst (LoadRange mem));
5843 ins_cost(MEMORY_REF_COST);
5844
5845 size(4);
5846 format %{ "LDUW $mem,$dst\t! range" %}
5847 opcode(Assembler::lduw_op3);
5848 ins_encode(simple_form3_mem_reg( mem, dst ) );
5849 ins_pipe(iload_mem);
5850 %}
5851
5852 // Load Integer into %f register (for fitos/fitod)
5853 instruct loadI_freg(regF dst, memory mem) %{
5854 match(Set dst (LoadI mem));
5855 ins_cost(MEMORY_REF_COST);
5856 size(4);
5857
5858 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5859 opcode(Assembler::ldf_op3);
5860 ins_encode(simple_form3_mem_reg( mem, dst ) );
5861 ins_pipe(floadF_mem);
5862 %}
5863
5864 // Load Pointer
5865 instruct loadP(iRegP dst, memory mem) %{
5866 match(Set dst (LoadP mem));
5867 ins_cost(MEMORY_REF_COST);
5868 size(4);
5869
5870 #ifndef _LP64
5871 format %{ "LDUW $mem,$dst\t! ptr" %}
5872 ins_encode %{
5873 __ lduw($mem$$Address, $dst$$Register);
5874 %}
5875 #else
5876 format %{ "LDX $mem,$dst\t! ptr" %}
5877 ins_encode %{
5878 __ ldx($mem$$Address, $dst$$Register);
5879 %}
5880 #endif
5881 ins_pipe(iload_mem);
5882 %}
5883
5884 // Load Compressed Pointer
5885 instruct loadN(iRegN dst, memory mem) %{
5886 match(Set dst (LoadN mem));
5887 ins_cost(MEMORY_REF_COST);
5888 size(4);
5889
5890 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5891 ins_encode %{
5892 __ lduw($mem$$Address, $dst$$Register);
5893 %}
5894 ins_pipe(iload_mem);
5895 %}
5896
5897 // Load Klass Pointer
5898 instruct loadKlass(iRegP dst, memory mem) %{
5899 match(Set dst (LoadKlass mem));
5900 ins_cost(MEMORY_REF_COST);
5901 size(4);
5902
5903 #ifndef _LP64
5904 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5905 ins_encode %{
5906 __ lduw($mem$$Address, $dst$$Register);
5907 %}
5908 #else
5909 format %{ "LDX $mem,$dst\t! klass ptr" %}
5910 ins_encode %{
5911 __ ldx($mem$$Address, $dst$$Register);
5912 %}
5913 #endif
5914 ins_pipe(iload_mem);
5915 %}
5916
5917 // Load narrow Klass Pointer
5918 instruct loadNKlass(iRegN dst, memory mem) %{
5919 match(Set dst (LoadNKlass mem));
5920 ins_cost(MEMORY_REF_COST);
5921 size(4);
5922
5923 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5924 ins_encode %{
5925 __ lduw($mem$$Address, $dst$$Register);
5926 %}
5927 ins_pipe(iload_mem);
5928 %}
5929
5930 // Load Double
5931 instruct loadD(regD dst, memory mem) %{
5932 match(Set dst (LoadD mem));
5933 ins_cost(MEMORY_REF_COST);
5934
5935 size(4);
5936 format %{ "LDDF $mem,$dst" %}
5937 opcode(Assembler::lddf_op3);
5938 ins_encode(simple_form3_mem_reg( mem, dst ) );
5939 ins_pipe(floadD_mem);
5940 %}
5941
5942 // Load Double - UNaligned
5943 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5944 match(Set dst (LoadD_unaligned mem));
5945 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5946 size(8);
5947 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5948 "\tLDF $mem+4,$dst.lo\t!" %}
5949 opcode(Assembler::ldf_op3);
5950 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5951 ins_pipe(iload_mem);
5952 %}
5953
5954 // Load Float
5955 instruct loadF(regF dst, memory mem) %{
5956 match(Set dst (LoadF mem));
5957 ins_cost(MEMORY_REF_COST);
5958
5959 size(4);
5960 format %{ "LDF $mem,$dst" %}
5961 opcode(Assembler::ldf_op3);
5962 ins_encode(simple_form3_mem_reg( mem, dst ) );
5963 ins_pipe(floadF_mem);
5964 %}
5965
5966 // Load Constant
5967 instruct loadConI( iRegI dst, immI src ) %{
5968 match(Set dst src);
5969 ins_cost(DEFAULT_COST * 3/2);
5970 format %{ "SET $src,$dst" %}
5971 ins_encode( Set32(src, dst) );
5972 ins_pipe(ialu_hi_lo_reg);
5973 %}
5974
5975 instruct loadConI13( iRegI dst, immI13 src ) %{
5976 match(Set dst src);
5977
5978 size(4);
5979 format %{ "MOV $src,$dst" %}
5980 ins_encode( Set13( src, dst ) );
5981 ins_pipe(ialu_imm);
5982 %}
5983
5984 instruct loadConP(iRegP dst, immP src) %{
5985 match(Set dst src);
5986 ins_cost(DEFAULT_COST * 3/2);
5987 format %{ "SET $src,$dst\t!ptr" %}
5988 // This rule does not use "expand" unlike loadConI because then
5989 // the result type is not known to be an Oop. An ADLC
5990 // enhancement will be needed to make that work - not worth it!
5991
5992 ins_encode( SetPtr( src, dst ) );
5993 ins_pipe(loadConP);
5994
5995 %}
5996
5997 instruct loadConP0(iRegP dst, immP0 src) %{
5998 match(Set dst src);
5999
6000 size(4);
6001 format %{ "CLR $dst\t!ptr" %}
6002 ins_encode( SetNull( dst ) );
6003 ins_pipe(ialu_imm);
6004 %}
6005
6006 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6007 match(Set dst src);
6008 ins_cost(DEFAULT_COST);
6009 format %{ "SET $src,$dst\t!ptr" %}
6010 ins_encode %{
6011 AddressLiteral polling_page(os::get_polling_page());
6012 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6013 %}
6014 ins_pipe(loadConP_poll);
6015 %}
6016
6017 instruct loadConN0(iRegN dst, immN0 src) %{
6018 match(Set dst src);
6019
6020 size(4);
6021 format %{ "CLR $dst\t! compressed NULL ptr" %}
6022 ins_encode( SetNull( dst ) );
6023 ins_pipe(ialu_imm);
6024 %}
6025
6026 instruct loadConN(iRegN dst, immN src) %{
6027 match(Set dst src);
6028 ins_cost(DEFAULT_COST * 3/2);
6029 format %{ "SET $src,$dst\t! compressed ptr" %}
6030 ins_encode %{
6031 Register dst = $dst$$Register;
6032 __ set_narrow_oop((jobject)$src$$constant, dst);
6033 %}
6034 ins_pipe(ialu_hi_lo_reg);
6035 %}
6036
6037 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6038 // %%% maybe this should work like loadConD
6039 match(Set dst src);
6040 effect(KILL tmp);
6041 ins_cost(DEFAULT_COST * 4);
6042 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6043 ins_encode( LdImmL(src, dst, tmp) );
6044 ins_pipe(loadConL);
6045 %}
6046
6047 instruct loadConL0( iRegL dst, immL0 src ) %{
6048 match(Set dst src);
6049 ins_cost(DEFAULT_COST);
6050 size(4);
6051 format %{ "CLR $dst\t! long" %}
6052 ins_encode( Set13( src, dst ) );
6053 ins_pipe(ialu_imm);
6054 %}
6055
6056 instruct loadConL13( iRegL dst, immL13 src ) %{
6057 match(Set dst src);
6058 ins_cost(DEFAULT_COST * 2);
6059
6060 size(4);
6061 format %{ "MOV $src,$dst\t! long" %}
6062 ins_encode( Set13( src, dst ) );
6063 ins_pipe(ialu_imm);
6064 %}
6065
6066 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6067 match(Set dst src);
6068 effect(KILL tmp);
6069
6070 #ifdef _LP64
6071 size(8*4);
6072 #else
6073 size(2*4);
6074 #endif
6075
6076 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6077 "LDF [$tmp+lo(&$src)],$dst" %}
6078 ins_encode %{
6079 address float_address = __ float_constant($src$$constant);
6080 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6081 AddressLiteral addrlit(float_address, rspec);
6082
6083 __ sethi(addrlit, $tmp$$Register);
6084 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6085 %}
6086 ins_pipe(loadConFD);
6087 %}
6088
6089 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6090 match(Set dst src);
6091 effect(KILL tmp);
6092
6093 #ifdef _LP64
6094 size(8*4);
6095 #else
6096 size(2*4);
6097 #endif
6098
6099 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6100 "LDDF [$tmp+lo(&$src)],$dst" %}
6101 ins_encode %{
6102 address double_address = __ double_constant($src$$constant);
6103 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6104 AddressLiteral addrlit(double_address, rspec);
6105
6106 __ sethi(addrlit, $tmp$$Register);
6107 // XXX This is a quick fix for 6833573.
6108 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6109 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6110 %}
6111 ins_pipe(loadConFD);
6112 %}
6113
6114 // Prefetch instructions.
6115 // Must be safe to execute with invalid address (cannot fault).
6116
6117 instruct prefetchr( memory mem ) %{
6118 match( PrefetchRead mem );
6119 ins_cost(MEMORY_REF_COST);
6120
6121 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6122 opcode(Assembler::prefetch_op3);
6123 ins_encode( form3_mem_prefetch_read( mem ) );
6124 ins_pipe(iload_mem);
6125 %}
6126
6127 instruct prefetchw( memory mem ) %{
6128 predicate(AllocatePrefetchStyle != 3 );
6129 match( PrefetchWrite mem );
6130 ins_cost(MEMORY_REF_COST);
6131
6132 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6133 opcode(Assembler::prefetch_op3);
6134 ins_encode( form3_mem_prefetch_write( mem ) );
6135 ins_pipe(iload_mem);
6136 %}
6137
6138 // Use BIS instruction to prefetch.
6139 instruct prefetchw_bis( memory mem ) %{
6140 predicate(AllocatePrefetchStyle == 3);
6141 match( PrefetchWrite mem );
6142 ins_cost(MEMORY_REF_COST);
6143
6144 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6145 ins_encode %{
6146 Register base = as_Register($mem$$base);
6147 int disp = $mem$$disp;
6148 if (disp != 0) {
6149 __ add(base, AllocatePrefetchStepSize, base);
6150 }
6151 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6152 %}
6153 ins_pipe(istore_mem_reg);
6154 %}
6155
6156 //----------Store Instructions-------------------------------------------------
6157 // Store Byte
6158 instruct storeB(memory mem, iRegI src) %{
6159 match(Set mem (StoreB mem src));
6160 ins_cost(MEMORY_REF_COST);
6161
6162 size(4);
6163 format %{ "STB $src,$mem\t! byte" %}
6164 opcode(Assembler::stb_op3);
6165 ins_encode(simple_form3_mem_reg( mem, src ) );
6166 ins_pipe(istore_mem_reg);
6167 %}
6168
6169 instruct storeB0(memory mem, immI0 src) %{
6170 match(Set mem (StoreB mem src));
6171 ins_cost(MEMORY_REF_COST);
6172
6173 size(4);
6174 format %{ "STB $src,$mem\t! byte" %}
6175 opcode(Assembler::stb_op3);
6176 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6177 ins_pipe(istore_mem_zero);
6178 %}
6179
6180 instruct storeCM0(memory mem, immI0 src) %{
6181 match(Set mem (StoreCM mem src));
6182 ins_cost(MEMORY_REF_COST);
6183
6184 size(4);
6185 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6186 opcode(Assembler::stb_op3);
6187 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6188 ins_pipe(istore_mem_zero);
6189 %}
6190
6191 // Store Char/Short
6192 instruct storeC(memory mem, iRegI src) %{
6193 match(Set mem (StoreC mem src));
6194 ins_cost(MEMORY_REF_COST);
6195
6196 size(4);
6197 format %{ "STH $src,$mem\t! short" %}
6198 opcode(Assembler::sth_op3);
6199 ins_encode(simple_form3_mem_reg( mem, src ) );
6200 ins_pipe(istore_mem_reg);
6201 %}
6202
6203 instruct storeC0(memory mem, immI0 src) %{
6204 match(Set mem (StoreC mem src));
6205 ins_cost(MEMORY_REF_COST);
6206
6207 size(4);
6208 format %{ "STH $src,$mem\t! short" %}
6209 opcode(Assembler::sth_op3);
6210 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6211 ins_pipe(istore_mem_zero);
6212 %}
6213
6214 // Store Integer
6215 instruct storeI(memory mem, iRegI src) %{
6216 match(Set mem (StoreI mem src));
6217 ins_cost(MEMORY_REF_COST);
6218
6219 size(4);
6220 format %{ "STW $src,$mem" %}
6221 opcode(Assembler::stw_op3);
6222 ins_encode(simple_form3_mem_reg( mem, src ) );
6223 ins_pipe(istore_mem_reg);
6224 %}
6225
6226 // Store Long
6227 instruct storeL(memory mem, iRegL src) %{
6228 match(Set mem (StoreL mem src));
6229 ins_cost(MEMORY_REF_COST);
6230 size(4);
6231 format %{ "STX $src,$mem\t! long" %}
6232 opcode(Assembler::stx_op3);
6233 ins_encode(simple_form3_mem_reg( mem, src ) );
6234 ins_pipe(istore_mem_reg);
6235 %}
6236
6237 instruct storeI0(memory mem, immI0 src) %{
6238 match(Set mem (StoreI mem src));
6239 ins_cost(MEMORY_REF_COST);
6240
6241 size(4);
6242 format %{ "STW $src,$mem" %}
6243 opcode(Assembler::stw_op3);
6244 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6245 ins_pipe(istore_mem_zero);
6246 %}
6247
6248 instruct storeL0(memory mem, immL0 src) %{
6249 match(Set mem (StoreL mem src));
6250 ins_cost(MEMORY_REF_COST);
6251
6252 size(4);
6253 format %{ "STX $src,$mem" %}
6254 opcode(Assembler::stx_op3);
6255 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6256 ins_pipe(istore_mem_zero);
6257 %}
6258
6259 // Store Integer from float register (used after fstoi)
6260 instruct storeI_Freg(memory mem, regF src) %{
6261 match(Set mem (StoreI mem src));
6262 ins_cost(MEMORY_REF_COST);
6263
6264 size(4);
6265 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6266 opcode(Assembler::stf_op3);
6267 ins_encode(simple_form3_mem_reg( mem, src ) );
6268 ins_pipe(fstoreF_mem_reg);
6269 %}
6270
6271 // Store Pointer
6272 instruct storeP(memory dst, sp_ptr_RegP src) %{
6273 match(Set dst (StoreP dst src));
6274 ins_cost(MEMORY_REF_COST);
6275 size(4);
6276
6277 #ifndef _LP64
6278 format %{ "STW $src,$dst\t! ptr" %}
6279 opcode(Assembler::stw_op3, 0, REGP_OP);
6280 #else
6281 format %{ "STX $src,$dst\t! ptr" %}
6282 opcode(Assembler::stx_op3, 0, REGP_OP);
6283 #endif
6284 ins_encode( form3_mem_reg( dst, src ) );
6285 ins_pipe(istore_mem_spORreg);
6286 %}
6287
6288 instruct storeP0(memory dst, immP0 src) %{
6289 match(Set dst (StoreP dst src));
6290 ins_cost(MEMORY_REF_COST);
6291 size(4);
6292
6293 #ifndef _LP64
6294 format %{ "STW $src,$dst\t! ptr" %}
6295 opcode(Assembler::stw_op3, 0, REGP_OP);
6296 #else
6297 format %{ "STX $src,$dst\t! ptr" %}
6298 opcode(Assembler::stx_op3, 0, REGP_OP);
6299 #endif
6300 ins_encode( form3_mem_reg( dst, R_G0 ) );
6301 ins_pipe(istore_mem_zero);
6302 %}
6303
6304 // Store Compressed Pointer
6305 instruct storeN(memory dst, iRegN src) %{
6306 match(Set dst (StoreN dst src));
6307 ins_cost(MEMORY_REF_COST);
6308 size(4);
6309
6310 format %{ "STW $src,$dst\t! compressed ptr" %}
6311 ins_encode %{
6312 Register base = as_Register($dst$$base);
6313 Register index = as_Register($dst$$index);
6314 Register src = $src$$Register;
6315 if (index != G0) {
6316 __ stw(src, base, index);
6317 } else {
6318 __ stw(src, base, $dst$$disp);
6319 }
6320 %}
6321 ins_pipe(istore_mem_spORreg);
6322 %}
6323
6324 instruct storeN0(memory dst, immN0 src) %{
6325 match(Set dst (StoreN dst src));
6326 ins_cost(MEMORY_REF_COST);
6327 size(4);
6328
6329 format %{ "STW $src,$dst\t! compressed ptr" %}
6330 ins_encode %{
6331 Register base = as_Register($dst$$base);
6332 Register index = as_Register($dst$$index);
6333 if (index != G0) {
6334 __ stw(0, base, index);
6335 } else {
6336 __ stw(0, base, $dst$$disp);
6337 }
6338 %}
6339 ins_pipe(istore_mem_zero);
6340 %}
6341
6342 // Store Double
6343 instruct storeD( memory mem, regD src) %{
6344 match(Set mem (StoreD mem src));
6345 ins_cost(MEMORY_REF_COST);
6346
6347 size(4);
6348 format %{ "STDF $src,$mem" %}
6349 opcode(Assembler::stdf_op3);
6350 ins_encode(simple_form3_mem_reg( mem, src ) );
6351 ins_pipe(fstoreD_mem_reg);
6352 %}
6353
6354 instruct storeD0( memory mem, immD0 src) %{
6355 match(Set mem (StoreD mem src));
6356 ins_cost(MEMORY_REF_COST);
6357
6358 size(4);
6359 format %{ "STX $src,$mem" %}
6360 opcode(Assembler::stx_op3);
6361 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6362 ins_pipe(fstoreD_mem_zero);
6363 %}
6364
6365 // Store Float
6366 instruct storeF( memory mem, regF src) %{
6367 match(Set mem (StoreF mem src));
6368 ins_cost(MEMORY_REF_COST);
6369
6370 size(4);
6371 format %{ "STF $src,$mem" %}
6372 opcode(Assembler::stf_op3);
6373 ins_encode(simple_form3_mem_reg( mem, src ) );
6374 ins_pipe(fstoreF_mem_reg);
6375 %}
6376
6377 instruct storeF0( memory mem, immF0 src) %{
6378 match(Set mem (StoreF mem src));
6379 ins_cost(MEMORY_REF_COST);
6380
6381 size(4);
6382 format %{ "STW $src,$mem\t! storeF0" %}
6383 opcode(Assembler::stw_op3);
6384 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6385 ins_pipe(fstoreF_mem_zero);
6386 %}
6387
6388 // Store Aligned Packed Bytes in Double register to memory
6389 instruct storeA8B(memory mem, regD src) %{
6390 match(Set mem (Store8B mem src));
6391 ins_cost(MEMORY_REF_COST);
6392 size(4);
6393 format %{ "STDF $src,$mem\t! packed8B" %}
6394 opcode(Assembler::stdf_op3);
6395 ins_encode(simple_form3_mem_reg( mem, src ) );
6396 ins_pipe(fstoreD_mem_reg);
6397 %}
6398
6399 // Convert oop pointer into compressed form
6400 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6401 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6402 match(Set dst (EncodeP src));
6403 format %{ "encode_heap_oop $src, $dst" %}
6404 ins_encode %{
6405 __ encode_heap_oop($src$$Register, $dst$$Register);
6406 %}
6407 ins_pipe(ialu_reg);
6408 %}
6409
6410 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6411 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6412 match(Set dst (EncodeP src));
6413 format %{ "encode_heap_oop_not_null $src, $dst" %}
6414 ins_encode %{
6415 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6416 %}
6417 ins_pipe(ialu_reg);
6418 %}
6419
6420 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6421 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6422 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6423 match(Set dst (DecodeN src));
6424 format %{ "decode_heap_oop $src, $dst" %}
6425 ins_encode %{
6426 __ decode_heap_oop($src$$Register, $dst$$Register);
6427 %}
6428 ins_pipe(ialu_reg);
6429 %}
6430
6431 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6432 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6433 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6434 match(Set dst (DecodeN src));
6435 format %{ "decode_heap_oop_not_null $src, $dst" %}
6436 ins_encode %{
6437 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6438 %}
6439 ins_pipe(ialu_reg);
6440 %}
6441
6442
6443 // Store Zero into Aligned Packed Bytes
6444 instruct storeA8B0(memory mem, immI0 zero) %{
6445 match(Set mem (Store8B mem zero));
6446 ins_cost(MEMORY_REF_COST);
6447 size(4);
6448 format %{ "STX $zero,$mem\t! packed8B" %}
6449 opcode(Assembler::stx_op3);
6450 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6451 ins_pipe(fstoreD_mem_zero);
6452 %}
6453
6454 // Store Aligned Packed Chars/Shorts in Double register to memory
6455 instruct storeA4C(memory mem, regD src) %{
6456 match(Set mem (Store4C mem src));
6457 ins_cost(MEMORY_REF_COST);
6458 size(4);
6459 format %{ "STDF $src,$mem\t! packed4C" %}
6460 opcode(Assembler::stdf_op3);
6461 ins_encode(simple_form3_mem_reg( mem, src ) );
6462 ins_pipe(fstoreD_mem_reg);
6463 %}
6464
6465 // Store Zero into Aligned Packed Chars/Shorts
6466 instruct storeA4C0(memory mem, immI0 zero) %{
6467 match(Set mem (Store4C mem (Replicate4C zero)));
6468 ins_cost(MEMORY_REF_COST);
6469 size(4);
6470 format %{ "STX $zero,$mem\t! packed4C" %}
6471 opcode(Assembler::stx_op3);
6472 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6473 ins_pipe(fstoreD_mem_zero);
6474 %}
6475
6476 // Store Aligned Packed Ints in Double register to memory
6477 instruct storeA2I(memory mem, regD src) %{
6478 match(Set mem (Store2I mem src));
6479 ins_cost(MEMORY_REF_COST);
6480 size(4);
6481 format %{ "STDF $src,$mem\t! packed2I" %}
6482 opcode(Assembler::stdf_op3);
6483 ins_encode(simple_form3_mem_reg( mem, src ) );
6484 ins_pipe(fstoreD_mem_reg);
6485 %}
6486
6487 // Store Zero into Aligned Packed Ints
6488 instruct storeA2I0(memory mem, immI0 zero) %{
6489 match(Set mem (Store2I mem zero));
6490 ins_cost(MEMORY_REF_COST);
6491 size(4);
6492 format %{ "STX $zero,$mem\t! packed2I" %}
6493 opcode(Assembler::stx_op3);
6494 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6495 ins_pipe(fstoreD_mem_zero);
6496 %}
6497
6498
6499 //----------MemBar Instructions-----------------------------------------------
6500 // Memory barrier flavors
6501
6502 instruct membar_acquire() %{
6503 match(MemBarAcquire);
6504 ins_cost(4*MEMORY_REF_COST);
6505
6506 size(0);
6507 format %{ "MEMBAR-acquire" %}
6508 ins_encode( enc_membar_acquire );
6509 ins_pipe(long_memory_op);
6510 %}
6511
6512 instruct membar_acquire_lock() %{
6513 match(MemBarAcquire);
6514 predicate(Matcher::prior_fast_lock(n));
6515 ins_cost(0);
6516
6517 size(0);
6518 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6519 ins_encode( );
6520 ins_pipe(empty);
6521 %}
6522
6523 instruct membar_release() %{
6524 match(MemBarRelease);
6525 ins_cost(4*MEMORY_REF_COST);
6526
6527 size(0);
6528 format %{ "MEMBAR-release" %}
6529 ins_encode( enc_membar_release );
6530 ins_pipe(long_memory_op);
6531 %}
6532
6533 instruct membar_release_lock() %{
6534 match(MemBarRelease);
6535 predicate(Matcher::post_fast_unlock(n));
6536 ins_cost(0);
6537
6538 size(0);
6539 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6540 ins_encode( );
6541 ins_pipe(empty);
6542 %}
6543
6544 instruct membar_volatile() %{
6545 match(MemBarVolatile);
6546 ins_cost(4*MEMORY_REF_COST);
6547
6548 size(4);
6549 format %{ "MEMBAR-volatile" %}
6550 ins_encode( enc_membar_volatile );
6551 ins_pipe(long_memory_op);
6552 %}
6553
6554 instruct unnecessary_membar_volatile() %{
6555 match(MemBarVolatile);
6556 predicate(Matcher::post_store_load_barrier(n));
6557 ins_cost(0);
6558
6559 size(0);
6560 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6561 ins_encode( );
6562 ins_pipe(empty);
6563 %}
6564
6565 //----------Register Move Instructions-----------------------------------------
6566 instruct roundDouble_nop(regD dst) %{
6567 match(Set dst (RoundDouble dst));
6568 ins_cost(0);
6569 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6570 ins_encode( );
6571 ins_pipe(empty);
6572 %}
6573
6574
6575 instruct roundFloat_nop(regF dst) %{
6576 match(Set dst (RoundFloat dst));
6577 ins_cost(0);
6578 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6579 ins_encode( );
6580 ins_pipe(empty);
6581 %}
6582
6583
6584 // Cast Index to Pointer for unsafe natives
6585 instruct castX2P(iRegX src, iRegP dst) %{
6586 match(Set dst (CastX2P src));
6587
6588 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6589 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6590 ins_pipe(ialu_reg);
6591 %}
6592
6593 // Cast Pointer to Index for unsafe natives
6594 instruct castP2X(iRegP src, iRegX dst) %{
6595 match(Set dst (CastP2X src));
6596
6597 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6598 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6599 ins_pipe(ialu_reg);
6600 %}
6601
6602 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6603 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6604 match(Set stkSlot src); // chain rule
6605 ins_cost(MEMORY_REF_COST);
6606 format %{ "STDF $src,$stkSlot\t!stk" %}
6607 opcode(Assembler::stdf_op3);
6608 ins_encode(simple_form3_mem_reg(stkSlot, src));
6609 ins_pipe(fstoreD_stk_reg);
6610 %}
6611
6612 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6613 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6614 match(Set dst stkSlot); // chain rule
6615 ins_cost(MEMORY_REF_COST);
6616 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6617 opcode(Assembler::lddf_op3);
6618 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6619 ins_pipe(floadD_stk);
6620 %}
6621
6622 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6623 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6624 match(Set stkSlot src); // chain rule
6625 ins_cost(MEMORY_REF_COST);
6626 format %{ "STF $src,$stkSlot\t!stk" %}
6627 opcode(Assembler::stf_op3);
6628 ins_encode(simple_form3_mem_reg(stkSlot, src));
6629 ins_pipe(fstoreF_stk_reg);
6630 %}
6631
6632 //----------Conditional Move---------------------------------------------------
6633 // Conditional move
6634 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6635 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6636 ins_cost(150);
6637 format %{ "MOV$cmp $pcc,$src,$dst" %}
6638 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6639 ins_pipe(ialu_reg);
6640 %}
6641
6642 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6643 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6644 ins_cost(140);
6645 format %{ "MOV$cmp $pcc,$src,$dst" %}
6646 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6647 ins_pipe(ialu_imm);
6648 %}
6649
6650 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6651 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6652 ins_cost(150);
6653 size(4);
6654 format %{ "MOV$cmp $icc,$src,$dst" %}
6655 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6656 ins_pipe(ialu_reg);
6657 %}
6658
6659 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6660 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6661 ins_cost(140);
6662 size(4);
6663 format %{ "MOV$cmp $icc,$src,$dst" %}
6664 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6665 ins_pipe(ialu_imm);
6666 %}
6667
6668 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6669 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6670 ins_cost(150);
6671 size(4);
6672 format %{ "MOV$cmp $icc,$src,$dst" %}
6673 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6674 ins_pipe(ialu_reg);
6675 %}
6676
6677 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6678 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6679 ins_cost(140);
6680 size(4);
6681 format %{ "MOV$cmp $icc,$src,$dst" %}
6682 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6683 ins_pipe(ialu_imm);
6684 %}
6685
6686 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6687 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6688 ins_cost(150);
6689 size(4);
6690 format %{ "MOV$cmp $fcc,$src,$dst" %}
6691 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6692 ins_pipe(ialu_reg);
6693 %}
6694
6695 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6696 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6697 ins_cost(140);
6698 size(4);
6699 format %{ "MOV$cmp $fcc,$src,$dst" %}
6700 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6701 ins_pipe(ialu_imm);
6702 %}
6703
6704 // Conditional move for RegN. Only cmov(reg,reg).
6705 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6706 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6707 ins_cost(150);
6708 format %{ "MOV$cmp $pcc,$src,$dst" %}
6709 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6710 ins_pipe(ialu_reg);
6711 %}
6712
6713 // This instruction also works with CmpN so we don't need cmovNN_reg.
6714 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6715 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6716 ins_cost(150);
6717 size(4);
6718 format %{ "MOV$cmp $icc,$src,$dst" %}
6719 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6720 ins_pipe(ialu_reg);
6721 %}
6722
6723 // This instruction also works with CmpN so we don't need cmovNN_reg.
6724 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6725 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6726 ins_cost(150);
6727 size(4);
6728 format %{ "MOV$cmp $icc,$src,$dst" %}
6729 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6730 ins_pipe(ialu_reg);
6731 %}
6732
6733 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6734 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6735 ins_cost(150);
6736 size(4);
6737 format %{ "MOV$cmp $fcc,$src,$dst" %}
6738 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6739 ins_pipe(ialu_reg);
6740 %}
6741
6742 // Conditional move
6743 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6744 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6745 ins_cost(150);
6746 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6747 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6748 ins_pipe(ialu_reg);
6749 %}
6750
6751 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6752 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6753 ins_cost(140);
6754 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6755 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6756 ins_pipe(ialu_imm);
6757 %}
6758
6759 // This instruction also works with CmpN so we don't need cmovPN_reg.
6760 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6761 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6762 ins_cost(150);
6763
6764 size(4);
6765 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6766 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6767 ins_pipe(ialu_reg);
6768 %}
6769
6770 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6771 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6772 ins_cost(150);
6773
6774 size(4);
6775 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6776 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6777 ins_pipe(ialu_reg);
6778 %}
6779
6780 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6781 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6782 ins_cost(140);
6783
6784 size(4);
6785 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6786 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6787 ins_pipe(ialu_imm);
6788 %}
6789
6790 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6791 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6792 ins_cost(140);
6793
6794 size(4);
6795 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6797 ins_pipe(ialu_imm);
6798 %}
6799
6800 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6801 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6802 ins_cost(150);
6803 size(4);
6804 format %{ "MOV$cmp $fcc,$src,$dst" %}
6805 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6806 ins_pipe(ialu_imm);
6807 %}
6808
6809 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6810 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6811 ins_cost(140);
6812 size(4);
6813 format %{ "MOV$cmp $fcc,$src,$dst" %}
6814 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6815 ins_pipe(ialu_imm);
6816 %}
6817
6818 // Conditional move
6819 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6820 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6821 ins_cost(150);
6822 opcode(0x101);
6823 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6824 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6825 ins_pipe(int_conditional_float_move);
6826 %}
6827
6828 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6829 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6830 ins_cost(150);
6831
6832 size(4);
6833 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6834 opcode(0x101);
6835 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6836 ins_pipe(int_conditional_float_move);
6837 %}
6838
6839 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6840 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6841 ins_cost(150);
6842
6843 size(4);
6844 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6845 opcode(0x101);
6846 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6847 ins_pipe(int_conditional_float_move);
6848 %}
6849
6850 // Conditional move,
6851 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6852 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6853 ins_cost(150);
6854 size(4);
6855 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6856 opcode(0x1);
6857 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6858 ins_pipe(int_conditional_double_move);
6859 %}
6860
6861 // Conditional move
6862 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6863 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6864 ins_cost(150);
6865 size(4);
6866 opcode(0x102);
6867 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6868 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6869 ins_pipe(int_conditional_double_move);
6870 %}
6871
6872 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6873 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6874 ins_cost(150);
6875
6876 size(4);
6877 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6878 opcode(0x102);
6879 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6880 ins_pipe(int_conditional_double_move);
6881 %}
6882
6883 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6884 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6885 ins_cost(150);
6886
6887 size(4);
6888 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6889 opcode(0x102);
6890 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6891 ins_pipe(int_conditional_double_move);
6892 %}
6893
6894 // Conditional move,
6895 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6896 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6897 ins_cost(150);
6898 size(4);
6899 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6900 opcode(0x2);
6901 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6902 ins_pipe(int_conditional_double_move);
6903 %}
6904
6905 // Conditional move
6906 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6907 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6908 ins_cost(150);
6909 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6911 ins_pipe(ialu_reg);
6912 %}
6913
6914 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6915 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6916 ins_cost(140);
6917 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6919 ins_pipe(ialu_imm);
6920 %}
6921
6922 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6923 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6924 ins_cost(150);
6925
6926 size(4);
6927 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6928 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6929 ins_pipe(ialu_reg);
6930 %}
6931
6932
6933 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6934 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6935 ins_cost(150);
6936
6937 size(4);
6938 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6939 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6940 ins_pipe(ialu_reg);
6941 %}
6942
6943
6944 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6945 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6946 ins_cost(150);
6947
6948 size(4);
6949 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6950 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6951 ins_pipe(ialu_reg);
6952 %}
6953
6954
6955
6956 //----------OS and Locking Instructions----------------------------------------
6957
6958 // This name is KNOWN by the ADLC and cannot be changed.
6959 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6960 // for this guy.
6961 instruct tlsLoadP(g2RegP dst) %{
6962 match(Set dst (ThreadLocal));
6963
6964 size(0);
6965 ins_cost(0);
6966 format %{ "# TLS is in G2" %}
6967 ins_encode( /*empty encoding*/ );
6968 ins_pipe(ialu_none);
6969 %}
6970
6971 instruct checkCastPP( iRegP dst ) %{
6972 match(Set dst (CheckCastPP dst));
6973
6974 size(0);
6975 format %{ "# checkcastPP of $dst" %}
6976 ins_encode( /*empty encoding*/ );
6977 ins_pipe(empty);
6978 %}
6979
6980
6981 instruct castPP( iRegP dst ) %{
6982 match(Set dst (CastPP dst));
6983 format %{ "# castPP of $dst" %}
6984 ins_encode( /*empty encoding*/ );
6985 ins_pipe(empty);
6986 %}
6987
6988 instruct castII( iRegI dst ) %{
6989 match(Set dst (CastII dst));
6990 format %{ "# castII of $dst" %}
6991 ins_encode( /*empty encoding*/ );
6992 ins_cost(0);
6993 ins_pipe(empty);
6994 %}
6995
6996 //----------Arithmetic Instructions--------------------------------------------
6997 // Addition Instructions
6998 // Register Addition
6999 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7000 match(Set dst (AddI src1 src2));
7001
7002 size(4);
7003 format %{ "ADD $src1,$src2,$dst" %}
7004 ins_encode %{
7005 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7006 %}
7007 ins_pipe(ialu_reg_reg);
7008 %}
7009
7010 // Immediate Addition
7011 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7012 match(Set dst (AddI src1 src2));
7013
7014 size(4);
7015 format %{ "ADD $src1,$src2,$dst" %}
7016 opcode(Assembler::add_op3, Assembler::arith_op);
7017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7018 ins_pipe(ialu_reg_imm);
7019 %}
7020
7021 // Pointer Register Addition
7022 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7023 match(Set dst (AddP src1 src2));
7024
7025 size(4);
7026 format %{ "ADD $src1,$src2,$dst" %}
7027 opcode(Assembler::add_op3, Assembler::arith_op);
7028 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7029 ins_pipe(ialu_reg_reg);
7030 %}
7031
7032 // Pointer Immediate Addition
7033 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7034 match(Set dst (AddP src1 src2));
7035
7036 size(4);
7037 format %{ "ADD $src1,$src2,$dst" %}
7038 opcode(Assembler::add_op3, Assembler::arith_op);
7039 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7040 ins_pipe(ialu_reg_imm);
7041 %}
7042
7043 // Long Addition
7044 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7045 match(Set dst (AddL src1 src2));
7046
7047 size(4);
7048 format %{ "ADD $src1,$src2,$dst\t! long" %}
7049 opcode(Assembler::add_op3, Assembler::arith_op);
7050 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7051 ins_pipe(ialu_reg_reg);
7052 %}
7053
7054 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7055 match(Set dst (AddL src1 con));
7056
7057 size(4);
7058 format %{ "ADD $src1,$con,$dst" %}
7059 opcode(Assembler::add_op3, Assembler::arith_op);
7060 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7061 ins_pipe(ialu_reg_imm);
7062 %}
7063
7064 //----------Conditional_store--------------------------------------------------
7065 // Conditional-store of the updated heap-top.
7066 // Used during allocation of the shared heap.
7067 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7068
7069 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7070 instruct loadPLocked(iRegP dst, memory mem) %{
7071 match(Set dst (LoadPLocked mem));
7072 ins_cost(MEMORY_REF_COST);
7073
7074 #ifndef _LP64
7075 size(4);
7076 format %{ "LDUW $mem,$dst\t! ptr" %}
7077 opcode(Assembler::lduw_op3, 0, REGP_OP);
7078 #else
7079 format %{ "LDX $mem,$dst\t! ptr" %}
7080 opcode(Assembler::ldx_op3, 0, REGP_OP);
7081 #endif
7082 ins_encode( form3_mem_reg( mem, dst ) );
7083 ins_pipe(iload_mem);
7084 %}
7085
7086 // LoadL-locked. Same as a regular long load when used with a compare-swap
7087 instruct loadLLocked(iRegL dst, memory mem) %{
7088 match(Set dst (LoadLLocked mem));
7089 ins_cost(MEMORY_REF_COST);
7090 size(4);
7091 format %{ "LDX $mem,$dst\t! long" %}
7092 opcode(Assembler::ldx_op3);
7093 ins_encode(simple_form3_mem_reg( mem, dst ) );
7094 ins_pipe(iload_mem);
7095 %}
7096
7097 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7098 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7099 effect( KILL newval );
7100 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7101 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7102 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7103 ins_pipe( long_memory_op );
7104 %}
7105
7106 // Conditional-store of an int value.
7107 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7108 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7109 effect( KILL newval );
7110 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7111 "CMP $oldval,$newval\t\t! See if we made progress" %}
7112 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7113 ins_pipe( long_memory_op );
7114 %}
7115
7116 // Conditional-store of a long value.
7117 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7118 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7119 effect( KILL newval );
7120 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7121 "CMP $oldval,$newval\t\t! See if we made progress" %}
7122 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7123 ins_pipe( long_memory_op );
7124 %}
7125
7126 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7127
7128 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7129 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7130 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7131 format %{
7132 "MOV $newval,O7\n\t"
7133 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7134 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7135 "MOV 1,$res\n\t"
7136 "MOVne xcc,R_G0,$res"
7137 %}
7138 ins_encode( enc_casx(mem_ptr, oldval, newval),
7139 enc_lflags_ne_to_boolean(res) );
7140 ins_pipe( long_memory_op );
7141 %}
7142
7143
7144 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7145 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7146 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7147 format %{
7148 "MOV $newval,O7\n\t"
7149 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7150 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7151 "MOV 1,$res\n\t"
7152 "MOVne icc,R_G0,$res"
7153 %}
7154 ins_encode( enc_casi(mem_ptr, oldval, newval),
7155 enc_iflags_ne_to_boolean(res) );
7156 ins_pipe( long_memory_op );
7157 %}
7158
7159 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7160 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7161 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7162 format %{
7163 "MOV $newval,O7\n\t"
7164 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7165 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7166 "MOV 1,$res\n\t"
7167 "MOVne xcc,R_G0,$res"
7168 %}
7169 #ifdef _LP64
7170 ins_encode( enc_casx(mem_ptr, oldval, newval),
7171 enc_lflags_ne_to_boolean(res) );
7172 #else
7173 ins_encode( enc_casi(mem_ptr, oldval, newval),
7174 enc_iflags_ne_to_boolean(res) );
7175 #endif
7176 ins_pipe( long_memory_op );
7177 %}
7178
7179 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7180 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7181 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7182 format %{
7183 "MOV $newval,O7\n\t"
7184 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7185 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7186 "MOV 1,$res\n\t"
7187 "MOVne icc,R_G0,$res"
7188 %}
7189 ins_encode( enc_casi(mem_ptr, oldval, newval),
7190 enc_iflags_ne_to_boolean(res) );
7191 ins_pipe( long_memory_op );
7192 %}
7193
7194 //---------------------
7195 // Subtraction Instructions
7196 // Register Subtraction
7197 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7198 match(Set dst (SubI src1 src2));
7199
7200 size(4);
7201 format %{ "SUB $src1,$src2,$dst" %}
7202 opcode(Assembler::sub_op3, Assembler::arith_op);
7203 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7204 ins_pipe(ialu_reg_reg);
7205 %}
7206
7207 // Immediate Subtraction
7208 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7209 match(Set dst (SubI src1 src2));
7210
7211 size(4);
7212 format %{ "SUB $src1,$src2,$dst" %}
7213 opcode(Assembler::sub_op3, Assembler::arith_op);
7214 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7215 ins_pipe(ialu_reg_imm);
7216 %}
7217
7218 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7219 match(Set dst (SubI zero src2));
7220
7221 size(4);
7222 format %{ "NEG $src2,$dst" %}
7223 opcode(Assembler::sub_op3, Assembler::arith_op);
7224 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7225 ins_pipe(ialu_zero_reg);
7226 %}
7227
7228 // Long subtraction
7229 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7230 match(Set dst (SubL src1 src2));
7231
7232 size(4);
7233 format %{ "SUB $src1,$src2,$dst\t! long" %}
7234 opcode(Assembler::sub_op3, Assembler::arith_op);
7235 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7236 ins_pipe(ialu_reg_reg);
7237 %}
7238
7239 // Immediate Subtraction
7240 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7241 match(Set dst (SubL src1 con));
7242
7243 size(4);
7244 format %{ "SUB $src1,$con,$dst\t! long" %}
7245 opcode(Assembler::sub_op3, Assembler::arith_op);
7246 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7247 ins_pipe(ialu_reg_imm);
7248 %}
7249
7250 // Long negation
7251 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7252 match(Set dst (SubL zero src2));
7253
7254 size(4);
7255 format %{ "NEG $src2,$dst\t! long" %}
7256 opcode(Assembler::sub_op3, Assembler::arith_op);
7257 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7258 ins_pipe(ialu_zero_reg);
7259 %}
7260
7261 // Multiplication Instructions
7262 // Integer Multiplication
7263 // Register Multiplication
7264 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7265 match(Set dst (MulI src1 src2));
7266
7267 size(4);
7268 format %{ "MULX $src1,$src2,$dst" %}
7269 opcode(Assembler::mulx_op3, Assembler::arith_op);
7270 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7271 ins_pipe(imul_reg_reg);
7272 %}
7273
7274 // Immediate Multiplication
7275 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7276 match(Set dst (MulI src1 src2));
7277
7278 size(4);
7279 format %{ "MULX $src1,$src2,$dst" %}
7280 opcode(Assembler::mulx_op3, Assembler::arith_op);
7281 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7282 ins_pipe(imul_reg_imm);
7283 %}
7284
7285 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7286 match(Set dst (MulL src1 src2));
7287 ins_cost(DEFAULT_COST * 5);
7288 size(4);
7289 format %{ "MULX $src1,$src2,$dst\t! long" %}
7290 opcode(Assembler::mulx_op3, Assembler::arith_op);
7291 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7292 ins_pipe(mulL_reg_reg);
7293 %}
7294
7295 // Immediate Multiplication
7296 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7297 match(Set dst (MulL src1 src2));
7298 ins_cost(DEFAULT_COST * 5);
7299 size(4);
7300 format %{ "MULX $src1,$src2,$dst" %}
7301 opcode(Assembler::mulx_op3, Assembler::arith_op);
7302 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7303 ins_pipe(mulL_reg_imm);
7304 %}
7305
7306 // Integer Division
7307 // Register Division
7308 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7309 match(Set dst (DivI src1 src2));
7310 ins_cost((2+71)*DEFAULT_COST);
7311
7312 format %{ "SRA $src2,0,$src2\n\t"
7313 "SRA $src1,0,$src1\n\t"
7314 "SDIVX $src1,$src2,$dst" %}
7315 ins_encode( idiv_reg( src1, src2, dst ) );
7316 ins_pipe(sdiv_reg_reg);
7317 %}
7318
7319 // Immediate Division
7320 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7321 match(Set dst (DivI src1 src2));
7322 ins_cost((2+71)*DEFAULT_COST);
7323
7324 format %{ "SRA $src1,0,$src1\n\t"
7325 "SDIVX $src1,$src2,$dst" %}
7326 ins_encode( idiv_imm( src1, src2, dst ) );
7327 ins_pipe(sdiv_reg_imm);
7328 %}
7329
7330 //----------Div-By-10-Expansion------------------------------------------------
7331 // Extract hi bits of a 32x32->64 bit multiply.
7332 // Expand rule only, not matched
7333 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7334 effect( DEF dst, USE src1, USE src2 );
7335 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7336 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7337 ins_encode( enc_mul_hi(dst,src1,src2));
7338 ins_pipe(sdiv_reg_reg);
7339 %}
7340
7341 // Magic constant, reciprocal of 10
7342 instruct loadConI_x66666667(iRegIsafe dst) %{
7343 effect( DEF dst );
7344
7345 size(8);
7346 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7347 ins_encode( Set32(0x66666667, dst) );
7348 ins_pipe(ialu_hi_lo_reg);
7349 %}
7350
7351 // Register Shift Right Arithmetic Long by 32-63
7352 instruct sra_31( iRegI dst, iRegI src ) %{
7353 effect( DEF dst, USE src );
7354 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7355 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7356 ins_pipe(ialu_reg_reg);
7357 %}
7358
7359 // Arithmetic Shift Right by 8-bit immediate
7360 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7361 effect( DEF dst, USE src );
7362 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7363 opcode(Assembler::sra_op3, Assembler::arith_op);
7364 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7365 ins_pipe(ialu_reg_imm);
7366 %}
7367
7368 // Integer DIV with 10
7369 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7370 match(Set dst (DivI src div));
7371 ins_cost((6+6)*DEFAULT_COST);
7372 expand %{
7373 iRegIsafe tmp1; // Killed temps;
7374 iRegIsafe tmp2; // Killed temps;
7375 iRegI tmp3; // Killed temps;
7376 iRegI tmp4; // Killed temps;
7377 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7378 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7379 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7380 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7381 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7382 %}
7383 %}
7384
7385 // Register Long Division
7386 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7387 match(Set dst (DivL src1 src2));
7388 ins_cost(DEFAULT_COST*71);
7389 size(4);
7390 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7391 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7392 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7393 ins_pipe(divL_reg_reg);
7394 %}
7395
7396 // Register Long Division
7397 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7398 match(Set dst (DivL src1 src2));
7399 ins_cost(DEFAULT_COST*71);
7400 size(4);
7401 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7402 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7403 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7404 ins_pipe(divL_reg_imm);
7405 %}
7406
7407 // Integer Remainder
7408 // Register Remainder
7409 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7410 match(Set dst (ModI src1 src2));
7411 effect( KILL ccr, KILL temp);
7412
7413 format %{ "SREM $src1,$src2,$dst" %}
7414 ins_encode( irem_reg(src1, src2, dst, temp) );
7415 ins_pipe(sdiv_reg_reg);
7416 %}
7417
7418 // Immediate Remainder
7419 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7420 match(Set dst (ModI src1 src2));
7421 effect( KILL ccr, KILL temp);
7422
7423 format %{ "SREM $src1,$src2,$dst" %}
7424 ins_encode( irem_imm(src1, src2, dst, temp) );
7425 ins_pipe(sdiv_reg_imm);
7426 %}
7427
7428 // Register Long Remainder
7429 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7430 effect(DEF dst, USE src1, USE src2);
7431 size(4);
7432 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7433 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7434 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7435 ins_pipe(divL_reg_reg);
7436 %}
7437
7438 // Register Long Division
7439 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7440 effect(DEF dst, USE src1, USE src2);
7441 size(4);
7442 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7443 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7444 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7445 ins_pipe(divL_reg_imm);
7446 %}
7447
7448 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7449 effect(DEF dst, USE src1, USE src2);
7450 size(4);
7451 format %{ "MULX $src1,$src2,$dst\t! long" %}
7452 opcode(Assembler::mulx_op3, Assembler::arith_op);
7453 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7454 ins_pipe(mulL_reg_reg);
7455 %}
7456
7457 // Immediate Multiplication
7458 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7459 effect(DEF dst, USE src1, USE src2);
7460 size(4);
7461 format %{ "MULX $src1,$src2,$dst" %}
7462 opcode(Assembler::mulx_op3, Assembler::arith_op);
7463 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7464 ins_pipe(mulL_reg_imm);
7465 %}
7466
7467 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7468 effect(DEF dst, USE src1, USE src2);
7469 size(4);
7470 format %{ "SUB $src1,$src2,$dst\t! long" %}
7471 opcode(Assembler::sub_op3, Assembler::arith_op);
7472 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7473 ins_pipe(ialu_reg_reg);
7474 %}
7475
7476 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7477 effect(DEF dst, USE src1, USE src2);
7478 size(4);
7479 format %{ "SUB $src1,$src2,$dst\t! long" %}
7480 opcode(Assembler::sub_op3, Assembler::arith_op);
7481 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7482 ins_pipe(ialu_reg_reg);
7483 %}
7484
7485 // Register Long Remainder
7486 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7487 match(Set dst (ModL src1 src2));
7488 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7489 expand %{
7490 iRegL tmp1;
7491 iRegL tmp2;
7492 divL_reg_reg_1(tmp1, src1, src2);
7493 mulL_reg_reg_1(tmp2, tmp1, src2);
7494 subL_reg_reg_1(dst, src1, tmp2);
7495 %}
7496 %}
7497
7498 // Register Long Remainder
7499 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7500 match(Set dst (ModL src1 src2));
7501 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7502 expand %{
7503 iRegL tmp1;
7504 iRegL tmp2;
7505 divL_reg_imm13_1(tmp1, src1, src2);
7506 mulL_reg_imm13_1(tmp2, tmp1, src2);
7507 subL_reg_reg_2 (dst, src1, tmp2);
7508 %}
7509 %}
7510
7511 // Integer Shift Instructions
7512 // Register Shift Left
7513 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7514 match(Set dst (LShiftI src1 src2));
7515
7516 size(4);
7517 format %{ "SLL $src1,$src2,$dst" %}
7518 opcode(Assembler::sll_op3, Assembler::arith_op);
7519 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7520 ins_pipe(ialu_reg_reg);
7521 %}
7522
7523 // Register Shift Left Immediate
7524 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7525 match(Set dst (LShiftI src1 src2));
7526
7527 size(4);
7528 format %{ "SLL $src1,$src2,$dst" %}
7529 opcode(Assembler::sll_op3, Assembler::arith_op);
7530 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7531 ins_pipe(ialu_reg_imm);
7532 %}
7533
7534 // Register Shift Left
7535 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7536 match(Set dst (LShiftL src1 src2));
7537
7538 size(4);
7539 format %{ "SLLX $src1,$src2,$dst" %}
7540 opcode(Assembler::sllx_op3, Assembler::arith_op);
7541 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7542 ins_pipe(ialu_reg_reg);
7543 %}
7544
7545 // Register Shift Left Immediate
7546 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7547 match(Set dst (LShiftL src1 src2));
7548
7549 size(4);
7550 format %{ "SLLX $src1,$src2,$dst" %}
7551 opcode(Assembler::sllx_op3, Assembler::arith_op);
7552 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7553 ins_pipe(ialu_reg_imm);
7554 %}
7555
7556 // Register Arithmetic Shift Right
7557 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7558 match(Set dst (RShiftI src1 src2));
7559 size(4);
7560 format %{ "SRA $src1,$src2,$dst" %}
7561 opcode(Assembler::sra_op3, Assembler::arith_op);
7562 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7563 ins_pipe(ialu_reg_reg);
7564 %}
7565
7566 // Register Arithmetic Shift Right Immediate
7567 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7568 match(Set dst (RShiftI src1 src2));
7569
7570 size(4);
7571 format %{ "SRA $src1,$src2,$dst" %}
7572 opcode(Assembler::sra_op3, Assembler::arith_op);
7573 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7574 ins_pipe(ialu_reg_imm);
7575 %}
7576
7577 // Register Shift Right Arithmatic Long
7578 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7579 match(Set dst (RShiftL src1 src2));
7580
7581 size(4);
7582 format %{ "SRAX $src1,$src2,$dst" %}
7583 opcode(Assembler::srax_op3, Assembler::arith_op);
7584 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7585 ins_pipe(ialu_reg_reg);
7586 %}
7587
7588 // Register Shift Left Immediate
7589 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7590 match(Set dst (RShiftL src1 src2));
7591
7592 size(4);
7593 format %{ "SRAX $src1,$src2,$dst" %}
7594 opcode(Assembler::srax_op3, Assembler::arith_op);
7595 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7596 ins_pipe(ialu_reg_imm);
7597 %}
7598
7599 // Register Shift Right
7600 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7601 match(Set dst (URShiftI src1 src2));
7602
7603 size(4);
7604 format %{ "SRL $src1,$src2,$dst" %}
7605 opcode(Assembler::srl_op3, Assembler::arith_op);
7606 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7607 ins_pipe(ialu_reg_reg);
7608 %}
7609
7610 // Register Shift Right Immediate
7611 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7612 match(Set dst (URShiftI src1 src2));
7613
7614 size(4);
7615 format %{ "SRL $src1,$src2,$dst" %}
7616 opcode(Assembler::srl_op3, Assembler::arith_op);
7617 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7618 ins_pipe(ialu_reg_imm);
7619 %}
7620
7621 // Register Shift Right
7622 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7623 match(Set dst (URShiftL src1 src2));
7624
7625 size(4);
7626 format %{ "SRLX $src1,$src2,$dst" %}
7627 opcode(Assembler::srlx_op3, Assembler::arith_op);
7628 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7629 ins_pipe(ialu_reg_reg);
7630 %}
7631
7632 // Register Shift Right Immediate
7633 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7634 match(Set dst (URShiftL src1 src2));
7635
7636 size(4);
7637 format %{ "SRLX $src1,$src2,$dst" %}
7638 opcode(Assembler::srlx_op3, Assembler::arith_op);
7639 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7640 ins_pipe(ialu_reg_imm);
7641 %}
7642
7643 // Register Shift Right Immediate with a CastP2X
7644 #ifdef _LP64
7645 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7646 match(Set dst (URShiftL (CastP2X src1) src2));
7647 size(4);
7648 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7649 opcode(Assembler::srlx_op3, Assembler::arith_op);
7650 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7651 ins_pipe(ialu_reg_imm);
7652 %}
7653 #else
7654 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7655 match(Set dst (URShiftI (CastP2X src1) src2));
7656 size(4);
7657 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7658 opcode(Assembler::srl_op3, Assembler::arith_op);
7659 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7660 ins_pipe(ialu_reg_imm);
7661 %}
7662 #endif
7663
7664
7665 //----------Floating Point Arithmetic Instructions-----------------------------
7666
7667 // Add float single precision
7668 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7669 match(Set dst (AddF src1 src2));
7670
7671 size(4);
7672 format %{ "FADDS $src1,$src2,$dst" %}
7673 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7674 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7675 ins_pipe(faddF_reg_reg);
7676 %}
7677
7678 // Add float double precision
7679 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7680 match(Set dst (AddD src1 src2));
7681
7682 size(4);
7683 format %{ "FADDD $src1,$src2,$dst" %}
7684 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7685 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7686 ins_pipe(faddD_reg_reg);
7687 %}
7688
7689 // Sub float single precision
7690 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7691 match(Set dst (SubF src1 src2));
7692
7693 size(4);
7694 format %{ "FSUBS $src1,$src2,$dst" %}
7695 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7696 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7697 ins_pipe(faddF_reg_reg);
7698 %}
7699
7700 // Sub float double precision
7701 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7702 match(Set dst (SubD src1 src2));
7703
7704 size(4);
7705 format %{ "FSUBD $src1,$src2,$dst" %}
7706 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7707 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7708 ins_pipe(faddD_reg_reg);
7709 %}
7710
7711 // Mul float single precision
7712 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7713 match(Set dst (MulF src1 src2));
7714
7715 size(4);
7716 format %{ "FMULS $src1,$src2,$dst" %}
7717 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7718 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7719 ins_pipe(fmulF_reg_reg);
7720 %}
7721
7722 // Mul float double precision
7723 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7724 match(Set dst (MulD src1 src2));
7725
7726 size(4);
7727 format %{ "FMULD $src1,$src2,$dst" %}
7728 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7729 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7730 ins_pipe(fmulD_reg_reg);
7731 %}
7732
7733 // Div float single precision
7734 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7735 match(Set dst (DivF src1 src2));
7736
7737 size(4);
7738 format %{ "FDIVS $src1,$src2,$dst" %}
7739 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7740 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7741 ins_pipe(fdivF_reg_reg);
7742 %}
7743
7744 // Div float double precision
7745 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7746 match(Set dst (DivD src1 src2));
7747
7748 size(4);
7749 format %{ "FDIVD $src1,$src2,$dst" %}
7750 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7751 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7752 ins_pipe(fdivD_reg_reg);
7753 %}
7754
7755 // Absolute float double precision
7756 instruct absD_reg(regD dst, regD src) %{
7757 match(Set dst (AbsD src));
7758
7759 format %{ "FABSd $src,$dst" %}
7760 ins_encode(fabsd(dst, src));
7761 ins_pipe(faddD_reg);
7762 %}
7763
7764 // Absolute float single precision
7765 instruct absF_reg(regF dst, regF src) %{
7766 match(Set dst (AbsF src));
7767
7768 format %{ "FABSs $src,$dst" %}
7769 ins_encode(fabss(dst, src));
7770 ins_pipe(faddF_reg);
7771 %}
7772
7773 instruct negF_reg(regF dst, regF src) %{
7774 match(Set dst (NegF src));
7775
7776 size(4);
7777 format %{ "FNEGs $src,$dst" %}
7778 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7779 ins_encode(form3_opf_rs2F_rdF(src, dst));
7780 ins_pipe(faddF_reg);
7781 %}
7782
7783 instruct negD_reg(regD dst, regD src) %{
7784 match(Set dst (NegD src));
7785
7786 format %{ "FNEGd $src,$dst" %}
7787 ins_encode(fnegd(dst, src));
7788 ins_pipe(faddD_reg);
7789 %}
7790
7791 // Sqrt float double precision
7792 instruct sqrtF_reg_reg(regF dst, regF src) %{
7793 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7794
7795 size(4);
7796 format %{ "FSQRTS $src,$dst" %}
7797 ins_encode(fsqrts(dst, src));
7798 ins_pipe(fdivF_reg_reg);
7799 %}
7800
7801 // Sqrt float double precision
7802 instruct sqrtD_reg_reg(regD dst, regD src) %{
7803 match(Set dst (SqrtD src));
7804
7805 size(4);
7806 format %{ "FSQRTD $src,$dst" %}
7807 ins_encode(fsqrtd(dst, src));
7808 ins_pipe(fdivD_reg_reg);
7809 %}
7810
7811 //----------Logical Instructions-----------------------------------------------
7812 // And Instructions
7813 // Register And
7814 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7815 match(Set dst (AndI src1 src2));
7816
7817 size(4);
7818 format %{ "AND $src1,$src2,$dst" %}
7819 opcode(Assembler::and_op3, Assembler::arith_op);
7820 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7821 ins_pipe(ialu_reg_reg);
7822 %}
7823
7824 // Immediate And
7825 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7826 match(Set dst (AndI src1 src2));
7827
7828 size(4);
7829 format %{ "AND $src1,$src2,$dst" %}
7830 opcode(Assembler::and_op3, Assembler::arith_op);
7831 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7832 ins_pipe(ialu_reg_imm);
7833 %}
7834
7835 // Register And Long
7836 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7837 match(Set dst (AndL src1 src2));
7838
7839 ins_cost(DEFAULT_COST);
7840 size(4);
7841 format %{ "AND $src1,$src2,$dst\t! long" %}
7842 opcode(Assembler::and_op3, Assembler::arith_op);
7843 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7844 ins_pipe(ialu_reg_reg);
7845 %}
7846
7847 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7848 match(Set dst (AndL src1 con));
7849
7850 ins_cost(DEFAULT_COST);
7851 size(4);
7852 format %{ "AND $src1,$con,$dst\t! long" %}
7853 opcode(Assembler::and_op3, Assembler::arith_op);
7854 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7855 ins_pipe(ialu_reg_imm);
7856 %}
7857
7858 // Or Instructions
7859 // Register Or
7860 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7861 match(Set dst (OrI src1 src2));
7862
7863 size(4);
7864 format %{ "OR $src1,$src2,$dst" %}
7865 opcode(Assembler::or_op3, Assembler::arith_op);
7866 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7867 ins_pipe(ialu_reg_reg);
7868 %}
7869
7870 // Immediate Or
7871 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7872 match(Set dst (OrI src1 src2));
7873
7874 size(4);
7875 format %{ "OR $src1,$src2,$dst" %}
7876 opcode(Assembler::or_op3, Assembler::arith_op);
7877 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7878 ins_pipe(ialu_reg_imm);
7879 %}
7880
7881 // Register Or Long
7882 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7883 match(Set dst (OrL src1 src2));
7884
7885 ins_cost(DEFAULT_COST);
7886 size(4);
7887 format %{ "OR $src1,$src2,$dst\t! long" %}
7888 opcode(Assembler::or_op3, Assembler::arith_op);
7889 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7890 ins_pipe(ialu_reg_reg);
7891 %}
7892
7893 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7894 match(Set dst (OrL src1 con));
7895 ins_cost(DEFAULT_COST*2);
7896
7897 ins_cost(DEFAULT_COST);
7898 size(4);
7899 format %{ "OR $src1,$con,$dst\t! long" %}
7900 opcode(Assembler::or_op3, Assembler::arith_op);
7901 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7902 ins_pipe(ialu_reg_imm);
7903 %}
7904
7905 #ifndef _LP64
7906
7907 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7908 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7909 match(Set dst (OrI src1 (CastP2X src2)));
7910
7911 size(4);
7912 format %{ "OR $src1,$src2,$dst" %}
7913 opcode(Assembler::or_op3, Assembler::arith_op);
7914 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7915 ins_pipe(ialu_reg_reg);
7916 %}
7917
7918 #else
7919
7920 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7921 match(Set dst (OrL src1 (CastP2X src2)));
7922
7923 ins_cost(DEFAULT_COST);
7924 size(4);
7925 format %{ "OR $src1,$src2,$dst\t! long" %}
7926 opcode(Assembler::or_op3, Assembler::arith_op);
7927 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7928 ins_pipe(ialu_reg_reg);
7929 %}
7930
7931 #endif
7932
7933 // Xor Instructions
7934 // Register Xor
7935 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7936 match(Set dst (XorI src1 src2));
7937
7938 size(4);
7939 format %{ "XOR $src1,$src2,$dst" %}
7940 opcode(Assembler::xor_op3, Assembler::arith_op);
7941 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7942 ins_pipe(ialu_reg_reg);
7943 %}
7944
7945 // Immediate Xor
7946 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7947 match(Set dst (XorI src1 src2));
7948
7949 size(4);
7950 format %{ "XOR $src1,$src2,$dst" %}
7951 opcode(Assembler::xor_op3, Assembler::arith_op);
7952 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7953 ins_pipe(ialu_reg_imm);
7954 %}
7955
7956 // Register Xor Long
7957 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7958 match(Set dst (XorL src1 src2));
7959
7960 ins_cost(DEFAULT_COST);
7961 size(4);
7962 format %{ "XOR $src1,$src2,$dst\t! long" %}
7963 opcode(Assembler::xor_op3, Assembler::arith_op);
7964 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7965 ins_pipe(ialu_reg_reg);
7966 %}
7967
7968 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7969 match(Set dst (XorL src1 con));
7970
7971 ins_cost(DEFAULT_COST);
7972 size(4);
7973 format %{ "XOR $src1,$con,$dst\t! long" %}
7974 opcode(Assembler::xor_op3, Assembler::arith_op);
7975 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7976 ins_pipe(ialu_reg_imm);
7977 %}
7978
7979 //----------Convert to Boolean-------------------------------------------------
7980 // Nice hack for 32-bit tests but doesn't work for
7981 // 64-bit pointers.
7982 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7983 match(Set dst (Conv2B src));
7984 effect( KILL ccr );
7985 ins_cost(DEFAULT_COST*2);
7986 format %{ "CMP R_G0,$src\n\t"
7987 "ADDX R_G0,0,$dst" %}
7988 ins_encode( enc_to_bool( src, dst ) );
7989 ins_pipe(ialu_reg_ialu);
7990 %}
7991
7992 #ifndef _LP64
7993 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7994 match(Set dst (Conv2B src));
7995 effect( KILL ccr );
7996 ins_cost(DEFAULT_COST*2);
7997 format %{ "CMP R_G0,$src\n\t"
7998 "ADDX R_G0,0,$dst" %}
7999 ins_encode( enc_to_bool( src, dst ) );
8000 ins_pipe(ialu_reg_ialu);
8001 %}
8002 #else
8003 instruct convP2B( iRegI dst, iRegP src ) %{
8004 match(Set dst (Conv2B src));
8005 ins_cost(DEFAULT_COST*2);
8006 format %{ "MOV $src,$dst\n\t"
8007 "MOVRNZ $src,1,$dst" %}
8008 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8009 ins_pipe(ialu_clr_and_mover);
8010 %}
8011 #endif
8012
8013 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8014 match(Set dst (CmpLTMask p q));
8015 effect( KILL ccr );
8016 ins_cost(DEFAULT_COST*4);
8017 format %{ "CMP $p,$q\n\t"
8018 "MOV #0,$dst\n\t"
8019 "BLT,a .+8\n\t"
8020 "MOV #-1,$dst" %}
8021 ins_encode( enc_ltmask(p,q,dst) );
8022 ins_pipe(ialu_reg_reg_ialu);
8023 %}
8024
8025 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8026 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8027 effect(KILL ccr, TEMP tmp);
8028 ins_cost(DEFAULT_COST*3);
8029
8030 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8031 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8032 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8033 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8034 ins_pipe( cadd_cmpltmask );
8035 %}
8036
8037 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8038 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
8039 effect( KILL ccr, TEMP tmp);
8040 ins_cost(DEFAULT_COST*3);
8041
8042 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8043 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8044 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8045 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8046 ins_pipe( cadd_cmpltmask );
8047 %}
8048
8049 //----------Arithmetic Conversion Instructions---------------------------------
8050 // The conversions operations are all Alpha sorted. Please keep it that way!
8051
8052 instruct convD2F_reg(regF dst, regD src) %{
8053 match(Set dst (ConvD2F src));
8054 size(4);
8055 format %{ "FDTOS $src,$dst" %}
8056 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8057 ins_encode(form3_opf_rs2D_rdF(src, dst));
8058 ins_pipe(fcvtD2F);
8059 %}
8060
8061
8062 // Convert a double to an int in a float register.
8063 // If the double is a NAN, stuff a zero in instead.
8064 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8065 effect(DEF dst, USE src, KILL fcc0);
8066 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8067 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8068 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8069 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8070 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8071 "skip:" %}
8072 ins_encode(form_d2i_helper(src,dst));
8073 ins_pipe(fcvtD2I);
8074 %}
8075
8076 instruct convD2I_reg(stackSlotI dst, regD src) %{
8077 match(Set dst (ConvD2I src));
8078 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8079 expand %{
8080 regF tmp;
8081 convD2I_helper(tmp, src);
8082 regF_to_stkI(dst, tmp);
8083 %}
8084 %}
8085
8086 // Convert a double to a long in a double register.
8087 // If the double is a NAN, stuff a zero in instead.
8088 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8089 effect(DEF dst, USE src, KILL fcc0);
8090 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8091 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8092 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8093 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8094 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8095 "skip:" %}
8096 ins_encode(form_d2l_helper(src,dst));
8097 ins_pipe(fcvtD2L);
8098 %}
8099
8100
8101 // Double to Long conversion
8102 instruct convD2L_reg(stackSlotL dst, regD src) %{
8103 match(Set dst (ConvD2L src));
8104 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8105 expand %{
8106 regD tmp;
8107 convD2L_helper(tmp, src);
8108 regD_to_stkL(dst, tmp);
8109 %}
8110 %}
8111
8112
8113 instruct convF2D_reg(regD dst, regF src) %{
8114 match(Set dst (ConvF2D src));
8115 format %{ "FSTOD $src,$dst" %}
8116 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8117 ins_encode(form3_opf_rs2F_rdD(src, dst));
8118 ins_pipe(fcvtF2D);
8119 %}
8120
8121
8122 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8123 effect(DEF dst, USE src, KILL fcc0);
8124 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8125 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8126 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8127 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8128 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8129 "skip:" %}
8130 ins_encode(form_f2i_helper(src,dst));
8131 ins_pipe(fcvtF2I);
8132 %}
8133
8134 instruct convF2I_reg(stackSlotI dst, regF src) %{
8135 match(Set dst (ConvF2I src));
8136 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8137 expand %{
8138 regF tmp;
8139 convF2I_helper(tmp, src);
8140 regF_to_stkI(dst, tmp);
8141 %}
8142 %}
8143
8144
8145 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8146 effect(DEF dst, USE src, KILL fcc0);
8147 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8148 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8149 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8150 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8151 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8152 "skip:" %}
8153 ins_encode(form_f2l_helper(src,dst));
8154 ins_pipe(fcvtF2L);
8155 %}
8156
8157 // Float to Long conversion
8158 instruct convF2L_reg(stackSlotL dst, regF src) %{
8159 match(Set dst (ConvF2L src));
8160 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8161 expand %{
8162 regD tmp;
8163 convF2L_helper(tmp, src);
8164 regD_to_stkL(dst, tmp);
8165 %}
8166 %}
8167
8168
8169 instruct convI2D_helper(regD dst, regF tmp) %{
8170 effect(USE tmp, DEF dst);
8171 format %{ "FITOD $tmp,$dst" %}
8172 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8173 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8174 ins_pipe(fcvtI2D);
8175 %}
8176
8177 instruct convI2D_reg(stackSlotI src, regD dst) %{
8178 match(Set dst (ConvI2D src));
8179 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8180 expand %{
8181 regF tmp;
8182 stkI_to_regF( tmp, src);
8183 convI2D_helper( dst, tmp);
8184 %}
8185 %}
8186
8187 instruct convI2D_mem( regD_low dst, memory mem ) %{
8188 match(Set dst (ConvI2D (LoadI mem)));
8189 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8190 size(8);
8191 format %{ "LDF $mem,$dst\n\t"
8192 "FITOD $dst,$dst" %}
8193 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8194 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8195 ins_pipe(floadF_mem);
8196 %}
8197
8198
8199 instruct convI2F_helper(regF dst, regF tmp) %{
8200 effect(DEF dst, USE tmp);
8201 format %{ "FITOS $tmp,$dst" %}
8202 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8203 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8204 ins_pipe(fcvtI2F);
8205 %}
8206
8207 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8208 match(Set dst (ConvI2F src));
8209 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8210 expand %{
8211 regF tmp;
8212 stkI_to_regF(tmp,src);
8213 convI2F_helper(dst, tmp);
8214 %}
8215 %}
8216
8217 instruct convI2F_mem( regF dst, memory mem ) %{
8218 match(Set dst (ConvI2F (LoadI mem)));
8219 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8220 size(8);
8221 format %{ "LDF $mem,$dst\n\t"
8222 "FITOS $dst,$dst" %}
8223 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8224 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8225 ins_pipe(floadF_mem);
8226 %}
8227
8228
8229 instruct convI2L_reg(iRegL dst, iRegI src) %{
8230 match(Set dst (ConvI2L src));
8231 size(4);
8232 format %{ "SRA $src,0,$dst\t! int->long" %}
8233 opcode(Assembler::sra_op3, Assembler::arith_op);
8234 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8235 ins_pipe(ialu_reg_reg);
8236 %}
8237
8238 // Zero-extend convert int to long
8239 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8240 match(Set dst (AndL (ConvI2L src) mask) );
8241 size(4);
8242 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8243 opcode(Assembler::srl_op3, Assembler::arith_op);
8244 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8245 ins_pipe(ialu_reg_reg);
8246 %}
8247
8248 // Zero-extend long
8249 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8250 match(Set dst (AndL src mask) );
8251 size(4);
8252 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8253 opcode(Assembler::srl_op3, Assembler::arith_op);
8254 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8255 ins_pipe(ialu_reg_reg);
8256 %}
8257
8258 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8259 match(Set dst (MoveF2I src));
8260 effect(DEF dst, USE src);
8261 ins_cost(MEMORY_REF_COST);
8262
8263 size(4);
8264 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8265 opcode(Assembler::lduw_op3);
8266 ins_encode(simple_form3_mem_reg( src, dst ) );
8267 ins_pipe(iload_mem);
8268 %}
8269
8270 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8271 match(Set dst (MoveI2F src));
8272 effect(DEF dst, USE src);
8273 ins_cost(MEMORY_REF_COST);
8274
8275 size(4);
8276 format %{ "LDF $src,$dst\t! MoveI2F" %}
8277 opcode(Assembler::ldf_op3);
8278 ins_encode(simple_form3_mem_reg(src, dst));
8279 ins_pipe(floadF_stk);
8280 %}
8281
8282 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8283 match(Set dst (MoveD2L src));
8284 effect(DEF dst, USE src);
8285 ins_cost(MEMORY_REF_COST);
8286
8287 size(4);
8288 format %{ "LDX $src,$dst\t! MoveD2L" %}
8289 opcode(Assembler::ldx_op3);
8290 ins_encode(simple_form3_mem_reg( src, dst ) );
8291 ins_pipe(iload_mem);
8292 %}
8293
8294 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8295 match(Set dst (MoveL2D src));
8296 effect(DEF dst, USE src);
8297 ins_cost(MEMORY_REF_COST);
8298
8299 size(4);
8300 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8301 opcode(Assembler::lddf_op3);
8302 ins_encode(simple_form3_mem_reg(src, dst));
8303 ins_pipe(floadD_stk);
8304 %}
8305
8306 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8307 match(Set dst (MoveF2I src));
8308 effect(DEF dst, USE src);
8309 ins_cost(MEMORY_REF_COST);
8310
8311 size(4);
8312 format %{ "STF $src,$dst\t!MoveF2I" %}
8313 opcode(Assembler::stf_op3);
8314 ins_encode(simple_form3_mem_reg(dst, src));
8315 ins_pipe(fstoreF_stk_reg);
8316 %}
8317
8318 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8319 match(Set dst (MoveI2F src));
8320 effect(DEF dst, USE src);
8321 ins_cost(MEMORY_REF_COST);
8322
8323 size(4);
8324 format %{ "STW $src,$dst\t!MoveI2F" %}
8325 opcode(Assembler::stw_op3);
8326 ins_encode(simple_form3_mem_reg( dst, src ) );
8327 ins_pipe(istore_mem_reg);
8328 %}
8329
8330 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8331 match(Set dst (MoveD2L src));
8332 effect(DEF dst, USE src);
8333 ins_cost(MEMORY_REF_COST);
8334
8335 size(4);
8336 format %{ "STDF $src,$dst\t!MoveD2L" %}
8337 opcode(Assembler::stdf_op3);
8338 ins_encode(simple_form3_mem_reg(dst, src));
8339 ins_pipe(fstoreD_stk_reg);
8340 %}
8341
8342 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8343 match(Set dst (MoveL2D src));
8344 effect(DEF dst, USE src);
8345 ins_cost(MEMORY_REF_COST);
8346
8347 size(4);
8348 format %{ "STX $src,$dst\t!MoveL2D" %}
8349 opcode(Assembler::stx_op3);
8350 ins_encode(simple_form3_mem_reg( dst, src ) );
8351 ins_pipe(istore_mem_reg);
8352 %}
8353
8354
8355 //-----------
8356 // Long to Double conversion using V8 opcodes.
8357 // Still useful because cheetah traps and becomes
8358 // amazingly slow for some common numbers.
8359
8360 // Magic constant, 0x43300000
8361 instruct loadConI_x43300000(iRegI dst) %{
8362 effect(DEF dst);
8363 size(4);
8364 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8365 ins_encode(SetHi22(0x43300000, dst));
8366 ins_pipe(ialu_none);
8367 %}
8368
8369 // Magic constant, 0x41f00000
8370 instruct loadConI_x41f00000(iRegI dst) %{
8371 effect(DEF dst);
8372 size(4);
8373 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8374 ins_encode(SetHi22(0x41f00000, dst));
8375 ins_pipe(ialu_none);
8376 %}
8377
8378 // Construct a double from two float halves
8379 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8380 effect(DEF dst, USE src1, USE src2);
8381 size(8);
8382 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8383 "FMOVS $src2.lo,$dst.lo" %}
8384 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8385 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8386 ins_pipe(faddD_reg_reg);
8387 %}
8388
8389 // Convert integer in high half of a double register (in the lower half of
8390 // the double register file) to double
8391 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8392 effect(DEF dst, USE src);
8393 size(4);
8394 format %{ "FITOD $src,$dst" %}
8395 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8396 ins_encode(form3_opf_rs2D_rdD(src, dst));
8397 ins_pipe(fcvtLHi2D);
8398 %}
8399
8400 // Add float double precision
8401 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8402 effect(DEF dst, USE src1, USE src2);
8403 size(4);
8404 format %{ "FADDD $src1,$src2,$dst" %}
8405 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8406 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8407 ins_pipe(faddD_reg_reg);
8408 %}
8409
8410 // Sub float double precision
8411 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8412 effect(DEF dst, USE src1, USE src2);
8413 size(4);
8414 format %{ "FSUBD $src1,$src2,$dst" %}
8415 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8416 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8417 ins_pipe(faddD_reg_reg);
8418 %}
8419
8420 // Mul float double precision
8421 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8422 effect(DEF dst, USE src1, USE src2);
8423 size(4);
8424 format %{ "FMULD $src1,$src2,$dst" %}
8425 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8426 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8427 ins_pipe(fmulD_reg_reg);
8428 %}
8429
8430 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8431 match(Set dst (ConvL2D src));
8432 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8433
8434 expand %{
8435 regD_low tmpsrc;
8436 iRegI ix43300000;
8437 iRegI ix41f00000;
8438 stackSlotL lx43300000;
8439 stackSlotL lx41f00000;
8440 regD_low dx43300000;
8441 regD dx41f00000;
8442 regD tmp1;
8443 regD_low tmp2;
8444 regD tmp3;
8445 regD tmp4;
8446
8447 stkL_to_regD(tmpsrc, src);
8448
8449 loadConI_x43300000(ix43300000);
8450 loadConI_x41f00000(ix41f00000);
8451 regI_to_stkLHi(lx43300000, ix43300000);
8452 regI_to_stkLHi(lx41f00000, ix41f00000);
8453 stkL_to_regD(dx43300000, lx43300000);
8454 stkL_to_regD(dx41f00000, lx41f00000);
8455
8456 convI2D_regDHi_regD(tmp1, tmpsrc);
8457 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8458 subD_regD_regD(tmp3, tmp2, dx43300000);
8459 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8460 addD_regD_regD(dst, tmp3, tmp4);
8461 %}
8462 %}
8463
8464 // Long to Double conversion using fast fxtof
8465 instruct convL2D_helper(regD dst, regD tmp) %{
8466 effect(DEF dst, USE tmp);
8467 size(4);
8468 format %{ "FXTOD $tmp,$dst" %}
8469 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8470 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8471 ins_pipe(fcvtL2D);
8472 %}
8473
8474 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8475 predicate(VM_Version::has_fast_fxtof());
8476 match(Set dst (ConvL2D src));
8477 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8478 expand %{
8479 regD tmp;
8480 stkL_to_regD(tmp, src);
8481 convL2D_helper(dst, tmp);
8482 %}
8483 %}
8484
8485 //-----------
8486 // Long to Float conversion using V8 opcodes.
8487 // Still useful because cheetah traps and becomes
8488 // amazingly slow for some common numbers.
8489
8490 // Long to Float conversion using fast fxtof
8491 instruct convL2F_helper(regF dst, regD tmp) %{
8492 effect(DEF dst, USE tmp);
8493 size(4);
8494 format %{ "FXTOS $tmp,$dst" %}
8495 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8496 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8497 ins_pipe(fcvtL2F);
8498 %}
8499
8500 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8501 match(Set dst (ConvL2F src));
8502 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8503 expand %{
8504 regD tmp;
8505 stkL_to_regD(tmp, src);
8506 convL2F_helper(dst, tmp);
8507 %}
8508 %}
8509 //-----------
8510
8511 instruct convL2I_reg(iRegI dst, iRegL src) %{
8512 match(Set dst (ConvL2I src));
8513 #ifndef _LP64
8514 format %{ "MOV $src.lo,$dst\t! long->int" %}
8515 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8516 ins_pipe(ialu_move_reg_I_to_L);
8517 #else
8518 size(4);
8519 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8520 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8521 ins_pipe(ialu_reg);
8522 #endif
8523 %}
8524
8525 // Register Shift Right Immediate
8526 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8527 match(Set dst (ConvL2I (RShiftL src cnt)));
8528
8529 size(4);
8530 format %{ "SRAX $src,$cnt,$dst" %}
8531 opcode(Assembler::srax_op3, Assembler::arith_op);
8532 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8533 ins_pipe(ialu_reg_imm);
8534 %}
8535
8536 // Replicate scalar to packed byte values in Double register
8537 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8538 effect(DEF dst, USE src);
8539 format %{ "SLLX $src,56,$dst\n\t"
8540 "SRLX $dst, 8,O7\n\t"
8541 "OR $dst,O7,$dst\n\t"
8542 "SRLX $dst,16,O7\n\t"
8543 "OR $dst,O7,$dst\n\t"
8544 "SRLX $dst,32,O7\n\t"
8545 "OR $dst,O7,$dst\t! replicate8B" %}
8546 ins_encode( enc_repl8b(src, dst));
8547 ins_pipe(ialu_reg);
8548 %}
8549
8550 // Replicate scalar to packed byte values in Double register
8551 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8552 match(Set dst (Replicate8B src));
8553 expand %{
8554 iRegL tmp;
8555 Repl8B_reg_helper(tmp, src);
8556 regL_to_stkD(dst, tmp);
8557 %}
8558 %}
8559
8560 // Replicate scalar constant to packed byte values in Double register
8561 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8562 match(Set dst (Replicate8B src));
8563 #ifdef _LP64
8564 size(36);
8565 #else
8566 size(8);
8567 #endif
8568 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8569 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8570 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8571 ins_pipe(loadConFD);
8572 %}
8573
8574 // Replicate scalar to packed char values into stack slot
8575 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8576 effect(DEF dst, USE src);
8577 format %{ "SLLX $src,48,$dst\n\t"
8578 "SRLX $dst,16,O7\n\t"
8579 "OR $dst,O7,$dst\n\t"
8580 "SRLX $dst,32,O7\n\t"
8581 "OR $dst,O7,$dst\t! replicate4C" %}
8582 ins_encode( enc_repl4s(src, dst) );
8583 ins_pipe(ialu_reg);
8584 %}
8585
8586 // Replicate scalar to packed char values into stack slot
8587 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8588 match(Set dst (Replicate4C src));
8589 expand %{
8590 iRegL tmp;
8591 Repl4C_reg_helper(tmp, src);
8592 regL_to_stkD(dst, tmp);
8593 %}
8594 %}
8595
8596 // Replicate scalar constant to packed char values in Double register
8597 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8598 match(Set dst (Replicate4C src));
8599 #ifdef _LP64
8600 size(36);
8601 #else
8602 size(8);
8603 #endif
8604 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8605 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8606 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8607 ins_pipe(loadConFD);
8608 %}
8609
8610 // Replicate scalar to packed short values into stack slot
8611 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8612 effect(DEF dst, USE src);
8613 format %{ "SLLX $src,48,$dst\n\t"
8614 "SRLX $dst,16,O7\n\t"
8615 "OR $dst,O7,$dst\n\t"
8616 "SRLX $dst,32,O7\n\t"
8617 "OR $dst,O7,$dst\t! replicate4S" %}
8618 ins_encode( enc_repl4s(src, dst) );
8619 ins_pipe(ialu_reg);
8620 %}
8621
8622 // Replicate scalar to packed short values into stack slot
8623 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8624 match(Set dst (Replicate4S src));
8625 expand %{
8626 iRegL tmp;
8627 Repl4S_reg_helper(tmp, src);
8628 regL_to_stkD(dst, tmp);
8629 %}
8630 %}
8631
8632 // Replicate scalar constant to packed short values in Double register
8633 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8634 match(Set dst (Replicate4S src));
8635 #ifdef _LP64
8636 size(36);
8637 #else
8638 size(8);
8639 #endif
8640 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8641 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8642 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8643 ins_pipe(loadConFD);
8644 %}
8645
8646 // Replicate scalar to packed int values in Double register
8647 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8648 effect(DEF dst, USE src);
8649 format %{ "SLLX $src,32,$dst\n\t"
8650 "SRLX $dst,32,O7\n\t"
8651 "OR $dst,O7,$dst\t! replicate2I" %}
8652 ins_encode( enc_repl2i(src, dst));
8653 ins_pipe(ialu_reg);
8654 %}
8655
8656 // Replicate scalar to packed int values in Double register
8657 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8658 match(Set dst (Replicate2I src));
8659 expand %{
8660 iRegL tmp;
8661 Repl2I_reg_helper(tmp, src);
8662 regL_to_stkD(dst, tmp);
8663 %}
8664 %}
8665
8666 // Replicate scalar zero constant to packed int values in Double register
8667 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8668 match(Set dst (Replicate2I src));
8669 #ifdef _LP64
8670 size(36);
8671 #else
8672 size(8);
8673 #endif
8674 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8675 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8676 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8677 ins_pipe(loadConFD);
8678 %}
8679
8680 //----------Control Flow Instructions------------------------------------------
8681 // Compare Instructions
8682 // Compare Integers
8683 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8684 match(Set icc (CmpI op1 op2));
8685 effect( DEF icc, USE op1, USE op2 );
8686
8687 size(4);
8688 format %{ "CMP $op1,$op2" %}
8689 opcode(Assembler::subcc_op3, Assembler::arith_op);
8690 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8691 ins_pipe(ialu_cconly_reg_reg);
8692 %}
8693
8694 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8695 match(Set icc (CmpU op1 op2));
8696
8697 size(4);
8698 format %{ "CMP $op1,$op2\t! unsigned" %}
8699 opcode(Assembler::subcc_op3, Assembler::arith_op);
8700 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8701 ins_pipe(ialu_cconly_reg_reg);
8702 %}
8703
8704 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8705 match(Set icc (CmpI op1 op2));
8706 effect( DEF icc, USE op1 );
8707
8708 size(4);
8709 format %{ "CMP $op1,$op2" %}
8710 opcode(Assembler::subcc_op3, Assembler::arith_op);
8711 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8712 ins_pipe(ialu_cconly_reg_imm);
8713 %}
8714
8715 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8716 match(Set icc (CmpI (AndI op1 op2) zero));
8717
8718 size(4);
8719 format %{ "BTST $op2,$op1" %}
8720 opcode(Assembler::andcc_op3, Assembler::arith_op);
8721 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8722 ins_pipe(ialu_cconly_reg_reg_zero);
8723 %}
8724
8725 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8726 match(Set icc (CmpI (AndI op1 op2) zero));
8727
8728 size(4);
8729 format %{ "BTST $op2,$op1" %}
8730 opcode(Assembler::andcc_op3, Assembler::arith_op);
8731 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8732 ins_pipe(ialu_cconly_reg_imm_zero);
8733 %}
8734
8735 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8736 match(Set xcc (CmpL op1 op2));
8737 effect( DEF xcc, USE op1, USE op2 );
8738
8739 size(4);
8740 format %{ "CMP $op1,$op2\t\t! long" %}
8741 opcode(Assembler::subcc_op3, Assembler::arith_op);
8742 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8743 ins_pipe(ialu_cconly_reg_reg);
8744 %}
8745
8746 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8747 match(Set xcc (CmpL op1 con));
8748 effect( DEF xcc, USE op1, USE con );
8749
8750 size(4);
8751 format %{ "CMP $op1,$con\t\t! long" %}
8752 opcode(Assembler::subcc_op3, Assembler::arith_op);
8753 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8754 ins_pipe(ialu_cconly_reg_reg);
8755 %}
8756
8757 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8758 match(Set xcc (CmpL (AndL op1 op2) zero));
8759 effect( DEF xcc, USE op1, USE op2 );
8760
8761 size(4);
8762 format %{ "BTST $op1,$op2\t\t! long" %}
8763 opcode(Assembler::andcc_op3, Assembler::arith_op);
8764 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8765 ins_pipe(ialu_cconly_reg_reg);
8766 %}
8767
8768 // useful for checking the alignment of a pointer:
8769 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8770 match(Set xcc (CmpL (AndL op1 con) zero));
8771 effect( DEF xcc, USE op1, USE con );
8772
8773 size(4);
8774 format %{ "BTST $op1,$con\t\t! long" %}
8775 opcode(Assembler::andcc_op3, Assembler::arith_op);
8776 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8777 ins_pipe(ialu_cconly_reg_reg);
8778 %}
8779
8780 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8781 match(Set icc (CmpU op1 op2));
8782
8783 size(4);
8784 format %{ "CMP $op1,$op2\t! unsigned" %}
8785 opcode(Assembler::subcc_op3, Assembler::arith_op);
8786 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8787 ins_pipe(ialu_cconly_reg_imm);
8788 %}
8789
8790 // Compare Pointers
8791 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8792 match(Set pcc (CmpP op1 op2));
8793
8794 size(4);
8795 format %{ "CMP $op1,$op2\t! ptr" %}
8796 opcode(Assembler::subcc_op3, Assembler::arith_op);
8797 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8798 ins_pipe(ialu_cconly_reg_reg);
8799 %}
8800
8801 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8802 match(Set pcc (CmpP op1 op2));
8803
8804 size(4);
8805 format %{ "CMP $op1,$op2\t! ptr" %}
8806 opcode(Assembler::subcc_op3, Assembler::arith_op);
8807 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8808 ins_pipe(ialu_cconly_reg_imm);
8809 %}
8810
8811 // Compare Narrow oops
8812 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8813 match(Set icc (CmpN op1 op2));
8814
8815 size(4);
8816 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8817 opcode(Assembler::subcc_op3, Assembler::arith_op);
8818 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8819 ins_pipe(ialu_cconly_reg_reg);
8820 %}
8821
8822 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8823 match(Set icc (CmpN op1 op2));
8824
8825 size(4);
8826 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8827 opcode(Assembler::subcc_op3, Assembler::arith_op);
8828 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8829 ins_pipe(ialu_cconly_reg_imm);
8830 %}
8831
8832 //----------Max and Min--------------------------------------------------------
8833 // Min Instructions
8834 // Conditional move for min
8835 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8836 effect( USE_DEF op2, USE op1, USE icc );
8837
8838 size(4);
8839 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8840 opcode(Assembler::less);
8841 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8842 ins_pipe(ialu_reg_flags);
8843 %}
8844
8845 // Min Register with Register.
8846 instruct minI_eReg(iRegI op1, iRegI op2) %{
8847 match(Set op2 (MinI op1 op2));
8848 ins_cost(DEFAULT_COST*2);
8849 expand %{
8850 flagsReg icc;
8851 compI_iReg(icc,op1,op2);
8852 cmovI_reg_lt(op2,op1,icc);
8853 %}
8854 %}
8855
8856 // Max Instructions
8857 // Conditional move for max
8858 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8859 effect( USE_DEF op2, USE op1, USE icc );
8860 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8861 opcode(Assembler::greater);
8862 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8863 ins_pipe(ialu_reg_flags);
8864 %}
8865
8866 // Max Register with Register
8867 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8868 match(Set op2 (MaxI op1 op2));
8869 ins_cost(DEFAULT_COST*2);
8870 expand %{
8871 flagsReg icc;
8872 compI_iReg(icc,op1,op2);
8873 cmovI_reg_gt(op2,op1,icc);
8874 %}
8875 %}
8876
8877
8878 //----------Float Compares----------------------------------------------------
8879 // Compare floating, generate condition code
8880 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8881 match(Set fcc (CmpF src1 src2));
8882
8883 size(4);
8884 format %{ "FCMPs $fcc,$src1,$src2" %}
8885 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8886 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8887 ins_pipe(faddF_fcc_reg_reg_zero);
8888 %}
8889
8890 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8891 match(Set fcc (CmpD src1 src2));
8892
8893 size(4);
8894 format %{ "FCMPd $fcc,$src1,$src2" %}
8895 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8896 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8897 ins_pipe(faddD_fcc_reg_reg_zero);
8898 %}
8899
8900
8901 // Compare floating, generate -1,0,1
8902 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8903 match(Set dst (CmpF3 src1 src2));
8904 effect(KILL fcc0);
8905 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8906 format %{ "fcmpl $dst,$src1,$src2" %}
8907 // Primary = float
8908 opcode( true );
8909 ins_encode( floating_cmp( dst, src1, src2 ) );
8910 ins_pipe( floating_cmp );
8911 %}
8912
8913 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8914 match(Set dst (CmpD3 src1 src2));
8915 effect(KILL fcc0);
8916 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8917 format %{ "dcmpl $dst,$src1,$src2" %}
8918 // Primary = double (not float)
8919 opcode( false );
8920 ins_encode( floating_cmp( dst, src1, src2 ) );
8921 ins_pipe( floating_cmp );
8922 %}
8923
8924 //----------Branches---------------------------------------------------------
8925 // Jump
8926 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8927 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8928 match(Jump switch_val);
8929
8930 ins_cost(350);
8931
8932 format %{ "SETHI [hi(table_base)],O7\n\t"
8933 "ADD O7, lo(table_base), O7\n\t"
8934 "LD [O7+$switch_val], O7\n\t"
8935 "JUMP O7"
8936 %}
8937 ins_encode( jump_enc( switch_val, table) );
8938 ins_pc_relative(1);
8939 ins_pipe(ialu_reg_reg);
8940 %}
8941
8942 // Direct Branch. Use V8 version with longer range.
8943 instruct branch(label labl) %{
8944 match(Goto);
8945 effect(USE labl);
8946
8947 size(8);
8948 ins_cost(BRANCH_COST);
8949 format %{ "BA $labl" %}
8950 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8951 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8952 ins_encode( enc_ba( labl ) );
8953 ins_pc_relative(1);
8954 ins_pipe(br);
8955 %}
8956
8957 // Conditional Direct Branch
8958 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8959 match(If cmp icc);
8960 effect(USE labl);
8961
8962 size(8);
8963 ins_cost(BRANCH_COST);
8964 format %{ "BP$cmp $icc,$labl" %}
8965 // Prim = bits 24-22, Secnd = bits 31-30
8966 ins_encode( enc_bp( labl, cmp, icc ) );
8967 ins_pc_relative(1);
8968 ins_pipe(br_cc);
8969 %}
8970
8971 // Branch-on-register tests all 64 bits. We assume that values
8972 // in 64-bit registers always remains zero or sign extended
8973 // unless our code munges the high bits. Interrupts can chop
8974 // the high order bits to zero or sign at any time.
8975 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8976 match(If cmp (CmpI op1 zero));
8977 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8978 effect(USE labl);
8979
8980 size(8);
8981 ins_cost(BRANCH_COST);
8982 format %{ "BR$cmp $op1,$labl" %}
8983 ins_encode( enc_bpr( labl, cmp, op1 ) );
8984 ins_pc_relative(1);
8985 ins_pipe(br_reg);
8986 %}
8987
8988 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8989 match(If cmp (CmpP op1 null));
8990 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8991 effect(USE labl);
8992
8993 size(8);
8994 ins_cost(BRANCH_COST);
8995 format %{ "BR$cmp $op1,$labl" %}
8996 ins_encode( enc_bpr( labl, cmp, op1 ) );
8997 ins_pc_relative(1);
8998 ins_pipe(br_reg);
8999 %}
9000
9001 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9002 match(If cmp (CmpL op1 zero));
9003 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9004 effect(USE labl);
9005
9006 size(8);
9007 ins_cost(BRANCH_COST);
9008 format %{ "BR$cmp $op1,$labl" %}
9009 ins_encode( enc_bpr( labl, cmp, op1 ) );
9010 ins_pc_relative(1);
9011 ins_pipe(br_reg);
9012 %}
9013
9014 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9015 match(If cmp icc);
9016 effect(USE labl);
9017
9018 format %{ "BP$cmp $icc,$labl" %}
9019 // Prim = bits 24-22, Secnd = bits 31-30
9020 ins_encode( enc_bp( labl, cmp, icc ) );
9021 ins_pc_relative(1);
9022 ins_pipe(br_cc);
9023 %}
9024
9025 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9026 match(If cmp pcc);
9027 effect(USE labl);
9028
9029 size(8);
9030 ins_cost(BRANCH_COST);
9031 format %{ "BP$cmp $pcc,$labl" %}
9032 // Prim = bits 24-22, Secnd = bits 31-30
9033 ins_encode( enc_bpx( labl, cmp, pcc ) );
9034 ins_pc_relative(1);
9035 ins_pipe(br_cc);
9036 %}
9037
9038 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9039 match(If cmp fcc);
9040 effect(USE labl);
9041
9042 size(8);
9043 ins_cost(BRANCH_COST);
9044 format %{ "FBP$cmp $fcc,$labl" %}
9045 // Prim = bits 24-22, Secnd = bits 31-30
9046 ins_encode( enc_fbp( labl, cmp, fcc ) );
9047 ins_pc_relative(1);
9048 ins_pipe(br_fcc);
9049 %}
9050
9051 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9052 match(CountedLoopEnd cmp icc);
9053 effect(USE labl);
9054
9055 size(8);
9056 ins_cost(BRANCH_COST);
9057 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9058 // Prim = bits 24-22, Secnd = bits 31-30
9059 ins_encode( enc_bp( labl, cmp, icc ) );
9060 ins_pc_relative(1);
9061 ins_pipe(br_cc);
9062 %}
9063
9064 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9065 match(CountedLoopEnd cmp icc);
9066 effect(USE labl);
9067
9068 size(8);
9069 ins_cost(BRANCH_COST);
9070 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9071 // Prim = bits 24-22, Secnd = bits 31-30
9072 ins_encode( enc_bp( labl, cmp, icc ) );
9073 ins_pc_relative(1);
9074 ins_pipe(br_cc);
9075 %}
9076
9077 // ============================================================================
9078 // Long Compare
9079 //
9080 // Currently we hold longs in 2 registers. Comparing such values efficiently
9081 // is tricky. The flavor of compare used depends on whether we are testing
9082 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9083 // The GE test is the negated LT test. The LE test can be had by commuting
9084 // the operands (yielding a GE test) and then negating; negate again for the
9085 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9086 // NE test is negated from that.
9087
9088 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9089 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9090 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9091 // are collapsed internally in the ADLC's dfa-gen code. The match for
9092 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9093 // foo match ends up with the wrong leaf. One fix is to not match both
9094 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9095 // both forms beat the trinary form of long-compare and both are very useful
9096 // on Intel which has so few registers.
9097
9098 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9099 match(If cmp xcc);
9100 effect(USE labl);
9101
9102 size(8);
9103 ins_cost(BRANCH_COST);
9104 format %{ "BP$cmp $xcc,$labl" %}
9105 // Prim = bits 24-22, Secnd = bits 31-30
9106 ins_encode( enc_bpl( labl, cmp, xcc ) );
9107 ins_pc_relative(1);
9108 ins_pipe(br_cc);
9109 %}
9110
9111 // Manifest a CmpL3 result in an integer register. Very painful.
9112 // This is the test to avoid.
9113 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9114 match(Set dst (CmpL3 src1 src2) );
9115 effect( KILL ccr );
9116 ins_cost(6*DEFAULT_COST);
9117 size(24);
9118 format %{ "CMP $src1,$src2\t\t! long\n"
9119 "\tBLT,a,pn done\n"
9120 "\tMOV -1,$dst\t! delay slot\n"
9121 "\tBGT,a,pn done\n"
9122 "\tMOV 1,$dst\t! delay slot\n"
9123 "\tCLR $dst\n"
9124 "done:" %}
9125 ins_encode( cmpl_flag(src1,src2,dst) );
9126 ins_pipe(cmpL_reg);
9127 %}
9128
9129 // Conditional move
9130 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9131 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9132 ins_cost(150);
9133 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9134 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9135 ins_pipe(ialu_reg);
9136 %}
9137
9138 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9139 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9140 ins_cost(140);
9141 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9142 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9143 ins_pipe(ialu_imm);
9144 %}
9145
9146 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9147 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9148 ins_cost(150);
9149 format %{ "MOV$cmp $xcc,$src,$dst" %}
9150 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9151 ins_pipe(ialu_reg);
9152 %}
9153
9154 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9155 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9156 ins_cost(140);
9157 format %{ "MOV$cmp $xcc,$src,$dst" %}
9158 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9159 ins_pipe(ialu_imm);
9160 %}
9161
9162 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9163 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9164 ins_cost(150);
9165 format %{ "MOV$cmp $xcc,$src,$dst" %}
9166 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9167 ins_pipe(ialu_reg);
9168 %}
9169
9170 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9171 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9172 ins_cost(150);
9173 format %{ "MOV$cmp $xcc,$src,$dst" %}
9174 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9175 ins_pipe(ialu_reg);
9176 %}
9177
9178 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9179 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9180 ins_cost(140);
9181 format %{ "MOV$cmp $xcc,$src,$dst" %}
9182 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9183 ins_pipe(ialu_imm);
9184 %}
9185
9186 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9187 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9188 ins_cost(150);
9189 opcode(0x101);
9190 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9191 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9192 ins_pipe(int_conditional_float_move);
9193 %}
9194
9195 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9196 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9197 ins_cost(150);
9198 opcode(0x102);
9199 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9200 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9201 ins_pipe(int_conditional_float_move);
9202 %}
9203
9204 // ============================================================================
9205 // Safepoint Instruction
9206 instruct safePoint_poll(iRegP poll) %{
9207 match(SafePoint poll);
9208 effect(USE poll);
9209
9210 size(4);
9211 #ifdef _LP64
9212 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9213 #else
9214 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9215 #endif
9216 ins_encode %{
9217 __ relocate(relocInfo::poll_type);
9218 __ ld_ptr($poll$$Register, 0, G0);
9219 %}
9220 ins_pipe(loadPollP);
9221 %}
9222
9223 // ============================================================================
9224 // Call Instructions
9225 // Call Java Static Instruction
9226 instruct CallStaticJavaDirect( method meth ) %{
9227 match(CallStaticJava);
9228 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9229 effect(USE meth);
9230
9231 size(8);
9232 ins_cost(CALL_COST);
9233 format %{ "CALL,static ; NOP ==> " %}
9234 ins_encode( Java_Static_Call( meth ), call_epilog );
9235 ins_pc_relative(1);
9236 ins_pipe(simple_call);
9237 %}
9238
9239 // Call Java Static Instruction (method handle version)
9240 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9241 match(CallStaticJava);
9242 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9243 effect(USE meth, KILL l7_mh_SP_save);
9244
9245 size(8);
9246 ins_cost(CALL_COST);
9247 format %{ "CALL,static/MethodHandle" %}
9248 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9249 ins_pc_relative(1);
9250 ins_pipe(simple_call);
9251 %}
9252
9253 // Call Java Dynamic Instruction
9254 instruct CallDynamicJavaDirect( method meth ) %{
9255 match(CallDynamicJava);
9256 effect(USE meth);
9257
9258 ins_cost(CALL_COST);
9259 format %{ "SET (empty),R_G5\n\t"
9260 "CALL,dynamic ; NOP ==> " %}
9261 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9262 ins_pc_relative(1);
9263 ins_pipe(call);
9264 %}
9265
9266 // Call Runtime Instruction
9267 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9268 match(CallRuntime);
9269 effect(USE meth, KILL l7);
9270 ins_cost(CALL_COST);
9271 format %{ "CALL,runtime" %}
9272 ins_encode( Java_To_Runtime( meth ),
9273 call_epilog, adjust_long_from_native_call );
9274 ins_pc_relative(1);
9275 ins_pipe(simple_call);
9276 %}
9277
9278 // Call runtime without safepoint - same as CallRuntime
9279 instruct CallLeafDirect(method meth, l7RegP l7) %{
9280 match(CallLeaf);
9281 effect(USE meth, KILL l7);
9282 ins_cost(CALL_COST);
9283 format %{ "CALL,runtime leaf" %}
9284 ins_encode( Java_To_Runtime( meth ),
9285 call_epilog,
9286 adjust_long_from_native_call );
9287 ins_pc_relative(1);
9288 ins_pipe(simple_call);
9289 %}
9290
9291 // Call runtime without safepoint - same as CallLeaf
9292 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9293 match(CallLeafNoFP);
9294 effect(USE meth, KILL l7);
9295 ins_cost(CALL_COST);
9296 format %{ "CALL,runtime leaf nofp" %}
9297 ins_encode( Java_To_Runtime( meth ),
9298 call_epilog,
9299 adjust_long_from_native_call );
9300 ins_pc_relative(1);
9301 ins_pipe(simple_call);
9302 %}
9303
9304 // Tail Call; Jump from runtime stub to Java code.
9305 // Also known as an 'interprocedural jump'.
9306 // Target of jump will eventually return to caller.
9307 // TailJump below removes the return address.
9308 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9309 match(TailCall jump_target method_oop );
9310
9311 ins_cost(CALL_COST);
9312 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9313 ins_encode(form_jmpl(jump_target));
9314 ins_pipe(tail_call);
9315 %}
9316
9317
9318 // Return Instruction
9319 instruct Ret() %{
9320 match(Return);
9321
9322 // The epilogue node did the ret already.
9323 size(0);
9324 format %{ "! return" %}
9325 ins_encode();
9326 ins_pipe(empty);
9327 %}
9328
9329
9330 // Tail Jump; remove the return address; jump to target.
9331 // TailCall above leaves the return address around.
9332 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9333 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9334 // "restore" before this instruction (in Epilogue), we need to materialize it
9335 // in %i0.
9336 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9337 match( TailJump jump_target ex_oop );
9338 ins_cost(CALL_COST);
9339 format %{ "! discard R_O7\n\t"
9340 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9341 ins_encode(form_jmpl_set_exception_pc(jump_target));
9342 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9343 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9344 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9345 ins_pipe(tail_call);
9346 %}
9347
9348 // Create exception oop: created by stack-crawling runtime code.
9349 // Created exception is now available to this handler, and is setup
9350 // just prior to jumping to this handler. No code emitted.
9351 instruct CreateException( o0RegP ex_oop )
9352 %{
9353 match(Set ex_oop (CreateEx));
9354 ins_cost(0);
9355
9356 size(0);
9357 // use the following format syntax
9358 format %{ "! exception oop is in R_O0; no code emitted" %}
9359 ins_encode();
9360 ins_pipe(empty);
9361 %}
9362
9363
9364 // Rethrow exception:
9365 // The exception oop will come in the first argument position.
9366 // Then JUMP (not call) to the rethrow stub code.
9367 instruct RethrowException()
9368 %{
9369 match(Rethrow);
9370 ins_cost(CALL_COST);
9371
9372 // use the following format syntax
9373 format %{ "Jmp rethrow_stub" %}
9374 ins_encode(enc_rethrow);
9375 ins_pipe(tail_call);
9376 %}
9377
9378
9379 // Die now
9380 instruct ShouldNotReachHere( )
9381 %{
9382 match(Halt);
9383 ins_cost(CALL_COST);
9384
9385 size(4);
9386 // Use the following format syntax
9387 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9388 ins_encode( form2_illtrap() );
9389 ins_pipe(tail_call);
9390 %}
9391
9392 // ============================================================================
9393 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9394 // array for an instance of the superklass. Set a hidden internal cache on a
9395 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9396 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9397 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9398 match(Set index (PartialSubtypeCheck sub super));
9399 effect( KILL pcc, KILL o7 );
9400 ins_cost(DEFAULT_COST*10);
9401 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9402 ins_encode( enc_PartialSubtypeCheck() );
9403 ins_pipe(partial_subtype_check_pipe);
9404 %}
9405
9406 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9407 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9408 effect( KILL idx, KILL o7 );
9409 ins_cost(DEFAULT_COST*10);
9410 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9411 ins_encode( enc_PartialSubtypeCheck() );
9412 ins_pipe(partial_subtype_check_pipe);
9413 %}
9414
9415
9416 // ============================================================================
9417 // inlined locking and unlocking
9418
9419 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9420 match(Set pcc (FastLock object box));
9421
9422 effect(KILL scratch, TEMP scratch2);
9423 ins_cost(100);
9424
9425 size(4*112); // conservative overestimation ...
9426 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9427 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9428 ins_pipe(long_memory_op);
9429 %}
9430
9431
9432 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9433 match(Set pcc (FastUnlock object box));
9434 effect(KILL scratch, TEMP scratch2);
9435 ins_cost(100);
9436
9437 size(4*120); // conservative overestimation ...
9438 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9439 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9440 ins_pipe(long_memory_op);
9441 %}
9442
9443 // Count and Base registers are fixed because the allocator cannot
9444 // kill unknown registers. The encodings are generic.
9445 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9446 match(Set dummy (ClearArray cnt base));
9447 effect(TEMP temp, KILL ccr);
9448 ins_cost(300);
9449 format %{ "MOV $cnt,$temp\n"
9450 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9451 " BRge loop\t\t! Clearing loop\n"
9452 " STX G0,[$base+$temp]\t! delay slot" %}
9453 ins_encode( enc_Clear_Array(cnt, base, temp) );
9454 ins_pipe(long_memory_op);
9455 %}
9456
9457 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9458 o7RegI tmp, flagsReg ccr) %{
9459 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9460 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9461 ins_cost(300);
9462 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9463 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9464 ins_pipe(long_memory_op);
9465 %}
9466
9467 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9468 o7RegI tmp, flagsReg ccr) %{
9469 match(Set result (StrEquals (Binary str1 str2) cnt));
9470 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9471 ins_cost(300);
9472 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9473 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9474 ins_pipe(long_memory_op);
9475 %}
9476
9477 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9478 o7RegI tmp2, flagsReg ccr) %{
9479 match(Set result (AryEq ary1 ary2));
9480 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9481 ins_cost(300);
9482 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9483 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9484 ins_pipe(long_memory_op);
9485 %}
9486
9487
9488 //---------- Zeros Count Instructions ------------------------------------------
9489
9490 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9491 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9492 match(Set dst (CountLeadingZerosI src));
9493 effect(TEMP dst, TEMP tmp, KILL cr);
9494
9495 // x |= (x >> 1);
9496 // x |= (x >> 2);
9497 // x |= (x >> 4);
9498 // x |= (x >> 8);
9499 // x |= (x >> 16);
9500 // return (WORDBITS - popc(x));
9501 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9502 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9503 "OR $dst,$tmp,$dst\n\t"
9504 "SRL $dst,2,$tmp\n\t"
9505 "OR $dst,$tmp,$dst\n\t"
9506 "SRL $dst,4,$tmp\n\t"
9507 "OR $dst,$tmp,$dst\n\t"
9508 "SRL $dst,8,$tmp\n\t"
9509 "OR $dst,$tmp,$dst\n\t"
9510 "SRL $dst,16,$tmp\n\t"
9511 "OR $dst,$tmp,$dst\n\t"
9512 "POPC $dst,$dst\n\t"
9513 "MOV 32,$tmp\n\t"
9514 "SUB $tmp,$dst,$dst" %}
9515 ins_encode %{
9516 Register Rdst = $dst$$Register;
9517 Register Rsrc = $src$$Register;
9518 Register Rtmp = $tmp$$Register;
9519 __ srl(Rsrc, 1, Rtmp);
9520 __ srl(Rsrc, 0, Rdst);
9521 __ or3(Rdst, Rtmp, Rdst);
9522 __ srl(Rdst, 2, Rtmp);
9523 __ or3(Rdst, Rtmp, Rdst);
9524 __ srl(Rdst, 4, Rtmp);
9525 __ or3(Rdst, Rtmp, Rdst);
9526 __ srl(Rdst, 8, Rtmp);
9527 __ or3(Rdst, Rtmp, Rdst);
9528 __ srl(Rdst, 16, Rtmp);
9529 __ or3(Rdst, Rtmp, Rdst);
9530 __ popc(Rdst, Rdst);
9531 __ mov(BitsPerInt, Rtmp);
9532 __ sub(Rtmp, Rdst, Rdst);
9533 %}
9534 ins_pipe(ialu_reg);
9535 %}
9536
9537 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9538 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9539 match(Set dst (CountLeadingZerosL src));
9540 effect(TEMP dst, TEMP tmp, KILL cr);
9541
9542 // x |= (x >> 1);
9543 // x |= (x >> 2);
9544 // x |= (x >> 4);
9545 // x |= (x >> 8);
9546 // x |= (x >> 16);
9547 // x |= (x >> 32);
9548 // return (WORDBITS - popc(x));
9549 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9550 "OR $src,$tmp,$dst\n\t"
9551 "SRLX $dst,2,$tmp\n\t"
9552 "OR $dst,$tmp,$dst\n\t"
9553 "SRLX $dst,4,$tmp\n\t"
9554 "OR $dst,$tmp,$dst\n\t"
9555 "SRLX $dst,8,$tmp\n\t"
9556 "OR $dst,$tmp,$dst\n\t"
9557 "SRLX $dst,16,$tmp\n\t"
9558 "OR $dst,$tmp,$dst\n\t"
9559 "SRLX $dst,32,$tmp\n\t"
9560 "OR $dst,$tmp,$dst\n\t"
9561 "POPC $dst,$dst\n\t"
9562 "MOV 64,$tmp\n\t"
9563 "SUB $tmp,$dst,$dst" %}
9564 ins_encode %{
9565 Register Rdst = $dst$$Register;
9566 Register Rsrc = $src$$Register;
9567 Register Rtmp = $tmp$$Register;
9568 __ srlx(Rsrc, 1, Rtmp);
9569 __ or3( Rsrc, Rtmp, Rdst);
9570 __ srlx(Rdst, 2, Rtmp);
9571 __ or3( Rdst, Rtmp, Rdst);
9572 __ srlx(Rdst, 4, Rtmp);
9573 __ or3( Rdst, Rtmp, Rdst);
9574 __ srlx(Rdst, 8, Rtmp);
9575 __ or3( Rdst, Rtmp, Rdst);
9576 __ srlx(Rdst, 16, Rtmp);
9577 __ or3( Rdst, Rtmp, Rdst);
9578 __ srlx(Rdst, 32, Rtmp);
9579 __ or3( Rdst, Rtmp, Rdst);
9580 __ popc(Rdst, Rdst);
9581 __ mov(BitsPerLong, Rtmp);
9582 __ sub(Rtmp, Rdst, Rdst);
9583 %}
9584 ins_pipe(ialu_reg);
9585 %}
9586
9587 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9588 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9589 match(Set dst (CountTrailingZerosI src));
9590 effect(TEMP dst, KILL cr);
9591
9592 // return popc(~x & (x - 1));
9593 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9594 "ANDN $dst,$src,$dst\n\t"
9595 "SRL $dst,R_G0,$dst\n\t"
9596 "POPC $dst,$dst" %}
9597 ins_encode %{
9598 Register Rdst = $dst$$Register;
9599 Register Rsrc = $src$$Register;
9600 __ sub(Rsrc, 1, Rdst);
9601 __ andn(Rdst, Rsrc, Rdst);
9602 __ srl(Rdst, G0, Rdst);
9603 __ popc(Rdst, Rdst);
9604 %}
9605 ins_pipe(ialu_reg);
9606 %}
9607
9608 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9609 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9610 match(Set dst (CountTrailingZerosL src));
9611 effect(TEMP dst, KILL cr);
9612
9613 // return popc(~x & (x - 1));
9614 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9615 "ANDN $dst,$src,$dst\n\t"
9616 "POPC $dst,$dst" %}
9617 ins_encode %{
9618 Register Rdst = $dst$$Register;
9619 Register Rsrc = $src$$Register;
9620 __ sub(Rsrc, 1, Rdst);
9621 __ andn(Rdst, Rsrc, Rdst);
9622 __ popc(Rdst, Rdst);
9623 %}
9624 ins_pipe(ialu_reg);
9625 %}
9626
9627
9628 //---------- Population Count Instructions -------------------------------------
9629
9630 instruct popCountI(iRegI dst, iRegI src) %{
9631 predicate(UsePopCountInstruction);
9632 match(Set dst (PopCountI src));
9633
9634 format %{ "POPC $src, $dst" %}
9635 ins_encode %{
9636 __ popc($src$$Register, $dst$$Register);
9637 %}
9638 ins_pipe(ialu_reg);
9639 %}
9640
9641 // Note: Long.bitCount(long) returns an int.
9642 instruct popCountL(iRegI dst, iRegL src) %{
9643 predicate(UsePopCountInstruction);
9644 match(Set dst (PopCountL src));
9645
9646 format %{ "POPC $src, $dst" %}
9647 ins_encode %{
9648 __ popc($src$$Register, $dst$$Register);
9649 %}
9650 ins_pipe(ialu_reg);
9651 %}
9652
9653
9654 // ============================================================================
9655 //------------Bytes reverse--------------------------------------------------
9656
9657 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9658 match(Set dst (ReverseBytesI src));
9659
9660 // Op cost is artificially doubled to make sure that load or store
9661 // instructions are preferred over this one which requires a spill
9662 // onto a stack slot.
9663 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9664 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9665
9666 ins_encode %{
9667 __ set($src$$disp + STACK_BIAS, O7);
9668 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9669 %}
9670 ins_pipe( iload_mem );
9671 %}
9672
9673 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9674 match(Set dst (ReverseBytesL src));
9675
9676 // Op cost is artificially doubled to make sure that load or store
9677 // instructions are preferred over this one which requires a spill
9678 // onto a stack slot.
9679 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9680 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9681
9682 ins_encode %{
9683 __ set($src$$disp + STACK_BIAS, O7);
9684 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9685 %}
9686 ins_pipe( iload_mem );
9687 %}
9688
9689 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9690 match(Set dst (ReverseBytesUS src));
9691
9692 // Op cost is artificially doubled to make sure that load or store
9693 // instructions are preferred over this one which requires a spill
9694 // onto a stack slot.
9695 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9696 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9697
9698 ins_encode %{
9699 // the value was spilled as an int so bias the load
9700 __ set($src$$disp + STACK_BIAS + 2, O7);
9701 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9702 %}
9703 ins_pipe( iload_mem );
9704 %}
9705
9706 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9707 match(Set dst (ReverseBytesS src));
9708
9709 // Op cost is artificially doubled to make sure that load or store
9710 // instructions are preferred over this one which requires a spill
9711 // onto a stack slot.
9712 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9713 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9714
9715 ins_encode %{
9716 // the value was spilled as an int so bias the load
9717 __ set($src$$disp + STACK_BIAS + 2, O7);
9718 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9719 %}
9720 ins_pipe( iload_mem );
9721 %}
9722
9723 // Load Integer reversed byte order
9724 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9725 match(Set dst (ReverseBytesI (LoadI src)));
9726
9727 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9728 size(4);
9729 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9730
9731 ins_encode %{
9732 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9733 %}
9734 ins_pipe(iload_mem);
9735 %}
9736
9737 // Load Long - aligned and reversed
9738 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9739 match(Set dst (ReverseBytesL (LoadL src)));
9740
9741 ins_cost(MEMORY_REF_COST);
9742 size(4);
9743 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9744
9745 ins_encode %{
9746 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9747 %}
9748 ins_pipe(iload_mem);
9749 %}
9750
9751 // Load unsigned short / char reversed byte order
9752 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9753 match(Set dst (ReverseBytesUS (LoadUS src)));
9754
9755 ins_cost(MEMORY_REF_COST);
9756 size(4);
9757 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9758
9759 ins_encode %{
9760 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9761 %}
9762 ins_pipe(iload_mem);
9763 %}
9764
9765 // Load short reversed byte order
9766 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
9767 match(Set dst (ReverseBytesS (LoadS src)));
9768
9769 ins_cost(MEMORY_REF_COST);
9770 size(4);
9771 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9772
9773 ins_encode %{
9774 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9775 %}
9776 ins_pipe(iload_mem);
9777 %}
9778
9779 // Store Integer reversed byte order
9780 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
9781 match(Set dst (StoreI dst (ReverseBytesI src)));
9782
9783 ins_cost(MEMORY_REF_COST);
9784 size(4);
9785 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9786
9787 ins_encode %{
9788 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9789 %}
9790 ins_pipe(istore_mem_reg);
9791 %}
9792
9793 // Store Long reversed byte order
9794 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
9795 match(Set dst (StoreL dst (ReverseBytesL src)));
9796
9797 ins_cost(MEMORY_REF_COST);
9798 size(4);
9799 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9800
9801 ins_encode %{
9802 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9803 %}
9804 ins_pipe(istore_mem_reg);
9805 %}
9806
9807 // Store unsighed short/char reversed byte order
9808 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
9809 match(Set dst (StoreC dst (ReverseBytesUS src)));
9810
9811 ins_cost(MEMORY_REF_COST);
9812 size(4);
9813 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9814
9815 ins_encode %{
9816 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9817 %}
9818 ins_pipe(istore_mem_reg);
9819 %}
9820
9821 // Store short reversed byte order
9822 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
9823 match(Set dst (StoreC dst (ReverseBytesS src)));
9824
9825 ins_cost(MEMORY_REF_COST);
9826 size(4);
9827 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9828
9829 ins_encode %{
9830 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9831 %}
9832 ins_pipe(istore_mem_reg);
9833 %}
9834
9835 //----------PEEPHOLE RULES-----------------------------------------------------
9836 // These must follow all instruction definitions as they use the names
9837 // defined in the instructions definitions.
9838 //
9839 // peepmatch ( root_instr_name [preceding_instruction]* );
9840 //
9841 // peepconstraint %{
9842 // (instruction_number.operand_name relational_op instruction_number.operand_name
9843 // [, ...] );
9844 // // instruction numbers are zero-based using left to right order in peepmatch
9845 //
9846 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9847 // // provide an instruction_number.operand_name for each operand that appears
9848 // // in the replacement instruction's match rule
9849 //
9850 // ---------VM FLAGS---------------------------------------------------------
9851 //
9852 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9853 //
9854 // Each peephole rule is given an identifying number starting with zero and
9855 // increasing by one in the order seen by the parser. An individual peephole
9856 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9857 // on the command-line.
9858 //
9859 // ---------CURRENT LIMITATIONS----------------------------------------------
9860 //
9861 // Only match adjacent instructions in same basic block
9862 // Only equality constraints
9863 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9864 // Only one replacement instruction
9865 //
9866 // ---------EXAMPLE----------------------------------------------------------
9867 //
9868 // // pertinent parts of existing instructions in architecture description
9869 // instruct movI(eRegI dst, eRegI src) %{
9870 // match(Set dst (CopyI src));
9871 // %}
9872 //
9873 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9874 // match(Set dst (AddI dst src));
9875 // effect(KILL cr);
9876 // %}
9877 //
9878 // // Change (inc mov) to lea
9879 // peephole %{
9880 // // increment preceeded by register-register move
9881 // peepmatch ( incI_eReg movI );
9882 // // require that the destination register of the increment
9883 // // match the destination register of the move
9884 // peepconstraint ( 0.dst == 1.dst );
9885 // // construct a replacement instruction that sets
9886 // // the destination to ( move's source register + one )
9887 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9888 // %}
9889 //
9890
9891 // // Change load of spilled value to only a spill
9892 // instruct storeI(memory mem, eRegI src) %{
9893 // match(Set mem (StoreI mem src));
9894 // %}
9895 //
9896 // instruct loadI(eRegI dst, memory mem) %{
9897 // match(Set dst (LoadI mem));
9898 // %}
9899 //
9900 // peephole %{
9901 // peepmatch ( loadI storeI );
9902 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9903 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9904 // %}
9905
9906 //----------SMARTSPILL RULES---------------------------------------------------
9907 // These must follow all instruction definitions as they use the names
9908 // defined in the instructions definitions.
9909 //
9910 // SPARC will probably not have any of these rules due to RISC instruction set.
9911
9912 //----------PIPELINE-----------------------------------------------------------
9913 // Rules which define the behavior of the target architectures pipeline.