1 // 2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Must be visible to the DFA in dfa_sparc.cpp 461 extern bool can_branch_register( Node *bol, Node *cmp ); 462 463 // Macros to extract hi & lo halves from a long pair. 464 // G0 is not part of any long pair, so assert on that. 465 // Prevents accidentally using G1 instead of G0. 466 #define LONG_HI_REG(x) (x) 467 #define LONG_LO_REG(x) (x) 468 469 %} 470 471 source %{ 472 #define __ _masm. 473 474 // Block initializing store 475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 476 477 // tertiary op of a LoadP or StoreP encoding 478 #define REGP_OP true 479 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 482 static Register reg_to_register_object(int register_encoding); 483 484 // Used by the DFA in dfa_sparc.cpp. 485 // Check for being able to use a V9 branch-on-register. Requires a 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 487 // extended. Doesn't work following an integer ADD, for example, because of 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 490 // replace them with zero, which could become sign-extension in a different OS 491 // release. There's no obvious reason why an interrupt will ever fill these 492 // bits with non-zero junk (the registers are reloaded with standard LD 493 // instructions which either zero-fill or sign-fill). 494 bool can_branch_register( Node *bol, Node *cmp ) { 495 if( !BranchOnRegister ) return false; 496 #ifdef _LP64 497 if( cmp->Opcode() == Op_CmpP ) 498 return true; // No problems with pointer compares 499 #endif 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525 } 526 527 // **************************************************************************** 528 529 // REQUIRED FUNCTIONALITY 530 531 // !!!!! Special hack to get all type of calls to specify the byte offset 532 // from the start of the call to the point where the return address 533 // will point. 534 // The "return address" is the address of the call instruction, plus 8. 535 536 int MachCallStaticJavaNode::ret_addr_offset() { 537 int offset = NativeCall::instruction_size; // call; delay slot 538 if (_method_handle_invoke) 539 offset += 4; // restore SP 540 return offset; 541 } 542 543 int MachCallDynamicJavaNode::ret_addr_offset() { 544 int vtable_index = this->_vtable_index; 545 if (vtable_index < 0) { 546 // must be invalid_vtable_index, not nonvirtual_vtable_index 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 548 return (NativeMovConstReg::instruction_size + 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot 550 } else { 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 554 int klass_load_size; 555 if (UseCompressedOops) { 556 assert(Universe::heap() != NULL, "java heap should be initialized"); 557 if (Universe::narrow_oop_base() == NULL) 558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 559 else 560 klass_load_size = 3*BytesPerInstWord; 561 } else { 562 klass_load_size = 1*BytesPerInstWord; 563 } 564 if( Assembler::is_simm13(v_off) ) { 565 return klass_load_size + 566 (2*BytesPerInstWord + // ld_ptr, ld_ptr 567 NativeCall::instruction_size); // call; delay slot 568 } else { 569 return klass_load_size + 570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 571 NativeCall::instruction_size); // call; delay slot 572 } 573 } 574 } 575 576 int MachCallRuntimeNode::ret_addr_offset() { 577 #ifdef _LP64 578 return NativeFarCall::instruction_size; // farcall; delay slot 579 #else 580 return NativeCall::instruction_size; // call; delay slot 581 #endif 582 } 583 584 // Indicate if the safepoint node needs the polling page as an input. 585 // Since Sparc does not have absolute addressing, it does. 586 bool SafePointNode::needs_polling_address_input() { 587 return true; 588 } 589 590 // emit an interrupt that is caught by the debugger (for debugging compiler) 591 void emit_break(CodeBuffer &cbuf) { 592 MacroAssembler _masm(&cbuf); 593 __ breakpoint_trap(); 594 } 595 596 #ifndef PRODUCT 597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 598 st->print("TA"); 599 } 600 #endif 601 602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 603 emit_break(cbuf); 604 } 605 606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 607 return MachNode::size(ra_); 608 } 609 610 // Traceable jump 611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 612 MacroAssembler _masm(&cbuf); 613 Register rdest = reg_to_register_object(jump_target); 614 __ JMP(rdest, 0); 615 __ delayed()->nop(); 616 } 617 618 // Traceable jump and set exception pc 619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 620 MacroAssembler _masm(&cbuf); 621 Register rdest = reg_to_register_object(jump_target); 622 __ JMP(rdest, 0); 623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 624 } 625 626 void emit_nop(CodeBuffer &cbuf) { 627 MacroAssembler _masm(&cbuf); 628 __ nop(); 629 } 630 631 void emit_illtrap(CodeBuffer &cbuf) { 632 MacroAssembler _masm(&cbuf); 633 __ illtrap(0); 634 } 635 636 637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 638 assert(n->rule() != loadUB_rule, ""); 639 640 intptr_t offset = 0; 641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 642 const Node* addr = n->get_base_and_disp(offset, adr_type); 643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 644 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 645 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 646 atype = atype->add_offset(offset); 647 assert(disp32 == offset, "wrong disp32"); 648 return atype->_offset; 649 } 650 651 652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 653 assert(n->rule() != loadUB_rule, ""); 654 655 intptr_t offset = 0; 656 Node* addr = n->in(2); 657 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 659 Node* a = addr->in(2/*AddPNode::Address*/); 660 Node* o = addr->in(3/*AddPNode::Offset*/); 661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 662 atype = a->bottom_type()->is_ptr()->add_offset(offset); 663 assert(atype->isa_oop_ptr(), "still an oop"); 664 } 665 offset = atype->is_ptr()->_offset; 666 if (offset != Type::OffsetBot) offset += disp32; 667 return offset; 668 } 669 670 static inline jdouble replicate_immI(int con, int count, int width) { 671 // Load a constant replicated "count" times with width "width" 672 int bit_width = width * 8; 673 jlong elt_val = con; 674 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 675 jlong val = elt_val; 676 for (int i = 0; i < count - 1; i++) { 677 val <<= bit_width; 678 val |= elt_val; 679 } 680 jdouble dval = *((jdouble*) &val); // coerce to double type 681 return dval; 682 } 683 684 // Standard Sparc opcode form2 field breakdown 685 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 686 f0 &= (1<<19)-1; // Mask displacement to 19 bits 687 int op = (f30 << 30) | 688 (f29 << 29) | 689 (f25 << 25) | 690 (f22 << 22) | 691 (f20 << 20) | 692 (f19 << 19) | 693 (f0 << 0); 694 cbuf.insts()->emit_int32(op); 695 } 696 697 // Standard Sparc opcode form2 field breakdown 698 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 699 f0 >>= 10; // Drop 10 bits 700 f0 &= (1<<22)-1; // Mask displacement to 22 bits 701 int op = (f30 << 30) | 702 (f25 << 25) | 703 (f22 << 22) | 704 (f0 << 0); 705 cbuf.insts()->emit_int32(op); 706 } 707 708 // Standard Sparc opcode form3 field breakdown 709 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 710 int op = (f30 << 30) | 711 (f25 << 25) | 712 (f19 << 19) | 713 (f14 << 14) | 714 (f5 << 5) | 715 (f0 << 0); 716 cbuf.insts()->emit_int32(op); 717 } 718 719 // Standard Sparc opcode form3 field breakdown 720 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 721 simm13 &= (1<<13)-1; // Mask to 13 bits 722 int op = (f30 << 30) | 723 (f25 << 25) | 724 (f19 << 19) | 725 (f14 << 14) | 726 (1 << 13) | // bit to indicate immediate-mode 727 (simm13<<0); 728 cbuf.insts()->emit_int32(op); 729 } 730 731 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 732 simm10 &= (1<<10)-1; // Mask to 10 bits 733 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 734 } 735 736 #ifdef ASSERT 737 // Helper function for VerifyOops in emit_form3_mem_reg 738 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 739 warning("VerifyOops encountered unexpected instruction:"); 740 n->dump(2); 741 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 742 } 743 #endif 744 745 746 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 747 int src1_enc, int disp32, int src2_enc, int dst_enc) { 748 749 #ifdef ASSERT 750 // The following code implements the +VerifyOops feature. 751 // It verifies oop values which are loaded into or stored out of 752 // the current method activation. +VerifyOops complements techniques 753 // like ScavengeALot, because it eagerly inspects oops in transit, 754 // as they enter or leave the stack, as opposed to ScavengeALot, 755 // which inspects oops "at rest", in the stack or heap, at safepoints. 756 // For this reason, +VerifyOops can sometimes detect bugs very close 757 // to their point of creation. It can also serve as a cross-check 758 // on the validity of oop maps, when used toegether with ScavengeALot. 759 760 // It would be good to verify oops at other points, especially 761 // when an oop is used as a base pointer for a load or store. 762 // This is presently difficult, because it is hard to know when 763 // a base address is biased or not. (If we had such information, 764 // it would be easy and useful to make a two-argument version of 765 // verify_oop which unbiases the base, and performs verification.) 766 767 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 768 bool is_verified_oop_base = false; 769 bool is_verified_oop_load = false; 770 bool is_verified_oop_store = false; 771 int tmp_enc = -1; 772 if (VerifyOops && src1_enc != R_SP_enc) { 773 // classify the op, mainly for an assert check 774 int st_op = 0, ld_op = 0; 775 switch (primary) { 776 case Assembler::stb_op3: st_op = Op_StoreB; break; 777 case Assembler::sth_op3: st_op = Op_StoreC; break; 778 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 779 case Assembler::stw_op3: st_op = Op_StoreI; break; 780 case Assembler::std_op3: st_op = Op_StoreL; break; 781 case Assembler::stf_op3: st_op = Op_StoreF; break; 782 case Assembler::stdf_op3: st_op = Op_StoreD; break; 783 784 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 785 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 786 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 787 case Assembler::ldx_op3: // may become LoadP or stay LoadI 788 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 789 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 790 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 791 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 792 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 793 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 794 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 795 796 default: ShouldNotReachHere(); 797 } 798 if (tertiary == REGP_OP) { 799 if (st_op == Op_StoreI) st_op = Op_StoreP; 800 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 801 else ShouldNotReachHere(); 802 if (st_op) { 803 // a store 804 // inputs are (0:control, 1:memory, 2:address, 3:value) 805 Node* n2 = n->in(3); 806 if (n2 != NULL) { 807 const Type* t = n2->bottom_type(); 808 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 809 } 810 } else { 811 // a load 812 const Type* t = n->bottom_type(); 813 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 814 } 815 } 816 817 if (ld_op) { 818 // a Load 819 // inputs are (0:control, 1:memory, 2:address) 820 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 821 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 822 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 823 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 824 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 825 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 826 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 827 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 828 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 829 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 830 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 831 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 832 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 834 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && 835 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && 836 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && 837 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && 838 !(n->rule() == loadUB_rule)) { 839 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 840 } 841 } else if (st_op) { 842 // a Store 843 // inputs are (0:control, 1:memory, 2:address, 3:value) 844 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 845 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 846 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 847 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 848 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 849 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && 850 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && 851 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && 852 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 853 verify_oops_warning(n, n->ideal_Opcode(), st_op); 854 } 855 } 856 857 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 858 Node* addr = n->in(2); 859 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 860 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 861 if (atype != NULL) { 862 intptr_t offset = get_offset_from_base(n, atype, disp32); 863 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 864 if (offset != offset_2) { 865 get_offset_from_base(n, atype, disp32); 866 get_offset_from_base_2(n, atype, disp32); 867 } 868 assert(offset == offset_2, "different offsets"); 869 if (offset == disp32) { 870 // we now know that src1 is a true oop pointer 871 is_verified_oop_base = true; 872 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 873 if( primary == Assembler::ldd_op3 ) { 874 is_verified_oop_base = false; // Cannot 'ldd' into O7 875 } else { 876 tmp_enc = dst_enc; 877 dst_enc = R_O7_enc; // Load into O7; preserve source oop 878 assert(src1_enc != dst_enc, ""); 879 } 880 } 881 } 882 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 883 || offset == oopDesc::mark_offset_in_bytes())) { 884 // loading the mark should not be allowed either, but 885 // we don't check this since it conflicts with InlineObjectHash 886 // usage of LoadINode to get the mark. We could keep the 887 // check if we create a new LoadMarkNode 888 // but do not verify the object before its header is initialized 889 ShouldNotReachHere(); 890 } 891 } 892 } 893 } 894 } 895 #endif 896 897 uint instr; 898 instr = (Assembler::ldst_op << 30) 899 | (dst_enc << 25) 900 | (primary << 19) 901 | (src1_enc << 14); 902 903 uint index = src2_enc; 904 int disp = disp32; 905 906 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 907 disp += STACK_BIAS; 908 909 // We should have a compiler bailout here rather than a guarantee. 910 // Better yet would be some mechanism to handle variable-size matches correctly. 911 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 912 913 if( disp == 0 ) { 914 // use reg-reg form 915 // bit 13 is already zero 916 instr |= index; 917 } else { 918 // use reg-imm form 919 instr |= 0x00002000; // set bit 13 to one 920 instr |= disp & 0x1FFF; 921 } 922 923 cbuf.insts()->emit_int32(instr); 924 925 #ifdef ASSERT 926 { 927 MacroAssembler _masm(&cbuf); 928 if (is_verified_oop_base) { 929 __ verify_oop(reg_to_register_object(src1_enc)); 930 } 931 if (is_verified_oop_store) { 932 __ verify_oop(reg_to_register_object(dst_enc)); 933 } 934 if (tmp_enc != -1) { 935 __ mov(O7, reg_to_register_object(tmp_enc)); 936 } 937 if (is_verified_oop_load) { 938 __ verify_oop(reg_to_register_object(dst_enc)); 939 } 940 } 941 #endif 942 } 943 944 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 945 // The method which records debug information at every safepoint 946 // expects the call to be the first instruction in the snippet as 947 // it creates a PcDesc structure which tracks the offset of a call 948 // from the start of the codeBlob. This offset is computed as 949 // code_end() - code_begin() of the code which has been emitted 950 // so far. 951 // In this particular case we have skirted around the problem by 952 // putting the "mov" instruction in the delay slot but the problem 953 // may bite us again at some other point and a cleaner/generic 954 // solution using relocations would be needed. 955 MacroAssembler _masm(&cbuf); 956 __ set_inst_mark(); 957 958 // We flush the current window just so that there is a valid stack copy 959 // the fact that the current window becomes active again instantly is 960 // not a problem there is nothing live in it. 961 962 #ifdef ASSERT 963 int startpos = __ offset(); 964 #endif /* ASSERT */ 965 966 #ifdef _LP64 967 // Calls to the runtime or native may not be reachable from compiled code, 968 // so we generate the far call sequence on 64 bit sparc. 969 // This code sequence is relocatable to any address, even on LP64. 970 if ( force_far_call ) { 971 __ relocate(rtype); 972 AddressLiteral dest(entry_point); 973 __ jumpl_to(dest, O7, O7); 974 } 975 else 976 #endif 977 { 978 __ call((address)entry_point, rtype); 979 } 980 981 if (preserve_g2) __ delayed()->mov(G2, L7); 982 else __ delayed()->nop(); 983 984 if (preserve_g2) __ mov(L7, G2); 985 986 #ifdef ASSERT 987 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 988 #ifdef _LP64 989 // Trash argument dump slots. 990 __ set(0xb0b8ac0db0b8ac0d, G1); 991 __ mov(G1, G5); 992 __ stx(G1, SP, STACK_BIAS + 0x80); 993 __ stx(G1, SP, STACK_BIAS + 0x88); 994 __ stx(G1, SP, STACK_BIAS + 0x90); 995 __ stx(G1, SP, STACK_BIAS + 0x98); 996 __ stx(G1, SP, STACK_BIAS + 0xA0); 997 __ stx(G1, SP, STACK_BIAS + 0xA8); 998 #else // _LP64 999 // this is also a native call, so smash the first 7 stack locations, 1000 // and the various registers 1001 1002 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1003 // while [SP+0x44..0x58] are the argument dump slots. 1004 __ set((intptr_t)0xbaadf00d, G1); 1005 __ mov(G1, G5); 1006 __ sllx(G1, 32, G1); 1007 __ or3(G1, G5, G1); 1008 __ mov(G1, G5); 1009 __ stx(G1, SP, 0x40); 1010 __ stx(G1, SP, 0x48); 1011 __ stx(G1, SP, 0x50); 1012 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1013 #endif // _LP64 1014 } 1015 #endif /*ASSERT*/ 1016 } 1017 1018 //============================================================================= 1019 // REQUIRED FUNCTIONALITY for encoding 1020 void emit_lo(CodeBuffer &cbuf, int val) { } 1021 void emit_hi(CodeBuffer &cbuf, int val) { } 1022 1023 1024 //============================================================================= 1025 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; 1026 1027 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1028 emit_constant_table(cbuf); 1029 MacroAssembler _masm(&cbuf); 1030 1031 Register r = as_Register(ra_->get_encode(this)); 1032 CodeSection* cs = __ code()->consts(); 1033 int consts_size = cs->align_at_start(cs->size()); 1034 1035 if (UseRDPCForConstantTableBase) { 1036 int offset = __ offset(); 1037 int disp; 1038 1039 // If the displacement from the current PC to the constant table 1040 // base fits into simm13 we set the constant table base to the 1041 // current PC. 1042 if (__ is_simm13(-(consts_size + offset))) { 1043 set_table_base_offset(-(consts_size + offset)); 1044 disp = 0; 1045 } else { 1046 // If the offset of the top constant (last entry in the table) 1047 // fits into simm13 we set the constant table base to the actual 1048 // table base. 1049 if (__ is_simm13(top_constant_offset())) { 1050 set_table_base_offset(0); 1051 disp = consts_size + offset; 1052 } else { 1053 // Otherwise we set the constant table base in the middle of the 1054 // constant table. 1055 int half_consts_size = consts_size / 2; 1056 assert(half_consts_size * 2 == consts_size, "sanity"); 1057 set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. 1058 disp = half_consts_size + offset; 1059 } 1060 } 1061 1062 __ get_pc(r); 1063 1064 if (disp != 0) { 1065 assert(r != O7, "need temporary"); 1066 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1067 } 1068 } 1069 else { 1070 // Materialize the constant table base. 1071 // Set the constant table base in the middle of the constant 1072 // table. 1073 int half_consts_size = consts_size / 2; 1074 assert(half_consts_size * 2 == consts_size, "sanity"); 1075 set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. 1076 1077 address baseaddr = cs->start() + half_consts_size; 1078 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1079 AddressLiteral base(baseaddr, rspec); 1080 __ set(base, r); 1081 } 1082 } 1083 1084 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1085 Unimplemented(); 1086 return 0; 1087 } 1088 1089 #ifndef PRODUCT 1090 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1091 char reg[128]; 1092 ra_->dump_register(this, reg); 1093 if (UseRDPCForConstantTableBase) { 1094 st->print("RDPC %s\t! constant table base", reg); 1095 } else { 1096 st->print("SET &constanttable,%s\t! constant table base", reg); 1097 } 1098 } 1099 #endif 1100 1101 1102 //============================================================================= 1103 1104 #ifndef PRODUCT 1105 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1106 Compile* C = ra_->C; 1107 1108 for (int i = 0; i < OptoPrologueNops; i++) { 1109 st->print_cr("NOP"); st->print("\t"); 1110 } 1111 1112 if( VerifyThread ) { 1113 st->print_cr("Verify_Thread"); st->print("\t"); 1114 } 1115 1116 size_t framesize = C->frame_slots() << LogBytesPerInt; 1117 1118 // Calls to C2R adapters often do not accept exceptional returns. 1119 // We require that their callers must bang for them. But be careful, because 1120 // some VM calls (such as call site linkage) can use several kilobytes of 1121 // stack. But the stack safety zone should account for that. 1122 // See bugs 4446381, 4468289, 4497237. 1123 if (C->need_stack_bang(framesize)) { 1124 st->print_cr("! stack bang"); st->print("\t"); 1125 } 1126 1127 if (Assembler::is_simm13(-framesize)) { 1128 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1129 } else { 1130 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1131 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1132 st->print ("SAVE R_SP,R_G3,R_SP"); 1133 } 1134 1135 } 1136 #endif 1137 1138 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1139 Compile* C = ra_->C; 1140 MacroAssembler _masm(&cbuf); 1141 1142 for (int i = 0; i < OptoPrologueNops; i++) { 1143 __ nop(); 1144 } 1145 1146 __ verify_thread(); 1147 1148 size_t framesize = C->frame_slots() << LogBytesPerInt; 1149 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1150 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1151 1152 // Calls to C2R adapters often do not accept exceptional returns. 1153 // We require that their callers must bang for them. But be careful, because 1154 // some VM calls (such as call site linkage) can use several kilobytes of 1155 // stack. But the stack safety zone should account for that. 1156 // See bugs 4446381, 4468289, 4497237. 1157 if (C->need_stack_bang(framesize)) { 1158 __ generate_stack_overflow_check(framesize); 1159 } 1160 1161 if (Assembler::is_simm13(-framesize)) { 1162 __ save(SP, -framesize, SP); 1163 } else { 1164 __ sethi(-framesize & ~0x3ff, G3); 1165 __ add(G3, -framesize & 0x3ff, G3); 1166 __ save(SP, G3, SP); 1167 } 1168 C->set_frame_complete( __ offset() ); 1169 } 1170 1171 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1172 return MachNode::size(ra_); 1173 } 1174 1175 int MachPrologNode::reloc() const { 1176 return 10; // a large enough number 1177 } 1178 1179 //============================================================================= 1180 #ifndef PRODUCT 1181 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1182 Compile* C = ra_->C; 1183 1184 if( do_polling() && ra_->C->is_method_compilation() ) { 1185 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1186 #ifdef _LP64 1187 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1188 #else 1189 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1190 #endif 1191 } 1192 1193 if( do_polling() ) 1194 st->print("RET\n\t"); 1195 1196 st->print("RESTORE"); 1197 } 1198 #endif 1199 1200 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1201 MacroAssembler _masm(&cbuf); 1202 Compile* C = ra_->C; 1203 1204 __ verify_thread(); 1205 1206 // If this does safepoint polling, then do it here 1207 if( do_polling() && ra_->C->is_method_compilation() ) { 1208 AddressLiteral polling_page(os::get_polling_page()); 1209 __ sethi(polling_page, L0); 1210 __ relocate(relocInfo::poll_return_type); 1211 __ ld_ptr( L0, 0, G0 ); 1212 } 1213 1214 // If this is a return, then stuff the restore in the delay slot 1215 if( do_polling() ) { 1216 __ ret(); 1217 __ delayed()->restore(); 1218 } else { 1219 __ restore(); 1220 } 1221 } 1222 1223 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1224 return MachNode::size(ra_); 1225 } 1226 1227 int MachEpilogNode::reloc() const { 1228 return 16; // a large enough number 1229 } 1230 1231 const Pipeline * MachEpilogNode::pipeline() const { 1232 return MachNode::pipeline_class(); 1233 } 1234 1235 int MachEpilogNode::safepoint_offset() const { 1236 assert( do_polling(), "no return for this epilog node"); 1237 return MacroAssembler::size_of_sethi(os::get_polling_page()); 1238 } 1239 1240 //============================================================================= 1241 1242 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1243 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1244 static enum RC rc_class( OptoReg::Name reg ) { 1245 if( !OptoReg::is_valid(reg) ) return rc_bad; 1246 if (OptoReg::is_stack(reg)) return rc_stack; 1247 VMReg r = OptoReg::as_VMReg(reg); 1248 if (r->is_Register()) return rc_int; 1249 assert(r->is_FloatRegister(), "must be"); 1250 return rc_float; 1251 } 1252 1253 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1254 if( cbuf ) { 1255 // Better yet would be some mechanism to handle variable-size matches correctly 1256 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1257 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1258 } else { 1259 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1260 } 1261 } 1262 #ifndef PRODUCT 1263 else if( !do_size ) { 1264 if( size != 0 ) st->print("\n\t"); 1265 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1266 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1267 } 1268 #endif 1269 return size+4; 1270 } 1271 1272 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1273 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1274 #ifndef PRODUCT 1275 else if( !do_size ) { 1276 if( size != 0 ) st->print("\n\t"); 1277 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1278 } 1279 #endif 1280 return size+4; 1281 } 1282 1283 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1284 PhaseRegAlloc *ra_, 1285 bool do_size, 1286 outputStream* st ) const { 1287 // Get registers to move 1288 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1289 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1290 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1291 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1292 1293 enum RC src_second_rc = rc_class(src_second); 1294 enum RC src_first_rc = rc_class(src_first); 1295 enum RC dst_second_rc = rc_class(dst_second); 1296 enum RC dst_first_rc = rc_class(dst_first); 1297 1298 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1299 1300 // Generate spill code! 1301 int size = 0; 1302 1303 if( src_first == dst_first && src_second == dst_second ) 1304 return size; // Self copy, no move 1305 1306 // -------------------------------------- 1307 // Check for mem-mem move. Load into unused float registers and fall into 1308 // the float-store case. 1309 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1310 int offset = ra_->reg2offset(src_first); 1311 // Further check for aligned-adjacent pair, so we can use a double load 1312 if( (src_first&1)==0 && src_first+1 == src_second ) { 1313 src_second = OptoReg::Name(R_F31_num); 1314 src_second_rc = rc_float; 1315 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1316 } else { 1317 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1318 } 1319 src_first = OptoReg::Name(R_F30_num); 1320 src_first_rc = rc_float; 1321 } 1322 1323 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1324 int offset = ra_->reg2offset(src_second); 1325 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1326 src_second = OptoReg::Name(R_F31_num); 1327 src_second_rc = rc_float; 1328 } 1329 1330 // -------------------------------------- 1331 // Check for float->int copy; requires a trip through memory 1332 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 1333 int offset = frame::register_save_words*wordSize; 1334 if( cbuf ) { 1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1336 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1337 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1338 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1339 } 1340 #ifndef PRODUCT 1341 else if( !do_size ) { 1342 if( size != 0 ) st->print("\n\t"); 1343 st->print( "SUB R_SP,16,R_SP\n"); 1344 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1345 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1346 st->print("\tADD R_SP,16,R_SP\n"); 1347 } 1348 #endif 1349 size += 16; 1350 } 1351 1352 // -------------------------------------- 1353 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1354 // In such cases, I have to do the big-endian swap. For aligned targets, the 1355 // hardware does the flop for me. Doubles are always aligned, so no problem 1356 // there. Misaligned sources only come from native-long-returns (handled 1357 // special below). 1358 #ifndef _LP64 1359 if( src_first_rc == rc_int && // source is already big-endian 1360 src_second_rc != rc_bad && // 64-bit move 1361 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1362 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1363 // Do the big-endian flop. 1364 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1365 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1366 } 1367 #endif 1368 1369 // -------------------------------------- 1370 // Check for integer reg-reg copy 1371 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1372 #ifndef _LP64 1373 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1374 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1375 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1376 // operand contains the least significant word of the 64-bit value and vice versa. 1377 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1378 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1379 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1380 if( cbuf ) { 1381 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1382 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1383 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1384 #ifndef PRODUCT 1385 } else if( !do_size ) { 1386 if( size != 0 ) st->print("\n\t"); 1387 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1388 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1389 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1390 #endif 1391 } 1392 return size+12; 1393 } 1394 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1395 // returning a long value in I0/I1 1396 // a SpillCopy must be able to target a return instruction's reg_class 1397 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1398 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1399 // operand contains the least significant word of the 64-bit value and vice versa. 1400 OptoReg::Name tdest = dst_first; 1401 1402 if (src_first == dst_first) { 1403 tdest = OptoReg::Name(R_O7_num); 1404 size += 4; 1405 } 1406 1407 if( cbuf ) { 1408 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1409 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1410 // ShrL_reg_imm6 1411 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1412 // ShrR_reg_imm6 src, 0, dst 1413 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1414 if (tdest != dst_first) { 1415 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1416 } 1417 } 1418 #ifndef PRODUCT 1419 else if( !do_size ) { 1420 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1421 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1422 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1423 if (tdest != dst_first) { 1424 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1425 } 1426 } 1427 #endif // PRODUCT 1428 return size+8; 1429 } 1430 #endif // !_LP64 1431 // Else normal reg-reg copy 1432 assert( src_second != dst_first, "smashed second before evacuating it" ); 1433 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1434 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1435 // This moves an aligned adjacent pair. 1436 // See if we are done. 1437 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1438 return size; 1439 } 1440 1441 // Check for integer store 1442 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1443 int offset = ra_->reg2offset(dst_first); 1444 // Further check for aligned-adjacent pair, so we can use a double store 1445 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1446 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1447 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1448 } 1449 1450 // Check for integer load 1451 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1452 int offset = ra_->reg2offset(src_first); 1453 // Further check for aligned-adjacent pair, so we can use a double load 1454 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1455 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1456 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1457 } 1458 1459 // Check for float reg-reg copy 1460 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1461 // Further check for aligned-adjacent pair, so we can use a double move 1462 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1463 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1464 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1465 } 1466 1467 // Check for float store 1468 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1469 int offset = ra_->reg2offset(dst_first); 1470 // Further check for aligned-adjacent pair, so we can use a double store 1471 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1472 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1473 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1474 } 1475 1476 // Check for float load 1477 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1478 int offset = ra_->reg2offset(src_first); 1479 // Further check for aligned-adjacent pair, so we can use a double load 1480 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1481 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1482 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1483 } 1484 1485 // -------------------------------------------------------------------- 1486 // Check for hi bits still needing moving. Only happens for misaligned 1487 // arguments to native calls. 1488 if( src_second == dst_second ) 1489 return size; // Self copy; no move 1490 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1491 1492 #ifndef _LP64 1493 // In the LP64 build, all registers can be moved as aligned/adjacent 1494 // pairs, so there's never any need to move the high bits separately. 1495 // The 32-bit builds have to deal with the 32-bit ABI which can force 1496 // all sorts of silly alignment problems. 1497 1498 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1499 // 32-bits of a 64-bit register, but are needed in low bits of another 1500 // register (else it's a hi-bits-to-hi-bits copy which should have 1501 // happened already as part of a 64-bit move) 1502 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1503 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1504 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1505 // Shift src_second down to dst_second's low bits. 1506 if( cbuf ) { 1507 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1508 #ifndef PRODUCT 1509 } else if( !do_size ) { 1510 if( size != 0 ) st->print("\n\t"); 1511 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1512 #endif 1513 } 1514 return size+4; 1515 } 1516 1517 // Check for high word integer store. Must down-shift the hi bits 1518 // into a temp register, then fall into the case of storing int bits. 1519 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1520 // Shift src_second down to dst_second's low bits. 1521 if( cbuf ) { 1522 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1523 #ifndef PRODUCT 1524 } else if( !do_size ) { 1525 if( size != 0 ) st->print("\n\t"); 1526 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1527 #endif 1528 } 1529 size+=4; 1530 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1531 } 1532 1533 // Check for high word integer load 1534 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1535 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1536 1537 // Check for high word integer store 1538 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1539 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1540 1541 // Check for high word float store 1542 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1543 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1544 1545 #endif // !_LP64 1546 1547 Unimplemented(); 1548 } 1549 1550 #ifndef PRODUCT 1551 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1552 implementation( NULL, ra_, false, st ); 1553 } 1554 #endif 1555 1556 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1557 implementation( &cbuf, ra_, false, NULL ); 1558 } 1559 1560 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1561 return implementation( NULL, ra_, true, NULL ); 1562 } 1563 1564 //============================================================================= 1565 #ifndef PRODUCT 1566 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1567 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1568 } 1569 #endif 1570 1571 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1572 MacroAssembler _masm(&cbuf); 1573 for(int i = 0; i < _count; i += 1) { 1574 __ nop(); 1575 } 1576 } 1577 1578 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1579 return 4 * _count; 1580 } 1581 1582 1583 //============================================================================= 1584 #ifndef PRODUCT 1585 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1586 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1587 int reg = ra_->get_reg_first(this); 1588 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1589 } 1590 #endif 1591 1592 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1593 MacroAssembler _masm(&cbuf); 1594 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1595 int reg = ra_->get_encode(this); 1596 1597 if (Assembler::is_simm13(offset)) { 1598 __ add(SP, offset, reg_to_register_object(reg)); 1599 } else { 1600 __ set(offset, O7); 1601 __ add(SP, O7, reg_to_register_object(reg)); 1602 } 1603 } 1604 1605 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1606 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1607 assert(ra_ == ra_->C->regalloc(), "sanity"); 1608 return ra_->C->scratch_emit_size(this); 1609 } 1610 1611 //============================================================================= 1612 1613 // emit call stub, compiled java to interpretor 1614 void emit_java_to_interp(CodeBuffer &cbuf ) { 1615 1616 // Stub is fixed up when the corresponding call is converted from calling 1617 // compiled code to calling interpreted code. 1618 // set (empty), G5 1619 // jmp -1 1620 1621 address mark = cbuf.insts_mark(); // get mark within main instrs section 1622 1623 MacroAssembler _masm(&cbuf); 1624 1625 address base = 1626 __ start_a_stub(Compile::MAX_stubs_size); 1627 if (base == NULL) return; // CodeBuffer::expand failed 1628 1629 // static stub relocation stores the instruction address of the call 1630 __ relocate(static_stub_Relocation::spec(mark)); 1631 1632 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1633 1634 __ set_inst_mark(); 1635 AddressLiteral addrlit(-1); 1636 __ JUMP(addrlit, G3, 0); 1637 1638 __ delayed()->nop(); 1639 1640 // Update current stubs pointer and restore code_end. 1641 __ end_a_stub(); 1642 } 1643 1644 // size of call stub, compiled java to interpretor 1645 uint size_java_to_interp() { 1646 // This doesn't need to be accurate but it must be larger or equal to 1647 // the real size of the stub. 1648 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1649 NativeJump::instruction_size + // sethi; jmp; nop 1650 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1651 } 1652 // relocation entries for call stub, compiled java to interpretor 1653 uint reloc_java_to_interp() { 1654 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1655 } 1656 1657 1658 //============================================================================= 1659 #ifndef PRODUCT 1660 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1661 st->print_cr("\nUEP:"); 1662 #ifdef _LP64 1663 if (UseCompressedOops) { 1664 assert(Universe::heap() != NULL, "java heap should be initialized"); 1665 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1666 st->print_cr("\tSLL R_G5,3,R_G5"); 1667 if (Universe::narrow_oop_base() != NULL) 1668 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1669 } else { 1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1671 } 1672 st->print_cr("\tCMP R_G5,R_G3" ); 1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1674 #else // _LP64 1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1676 st->print_cr("\tCMP R_G5,R_G3" ); 1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1678 #endif // _LP64 1679 } 1680 #endif 1681 1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1683 MacroAssembler _masm(&cbuf); 1684 Label L; 1685 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1686 Register temp_reg = G3; 1687 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1688 1689 // Load klass from receiver 1690 __ load_klass(O0, temp_reg); 1691 // Compare against expected klass 1692 __ cmp(temp_reg, G5_ic_reg); 1693 // Branch to miss code, checks xcc or icc depending 1694 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1695 } 1696 1697 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1698 return MachNode::size(ra_); 1699 } 1700 1701 1702 //============================================================================= 1703 1704 uint size_exception_handler() { 1705 if (TraceJumps) { 1706 return (400); // just a guess 1707 } 1708 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1709 } 1710 1711 uint size_deopt_handler() { 1712 if (TraceJumps) { 1713 return (400); // just a guess 1714 } 1715 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1716 } 1717 1718 // Emit exception handler code. 1719 int emit_exception_handler(CodeBuffer& cbuf) { 1720 Register temp_reg = G3; 1721 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1722 MacroAssembler _masm(&cbuf); 1723 1724 address base = 1725 __ start_a_stub(size_exception_handler()); 1726 if (base == NULL) return 0; // CodeBuffer::expand failed 1727 1728 int offset = __ offset(); 1729 1730 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1731 __ delayed()->nop(); 1732 1733 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1734 1735 __ end_a_stub(); 1736 1737 return offset; 1738 } 1739 1740 int emit_deopt_handler(CodeBuffer& cbuf) { 1741 // Can't use any of the current frame's registers as we may have deopted 1742 // at a poll and everything (including G3) can be live. 1743 Register temp_reg = L0; 1744 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1745 MacroAssembler _masm(&cbuf); 1746 1747 address base = 1748 __ start_a_stub(size_deopt_handler()); 1749 if (base == NULL) return 0; // CodeBuffer::expand failed 1750 1751 int offset = __ offset(); 1752 __ save_frame(0); 1753 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1754 __ delayed()->restore(); 1755 1756 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1757 1758 __ end_a_stub(); 1759 return offset; 1760 1761 } 1762 1763 // Given a register encoding, produce a Integer Register object 1764 static Register reg_to_register_object(int register_encoding) { 1765 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1766 return as_Register(register_encoding); 1767 } 1768 1769 // Given a register encoding, produce a single-precision Float Register object 1770 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1771 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1772 return as_SingleFloatRegister(register_encoding); 1773 } 1774 1775 // Given a register encoding, produce a double-precision Float Register object 1776 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1777 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1778 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1779 return as_DoubleFloatRegister(register_encoding); 1780 } 1781 1782 const bool Matcher::match_rule_supported(int opcode) { 1783 if (!has_match_rule(opcode)) 1784 return false; 1785 1786 switch (opcode) { 1787 case Op_CountLeadingZerosI: 1788 case Op_CountLeadingZerosL: 1789 case Op_CountTrailingZerosI: 1790 case Op_CountTrailingZerosL: 1791 if (!UsePopCountInstruction) 1792 return false; 1793 break; 1794 } 1795 1796 return true; // Per default match rules are supported. 1797 } 1798 1799 int Matcher::regnum_to_fpu_offset(int regnum) { 1800 return regnum - 32; // The FP registers are in the second chunk 1801 } 1802 1803 #ifdef ASSERT 1804 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1805 #endif 1806 1807 // Vector width in bytes 1808 const uint Matcher::vector_width_in_bytes(void) { 1809 return 8; 1810 } 1811 1812 // Vector ideal reg 1813 const uint Matcher::vector_ideal_reg(void) { 1814 return Op_RegD; 1815 } 1816 1817 // USII supports fxtof through the whole range of number, USIII doesn't 1818 const bool Matcher::convL2FSupported(void) { 1819 return VM_Version::has_fast_fxtof(); 1820 } 1821 1822 // Is this branch offset short enough that a short branch can be used? 1823 // 1824 // NOTE: If the platform does not provide any short branch variants, then 1825 // this method should return false for offset 0. 1826 bool Matcher::is_short_branch_offset(int rule, int offset) { 1827 return false; 1828 } 1829 1830 const bool Matcher::isSimpleConstant64(jlong value) { 1831 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1832 // Depends on optimizations in MacroAssembler::setx. 1833 int hi = (int)(value >> 32); 1834 int lo = (int)(value & ~0); 1835 return (hi == 0) || (hi == -1) || (lo == 0); 1836 } 1837 1838 // No scaling for the parameter the ClearArray node. 1839 const bool Matcher::init_array_count_is_in_bytes = true; 1840 1841 // Threshold size for cleararray. 1842 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1843 1844 // Should the Matcher clone shifts on addressing modes, expecting them to 1845 // be subsumed into complex addressing expressions or compute them into 1846 // registers? True for Intel but false for most RISCs 1847 const bool Matcher::clone_shift_expressions = false; 1848 1849 bool Matcher::narrow_oop_use_complex_address() { 1850 NOT_LP64(ShouldNotCallThis()); 1851 assert(UseCompressedOops, "only for compressed oops code"); 1852 return false; 1853 } 1854 1855 // Is it better to copy float constants, or load them directly from memory? 1856 // Intel can load a float constant from a direct address, requiring no 1857 // extra registers. Most RISCs will have to materialize an address into a 1858 // register first, so they would do better to copy the constant from stack. 1859 const bool Matcher::rematerialize_float_constants = false; 1860 1861 // If CPU can load and store mis-aligned doubles directly then no fixup is 1862 // needed. Else we split the double into 2 integer pieces and move it 1863 // piece-by-piece. Only happens when passing doubles into C code as the 1864 // Java calling convention forces doubles to be aligned. 1865 #ifdef _LP64 1866 const bool Matcher::misaligned_doubles_ok = true; 1867 #else 1868 const bool Matcher::misaligned_doubles_ok = false; 1869 #endif 1870 1871 // No-op on SPARC. 1872 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1873 } 1874 1875 // Advertise here if the CPU requires explicit rounding operations 1876 // to implement the UseStrictFP mode. 1877 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1878 1879 // Are floats conerted to double when stored to stack during deoptimization? 1880 // Sparc does not handle callee-save floats. 1881 bool Matcher::float_in_double() { return false; } 1882 1883 // Do ints take an entire long register or just half? 1884 // Note that we if-def off of _LP64. 1885 // The relevant question is how the int is callee-saved. In _LP64 1886 // the whole long is written but de-opt'ing will have to extract 1887 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1888 #ifdef _LP64 1889 const bool Matcher::int_in_long = true; 1890 #else 1891 const bool Matcher::int_in_long = false; 1892 #endif 1893 1894 // Return whether or not this register is ever used as an argument. This 1895 // function is used on startup to build the trampoline stubs in generateOptoStub. 1896 // Registers not mentioned will be killed by the VM call in the trampoline, and 1897 // arguments in those registers not be available to the callee. 1898 bool Matcher::can_be_java_arg( int reg ) { 1899 // Standard sparc 6 args in registers 1900 if( reg == R_I0_num || 1901 reg == R_I1_num || 1902 reg == R_I2_num || 1903 reg == R_I3_num || 1904 reg == R_I4_num || 1905 reg == R_I5_num ) return true; 1906 #ifdef _LP64 1907 // 64-bit builds can pass 64-bit pointers and longs in 1908 // the high I registers 1909 if( reg == R_I0H_num || 1910 reg == R_I1H_num || 1911 reg == R_I2H_num || 1912 reg == R_I3H_num || 1913 reg == R_I4H_num || 1914 reg == R_I5H_num ) return true; 1915 1916 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1917 return true; 1918 } 1919 1920 #else 1921 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1922 // Longs cannot be passed in O regs, because O regs become I regs 1923 // after a 'save' and I regs get their high bits chopped off on 1924 // interrupt. 1925 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1926 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1927 #endif 1928 // A few float args in registers 1929 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1930 1931 return false; 1932 } 1933 1934 bool Matcher::is_spillable_arg( int reg ) { 1935 return can_be_java_arg(reg); 1936 } 1937 1938 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1939 // Use hardware SDIVX instruction when it is 1940 // faster than a code which use multiply. 1941 return VM_Version::has_fast_idiv(); 1942 } 1943 1944 // Register for DIVI projection of divmodI 1945 RegMask Matcher::divI_proj_mask() { 1946 ShouldNotReachHere(); 1947 return RegMask(); 1948 } 1949 1950 // Register for MODI projection of divmodI 1951 RegMask Matcher::modI_proj_mask() { 1952 ShouldNotReachHere(); 1953 return RegMask(); 1954 } 1955 1956 // Register for DIVL projection of divmodL 1957 RegMask Matcher::divL_proj_mask() { 1958 ShouldNotReachHere(); 1959 return RegMask(); 1960 } 1961 1962 // Register for MODL projection of divmodL 1963 RegMask Matcher::modL_proj_mask() { 1964 ShouldNotReachHere(); 1965 return RegMask(); 1966 } 1967 1968 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1969 return L7_REGP_mask; 1970 } 1971 1972 %} 1973 1974 1975 // The intptr_t operand types, defined by textual substitution. 1976 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1977 #ifdef _LP64 1978 #define immX immL 1979 #define immX13 immL13 1980 #define immX13m7 immL13m7 1981 #define iRegX iRegL 1982 #define g1RegX g1RegL 1983 #else 1984 #define immX immI 1985 #define immX13 immI13 1986 #define immX13m7 immI13m7 1987 #define iRegX iRegI 1988 #define g1RegX g1RegI 1989 #endif 1990 1991 //----------ENCODING BLOCK----------------------------------------------------- 1992 // This block specifies the encoding classes used by the compiler to output 1993 // byte streams. Encoding classes are parameterized macros used by 1994 // Machine Instruction Nodes in order to generate the bit encoding of the 1995 // instruction. Operands specify their base encoding interface with the 1996 // interface keyword. There are currently supported four interfaces, 1997 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1998 // operand to generate a function which returns its register number when 1999 // queried. CONST_INTER causes an operand to generate a function which 2000 // returns the value of the constant when queried. MEMORY_INTER causes an 2001 // operand to generate four functions which return the Base Register, the 2002 // Index Register, the Scale Value, and the Offset Value of the operand when 2003 // queried. COND_INTER causes an operand to generate six functions which 2004 // return the encoding code (ie - encoding bits for the instruction) 2005 // associated with each basic boolean condition for a conditional instruction. 2006 // 2007 // Instructions specify two basic values for encoding. Again, a function 2008 // is available to check if the constant displacement is an oop. They use the 2009 // ins_encode keyword to specify their encoding classes (which must be 2010 // a sequence of enc_class names, and their parameters, specified in 2011 // the encoding block), and they use the 2012 // opcode keyword to specify, in order, their primary, secondary, and 2013 // tertiary opcode. Only the opcode sections which a particular instruction 2014 // needs for encoding need to be specified. 2015 encode %{ 2016 enc_class enc_untested %{ 2017 #ifdef ASSERT 2018 MacroAssembler _masm(&cbuf); 2019 __ untested("encoding"); 2020 #endif 2021 %} 2022 2023 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2024 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 2025 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2026 %} 2027 2028 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2029 emit_form3_mem_reg(cbuf, this, $primary, -1, 2030 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2031 %} 2032 2033 enc_class form3_mem_prefetch_read( memory mem ) %{ 2034 emit_form3_mem_reg(cbuf, this, $primary, -1, 2035 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2036 %} 2037 2038 enc_class form3_mem_prefetch_write( memory mem ) %{ 2039 emit_form3_mem_reg(cbuf, this, $primary, -1, 2040 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2041 %} 2042 2043 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2044 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 2045 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 2046 guarantee($mem$$index == R_G0_enc, "double index?"); 2047 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2048 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2049 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2050 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2051 %} 2052 2053 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2054 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 2055 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 2056 guarantee($mem$$index == R_G0_enc, "double index?"); 2057 // Load long with 2 instructions 2058 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2059 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2060 %} 2061 2062 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2063 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2064 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2065 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2066 %} 2067 2068 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2069 // Encode a reg-reg copy. If it is useless, then empty encoding. 2070 if( $rs2$$reg != $rd$$reg ) 2071 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2072 %} 2073 2074 // Target lo half of long 2075 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2076 // Encode a reg-reg copy. If it is useless, then empty encoding. 2077 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2078 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2079 %} 2080 2081 // Source lo half of long 2082 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2083 // Encode a reg-reg copy. If it is useless, then empty encoding. 2084 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2085 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2086 %} 2087 2088 // Target hi half of long 2089 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2090 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2091 %} 2092 2093 // Source lo half of long, and leave it sign extended. 2094 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2095 // Sign extend low half 2096 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2097 %} 2098 2099 // Source hi half of long, and leave it sign extended. 2100 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2101 // Shift high half to low half 2102 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2103 %} 2104 2105 // Source hi half of long 2106 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2107 // Encode a reg-reg copy. If it is useless, then empty encoding. 2108 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2109 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2110 %} 2111 2112 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2113 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2114 %} 2115 2116 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2117 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2118 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2119 %} 2120 2121 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2122 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2123 // clear if nothing else is happening 2124 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2125 // blt,a,pn done 2126 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2127 // mov dst,-1 in delay slot 2128 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2129 %} 2130 2131 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2132 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2133 %} 2134 2135 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2136 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2137 %} 2138 2139 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2140 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2141 %} 2142 2143 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2144 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2145 %} 2146 2147 enc_class move_return_pc_to_o1() %{ 2148 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2149 %} 2150 2151 #ifdef _LP64 2152 /* %%% merge with enc_to_bool */ 2153 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2154 MacroAssembler _masm(&cbuf); 2155 2156 Register src_reg = reg_to_register_object($src$$reg); 2157 Register dst_reg = reg_to_register_object($dst$$reg); 2158 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2159 %} 2160 #endif 2161 2162 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2163 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2164 MacroAssembler _masm(&cbuf); 2165 2166 Register p_reg = reg_to_register_object($p$$reg); 2167 Register q_reg = reg_to_register_object($q$$reg); 2168 Register y_reg = reg_to_register_object($y$$reg); 2169 Register tmp_reg = reg_to_register_object($tmp$$reg); 2170 2171 __ subcc( p_reg, q_reg, p_reg ); 2172 __ add ( p_reg, y_reg, tmp_reg ); 2173 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2174 %} 2175 2176 enc_class form_d2i_helper(regD src, regF dst) %{ 2177 // fcmp %fcc0,$src,$src 2178 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2179 // branch %fcc0 not-nan, predict taken 2180 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2181 // fdtoi $src,$dst 2182 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2183 // fitos $dst,$dst (if nan) 2184 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2185 // clear $dst (if nan) 2186 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2187 // carry on here... 2188 %} 2189 2190 enc_class form_d2l_helper(regD src, regD dst) %{ 2191 // fcmp %fcc0,$src,$src check for NAN 2192 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2193 // branch %fcc0 not-nan, predict taken 2194 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2195 // fdtox $src,$dst convert in delay slot 2196 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2197 // fxtod $dst,$dst (if nan) 2198 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2199 // clear $dst (if nan) 2200 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2201 // carry on here... 2202 %} 2203 2204 enc_class form_f2i_helper(regF src, regF dst) %{ 2205 // fcmps %fcc0,$src,$src 2206 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2207 // branch %fcc0 not-nan, predict taken 2208 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2209 // fstoi $src,$dst 2210 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2211 // fitos $dst,$dst (if nan) 2212 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2213 // clear $dst (if nan) 2214 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2215 // carry on here... 2216 %} 2217 2218 enc_class form_f2l_helper(regF src, regD dst) %{ 2219 // fcmps %fcc0,$src,$src 2220 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2221 // branch %fcc0 not-nan, predict taken 2222 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2223 // fstox $src,$dst 2224 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2225 // fxtod $dst,$dst (if nan) 2226 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2227 // clear $dst (if nan) 2228 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2229 // carry on here... 2230 %} 2231 2232 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2233 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2234 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2235 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2236 2237 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2238 2239 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2240 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2241 2242 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2243 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2244 %} 2245 2246 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2247 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2248 %} 2249 2250 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2251 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2252 %} 2253 2254 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2255 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2256 %} 2257 2258 enc_class form3_convI2F(regF rs2, regF rd) %{ 2259 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2260 %} 2261 2262 // Encloding class for traceable jumps 2263 enc_class form_jmpl(g3RegP dest) %{ 2264 emit_jmpl(cbuf, $dest$$reg); 2265 %} 2266 2267 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2268 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2269 %} 2270 2271 enc_class form2_nop() %{ 2272 emit_nop(cbuf); 2273 %} 2274 2275 enc_class form2_illtrap() %{ 2276 emit_illtrap(cbuf); 2277 %} 2278 2279 2280 // Compare longs and convert into -1, 0, 1. 2281 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2282 // CMP $src1,$src2 2283 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2284 // blt,a,pn done 2285 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2286 // mov dst,-1 in delay slot 2287 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2288 // bgt,a,pn done 2289 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2290 // mov dst,1 in delay slot 2291 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2292 // CLR $dst 2293 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2294 %} 2295 2296 enc_class enc_PartialSubtypeCheck() %{ 2297 MacroAssembler _masm(&cbuf); 2298 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2299 __ delayed()->nop(); 2300 %} 2301 2302 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2303 MacroAssembler _masm(&cbuf); 2304 Label &L = *($labl$$label); 2305 Assembler::Predict predict_taken = 2306 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2307 2308 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2309 __ delayed()->nop(); 2310 %} 2311 2312 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2313 MacroAssembler _masm(&cbuf); 2314 Label &L = *($labl$$label); 2315 Assembler::Predict predict_taken = 2316 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2317 2318 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2319 __ delayed()->nop(); 2320 %} 2321 2322 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2323 MacroAssembler _masm(&cbuf); 2324 Label &L = *($labl$$label); 2325 Assembler::Predict predict_taken = 2326 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2327 2328 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2329 __ delayed()->nop(); 2330 %} 2331 2332 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2333 MacroAssembler _masm(&cbuf); 2334 Label &L = *($labl$$label); 2335 Assembler::Predict predict_taken = 2336 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2337 2338 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2339 __ delayed()->nop(); 2340 %} 2341 2342 enc_class enc_ba( Label labl ) %{ 2343 MacroAssembler _masm(&cbuf); 2344 Label &L = *($labl$$label); 2345 __ ba(false, L); 2346 __ delayed()->nop(); 2347 %} 2348 2349 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2350 MacroAssembler _masm(&cbuf); 2351 Label &L = *$labl$$label; 2352 Assembler::Predict predict_taken = 2353 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2354 2355 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2356 __ delayed()->nop(); 2357 %} 2358 2359 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2360 int op = (Assembler::arith_op << 30) | 2361 ($dst$$reg << 25) | 2362 (Assembler::movcc_op3 << 19) | 2363 (1 << 18) | // cc2 bit for 'icc' 2364 ($cmp$$cmpcode << 14) | 2365 (0 << 13) | // select register move 2366 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2367 ($src$$reg << 0); 2368 cbuf.insts()->emit_int32(op); 2369 %} 2370 2371 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2372 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2373 int op = (Assembler::arith_op << 30) | 2374 ($dst$$reg << 25) | 2375 (Assembler::movcc_op3 << 19) | 2376 (1 << 18) | // cc2 bit for 'icc' 2377 ($cmp$$cmpcode << 14) | 2378 (1 << 13) | // select immediate move 2379 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2380 (simm11 << 0); 2381 cbuf.insts()->emit_int32(op); 2382 %} 2383 2384 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2385 int op = (Assembler::arith_op << 30) | 2386 ($dst$$reg << 25) | 2387 (Assembler::movcc_op3 << 19) | 2388 (0 << 18) | // cc2 bit for 'fccX' 2389 ($cmp$$cmpcode << 14) | 2390 (0 << 13) | // select register move 2391 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2392 ($src$$reg << 0); 2393 cbuf.insts()->emit_int32(op); 2394 %} 2395 2396 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2397 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2398 int op = (Assembler::arith_op << 30) | 2399 ($dst$$reg << 25) | 2400 (Assembler::movcc_op3 << 19) | 2401 (0 << 18) | // cc2 bit for 'fccX' 2402 ($cmp$$cmpcode << 14) | 2403 (1 << 13) | // select immediate move 2404 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2405 (simm11 << 0); 2406 cbuf.insts()->emit_int32(op); 2407 %} 2408 2409 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2410 int op = (Assembler::arith_op << 30) | 2411 ($dst$$reg << 25) | 2412 (Assembler::fpop2_op3 << 19) | 2413 (0 << 18) | 2414 ($cmp$$cmpcode << 14) | 2415 (1 << 13) | // select register move 2416 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2417 ($primary << 5) | // select single, double or quad 2418 ($src$$reg << 0); 2419 cbuf.insts()->emit_int32(op); 2420 %} 2421 2422 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2423 int op = (Assembler::arith_op << 30) | 2424 ($dst$$reg << 25) | 2425 (Assembler::fpop2_op3 << 19) | 2426 (0 << 18) | 2427 ($cmp$$cmpcode << 14) | 2428 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2429 ($primary << 5) | // select single, double or quad 2430 ($src$$reg << 0); 2431 cbuf.insts()->emit_int32(op); 2432 %} 2433 2434 // Used by the MIN/MAX encodings. Same as a CMOV, but 2435 // the condition comes from opcode-field instead of an argument. 2436 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2437 int op = (Assembler::arith_op << 30) | 2438 ($dst$$reg << 25) | 2439 (Assembler::movcc_op3 << 19) | 2440 (1 << 18) | // cc2 bit for 'icc' 2441 ($primary << 14) | 2442 (0 << 13) | // select register move 2443 (0 << 11) | // cc1, cc0 bits for 'icc' 2444 ($src$$reg << 0); 2445 cbuf.insts()->emit_int32(op); 2446 %} 2447 2448 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2449 int op = (Assembler::arith_op << 30) | 2450 ($dst$$reg << 25) | 2451 (Assembler::movcc_op3 << 19) | 2452 (6 << 16) | // cc2 bit for 'xcc' 2453 ($primary << 14) | 2454 (0 << 13) | // select register move 2455 (0 << 11) | // cc1, cc0 bits for 'icc' 2456 ($src$$reg << 0); 2457 cbuf.insts()->emit_int32(op); 2458 %} 2459 2460 enc_class Set13( immI13 src, iRegI rd ) %{ 2461 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2462 %} 2463 2464 enc_class SetHi22( immI src, iRegI rd ) %{ 2465 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2466 %} 2467 2468 enc_class Set32( immI src, iRegI rd ) %{ 2469 MacroAssembler _masm(&cbuf); 2470 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2471 %} 2472 2473 enc_class call_epilog %{ 2474 if( VerifyStackAtCalls ) { 2475 MacroAssembler _masm(&cbuf); 2476 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2477 Register temp_reg = G3; 2478 __ add(SP, framesize, temp_reg); 2479 __ cmp(temp_reg, FP); 2480 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2481 } 2482 %} 2483 2484 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2485 // to G1 so the register allocator will not have to deal with the misaligned register 2486 // pair. 2487 enc_class adjust_long_from_native_call %{ 2488 #ifndef _LP64 2489 if (returns_long()) { 2490 // sllx O0,32,O0 2491 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2492 // srl O1,0,O1 2493 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2494 // or O0,O1,G1 2495 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2496 } 2497 #endif 2498 %} 2499 2500 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2501 // CALL directly to the runtime 2502 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2503 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2504 /*preserve_g2=*/true, /*force far call*/true); 2505 %} 2506 2507 enc_class preserve_SP %{ 2508 MacroAssembler _masm(&cbuf); 2509 __ mov(SP, L7_mh_SP_save); 2510 %} 2511 2512 enc_class restore_SP %{ 2513 MacroAssembler _masm(&cbuf); 2514 __ mov(L7_mh_SP_save, SP); 2515 %} 2516 2517 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2518 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2519 // who we intended to call. 2520 if ( !_method ) { 2521 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2522 } else if (_optimized_virtual) { 2523 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2524 } else { 2525 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2526 } 2527 if( _method ) { // Emit stub for static call 2528 emit_java_to_interp(cbuf); 2529 } 2530 %} 2531 2532 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2533 MacroAssembler _masm(&cbuf); 2534 __ set_inst_mark(); 2535 int vtable_index = this->_vtable_index; 2536 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2537 if (vtable_index < 0) { 2538 // must be invalid_vtable_index, not nonvirtual_vtable_index 2539 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2540 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2541 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2542 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2543 // !!!!! 2544 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2545 // emit_call_dynamic_prologue( cbuf ); 2546 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2547 2548 address virtual_call_oop_addr = __ inst_mark(); 2549 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2550 // who we intended to call. 2551 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2552 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2553 } else { 2554 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2555 // Just go thru the vtable 2556 // get receiver klass (receiver already checked for non-null) 2557 // If we end up going thru a c2i adapter interpreter expects method in G5 2558 int off = __ offset(); 2559 __ load_klass(O0, G3_scratch); 2560 int klass_load_size; 2561 if (UseCompressedOops) { 2562 assert(Universe::heap() != NULL, "java heap should be initialized"); 2563 if (Universe::narrow_oop_base() == NULL) 2564 klass_load_size = 2*BytesPerInstWord; 2565 else 2566 klass_load_size = 3*BytesPerInstWord; 2567 } else { 2568 klass_load_size = 1*BytesPerInstWord; 2569 } 2570 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2571 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2572 if( __ is_simm13(v_off) ) { 2573 __ ld_ptr(G3, v_off, G5_method); 2574 } else { 2575 // Generate 2 instructions 2576 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2577 __ or3(G5_method, v_off & 0x3ff, G5_method); 2578 // ld_ptr, set_hi, set 2579 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2580 "Unexpected instruction size(s)"); 2581 __ ld_ptr(G3, G5_method, G5_method); 2582 } 2583 // NOTE: for vtable dispatches, the vtable entry will never be null. 2584 // However it may very well end up in handle_wrong_method if the 2585 // method is abstract for the particular class. 2586 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2587 // jump to target (either compiled code or c2iadapter) 2588 __ jmpl(G3_scratch, G0, O7); 2589 __ delayed()->nop(); 2590 } 2591 %} 2592 2593 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2594 MacroAssembler _masm(&cbuf); 2595 2596 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2597 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2598 // we might be calling a C2I adapter which needs it. 2599 2600 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2601 // Load nmethod 2602 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2603 2604 // CALL to compiled java, indirect the contents of G3 2605 __ set_inst_mark(); 2606 __ callr(temp_reg, G0); 2607 __ delayed()->nop(); 2608 %} 2609 2610 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2611 MacroAssembler _masm(&cbuf); 2612 Register Rdividend = reg_to_register_object($src1$$reg); 2613 Register Rdivisor = reg_to_register_object($src2$$reg); 2614 Register Rresult = reg_to_register_object($dst$$reg); 2615 2616 __ sra(Rdivisor, 0, Rdivisor); 2617 __ sra(Rdividend, 0, Rdividend); 2618 __ sdivx(Rdividend, Rdivisor, Rresult); 2619 %} 2620 2621 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2622 MacroAssembler _masm(&cbuf); 2623 2624 Register Rdividend = reg_to_register_object($src1$$reg); 2625 int divisor = $imm$$constant; 2626 Register Rresult = reg_to_register_object($dst$$reg); 2627 2628 __ sra(Rdividend, 0, Rdividend); 2629 __ sdivx(Rdividend, divisor, Rresult); 2630 %} 2631 2632 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2633 MacroAssembler _masm(&cbuf); 2634 Register Rsrc1 = reg_to_register_object($src1$$reg); 2635 Register Rsrc2 = reg_to_register_object($src2$$reg); 2636 Register Rdst = reg_to_register_object($dst$$reg); 2637 2638 __ sra( Rsrc1, 0, Rsrc1 ); 2639 __ sra( Rsrc2, 0, Rsrc2 ); 2640 __ mulx( Rsrc1, Rsrc2, Rdst ); 2641 __ srlx( Rdst, 32, Rdst ); 2642 %} 2643 2644 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2645 MacroAssembler _masm(&cbuf); 2646 Register Rdividend = reg_to_register_object($src1$$reg); 2647 Register Rdivisor = reg_to_register_object($src2$$reg); 2648 Register Rresult = reg_to_register_object($dst$$reg); 2649 Register Rscratch = reg_to_register_object($scratch$$reg); 2650 2651 assert(Rdividend != Rscratch, ""); 2652 assert(Rdivisor != Rscratch, ""); 2653 2654 __ sra(Rdividend, 0, Rdividend); 2655 __ sra(Rdivisor, 0, Rdivisor); 2656 __ sdivx(Rdividend, Rdivisor, Rscratch); 2657 __ mulx(Rscratch, Rdivisor, Rscratch); 2658 __ sub(Rdividend, Rscratch, Rresult); 2659 %} 2660 2661 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2662 MacroAssembler _masm(&cbuf); 2663 2664 Register Rdividend = reg_to_register_object($src1$$reg); 2665 int divisor = $imm$$constant; 2666 Register Rresult = reg_to_register_object($dst$$reg); 2667 Register Rscratch = reg_to_register_object($scratch$$reg); 2668 2669 assert(Rdividend != Rscratch, ""); 2670 2671 __ sra(Rdividend, 0, Rdividend); 2672 __ sdivx(Rdividend, divisor, Rscratch); 2673 __ mulx(Rscratch, divisor, Rscratch); 2674 __ sub(Rdividend, Rscratch, Rresult); 2675 %} 2676 2677 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2678 MacroAssembler _masm(&cbuf); 2679 2680 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2681 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2682 2683 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2684 %} 2685 2686 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2687 MacroAssembler _masm(&cbuf); 2688 2689 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2690 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2691 2692 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2693 %} 2694 2695 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2696 MacroAssembler _masm(&cbuf); 2697 2698 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2699 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2700 2701 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2702 %} 2703 2704 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2705 MacroAssembler _masm(&cbuf); 2706 2707 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2708 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2709 2710 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2711 %} 2712 2713 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2714 MacroAssembler _masm(&cbuf); 2715 2716 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2717 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2718 2719 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2720 %} 2721 2722 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2723 MacroAssembler _masm(&cbuf); 2724 2725 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2726 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2727 2728 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2729 %} 2730 2731 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2732 MacroAssembler _masm(&cbuf); 2733 2734 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2735 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2736 2737 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2738 %} 2739 2740 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2741 MacroAssembler _masm(&cbuf); 2742 2743 Register Roop = reg_to_register_object($oop$$reg); 2744 Register Rbox = reg_to_register_object($box$$reg); 2745 Register Rscratch = reg_to_register_object($scratch$$reg); 2746 Register Rmark = reg_to_register_object($scratch2$$reg); 2747 2748 assert(Roop != Rscratch, ""); 2749 assert(Roop != Rmark, ""); 2750 assert(Rbox != Rscratch, ""); 2751 assert(Rbox != Rmark, ""); 2752 2753 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2754 %} 2755 2756 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2757 MacroAssembler _masm(&cbuf); 2758 2759 Register Roop = reg_to_register_object($oop$$reg); 2760 Register Rbox = reg_to_register_object($box$$reg); 2761 Register Rscratch = reg_to_register_object($scratch$$reg); 2762 Register Rmark = reg_to_register_object($scratch2$$reg); 2763 2764 assert(Roop != Rscratch, ""); 2765 assert(Roop != Rmark, ""); 2766 assert(Rbox != Rscratch, ""); 2767 assert(Rbox != Rmark, ""); 2768 2769 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2770 %} 2771 2772 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2773 MacroAssembler _masm(&cbuf); 2774 Register Rmem = reg_to_register_object($mem$$reg); 2775 Register Rold = reg_to_register_object($old$$reg); 2776 Register Rnew = reg_to_register_object($new$$reg); 2777 2778 // casx_under_lock picks 1 of 3 encodings: 2779 // For 32-bit pointers you get a 32-bit CAS 2780 // For 64-bit pointers you get a 64-bit CASX 2781 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2782 __ cmp( Rold, Rnew ); 2783 %} 2784 2785 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2786 Register Rmem = reg_to_register_object($mem$$reg); 2787 Register Rold = reg_to_register_object($old$$reg); 2788 Register Rnew = reg_to_register_object($new$$reg); 2789 2790 MacroAssembler _masm(&cbuf); 2791 __ mov(Rnew, O7); 2792 __ casx(Rmem, Rold, O7); 2793 __ cmp( Rold, O7 ); 2794 %} 2795 2796 // raw int cas, used for compareAndSwap 2797 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2798 Register Rmem = reg_to_register_object($mem$$reg); 2799 Register Rold = reg_to_register_object($old$$reg); 2800 Register Rnew = reg_to_register_object($new$$reg); 2801 2802 MacroAssembler _masm(&cbuf); 2803 __ mov(Rnew, O7); 2804 __ cas(Rmem, Rold, O7); 2805 __ cmp( Rold, O7 ); 2806 %} 2807 2808 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2809 Register Rres = reg_to_register_object($res$$reg); 2810 2811 MacroAssembler _masm(&cbuf); 2812 __ mov(1, Rres); 2813 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2814 %} 2815 2816 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2817 Register Rres = reg_to_register_object($res$$reg); 2818 2819 MacroAssembler _masm(&cbuf); 2820 __ mov(1, Rres); 2821 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2822 %} 2823 2824 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2825 MacroAssembler _masm(&cbuf); 2826 Register Rdst = reg_to_register_object($dst$$reg); 2827 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2828 : reg_to_DoubleFloatRegister_object($src1$$reg); 2829 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2830 : reg_to_DoubleFloatRegister_object($src2$$reg); 2831 2832 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2833 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2834 %} 2835 2836 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2837 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2838 MacroAssembler _masm(&cbuf); 2839 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2840 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2841 Register base_pointer_arg = reg_to_register_object($base$$reg); 2842 2843 Label loop; 2844 __ mov(nof_bytes_arg, nof_bytes_tmp); 2845 2846 // Loop and clear, walking backwards through the array. 2847 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2848 __ bind(loop); 2849 __ deccc(nof_bytes_tmp, 8); 2850 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2851 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2852 // %%%% this mini-loop must not cross a cache boundary! 2853 %} 2854 2855 2856 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2857 Label Ldone, Lloop; 2858 MacroAssembler _masm(&cbuf); 2859 2860 Register str1_reg = reg_to_register_object($str1$$reg); 2861 Register str2_reg = reg_to_register_object($str2$$reg); 2862 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2863 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2864 Register result_reg = reg_to_register_object($result$$reg); 2865 2866 assert(result_reg != str1_reg && 2867 result_reg != str2_reg && 2868 result_reg != cnt1_reg && 2869 result_reg != cnt2_reg , 2870 "need different registers"); 2871 2872 // Compute the minimum of the string lengths(str1_reg) and the 2873 // difference of the string lengths (stack) 2874 2875 // See if the lengths are different, and calculate min in str1_reg. 2876 // Stash diff in O7 in case we need it for a tie-breaker. 2877 Label Lskip; 2878 __ subcc(cnt1_reg, cnt2_reg, O7); 2879 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2880 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2881 // cnt2 is shorter, so use its count: 2882 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2883 __ bind(Lskip); 2884 2885 // reallocate cnt1_reg, cnt2_reg, result_reg 2886 // Note: limit_reg holds the string length pre-scaled by 2 2887 Register limit_reg = cnt1_reg; 2888 Register chr2_reg = cnt2_reg; 2889 Register chr1_reg = result_reg; 2890 // str{12} are the base pointers 2891 2892 // Is the minimum length zero? 2893 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2894 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2895 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2896 2897 // Load first characters 2898 __ lduh(str1_reg, 0, chr1_reg); 2899 __ lduh(str2_reg, 0, chr2_reg); 2900 2901 // Compare first characters 2902 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2903 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2904 assert(chr1_reg == result_reg, "result must be pre-placed"); 2905 __ delayed()->nop(); 2906 2907 { 2908 // Check after comparing first character to see if strings are equivalent 2909 Label LSkip2; 2910 // Check if the strings start at same location 2911 __ cmp(str1_reg, str2_reg); 2912 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2913 __ delayed()->nop(); 2914 2915 // Check if the length difference is zero (in O7) 2916 __ cmp(G0, O7); 2917 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2918 __ delayed()->mov(G0, result_reg); // result is zero 2919 2920 // Strings might not be equal 2921 __ bind(LSkip2); 2922 } 2923 2924 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2925 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2926 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2927 2928 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2929 __ add(str1_reg, limit_reg, str1_reg); 2930 __ add(str2_reg, limit_reg, str2_reg); 2931 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2932 2933 // Compare the rest of the characters 2934 __ lduh(str1_reg, limit_reg, chr1_reg); 2935 __ bind(Lloop); 2936 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2937 __ lduh(str2_reg, limit_reg, chr2_reg); 2938 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2939 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2940 assert(chr1_reg == result_reg, "result must be pre-placed"); 2941 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2942 // annul LDUH if branch is not taken to prevent access past end of string 2943 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2944 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2945 2946 // If strings are equal up to min length, return the length difference. 2947 __ mov(O7, result_reg); 2948 2949 // Otherwise, return the difference between the first mismatched chars. 2950 __ bind(Ldone); 2951 %} 2952 2953 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2954 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2955 MacroAssembler _masm(&cbuf); 2956 2957 Register str1_reg = reg_to_register_object($str1$$reg); 2958 Register str2_reg = reg_to_register_object($str2$$reg); 2959 Register cnt_reg = reg_to_register_object($cnt$$reg); 2960 Register tmp1_reg = O7; 2961 Register result_reg = reg_to_register_object($result$$reg); 2962 2963 assert(result_reg != str1_reg && 2964 result_reg != str2_reg && 2965 result_reg != cnt_reg && 2966 result_reg != tmp1_reg , 2967 "need different registers"); 2968 2969 __ cmp(str1_reg, str2_reg); //same char[] ? 2970 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2971 __ delayed()->add(G0, 1, result_reg); 2972 2973 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); 2974 __ delayed()->add(G0, 1, result_reg); // count == 0 2975 2976 //rename registers 2977 Register limit_reg = cnt_reg; 2978 Register chr1_reg = result_reg; 2979 Register chr2_reg = tmp1_reg; 2980 2981 //check for alignment and position the pointers to the ends 2982 __ or3(str1_reg, str2_reg, chr1_reg); 2983 __ andcc(chr1_reg, 0x3, chr1_reg); 2984 // notZero means at least one not 4-byte aligned. 2985 // We could optimize the case when both arrays are not aligned 2986 // but it is not frequent case and it requires additional checks. 2987 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 2988 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 2989 2990 // Compare char[] arrays aligned to 4 bytes. 2991 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 2992 chr1_reg, chr2_reg, Ldone); 2993 __ ba(false,Ldone); 2994 __ delayed()->add(G0, 1, result_reg); 2995 2996 // char by char compare 2997 __ bind(Lchar); 2998 __ add(str1_reg, limit_reg, str1_reg); 2999 __ add(str2_reg, limit_reg, str2_reg); 3000 __ neg(limit_reg); //negate count 3001 3002 __ lduh(str1_reg, limit_reg, chr1_reg); 3003 // Lchar_loop 3004 __ bind(Lchar_loop); 3005 __ lduh(str2_reg, limit_reg, chr2_reg); 3006 __ cmp(chr1_reg, chr2_reg); 3007 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3008 __ delayed()->mov(G0, result_reg); //not equal 3009 __ inccc(limit_reg, sizeof(jchar)); 3010 // annul LDUH if branch is not taken to prevent access past end of string 3011 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 3012 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 3013 3014 __ add(G0, 1, result_reg); //equal 3015 3016 __ bind(Ldone); 3017 %} 3018 3019 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 3020 Label Lvector, Ldone, Lloop; 3021 MacroAssembler _masm(&cbuf); 3022 3023 Register ary1_reg = reg_to_register_object($ary1$$reg); 3024 Register ary2_reg = reg_to_register_object($ary2$$reg); 3025 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3026 Register tmp2_reg = O7; 3027 Register result_reg = reg_to_register_object($result$$reg); 3028 3029 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3030 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3031 3032 // return true if the same array 3033 __ cmp(ary1_reg, ary2_reg); 3034 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3035 __ delayed()->add(G0, 1, result_reg); // equal 3036 3037 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3038 __ delayed()->mov(G0, result_reg); // not equal 3039 3040 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3041 __ delayed()->mov(G0, result_reg); // not equal 3042 3043 //load the lengths of arrays 3044 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3045 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3046 3047 // return false if the two arrays are not equal length 3048 __ cmp(tmp1_reg, tmp2_reg); 3049 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3050 __ delayed()->mov(G0, result_reg); // not equal 3051 3052 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); 3053 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3054 3055 // load array addresses 3056 __ add(ary1_reg, base_offset, ary1_reg); 3057 __ add(ary2_reg, base_offset, ary2_reg); 3058 3059 // renaming registers 3060 Register chr1_reg = result_reg; // for characters in ary1 3061 Register chr2_reg = tmp2_reg; // for characters in ary2 3062 Register limit_reg = tmp1_reg; // length 3063 3064 // set byte count 3065 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3066 3067 // Compare char[] arrays aligned to 4 bytes. 3068 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3069 chr1_reg, chr2_reg, Ldone); 3070 __ add(G0, 1, result_reg); // equals 3071 3072 __ bind(Ldone); 3073 %} 3074 3075 enc_class enc_rethrow() %{ 3076 cbuf.set_insts_mark(); 3077 Register temp_reg = G3; 3078 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3079 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3080 MacroAssembler _masm(&cbuf); 3081 #ifdef ASSERT 3082 __ save_frame(0); 3083 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3084 __ sethi(last_rethrow_addrlit, L1); 3085 Address addr(L1, last_rethrow_addrlit.low10()); 3086 __ get_pc(L2); 3087 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3088 __ st_ptr(L2, addr); 3089 __ restore(); 3090 #endif 3091 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3092 __ delayed()->nop(); 3093 %} 3094 3095 enc_class emit_mem_nop() %{ 3096 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3097 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3098 %} 3099 3100 enc_class emit_fadd_nop() %{ 3101 // Generates the instruction FMOVS f31,f31 3102 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3103 %} 3104 3105 enc_class emit_br_nop() %{ 3106 // Generates the instruction BPN,PN . 3107 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3108 %} 3109 3110 enc_class enc_membar_acquire %{ 3111 MacroAssembler _masm(&cbuf); 3112 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3113 %} 3114 3115 enc_class enc_membar_release %{ 3116 MacroAssembler _masm(&cbuf); 3117 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3118 %} 3119 3120 enc_class enc_membar_volatile %{ 3121 MacroAssembler _masm(&cbuf); 3122 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3123 %} 3124 3125 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3126 MacroAssembler _masm(&cbuf); 3127 Register src_reg = reg_to_register_object($src$$reg); 3128 Register dst_reg = reg_to_register_object($dst$$reg); 3129 __ sllx(src_reg, 56, dst_reg); 3130 __ srlx(dst_reg, 8, O7); 3131 __ or3 (dst_reg, O7, dst_reg); 3132 __ srlx(dst_reg, 16, O7); 3133 __ or3 (dst_reg, O7, dst_reg); 3134 __ srlx(dst_reg, 32, O7); 3135 __ or3 (dst_reg, O7, dst_reg); 3136 %} 3137 3138 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3139 MacroAssembler _masm(&cbuf); 3140 Register src_reg = reg_to_register_object($src$$reg); 3141 Register dst_reg = reg_to_register_object($dst$$reg); 3142 __ sll(src_reg, 24, dst_reg); 3143 __ srl(dst_reg, 8, O7); 3144 __ or3(dst_reg, O7, dst_reg); 3145 __ srl(dst_reg, 16, O7); 3146 __ or3(dst_reg, O7, dst_reg); 3147 %} 3148 3149 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3150 MacroAssembler _masm(&cbuf); 3151 Register src_reg = reg_to_register_object($src$$reg); 3152 Register dst_reg = reg_to_register_object($dst$$reg); 3153 __ sllx(src_reg, 48, dst_reg); 3154 __ srlx(dst_reg, 16, O7); 3155 __ or3 (dst_reg, O7, dst_reg); 3156 __ srlx(dst_reg, 32, O7); 3157 __ or3 (dst_reg, O7, dst_reg); 3158 %} 3159 3160 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3161 MacroAssembler _masm(&cbuf); 3162 Register src_reg = reg_to_register_object($src$$reg); 3163 Register dst_reg = reg_to_register_object($dst$$reg); 3164 __ sllx(src_reg, 32, dst_reg); 3165 __ srlx(dst_reg, 32, O7); 3166 __ or3 (dst_reg, O7, dst_reg); 3167 %} 3168 3169 %} 3170 3171 //----------FRAME-------------------------------------------------------------- 3172 // Definition of frame structure and management information. 3173 // 3174 // S T A C K L A Y O U T Allocators stack-slot number 3175 // | (to get allocators register number 3176 // G Owned by | | v add VMRegImpl::stack0) 3177 // r CALLER | | 3178 // o | +--------+ pad to even-align allocators stack-slot 3179 // w V | pad0 | numbers; owned by CALLER 3180 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3181 // h ^ | in | 5 3182 // | | args | 4 Holes in incoming args owned by SELF 3183 // | | | | 3 3184 // | | +--------+ 3185 // V | | old out| Empty on Intel, window on Sparc 3186 // | old |preserve| Must be even aligned. 3187 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3188 // | | in | 3 area for Intel ret address 3189 // Owned by |preserve| Empty on Sparc. 3190 // SELF +--------+ 3191 // | | pad2 | 2 pad to align old SP 3192 // | +--------+ 1 3193 // | | locks | 0 3194 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3195 // | | pad1 | 11 pad to align new SP 3196 // | +--------+ 3197 // | | | 10 3198 // | | spills | 9 spills 3199 // V | | 8 (pad0 slot for callee) 3200 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3201 // ^ | out | 7 3202 // | | args | 6 Holes in outgoing args owned by CALLEE 3203 // Owned by +--------+ 3204 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3205 // | new |preserve| Must be even-aligned. 3206 // | SP-+--------+----> Matcher::_new_SP, even aligned 3207 // | | | 3208 // 3209 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3210 // known from SELF's arguments and the Java calling convention. 3211 // Region 6-7 is determined per call site. 3212 // Note 2: If the calling convention leaves holes in the incoming argument 3213 // area, those holes are owned by SELF. Holes in the outgoing area 3214 // are owned by the CALLEE. Holes should not be nessecary in the 3215 // incoming area, as the Java calling convention is completely under 3216 // the control of the AD file. Doubles can be sorted and packed to 3217 // avoid holes. Holes in the outgoing arguments may be nessecary for 3218 // varargs C calling conventions. 3219 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3220 // even aligned with pad0 as needed. 3221 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3222 // region 6-11 is even aligned; it may be padded out more so that 3223 // the region from SP to FP meets the minimum stack alignment. 3224 3225 frame %{ 3226 // What direction does stack grow in (assumed to be same for native & Java) 3227 stack_direction(TOWARDS_LOW); 3228 3229 // These two registers define part of the calling convention 3230 // between compiled code and the interpreter. 3231 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3232 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3233 3234 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3235 cisc_spilling_operand_name(indOffset); 3236 3237 // Number of stack slots consumed by a Monitor enter 3238 #ifdef _LP64 3239 sync_stack_slots(2); 3240 #else 3241 sync_stack_slots(1); 3242 #endif 3243 3244 // Compiled code's Frame Pointer 3245 frame_pointer(R_SP); 3246 3247 // Stack alignment requirement 3248 stack_alignment(StackAlignmentInBytes); 3249 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3250 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3251 3252 // Number of stack slots between incoming argument block and the start of 3253 // a new frame. The PROLOG must add this many slots to the stack. The 3254 // EPILOG must remove this many slots. 3255 in_preserve_stack_slots(0); 3256 3257 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3258 // for calls to C. Supports the var-args backing area for register parms. 3259 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3260 #ifdef _LP64 3261 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3262 varargs_C_out_slots_killed(12); 3263 #else 3264 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3265 varargs_C_out_slots_killed( 7); 3266 #endif 3267 3268 // The after-PROLOG location of the return address. Location of 3269 // return address specifies a type (REG or STACK) and a number 3270 // representing the register number (i.e. - use a register name) or 3271 // stack slot. 3272 return_addr(REG R_I7); // Ret Addr is in register I7 3273 3274 // Body of function which returns an OptoRegs array locating 3275 // arguments either in registers or in stack slots for calling 3276 // java 3277 calling_convention %{ 3278 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3279 3280 %} 3281 3282 // Body of function which returns an OptoRegs array locating 3283 // arguments either in registers or in stack slots for callin 3284 // C. 3285 c_calling_convention %{ 3286 // This is obviously always outgoing 3287 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3288 %} 3289 3290 // Location of native (C/C++) and interpreter return values. This is specified to 3291 // be the same as Java. In the 32-bit VM, long values are actually returned from 3292 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3293 // to and from the register pairs is done by the appropriate call and epilog 3294 // opcodes. This simplifies the register allocator. 3295 c_return_value %{ 3296 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3297 #ifdef _LP64 3298 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3299 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3300 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3301 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3302 #else // !_LP64 3303 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3304 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3305 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3306 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3307 #endif 3308 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3309 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3310 %} 3311 3312 // Location of compiled Java return values. Same as C 3313 return_value %{ 3314 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3315 #ifdef _LP64 3316 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3317 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3318 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3319 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3320 #else // !_LP64 3321 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3322 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3323 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3324 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3325 #endif 3326 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3327 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3328 %} 3329 3330 %} 3331 3332 3333 //----------ATTRIBUTES--------------------------------------------------------- 3334 //----------Operand Attributes------------------------------------------------- 3335 op_attrib op_cost(1); // Required cost attribute 3336 3337 //----------Instruction Attributes--------------------------------------------- 3338 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3339 ins_attrib ins_size(32); // Required size attribute (in bits) 3340 ins_attrib ins_pc_relative(0); // Required PC Relative flag 3341 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3342 // non-matching short branch variant of some 3343 // long branch? 3344 3345 //----------OPERANDS----------------------------------------------------------- 3346 // Operand definitions must precede instruction definitions for correct parsing 3347 // in the ADLC because operands constitute user defined types which are used in 3348 // instruction definitions. 3349 3350 //----------Simple Operands---------------------------------------------------- 3351 // Immediate Operands 3352 // Integer Immediate: 32-bit 3353 operand immI() %{ 3354 match(ConI); 3355 3356 op_cost(0); 3357 // formats are generated automatically for constants and base registers 3358 format %{ %} 3359 interface(CONST_INTER); 3360 %} 3361 3362 // Integer Immediate: 8-bit 3363 operand immI8() %{ 3364 predicate(Assembler::is_simm(n->get_int(), 8)); 3365 match(ConI); 3366 op_cost(0); 3367 format %{ %} 3368 interface(CONST_INTER); 3369 %} 3370 3371 // Integer Immediate: 13-bit 3372 operand immI13() %{ 3373 predicate(Assembler::is_simm13(n->get_int())); 3374 match(ConI); 3375 op_cost(0); 3376 3377 format %{ %} 3378 interface(CONST_INTER); 3379 %} 3380 3381 // Integer Immediate: 13-bit minus 7 3382 operand immI13m7() %{ 3383 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3384 match(ConI); 3385 op_cost(0); 3386 3387 format %{ %} 3388 interface(CONST_INTER); 3389 %} 3390 3391 // Integer Immediate: 16-bit 3392 operand immI16() %{ 3393 predicate(Assembler::is_simm(n->get_int(), 16)); 3394 match(ConI); 3395 op_cost(0); 3396 format %{ %} 3397 interface(CONST_INTER); 3398 %} 3399 3400 // Unsigned (positive) Integer Immediate: 13-bit 3401 operand immU13() %{ 3402 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3403 match(ConI); 3404 op_cost(0); 3405 3406 format %{ %} 3407 interface(CONST_INTER); 3408 %} 3409 3410 // Integer Immediate: 6-bit 3411 operand immU6() %{ 3412 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3413 match(ConI); 3414 op_cost(0); 3415 format %{ %} 3416 interface(CONST_INTER); 3417 %} 3418 3419 // Integer Immediate: 11-bit 3420 operand immI11() %{ 3421 predicate(Assembler::is_simm(n->get_int(),11)); 3422 match(ConI); 3423 op_cost(0); 3424 format %{ %} 3425 interface(CONST_INTER); 3426 %} 3427 3428 // Integer Immediate: 0-bit 3429 operand immI0() %{ 3430 predicate(n->get_int() == 0); 3431 match(ConI); 3432 op_cost(0); 3433 3434 format %{ %} 3435 interface(CONST_INTER); 3436 %} 3437 3438 // Integer Immediate: the value 10 3439 operand immI10() %{ 3440 predicate(n->get_int() == 10); 3441 match(ConI); 3442 op_cost(0); 3443 3444 format %{ %} 3445 interface(CONST_INTER); 3446 %} 3447 3448 // Integer Immediate: the values 0-31 3449 operand immU5() %{ 3450 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3451 match(ConI); 3452 op_cost(0); 3453 3454 format %{ %} 3455 interface(CONST_INTER); 3456 %} 3457 3458 // Integer Immediate: the values 1-31 3459 operand immI_1_31() %{ 3460 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3461 match(ConI); 3462 op_cost(0); 3463 3464 format %{ %} 3465 interface(CONST_INTER); 3466 %} 3467 3468 // Integer Immediate: the values 32-63 3469 operand immI_32_63() %{ 3470 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3471 match(ConI); 3472 op_cost(0); 3473 3474 format %{ %} 3475 interface(CONST_INTER); 3476 %} 3477 3478 // Immediates for special shifts (sign extend) 3479 3480 // Integer Immediate: the value 16 3481 operand immI_16() %{ 3482 predicate(n->get_int() == 16); 3483 match(ConI); 3484 op_cost(0); 3485 3486 format %{ %} 3487 interface(CONST_INTER); 3488 %} 3489 3490 // Integer Immediate: the value 24 3491 operand immI_24() %{ 3492 predicate(n->get_int() == 24); 3493 match(ConI); 3494 op_cost(0); 3495 3496 format %{ %} 3497 interface(CONST_INTER); 3498 %} 3499 3500 // Integer Immediate: the value 255 3501 operand immI_255() %{ 3502 predicate( n->get_int() == 255 ); 3503 match(ConI); 3504 op_cost(0); 3505 3506 format %{ %} 3507 interface(CONST_INTER); 3508 %} 3509 3510 // Integer Immediate: the value 65535 3511 operand immI_65535() %{ 3512 predicate(n->get_int() == 65535); 3513 match(ConI); 3514 op_cost(0); 3515 3516 format %{ %} 3517 interface(CONST_INTER); 3518 %} 3519 3520 // Long Immediate: the value FF 3521 operand immL_FF() %{ 3522 predicate( n->get_long() == 0xFFL ); 3523 match(ConL); 3524 op_cost(0); 3525 3526 format %{ %} 3527 interface(CONST_INTER); 3528 %} 3529 3530 // Long Immediate: the value FFFF 3531 operand immL_FFFF() %{ 3532 predicate( n->get_long() == 0xFFFFL ); 3533 match(ConL); 3534 op_cost(0); 3535 3536 format %{ %} 3537 interface(CONST_INTER); 3538 %} 3539 3540 // Pointer Immediate: 32 or 64-bit 3541 operand immP() %{ 3542 match(ConP); 3543 3544 op_cost(5); 3545 // formats are generated automatically for constants and base registers 3546 format %{ %} 3547 interface(CONST_INTER); 3548 %} 3549 3550 operand immP13() %{ 3551 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3552 match(ConP); 3553 op_cost(0); 3554 3555 format %{ %} 3556 interface(CONST_INTER); 3557 %} 3558 3559 operand immP0() %{ 3560 predicate(n->get_ptr() == 0); 3561 match(ConP); 3562 op_cost(0); 3563 3564 format %{ %} 3565 interface(CONST_INTER); 3566 %} 3567 3568 operand immP_poll() %{ 3569 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3570 match(ConP); 3571 3572 // formats are generated automatically for constants and base registers 3573 format %{ %} 3574 interface(CONST_INTER); 3575 %} 3576 3577 // Pointer Immediate 3578 operand immN() 3579 %{ 3580 match(ConN); 3581 3582 op_cost(10); 3583 format %{ %} 3584 interface(CONST_INTER); 3585 %} 3586 3587 // NULL Pointer Immediate 3588 operand immN0() 3589 %{ 3590 predicate(n->get_narrowcon() == 0); 3591 match(ConN); 3592 3593 op_cost(0); 3594 format %{ %} 3595 interface(CONST_INTER); 3596 %} 3597 3598 operand immL() %{ 3599 match(ConL); 3600 op_cost(40); 3601 // formats are generated automatically for constants and base registers 3602 format %{ %} 3603 interface(CONST_INTER); 3604 %} 3605 3606 operand immL0() %{ 3607 predicate(n->get_long() == 0L); 3608 match(ConL); 3609 op_cost(0); 3610 // formats are generated automatically for constants and base registers 3611 format %{ %} 3612 interface(CONST_INTER); 3613 %} 3614 3615 // Long Immediate: 13-bit 3616 operand immL13() %{ 3617 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3618 match(ConL); 3619 op_cost(0); 3620 3621 format %{ %} 3622 interface(CONST_INTER); 3623 %} 3624 3625 // Long Immediate: 13-bit minus 7 3626 operand immL13m7() %{ 3627 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3628 match(ConL); 3629 op_cost(0); 3630 3631 format %{ %} 3632 interface(CONST_INTER); 3633 %} 3634 3635 // Long Immediate: low 32-bit mask 3636 operand immL_32bits() %{ 3637 predicate(n->get_long() == 0xFFFFFFFFL); 3638 match(ConL); 3639 op_cost(0); 3640 3641 format %{ %} 3642 interface(CONST_INTER); 3643 %} 3644 3645 // Long Immediate: cheap (materialize in <= 3 instructions) 3646 operand immL_cheap() %{ 3647 predicate(MacroAssembler::size_of_set64(n->get_long()) <= 3); 3648 match(ConL); 3649 op_cost(0); 3650 3651 format %{ %} 3652 interface(CONST_INTER); 3653 %} 3654 3655 // Long Immediate: expensive (materialize in > 3 instructions) 3656 operand immL_expensive() %{ 3657 predicate(MacroAssembler::size_of_set64(n->get_long()) > 3); 3658 match(ConL); 3659 op_cost(0); 3660 3661 format %{ %} 3662 interface(CONST_INTER); 3663 %} 3664 3665 // Double Immediate 3666 operand immD() %{ 3667 match(ConD); 3668 3669 op_cost(40); 3670 format %{ %} 3671 interface(CONST_INTER); 3672 %} 3673 3674 operand immD0() %{ 3675 #ifdef _LP64 3676 // on 64-bit architectures this comparision is faster 3677 predicate(jlong_cast(n->getd()) == 0); 3678 #else 3679 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3680 #endif 3681 match(ConD); 3682 3683 op_cost(0); 3684 format %{ %} 3685 interface(CONST_INTER); 3686 %} 3687 3688 // Float Immediate 3689 operand immF() %{ 3690 match(ConF); 3691 3692 op_cost(20); 3693 format %{ %} 3694 interface(CONST_INTER); 3695 %} 3696 3697 // Float Immediate: 0 3698 operand immF0() %{ 3699 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3700 match(ConF); 3701 3702 op_cost(0); 3703 format %{ %} 3704 interface(CONST_INTER); 3705 %} 3706 3707 // Integer Register Operands 3708 // Integer Register 3709 operand iRegI() %{ 3710 constraint(ALLOC_IN_RC(int_reg)); 3711 match(RegI); 3712 3713 match(notemp_iRegI); 3714 match(g1RegI); 3715 match(o0RegI); 3716 match(iRegIsafe); 3717 3718 format %{ %} 3719 interface(REG_INTER); 3720 %} 3721 3722 operand notemp_iRegI() %{ 3723 constraint(ALLOC_IN_RC(notemp_int_reg)); 3724 match(RegI); 3725 3726 match(o0RegI); 3727 3728 format %{ %} 3729 interface(REG_INTER); 3730 %} 3731 3732 operand o0RegI() %{ 3733 constraint(ALLOC_IN_RC(o0_regI)); 3734 match(iRegI); 3735 3736 format %{ %} 3737 interface(REG_INTER); 3738 %} 3739 3740 // Pointer Register 3741 operand iRegP() %{ 3742 constraint(ALLOC_IN_RC(ptr_reg)); 3743 match(RegP); 3744 3745 match(lock_ptr_RegP); 3746 match(g1RegP); 3747 match(g2RegP); 3748 match(g3RegP); 3749 match(g4RegP); 3750 match(i0RegP); 3751 match(o0RegP); 3752 match(o1RegP); 3753 match(l7RegP); 3754 3755 format %{ %} 3756 interface(REG_INTER); 3757 %} 3758 3759 operand sp_ptr_RegP() %{ 3760 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3761 match(RegP); 3762 match(iRegP); 3763 3764 format %{ %} 3765 interface(REG_INTER); 3766 %} 3767 3768 operand lock_ptr_RegP() %{ 3769 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3770 match(RegP); 3771 match(i0RegP); 3772 match(o0RegP); 3773 match(o1RegP); 3774 match(l7RegP); 3775 3776 format %{ %} 3777 interface(REG_INTER); 3778 %} 3779 3780 operand g1RegP() %{ 3781 constraint(ALLOC_IN_RC(g1_regP)); 3782 match(iRegP); 3783 3784 format %{ %} 3785 interface(REG_INTER); 3786 %} 3787 3788 operand g2RegP() %{ 3789 constraint(ALLOC_IN_RC(g2_regP)); 3790 match(iRegP); 3791 3792 format %{ %} 3793 interface(REG_INTER); 3794 %} 3795 3796 operand g3RegP() %{ 3797 constraint(ALLOC_IN_RC(g3_regP)); 3798 match(iRegP); 3799 3800 format %{ %} 3801 interface(REG_INTER); 3802 %} 3803 3804 operand g1RegI() %{ 3805 constraint(ALLOC_IN_RC(g1_regI)); 3806 match(iRegI); 3807 3808 format %{ %} 3809 interface(REG_INTER); 3810 %} 3811 3812 operand g3RegI() %{ 3813 constraint(ALLOC_IN_RC(g3_regI)); 3814 match(iRegI); 3815 3816 format %{ %} 3817 interface(REG_INTER); 3818 %} 3819 3820 operand g4RegI() %{ 3821 constraint(ALLOC_IN_RC(g4_regI)); 3822 match(iRegI); 3823 3824 format %{ %} 3825 interface(REG_INTER); 3826 %} 3827 3828 operand g4RegP() %{ 3829 constraint(ALLOC_IN_RC(g4_regP)); 3830 match(iRegP); 3831 3832 format %{ %} 3833 interface(REG_INTER); 3834 %} 3835 3836 operand i0RegP() %{ 3837 constraint(ALLOC_IN_RC(i0_regP)); 3838 match(iRegP); 3839 3840 format %{ %} 3841 interface(REG_INTER); 3842 %} 3843 3844 operand o0RegP() %{ 3845 constraint(ALLOC_IN_RC(o0_regP)); 3846 match(iRegP); 3847 3848 format %{ %} 3849 interface(REG_INTER); 3850 %} 3851 3852 operand o1RegP() %{ 3853 constraint(ALLOC_IN_RC(o1_regP)); 3854 match(iRegP); 3855 3856 format %{ %} 3857 interface(REG_INTER); 3858 %} 3859 3860 operand o2RegP() %{ 3861 constraint(ALLOC_IN_RC(o2_regP)); 3862 match(iRegP); 3863 3864 format %{ %} 3865 interface(REG_INTER); 3866 %} 3867 3868 operand o7RegP() %{ 3869 constraint(ALLOC_IN_RC(o7_regP)); 3870 match(iRegP); 3871 3872 format %{ %} 3873 interface(REG_INTER); 3874 %} 3875 3876 operand l7RegP() %{ 3877 constraint(ALLOC_IN_RC(l7_regP)); 3878 match(iRegP); 3879 3880 format %{ %} 3881 interface(REG_INTER); 3882 %} 3883 3884 operand o7RegI() %{ 3885 constraint(ALLOC_IN_RC(o7_regI)); 3886 match(iRegI); 3887 3888 format %{ %} 3889 interface(REG_INTER); 3890 %} 3891 3892 operand iRegN() %{ 3893 constraint(ALLOC_IN_RC(int_reg)); 3894 match(RegN); 3895 3896 format %{ %} 3897 interface(REG_INTER); 3898 %} 3899 3900 // Long Register 3901 operand iRegL() %{ 3902 constraint(ALLOC_IN_RC(long_reg)); 3903 match(RegL); 3904 3905 format %{ %} 3906 interface(REG_INTER); 3907 %} 3908 3909 operand o2RegL() %{ 3910 constraint(ALLOC_IN_RC(o2_regL)); 3911 match(iRegL); 3912 3913 format %{ %} 3914 interface(REG_INTER); 3915 %} 3916 3917 operand o7RegL() %{ 3918 constraint(ALLOC_IN_RC(o7_regL)); 3919 match(iRegL); 3920 3921 format %{ %} 3922 interface(REG_INTER); 3923 %} 3924 3925 operand g1RegL() %{ 3926 constraint(ALLOC_IN_RC(g1_regL)); 3927 match(iRegL); 3928 3929 format %{ %} 3930 interface(REG_INTER); 3931 %} 3932 3933 operand g3RegL() %{ 3934 constraint(ALLOC_IN_RC(g3_regL)); 3935 match(iRegL); 3936 3937 format %{ %} 3938 interface(REG_INTER); 3939 %} 3940 3941 // Int Register safe 3942 // This is 64bit safe 3943 operand iRegIsafe() %{ 3944 constraint(ALLOC_IN_RC(long_reg)); 3945 3946 match(iRegI); 3947 3948 format %{ %} 3949 interface(REG_INTER); 3950 %} 3951 3952 // Condition Code Flag Register 3953 operand flagsReg() %{ 3954 constraint(ALLOC_IN_RC(int_flags)); 3955 match(RegFlags); 3956 3957 format %{ "ccr" %} // both ICC and XCC 3958 interface(REG_INTER); 3959 %} 3960 3961 // Condition Code Register, unsigned comparisons. 3962 operand flagsRegU() %{ 3963 constraint(ALLOC_IN_RC(int_flags)); 3964 match(RegFlags); 3965 3966 format %{ "icc_U" %} 3967 interface(REG_INTER); 3968 %} 3969 3970 // Condition Code Register, pointer comparisons. 3971 operand flagsRegP() %{ 3972 constraint(ALLOC_IN_RC(int_flags)); 3973 match(RegFlags); 3974 3975 #ifdef _LP64 3976 format %{ "xcc_P" %} 3977 #else 3978 format %{ "icc_P" %} 3979 #endif 3980 interface(REG_INTER); 3981 %} 3982 3983 // Condition Code Register, long comparisons. 3984 operand flagsRegL() %{ 3985 constraint(ALLOC_IN_RC(int_flags)); 3986 match(RegFlags); 3987 3988 format %{ "xcc_L" %} 3989 interface(REG_INTER); 3990 %} 3991 3992 // Condition Code Register, floating comparisons, unordered same as "less". 3993 operand flagsRegF() %{ 3994 constraint(ALLOC_IN_RC(float_flags)); 3995 match(RegFlags); 3996 match(flagsRegF0); 3997 3998 format %{ %} 3999 interface(REG_INTER); 4000 %} 4001 4002 operand flagsRegF0() %{ 4003 constraint(ALLOC_IN_RC(float_flag0)); 4004 match(RegFlags); 4005 4006 format %{ %} 4007 interface(REG_INTER); 4008 %} 4009 4010 4011 // Condition Code Flag Register used by long compare 4012 operand flagsReg_long_LTGE() %{ 4013 constraint(ALLOC_IN_RC(int_flags)); 4014 match(RegFlags); 4015 format %{ "icc_LTGE" %} 4016 interface(REG_INTER); 4017 %} 4018 operand flagsReg_long_EQNE() %{ 4019 constraint(ALLOC_IN_RC(int_flags)); 4020 match(RegFlags); 4021 format %{ "icc_EQNE" %} 4022 interface(REG_INTER); 4023 %} 4024 operand flagsReg_long_LEGT() %{ 4025 constraint(ALLOC_IN_RC(int_flags)); 4026 match(RegFlags); 4027 format %{ "icc_LEGT" %} 4028 interface(REG_INTER); 4029 %} 4030 4031 4032 operand regD() %{ 4033 constraint(ALLOC_IN_RC(dflt_reg)); 4034 match(RegD); 4035 4036 match(regD_low); 4037 4038 format %{ %} 4039 interface(REG_INTER); 4040 %} 4041 4042 operand regF() %{ 4043 constraint(ALLOC_IN_RC(sflt_reg)); 4044 match(RegF); 4045 4046 format %{ %} 4047 interface(REG_INTER); 4048 %} 4049 4050 operand regD_low() %{ 4051 constraint(ALLOC_IN_RC(dflt_low_reg)); 4052 match(regD); 4053 4054 format %{ %} 4055 interface(REG_INTER); 4056 %} 4057 4058 // Special Registers 4059 4060 // Method Register 4061 operand inline_cache_regP(iRegP reg) %{ 4062 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4063 match(reg); 4064 format %{ %} 4065 interface(REG_INTER); 4066 %} 4067 4068 operand interpreter_method_oop_regP(iRegP reg) %{ 4069 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4070 match(reg); 4071 format %{ %} 4072 interface(REG_INTER); 4073 %} 4074 4075 4076 //----------Complex Operands--------------------------------------------------- 4077 // Indirect Memory Reference 4078 operand indirect(sp_ptr_RegP reg) %{ 4079 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4080 match(reg); 4081 4082 op_cost(100); 4083 format %{ "[$reg]" %} 4084 interface(MEMORY_INTER) %{ 4085 base($reg); 4086 index(0x0); 4087 scale(0x0); 4088 disp(0x0); 4089 %} 4090 %} 4091 4092 // Indirect with simm13 Offset 4093 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4094 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4095 match(AddP reg offset); 4096 4097 op_cost(100); 4098 format %{ "[$reg + $offset]" %} 4099 interface(MEMORY_INTER) %{ 4100 base($reg); 4101 index(0x0); 4102 scale(0x0); 4103 disp($offset); 4104 %} 4105 %} 4106 4107 // Indirect with simm13 Offset minus 7 4108 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4109 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4110 match(AddP reg offset); 4111 4112 op_cost(100); 4113 format %{ "[$reg + $offset]" %} 4114 interface(MEMORY_INTER) %{ 4115 base($reg); 4116 index(0x0); 4117 scale(0x0); 4118 disp($offset); 4119 %} 4120 %} 4121 4122 // Note: Intel has a swapped version also, like this: 4123 //operand indOffsetX(iRegI reg, immP offset) %{ 4124 // constraint(ALLOC_IN_RC(int_reg)); 4125 // match(AddP offset reg); 4126 // 4127 // op_cost(100); 4128 // format %{ "[$reg + $offset]" %} 4129 // interface(MEMORY_INTER) %{ 4130 // base($reg); 4131 // index(0x0); 4132 // scale(0x0); 4133 // disp($offset); 4134 // %} 4135 //%} 4136 //// However, it doesn't make sense for SPARC, since 4137 // we have no particularly good way to embed oops in 4138 // single instructions. 4139 4140 // Indirect with Register Index 4141 operand indIndex(iRegP addr, iRegX index) %{ 4142 constraint(ALLOC_IN_RC(ptr_reg)); 4143 match(AddP addr index); 4144 4145 op_cost(100); 4146 format %{ "[$addr + $index]" %} 4147 interface(MEMORY_INTER) %{ 4148 base($addr); 4149 index($index); 4150 scale(0x0); 4151 disp(0x0); 4152 %} 4153 %} 4154 4155 //----------Special Memory Operands-------------------------------------------- 4156 // Stack Slot Operand - This operand is used for loading and storing temporary 4157 // values on the stack where a match requires a value to 4158 // flow through memory. 4159 operand stackSlotI(sRegI reg) %{ 4160 constraint(ALLOC_IN_RC(stack_slots)); 4161 op_cost(100); 4162 //match(RegI); 4163 format %{ "[$reg]" %} 4164 interface(MEMORY_INTER) %{ 4165 base(0xE); // R_SP 4166 index(0x0); 4167 scale(0x0); 4168 disp($reg); // Stack Offset 4169 %} 4170 %} 4171 4172 operand stackSlotP(sRegP reg) %{ 4173 constraint(ALLOC_IN_RC(stack_slots)); 4174 op_cost(100); 4175 //match(RegP); 4176 format %{ "[$reg]" %} 4177 interface(MEMORY_INTER) %{ 4178 base(0xE); // R_SP 4179 index(0x0); 4180 scale(0x0); 4181 disp($reg); // Stack Offset 4182 %} 4183 %} 4184 4185 operand stackSlotF(sRegF reg) %{ 4186 constraint(ALLOC_IN_RC(stack_slots)); 4187 op_cost(100); 4188 //match(RegF); 4189 format %{ "[$reg]" %} 4190 interface(MEMORY_INTER) %{ 4191 base(0xE); // R_SP 4192 index(0x0); 4193 scale(0x0); 4194 disp($reg); // Stack Offset 4195 %} 4196 %} 4197 operand stackSlotD(sRegD reg) %{ 4198 constraint(ALLOC_IN_RC(stack_slots)); 4199 op_cost(100); 4200 //match(RegD); 4201 format %{ "[$reg]" %} 4202 interface(MEMORY_INTER) %{ 4203 base(0xE); // R_SP 4204 index(0x0); 4205 scale(0x0); 4206 disp($reg); // Stack Offset 4207 %} 4208 %} 4209 operand stackSlotL(sRegL reg) %{ 4210 constraint(ALLOC_IN_RC(stack_slots)); 4211 op_cost(100); 4212 //match(RegL); 4213 format %{ "[$reg]" %} 4214 interface(MEMORY_INTER) %{ 4215 base(0xE); // R_SP 4216 index(0x0); 4217 scale(0x0); 4218 disp($reg); // Stack Offset 4219 %} 4220 %} 4221 4222 // Operands for expressing Control Flow 4223 // NOTE: Label is a predefined operand which should not be redefined in 4224 // the AD file. It is generically handled within the ADLC. 4225 4226 //----------Conditional Branch Operands---------------------------------------- 4227 // Comparison Op - This is the operation of the comparison, and is limited to 4228 // the following set of codes: 4229 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4230 // 4231 // Other attributes of the comparison, such as unsignedness, are specified 4232 // by the comparison instruction that sets a condition code flags register. 4233 // That result is represented by a flags operand whose subtype is appropriate 4234 // to the unsignedness (etc.) of the comparison. 4235 // 4236 // Later, the instruction which matches both the Comparison Op (a Bool) and 4237 // the flags (produced by the Cmp) specifies the coding of the comparison op 4238 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4239 4240 operand cmpOp() %{ 4241 match(Bool); 4242 4243 format %{ "" %} 4244 interface(COND_INTER) %{ 4245 equal(0x1); 4246 not_equal(0x9); 4247 less(0x3); 4248 greater_equal(0xB); 4249 less_equal(0x2); 4250 greater(0xA); 4251 %} 4252 %} 4253 4254 // Comparison Op, unsigned 4255 operand cmpOpU() %{ 4256 match(Bool); 4257 4258 format %{ "u" %} 4259 interface(COND_INTER) %{ 4260 equal(0x1); 4261 not_equal(0x9); 4262 less(0x5); 4263 greater_equal(0xD); 4264 less_equal(0x4); 4265 greater(0xC); 4266 %} 4267 %} 4268 4269 // Comparison Op, pointer (same as unsigned) 4270 operand cmpOpP() %{ 4271 match(Bool); 4272 4273 format %{ "p" %} 4274 interface(COND_INTER) %{ 4275 equal(0x1); 4276 not_equal(0x9); 4277 less(0x5); 4278 greater_equal(0xD); 4279 less_equal(0x4); 4280 greater(0xC); 4281 %} 4282 %} 4283 4284 // Comparison Op, branch-register encoding 4285 operand cmpOp_reg() %{ 4286 match(Bool); 4287 4288 format %{ "" %} 4289 interface(COND_INTER) %{ 4290 equal (0x1); 4291 not_equal (0x5); 4292 less (0x3); 4293 greater_equal(0x7); 4294 less_equal (0x2); 4295 greater (0x6); 4296 %} 4297 %} 4298 4299 // Comparison Code, floating, unordered same as less 4300 operand cmpOpF() %{ 4301 match(Bool); 4302 4303 format %{ "fl" %} 4304 interface(COND_INTER) %{ 4305 equal(0x9); 4306 not_equal(0x1); 4307 less(0x3); 4308 greater_equal(0xB); 4309 less_equal(0xE); 4310 greater(0x6); 4311 %} 4312 %} 4313 4314 // Used by long compare 4315 operand cmpOp_commute() %{ 4316 match(Bool); 4317 4318 format %{ "" %} 4319 interface(COND_INTER) %{ 4320 equal(0x1); 4321 not_equal(0x9); 4322 less(0xA); 4323 greater_equal(0x2); 4324 less_equal(0xB); 4325 greater(0x3); 4326 %} 4327 %} 4328 4329 //----------OPERAND CLASSES---------------------------------------------------- 4330 // Operand Classes are groups of operands that are used to simplify 4331 // instruction definitions by not requiring the AD writer to specify separate 4332 // instructions for every form of operand when the instruction accepts 4333 // multiple operand types with the same basic encoding and format. The classic 4334 // case of this is memory operands. 4335 opclass memory( indirect, indOffset13, indIndex ); 4336 opclass indIndexMemory( indIndex ); 4337 4338 //----------PIPELINE----------------------------------------------------------- 4339 pipeline %{ 4340 4341 //----------ATTRIBUTES--------------------------------------------------------- 4342 attributes %{ 4343 fixed_size_instructions; // Fixed size instructions 4344 branch_has_delay_slot; // Branch has delay slot following 4345 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4346 instruction_unit_size = 4; // An instruction is 4 bytes long 4347 instruction_fetch_unit_size = 16; // The processor fetches one line 4348 instruction_fetch_units = 1; // of 16 bytes 4349 4350 // List of nop instructions 4351 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4352 %} 4353 4354 //----------RESOURCES---------------------------------------------------------- 4355 // Resources are the functional units available to the machine 4356 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4357 4358 //----------PIPELINE DESCRIPTION----------------------------------------------- 4359 // Pipeline Description specifies the stages in the machine's pipeline 4360 4361 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4362 4363 //----------PIPELINE CLASSES--------------------------------------------------- 4364 // Pipeline Classes describe the stages in which input and output are 4365 // referenced by the hardware pipeline. 4366 4367 // Integer ALU reg-reg operation 4368 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4369 single_instruction; 4370 dst : E(write); 4371 src1 : R(read); 4372 src2 : R(read); 4373 IALU : R; 4374 %} 4375 4376 // Integer ALU reg-reg long operation 4377 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4378 instruction_count(2); 4379 dst : E(write); 4380 src1 : R(read); 4381 src2 : R(read); 4382 IALU : R; 4383 IALU : R; 4384 %} 4385 4386 // Integer ALU reg-reg long dependent operation 4387 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4388 instruction_count(1); multiple_bundles; 4389 dst : E(write); 4390 src1 : R(read); 4391 src2 : R(read); 4392 cr : E(write); 4393 IALU : R(2); 4394 %} 4395 4396 // Integer ALU reg-imm operaion 4397 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4398 single_instruction; 4399 dst : E(write); 4400 src1 : R(read); 4401 IALU : R; 4402 %} 4403 4404 // Integer ALU reg-reg operation with condition code 4405 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4406 single_instruction; 4407 dst : E(write); 4408 cr : E(write); 4409 src1 : R(read); 4410 src2 : R(read); 4411 IALU : R; 4412 %} 4413 4414 // Integer ALU reg-imm operation with condition code 4415 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4416 single_instruction; 4417 dst : E(write); 4418 cr : E(write); 4419 src1 : R(read); 4420 IALU : R; 4421 %} 4422 4423 // Integer ALU zero-reg operation 4424 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4425 single_instruction; 4426 dst : E(write); 4427 src2 : R(read); 4428 IALU : R; 4429 %} 4430 4431 // Integer ALU zero-reg operation with condition code only 4432 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4433 single_instruction; 4434 cr : E(write); 4435 src : R(read); 4436 IALU : R; 4437 %} 4438 4439 // Integer ALU reg-reg operation with condition code only 4440 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4441 single_instruction; 4442 cr : E(write); 4443 src1 : R(read); 4444 src2 : R(read); 4445 IALU : R; 4446 %} 4447 4448 // Integer ALU reg-imm operation with condition code only 4449 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4450 single_instruction; 4451 cr : E(write); 4452 src1 : R(read); 4453 IALU : R; 4454 %} 4455 4456 // Integer ALU reg-reg-zero operation with condition code only 4457 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4458 single_instruction; 4459 cr : E(write); 4460 src1 : R(read); 4461 src2 : R(read); 4462 IALU : R; 4463 %} 4464 4465 // Integer ALU reg-imm-zero operation with condition code only 4466 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4467 single_instruction; 4468 cr : E(write); 4469 src1 : R(read); 4470 IALU : R; 4471 %} 4472 4473 // Integer ALU reg-reg operation with condition code, src1 modified 4474 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4475 single_instruction; 4476 cr : E(write); 4477 src1 : E(write); 4478 src1 : R(read); 4479 src2 : R(read); 4480 IALU : R; 4481 %} 4482 4483 // Integer ALU reg-imm operation with condition code, src1 modified 4484 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4485 single_instruction; 4486 cr : E(write); 4487 src1 : E(write); 4488 src1 : R(read); 4489 IALU : R; 4490 %} 4491 4492 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4493 multiple_bundles; 4494 dst : E(write)+4; 4495 cr : E(write); 4496 src1 : R(read); 4497 src2 : R(read); 4498 IALU : R(3); 4499 BR : R(2); 4500 %} 4501 4502 // Integer ALU operation 4503 pipe_class ialu_none(iRegI dst) %{ 4504 single_instruction; 4505 dst : E(write); 4506 IALU : R; 4507 %} 4508 4509 // Integer ALU reg operation 4510 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4511 single_instruction; may_have_no_code; 4512 dst : E(write); 4513 src : R(read); 4514 IALU : R; 4515 %} 4516 4517 // Integer ALU reg conditional operation 4518 // This instruction has a 1 cycle stall, and cannot execute 4519 // in the same cycle as the instruction setting the condition 4520 // code. We kludge this by pretending to read the condition code 4521 // 1 cycle earlier, and by marking the functional units as busy 4522 // for 2 cycles with the result available 1 cycle later than 4523 // is really the case. 4524 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4525 single_instruction; 4526 op2_out : C(write); 4527 op1 : R(read); 4528 cr : R(read); // This is really E, with a 1 cycle stall 4529 BR : R(2); 4530 MS : R(2); 4531 %} 4532 4533 #ifdef _LP64 4534 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4535 instruction_count(1); multiple_bundles; 4536 dst : C(write)+1; 4537 src : R(read)+1; 4538 IALU : R(1); 4539 BR : E(2); 4540 MS : E(2); 4541 %} 4542 #endif 4543 4544 // Integer ALU reg operation 4545 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4546 single_instruction; may_have_no_code; 4547 dst : E(write); 4548 src : R(read); 4549 IALU : R; 4550 %} 4551 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4552 single_instruction; may_have_no_code; 4553 dst : E(write); 4554 src : R(read); 4555 IALU : R; 4556 %} 4557 4558 // Two integer ALU reg operations 4559 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4560 instruction_count(2); 4561 dst : E(write); 4562 src : R(read); 4563 A0 : R; 4564 A1 : R; 4565 %} 4566 4567 // Two integer ALU reg operations 4568 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4569 instruction_count(2); may_have_no_code; 4570 dst : E(write); 4571 src : R(read); 4572 A0 : R; 4573 A1 : R; 4574 %} 4575 4576 // Integer ALU imm operation 4577 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4578 single_instruction; 4579 dst : E(write); 4580 IALU : R; 4581 %} 4582 4583 // Integer ALU reg-reg with carry operation 4584 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4585 single_instruction; 4586 dst : E(write); 4587 src1 : R(read); 4588 src2 : R(read); 4589 IALU : R; 4590 %} 4591 4592 // Integer ALU cc operation 4593 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4594 single_instruction; 4595 dst : E(write); 4596 cc : R(read); 4597 IALU : R; 4598 %} 4599 4600 // Integer ALU cc / second IALU operation 4601 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4602 instruction_count(1); multiple_bundles; 4603 dst : E(write)+1; 4604 src : R(read); 4605 IALU : R; 4606 %} 4607 4608 // Integer ALU cc / second IALU operation 4609 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4610 instruction_count(1); multiple_bundles; 4611 dst : E(write)+1; 4612 p : R(read); 4613 q : R(read); 4614 IALU : R; 4615 %} 4616 4617 // Integer ALU hi-lo-reg operation 4618 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4619 instruction_count(1); multiple_bundles; 4620 dst : E(write)+1; 4621 IALU : R(2); 4622 %} 4623 4624 // Float ALU hi-lo-reg operation (with temp) 4625 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4626 instruction_count(1); multiple_bundles; 4627 dst : E(write)+1; 4628 IALU : R(2); 4629 %} 4630 4631 // Long Constant 4632 pipe_class loadConL( iRegL dst, immL src ) %{ 4633 instruction_count(2); multiple_bundles; 4634 dst : E(write)+1; 4635 IALU : R(2); 4636 IALU : R(2); 4637 %} 4638 4639 // Pointer Constant 4640 pipe_class loadConP( iRegP dst, immP src ) %{ 4641 instruction_count(0); multiple_bundles; 4642 fixed_latency(6); 4643 %} 4644 4645 // Polling Address 4646 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4647 #ifdef _LP64 4648 instruction_count(0); multiple_bundles; 4649 fixed_latency(6); 4650 #else 4651 dst : E(write); 4652 IALU : R; 4653 #endif 4654 %} 4655 4656 // Long Constant small 4657 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4658 instruction_count(2); 4659 dst : E(write); 4660 IALU : R; 4661 IALU : R; 4662 %} 4663 4664 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4665 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4666 instruction_count(1); multiple_bundles; 4667 src : R(read); 4668 dst : M(write)+1; 4669 IALU : R; 4670 MS : E; 4671 %} 4672 4673 // Integer ALU nop operation 4674 pipe_class ialu_nop() %{ 4675 single_instruction; 4676 IALU : R; 4677 %} 4678 4679 // Integer ALU nop operation 4680 pipe_class ialu_nop_A0() %{ 4681 single_instruction; 4682 A0 : R; 4683 %} 4684 4685 // Integer ALU nop operation 4686 pipe_class ialu_nop_A1() %{ 4687 single_instruction; 4688 A1 : R; 4689 %} 4690 4691 // Integer Multiply reg-reg operation 4692 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4693 single_instruction; 4694 dst : E(write); 4695 src1 : R(read); 4696 src2 : R(read); 4697 MS : R(5); 4698 %} 4699 4700 // Integer Multiply reg-imm operation 4701 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4702 single_instruction; 4703 dst : E(write); 4704 src1 : R(read); 4705 MS : R(5); 4706 %} 4707 4708 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4709 single_instruction; 4710 dst : E(write)+4; 4711 src1 : R(read); 4712 src2 : R(read); 4713 MS : R(6); 4714 %} 4715 4716 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4717 single_instruction; 4718 dst : E(write)+4; 4719 src1 : R(read); 4720 MS : R(6); 4721 %} 4722 4723 // Integer Divide reg-reg 4724 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4725 instruction_count(1); multiple_bundles; 4726 dst : E(write); 4727 temp : E(write); 4728 src1 : R(read); 4729 src2 : R(read); 4730 temp : R(read); 4731 MS : R(38); 4732 %} 4733 4734 // Integer Divide reg-imm 4735 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4736 instruction_count(1); multiple_bundles; 4737 dst : E(write); 4738 temp : E(write); 4739 src1 : R(read); 4740 temp : R(read); 4741 MS : R(38); 4742 %} 4743 4744 // Long Divide 4745 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4746 dst : E(write)+71; 4747 src1 : R(read); 4748 src2 : R(read)+1; 4749 MS : R(70); 4750 %} 4751 4752 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4753 dst : E(write)+71; 4754 src1 : R(read); 4755 MS : R(70); 4756 %} 4757 4758 // Floating Point Add Float 4759 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4760 single_instruction; 4761 dst : X(write); 4762 src1 : E(read); 4763 src2 : E(read); 4764 FA : R; 4765 %} 4766 4767 // Floating Point Add Double 4768 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4769 single_instruction; 4770 dst : X(write); 4771 src1 : E(read); 4772 src2 : E(read); 4773 FA : R; 4774 %} 4775 4776 // Floating Point Conditional Move based on integer flags 4777 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4778 single_instruction; 4779 dst : X(write); 4780 src : E(read); 4781 cr : R(read); 4782 FA : R(2); 4783 BR : R(2); 4784 %} 4785 4786 // Floating Point Conditional Move based on integer flags 4787 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4788 single_instruction; 4789 dst : X(write); 4790 src : E(read); 4791 cr : R(read); 4792 FA : R(2); 4793 BR : R(2); 4794 %} 4795 4796 // Floating Point Multiply Float 4797 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4798 single_instruction; 4799 dst : X(write); 4800 src1 : E(read); 4801 src2 : E(read); 4802 FM : R; 4803 %} 4804 4805 // Floating Point Multiply Double 4806 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4807 single_instruction; 4808 dst : X(write); 4809 src1 : E(read); 4810 src2 : E(read); 4811 FM : R; 4812 %} 4813 4814 // Floating Point Divide Float 4815 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4816 single_instruction; 4817 dst : X(write); 4818 src1 : E(read); 4819 src2 : E(read); 4820 FM : R; 4821 FDIV : C(14); 4822 %} 4823 4824 // Floating Point Divide Double 4825 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4826 single_instruction; 4827 dst : X(write); 4828 src1 : E(read); 4829 src2 : E(read); 4830 FM : R; 4831 FDIV : C(17); 4832 %} 4833 4834 // Floating Point Move/Negate/Abs Float 4835 pipe_class faddF_reg(regF dst, regF src) %{ 4836 single_instruction; 4837 dst : W(write); 4838 src : E(read); 4839 FA : R(1); 4840 %} 4841 4842 // Floating Point Move/Negate/Abs Double 4843 pipe_class faddD_reg(regD dst, regD src) %{ 4844 single_instruction; 4845 dst : W(write); 4846 src : E(read); 4847 FA : R; 4848 %} 4849 4850 // Floating Point Convert F->D 4851 pipe_class fcvtF2D(regD dst, regF src) %{ 4852 single_instruction; 4853 dst : X(write); 4854 src : E(read); 4855 FA : R; 4856 %} 4857 4858 // Floating Point Convert I->D 4859 pipe_class fcvtI2D(regD dst, regF src) %{ 4860 single_instruction; 4861 dst : X(write); 4862 src : E(read); 4863 FA : R; 4864 %} 4865 4866 // Floating Point Convert LHi->D 4867 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4868 single_instruction; 4869 dst : X(write); 4870 src : E(read); 4871 FA : R; 4872 %} 4873 4874 // Floating Point Convert L->D 4875 pipe_class fcvtL2D(regD dst, regF src) %{ 4876 single_instruction; 4877 dst : X(write); 4878 src : E(read); 4879 FA : R; 4880 %} 4881 4882 // Floating Point Convert L->F 4883 pipe_class fcvtL2F(regD dst, regF src) %{ 4884 single_instruction; 4885 dst : X(write); 4886 src : E(read); 4887 FA : R; 4888 %} 4889 4890 // Floating Point Convert D->F 4891 pipe_class fcvtD2F(regD dst, regF src) %{ 4892 single_instruction; 4893 dst : X(write); 4894 src : E(read); 4895 FA : R; 4896 %} 4897 4898 // Floating Point Convert I->L 4899 pipe_class fcvtI2L(regD dst, regF src) %{ 4900 single_instruction; 4901 dst : X(write); 4902 src : E(read); 4903 FA : R; 4904 %} 4905 4906 // Floating Point Convert D->F 4907 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4908 instruction_count(1); multiple_bundles; 4909 dst : X(write)+6; 4910 src : E(read); 4911 FA : R; 4912 %} 4913 4914 // Floating Point Convert D->L 4915 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4916 instruction_count(1); multiple_bundles; 4917 dst : X(write)+6; 4918 src : E(read); 4919 FA : R; 4920 %} 4921 4922 // Floating Point Convert F->I 4923 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4924 instruction_count(1); multiple_bundles; 4925 dst : X(write)+6; 4926 src : E(read); 4927 FA : R; 4928 %} 4929 4930 // Floating Point Convert F->L 4931 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4932 instruction_count(1); multiple_bundles; 4933 dst : X(write)+6; 4934 src : E(read); 4935 FA : R; 4936 %} 4937 4938 // Floating Point Convert I->F 4939 pipe_class fcvtI2F(regF dst, regF src) %{ 4940 single_instruction; 4941 dst : X(write); 4942 src : E(read); 4943 FA : R; 4944 %} 4945 4946 // Floating Point Compare 4947 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4948 single_instruction; 4949 cr : X(write); 4950 src1 : E(read); 4951 src2 : E(read); 4952 FA : R; 4953 %} 4954 4955 // Floating Point Compare 4956 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4957 single_instruction; 4958 cr : X(write); 4959 src1 : E(read); 4960 src2 : E(read); 4961 FA : R; 4962 %} 4963 4964 // Floating Add Nop 4965 pipe_class fadd_nop() %{ 4966 single_instruction; 4967 FA : R; 4968 %} 4969 4970 // Integer Store to Memory 4971 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4972 single_instruction; 4973 mem : R(read); 4974 src : C(read); 4975 MS : R; 4976 %} 4977 4978 // Integer Store to Memory 4979 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4980 single_instruction; 4981 mem : R(read); 4982 src : C(read); 4983 MS : R; 4984 %} 4985 4986 // Integer Store Zero to Memory 4987 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4988 single_instruction; 4989 mem : R(read); 4990 MS : R; 4991 %} 4992 4993 // Special Stack Slot Store 4994 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4995 single_instruction; 4996 stkSlot : R(read); 4997 src : C(read); 4998 MS : R; 4999 %} 5000 5001 // Special Stack Slot Store 5002 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5003 instruction_count(2); multiple_bundles; 5004 stkSlot : R(read); 5005 src : C(read); 5006 MS : R(2); 5007 %} 5008 5009 // Float Store 5010 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5011 single_instruction; 5012 mem : R(read); 5013 src : C(read); 5014 MS : R; 5015 %} 5016 5017 // Float Store 5018 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5019 single_instruction; 5020 mem : R(read); 5021 MS : R; 5022 %} 5023 5024 // Double Store 5025 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5026 instruction_count(1); 5027 mem : R(read); 5028 src : C(read); 5029 MS : R; 5030 %} 5031 5032 // Double Store 5033 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5034 single_instruction; 5035 mem : R(read); 5036 MS : R; 5037 %} 5038 5039 // Special Stack Slot Float Store 5040 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5041 single_instruction; 5042 stkSlot : R(read); 5043 src : C(read); 5044 MS : R; 5045 %} 5046 5047 // Special Stack Slot Double Store 5048 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5049 single_instruction; 5050 stkSlot : R(read); 5051 src : C(read); 5052 MS : R; 5053 %} 5054 5055 // Integer Load (when sign bit propagation not needed) 5056 pipe_class iload_mem(iRegI dst, memory mem) %{ 5057 single_instruction; 5058 mem : R(read); 5059 dst : C(write); 5060 MS : R; 5061 %} 5062 5063 // Integer Load from stack operand 5064 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5065 single_instruction; 5066 mem : R(read); 5067 dst : C(write); 5068 MS : R; 5069 %} 5070 5071 // Integer Load (when sign bit propagation or masking is needed) 5072 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5073 single_instruction; 5074 mem : R(read); 5075 dst : M(write); 5076 MS : R; 5077 %} 5078 5079 // Float Load 5080 pipe_class floadF_mem(regF dst, memory mem) %{ 5081 single_instruction; 5082 mem : R(read); 5083 dst : M(write); 5084 MS : R; 5085 %} 5086 5087 // Float Load 5088 pipe_class floadD_mem(regD dst, memory mem) %{ 5089 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5090 mem : R(read); 5091 dst : M(write); 5092 MS : R; 5093 %} 5094 5095 // Float Load 5096 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5097 single_instruction; 5098 stkSlot : R(read); 5099 dst : M(write); 5100 MS : R; 5101 %} 5102 5103 // Float Load 5104 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5105 single_instruction; 5106 stkSlot : R(read); 5107 dst : M(write); 5108 MS : R; 5109 %} 5110 5111 // Memory Nop 5112 pipe_class mem_nop() %{ 5113 single_instruction; 5114 MS : R; 5115 %} 5116 5117 pipe_class sethi(iRegP dst, immI src) %{ 5118 single_instruction; 5119 dst : E(write); 5120 IALU : R; 5121 %} 5122 5123 pipe_class loadPollP(iRegP poll) %{ 5124 single_instruction; 5125 poll : R(read); 5126 MS : R; 5127 %} 5128 5129 pipe_class br(Universe br, label labl) %{ 5130 single_instruction_with_delay_slot; 5131 BR : R; 5132 %} 5133 5134 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5135 single_instruction_with_delay_slot; 5136 cr : E(read); 5137 BR : R; 5138 %} 5139 5140 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5141 single_instruction_with_delay_slot; 5142 op1 : E(read); 5143 BR : R; 5144 MS : R; 5145 %} 5146 5147 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5148 single_instruction_with_delay_slot; 5149 cr : E(read); 5150 BR : R; 5151 %} 5152 5153 pipe_class br_nop() %{ 5154 single_instruction; 5155 BR : R; 5156 %} 5157 5158 pipe_class simple_call(method meth) %{ 5159 instruction_count(2); multiple_bundles; force_serialization; 5160 fixed_latency(100); 5161 BR : R(1); 5162 MS : R(1); 5163 A0 : R(1); 5164 %} 5165 5166 pipe_class compiled_call(method meth) %{ 5167 instruction_count(1); multiple_bundles; force_serialization; 5168 fixed_latency(100); 5169 MS : R(1); 5170 %} 5171 5172 pipe_class call(method meth) %{ 5173 instruction_count(0); multiple_bundles; force_serialization; 5174 fixed_latency(100); 5175 %} 5176 5177 pipe_class tail_call(Universe ignore, label labl) %{ 5178 single_instruction; has_delay_slot; 5179 fixed_latency(100); 5180 BR : R(1); 5181 MS : R(1); 5182 %} 5183 5184 pipe_class ret(Universe ignore) %{ 5185 single_instruction; has_delay_slot; 5186 BR : R(1); 5187 MS : R(1); 5188 %} 5189 5190 pipe_class ret_poll(g3RegP poll) %{ 5191 instruction_count(3); has_delay_slot; 5192 poll : E(read); 5193 MS : R; 5194 %} 5195 5196 // The real do-nothing guy 5197 pipe_class empty( ) %{ 5198 instruction_count(0); 5199 %} 5200 5201 pipe_class long_memory_op() %{ 5202 instruction_count(0); multiple_bundles; force_serialization; 5203 fixed_latency(25); 5204 MS : R(1); 5205 %} 5206 5207 // Check-cast 5208 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5209 array : R(read); 5210 match : R(read); 5211 IALU : R(2); 5212 BR : R(2); 5213 MS : R; 5214 %} 5215 5216 // Convert FPU flags into +1,0,-1 5217 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5218 src1 : E(read); 5219 src2 : E(read); 5220 dst : E(write); 5221 FA : R; 5222 MS : R(2); 5223 BR : R(2); 5224 %} 5225 5226 // Compare for p < q, and conditionally add y 5227 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5228 p : E(read); 5229 q : E(read); 5230 y : E(read); 5231 IALU : R(3) 5232 %} 5233 5234 // Perform a compare, then move conditionally in a branch delay slot. 5235 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5236 src2 : E(read); 5237 srcdst : E(read); 5238 IALU : R; 5239 BR : R; 5240 %} 5241 5242 // Define the class for the Nop node 5243 define %{ 5244 MachNop = ialu_nop; 5245 %} 5246 5247 %} 5248 5249 //----------INSTRUCTIONS------------------------------------------------------- 5250 5251 //------------Special Stack Slot instructions - no match rules----------------- 5252 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5253 // No match rule to avoid chain rule match. 5254 effect(DEF dst, USE src); 5255 ins_cost(MEMORY_REF_COST); 5256 size(4); 5257 format %{ "LDF $src,$dst\t! stkI to regF" %} 5258 opcode(Assembler::ldf_op3); 5259 ins_encode(simple_form3_mem_reg(src, dst)); 5260 ins_pipe(floadF_stk); 5261 %} 5262 5263 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5264 // No match rule to avoid chain rule match. 5265 effect(DEF dst, USE src); 5266 ins_cost(MEMORY_REF_COST); 5267 size(4); 5268 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5269 opcode(Assembler::lddf_op3); 5270 ins_encode(simple_form3_mem_reg(src, dst)); 5271 ins_pipe(floadD_stk); 5272 %} 5273 5274 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5275 // No match rule to avoid chain rule match. 5276 effect(DEF dst, USE src); 5277 ins_cost(MEMORY_REF_COST); 5278 size(4); 5279 format %{ "STF $src,$dst\t! regF to stkI" %} 5280 opcode(Assembler::stf_op3); 5281 ins_encode(simple_form3_mem_reg(dst, src)); 5282 ins_pipe(fstoreF_stk_reg); 5283 %} 5284 5285 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5286 // No match rule to avoid chain rule match. 5287 effect(DEF dst, USE src); 5288 ins_cost(MEMORY_REF_COST); 5289 size(4); 5290 format %{ "STDF $src,$dst\t! regD to stkL" %} 5291 opcode(Assembler::stdf_op3); 5292 ins_encode(simple_form3_mem_reg(dst, src)); 5293 ins_pipe(fstoreD_stk_reg); 5294 %} 5295 5296 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5297 effect(DEF dst, USE src); 5298 ins_cost(MEMORY_REF_COST*2); 5299 size(8); 5300 format %{ "STW $src,$dst.hi\t! long\n\t" 5301 "STW R_G0,$dst.lo" %} 5302 opcode(Assembler::stw_op3); 5303 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5304 ins_pipe(lstoreI_stk_reg); 5305 %} 5306 5307 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5308 // No match rule to avoid chain rule match. 5309 effect(DEF dst, USE src); 5310 ins_cost(MEMORY_REF_COST); 5311 size(4); 5312 format %{ "STX $src,$dst\t! regL to stkD" %} 5313 opcode(Assembler::stx_op3); 5314 ins_encode(simple_form3_mem_reg( dst, src ) ); 5315 ins_pipe(istore_stk_reg); 5316 %} 5317 5318 //---------- Chain stack slots between similar types -------- 5319 5320 // Load integer from stack slot 5321 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5322 match(Set dst src); 5323 ins_cost(MEMORY_REF_COST); 5324 5325 size(4); 5326 format %{ "LDUW $src,$dst\t!stk" %} 5327 opcode(Assembler::lduw_op3); 5328 ins_encode(simple_form3_mem_reg( src, dst ) ); 5329 ins_pipe(iload_mem); 5330 %} 5331 5332 // Store integer to stack slot 5333 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5334 match(Set dst src); 5335 ins_cost(MEMORY_REF_COST); 5336 5337 size(4); 5338 format %{ "STW $src,$dst\t!stk" %} 5339 opcode(Assembler::stw_op3); 5340 ins_encode(simple_form3_mem_reg( dst, src ) ); 5341 ins_pipe(istore_mem_reg); 5342 %} 5343 5344 // Load long from stack slot 5345 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5346 match(Set dst src); 5347 5348 ins_cost(MEMORY_REF_COST); 5349 size(4); 5350 format %{ "LDX $src,$dst\t! long" %} 5351 opcode(Assembler::ldx_op3); 5352 ins_encode(simple_form3_mem_reg( src, dst ) ); 5353 ins_pipe(iload_mem); 5354 %} 5355 5356 // Store long to stack slot 5357 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5358 match(Set dst src); 5359 5360 ins_cost(MEMORY_REF_COST); 5361 size(4); 5362 format %{ "STX $src,$dst\t! long" %} 5363 opcode(Assembler::stx_op3); 5364 ins_encode(simple_form3_mem_reg( dst, src ) ); 5365 ins_pipe(istore_mem_reg); 5366 %} 5367 5368 #ifdef _LP64 5369 // Load pointer from stack slot, 64-bit encoding 5370 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5371 match(Set dst src); 5372 ins_cost(MEMORY_REF_COST); 5373 size(4); 5374 format %{ "LDX $src,$dst\t!ptr" %} 5375 opcode(Assembler::ldx_op3); 5376 ins_encode(simple_form3_mem_reg( src, dst ) ); 5377 ins_pipe(iload_mem); 5378 %} 5379 5380 // Store pointer to stack slot 5381 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5382 match(Set dst src); 5383 ins_cost(MEMORY_REF_COST); 5384 size(4); 5385 format %{ "STX $src,$dst\t!ptr" %} 5386 opcode(Assembler::stx_op3); 5387 ins_encode(simple_form3_mem_reg( dst, src ) ); 5388 ins_pipe(istore_mem_reg); 5389 %} 5390 #else // _LP64 5391 // Load pointer from stack slot, 32-bit encoding 5392 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5393 match(Set dst src); 5394 ins_cost(MEMORY_REF_COST); 5395 format %{ "LDUW $src,$dst\t!ptr" %} 5396 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5397 ins_encode(simple_form3_mem_reg( src, dst ) ); 5398 ins_pipe(iload_mem); 5399 %} 5400 5401 // Store pointer to stack slot 5402 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5403 match(Set dst src); 5404 ins_cost(MEMORY_REF_COST); 5405 format %{ "STW $src,$dst\t!ptr" %} 5406 opcode(Assembler::stw_op3, Assembler::ldst_op); 5407 ins_encode(simple_form3_mem_reg( dst, src ) ); 5408 ins_pipe(istore_mem_reg); 5409 %} 5410 #endif // _LP64 5411 5412 //------------Special Nop instructions for bundling - no match rules----------- 5413 // Nop using the A0 functional unit 5414 instruct Nop_A0() %{ 5415 ins_cost(0); 5416 5417 format %{ "NOP ! Alu Pipeline" %} 5418 opcode(Assembler::or_op3, Assembler::arith_op); 5419 ins_encode( form2_nop() ); 5420 ins_pipe(ialu_nop_A0); 5421 %} 5422 5423 // Nop using the A1 functional unit 5424 instruct Nop_A1( ) %{ 5425 ins_cost(0); 5426 5427 format %{ "NOP ! Alu Pipeline" %} 5428 opcode(Assembler::or_op3, Assembler::arith_op); 5429 ins_encode( form2_nop() ); 5430 ins_pipe(ialu_nop_A1); 5431 %} 5432 5433 // Nop using the memory functional unit 5434 instruct Nop_MS( ) %{ 5435 ins_cost(0); 5436 5437 format %{ "NOP ! Memory Pipeline" %} 5438 ins_encode( emit_mem_nop ); 5439 ins_pipe(mem_nop); 5440 %} 5441 5442 // Nop using the floating add functional unit 5443 instruct Nop_FA( ) %{ 5444 ins_cost(0); 5445 5446 format %{ "NOP ! Floating Add Pipeline" %} 5447 ins_encode( emit_fadd_nop ); 5448 ins_pipe(fadd_nop); 5449 %} 5450 5451 // Nop using the branch functional unit 5452 instruct Nop_BR( ) %{ 5453 ins_cost(0); 5454 5455 format %{ "NOP ! Branch Pipeline" %} 5456 ins_encode( emit_br_nop ); 5457 ins_pipe(br_nop); 5458 %} 5459 5460 //----------Load/Store/Move Instructions--------------------------------------- 5461 //----------Load Instructions-------------------------------------------------- 5462 // Load Byte (8bit signed) 5463 instruct loadB(iRegI dst, memory mem) %{ 5464 match(Set dst (LoadB mem)); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 size(4); 5468 format %{ "LDSB $mem,$dst\t! byte" %} 5469 ins_encode %{ 5470 __ ldsb($mem$$Address, $dst$$Register); 5471 %} 5472 ins_pipe(iload_mask_mem); 5473 %} 5474 5475 // Load Byte (8bit signed) into a Long Register 5476 instruct loadB2L(iRegL dst, memory mem) %{ 5477 match(Set dst (ConvI2L (LoadB mem))); 5478 ins_cost(MEMORY_REF_COST); 5479 5480 size(4); 5481 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5482 ins_encode %{ 5483 __ ldsb($mem$$Address, $dst$$Register); 5484 %} 5485 ins_pipe(iload_mask_mem); 5486 %} 5487 5488 // Load Unsigned Byte (8bit UNsigned) into an int reg 5489 instruct loadUB(iRegI dst, memory mem) %{ 5490 match(Set dst (LoadUB mem)); 5491 ins_cost(MEMORY_REF_COST); 5492 5493 size(4); 5494 format %{ "LDUB $mem,$dst\t! ubyte" %} 5495 ins_encode %{ 5496 __ ldub($mem$$Address, $dst$$Register); 5497 %} 5498 ins_pipe(iload_mem); 5499 %} 5500 5501 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5502 instruct loadUB2L(iRegL dst, memory mem) %{ 5503 match(Set dst (ConvI2L (LoadUB mem))); 5504 ins_cost(MEMORY_REF_COST); 5505 5506 size(4); 5507 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5508 ins_encode %{ 5509 __ ldub($mem$$Address, $dst$$Register); 5510 %} 5511 ins_pipe(iload_mem); 5512 %} 5513 5514 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5515 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5516 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5517 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5518 5519 size(2*4); 5520 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5521 "AND $dst,$mask,$dst" %} 5522 ins_encode %{ 5523 __ ldub($mem$$Address, $dst$$Register); 5524 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5525 %} 5526 ins_pipe(iload_mem); 5527 %} 5528 5529 // Load Short (16bit signed) 5530 instruct loadS(iRegI dst, memory mem) %{ 5531 match(Set dst (LoadS mem)); 5532 ins_cost(MEMORY_REF_COST); 5533 5534 size(4); 5535 format %{ "LDSH $mem,$dst\t! short" %} 5536 ins_encode %{ 5537 __ ldsh($mem$$Address, $dst$$Register); 5538 %} 5539 ins_pipe(iload_mask_mem); 5540 %} 5541 5542 // Load Short (16 bit signed) to Byte (8 bit signed) 5543 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5544 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5545 ins_cost(MEMORY_REF_COST); 5546 5547 size(4); 5548 5549 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5550 ins_encode %{ 5551 __ ldsb($mem$$Address, $dst$$Register, 1); 5552 %} 5553 ins_pipe(iload_mask_mem); 5554 %} 5555 5556 // Load Short (16bit signed) into a Long Register 5557 instruct loadS2L(iRegL dst, memory mem) %{ 5558 match(Set dst (ConvI2L (LoadS mem))); 5559 ins_cost(MEMORY_REF_COST); 5560 5561 size(4); 5562 format %{ "LDSH $mem,$dst\t! short -> long" %} 5563 ins_encode %{ 5564 __ ldsh($mem$$Address, $dst$$Register); 5565 %} 5566 ins_pipe(iload_mask_mem); 5567 %} 5568 5569 // Load Unsigned Short/Char (16bit UNsigned) 5570 instruct loadUS(iRegI dst, memory mem) %{ 5571 match(Set dst (LoadUS mem)); 5572 ins_cost(MEMORY_REF_COST); 5573 5574 size(4); 5575 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5576 ins_encode %{ 5577 __ lduh($mem$$Address, $dst$$Register); 5578 %} 5579 ins_pipe(iload_mem); 5580 %} 5581 5582 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5583 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5584 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5585 ins_cost(MEMORY_REF_COST); 5586 5587 size(4); 5588 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5589 ins_encode %{ 5590 __ ldsb($mem$$Address, $dst$$Register, 1); 5591 %} 5592 ins_pipe(iload_mask_mem); 5593 %} 5594 5595 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5596 instruct loadUS2L(iRegL dst, memory mem) %{ 5597 match(Set dst (ConvI2L (LoadUS mem))); 5598 ins_cost(MEMORY_REF_COST); 5599 5600 size(4); 5601 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5602 ins_encode %{ 5603 __ lduh($mem$$Address, $dst$$Register); 5604 %} 5605 ins_pipe(iload_mem); 5606 %} 5607 5608 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5609 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5610 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5611 ins_cost(MEMORY_REF_COST); 5612 5613 size(4); 5614 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5615 ins_encode %{ 5616 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5617 %} 5618 ins_pipe(iload_mem); 5619 %} 5620 5621 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5622 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5623 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5624 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5625 5626 size(2*4); 5627 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5628 "AND $dst,$mask,$dst" %} 5629 ins_encode %{ 5630 Register Rdst = $dst$$Register; 5631 __ lduh($mem$$Address, Rdst); 5632 __ and3(Rdst, $mask$$constant, Rdst); 5633 %} 5634 ins_pipe(iload_mem); 5635 %} 5636 5637 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5638 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5639 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5640 effect(TEMP dst, TEMP tmp); 5641 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5642 5643 size((3+1)*4); // set may use two instructions. 5644 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5645 "SET $mask,$tmp\n\t" 5646 "AND $dst,$tmp,$dst" %} 5647 ins_encode %{ 5648 Register Rdst = $dst$$Register; 5649 Register Rtmp = $tmp$$Register; 5650 __ lduh($mem$$Address, Rdst); 5651 __ set($mask$$constant, Rtmp); 5652 __ and3(Rdst, Rtmp, Rdst); 5653 %} 5654 ins_pipe(iload_mem); 5655 %} 5656 5657 // Load Integer 5658 instruct loadI(iRegI dst, memory mem) %{ 5659 match(Set dst (LoadI mem)); 5660 ins_cost(MEMORY_REF_COST); 5661 5662 size(4); 5663 format %{ "LDUW $mem,$dst\t! int" %} 5664 ins_encode %{ 5665 __ lduw($mem$$Address, $dst$$Register); 5666 %} 5667 ins_pipe(iload_mem); 5668 %} 5669 5670 // Load Integer to Byte (8 bit signed) 5671 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5672 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5673 ins_cost(MEMORY_REF_COST); 5674 5675 size(4); 5676 5677 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5678 ins_encode %{ 5679 __ ldsb($mem$$Address, $dst$$Register, 3); 5680 %} 5681 ins_pipe(iload_mask_mem); 5682 %} 5683 5684 // Load Integer to Unsigned Byte (8 bit UNsigned) 5685 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5686 match(Set dst (AndI (LoadI mem) mask)); 5687 ins_cost(MEMORY_REF_COST); 5688 5689 size(4); 5690 5691 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5692 ins_encode %{ 5693 __ ldub($mem$$Address, $dst$$Register, 3); 5694 %} 5695 ins_pipe(iload_mask_mem); 5696 %} 5697 5698 // Load Integer to Short (16 bit signed) 5699 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5700 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5701 ins_cost(MEMORY_REF_COST); 5702 5703 size(4); 5704 5705 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5706 ins_encode %{ 5707 __ ldsh($mem$$Address, $dst$$Register, 2); 5708 %} 5709 ins_pipe(iload_mask_mem); 5710 %} 5711 5712 // Load Integer to Unsigned Short (16 bit UNsigned) 5713 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5714 match(Set dst (AndI (LoadI mem) mask)); 5715 ins_cost(MEMORY_REF_COST); 5716 5717 size(4); 5718 5719 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5720 ins_encode %{ 5721 __ lduh($mem$$Address, $dst$$Register, 2); 5722 %} 5723 ins_pipe(iload_mask_mem); 5724 %} 5725 5726 // Load Integer into a Long Register 5727 instruct loadI2L(iRegL dst, memory mem) %{ 5728 match(Set dst (ConvI2L (LoadI mem))); 5729 ins_cost(MEMORY_REF_COST); 5730 5731 size(4); 5732 format %{ "LDSW $mem,$dst\t! int -> long" %} 5733 ins_encode %{ 5734 __ ldsw($mem$$Address, $dst$$Register); 5735 %} 5736 ins_pipe(iload_mask_mem); 5737 %} 5738 5739 // Load Integer with mask 0xFF into a Long Register 5740 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5741 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5742 ins_cost(MEMORY_REF_COST); 5743 5744 size(4); 5745 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5746 ins_encode %{ 5747 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5748 %} 5749 ins_pipe(iload_mem); 5750 %} 5751 5752 // Load Integer with mask 0xFFFF into a Long Register 5753 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5754 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5755 ins_cost(MEMORY_REF_COST); 5756 5757 size(4); 5758 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5759 ins_encode %{ 5760 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5761 %} 5762 ins_pipe(iload_mem); 5763 %} 5764 5765 // Load Integer with a 13-bit mask into a Long Register 5766 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5767 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5768 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5769 5770 size(2*4); 5771 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5772 "AND $dst,$mask,$dst" %} 5773 ins_encode %{ 5774 Register Rdst = $dst$$Register; 5775 __ lduw($mem$$Address, Rdst); 5776 __ and3(Rdst, $mask$$constant, Rdst); 5777 %} 5778 ins_pipe(iload_mem); 5779 %} 5780 5781 // Load Integer with a 32-bit mask into a Long Register 5782 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5783 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5784 effect(TEMP dst, TEMP tmp); 5785 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5786 5787 size((3+1)*4); // set may use two instructions. 5788 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5789 "SET $mask,$tmp\n\t" 5790 "AND $dst,$tmp,$dst" %} 5791 ins_encode %{ 5792 Register Rdst = $dst$$Register; 5793 Register Rtmp = $tmp$$Register; 5794 __ lduw($mem$$Address, Rdst); 5795 __ set($mask$$constant, Rtmp); 5796 __ and3(Rdst, Rtmp, Rdst); 5797 %} 5798 ins_pipe(iload_mem); 5799 %} 5800 5801 // Load Unsigned Integer into a Long Register 5802 instruct loadUI2L(iRegL dst, memory mem) %{ 5803 match(Set dst (LoadUI2L mem)); 5804 ins_cost(MEMORY_REF_COST); 5805 5806 size(4); 5807 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5808 ins_encode %{ 5809 __ lduw($mem$$Address, $dst$$Register); 5810 %} 5811 ins_pipe(iload_mem); 5812 %} 5813 5814 // Load Long - aligned 5815 instruct loadL(iRegL dst, memory mem ) %{ 5816 match(Set dst (LoadL mem)); 5817 ins_cost(MEMORY_REF_COST); 5818 5819 size(4); 5820 format %{ "LDX $mem,$dst\t! long" %} 5821 ins_encode %{ 5822 __ ldx($mem$$Address, $dst$$Register); 5823 %} 5824 ins_pipe(iload_mem); 5825 %} 5826 5827 // Load Long - UNaligned 5828 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5829 match(Set dst (LoadL_unaligned mem)); 5830 effect(KILL tmp); 5831 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5832 size(16); 5833 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5834 "\tLDUW $mem ,$dst\n" 5835 "\tSLLX #32, $dst, $dst\n" 5836 "\tOR $dst, R_O7, $dst" %} 5837 opcode(Assembler::lduw_op3); 5838 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5839 ins_pipe(iload_mem); 5840 %} 5841 5842 // Load Aligned Packed Byte into a Double Register 5843 instruct loadA8B(regD dst, memory mem) %{ 5844 match(Set dst (Load8B mem)); 5845 ins_cost(MEMORY_REF_COST); 5846 size(4); 5847 format %{ "LDDF $mem,$dst\t! packed8B" %} 5848 opcode(Assembler::lddf_op3); 5849 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5850 ins_pipe(floadD_mem); 5851 %} 5852 5853 // Load Aligned Packed Char into a Double Register 5854 instruct loadA4C(regD dst, memory mem) %{ 5855 match(Set dst (Load4C mem)); 5856 ins_cost(MEMORY_REF_COST); 5857 size(4); 5858 format %{ "LDDF $mem,$dst\t! packed4C" %} 5859 opcode(Assembler::lddf_op3); 5860 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5861 ins_pipe(floadD_mem); 5862 %} 5863 5864 // Load Aligned Packed Short into a Double Register 5865 instruct loadA4S(regD dst, memory mem) %{ 5866 match(Set dst (Load4S mem)); 5867 ins_cost(MEMORY_REF_COST); 5868 size(4); 5869 format %{ "LDDF $mem,$dst\t! packed4S" %} 5870 opcode(Assembler::lddf_op3); 5871 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5872 ins_pipe(floadD_mem); 5873 %} 5874 5875 // Load Aligned Packed Int into a Double Register 5876 instruct loadA2I(regD dst, memory mem) %{ 5877 match(Set dst (Load2I mem)); 5878 ins_cost(MEMORY_REF_COST); 5879 size(4); 5880 format %{ "LDDF $mem,$dst\t! packed2I" %} 5881 opcode(Assembler::lddf_op3); 5882 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5883 ins_pipe(floadD_mem); 5884 %} 5885 5886 // Load Range 5887 instruct loadRange(iRegI dst, memory mem) %{ 5888 match(Set dst (LoadRange mem)); 5889 ins_cost(MEMORY_REF_COST); 5890 5891 size(4); 5892 format %{ "LDUW $mem,$dst\t! range" %} 5893 opcode(Assembler::lduw_op3); 5894 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5895 ins_pipe(iload_mem); 5896 %} 5897 5898 // Load Integer into %f register (for fitos/fitod) 5899 instruct loadI_freg(regF dst, memory mem) %{ 5900 match(Set dst (LoadI mem)); 5901 ins_cost(MEMORY_REF_COST); 5902 size(4); 5903 5904 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5905 opcode(Assembler::ldf_op3); 5906 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5907 ins_pipe(floadF_mem); 5908 %} 5909 5910 // Load Pointer 5911 instruct loadP(iRegP dst, memory mem) %{ 5912 match(Set dst (LoadP mem)); 5913 ins_cost(MEMORY_REF_COST); 5914 size(4); 5915 5916 #ifndef _LP64 5917 format %{ "LDUW $mem,$dst\t! ptr" %} 5918 ins_encode %{ 5919 __ lduw($mem$$Address, $dst$$Register); 5920 %} 5921 #else 5922 format %{ "LDX $mem,$dst\t! ptr" %} 5923 ins_encode %{ 5924 __ ldx($mem$$Address, $dst$$Register); 5925 %} 5926 #endif 5927 ins_pipe(iload_mem); 5928 %} 5929 5930 // Load Compressed Pointer 5931 instruct loadN(iRegN dst, memory mem) %{ 5932 match(Set dst (LoadN mem)); 5933 ins_cost(MEMORY_REF_COST); 5934 size(4); 5935 5936 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5937 ins_encode %{ 5938 __ lduw($mem$$Address, $dst$$Register); 5939 %} 5940 ins_pipe(iload_mem); 5941 %} 5942 5943 // Load Klass Pointer 5944 instruct loadKlass(iRegP dst, memory mem) %{ 5945 match(Set dst (LoadKlass mem)); 5946 ins_cost(MEMORY_REF_COST); 5947 size(4); 5948 5949 #ifndef _LP64 5950 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5951 ins_encode %{ 5952 __ lduw($mem$$Address, $dst$$Register); 5953 %} 5954 #else 5955 format %{ "LDX $mem,$dst\t! klass ptr" %} 5956 ins_encode %{ 5957 __ ldx($mem$$Address, $dst$$Register); 5958 %} 5959 #endif 5960 ins_pipe(iload_mem); 5961 %} 5962 5963 // Load narrow Klass Pointer 5964 instruct loadNKlass(iRegN dst, memory mem) %{ 5965 match(Set dst (LoadNKlass mem)); 5966 ins_cost(MEMORY_REF_COST); 5967 size(4); 5968 5969 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5970 ins_encode %{ 5971 __ lduw($mem$$Address, $dst$$Register); 5972 %} 5973 ins_pipe(iload_mem); 5974 %} 5975 5976 // Load Double 5977 instruct loadD(regD dst, memory mem) %{ 5978 match(Set dst (LoadD mem)); 5979 ins_cost(MEMORY_REF_COST); 5980 5981 size(4); 5982 format %{ "LDDF $mem,$dst" %} 5983 opcode(Assembler::lddf_op3); 5984 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5985 ins_pipe(floadD_mem); 5986 %} 5987 5988 // Load Double - UNaligned 5989 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5990 match(Set dst (LoadD_unaligned mem)); 5991 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5992 size(8); 5993 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5994 "\tLDF $mem+4,$dst.lo\t!" %} 5995 opcode(Assembler::ldf_op3); 5996 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5997 ins_pipe(iload_mem); 5998 %} 5999 6000 // Load Float 6001 instruct loadF(regF dst, memory mem) %{ 6002 match(Set dst (LoadF mem)); 6003 ins_cost(MEMORY_REF_COST); 6004 6005 size(4); 6006 format %{ "LDF $mem,$dst" %} 6007 opcode(Assembler::ldf_op3); 6008 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6009 ins_pipe(floadF_mem); 6010 %} 6011 6012 // Load Constant 6013 instruct loadConI( iRegI dst, immI src ) %{ 6014 match(Set dst src); 6015 ins_cost(DEFAULT_COST * 3/2); 6016 format %{ "SET $src,$dst" %} 6017 ins_encode( Set32(src, dst) ); 6018 ins_pipe(ialu_hi_lo_reg); 6019 %} 6020 6021 instruct loadConI13( iRegI dst, immI13 src ) %{ 6022 match(Set dst src); 6023 6024 size(4); 6025 format %{ "MOV $src,$dst" %} 6026 ins_encode( Set13( src, dst ) ); 6027 ins_pipe(ialu_imm); 6028 %} 6029 6030 instruct loadConP(iRegP dst, immP con) %{ 6031 match(Set dst con); 6032 #ifndef _LP64 6033 ins_cost(DEFAULT_COST * 3/2); 6034 format %{ "SET $con,$dst\t!ptr" %} 6035 ins_encode %{ 6036 // [RGV] This next line should be generated from ADLC 6037 if (_opnds[1]->constant_is_oop()) { 6038 intptr_t val = $con$$constant; 6039 __ set_oop_constant((jobject) val, $dst$$Register); 6040 } else { // non-oop pointers, e.g. card mark base, heap top 6041 __ set($con$$constant, $dst$$Register); 6042 } 6043 %} 6044 #else 6045 ins_cost(MEMORY_REF_COST); 6046 size(4); 6047 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6048 ins_encode %{ 6049 __ ld_ptr($constanttablebase, $constantoffset($con), $dst$$Register); 6050 %} 6051 #endif 6052 ins_pipe(loadConP); 6053 %} 6054 6055 instruct loadConP0(iRegP dst, immP0 src) %{ 6056 match(Set dst src); 6057 6058 size(4); 6059 format %{ "CLR $dst\t!ptr" %} 6060 ins_encode %{ 6061 __ clr($dst$$Register); 6062 %} 6063 ins_pipe(ialu_imm); 6064 %} 6065 6066 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6067 match(Set dst src); 6068 ins_cost(DEFAULT_COST); 6069 format %{ "SET $src,$dst\t!ptr" %} 6070 ins_encode %{ 6071 AddressLiteral polling_page(os::get_polling_page()); 6072 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6073 %} 6074 ins_pipe(loadConP_poll); 6075 %} 6076 6077 instruct loadConN0(iRegN dst, immN0 src) %{ 6078 match(Set dst src); 6079 6080 size(4); 6081 format %{ "CLR $dst\t! compressed NULL ptr" %} 6082 ins_encode %{ 6083 __ clr($dst$$Register); 6084 %} 6085 ins_pipe(ialu_imm); 6086 %} 6087 6088 instruct loadConN(iRegN dst, immN src) %{ 6089 match(Set dst src); 6090 ins_cost(DEFAULT_COST * 3/2); 6091 format %{ "SET $src,$dst\t! compressed ptr" %} 6092 ins_encode %{ 6093 Register dst = $dst$$Register; 6094 __ set_narrow_oop((jobject)$src$$constant, dst); 6095 %} 6096 ins_pipe(ialu_hi_lo_reg); 6097 %} 6098 6099 // Materialize long value (predicated by immL_cheap). 6100 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6101 match(Set dst con); 6102 effect(KILL tmp); 6103 ins_cost(DEFAULT_COST * 3); 6104 format %{ "SET64 $con,$dst KILL $tmp\t! long" %} 6105 ins_encode %{ 6106 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6107 %} 6108 ins_pipe(loadConL); 6109 %} 6110 6111 // Load long value from constant table (predicated by immL_expensive). 6112 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6113 match(Set dst con); 6114 ins_cost(MEMORY_REF_COST); 6115 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6116 ins_encode %{ 6117 __ ldx($constanttablebase, $constantoffset($con), $dst$$Register); 6118 %} 6119 ins_pipe(loadConL); 6120 %} 6121 6122 instruct loadConL0( iRegL dst, immL0 src ) %{ 6123 match(Set dst src); 6124 ins_cost(DEFAULT_COST); 6125 size(4); 6126 format %{ "CLR $dst\t! long" %} 6127 ins_encode( Set13( src, dst ) ); 6128 ins_pipe(ialu_imm); 6129 %} 6130 6131 instruct loadConL13( iRegL dst, immL13 src ) %{ 6132 match(Set dst src); 6133 ins_cost(DEFAULT_COST * 2); 6134 6135 size(4); 6136 format %{ "MOV $src,$dst\t! long" %} 6137 ins_encode( Set13( src, dst ) ); 6138 ins_pipe(ialu_imm); 6139 %} 6140 6141 instruct loadConF(regF dst, immF con) %{ 6142 match(Set dst con); 6143 size(4); 6144 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6145 ins_encode %{ 6146 __ ldf(FloatRegisterImpl::S, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6147 %} 6148 ins_pipe(loadConFD); 6149 %} 6150 6151 instruct loadConD(regD dst, immD con) %{ 6152 match(Set dst con); 6153 size(4); 6154 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6155 ins_encode %{ 6156 // XXX This is a quick fix for 6833573. 6157 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6158 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), as_DoubleFloatRegister($dst$$reg)); 6159 %} 6160 ins_pipe(loadConFD); 6161 %} 6162 6163 // Prefetch instructions. 6164 // Must be safe to execute with invalid address (cannot fault). 6165 6166 instruct prefetchr( memory mem ) %{ 6167 match( PrefetchRead mem ); 6168 ins_cost(MEMORY_REF_COST); 6169 6170 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6171 opcode(Assembler::prefetch_op3); 6172 ins_encode( form3_mem_prefetch_read( mem ) ); 6173 ins_pipe(iload_mem); 6174 %} 6175 6176 instruct prefetchw( memory mem ) %{ 6177 predicate(AllocatePrefetchStyle != 3 ); 6178 match( PrefetchWrite mem ); 6179 ins_cost(MEMORY_REF_COST); 6180 6181 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6182 opcode(Assembler::prefetch_op3); 6183 ins_encode( form3_mem_prefetch_write( mem ) ); 6184 ins_pipe(iload_mem); 6185 %} 6186 6187 // Use BIS instruction to prefetch. 6188 instruct prefetchw_bis( memory mem ) %{ 6189 predicate(AllocatePrefetchStyle == 3); 6190 match( PrefetchWrite mem ); 6191 ins_cost(MEMORY_REF_COST); 6192 6193 format %{ "STXA G0,$mem\t! // Block initializing store" %} 6194 ins_encode %{ 6195 Register base = as_Register($mem$$base); 6196 int disp = $mem$$disp; 6197 if (disp != 0) { 6198 __ add(base, AllocatePrefetchStepSize, base); 6199 } 6200 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 6201 %} 6202 ins_pipe(istore_mem_reg); 6203 %} 6204 6205 //----------Store Instructions------------------------------------------------- 6206 // Store Byte 6207 instruct storeB(memory mem, iRegI src) %{ 6208 match(Set mem (StoreB mem src)); 6209 ins_cost(MEMORY_REF_COST); 6210 6211 size(4); 6212 format %{ "STB $src,$mem\t! byte" %} 6213 opcode(Assembler::stb_op3); 6214 ins_encode(simple_form3_mem_reg( mem, src ) ); 6215 ins_pipe(istore_mem_reg); 6216 %} 6217 6218 instruct storeB0(memory mem, immI0 src) %{ 6219 match(Set mem (StoreB mem src)); 6220 ins_cost(MEMORY_REF_COST); 6221 6222 size(4); 6223 format %{ "STB $src,$mem\t! byte" %} 6224 opcode(Assembler::stb_op3); 6225 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6226 ins_pipe(istore_mem_zero); 6227 %} 6228 6229 instruct storeCM0(memory mem, immI0 src) %{ 6230 match(Set mem (StoreCM mem src)); 6231 ins_cost(MEMORY_REF_COST); 6232 6233 size(4); 6234 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6235 opcode(Assembler::stb_op3); 6236 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6237 ins_pipe(istore_mem_zero); 6238 %} 6239 6240 // Store Char/Short 6241 instruct storeC(memory mem, iRegI src) %{ 6242 match(Set mem (StoreC mem src)); 6243 ins_cost(MEMORY_REF_COST); 6244 6245 size(4); 6246 format %{ "STH $src,$mem\t! short" %} 6247 opcode(Assembler::sth_op3); 6248 ins_encode(simple_form3_mem_reg( mem, src ) ); 6249 ins_pipe(istore_mem_reg); 6250 %} 6251 6252 instruct storeC0(memory mem, immI0 src) %{ 6253 match(Set mem (StoreC mem src)); 6254 ins_cost(MEMORY_REF_COST); 6255 6256 size(4); 6257 format %{ "STH $src,$mem\t! short" %} 6258 opcode(Assembler::sth_op3); 6259 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6260 ins_pipe(istore_mem_zero); 6261 %} 6262 6263 // Store Integer 6264 instruct storeI(memory mem, iRegI src) %{ 6265 match(Set mem (StoreI mem src)); 6266 ins_cost(MEMORY_REF_COST); 6267 6268 size(4); 6269 format %{ "STW $src,$mem" %} 6270 opcode(Assembler::stw_op3); 6271 ins_encode(simple_form3_mem_reg( mem, src ) ); 6272 ins_pipe(istore_mem_reg); 6273 %} 6274 6275 // Store Long 6276 instruct storeL(memory mem, iRegL src) %{ 6277 match(Set mem (StoreL mem src)); 6278 ins_cost(MEMORY_REF_COST); 6279 size(4); 6280 format %{ "STX $src,$mem\t! long" %} 6281 opcode(Assembler::stx_op3); 6282 ins_encode(simple_form3_mem_reg( mem, src ) ); 6283 ins_pipe(istore_mem_reg); 6284 %} 6285 6286 instruct storeI0(memory mem, immI0 src) %{ 6287 match(Set mem (StoreI mem src)); 6288 ins_cost(MEMORY_REF_COST); 6289 6290 size(4); 6291 format %{ "STW $src,$mem" %} 6292 opcode(Assembler::stw_op3); 6293 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6294 ins_pipe(istore_mem_zero); 6295 %} 6296 6297 instruct storeL0(memory mem, immL0 src) %{ 6298 match(Set mem (StoreL mem src)); 6299 ins_cost(MEMORY_REF_COST); 6300 6301 size(4); 6302 format %{ "STX $src,$mem" %} 6303 opcode(Assembler::stx_op3); 6304 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6305 ins_pipe(istore_mem_zero); 6306 %} 6307 6308 // Store Integer from float register (used after fstoi) 6309 instruct storeI_Freg(memory mem, regF src) %{ 6310 match(Set mem (StoreI mem src)); 6311 ins_cost(MEMORY_REF_COST); 6312 6313 size(4); 6314 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6315 opcode(Assembler::stf_op3); 6316 ins_encode(simple_form3_mem_reg( mem, src ) ); 6317 ins_pipe(fstoreF_mem_reg); 6318 %} 6319 6320 // Store Pointer 6321 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6322 match(Set dst (StoreP dst src)); 6323 ins_cost(MEMORY_REF_COST); 6324 size(4); 6325 6326 #ifndef _LP64 6327 format %{ "STW $src,$dst\t! ptr" %} 6328 opcode(Assembler::stw_op3, 0, REGP_OP); 6329 #else 6330 format %{ "STX $src,$dst\t! ptr" %} 6331 opcode(Assembler::stx_op3, 0, REGP_OP); 6332 #endif 6333 ins_encode( form3_mem_reg( dst, src ) ); 6334 ins_pipe(istore_mem_spORreg); 6335 %} 6336 6337 instruct storeP0(memory dst, immP0 src) %{ 6338 match(Set dst (StoreP dst src)); 6339 ins_cost(MEMORY_REF_COST); 6340 size(4); 6341 6342 #ifndef _LP64 6343 format %{ "STW $src,$dst\t! ptr" %} 6344 opcode(Assembler::stw_op3, 0, REGP_OP); 6345 #else 6346 format %{ "STX $src,$dst\t! ptr" %} 6347 opcode(Assembler::stx_op3, 0, REGP_OP); 6348 #endif 6349 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6350 ins_pipe(istore_mem_zero); 6351 %} 6352 6353 // Store Compressed Pointer 6354 instruct storeN(memory dst, iRegN src) %{ 6355 match(Set dst (StoreN dst src)); 6356 ins_cost(MEMORY_REF_COST); 6357 size(4); 6358 6359 format %{ "STW $src,$dst\t! compressed ptr" %} 6360 ins_encode %{ 6361 Register base = as_Register($dst$$base); 6362 Register index = as_Register($dst$$index); 6363 Register src = $src$$Register; 6364 if (index != G0) { 6365 __ stw(src, base, index); 6366 } else { 6367 __ stw(src, base, $dst$$disp); 6368 } 6369 %} 6370 ins_pipe(istore_mem_spORreg); 6371 %} 6372 6373 instruct storeN0(memory dst, immN0 src) %{ 6374 match(Set dst (StoreN dst src)); 6375 ins_cost(MEMORY_REF_COST); 6376 size(4); 6377 6378 format %{ "STW $src,$dst\t! compressed ptr" %} 6379 ins_encode %{ 6380 Register base = as_Register($dst$$base); 6381 Register index = as_Register($dst$$index); 6382 if (index != G0) { 6383 __ stw(0, base, index); 6384 } else { 6385 __ stw(0, base, $dst$$disp); 6386 } 6387 %} 6388 ins_pipe(istore_mem_zero); 6389 %} 6390 6391 // Store Double 6392 instruct storeD( memory mem, regD src) %{ 6393 match(Set mem (StoreD mem src)); 6394 ins_cost(MEMORY_REF_COST); 6395 6396 size(4); 6397 format %{ "STDF $src,$mem" %} 6398 opcode(Assembler::stdf_op3); 6399 ins_encode(simple_form3_mem_reg( mem, src ) ); 6400 ins_pipe(fstoreD_mem_reg); 6401 %} 6402 6403 instruct storeD0( memory mem, immD0 src) %{ 6404 match(Set mem (StoreD mem src)); 6405 ins_cost(MEMORY_REF_COST); 6406 6407 size(4); 6408 format %{ "STX $src,$mem" %} 6409 opcode(Assembler::stx_op3); 6410 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6411 ins_pipe(fstoreD_mem_zero); 6412 %} 6413 6414 // Store Float 6415 instruct storeF( memory mem, regF src) %{ 6416 match(Set mem (StoreF mem src)); 6417 ins_cost(MEMORY_REF_COST); 6418 6419 size(4); 6420 format %{ "STF $src,$mem" %} 6421 opcode(Assembler::stf_op3); 6422 ins_encode(simple_form3_mem_reg( mem, src ) ); 6423 ins_pipe(fstoreF_mem_reg); 6424 %} 6425 6426 instruct storeF0( memory mem, immF0 src) %{ 6427 match(Set mem (StoreF mem src)); 6428 ins_cost(MEMORY_REF_COST); 6429 6430 size(4); 6431 format %{ "STW $src,$mem\t! storeF0" %} 6432 opcode(Assembler::stw_op3); 6433 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6434 ins_pipe(fstoreF_mem_zero); 6435 %} 6436 6437 // Store Aligned Packed Bytes in Double register to memory 6438 instruct storeA8B(memory mem, regD src) %{ 6439 match(Set mem (Store8B mem src)); 6440 ins_cost(MEMORY_REF_COST); 6441 size(4); 6442 format %{ "STDF $src,$mem\t! packed8B" %} 6443 opcode(Assembler::stdf_op3); 6444 ins_encode(simple_form3_mem_reg( mem, src ) ); 6445 ins_pipe(fstoreD_mem_reg); 6446 %} 6447 6448 // Convert oop pointer into compressed form 6449 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6450 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6451 match(Set dst (EncodeP src)); 6452 format %{ "encode_heap_oop $src, $dst" %} 6453 ins_encode %{ 6454 __ encode_heap_oop($src$$Register, $dst$$Register); 6455 %} 6456 ins_pipe(ialu_reg); 6457 %} 6458 6459 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6460 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6461 match(Set dst (EncodeP src)); 6462 format %{ "encode_heap_oop_not_null $src, $dst" %} 6463 ins_encode %{ 6464 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6465 %} 6466 ins_pipe(ialu_reg); 6467 %} 6468 6469 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6470 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6471 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6472 match(Set dst (DecodeN src)); 6473 format %{ "decode_heap_oop $src, $dst" %} 6474 ins_encode %{ 6475 __ decode_heap_oop($src$$Register, $dst$$Register); 6476 %} 6477 ins_pipe(ialu_reg); 6478 %} 6479 6480 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6481 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6482 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6483 match(Set dst (DecodeN src)); 6484 format %{ "decode_heap_oop_not_null $src, $dst" %} 6485 ins_encode %{ 6486 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6487 %} 6488 ins_pipe(ialu_reg); 6489 %} 6490 6491 6492 // Store Zero into Aligned Packed Bytes 6493 instruct storeA8B0(memory mem, immI0 zero) %{ 6494 match(Set mem (Store8B mem zero)); 6495 ins_cost(MEMORY_REF_COST); 6496 size(4); 6497 format %{ "STX $zero,$mem\t! packed8B" %} 6498 opcode(Assembler::stx_op3); 6499 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6500 ins_pipe(fstoreD_mem_zero); 6501 %} 6502 6503 // Store Aligned Packed Chars/Shorts in Double register to memory 6504 instruct storeA4C(memory mem, regD src) %{ 6505 match(Set mem (Store4C mem src)); 6506 ins_cost(MEMORY_REF_COST); 6507 size(4); 6508 format %{ "STDF $src,$mem\t! packed4C" %} 6509 opcode(Assembler::stdf_op3); 6510 ins_encode(simple_form3_mem_reg( mem, src ) ); 6511 ins_pipe(fstoreD_mem_reg); 6512 %} 6513 6514 // Store Zero into Aligned Packed Chars/Shorts 6515 instruct storeA4C0(memory mem, immI0 zero) %{ 6516 match(Set mem (Store4C mem (Replicate4C zero))); 6517 ins_cost(MEMORY_REF_COST); 6518 size(4); 6519 format %{ "STX $zero,$mem\t! packed4C" %} 6520 opcode(Assembler::stx_op3); 6521 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6522 ins_pipe(fstoreD_mem_zero); 6523 %} 6524 6525 // Store Aligned Packed Ints in Double register to memory 6526 instruct storeA2I(memory mem, regD src) %{ 6527 match(Set mem (Store2I mem src)); 6528 ins_cost(MEMORY_REF_COST); 6529 size(4); 6530 format %{ "STDF $src,$mem\t! packed2I" %} 6531 opcode(Assembler::stdf_op3); 6532 ins_encode(simple_form3_mem_reg( mem, src ) ); 6533 ins_pipe(fstoreD_mem_reg); 6534 %} 6535 6536 // Store Zero into Aligned Packed Ints 6537 instruct storeA2I0(memory mem, immI0 zero) %{ 6538 match(Set mem (Store2I mem zero)); 6539 ins_cost(MEMORY_REF_COST); 6540 size(4); 6541 format %{ "STX $zero,$mem\t! packed2I" %} 6542 opcode(Assembler::stx_op3); 6543 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6544 ins_pipe(fstoreD_mem_zero); 6545 %} 6546 6547 6548 //----------MemBar Instructions----------------------------------------------- 6549 // Memory barrier flavors 6550 6551 instruct membar_acquire() %{ 6552 match(MemBarAcquire); 6553 ins_cost(4*MEMORY_REF_COST); 6554 6555 size(0); 6556 format %{ "MEMBAR-acquire" %} 6557 ins_encode( enc_membar_acquire ); 6558 ins_pipe(long_memory_op); 6559 %} 6560 6561 instruct membar_acquire_lock() %{ 6562 match(MemBarAcquire); 6563 predicate(Matcher::prior_fast_lock(n)); 6564 ins_cost(0); 6565 6566 size(0); 6567 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6568 ins_encode( ); 6569 ins_pipe(empty); 6570 %} 6571 6572 instruct membar_release() %{ 6573 match(MemBarRelease); 6574 ins_cost(4*MEMORY_REF_COST); 6575 6576 size(0); 6577 format %{ "MEMBAR-release" %} 6578 ins_encode( enc_membar_release ); 6579 ins_pipe(long_memory_op); 6580 %} 6581 6582 instruct membar_release_lock() %{ 6583 match(MemBarRelease); 6584 predicate(Matcher::post_fast_unlock(n)); 6585 ins_cost(0); 6586 6587 size(0); 6588 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6589 ins_encode( ); 6590 ins_pipe(empty); 6591 %} 6592 6593 instruct membar_volatile() %{ 6594 match(MemBarVolatile); 6595 ins_cost(4*MEMORY_REF_COST); 6596 6597 size(4); 6598 format %{ "MEMBAR-volatile" %} 6599 ins_encode( enc_membar_volatile ); 6600 ins_pipe(long_memory_op); 6601 %} 6602 6603 instruct unnecessary_membar_volatile() %{ 6604 match(MemBarVolatile); 6605 predicate(Matcher::post_store_load_barrier(n)); 6606 ins_cost(0); 6607 6608 size(0); 6609 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6610 ins_encode( ); 6611 ins_pipe(empty); 6612 %} 6613 6614 //----------Register Move Instructions----------------------------------------- 6615 instruct roundDouble_nop(regD dst) %{ 6616 match(Set dst (RoundDouble dst)); 6617 ins_cost(0); 6618 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6619 ins_encode( ); 6620 ins_pipe(empty); 6621 %} 6622 6623 6624 instruct roundFloat_nop(regF dst) %{ 6625 match(Set dst (RoundFloat dst)); 6626 ins_cost(0); 6627 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6628 ins_encode( ); 6629 ins_pipe(empty); 6630 %} 6631 6632 6633 // Cast Index to Pointer for unsafe natives 6634 instruct castX2P(iRegX src, iRegP dst) %{ 6635 match(Set dst (CastX2P src)); 6636 6637 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6638 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6639 ins_pipe(ialu_reg); 6640 %} 6641 6642 // Cast Pointer to Index for unsafe natives 6643 instruct castP2X(iRegP src, iRegX dst) %{ 6644 match(Set dst (CastP2X src)); 6645 6646 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6647 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6648 ins_pipe(ialu_reg); 6649 %} 6650 6651 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6652 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6653 match(Set stkSlot src); // chain rule 6654 ins_cost(MEMORY_REF_COST); 6655 format %{ "STDF $src,$stkSlot\t!stk" %} 6656 opcode(Assembler::stdf_op3); 6657 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6658 ins_pipe(fstoreD_stk_reg); 6659 %} 6660 6661 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6662 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6663 match(Set dst stkSlot); // chain rule 6664 ins_cost(MEMORY_REF_COST); 6665 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6666 opcode(Assembler::lddf_op3); 6667 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6668 ins_pipe(floadD_stk); 6669 %} 6670 6671 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6672 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6673 match(Set stkSlot src); // chain rule 6674 ins_cost(MEMORY_REF_COST); 6675 format %{ "STF $src,$stkSlot\t!stk" %} 6676 opcode(Assembler::stf_op3); 6677 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6678 ins_pipe(fstoreF_stk_reg); 6679 %} 6680 6681 //----------Conditional Move--------------------------------------------------- 6682 // Conditional move 6683 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6684 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6685 ins_cost(150); 6686 format %{ "MOV$cmp $pcc,$src,$dst" %} 6687 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6688 ins_pipe(ialu_reg); 6689 %} 6690 6691 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6692 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6693 ins_cost(140); 6694 format %{ "MOV$cmp $pcc,$src,$dst" %} 6695 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6696 ins_pipe(ialu_imm); 6697 %} 6698 6699 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6700 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6701 ins_cost(150); 6702 size(4); 6703 format %{ "MOV$cmp $icc,$src,$dst" %} 6704 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6705 ins_pipe(ialu_reg); 6706 %} 6707 6708 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6709 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6710 ins_cost(140); 6711 size(4); 6712 format %{ "MOV$cmp $icc,$src,$dst" %} 6713 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6714 ins_pipe(ialu_imm); 6715 %} 6716 6717 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6718 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6719 ins_cost(150); 6720 size(4); 6721 format %{ "MOV$cmp $icc,$src,$dst" %} 6722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6723 ins_pipe(ialu_reg); 6724 %} 6725 6726 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6727 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6728 ins_cost(140); 6729 size(4); 6730 format %{ "MOV$cmp $icc,$src,$dst" %} 6731 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6732 ins_pipe(ialu_imm); 6733 %} 6734 6735 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6736 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6737 ins_cost(150); 6738 size(4); 6739 format %{ "MOV$cmp $fcc,$src,$dst" %} 6740 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6741 ins_pipe(ialu_reg); 6742 %} 6743 6744 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6745 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6746 ins_cost(140); 6747 size(4); 6748 format %{ "MOV$cmp $fcc,$src,$dst" %} 6749 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6750 ins_pipe(ialu_imm); 6751 %} 6752 6753 // Conditional move for RegN. Only cmov(reg,reg). 6754 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6755 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6756 ins_cost(150); 6757 format %{ "MOV$cmp $pcc,$src,$dst" %} 6758 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6759 ins_pipe(ialu_reg); 6760 %} 6761 6762 // This instruction also works with CmpN so we don't need cmovNN_reg. 6763 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6764 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6765 ins_cost(150); 6766 size(4); 6767 format %{ "MOV$cmp $icc,$src,$dst" %} 6768 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6769 ins_pipe(ialu_reg); 6770 %} 6771 6772 // This instruction also works with CmpN so we don't need cmovNN_reg. 6773 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6774 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6775 ins_cost(150); 6776 size(4); 6777 format %{ "MOV$cmp $icc,$src,$dst" %} 6778 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6779 ins_pipe(ialu_reg); 6780 %} 6781 6782 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6783 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6784 ins_cost(150); 6785 size(4); 6786 format %{ "MOV$cmp $fcc,$src,$dst" %} 6787 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6788 ins_pipe(ialu_reg); 6789 %} 6790 6791 // Conditional move 6792 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6793 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6794 ins_cost(150); 6795 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6796 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6797 ins_pipe(ialu_reg); 6798 %} 6799 6800 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6801 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6802 ins_cost(140); 6803 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6804 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6805 ins_pipe(ialu_imm); 6806 %} 6807 6808 // This instruction also works with CmpN so we don't need cmovPN_reg. 6809 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6810 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6811 ins_cost(150); 6812 6813 size(4); 6814 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6815 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6816 ins_pipe(ialu_reg); 6817 %} 6818 6819 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6820 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6821 ins_cost(150); 6822 6823 size(4); 6824 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6825 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6826 ins_pipe(ialu_reg); 6827 %} 6828 6829 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6830 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6831 ins_cost(140); 6832 6833 size(4); 6834 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6835 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6836 ins_pipe(ialu_imm); 6837 %} 6838 6839 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6840 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6841 ins_cost(140); 6842 6843 size(4); 6844 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6845 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6846 ins_pipe(ialu_imm); 6847 %} 6848 6849 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6850 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6851 ins_cost(150); 6852 size(4); 6853 format %{ "MOV$cmp $fcc,$src,$dst" %} 6854 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6855 ins_pipe(ialu_imm); 6856 %} 6857 6858 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6859 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6860 ins_cost(140); 6861 size(4); 6862 format %{ "MOV$cmp $fcc,$src,$dst" %} 6863 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6864 ins_pipe(ialu_imm); 6865 %} 6866 6867 // Conditional move 6868 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6869 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6870 ins_cost(150); 6871 opcode(0x101); 6872 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6873 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6874 ins_pipe(int_conditional_float_move); 6875 %} 6876 6877 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6878 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6879 ins_cost(150); 6880 6881 size(4); 6882 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6883 opcode(0x101); 6884 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6885 ins_pipe(int_conditional_float_move); 6886 %} 6887 6888 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6889 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6890 ins_cost(150); 6891 6892 size(4); 6893 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6894 opcode(0x101); 6895 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6896 ins_pipe(int_conditional_float_move); 6897 %} 6898 6899 // Conditional move, 6900 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6901 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6902 ins_cost(150); 6903 size(4); 6904 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6905 opcode(0x1); 6906 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6907 ins_pipe(int_conditional_double_move); 6908 %} 6909 6910 // Conditional move 6911 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6912 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6913 ins_cost(150); 6914 size(4); 6915 opcode(0x102); 6916 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6917 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6918 ins_pipe(int_conditional_double_move); 6919 %} 6920 6921 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6922 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6923 ins_cost(150); 6924 6925 size(4); 6926 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6927 opcode(0x102); 6928 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6929 ins_pipe(int_conditional_double_move); 6930 %} 6931 6932 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6933 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6934 ins_cost(150); 6935 6936 size(4); 6937 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6938 opcode(0x102); 6939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6940 ins_pipe(int_conditional_double_move); 6941 %} 6942 6943 // Conditional move, 6944 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6945 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6946 ins_cost(150); 6947 size(4); 6948 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6949 opcode(0x2); 6950 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6951 ins_pipe(int_conditional_double_move); 6952 %} 6953 6954 // Conditional move 6955 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6956 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6957 ins_cost(150); 6958 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6959 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6960 ins_pipe(ialu_reg); 6961 %} 6962 6963 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6964 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6965 ins_cost(140); 6966 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6967 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6968 ins_pipe(ialu_imm); 6969 %} 6970 6971 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6972 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6973 ins_cost(150); 6974 6975 size(4); 6976 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6977 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6978 ins_pipe(ialu_reg); 6979 %} 6980 6981 6982 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6983 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6984 ins_cost(150); 6985 6986 size(4); 6987 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6988 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6989 ins_pipe(ialu_reg); 6990 %} 6991 6992 6993 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6994 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6995 ins_cost(150); 6996 6997 size(4); 6998 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6999 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7000 ins_pipe(ialu_reg); 7001 %} 7002 7003 7004 7005 //----------OS and Locking Instructions---------------------------------------- 7006 7007 // This name is KNOWN by the ADLC and cannot be changed. 7008 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 7009 // for this guy. 7010 instruct tlsLoadP(g2RegP dst) %{ 7011 match(Set dst (ThreadLocal)); 7012 7013 size(0); 7014 ins_cost(0); 7015 format %{ "# TLS is in G2" %} 7016 ins_encode( /*empty encoding*/ ); 7017 ins_pipe(ialu_none); 7018 %} 7019 7020 instruct checkCastPP( iRegP dst ) %{ 7021 match(Set dst (CheckCastPP dst)); 7022 7023 size(0); 7024 format %{ "# checkcastPP of $dst" %} 7025 ins_encode( /*empty encoding*/ ); 7026 ins_pipe(empty); 7027 %} 7028 7029 7030 instruct castPP( iRegP dst ) %{ 7031 match(Set dst (CastPP dst)); 7032 format %{ "# castPP of $dst" %} 7033 ins_encode( /*empty encoding*/ ); 7034 ins_pipe(empty); 7035 %} 7036 7037 instruct castII( iRegI dst ) %{ 7038 match(Set dst (CastII dst)); 7039 format %{ "# castII of $dst" %} 7040 ins_encode( /*empty encoding*/ ); 7041 ins_cost(0); 7042 ins_pipe(empty); 7043 %} 7044 7045 //----------Arithmetic Instructions-------------------------------------------- 7046 // Addition Instructions 7047 // Register Addition 7048 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7049 match(Set dst (AddI src1 src2)); 7050 7051 size(4); 7052 format %{ "ADD $src1,$src2,$dst" %} 7053 ins_encode %{ 7054 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7055 %} 7056 ins_pipe(ialu_reg_reg); 7057 %} 7058 7059 // Immediate Addition 7060 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7061 match(Set dst (AddI src1 src2)); 7062 7063 size(4); 7064 format %{ "ADD $src1,$src2,$dst" %} 7065 opcode(Assembler::add_op3, Assembler::arith_op); 7066 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7067 ins_pipe(ialu_reg_imm); 7068 %} 7069 7070 // Pointer Register Addition 7071 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7072 match(Set dst (AddP src1 src2)); 7073 7074 size(4); 7075 format %{ "ADD $src1,$src2,$dst" %} 7076 opcode(Assembler::add_op3, Assembler::arith_op); 7077 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7078 ins_pipe(ialu_reg_reg); 7079 %} 7080 7081 // Pointer Immediate Addition 7082 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7083 match(Set dst (AddP src1 src2)); 7084 7085 size(4); 7086 format %{ "ADD $src1,$src2,$dst" %} 7087 opcode(Assembler::add_op3, Assembler::arith_op); 7088 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7089 ins_pipe(ialu_reg_imm); 7090 %} 7091 7092 // Long Addition 7093 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7094 match(Set dst (AddL src1 src2)); 7095 7096 size(4); 7097 format %{ "ADD $src1,$src2,$dst\t! long" %} 7098 opcode(Assembler::add_op3, Assembler::arith_op); 7099 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7100 ins_pipe(ialu_reg_reg); 7101 %} 7102 7103 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7104 match(Set dst (AddL src1 con)); 7105 7106 size(4); 7107 format %{ "ADD $src1,$con,$dst" %} 7108 opcode(Assembler::add_op3, Assembler::arith_op); 7109 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7110 ins_pipe(ialu_reg_imm); 7111 %} 7112 7113 //----------Conditional_store-------------------------------------------------- 7114 // Conditional-store of the updated heap-top. 7115 // Used during allocation of the shared heap. 7116 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7117 7118 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7119 instruct loadPLocked(iRegP dst, memory mem) %{ 7120 match(Set dst (LoadPLocked mem)); 7121 ins_cost(MEMORY_REF_COST); 7122 7123 #ifndef _LP64 7124 size(4); 7125 format %{ "LDUW $mem,$dst\t! ptr" %} 7126 opcode(Assembler::lduw_op3, 0, REGP_OP); 7127 #else 7128 format %{ "LDX $mem,$dst\t! ptr" %} 7129 opcode(Assembler::ldx_op3, 0, REGP_OP); 7130 #endif 7131 ins_encode( form3_mem_reg( mem, dst ) ); 7132 ins_pipe(iload_mem); 7133 %} 7134 7135 // LoadL-locked. Same as a regular long load when used with a compare-swap 7136 instruct loadLLocked(iRegL dst, memory mem) %{ 7137 match(Set dst (LoadLLocked mem)); 7138 ins_cost(MEMORY_REF_COST); 7139 size(4); 7140 format %{ "LDX $mem,$dst\t! long" %} 7141 opcode(Assembler::ldx_op3); 7142 ins_encode(simple_form3_mem_reg( mem, dst ) ); 7143 ins_pipe(iload_mem); 7144 %} 7145 7146 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7147 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7148 effect( KILL newval ); 7149 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7150 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7151 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7152 ins_pipe( long_memory_op ); 7153 %} 7154 7155 // Conditional-store of an int value. 7156 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7157 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7158 effect( KILL newval ); 7159 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7160 "CMP $oldval,$newval\t\t! See if we made progress" %} 7161 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7162 ins_pipe( long_memory_op ); 7163 %} 7164 7165 // Conditional-store of a long value. 7166 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7167 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7168 effect( KILL newval ); 7169 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7170 "CMP $oldval,$newval\t\t! See if we made progress" %} 7171 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7172 ins_pipe( long_memory_op ); 7173 %} 7174 7175 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7176 7177 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7178 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7179 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7180 format %{ 7181 "MOV $newval,O7\n\t" 7182 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7183 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7184 "MOV 1,$res\n\t" 7185 "MOVne xcc,R_G0,$res" 7186 %} 7187 ins_encode( enc_casx(mem_ptr, oldval, newval), 7188 enc_lflags_ne_to_boolean(res) ); 7189 ins_pipe( long_memory_op ); 7190 %} 7191 7192 7193 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7194 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7195 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7196 format %{ 7197 "MOV $newval,O7\n\t" 7198 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7199 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7200 "MOV 1,$res\n\t" 7201 "MOVne icc,R_G0,$res" 7202 %} 7203 ins_encode( enc_casi(mem_ptr, oldval, newval), 7204 enc_iflags_ne_to_boolean(res) ); 7205 ins_pipe( long_memory_op ); 7206 %} 7207 7208 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7209 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7210 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7211 format %{ 7212 "MOV $newval,O7\n\t" 7213 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7214 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7215 "MOV 1,$res\n\t" 7216 "MOVne xcc,R_G0,$res" 7217 %} 7218 #ifdef _LP64 7219 ins_encode( enc_casx(mem_ptr, oldval, newval), 7220 enc_lflags_ne_to_boolean(res) ); 7221 #else 7222 ins_encode( enc_casi(mem_ptr, oldval, newval), 7223 enc_iflags_ne_to_boolean(res) ); 7224 #endif 7225 ins_pipe( long_memory_op ); 7226 %} 7227 7228 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7229 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7230 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7231 format %{ 7232 "MOV $newval,O7\n\t" 7233 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7234 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7235 "MOV 1,$res\n\t" 7236 "MOVne icc,R_G0,$res" 7237 %} 7238 ins_encode( enc_casi(mem_ptr, oldval, newval), 7239 enc_iflags_ne_to_boolean(res) ); 7240 ins_pipe( long_memory_op ); 7241 %} 7242 7243 //--------------------- 7244 // Subtraction Instructions 7245 // Register Subtraction 7246 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7247 match(Set dst (SubI src1 src2)); 7248 7249 size(4); 7250 format %{ "SUB $src1,$src2,$dst" %} 7251 opcode(Assembler::sub_op3, Assembler::arith_op); 7252 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7253 ins_pipe(ialu_reg_reg); 7254 %} 7255 7256 // Immediate Subtraction 7257 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7258 match(Set dst (SubI src1 src2)); 7259 7260 size(4); 7261 format %{ "SUB $src1,$src2,$dst" %} 7262 opcode(Assembler::sub_op3, Assembler::arith_op); 7263 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7264 ins_pipe(ialu_reg_imm); 7265 %} 7266 7267 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7268 match(Set dst (SubI zero src2)); 7269 7270 size(4); 7271 format %{ "NEG $src2,$dst" %} 7272 opcode(Assembler::sub_op3, Assembler::arith_op); 7273 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7274 ins_pipe(ialu_zero_reg); 7275 %} 7276 7277 // Long subtraction 7278 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7279 match(Set dst (SubL src1 src2)); 7280 7281 size(4); 7282 format %{ "SUB $src1,$src2,$dst\t! long" %} 7283 opcode(Assembler::sub_op3, Assembler::arith_op); 7284 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7285 ins_pipe(ialu_reg_reg); 7286 %} 7287 7288 // Immediate Subtraction 7289 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7290 match(Set dst (SubL src1 con)); 7291 7292 size(4); 7293 format %{ "SUB $src1,$con,$dst\t! long" %} 7294 opcode(Assembler::sub_op3, Assembler::arith_op); 7295 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7296 ins_pipe(ialu_reg_imm); 7297 %} 7298 7299 // Long negation 7300 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7301 match(Set dst (SubL zero src2)); 7302 7303 size(4); 7304 format %{ "NEG $src2,$dst\t! long" %} 7305 opcode(Assembler::sub_op3, Assembler::arith_op); 7306 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7307 ins_pipe(ialu_zero_reg); 7308 %} 7309 7310 // Multiplication Instructions 7311 // Integer Multiplication 7312 // Register Multiplication 7313 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7314 match(Set dst (MulI src1 src2)); 7315 7316 size(4); 7317 format %{ "MULX $src1,$src2,$dst" %} 7318 opcode(Assembler::mulx_op3, Assembler::arith_op); 7319 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7320 ins_pipe(imul_reg_reg); 7321 %} 7322 7323 // Immediate Multiplication 7324 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7325 match(Set dst (MulI src1 src2)); 7326 7327 size(4); 7328 format %{ "MULX $src1,$src2,$dst" %} 7329 opcode(Assembler::mulx_op3, Assembler::arith_op); 7330 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7331 ins_pipe(imul_reg_imm); 7332 %} 7333 7334 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7335 match(Set dst (MulL src1 src2)); 7336 ins_cost(DEFAULT_COST * 5); 7337 size(4); 7338 format %{ "MULX $src1,$src2,$dst\t! long" %} 7339 opcode(Assembler::mulx_op3, Assembler::arith_op); 7340 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7341 ins_pipe(mulL_reg_reg); 7342 %} 7343 7344 // Immediate Multiplication 7345 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7346 match(Set dst (MulL src1 src2)); 7347 ins_cost(DEFAULT_COST * 5); 7348 size(4); 7349 format %{ "MULX $src1,$src2,$dst" %} 7350 opcode(Assembler::mulx_op3, Assembler::arith_op); 7351 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7352 ins_pipe(mulL_reg_imm); 7353 %} 7354 7355 // Integer Division 7356 // Register Division 7357 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7358 match(Set dst (DivI src1 src2)); 7359 ins_cost((2+71)*DEFAULT_COST); 7360 7361 format %{ "SRA $src2,0,$src2\n\t" 7362 "SRA $src1,0,$src1\n\t" 7363 "SDIVX $src1,$src2,$dst" %} 7364 ins_encode( idiv_reg( src1, src2, dst ) ); 7365 ins_pipe(sdiv_reg_reg); 7366 %} 7367 7368 // Immediate Division 7369 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7370 match(Set dst (DivI src1 src2)); 7371 ins_cost((2+71)*DEFAULT_COST); 7372 7373 format %{ "SRA $src1,0,$src1\n\t" 7374 "SDIVX $src1,$src2,$dst" %} 7375 ins_encode( idiv_imm( src1, src2, dst ) ); 7376 ins_pipe(sdiv_reg_imm); 7377 %} 7378 7379 //----------Div-By-10-Expansion------------------------------------------------ 7380 // Extract hi bits of a 32x32->64 bit multiply. 7381 // Expand rule only, not matched 7382 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7383 effect( DEF dst, USE src1, USE src2 ); 7384 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7385 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7386 ins_encode( enc_mul_hi(dst,src1,src2)); 7387 ins_pipe(sdiv_reg_reg); 7388 %} 7389 7390 // Magic constant, reciprocal of 10 7391 instruct loadConI_x66666667(iRegIsafe dst) %{ 7392 effect( DEF dst ); 7393 7394 size(8); 7395 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7396 ins_encode( Set32(0x66666667, dst) ); 7397 ins_pipe(ialu_hi_lo_reg); 7398 %} 7399 7400 // Register Shift Right Arithmetic Long by 32-63 7401 instruct sra_31( iRegI dst, iRegI src ) %{ 7402 effect( DEF dst, USE src ); 7403 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7404 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7405 ins_pipe(ialu_reg_reg); 7406 %} 7407 7408 // Arithmetic Shift Right by 8-bit immediate 7409 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7410 effect( DEF dst, USE src ); 7411 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7412 opcode(Assembler::sra_op3, Assembler::arith_op); 7413 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7414 ins_pipe(ialu_reg_imm); 7415 %} 7416 7417 // Integer DIV with 10 7418 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7419 match(Set dst (DivI src div)); 7420 ins_cost((6+6)*DEFAULT_COST); 7421 expand %{ 7422 iRegIsafe tmp1; // Killed temps; 7423 iRegIsafe tmp2; // Killed temps; 7424 iRegI tmp3; // Killed temps; 7425 iRegI tmp4; // Killed temps; 7426 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7427 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7428 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7429 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7430 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7431 %} 7432 %} 7433 7434 // Register Long Division 7435 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7436 match(Set dst (DivL src1 src2)); 7437 ins_cost(DEFAULT_COST*71); 7438 size(4); 7439 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7440 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7441 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7442 ins_pipe(divL_reg_reg); 7443 %} 7444 7445 // Register Long Division 7446 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7447 match(Set dst (DivL src1 src2)); 7448 ins_cost(DEFAULT_COST*71); 7449 size(4); 7450 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7451 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7452 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7453 ins_pipe(divL_reg_imm); 7454 %} 7455 7456 // Integer Remainder 7457 // Register Remainder 7458 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7459 match(Set dst (ModI src1 src2)); 7460 effect( KILL ccr, KILL temp); 7461 7462 format %{ "SREM $src1,$src2,$dst" %} 7463 ins_encode( irem_reg(src1, src2, dst, temp) ); 7464 ins_pipe(sdiv_reg_reg); 7465 %} 7466 7467 // Immediate Remainder 7468 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7469 match(Set dst (ModI src1 src2)); 7470 effect( KILL ccr, KILL temp); 7471 7472 format %{ "SREM $src1,$src2,$dst" %} 7473 ins_encode( irem_imm(src1, src2, dst, temp) ); 7474 ins_pipe(sdiv_reg_imm); 7475 %} 7476 7477 // Register Long Remainder 7478 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7479 effect(DEF dst, USE src1, USE src2); 7480 size(4); 7481 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7482 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7483 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7484 ins_pipe(divL_reg_reg); 7485 %} 7486 7487 // Register Long Division 7488 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7489 effect(DEF dst, USE src1, USE src2); 7490 size(4); 7491 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7492 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7493 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7494 ins_pipe(divL_reg_imm); 7495 %} 7496 7497 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7498 effect(DEF dst, USE src1, USE src2); 7499 size(4); 7500 format %{ "MULX $src1,$src2,$dst\t! long" %} 7501 opcode(Assembler::mulx_op3, Assembler::arith_op); 7502 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7503 ins_pipe(mulL_reg_reg); 7504 %} 7505 7506 // Immediate Multiplication 7507 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7508 effect(DEF dst, USE src1, USE src2); 7509 size(4); 7510 format %{ "MULX $src1,$src2,$dst" %} 7511 opcode(Assembler::mulx_op3, Assembler::arith_op); 7512 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7513 ins_pipe(mulL_reg_imm); 7514 %} 7515 7516 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7517 effect(DEF dst, USE src1, USE src2); 7518 size(4); 7519 format %{ "SUB $src1,$src2,$dst\t! long" %} 7520 opcode(Assembler::sub_op3, Assembler::arith_op); 7521 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7522 ins_pipe(ialu_reg_reg); 7523 %} 7524 7525 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7526 effect(DEF dst, USE src1, USE src2); 7527 size(4); 7528 format %{ "SUB $src1,$src2,$dst\t! long" %} 7529 opcode(Assembler::sub_op3, Assembler::arith_op); 7530 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7531 ins_pipe(ialu_reg_reg); 7532 %} 7533 7534 // Register Long Remainder 7535 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7536 match(Set dst (ModL src1 src2)); 7537 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7538 expand %{ 7539 iRegL tmp1; 7540 iRegL tmp2; 7541 divL_reg_reg_1(tmp1, src1, src2); 7542 mulL_reg_reg_1(tmp2, tmp1, src2); 7543 subL_reg_reg_1(dst, src1, tmp2); 7544 %} 7545 %} 7546 7547 // Register Long Remainder 7548 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7549 match(Set dst (ModL src1 src2)); 7550 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7551 expand %{ 7552 iRegL tmp1; 7553 iRegL tmp2; 7554 divL_reg_imm13_1(tmp1, src1, src2); 7555 mulL_reg_imm13_1(tmp2, tmp1, src2); 7556 subL_reg_reg_2 (dst, src1, tmp2); 7557 %} 7558 %} 7559 7560 // Integer Shift Instructions 7561 // Register Shift Left 7562 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7563 match(Set dst (LShiftI src1 src2)); 7564 7565 size(4); 7566 format %{ "SLL $src1,$src2,$dst" %} 7567 opcode(Assembler::sll_op3, Assembler::arith_op); 7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7569 ins_pipe(ialu_reg_reg); 7570 %} 7571 7572 // Register Shift Left Immediate 7573 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7574 match(Set dst (LShiftI src1 src2)); 7575 7576 size(4); 7577 format %{ "SLL $src1,$src2,$dst" %} 7578 opcode(Assembler::sll_op3, Assembler::arith_op); 7579 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7580 ins_pipe(ialu_reg_imm); 7581 %} 7582 7583 // Register Shift Left 7584 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7585 match(Set dst (LShiftL src1 src2)); 7586 7587 size(4); 7588 format %{ "SLLX $src1,$src2,$dst" %} 7589 opcode(Assembler::sllx_op3, Assembler::arith_op); 7590 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7591 ins_pipe(ialu_reg_reg); 7592 %} 7593 7594 // Register Shift Left Immediate 7595 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7596 match(Set dst (LShiftL src1 src2)); 7597 7598 size(4); 7599 format %{ "SLLX $src1,$src2,$dst" %} 7600 opcode(Assembler::sllx_op3, Assembler::arith_op); 7601 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7602 ins_pipe(ialu_reg_imm); 7603 %} 7604 7605 // Register Arithmetic Shift Right 7606 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7607 match(Set dst (RShiftI src1 src2)); 7608 size(4); 7609 format %{ "SRA $src1,$src2,$dst" %} 7610 opcode(Assembler::sra_op3, Assembler::arith_op); 7611 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7612 ins_pipe(ialu_reg_reg); 7613 %} 7614 7615 // Register Arithmetic Shift Right Immediate 7616 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7617 match(Set dst (RShiftI src1 src2)); 7618 7619 size(4); 7620 format %{ "SRA $src1,$src2,$dst" %} 7621 opcode(Assembler::sra_op3, Assembler::arith_op); 7622 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7623 ins_pipe(ialu_reg_imm); 7624 %} 7625 7626 // Register Shift Right Arithmatic Long 7627 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7628 match(Set dst (RShiftL src1 src2)); 7629 7630 size(4); 7631 format %{ "SRAX $src1,$src2,$dst" %} 7632 opcode(Assembler::srax_op3, Assembler::arith_op); 7633 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7634 ins_pipe(ialu_reg_reg); 7635 %} 7636 7637 // Register Shift Left Immediate 7638 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7639 match(Set dst (RShiftL src1 src2)); 7640 7641 size(4); 7642 format %{ "SRAX $src1,$src2,$dst" %} 7643 opcode(Assembler::srax_op3, Assembler::arith_op); 7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7645 ins_pipe(ialu_reg_imm); 7646 %} 7647 7648 // Register Shift Right 7649 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7650 match(Set dst (URShiftI src1 src2)); 7651 7652 size(4); 7653 format %{ "SRL $src1,$src2,$dst" %} 7654 opcode(Assembler::srl_op3, Assembler::arith_op); 7655 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7656 ins_pipe(ialu_reg_reg); 7657 %} 7658 7659 // Register Shift Right Immediate 7660 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7661 match(Set dst (URShiftI src1 src2)); 7662 7663 size(4); 7664 format %{ "SRL $src1,$src2,$dst" %} 7665 opcode(Assembler::srl_op3, Assembler::arith_op); 7666 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7667 ins_pipe(ialu_reg_imm); 7668 %} 7669 7670 // Register Shift Right 7671 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7672 match(Set dst (URShiftL src1 src2)); 7673 7674 size(4); 7675 format %{ "SRLX $src1,$src2,$dst" %} 7676 opcode(Assembler::srlx_op3, Assembler::arith_op); 7677 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7678 ins_pipe(ialu_reg_reg); 7679 %} 7680 7681 // Register Shift Right Immediate 7682 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7683 match(Set dst (URShiftL src1 src2)); 7684 7685 size(4); 7686 format %{ "SRLX $src1,$src2,$dst" %} 7687 opcode(Assembler::srlx_op3, Assembler::arith_op); 7688 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7689 ins_pipe(ialu_reg_imm); 7690 %} 7691 7692 // Register Shift Right Immediate with a CastP2X 7693 #ifdef _LP64 7694 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7695 match(Set dst (URShiftL (CastP2X src1) src2)); 7696 size(4); 7697 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7698 opcode(Assembler::srlx_op3, Assembler::arith_op); 7699 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7700 ins_pipe(ialu_reg_imm); 7701 %} 7702 #else 7703 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7704 match(Set dst (URShiftI (CastP2X src1) src2)); 7705 size(4); 7706 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7707 opcode(Assembler::srl_op3, Assembler::arith_op); 7708 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7709 ins_pipe(ialu_reg_imm); 7710 %} 7711 #endif 7712 7713 7714 //----------Floating Point Arithmetic Instructions----------------------------- 7715 7716 // Add float single precision 7717 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7718 match(Set dst (AddF src1 src2)); 7719 7720 size(4); 7721 format %{ "FADDS $src1,$src2,$dst" %} 7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7723 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7724 ins_pipe(faddF_reg_reg); 7725 %} 7726 7727 // Add float double precision 7728 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7729 match(Set dst (AddD src1 src2)); 7730 7731 size(4); 7732 format %{ "FADDD $src1,$src2,$dst" %} 7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7734 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7735 ins_pipe(faddD_reg_reg); 7736 %} 7737 7738 // Sub float single precision 7739 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7740 match(Set dst (SubF src1 src2)); 7741 7742 size(4); 7743 format %{ "FSUBS $src1,$src2,$dst" %} 7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7745 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7746 ins_pipe(faddF_reg_reg); 7747 %} 7748 7749 // Sub float double precision 7750 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7751 match(Set dst (SubD src1 src2)); 7752 7753 size(4); 7754 format %{ "FSUBD $src1,$src2,$dst" %} 7755 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7756 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7757 ins_pipe(faddD_reg_reg); 7758 %} 7759 7760 // Mul float single precision 7761 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7762 match(Set dst (MulF src1 src2)); 7763 7764 size(4); 7765 format %{ "FMULS $src1,$src2,$dst" %} 7766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7767 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7768 ins_pipe(fmulF_reg_reg); 7769 %} 7770 7771 // Mul float double precision 7772 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7773 match(Set dst (MulD src1 src2)); 7774 7775 size(4); 7776 format %{ "FMULD $src1,$src2,$dst" %} 7777 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7778 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7779 ins_pipe(fmulD_reg_reg); 7780 %} 7781 7782 // Div float single precision 7783 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7784 match(Set dst (DivF src1 src2)); 7785 7786 size(4); 7787 format %{ "FDIVS $src1,$src2,$dst" %} 7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7789 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7790 ins_pipe(fdivF_reg_reg); 7791 %} 7792 7793 // Div float double precision 7794 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7795 match(Set dst (DivD src1 src2)); 7796 7797 size(4); 7798 format %{ "FDIVD $src1,$src2,$dst" %} 7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7800 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7801 ins_pipe(fdivD_reg_reg); 7802 %} 7803 7804 // Absolute float double precision 7805 instruct absD_reg(regD dst, regD src) %{ 7806 match(Set dst (AbsD src)); 7807 7808 format %{ "FABSd $src,$dst" %} 7809 ins_encode(fabsd(dst, src)); 7810 ins_pipe(faddD_reg); 7811 %} 7812 7813 // Absolute float single precision 7814 instruct absF_reg(regF dst, regF src) %{ 7815 match(Set dst (AbsF src)); 7816 7817 format %{ "FABSs $src,$dst" %} 7818 ins_encode(fabss(dst, src)); 7819 ins_pipe(faddF_reg); 7820 %} 7821 7822 instruct negF_reg(regF dst, regF src) %{ 7823 match(Set dst (NegF src)); 7824 7825 size(4); 7826 format %{ "FNEGs $src,$dst" %} 7827 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7828 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7829 ins_pipe(faddF_reg); 7830 %} 7831 7832 instruct negD_reg(regD dst, regD src) %{ 7833 match(Set dst (NegD src)); 7834 7835 format %{ "FNEGd $src,$dst" %} 7836 ins_encode(fnegd(dst, src)); 7837 ins_pipe(faddD_reg); 7838 %} 7839 7840 // Sqrt float double precision 7841 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7842 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7843 7844 size(4); 7845 format %{ "FSQRTS $src,$dst" %} 7846 ins_encode(fsqrts(dst, src)); 7847 ins_pipe(fdivF_reg_reg); 7848 %} 7849 7850 // Sqrt float double precision 7851 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7852 match(Set dst (SqrtD src)); 7853 7854 size(4); 7855 format %{ "FSQRTD $src,$dst" %} 7856 ins_encode(fsqrtd(dst, src)); 7857 ins_pipe(fdivD_reg_reg); 7858 %} 7859 7860 //----------Logical Instructions----------------------------------------------- 7861 // And Instructions 7862 // Register And 7863 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7864 match(Set dst (AndI src1 src2)); 7865 7866 size(4); 7867 format %{ "AND $src1,$src2,$dst" %} 7868 opcode(Assembler::and_op3, Assembler::arith_op); 7869 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7870 ins_pipe(ialu_reg_reg); 7871 %} 7872 7873 // Immediate And 7874 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7875 match(Set dst (AndI src1 src2)); 7876 7877 size(4); 7878 format %{ "AND $src1,$src2,$dst" %} 7879 opcode(Assembler::and_op3, Assembler::arith_op); 7880 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7881 ins_pipe(ialu_reg_imm); 7882 %} 7883 7884 // Register And Long 7885 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7886 match(Set dst (AndL src1 src2)); 7887 7888 ins_cost(DEFAULT_COST); 7889 size(4); 7890 format %{ "AND $src1,$src2,$dst\t! long" %} 7891 opcode(Assembler::and_op3, Assembler::arith_op); 7892 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7893 ins_pipe(ialu_reg_reg); 7894 %} 7895 7896 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7897 match(Set dst (AndL src1 con)); 7898 7899 ins_cost(DEFAULT_COST); 7900 size(4); 7901 format %{ "AND $src1,$con,$dst\t! long" %} 7902 opcode(Assembler::and_op3, Assembler::arith_op); 7903 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7904 ins_pipe(ialu_reg_imm); 7905 %} 7906 7907 // Or Instructions 7908 // Register Or 7909 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7910 match(Set dst (OrI src1 src2)); 7911 7912 size(4); 7913 format %{ "OR $src1,$src2,$dst" %} 7914 opcode(Assembler::or_op3, Assembler::arith_op); 7915 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7916 ins_pipe(ialu_reg_reg); 7917 %} 7918 7919 // Immediate Or 7920 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7921 match(Set dst (OrI src1 src2)); 7922 7923 size(4); 7924 format %{ "OR $src1,$src2,$dst" %} 7925 opcode(Assembler::or_op3, Assembler::arith_op); 7926 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7927 ins_pipe(ialu_reg_imm); 7928 %} 7929 7930 // Register Or Long 7931 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7932 match(Set dst (OrL src1 src2)); 7933 7934 ins_cost(DEFAULT_COST); 7935 size(4); 7936 format %{ "OR $src1,$src2,$dst\t! long" %} 7937 opcode(Assembler::or_op3, Assembler::arith_op); 7938 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7939 ins_pipe(ialu_reg_reg); 7940 %} 7941 7942 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7943 match(Set dst (OrL src1 con)); 7944 ins_cost(DEFAULT_COST*2); 7945 7946 ins_cost(DEFAULT_COST); 7947 size(4); 7948 format %{ "OR $src1,$con,$dst\t! long" %} 7949 opcode(Assembler::or_op3, Assembler::arith_op); 7950 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7951 ins_pipe(ialu_reg_imm); 7952 %} 7953 7954 #ifndef _LP64 7955 7956 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 7957 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 7958 match(Set dst (OrI src1 (CastP2X src2))); 7959 7960 size(4); 7961 format %{ "OR $src1,$src2,$dst" %} 7962 opcode(Assembler::or_op3, Assembler::arith_op); 7963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7964 ins_pipe(ialu_reg_reg); 7965 %} 7966 7967 #else 7968 7969 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7970 match(Set dst (OrL src1 (CastP2X src2))); 7971 7972 ins_cost(DEFAULT_COST); 7973 size(4); 7974 format %{ "OR $src1,$src2,$dst\t! long" %} 7975 opcode(Assembler::or_op3, Assembler::arith_op); 7976 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7977 ins_pipe(ialu_reg_reg); 7978 %} 7979 7980 #endif 7981 7982 // Xor Instructions 7983 // Register Xor 7984 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7985 match(Set dst (XorI src1 src2)); 7986 7987 size(4); 7988 format %{ "XOR $src1,$src2,$dst" %} 7989 opcode(Assembler::xor_op3, Assembler::arith_op); 7990 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7991 ins_pipe(ialu_reg_reg); 7992 %} 7993 7994 // Immediate Xor 7995 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7996 match(Set dst (XorI src1 src2)); 7997 7998 size(4); 7999 format %{ "XOR $src1,$src2,$dst" %} 8000 opcode(Assembler::xor_op3, Assembler::arith_op); 8001 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8002 ins_pipe(ialu_reg_imm); 8003 %} 8004 8005 // Register Xor Long 8006 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8007 match(Set dst (XorL src1 src2)); 8008 8009 ins_cost(DEFAULT_COST); 8010 size(4); 8011 format %{ "XOR $src1,$src2,$dst\t! long" %} 8012 opcode(Assembler::xor_op3, Assembler::arith_op); 8013 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8014 ins_pipe(ialu_reg_reg); 8015 %} 8016 8017 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8018 match(Set dst (XorL src1 con)); 8019 8020 ins_cost(DEFAULT_COST); 8021 size(4); 8022 format %{ "XOR $src1,$con,$dst\t! long" %} 8023 opcode(Assembler::xor_op3, Assembler::arith_op); 8024 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8025 ins_pipe(ialu_reg_imm); 8026 %} 8027 8028 //----------Convert to Boolean------------------------------------------------- 8029 // Nice hack for 32-bit tests but doesn't work for 8030 // 64-bit pointers. 8031 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8032 match(Set dst (Conv2B src)); 8033 effect( KILL ccr ); 8034 ins_cost(DEFAULT_COST*2); 8035 format %{ "CMP R_G0,$src\n\t" 8036 "ADDX R_G0,0,$dst" %} 8037 ins_encode( enc_to_bool( src, dst ) ); 8038 ins_pipe(ialu_reg_ialu); 8039 %} 8040 8041 #ifndef _LP64 8042 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8043 match(Set dst (Conv2B src)); 8044 effect( KILL ccr ); 8045 ins_cost(DEFAULT_COST*2); 8046 format %{ "CMP R_G0,$src\n\t" 8047 "ADDX R_G0,0,$dst" %} 8048 ins_encode( enc_to_bool( src, dst ) ); 8049 ins_pipe(ialu_reg_ialu); 8050 %} 8051 #else 8052 instruct convP2B( iRegI dst, iRegP src ) %{ 8053 match(Set dst (Conv2B src)); 8054 ins_cost(DEFAULT_COST*2); 8055 format %{ "MOV $src,$dst\n\t" 8056 "MOVRNZ $src,1,$dst" %} 8057 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8058 ins_pipe(ialu_clr_and_mover); 8059 %} 8060 #endif 8061 8062 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8063 match(Set dst (CmpLTMask p q)); 8064 effect( KILL ccr ); 8065 ins_cost(DEFAULT_COST*4); 8066 format %{ "CMP $p,$q\n\t" 8067 "MOV #0,$dst\n\t" 8068 "BLT,a .+8\n\t" 8069 "MOV #-1,$dst" %} 8070 ins_encode( enc_ltmask(p,q,dst) ); 8071 ins_pipe(ialu_reg_reg_ialu); 8072 %} 8073 8074 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8075 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8076 effect(KILL ccr, TEMP tmp); 8077 ins_cost(DEFAULT_COST*3); 8078 8079 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8080 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8081 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8082 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8083 ins_pipe( cadd_cmpltmask ); 8084 %} 8085 8086 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8087 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 8088 effect( KILL ccr, TEMP tmp); 8089 ins_cost(DEFAULT_COST*3); 8090 8091 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8092 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8093 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8094 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8095 ins_pipe( cadd_cmpltmask ); 8096 %} 8097 8098 //----------Arithmetic Conversion Instructions--------------------------------- 8099 // The conversions operations are all Alpha sorted. Please keep it that way! 8100 8101 instruct convD2F_reg(regF dst, regD src) %{ 8102 match(Set dst (ConvD2F src)); 8103 size(4); 8104 format %{ "FDTOS $src,$dst" %} 8105 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8106 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8107 ins_pipe(fcvtD2F); 8108 %} 8109 8110 8111 // Convert a double to an int in a float register. 8112 // If the double is a NAN, stuff a zero in instead. 8113 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8114 effect(DEF dst, USE src, KILL fcc0); 8115 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8116 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8117 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8118 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8119 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8120 "skip:" %} 8121 ins_encode(form_d2i_helper(src,dst)); 8122 ins_pipe(fcvtD2I); 8123 %} 8124 8125 instruct convD2I_reg(stackSlotI dst, regD src) %{ 8126 match(Set dst (ConvD2I src)); 8127 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8128 expand %{ 8129 regF tmp; 8130 convD2I_helper(tmp, src); 8131 regF_to_stkI(dst, tmp); 8132 %} 8133 %} 8134 8135 // Convert a double to a long in a double register. 8136 // If the double is a NAN, stuff a zero in instead. 8137 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8138 effect(DEF dst, USE src, KILL fcc0); 8139 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8140 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8141 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8142 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8143 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8144 "skip:" %} 8145 ins_encode(form_d2l_helper(src,dst)); 8146 ins_pipe(fcvtD2L); 8147 %} 8148 8149 8150 // Double to Long conversion 8151 instruct convD2L_reg(stackSlotL dst, regD src) %{ 8152 match(Set dst (ConvD2L src)); 8153 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8154 expand %{ 8155 regD tmp; 8156 convD2L_helper(tmp, src); 8157 regD_to_stkL(dst, tmp); 8158 %} 8159 %} 8160 8161 8162 instruct convF2D_reg(regD dst, regF src) %{ 8163 match(Set dst (ConvF2D src)); 8164 format %{ "FSTOD $src,$dst" %} 8165 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8166 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8167 ins_pipe(fcvtF2D); 8168 %} 8169 8170 8171 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8172 effect(DEF dst, USE src, KILL fcc0); 8173 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8174 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8175 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8176 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8177 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8178 "skip:" %} 8179 ins_encode(form_f2i_helper(src,dst)); 8180 ins_pipe(fcvtF2I); 8181 %} 8182 8183 instruct convF2I_reg(stackSlotI dst, regF src) %{ 8184 match(Set dst (ConvF2I src)); 8185 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8186 expand %{ 8187 regF tmp; 8188 convF2I_helper(tmp, src); 8189 regF_to_stkI(dst, tmp); 8190 %} 8191 %} 8192 8193 8194 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8195 effect(DEF dst, USE src, KILL fcc0); 8196 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8197 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8198 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8199 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8200 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8201 "skip:" %} 8202 ins_encode(form_f2l_helper(src,dst)); 8203 ins_pipe(fcvtF2L); 8204 %} 8205 8206 // Float to Long conversion 8207 instruct convF2L_reg(stackSlotL dst, regF src) %{ 8208 match(Set dst (ConvF2L src)); 8209 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8210 expand %{ 8211 regD tmp; 8212 convF2L_helper(tmp, src); 8213 regD_to_stkL(dst, tmp); 8214 %} 8215 %} 8216 8217 8218 instruct convI2D_helper(regD dst, regF tmp) %{ 8219 effect(USE tmp, DEF dst); 8220 format %{ "FITOD $tmp,$dst" %} 8221 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8222 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8223 ins_pipe(fcvtI2D); 8224 %} 8225 8226 instruct convI2D_reg(stackSlotI src, regD dst) %{ 8227 match(Set dst (ConvI2D src)); 8228 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8229 expand %{ 8230 regF tmp; 8231 stkI_to_regF( tmp, src); 8232 convI2D_helper( dst, tmp); 8233 %} 8234 %} 8235 8236 instruct convI2D_mem( regD_low dst, memory mem ) %{ 8237 match(Set dst (ConvI2D (LoadI mem))); 8238 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8239 size(8); 8240 format %{ "LDF $mem,$dst\n\t" 8241 "FITOD $dst,$dst" %} 8242 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8243 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8244 ins_pipe(floadF_mem); 8245 %} 8246 8247 8248 instruct convI2F_helper(regF dst, regF tmp) %{ 8249 effect(DEF dst, USE tmp); 8250 format %{ "FITOS $tmp,$dst" %} 8251 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8252 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8253 ins_pipe(fcvtI2F); 8254 %} 8255 8256 instruct convI2F_reg( regF dst, stackSlotI src ) %{ 8257 match(Set dst (ConvI2F src)); 8258 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8259 expand %{ 8260 regF tmp; 8261 stkI_to_regF(tmp,src); 8262 convI2F_helper(dst, tmp); 8263 %} 8264 %} 8265 8266 instruct convI2F_mem( regF dst, memory mem ) %{ 8267 match(Set dst (ConvI2F (LoadI mem))); 8268 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8269 size(8); 8270 format %{ "LDF $mem,$dst\n\t" 8271 "FITOS $dst,$dst" %} 8272 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8273 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8274 ins_pipe(floadF_mem); 8275 %} 8276 8277 8278 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8279 match(Set dst (ConvI2L src)); 8280 size(4); 8281 format %{ "SRA $src,0,$dst\t! int->long" %} 8282 opcode(Assembler::sra_op3, Assembler::arith_op); 8283 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8284 ins_pipe(ialu_reg_reg); 8285 %} 8286 8287 // Zero-extend convert int to long 8288 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8289 match(Set dst (AndL (ConvI2L src) mask) ); 8290 size(4); 8291 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8292 opcode(Assembler::srl_op3, Assembler::arith_op); 8293 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8294 ins_pipe(ialu_reg_reg); 8295 %} 8296 8297 // Zero-extend long 8298 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8299 match(Set dst (AndL src mask) ); 8300 size(4); 8301 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8302 opcode(Assembler::srl_op3, Assembler::arith_op); 8303 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8304 ins_pipe(ialu_reg_reg); 8305 %} 8306 8307 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8308 match(Set dst (MoveF2I src)); 8309 effect(DEF dst, USE src); 8310 ins_cost(MEMORY_REF_COST); 8311 8312 size(4); 8313 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8314 opcode(Assembler::lduw_op3); 8315 ins_encode(simple_form3_mem_reg( src, dst ) ); 8316 ins_pipe(iload_mem); 8317 %} 8318 8319 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8320 match(Set dst (MoveI2F src)); 8321 effect(DEF dst, USE src); 8322 ins_cost(MEMORY_REF_COST); 8323 8324 size(4); 8325 format %{ "LDF $src,$dst\t! MoveI2F" %} 8326 opcode(Assembler::ldf_op3); 8327 ins_encode(simple_form3_mem_reg(src, dst)); 8328 ins_pipe(floadF_stk); 8329 %} 8330 8331 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8332 match(Set dst (MoveD2L src)); 8333 effect(DEF dst, USE src); 8334 ins_cost(MEMORY_REF_COST); 8335 8336 size(4); 8337 format %{ "LDX $src,$dst\t! MoveD2L" %} 8338 opcode(Assembler::ldx_op3); 8339 ins_encode(simple_form3_mem_reg( src, dst ) ); 8340 ins_pipe(iload_mem); 8341 %} 8342 8343 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8344 match(Set dst (MoveL2D src)); 8345 effect(DEF dst, USE src); 8346 ins_cost(MEMORY_REF_COST); 8347 8348 size(4); 8349 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8350 opcode(Assembler::lddf_op3); 8351 ins_encode(simple_form3_mem_reg(src, dst)); 8352 ins_pipe(floadD_stk); 8353 %} 8354 8355 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8356 match(Set dst (MoveF2I src)); 8357 effect(DEF dst, USE src); 8358 ins_cost(MEMORY_REF_COST); 8359 8360 size(4); 8361 format %{ "STF $src,$dst\t!MoveF2I" %} 8362 opcode(Assembler::stf_op3); 8363 ins_encode(simple_form3_mem_reg(dst, src)); 8364 ins_pipe(fstoreF_stk_reg); 8365 %} 8366 8367 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8368 match(Set dst (MoveI2F src)); 8369 effect(DEF dst, USE src); 8370 ins_cost(MEMORY_REF_COST); 8371 8372 size(4); 8373 format %{ "STW $src,$dst\t!MoveI2F" %} 8374 opcode(Assembler::stw_op3); 8375 ins_encode(simple_form3_mem_reg( dst, src ) ); 8376 ins_pipe(istore_mem_reg); 8377 %} 8378 8379 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8380 match(Set dst (MoveD2L src)); 8381 effect(DEF dst, USE src); 8382 ins_cost(MEMORY_REF_COST); 8383 8384 size(4); 8385 format %{ "STDF $src,$dst\t!MoveD2L" %} 8386 opcode(Assembler::stdf_op3); 8387 ins_encode(simple_form3_mem_reg(dst, src)); 8388 ins_pipe(fstoreD_stk_reg); 8389 %} 8390 8391 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8392 match(Set dst (MoveL2D src)); 8393 effect(DEF dst, USE src); 8394 ins_cost(MEMORY_REF_COST); 8395 8396 size(4); 8397 format %{ "STX $src,$dst\t!MoveL2D" %} 8398 opcode(Assembler::stx_op3); 8399 ins_encode(simple_form3_mem_reg( dst, src ) ); 8400 ins_pipe(istore_mem_reg); 8401 %} 8402 8403 8404 //----------- 8405 // Long to Double conversion using V8 opcodes. 8406 // Still useful because cheetah traps and becomes 8407 // amazingly slow for some common numbers. 8408 8409 // Magic constant, 0x43300000 8410 instruct loadConI_x43300000(iRegI dst) %{ 8411 effect(DEF dst); 8412 size(4); 8413 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8414 ins_encode(SetHi22(0x43300000, dst)); 8415 ins_pipe(ialu_none); 8416 %} 8417 8418 // Magic constant, 0x41f00000 8419 instruct loadConI_x41f00000(iRegI dst) %{ 8420 effect(DEF dst); 8421 size(4); 8422 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8423 ins_encode(SetHi22(0x41f00000, dst)); 8424 ins_pipe(ialu_none); 8425 %} 8426 8427 // Construct a double from two float halves 8428 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8429 effect(DEF dst, USE src1, USE src2); 8430 size(8); 8431 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8432 "FMOVS $src2.lo,$dst.lo" %} 8433 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8434 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8435 ins_pipe(faddD_reg_reg); 8436 %} 8437 8438 // Convert integer in high half of a double register (in the lower half of 8439 // the double register file) to double 8440 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8441 effect(DEF dst, USE src); 8442 size(4); 8443 format %{ "FITOD $src,$dst" %} 8444 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8445 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8446 ins_pipe(fcvtLHi2D); 8447 %} 8448 8449 // Add float double precision 8450 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8451 effect(DEF dst, USE src1, USE src2); 8452 size(4); 8453 format %{ "FADDD $src1,$src2,$dst" %} 8454 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8455 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8456 ins_pipe(faddD_reg_reg); 8457 %} 8458 8459 // Sub float double precision 8460 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8461 effect(DEF dst, USE src1, USE src2); 8462 size(4); 8463 format %{ "FSUBD $src1,$src2,$dst" %} 8464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8465 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8466 ins_pipe(faddD_reg_reg); 8467 %} 8468 8469 // Mul float double precision 8470 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8471 effect(DEF dst, USE src1, USE src2); 8472 size(4); 8473 format %{ "FMULD $src1,$src2,$dst" %} 8474 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8475 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8476 ins_pipe(fmulD_reg_reg); 8477 %} 8478 8479 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8480 match(Set dst (ConvL2D src)); 8481 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8482 8483 expand %{ 8484 regD_low tmpsrc; 8485 iRegI ix43300000; 8486 iRegI ix41f00000; 8487 stackSlotL lx43300000; 8488 stackSlotL lx41f00000; 8489 regD_low dx43300000; 8490 regD dx41f00000; 8491 regD tmp1; 8492 regD_low tmp2; 8493 regD tmp3; 8494 regD tmp4; 8495 8496 stkL_to_regD(tmpsrc, src); 8497 8498 loadConI_x43300000(ix43300000); 8499 loadConI_x41f00000(ix41f00000); 8500 regI_to_stkLHi(lx43300000, ix43300000); 8501 regI_to_stkLHi(lx41f00000, ix41f00000); 8502 stkL_to_regD(dx43300000, lx43300000); 8503 stkL_to_regD(dx41f00000, lx41f00000); 8504 8505 convI2D_regDHi_regD(tmp1, tmpsrc); 8506 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8507 subD_regD_regD(tmp3, tmp2, dx43300000); 8508 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8509 addD_regD_regD(dst, tmp3, tmp4); 8510 %} 8511 %} 8512 8513 // Long to Double conversion using fast fxtof 8514 instruct convL2D_helper(regD dst, regD tmp) %{ 8515 effect(DEF dst, USE tmp); 8516 size(4); 8517 format %{ "FXTOD $tmp,$dst" %} 8518 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8519 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8520 ins_pipe(fcvtL2D); 8521 %} 8522 8523 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 8524 predicate(VM_Version::has_fast_fxtof()); 8525 match(Set dst (ConvL2D src)); 8526 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8527 expand %{ 8528 regD tmp; 8529 stkL_to_regD(tmp, src); 8530 convL2D_helper(dst, tmp); 8531 %} 8532 %} 8533 8534 //----------- 8535 // Long to Float conversion using V8 opcodes. 8536 // Still useful because cheetah traps and becomes 8537 // amazingly slow for some common numbers. 8538 8539 // Long to Float conversion using fast fxtof 8540 instruct convL2F_helper(regF dst, regD tmp) %{ 8541 effect(DEF dst, USE tmp); 8542 size(4); 8543 format %{ "FXTOS $tmp,$dst" %} 8544 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8545 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8546 ins_pipe(fcvtL2F); 8547 %} 8548 8549 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 8550 match(Set dst (ConvL2F src)); 8551 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8552 expand %{ 8553 regD tmp; 8554 stkL_to_regD(tmp, src); 8555 convL2F_helper(dst, tmp); 8556 %} 8557 %} 8558 //----------- 8559 8560 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8561 match(Set dst (ConvL2I src)); 8562 #ifndef _LP64 8563 format %{ "MOV $src.lo,$dst\t! long->int" %} 8564 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8565 ins_pipe(ialu_move_reg_I_to_L); 8566 #else 8567 size(4); 8568 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8569 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8570 ins_pipe(ialu_reg); 8571 #endif 8572 %} 8573 8574 // Register Shift Right Immediate 8575 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8576 match(Set dst (ConvL2I (RShiftL src cnt))); 8577 8578 size(4); 8579 format %{ "SRAX $src,$cnt,$dst" %} 8580 opcode(Assembler::srax_op3, Assembler::arith_op); 8581 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8582 ins_pipe(ialu_reg_imm); 8583 %} 8584 8585 // Replicate scalar to packed byte values in Double register 8586 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8587 effect(DEF dst, USE src); 8588 format %{ "SLLX $src,56,$dst\n\t" 8589 "SRLX $dst, 8,O7\n\t" 8590 "OR $dst,O7,$dst\n\t" 8591 "SRLX $dst,16,O7\n\t" 8592 "OR $dst,O7,$dst\n\t" 8593 "SRLX $dst,32,O7\n\t" 8594 "OR $dst,O7,$dst\t! replicate8B" %} 8595 ins_encode( enc_repl8b(src, dst)); 8596 ins_pipe(ialu_reg); 8597 %} 8598 8599 // Replicate scalar to packed byte values in Double register 8600 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8601 match(Set dst (Replicate8B src)); 8602 expand %{ 8603 iRegL tmp; 8604 Repl8B_reg_helper(tmp, src); 8605 regL_to_stkD(dst, tmp); 8606 %} 8607 %} 8608 8609 // Replicate scalar constant to packed byte values in Double register 8610 instruct Repl8B_immI(regD dst, immI13 con) %{ 8611 match(Set dst (Replicate8B con)); 8612 size(4); 8613 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 8614 ins_encode %{ 8615 // XXX This is a quick fix for 6833573. 8616 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 8617 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), as_DoubleFloatRegister($dst$$reg)); 8618 %} 8619 ins_pipe(loadConFD); 8620 %} 8621 8622 // Replicate scalar to packed char values into stack slot 8623 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8624 effect(DEF dst, USE src); 8625 format %{ "SLLX $src,48,$dst\n\t" 8626 "SRLX $dst,16,O7\n\t" 8627 "OR $dst,O7,$dst\n\t" 8628 "SRLX $dst,32,O7\n\t" 8629 "OR $dst,O7,$dst\t! replicate4C" %} 8630 ins_encode( enc_repl4s(src, dst) ); 8631 ins_pipe(ialu_reg); 8632 %} 8633 8634 // Replicate scalar to packed char values into stack slot 8635 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8636 match(Set dst (Replicate4C src)); 8637 expand %{ 8638 iRegL tmp; 8639 Repl4C_reg_helper(tmp, src); 8640 regL_to_stkD(dst, tmp); 8641 %} 8642 %} 8643 8644 // Replicate scalar constant to packed char values in Double register 8645 instruct Repl4C_immI(regD dst, immI con) %{ 8646 match(Set dst (Replicate4C con)); 8647 size(4); 8648 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} 8649 ins_encode %{ 8650 // XXX This is a quick fix for 6833573. 8651 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 8652 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg)); 8653 %} 8654 ins_pipe(loadConFD); 8655 %} 8656 8657 // Replicate scalar to packed short values into stack slot 8658 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8659 effect(DEF dst, USE src); 8660 format %{ "SLLX $src,48,$dst\n\t" 8661 "SRLX $dst,16,O7\n\t" 8662 "OR $dst,O7,$dst\n\t" 8663 "SRLX $dst,32,O7\n\t" 8664 "OR $dst,O7,$dst\t! replicate4S" %} 8665 ins_encode( enc_repl4s(src, dst) ); 8666 ins_pipe(ialu_reg); 8667 %} 8668 8669 // Replicate scalar to packed short values into stack slot 8670 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8671 match(Set dst (Replicate4S src)); 8672 expand %{ 8673 iRegL tmp; 8674 Repl4S_reg_helper(tmp, src); 8675 regL_to_stkD(dst, tmp); 8676 %} 8677 %} 8678 8679 // Replicate scalar constant to packed short values in Double register 8680 instruct Repl4S_immI(regD dst, immI con) %{ 8681 match(Set dst (Replicate4S con)); 8682 size(4); 8683 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 8684 ins_encode %{ 8685 // XXX This is a quick fix for 6833573. 8686 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 8687 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg)); 8688 %} 8689 ins_pipe(loadConFD); 8690 %} 8691 8692 // Replicate scalar to packed int values in Double register 8693 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8694 effect(DEF dst, USE src); 8695 format %{ "SLLX $src,32,$dst\n\t" 8696 "SRLX $dst,32,O7\n\t" 8697 "OR $dst,O7,$dst\t! replicate2I" %} 8698 ins_encode( enc_repl2i(src, dst)); 8699 ins_pipe(ialu_reg); 8700 %} 8701 8702 // Replicate scalar to packed int values in Double register 8703 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8704 match(Set dst (Replicate2I src)); 8705 expand %{ 8706 iRegL tmp; 8707 Repl2I_reg_helper(tmp, src); 8708 regL_to_stkD(dst, tmp); 8709 %} 8710 %} 8711 8712 // Replicate scalar zero constant to packed int values in Double register 8713 instruct Repl2I_immI(regD dst, immI con) %{ 8714 match(Set dst (Replicate2I con)); 8715 size(4); 8716 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 8717 ins_encode %{ 8718 // XXX This is a quick fix for 6833573. 8719 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 8720 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), as_DoubleFloatRegister($dst$$reg)); 8721 %} 8722 ins_pipe(loadConFD); 8723 %} 8724 8725 //----------Control Flow Instructions------------------------------------------ 8726 // Compare Instructions 8727 // Compare Integers 8728 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8729 match(Set icc (CmpI op1 op2)); 8730 effect( DEF icc, USE op1, USE op2 ); 8731 8732 size(4); 8733 format %{ "CMP $op1,$op2" %} 8734 opcode(Assembler::subcc_op3, Assembler::arith_op); 8735 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8736 ins_pipe(ialu_cconly_reg_reg); 8737 %} 8738 8739 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8740 match(Set icc (CmpU op1 op2)); 8741 8742 size(4); 8743 format %{ "CMP $op1,$op2\t! unsigned" %} 8744 opcode(Assembler::subcc_op3, Assembler::arith_op); 8745 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8746 ins_pipe(ialu_cconly_reg_reg); 8747 %} 8748 8749 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8750 match(Set icc (CmpI op1 op2)); 8751 effect( DEF icc, USE op1 ); 8752 8753 size(4); 8754 format %{ "CMP $op1,$op2" %} 8755 opcode(Assembler::subcc_op3, Assembler::arith_op); 8756 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8757 ins_pipe(ialu_cconly_reg_imm); 8758 %} 8759 8760 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8761 match(Set icc (CmpI (AndI op1 op2) zero)); 8762 8763 size(4); 8764 format %{ "BTST $op2,$op1" %} 8765 opcode(Assembler::andcc_op3, Assembler::arith_op); 8766 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8767 ins_pipe(ialu_cconly_reg_reg_zero); 8768 %} 8769 8770 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8771 match(Set icc (CmpI (AndI op1 op2) zero)); 8772 8773 size(4); 8774 format %{ "BTST $op2,$op1" %} 8775 opcode(Assembler::andcc_op3, Assembler::arith_op); 8776 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8777 ins_pipe(ialu_cconly_reg_imm_zero); 8778 %} 8779 8780 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8781 match(Set xcc (CmpL op1 op2)); 8782 effect( DEF xcc, USE op1, USE op2 ); 8783 8784 size(4); 8785 format %{ "CMP $op1,$op2\t\t! long" %} 8786 opcode(Assembler::subcc_op3, Assembler::arith_op); 8787 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8788 ins_pipe(ialu_cconly_reg_reg); 8789 %} 8790 8791 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8792 match(Set xcc (CmpL op1 con)); 8793 effect( DEF xcc, USE op1, USE con ); 8794 8795 size(4); 8796 format %{ "CMP $op1,$con\t\t! long" %} 8797 opcode(Assembler::subcc_op3, Assembler::arith_op); 8798 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8799 ins_pipe(ialu_cconly_reg_reg); 8800 %} 8801 8802 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8803 match(Set xcc (CmpL (AndL op1 op2) zero)); 8804 effect( DEF xcc, USE op1, USE op2 ); 8805 8806 size(4); 8807 format %{ "BTST $op1,$op2\t\t! long" %} 8808 opcode(Assembler::andcc_op3, Assembler::arith_op); 8809 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8810 ins_pipe(ialu_cconly_reg_reg); 8811 %} 8812 8813 // useful for checking the alignment of a pointer: 8814 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8815 match(Set xcc (CmpL (AndL op1 con) zero)); 8816 effect( DEF xcc, USE op1, USE con ); 8817 8818 size(4); 8819 format %{ "BTST $op1,$con\t\t! long" %} 8820 opcode(Assembler::andcc_op3, Assembler::arith_op); 8821 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8822 ins_pipe(ialu_cconly_reg_reg); 8823 %} 8824 8825 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8826 match(Set icc (CmpU op1 op2)); 8827 8828 size(4); 8829 format %{ "CMP $op1,$op2\t! unsigned" %} 8830 opcode(Assembler::subcc_op3, Assembler::arith_op); 8831 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8832 ins_pipe(ialu_cconly_reg_imm); 8833 %} 8834 8835 // Compare Pointers 8836 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8837 match(Set pcc (CmpP op1 op2)); 8838 8839 size(4); 8840 format %{ "CMP $op1,$op2\t! ptr" %} 8841 opcode(Assembler::subcc_op3, Assembler::arith_op); 8842 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8843 ins_pipe(ialu_cconly_reg_reg); 8844 %} 8845 8846 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8847 match(Set pcc (CmpP op1 op2)); 8848 8849 size(4); 8850 format %{ "CMP $op1,$op2\t! ptr" %} 8851 opcode(Assembler::subcc_op3, Assembler::arith_op); 8852 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8853 ins_pipe(ialu_cconly_reg_imm); 8854 %} 8855 8856 // Compare Narrow oops 8857 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8858 match(Set icc (CmpN op1 op2)); 8859 8860 size(4); 8861 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8862 opcode(Assembler::subcc_op3, Assembler::arith_op); 8863 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8864 ins_pipe(ialu_cconly_reg_reg); 8865 %} 8866 8867 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8868 match(Set icc (CmpN op1 op2)); 8869 8870 size(4); 8871 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8872 opcode(Assembler::subcc_op3, Assembler::arith_op); 8873 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8874 ins_pipe(ialu_cconly_reg_imm); 8875 %} 8876 8877 //----------Max and Min-------------------------------------------------------- 8878 // Min Instructions 8879 // Conditional move for min 8880 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8881 effect( USE_DEF op2, USE op1, USE icc ); 8882 8883 size(4); 8884 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8885 opcode(Assembler::less); 8886 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8887 ins_pipe(ialu_reg_flags); 8888 %} 8889 8890 // Min Register with Register. 8891 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8892 match(Set op2 (MinI op1 op2)); 8893 ins_cost(DEFAULT_COST*2); 8894 expand %{ 8895 flagsReg icc; 8896 compI_iReg(icc,op1,op2); 8897 cmovI_reg_lt(op2,op1,icc); 8898 %} 8899 %} 8900 8901 // Max Instructions 8902 // Conditional move for max 8903 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8904 effect( USE_DEF op2, USE op1, USE icc ); 8905 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8906 opcode(Assembler::greater); 8907 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8908 ins_pipe(ialu_reg_flags); 8909 %} 8910 8911 // Max Register with Register 8912 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8913 match(Set op2 (MaxI op1 op2)); 8914 ins_cost(DEFAULT_COST*2); 8915 expand %{ 8916 flagsReg icc; 8917 compI_iReg(icc,op1,op2); 8918 cmovI_reg_gt(op2,op1,icc); 8919 %} 8920 %} 8921 8922 8923 //----------Float Compares---------------------------------------------------- 8924 // Compare floating, generate condition code 8925 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8926 match(Set fcc (CmpF src1 src2)); 8927 8928 size(4); 8929 format %{ "FCMPs $fcc,$src1,$src2" %} 8930 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8931 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8932 ins_pipe(faddF_fcc_reg_reg_zero); 8933 %} 8934 8935 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8936 match(Set fcc (CmpD src1 src2)); 8937 8938 size(4); 8939 format %{ "FCMPd $fcc,$src1,$src2" %} 8940 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8941 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8942 ins_pipe(faddD_fcc_reg_reg_zero); 8943 %} 8944 8945 8946 // Compare floating, generate -1,0,1 8947 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8948 match(Set dst (CmpF3 src1 src2)); 8949 effect(KILL fcc0); 8950 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8951 format %{ "fcmpl $dst,$src1,$src2" %} 8952 // Primary = float 8953 opcode( true ); 8954 ins_encode( floating_cmp( dst, src1, src2 ) ); 8955 ins_pipe( floating_cmp ); 8956 %} 8957 8958 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8959 match(Set dst (CmpD3 src1 src2)); 8960 effect(KILL fcc0); 8961 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8962 format %{ "dcmpl $dst,$src1,$src2" %} 8963 // Primary = double (not float) 8964 opcode( false ); 8965 ins_encode( floating_cmp( dst, src1, src2 ) ); 8966 ins_pipe( floating_cmp ); 8967 %} 8968 8969 //----------Branches--------------------------------------------------------- 8970 // Jump 8971 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8972 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8973 match(Jump switch_val); 8974 8975 ins_cost(350); 8976 8977 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 8978 "LD [O7 + $switch_val], O7\n\t" 8979 "JUMP O7" 8980 %} 8981 ins_encode %{ 8982 // Calculate table address into a register. 8983 Register table_reg; 8984 Register label_reg = O7; 8985 if (constant_offset() == 0) { 8986 table_reg = $constanttablebase; 8987 } else { 8988 table_reg = O7; 8989 __ add($constanttablebase, $constantoffset, table_reg); 8990 } 8991 8992 // Jump to base address + switch value 8993 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 8994 __ jmp(label_reg, G0); 8995 __ delayed()->nop(); 8996 %} 8997 ins_pc_relative(1); 8998 ins_pipe(ialu_reg_reg); 8999 %} 9000 9001 // Direct Branch. Use V8 version with longer range. 9002 instruct branch(label labl) %{ 9003 match(Goto); 9004 effect(USE labl); 9005 9006 size(8); 9007 ins_cost(BRANCH_COST); 9008 format %{ "BA $labl" %} 9009 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 9010 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 9011 ins_encode( enc_ba( labl ) ); 9012 ins_pc_relative(1); 9013 ins_pipe(br); 9014 %} 9015 9016 // Conditional Direct Branch 9017 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9018 match(If cmp icc); 9019 effect(USE labl); 9020 9021 size(8); 9022 ins_cost(BRANCH_COST); 9023 format %{ "BP$cmp $icc,$labl" %} 9024 // Prim = bits 24-22, Secnd = bits 31-30 9025 ins_encode( enc_bp( labl, cmp, icc ) ); 9026 ins_pc_relative(1); 9027 ins_pipe(br_cc); 9028 %} 9029 9030 // Branch-on-register tests all 64 bits. We assume that values 9031 // in 64-bit registers always remains zero or sign extended 9032 // unless our code munges the high bits. Interrupts can chop 9033 // the high order bits to zero or sign at any time. 9034 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9035 match(If cmp (CmpI op1 zero)); 9036 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9037 effect(USE labl); 9038 9039 size(8); 9040 ins_cost(BRANCH_COST); 9041 format %{ "BR$cmp $op1,$labl" %} 9042 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9043 ins_pc_relative(1); 9044 ins_pipe(br_reg); 9045 %} 9046 9047 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9048 match(If cmp (CmpP op1 null)); 9049 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9050 effect(USE labl); 9051 9052 size(8); 9053 ins_cost(BRANCH_COST); 9054 format %{ "BR$cmp $op1,$labl" %} 9055 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9056 ins_pc_relative(1); 9057 ins_pipe(br_reg); 9058 %} 9059 9060 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9061 match(If cmp (CmpL op1 zero)); 9062 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9063 effect(USE labl); 9064 9065 size(8); 9066 ins_cost(BRANCH_COST); 9067 format %{ "BR$cmp $op1,$labl" %} 9068 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9069 ins_pc_relative(1); 9070 ins_pipe(br_reg); 9071 %} 9072 9073 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9074 match(If cmp icc); 9075 effect(USE labl); 9076 9077 format %{ "BP$cmp $icc,$labl" %} 9078 // Prim = bits 24-22, Secnd = bits 31-30 9079 ins_encode( enc_bp( labl, cmp, icc ) ); 9080 ins_pc_relative(1); 9081 ins_pipe(br_cc); 9082 %} 9083 9084 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9085 match(If cmp pcc); 9086 effect(USE labl); 9087 9088 size(8); 9089 ins_cost(BRANCH_COST); 9090 format %{ "BP$cmp $pcc,$labl" %} 9091 // Prim = bits 24-22, Secnd = bits 31-30 9092 ins_encode( enc_bpx( labl, cmp, pcc ) ); 9093 ins_pc_relative(1); 9094 ins_pipe(br_cc); 9095 %} 9096 9097 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9098 match(If cmp fcc); 9099 effect(USE labl); 9100 9101 size(8); 9102 ins_cost(BRANCH_COST); 9103 format %{ "FBP$cmp $fcc,$labl" %} 9104 // Prim = bits 24-22, Secnd = bits 31-30 9105 ins_encode( enc_fbp( labl, cmp, fcc ) ); 9106 ins_pc_relative(1); 9107 ins_pipe(br_fcc); 9108 %} 9109 9110 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9111 match(CountedLoopEnd cmp icc); 9112 effect(USE labl); 9113 9114 size(8); 9115 ins_cost(BRANCH_COST); 9116 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9117 // Prim = bits 24-22, Secnd = bits 31-30 9118 ins_encode( enc_bp( labl, cmp, icc ) ); 9119 ins_pc_relative(1); 9120 ins_pipe(br_cc); 9121 %} 9122 9123 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9124 match(CountedLoopEnd cmp icc); 9125 effect(USE labl); 9126 9127 size(8); 9128 ins_cost(BRANCH_COST); 9129 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9130 // Prim = bits 24-22, Secnd = bits 31-30 9131 ins_encode( enc_bp( labl, cmp, icc ) ); 9132 ins_pc_relative(1); 9133 ins_pipe(br_cc); 9134 %} 9135 9136 // ============================================================================ 9137 // Long Compare 9138 // 9139 // Currently we hold longs in 2 registers. Comparing such values efficiently 9140 // is tricky. The flavor of compare used depends on whether we are testing 9141 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9142 // The GE test is the negated LT test. The LE test can be had by commuting 9143 // the operands (yielding a GE test) and then negating; negate again for the 9144 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9145 // NE test is negated from that. 9146 9147 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9148 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9149 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9150 // are collapsed internally in the ADLC's dfa-gen code. The match for 9151 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9152 // foo match ends up with the wrong leaf. One fix is to not match both 9153 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9154 // both forms beat the trinary form of long-compare and both are very useful 9155 // on Intel which has so few registers. 9156 9157 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9158 match(If cmp xcc); 9159 effect(USE labl); 9160 9161 size(8); 9162 ins_cost(BRANCH_COST); 9163 format %{ "BP$cmp $xcc,$labl" %} 9164 // Prim = bits 24-22, Secnd = bits 31-30 9165 ins_encode( enc_bpl( labl, cmp, xcc ) ); 9166 ins_pc_relative(1); 9167 ins_pipe(br_cc); 9168 %} 9169 9170 // Manifest a CmpL3 result in an integer register. Very painful. 9171 // This is the test to avoid. 9172 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9173 match(Set dst (CmpL3 src1 src2) ); 9174 effect( KILL ccr ); 9175 ins_cost(6*DEFAULT_COST); 9176 size(24); 9177 format %{ "CMP $src1,$src2\t\t! long\n" 9178 "\tBLT,a,pn done\n" 9179 "\tMOV -1,$dst\t! delay slot\n" 9180 "\tBGT,a,pn done\n" 9181 "\tMOV 1,$dst\t! delay slot\n" 9182 "\tCLR $dst\n" 9183 "done:" %} 9184 ins_encode( cmpl_flag(src1,src2,dst) ); 9185 ins_pipe(cmpL_reg); 9186 %} 9187 9188 // Conditional move 9189 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9190 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9191 ins_cost(150); 9192 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9193 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9194 ins_pipe(ialu_reg); 9195 %} 9196 9197 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9198 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9199 ins_cost(140); 9200 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9201 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9202 ins_pipe(ialu_imm); 9203 %} 9204 9205 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9206 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9207 ins_cost(150); 9208 format %{ "MOV$cmp $xcc,$src,$dst" %} 9209 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9210 ins_pipe(ialu_reg); 9211 %} 9212 9213 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9214 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9215 ins_cost(140); 9216 format %{ "MOV$cmp $xcc,$src,$dst" %} 9217 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9218 ins_pipe(ialu_imm); 9219 %} 9220 9221 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9222 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9223 ins_cost(150); 9224 format %{ "MOV$cmp $xcc,$src,$dst" %} 9225 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9226 ins_pipe(ialu_reg); 9227 %} 9228 9229 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9230 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9231 ins_cost(150); 9232 format %{ "MOV$cmp $xcc,$src,$dst" %} 9233 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9234 ins_pipe(ialu_reg); 9235 %} 9236 9237 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9238 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9239 ins_cost(140); 9240 format %{ "MOV$cmp $xcc,$src,$dst" %} 9241 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9242 ins_pipe(ialu_imm); 9243 %} 9244 9245 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9246 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9247 ins_cost(150); 9248 opcode(0x101); 9249 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9250 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9251 ins_pipe(int_conditional_float_move); 9252 %} 9253 9254 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9255 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9256 ins_cost(150); 9257 opcode(0x102); 9258 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9259 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9260 ins_pipe(int_conditional_float_move); 9261 %} 9262 9263 // ============================================================================ 9264 // Safepoint Instruction 9265 instruct safePoint_poll(iRegP poll) %{ 9266 match(SafePoint poll); 9267 effect(USE poll); 9268 9269 size(4); 9270 #ifdef _LP64 9271 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9272 #else 9273 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9274 #endif 9275 ins_encode %{ 9276 __ relocate(relocInfo::poll_type); 9277 __ ld_ptr($poll$$Register, 0, G0); 9278 %} 9279 ins_pipe(loadPollP); 9280 %} 9281 9282 // ============================================================================ 9283 // Call Instructions 9284 // Call Java Static Instruction 9285 instruct CallStaticJavaDirect( method meth ) %{ 9286 match(CallStaticJava); 9287 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9288 effect(USE meth); 9289 9290 size(8); 9291 ins_cost(CALL_COST); 9292 format %{ "CALL,static ; NOP ==> " %} 9293 ins_encode( Java_Static_Call( meth ), call_epilog ); 9294 ins_pc_relative(1); 9295 ins_pipe(simple_call); 9296 %} 9297 9298 // Call Java Static Instruction (method handle version) 9299 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9300 match(CallStaticJava); 9301 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9302 effect(USE meth, KILL l7_mh_SP_save); 9303 9304 size(8); 9305 ins_cost(CALL_COST); 9306 format %{ "CALL,static/MethodHandle" %} 9307 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9308 ins_pc_relative(1); 9309 ins_pipe(simple_call); 9310 %} 9311 9312 // Call Java Dynamic Instruction 9313 instruct CallDynamicJavaDirect( method meth ) %{ 9314 match(CallDynamicJava); 9315 effect(USE meth); 9316 9317 ins_cost(CALL_COST); 9318 format %{ "SET (empty),R_G5\n\t" 9319 "CALL,dynamic ; NOP ==> " %} 9320 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9321 ins_pc_relative(1); 9322 ins_pipe(call); 9323 %} 9324 9325 // Call Runtime Instruction 9326 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9327 match(CallRuntime); 9328 effect(USE meth, KILL l7); 9329 ins_cost(CALL_COST); 9330 format %{ "CALL,runtime" %} 9331 ins_encode( Java_To_Runtime( meth ), 9332 call_epilog, adjust_long_from_native_call ); 9333 ins_pc_relative(1); 9334 ins_pipe(simple_call); 9335 %} 9336 9337 // Call runtime without safepoint - same as CallRuntime 9338 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9339 match(CallLeaf); 9340 effect(USE meth, KILL l7); 9341 ins_cost(CALL_COST); 9342 format %{ "CALL,runtime leaf" %} 9343 ins_encode( Java_To_Runtime( meth ), 9344 call_epilog, 9345 adjust_long_from_native_call ); 9346 ins_pc_relative(1); 9347 ins_pipe(simple_call); 9348 %} 9349 9350 // Call runtime without safepoint - same as CallLeaf 9351 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9352 match(CallLeafNoFP); 9353 effect(USE meth, KILL l7); 9354 ins_cost(CALL_COST); 9355 format %{ "CALL,runtime leaf nofp" %} 9356 ins_encode( Java_To_Runtime( meth ), 9357 call_epilog, 9358 adjust_long_from_native_call ); 9359 ins_pc_relative(1); 9360 ins_pipe(simple_call); 9361 %} 9362 9363 // Tail Call; Jump from runtime stub to Java code. 9364 // Also known as an 'interprocedural jump'. 9365 // Target of jump will eventually return to caller. 9366 // TailJump below removes the return address. 9367 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9368 match(TailCall jump_target method_oop ); 9369 9370 ins_cost(CALL_COST); 9371 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9372 ins_encode(form_jmpl(jump_target)); 9373 ins_pipe(tail_call); 9374 %} 9375 9376 9377 // Return Instruction 9378 instruct Ret() %{ 9379 match(Return); 9380 9381 // The epilogue node did the ret already. 9382 size(0); 9383 format %{ "! return" %} 9384 ins_encode(); 9385 ins_pipe(empty); 9386 %} 9387 9388 9389 // Tail Jump; remove the return address; jump to target. 9390 // TailCall above leaves the return address around. 9391 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9392 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9393 // "restore" before this instruction (in Epilogue), we need to materialize it 9394 // in %i0. 9395 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9396 match( TailJump jump_target ex_oop ); 9397 ins_cost(CALL_COST); 9398 format %{ "! discard R_O7\n\t" 9399 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9400 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9401 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9402 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9403 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9404 ins_pipe(tail_call); 9405 %} 9406 9407 // Create exception oop: created by stack-crawling runtime code. 9408 // Created exception is now available to this handler, and is setup 9409 // just prior to jumping to this handler. No code emitted. 9410 instruct CreateException( o0RegP ex_oop ) 9411 %{ 9412 match(Set ex_oop (CreateEx)); 9413 ins_cost(0); 9414 9415 size(0); 9416 // use the following format syntax 9417 format %{ "! exception oop is in R_O0; no code emitted" %} 9418 ins_encode(); 9419 ins_pipe(empty); 9420 %} 9421 9422 9423 // Rethrow exception: 9424 // The exception oop will come in the first argument position. 9425 // Then JUMP (not call) to the rethrow stub code. 9426 instruct RethrowException() 9427 %{ 9428 match(Rethrow); 9429 ins_cost(CALL_COST); 9430 9431 // use the following format syntax 9432 format %{ "Jmp rethrow_stub" %} 9433 ins_encode(enc_rethrow); 9434 ins_pipe(tail_call); 9435 %} 9436 9437 9438 // Die now 9439 instruct ShouldNotReachHere( ) 9440 %{ 9441 match(Halt); 9442 ins_cost(CALL_COST); 9443 9444 size(4); 9445 // Use the following format syntax 9446 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9447 ins_encode( form2_illtrap() ); 9448 ins_pipe(tail_call); 9449 %} 9450 9451 // ============================================================================ 9452 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9453 // array for an instance of the superklass. Set a hidden internal cache on a 9454 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9455 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9456 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9457 match(Set index (PartialSubtypeCheck sub super)); 9458 effect( KILL pcc, KILL o7 ); 9459 ins_cost(DEFAULT_COST*10); 9460 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9461 ins_encode( enc_PartialSubtypeCheck() ); 9462 ins_pipe(partial_subtype_check_pipe); 9463 %} 9464 9465 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9466 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9467 effect( KILL idx, KILL o7 ); 9468 ins_cost(DEFAULT_COST*10); 9469 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9470 ins_encode( enc_PartialSubtypeCheck() ); 9471 ins_pipe(partial_subtype_check_pipe); 9472 %} 9473 9474 9475 // ============================================================================ 9476 // inlined locking and unlocking 9477 9478 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9479 match(Set pcc (FastLock object box)); 9480 9481 effect(KILL scratch, TEMP scratch2); 9482 ins_cost(100); 9483 9484 size(4*112); // conservative overestimation ... 9485 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9486 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9487 ins_pipe(long_memory_op); 9488 %} 9489 9490 9491 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9492 match(Set pcc (FastUnlock object box)); 9493 effect(KILL scratch, TEMP scratch2); 9494 ins_cost(100); 9495 9496 size(4*120); // conservative overestimation ... 9497 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9498 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9499 ins_pipe(long_memory_op); 9500 %} 9501 9502 // Count and Base registers are fixed because the allocator cannot 9503 // kill unknown registers. The encodings are generic. 9504 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9505 match(Set dummy (ClearArray cnt base)); 9506 effect(TEMP temp, KILL ccr); 9507 ins_cost(300); 9508 format %{ "MOV $cnt,$temp\n" 9509 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9510 " BRge loop\t\t! Clearing loop\n" 9511 " STX G0,[$base+$temp]\t! delay slot" %} 9512 ins_encode( enc_Clear_Array(cnt, base, temp) ); 9513 ins_pipe(long_memory_op); 9514 %} 9515 9516 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9517 o7RegI tmp, flagsReg ccr) %{ 9518 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9519 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9520 ins_cost(300); 9521 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9522 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 9523 ins_pipe(long_memory_op); 9524 %} 9525 9526 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9527 o7RegI tmp, flagsReg ccr) %{ 9528 match(Set result (StrEquals (Binary str1 str2) cnt)); 9529 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9530 ins_cost(300); 9531 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 9532 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 9533 ins_pipe(long_memory_op); 9534 %} 9535 9536 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9537 o7RegI tmp2, flagsReg ccr) %{ 9538 match(Set result (AryEq ary1 ary2)); 9539 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9540 ins_cost(300); 9541 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9542 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 9543 ins_pipe(long_memory_op); 9544 %} 9545 9546 9547 //---------- Zeros Count Instructions ------------------------------------------ 9548 9549 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9550 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9551 match(Set dst (CountLeadingZerosI src)); 9552 effect(TEMP dst, TEMP tmp, KILL cr); 9553 9554 // x |= (x >> 1); 9555 // x |= (x >> 2); 9556 // x |= (x >> 4); 9557 // x |= (x >> 8); 9558 // x |= (x >> 16); 9559 // return (WORDBITS - popc(x)); 9560 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 9561 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 9562 "OR $dst,$tmp,$dst\n\t" 9563 "SRL $dst,2,$tmp\n\t" 9564 "OR $dst,$tmp,$dst\n\t" 9565 "SRL $dst,4,$tmp\n\t" 9566 "OR $dst,$tmp,$dst\n\t" 9567 "SRL $dst,8,$tmp\n\t" 9568 "OR $dst,$tmp,$dst\n\t" 9569 "SRL $dst,16,$tmp\n\t" 9570 "OR $dst,$tmp,$dst\n\t" 9571 "POPC $dst,$dst\n\t" 9572 "MOV 32,$tmp\n\t" 9573 "SUB $tmp,$dst,$dst" %} 9574 ins_encode %{ 9575 Register Rdst = $dst$$Register; 9576 Register Rsrc = $src$$Register; 9577 Register Rtmp = $tmp$$Register; 9578 __ srl(Rsrc, 1, Rtmp); 9579 __ srl(Rsrc, 0, Rdst); 9580 __ or3(Rdst, Rtmp, Rdst); 9581 __ srl(Rdst, 2, Rtmp); 9582 __ or3(Rdst, Rtmp, Rdst); 9583 __ srl(Rdst, 4, Rtmp); 9584 __ or3(Rdst, Rtmp, Rdst); 9585 __ srl(Rdst, 8, Rtmp); 9586 __ or3(Rdst, Rtmp, Rdst); 9587 __ srl(Rdst, 16, Rtmp); 9588 __ or3(Rdst, Rtmp, Rdst); 9589 __ popc(Rdst, Rdst); 9590 __ mov(BitsPerInt, Rtmp); 9591 __ sub(Rtmp, Rdst, Rdst); 9592 %} 9593 ins_pipe(ialu_reg); 9594 %} 9595 9596 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9597 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9598 match(Set dst (CountLeadingZerosL src)); 9599 effect(TEMP dst, TEMP tmp, KILL cr); 9600 9601 // x |= (x >> 1); 9602 // x |= (x >> 2); 9603 // x |= (x >> 4); 9604 // x |= (x >> 8); 9605 // x |= (x >> 16); 9606 // x |= (x >> 32); 9607 // return (WORDBITS - popc(x)); 9608 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 9609 "OR $src,$tmp,$dst\n\t" 9610 "SRLX $dst,2,$tmp\n\t" 9611 "OR $dst,$tmp,$dst\n\t" 9612 "SRLX $dst,4,$tmp\n\t" 9613 "OR $dst,$tmp,$dst\n\t" 9614 "SRLX $dst,8,$tmp\n\t" 9615 "OR $dst,$tmp,$dst\n\t" 9616 "SRLX $dst,16,$tmp\n\t" 9617 "OR $dst,$tmp,$dst\n\t" 9618 "SRLX $dst,32,$tmp\n\t" 9619 "OR $dst,$tmp,$dst\n\t" 9620 "POPC $dst,$dst\n\t" 9621 "MOV 64,$tmp\n\t" 9622 "SUB $tmp,$dst,$dst" %} 9623 ins_encode %{ 9624 Register Rdst = $dst$$Register; 9625 Register Rsrc = $src$$Register; 9626 Register Rtmp = $tmp$$Register; 9627 __ srlx(Rsrc, 1, Rtmp); 9628 __ or3( Rsrc, Rtmp, Rdst); 9629 __ srlx(Rdst, 2, Rtmp); 9630 __ or3( Rdst, Rtmp, Rdst); 9631 __ srlx(Rdst, 4, Rtmp); 9632 __ or3( Rdst, Rtmp, Rdst); 9633 __ srlx(Rdst, 8, Rtmp); 9634 __ or3( Rdst, Rtmp, Rdst); 9635 __ srlx(Rdst, 16, Rtmp); 9636 __ or3( Rdst, Rtmp, Rdst); 9637 __ srlx(Rdst, 32, Rtmp); 9638 __ or3( Rdst, Rtmp, Rdst); 9639 __ popc(Rdst, Rdst); 9640 __ mov(BitsPerLong, Rtmp); 9641 __ sub(Rtmp, Rdst, Rdst); 9642 %} 9643 ins_pipe(ialu_reg); 9644 %} 9645 9646 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ 9647 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9648 match(Set dst (CountTrailingZerosI src)); 9649 effect(TEMP dst, KILL cr); 9650 9651 // return popc(~x & (x - 1)); 9652 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 9653 "ANDN $dst,$src,$dst\n\t" 9654 "SRL $dst,R_G0,$dst\n\t" 9655 "POPC $dst,$dst" %} 9656 ins_encode %{ 9657 Register Rdst = $dst$$Register; 9658 Register Rsrc = $src$$Register; 9659 __ sub(Rsrc, 1, Rdst); 9660 __ andn(Rdst, Rsrc, Rdst); 9661 __ srl(Rdst, G0, Rdst); 9662 __ popc(Rdst, Rdst); 9663 %} 9664 ins_pipe(ialu_reg); 9665 %} 9666 9667 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ 9668 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9669 match(Set dst (CountTrailingZerosL src)); 9670 effect(TEMP dst, KILL cr); 9671 9672 // return popc(~x & (x - 1)); 9673 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 9674 "ANDN $dst,$src,$dst\n\t" 9675 "POPC $dst,$dst" %} 9676 ins_encode %{ 9677 Register Rdst = $dst$$Register; 9678 Register Rsrc = $src$$Register; 9679 __ sub(Rsrc, 1, Rdst); 9680 __ andn(Rdst, Rsrc, Rdst); 9681 __ popc(Rdst, Rdst); 9682 %} 9683 ins_pipe(ialu_reg); 9684 %} 9685 9686 9687 //---------- Population Count Instructions ------------------------------------- 9688 9689 instruct popCountI(iRegI dst, iRegI src) %{ 9690 predicate(UsePopCountInstruction); 9691 match(Set dst (PopCountI src)); 9692 9693 format %{ "POPC $src, $dst" %} 9694 ins_encode %{ 9695 __ popc($src$$Register, $dst$$Register); 9696 %} 9697 ins_pipe(ialu_reg); 9698 %} 9699 9700 // Note: Long.bitCount(long) returns an int. 9701 instruct popCountL(iRegI dst, iRegL src) %{ 9702 predicate(UsePopCountInstruction); 9703 match(Set dst (PopCountL src)); 9704 9705 format %{ "POPC $src, $dst" %} 9706 ins_encode %{ 9707 __ popc($src$$Register, $dst$$Register); 9708 %} 9709 ins_pipe(ialu_reg); 9710 %} 9711 9712 9713 // ============================================================================ 9714 //------------Bytes reverse-------------------------------------------------- 9715 9716 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 9717 match(Set dst (ReverseBytesI src)); 9718 9719 // Op cost is artificially doubled to make sure that load or store 9720 // instructions are preferred over this one which requires a spill 9721 // onto a stack slot. 9722 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9723 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9724 9725 ins_encode %{ 9726 __ set($src$$disp + STACK_BIAS, O7); 9727 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9728 %} 9729 ins_pipe( iload_mem ); 9730 %} 9731 9732 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 9733 match(Set dst (ReverseBytesL src)); 9734 9735 // Op cost is artificially doubled to make sure that load or store 9736 // instructions are preferred over this one which requires a spill 9737 // onto a stack slot. 9738 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9739 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9740 9741 ins_encode %{ 9742 __ set($src$$disp + STACK_BIAS, O7); 9743 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9744 %} 9745 ins_pipe( iload_mem ); 9746 %} 9747 9748 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 9749 match(Set dst (ReverseBytesUS src)); 9750 9751 // Op cost is artificially doubled to make sure that load or store 9752 // instructions are preferred over this one which requires a spill 9753 // onto a stack slot. 9754 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9755 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 9756 9757 ins_encode %{ 9758 // the value was spilled as an int so bias the load 9759 __ set($src$$disp + STACK_BIAS + 2, O7); 9760 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9761 %} 9762 ins_pipe( iload_mem ); 9763 %} 9764 9765 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 9766 match(Set dst (ReverseBytesS src)); 9767 9768 // Op cost is artificially doubled to make sure that load or store 9769 // instructions are preferred over this one which requires a spill 9770 // onto a stack slot. 9771 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9772 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 9773 9774 ins_encode %{ 9775 // the value was spilled as an int so bias the load 9776 __ set($src$$disp + STACK_BIAS + 2, O7); 9777 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9778 %} 9779 ins_pipe( iload_mem ); 9780 %} 9781 9782 // Load Integer reversed byte order 9783 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 9784 match(Set dst (ReverseBytesI (LoadI src))); 9785 9786 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9787 size(4); 9788 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9789 9790 ins_encode %{ 9791 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9792 %} 9793 ins_pipe(iload_mem); 9794 %} 9795 9796 // Load Long - aligned and reversed 9797 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 9798 match(Set dst (ReverseBytesL (LoadL src))); 9799 9800 ins_cost(MEMORY_REF_COST); 9801 size(4); 9802 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9803 9804 ins_encode %{ 9805 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9806 %} 9807 ins_pipe(iload_mem); 9808 %} 9809 9810 // Load unsigned short / char reversed byte order 9811 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 9812 match(Set dst (ReverseBytesUS (LoadUS src))); 9813 9814 ins_cost(MEMORY_REF_COST); 9815 size(4); 9816 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 9817 9818 ins_encode %{ 9819 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9820 %} 9821 ins_pipe(iload_mem); 9822 %} 9823 9824 // Load short reversed byte order 9825 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 9826 match(Set dst (ReverseBytesS (LoadS src))); 9827 9828 ins_cost(MEMORY_REF_COST); 9829 size(4); 9830 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 9831 9832 ins_encode %{ 9833 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9834 %} 9835 ins_pipe(iload_mem); 9836 %} 9837 9838 // Store Integer reversed byte order 9839 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 9840 match(Set dst (StoreI dst (ReverseBytesI src))); 9841 9842 ins_cost(MEMORY_REF_COST); 9843 size(4); 9844 format %{ "STWA $src, $dst\t!asi=primary_little" %} 9845 9846 ins_encode %{ 9847 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9848 %} 9849 ins_pipe(istore_mem_reg); 9850 %} 9851 9852 // Store Long reversed byte order 9853 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 9854 match(Set dst (StoreL dst (ReverseBytesL src))); 9855 9856 ins_cost(MEMORY_REF_COST); 9857 size(4); 9858 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9859 9860 ins_encode %{ 9861 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9862 %} 9863 ins_pipe(istore_mem_reg); 9864 %} 9865 9866 // Store unsighed short/char reversed byte order 9867 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 9868 match(Set dst (StoreC dst (ReverseBytesUS src))); 9869 9870 ins_cost(MEMORY_REF_COST); 9871 size(4); 9872 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9873 9874 ins_encode %{ 9875 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9876 %} 9877 ins_pipe(istore_mem_reg); 9878 %} 9879 9880 // Store short reversed byte order 9881 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 9882 match(Set dst (StoreC dst (ReverseBytesS src))); 9883 9884 ins_cost(MEMORY_REF_COST); 9885 size(4); 9886 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9887 9888 ins_encode %{ 9889 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9890 %} 9891 ins_pipe(istore_mem_reg); 9892 %} 9893 9894 //----------PEEPHOLE RULES----------------------------------------------------- 9895 // These must follow all instruction definitions as they use the names 9896 // defined in the instructions definitions. 9897 // 9898 // peepmatch ( root_instr_name [preceding_instruction]* ); 9899 // 9900 // peepconstraint %{ 9901 // (instruction_number.operand_name relational_op instruction_number.operand_name 9902 // [, ...] ); 9903 // // instruction numbers are zero-based using left to right order in peepmatch 9904 // 9905 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9906 // // provide an instruction_number.operand_name for each operand that appears 9907 // // in the replacement instruction's match rule 9908 // 9909 // ---------VM FLAGS--------------------------------------------------------- 9910 // 9911 // All peephole optimizations can be turned off using -XX:-OptoPeephole 9912 // 9913 // Each peephole rule is given an identifying number starting with zero and 9914 // increasing by one in the order seen by the parser. An individual peephole 9915 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9916 // on the command-line. 9917 // 9918 // ---------CURRENT LIMITATIONS---------------------------------------------- 9919 // 9920 // Only match adjacent instructions in same basic block 9921 // Only equality constraints 9922 // Only constraints between operands, not (0.dest_reg == EAX_enc) 9923 // Only one replacement instruction 9924 // 9925 // ---------EXAMPLE---------------------------------------------------------- 9926 // 9927 // // pertinent parts of existing instructions in architecture description 9928 // instruct movI(eRegI dst, eRegI src) %{ 9929 // match(Set dst (CopyI src)); 9930 // %} 9931 // 9932 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9933 // match(Set dst (AddI dst src)); 9934 // effect(KILL cr); 9935 // %} 9936 // 9937 // // Change (inc mov) to lea 9938 // peephole %{ 9939 // // increment preceeded by register-register move 9940 // peepmatch ( incI_eReg movI ); 9941 // // require that the destination register of the increment 9942 // // match the destination register of the move 9943 // peepconstraint ( 0.dst == 1.dst ); 9944 // // construct a replacement instruction that sets 9945 // // the destination to ( move's source register + one ) 9946 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9947 // %} 9948 // 9949 9950 // // Change load of spilled value to only a spill 9951 // instruct storeI(memory mem, eRegI src) %{ 9952 // match(Set mem (StoreI mem src)); 9953 // %} 9954 // 9955 // instruct loadI(eRegI dst, memory mem) %{ 9956 // match(Set dst (LoadI mem)); 9957 // %} 9958 // 9959 // peephole %{ 9960 // peepmatch ( loadI storeI ); 9961 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9962 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9963 // %} 9964 9965 //----------SMARTSPILL RULES--------------------------------------------------- 9966 // These must follow all instruction definitions as they use the names 9967 // defined in the instructions definitions. 9968 // 9969 // SPARC will probably not have any of these rules due to RISC instruction set. 9970 9971 //----------PIPELINE----------------------------------------------------------- 9972 // Rules which define the behavior of the target architectures pipeline.