650
651
652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
653 assert(n->rule() != loadUB_rule, "");
654
655 intptr_t offset = 0;
656 Node* addr = n->in(2);
657 assert(addr->bottom_type()->isa_oopptr() == atype, "");
658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
659 Node* a = addr->in(2/*AddPNode::Address*/);
660 Node* o = addr->in(3/*AddPNode::Offset*/);
661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
662 atype = a->bottom_type()->is_ptr()->add_offset(offset);
663 assert(atype->isa_oop_ptr(), "still an oop");
664 }
665 offset = atype->is_ptr()->_offset;
666 if (offset != Type::OffsetBot) offset += disp32;
667 return offset;
668 }
669
670 // Standard Sparc opcode form2 field breakdown
671 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
672 f0 &= (1<<19)-1; // Mask displacement to 19 bits
673 int op = (f30 << 30) |
674 (f29 << 29) |
675 (f25 << 25) |
676 (f22 << 22) |
677 (f20 << 20) |
678 (f19 << 19) |
679 (f0 << 0);
680 cbuf.insts()->emit_int32(op);
681 }
682
683 // Standard Sparc opcode form2 field breakdown
684 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
685 f0 >>= 10; // Drop 10 bits
686 f0 &= (1<<22)-1; // Mask displacement to 22 bits
687 int op = (f30 << 30) |
688 (f25 << 25) |
689 (f22 << 22) |
991 __ mov(G1, G5);
992 __ sllx(G1, 32, G1);
993 __ or3(G1, G5, G1);
994 __ mov(G1, G5);
995 __ stx(G1, SP, 0x40);
996 __ stx(G1, SP, 0x48);
997 __ stx(G1, SP, 0x50);
998 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
999 #endif // _LP64
1000 }
1001 #endif /*ASSERT*/
1002 }
1003
1004 //=============================================================================
1005 // REQUIRED FUNCTIONALITY for encoding
1006 void emit_lo(CodeBuffer &cbuf, int val) { }
1007 void emit_hi(CodeBuffer &cbuf, int val) { }
1008
1009
1010 //=============================================================================
1011
1012 #ifndef PRODUCT
1013 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1014 Compile* C = ra_->C;
1015
1016 for (int i = 0; i < OptoPrologueNops; i++) {
1017 st->print_cr("NOP"); st->print("\t");
1018 }
1019
1020 if( VerifyThread ) {
1021 st->print_cr("Verify_Thread"); st->print("\t");
1022 }
1023
1024 size_t framesize = C->frame_slots() << LogBytesPerInt;
1025
1026 // Calls to C2R adapters often do not accept exceptional returns.
1027 // We require that their callers must bang for them. But be careful, because
1028 // some VM calls (such as call site linkage) can use several kilobytes of
1029 // stack. But the stack safety zone should account for that.
1030 // See bugs 4446381, 4468289, 4497237.
2230 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2231 MacroAssembler _masm(&cbuf);
2232 Label &L = *($labl$$label);
2233 Assembler::Predict predict_taken =
2234 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2235
2236 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2237 __ delayed()->nop();
2238 %}
2239
2240 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2241 MacroAssembler _masm(&cbuf);
2242 Label &L = *($labl$$label);
2243 Assembler::Predict predict_taken =
2244 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2245
2246 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2247 __ delayed()->nop();
2248 %}
2249
2250 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2251 MacroAssembler _masm(&cbuf);
2252
2253 Register switch_reg = as_Register($switch_val$$reg);
2254 Register table_reg = O7;
2255
2256 address table_base = __ address_table_constant(_index2label);
2257 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2258
2259 // Move table address into a register.
2260 __ set(table_base, table_reg, rspec);
2261
2262 // Jump to base address + switch value
2263 __ ld_ptr(table_reg, switch_reg, table_reg);
2264 __ jmp(table_reg, G0);
2265 __ delayed()->nop();
2266
2267 %}
2268
2269 enc_class enc_ba( Label labl ) %{
2270 MacroAssembler _masm(&cbuf);
2271 Label &L = *($labl$$label);
2272 __ ba(false, L);
2273 __ delayed()->nop();
2274 %}
2275
2276 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2277 MacroAssembler _masm(&cbuf);
2278 Label &L = *$labl$$label;
2279 Assembler::Predict predict_taken =
2280 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2281
2282 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2283 __ delayed()->nop();
2284 %}
2285
2286 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2287 int op = (Assembler::arith_op << 30) |
2288 ($dst$$reg << 25) |
2367 (1 << 18) | // cc2 bit for 'icc'
2368 ($primary << 14) |
2369 (0 << 13) | // select register move
2370 (0 << 11) | // cc1, cc0 bits for 'icc'
2371 ($src$$reg << 0);
2372 cbuf.insts()->emit_int32(op);
2373 %}
2374
2375 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2376 int op = (Assembler::arith_op << 30) |
2377 ($dst$$reg << 25) |
2378 (Assembler::movcc_op3 << 19) |
2379 (6 << 16) | // cc2 bit for 'xcc'
2380 ($primary << 14) |
2381 (0 << 13) | // select register move
2382 (0 << 11) | // cc1, cc0 bits for 'icc'
2383 ($src$$reg << 0);
2384 cbuf.insts()->emit_int32(op);
2385 %}
2386
2387 // Utility encoding for loading a 64 bit Pointer into a register
2388 // The 64 bit pointer is stored in the generated code stream
2389 enc_class SetPtr( immP src, iRegP rd ) %{
2390 Register dest = reg_to_register_object($rd$$reg);
2391 MacroAssembler _masm(&cbuf);
2392 // [RGV] This next line should be generated from ADLC
2393 if ( _opnds[1]->constant_is_oop() ) {
2394 intptr_t val = $src$$constant;
2395 __ set_oop_constant((jobject)val, dest);
2396 } else { // non-oop pointers, e.g. card mark base, heap top
2397 __ set($src$$constant, dest);
2398 }
2399 %}
2400
2401 enc_class Set13( immI13 src, iRegI rd ) %{
2402 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2403 %}
2404
2405 enc_class SetHi22( immI src, iRegI rd ) %{
2406 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2407 %}
2408
2409 enc_class Set32( immI src, iRegI rd ) %{
2410 MacroAssembler _masm(&cbuf);
2411 __ set($src$$constant, reg_to_register_object($rd$$reg));
2412 %}
2413
2414 enc_class SetNull( iRegI rd ) %{
2415 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2416 %}
2417
2418 enc_class call_epilog %{
2419 if( VerifyStackAtCalls ) {
2420 MacroAssembler _masm(&cbuf);
2421 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2422 Register temp_reg = G3;
2423 __ add(SP, framesize, temp_reg);
2424 __ cmp(temp_reg, FP);
2425 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2426 }
2427 %}
2428
2429 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2430 // to G1 so the register allocator will not have to deal with the misaligned register
2431 // pair.
2432 enc_class adjust_long_from_native_call %{
2433 #ifndef _LP64
2434 if (returns_long()) {
2435 // sllx O0,32,O0
2436 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2437 // srl O1,0,O1
2761 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2762 Register Rres = reg_to_register_object($res$$reg);
2763
2764 MacroAssembler _masm(&cbuf);
2765 __ mov(1, Rres);
2766 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2767 %}
2768
2769 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2770 MacroAssembler _masm(&cbuf);
2771 Register Rdst = reg_to_register_object($dst$$reg);
2772 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2773 : reg_to_DoubleFloatRegister_object($src1$$reg);
2774 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2775 : reg_to_DoubleFloatRegister_object($src2$$reg);
2776
2777 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2778 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2779 %}
2780
2781 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2782 MacroAssembler _masm(&cbuf);
2783 Register dest = reg_to_register_object($dst$$reg);
2784 Register temp = reg_to_register_object($tmp$$reg);
2785 __ set64( $src$$constant, dest, temp );
2786 %}
2787
2788 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2789 // Load a constant replicated "count" times with width "width"
2790 int bit_width = $width$$constant * 8;
2791 jlong elt_val = $src$$constant;
2792 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2793 jlong val = elt_val;
2794 for (int i = 0; i < $count$$constant - 1; i++) {
2795 val <<= bit_width;
2796 val |= elt_val;
2797 }
2798 jdouble dval = *(jdouble*)&val; // coerce to double type
2799 MacroAssembler _masm(&cbuf);
2800 address double_address = __ double_constant(dval);
2801 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2802 AddressLiteral addrlit(double_address, rspec);
2803
2804 __ sethi(addrlit, $tmp$$Register);
2805 // XXX This is a quick fix for 6833573.
2806 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2807 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2808 %}
2809
2810 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2811 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2812 MacroAssembler _masm(&cbuf);
2813 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2814 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2815 Register base_pointer_arg = reg_to_register_object($base$$reg);
2816
2817 Label loop;
2818 __ mov(nof_bytes_arg, nof_bytes_tmp);
2819
2820 // Loop and clear, walking backwards through the array.
2821 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2822 __ bind(loop);
2823 __ deccc(nof_bytes_tmp, 8);
2824 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2825 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2826 // %%%% this mini-loop must not cross a cache boundary!
2827 %}
2828
2829
3599 // Long Immediate: 13-bit minus 7
3600 operand immL13m7() %{
3601 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3602 match(ConL);
3603 op_cost(0);
3604
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 // Long Immediate: low 32-bit mask
3610 operand immL_32bits() %{
3611 predicate(n->get_long() == 0xFFFFFFFFL);
3612 match(ConL);
3613 op_cost(0);
3614
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 // Double Immediate
3620 operand immD() %{
3621 match(ConD);
3622
3623 op_cost(40);
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 operand immD0() %{
3629 #ifdef _LP64
3630 // on 64-bit architectures this comparision is faster
3631 predicate(jlong_cast(n->getd()) == 0);
3632 #else
3633 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3634 #endif
3635 match(ConD);
3636
3637 op_cost(0);
3638 format %{ %}
5964 %}
5965
5966 // Load Constant
5967 instruct loadConI( iRegI dst, immI src ) %{
5968 match(Set dst src);
5969 ins_cost(DEFAULT_COST * 3/2);
5970 format %{ "SET $src,$dst" %}
5971 ins_encode( Set32(src, dst) );
5972 ins_pipe(ialu_hi_lo_reg);
5973 %}
5974
5975 instruct loadConI13( iRegI dst, immI13 src ) %{
5976 match(Set dst src);
5977
5978 size(4);
5979 format %{ "MOV $src,$dst" %}
5980 ins_encode( Set13( src, dst ) );
5981 ins_pipe(ialu_imm);
5982 %}
5983
5984 instruct loadConP(iRegP dst, immP src) %{
5985 match(Set dst src);
5986 ins_cost(DEFAULT_COST * 3/2);
5987 format %{ "SET $src,$dst\t!ptr" %}
5988 // This rule does not use "expand" unlike loadConI because then
5989 // the result type is not known to be an Oop. An ADLC
5990 // enhancement will be needed to make that work - not worth it!
5991
5992 ins_encode( SetPtr( src, dst ) );
5993 ins_pipe(loadConP);
5994
5995 %}
5996
5997 instruct loadConP0(iRegP dst, immP0 src) %{
5998 match(Set dst src);
5999
6000 size(4);
6001 format %{ "CLR $dst\t!ptr" %}
6002 ins_encode( SetNull( dst ) );
6003 ins_pipe(ialu_imm);
6004 %}
6005
6006 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6007 match(Set dst src);
6008 ins_cost(DEFAULT_COST);
6009 format %{ "SET $src,$dst\t!ptr" %}
6010 ins_encode %{
6011 AddressLiteral polling_page(os::get_polling_page());
6012 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6013 %}
6014 ins_pipe(loadConP_poll);
6015 %}
6016
6017 instruct loadConN0(iRegN dst, immN0 src) %{
6018 match(Set dst src);
6019
6020 size(4);
6021 format %{ "CLR $dst\t! compressed NULL ptr" %}
6022 ins_encode( SetNull( dst ) );
6023 ins_pipe(ialu_imm);
6024 %}
6025
6026 instruct loadConN(iRegN dst, immN src) %{
6027 match(Set dst src);
6028 ins_cost(DEFAULT_COST * 3/2);
6029 format %{ "SET $src,$dst\t! compressed ptr" %}
6030 ins_encode %{
6031 Register dst = $dst$$Register;
6032 __ set_narrow_oop((jobject)$src$$constant, dst);
6033 %}
6034 ins_pipe(ialu_hi_lo_reg);
6035 %}
6036
6037 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6038 // %%% maybe this should work like loadConD
6039 match(Set dst src);
6040 effect(KILL tmp);
6041 ins_cost(DEFAULT_COST * 4);
6042 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6043 ins_encode( LdImmL(src, dst, tmp) );
6044 ins_pipe(loadConL);
6045 %}
6046
6047 instruct loadConL0( iRegL dst, immL0 src ) %{
6048 match(Set dst src);
6049 ins_cost(DEFAULT_COST);
6050 size(4);
6051 format %{ "CLR $dst\t! long" %}
6052 ins_encode( Set13( src, dst ) );
6053 ins_pipe(ialu_imm);
6054 %}
6055
6056 instruct loadConL13( iRegL dst, immL13 src ) %{
6057 match(Set dst src);
6058 ins_cost(DEFAULT_COST * 2);
6059
6060 size(4);
6061 format %{ "MOV $src,$dst\t! long" %}
6062 ins_encode( Set13( src, dst ) );
6063 ins_pipe(ialu_imm);
6064 %}
6065
6066 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6067 match(Set dst src);
6068 effect(KILL tmp);
6069
6070 #ifdef _LP64
6071 size(8*4);
6072 #else
6073 size(2*4);
6074 #endif
6075
6076 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6077 "LDF [$tmp+lo(&$src)],$dst" %}
6078 ins_encode %{
6079 address float_address = __ float_constant($src$$constant);
6080 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6081 AddressLiteral addrlit(float_address, rspec);
6082
6083 __ sethi(addrlit, $tmp$$Register);
6084 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6085 %}
6086 ins_pipe(loadConFD);
6087 %}
6088
6089 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6090 match(Set dst src);
6091 effect(KILL tmp);
6092
6093 #ifdef _LP64
6094 size(8*4);
6095 #else
6096 size(2*4);
6097 #endif
6098
6099 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6100 "LDDF [$tmp+lo(&$src)],$dst" %}
6101 ins_encode %{
6102 address double_address = __ double_constant($src$$constant);
6103 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6104 AddressLiteral addrlit(double_address, rspec);
6105
6106 __ sethi(addrlit, $tmp$$Register);
6107 // XXX This is a quick fix for 6833573.
6108 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6109 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6110 %}
6111 ins_pipe(loadConFD);
6112 %}
6113
6114 // Prefetch instructions.
6115 // Must be safe to execute with invalid address (cannot fault).
6116
6117 instruct prefetchr( memory mem ) %{
6118 match( PrefetchRead mem );
6119 ins_cost(MEMORY_REF_COST);
6120
6121 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6122 opcode(Assembler::prefetch_op3);
6123 ins_encode( form3_mem_prefetch_read( mem ) );
6124 ins_pipe(iload_mem);
6125 %}
6126
6127 instruct prefetchw( memory mem ) %{
6128 predicate(AllocatePrefetchStyle != 3 );
6129 match( PrefetchWrite mem );
8541 "OR $dst,O7,$dst\n\t"
8542 "SRLX $dst,16,O7\n\t"
8543 "OR $dst,O7,$dst\n\t"
8544 "SRLX $dst,32,O7\n\t"
8545 "OR $dst,O7,$dst\t! replicate8B" %}
8546 ins_encode( enc_repl8b(src, dst));
8547 ins_pipe(ialu_reg);
8548 %}
8549
8550 // Replicate scalar to packed byte values in Double register
8551 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8552 match(Set dst (Replicate8B src));
8553 expand %{
8554 iRegL tmp;
8555 Repl8B_reg_helper(tmp, src);
8556 regL_to_stkD(dst, tmp);
8557 %}
8558 %}
8559
8560 // Replicate scalar constant to packed byte values in Double register
8561 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8562 match(Set dst (Replicate8B src));
8563 #ifdef _LP64
8564 size(36);
8565 #else
8566 size(8);
8567 #endif
8568 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8569 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8570 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8571 ins_pipe(loadConFD);
8572 %}
8573
8574 // Replicate scalar to packed char values into stack slot
8575 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8576 effect(DEF dst, USE src);
8577 format %{ "SLLX $src,48,$dst\n\t"
8578 "SRLX $dst,16,O7\n\t"
8579 "OR $dst,O7,$dst\n\t"
8580 "SRLX $dst,32,O7\n\t"
8581 "OR $dst,O7,$dst\t! replicate4C" %}
8582 ins_encode( enc_repl4s(src, dst) );
8583 ins_pipe(ialu_reg);
8584 %}
8585
8586 // Replicate scalar to packed char values into stack slot
8587 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8588 match(Set dst (Replicate4C src));
8589 expand %{
8590 iRegL tmp;
8591 Repl4C_reg_helper(tmp, src);
8592 regL_to_stkD(dst, tmp);
8593 %}
8594 %}
8595
8596 // Replicate scalar constant to packed char values in Double register
8597 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8598 match(Set dst (Replicate4C src));
8599 #ifdef _LP64
8600 size(36);
8601 #else
8602 size(8);
8603 #endif
8604 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8605 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8606 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8607 ins_pipe(loadConFD);
8608 %}
8609
8610 // Replicate scalar to packed short values into stack slot
8611 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8612 effect(DEF dst, USE src);
8613 format %{ "SLLX $src,48,$dst\n\t"
8614 "SRLX $dst,16,O7\n\t"
8615 "OR $dst,O7,$dst\n\t"
8616 "SRLX $dst,32,O7\n\t"
8617 "OR $dst,O7,$dst\t! replicate4S" %}
8618 ins_encode( enc_repl4s(src, dst) );
8619 ins_pipe(ialu_reg);
8620 %}
8621
8622 // Replicate scalar to packed short values into stack slot
8623 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8624 match(Set dst (Replicate4S src));
8625 expand %{
8626 iRegL tmp;
8627 Repl4S_reg_helper(tmp, src);
8628 regL_to_stkD(dst, tmp);
8629 %}
8630 %}
8631
8632 // Replicate scalar constant to packed short values in Double register
8633 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8634 match(Set dst (Replicate4S src));
8635 #ifdef _LP64
8636 size(36);
8637 #else
8638 size(8);
8639 #endif
8640 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8641 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8642 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8643 ins_pipe(loadConFD);
8644 %}
8645
8646 // Replicate scalar to packed int values in Double register
8647 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8648 effect(DEF dst, USE src);
8649 format %{ "SLLX $src,32,$dst\n\t"
8650 "SRLX $dst,32,O7\n\t"
8651 "OR $dst,O7,$dst\t! replicate2I" %}
8652 ins_encode( enc_repl2i(src, dst));
8653 ins_pipe(ialu_reg);
8654 %}
8655
8656 // Replicate scalar to packed int values in Double register
8657 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8658 match(Set dst (Replicate2I src));
8659 expand %{
8660 iRegL tmp;
8661 Repl2I_reg_helper(tmp, src);
8662 regL_to_stkD(dst, tmp);
8663 %}
8664 %}
8665
8666 // Replicate scalar zero constant to packed int values in Double register
8667 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8668 match(Set dst (Replicate2I src));
8669 #ifdef _LP64
8670 size(36);
8671 #else
8672 size(8);
8673 #endif
8674 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8675 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8676 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8677 ins_pipe(loadConFD);
8678 %}
8679
8680 //----------Control Flow Instructions------------------------------------------
8681 // Compare Instructions
8682 // Compare Integers
8683 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8684 match(Set icc (CmpI op1 op2));
8685 effect( DEF icc, USE op1, USE op2 );
8686
8687 size(4);
8688 format %{ "CMP $op1,$op2" %}
8689 opcode(Assembler::subcc_op3, Assembler::arith_op);
8690 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8691 ins_pipe(ialu_cconly_reg_reg);
8692 %}
8693
8694 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8695 match(Set icc (CmpU op1 op2));
8696
8912
8913 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8914 match(Set dst (CmpD3 src1 src2));
8915 effect(KILL fcc0);
8916 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8917 format %{ "dcmpl $dst,$src1,$src2" %}
8918 // Primary = double (not float)
8919 opcode( false );
8920 ins_encode( floating_cmp( dst, src1, src2 ) );
8921 ins_pipe( floating_cmp );
8922 %}
8923
8924 //----------Branches---------------------------------------------------------
8925 // Jump
8926 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8927 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8928 match(Jump switch_val);
8929
8930 ins_cost(350);
8931
8932 format %{ "SETHI [hi(table_base)],O7\n\t"
8933 "ADD O7, lo(table_base), O7\n\t"
8934 "LD [O7+$switch_val], O7\n\t"
8935 "JUMP O7"
8936 %}
8937 ins_encode( jump_enc( switch_val, table) );
8938 ins_pc_relative(1);
8939 ins_pipe(ialu_reg_reg);
8940 %}
8941
8942 // Direct Branch. Use V8 version with longer range.
8943 instruct branch(label labl) %{
8944 match(Goto);
8945 effect(USE labl);
8946
8947 size(8);
8948 ins_cost(BRANCH_COST);
8949 format %{ "BA $labl" %}
8950 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8951 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8952 ins_encode( enc_ba( labl ) );
8953 ins_pc_relative(1);
8954 ins_pipe(br);
8955 %}
8956
8957 // Conditional Direct Branch
|
650
651
652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
653 assert(n->rule() != loadUB_rule, "");
654
655 intptr_t offset = 0;
656 Node* addr = n->in(2);
657 assert(addr->bottom_type()->isa_oopptr() == atype, "");
658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
659 Node* a = addr->in(2/*AddPNode::Address*/);
660 Node* o = addr->in(3/*AddPNode::Offset*/);
661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
662 atype = a->bottom_type()->is_ptr()->add_offset(offset);
663 assert(atype->isa_oop_ptr(), "still an oop");
664 }
665 offset = atype->is_ptr()->_offset;
666 if (offset != Type::OffsetBot) offset += disp32;
667 return offset;
668 }
669
670 static inline jdouble replicate_immI(int con, int count, int width) {
671 // Load a constant replicated "count" times with width "width"
672 int bit_width = width * 8;
673 jlong elt_val = con;
674 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
675 jlong val = elt_val;
676 for (int i = 0; i < count - 1; i++) {
677 val <<= bit_width;
678 val |= elt_val;
679 }
680 jdouble dval = *((jdouble*) &val); // coerce to double type
681 return dval;
682 }
683
684 // Standard Sparc opcode form2 field breakdown
685 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
686 f0 &= (1<<19)-1; // Mask displacement to 19 bits
687 int op = (f30 << 30) |
688 (f29 << 29) |
689 (f25 << 25) |
690 (f22 << 22) |
691 (f20 << 20) |
692 (f19 << 19) |
693 (f0 << 0);
694 cbuf.insts()->emit_int32(op);
695 }
696
697 // Standard Sparc opcode form2 field breakdown
698 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
699 f0 >>= 10; // Drop 10 bits
700 f0 &= (1<<22)-1; // Mask displacement to 22 bits
701 int op = (f30 << 30) |
702 (f25 << 25) |
703 (f22 << 22) |
1005 __ mov(G1, G5);
1006 __ sllx(G1, 32, G1);
1007 __ or3(G1, G5, G1);
1008 __ mov(G1, G5);
1009 __ stx(G1, SP, 0x40);
1010 __ stx(G1, SP, 0x48);
1011 __ stx(G1, SP, 0x50);
1012 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1013 #endif // _LP64
1014 }
1015 #endif /*ASSERT*/
1016 }
1017
1018 //=============================================================================
1019 // REQUIRED FUNCTIONALITY for encoding
1020 void emit_lo(CodeBuffer &cbuf, int val) { }
1021 void emit_hi(CodeBuffer &cbuf, int val) { }
1022
1023
1024 //=============================================================================
1025 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1026
1027 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1028 emit_constant_table(cbuf);
1029 MacroAssembler _masm(&cbuf);
1030
1031 Register r = as_Register(ra_->get_encode(this));
1032 CodeSection* cs = __ code()->consts();
1033 int consts_size = cs->align_at_start(cs->size());
1034
1035 if (UseRDPCForConstantTableBase) {
1036 int offset = __ offset();
1037 int disp;
1038
1039 // If the displacement from the current PC to the constant table
1040 // base fits into simm13 we set the constant table base to the
1041 // current PC.
1042 if (__ is_simm13(-(consts_size + offset))) {
1043 set_table_base_offset(-(consts_size + offset));
1044 disp = 0;
1045 } else {
1046 // If the offset of the top constant (last entry in the table)
1047 // fits into simm13 we set the constant table base to the actual
1048 // table base.
1049 if (__ is_simm13(top_constant_offset())) {
1050 set_table_base_offset(0);
1051 disp = consts_size + offset;
1052 } else {
1053 // Otherwise we set the constant table base in the middle of the
1054 // constant table.
1055 int half_consts_size = consts_size / 2;
1056 assert(half_consts_size * 2 == consts_size, "sanity");
1057 set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1058 disp = half_consts_size + offset;
1059 }
1060 }
1061
1062 __ get_pc(r);
1063
1064 if (disp != 0) {
1065 assert(r != O7, "need temporary");
1066 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1067 }
1068 }
1069 else {
1070 // Materialize the constant table base.
1071 // Set the constant table base in the middle of the constant
1072 // table.
1073 int half_consts_size = consts_size / 2;
1074 assert(half_consts_size * 2 == consts_size, "sanity");
1075 set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1076
1077 address baseaddr = cs->start() + half_consts_size;
1078 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1079 AddressLiteral base(baseaddr, rspec);
1080 __ set(base, r);
1081 }
1082 }
1083
1084 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1085 Unimplemented();
1086 return 0;
1087 }
1088
1089 #ifndef PRODUCT
1090 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1091 char reg[128];
1092 ra_->dump_register(this, reg);
1093 if (UseRDPCForConstantTableBase) {
1094 st->print("RDPC %s\t! constant table base", reg);
1095 } else {
1096 st->print("SET &constanttable,%s\t! constant table base", reg);
1097 }
1098 }
1099 #endif
1100
1101
1102 //=============================================================================
1103
1104 #ifndef PRODUCT
1105 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1106 Compile* C = ra_->C;
1107
1108 for (int i = 0; i < OptoPrologueNops; i++) {
1109 st->print_cr("NOP"); st->print("\t");
1110 }
1111
1112 if( VerifyThread ) {
1113 st->print_cr("Verify_Thread"); st->print("\t");
1114 }
1115
1116 size_t framesize = C->frame_slots() << LogBytesPerInt;
1117
1118 // Calls to C2R adapters often do not accept exceptional returns.
1119 // We require that their callers must bang for them. But be careful, because
1120 // some VM calls (such as call site linkage) can use several kilobytes of
1121 // stack. But the stack safety zone should account for that.
1122 // See bugs 4446381, 4468289, 4497237.
2322 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2323 MacroAssembler _masm(&cbuf);
2324 Label &L = *($labl$$label);
2325 Assembler::Predict predict_taken =
2326 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2327
2328 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2329 __ delayed()->nop();
2330 %}
2331
2332 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2333 MacroAssembler _masm(&cbuf);
2334 Label &L = *($labl$$label);
2335 Assembler::Predict predict_taken =
2336 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2337
2338 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2339 __ delayed()->nop();
2340 %}
2341
2342 enc_class enc_ba( Label labl ) %{
2343 MacroAssembler _masm(&cbuf);
2344 Label &L = *($labl$$label);
2345 __ ba(false, L);
2346 __ delayed()->nop();
2347 %}
2348
2349 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2350 MacroAssembler _masm(&cbuf);
2351 Label &L = *$labl$$label;
2352 Assembler::Predict predict_taken =
2353 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2354
2355 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2356 __ delayed()->nop();
2357 %}
2358
2359 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2360 int op = (Assembler::arith_op << 30) |
2361 ($dst$$reg << 25) |
2440 (1 << 18) | // cc2 bit for 'icc'
2441 ($primary << 14) |
2442 (0 << 13) | // select register move
2443 (0 << 11) | // cc1, cc0 bits for 'icc'
2444 ($src$$reg << 0);
2445 cbuf.insts()->emit_int32(op);
2446 %}
2447
2448 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2449 int op = (Assembler::arith_op << 30) |
2450 ($dst$$reg << 25) |
2451 (Assembler::movcc_op3 << 19) |
2452 (6 << 16) | // cc2 bit for 'xcc'
2453 ($primary << 14) |
2454 (0 << 13) | // select register move
2455 (0 << 11) | // cc1, cc0 bits for 'icc'
2456 ($src$$reg << 0);
2457 cbuf.insts()->emit_int32(op);
2458 %}
2459
2460 enc_class Set13( immI13 src, iRegI rd ) %{
2461 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2462 %}
2463
2464 enc_class SetHi22( immI src, iRegI rd ) %{
2465 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2466 %}
2467
2468 enc_class Set32( immI src, iRegI rd ) %{
2469 MacroAssembler _masm(&cbuf);
2470 __ set($src$$constant, reg_to_register_object($rd$$reg));
2471 %}
2472
2473 enc_class call_epilog %{
2474 if( VerifyStackAtCalls ) {
2475 MacroAssembler _masm(&cbuf);
2476 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2477 Register temp_reg = G3;
2478 __ add(SP, framesize, temp_reg);
2479 __ cmp(temp_reg, FP);
2480 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2481 }
2482 %}
2483
2484 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2485 // to G1 so the register allocator will not have to deal with the misaligned register
2486 // pair.
2487 enc_class adjust_long_from_native_call %{
2488 #ifndef _LP64
2489 if (returns_long()) {
2490 // sllx O0,32,O0
2491 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2492 // srl O1,0,O1
2816 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2817 Register Rres = reg_to_register_object($res$$reg);
2818
2819 MacroAssembler _masm(&cbuf);
2820 __ mov(1, Rres);
2821 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2822 %}
2823
2824 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2825 MacroAssembler _masm(&cbuf);
2826 Register Rdst = reg_to_register_object($dst$$reg);
2827 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2828 : reg_to_DoubleFloatRegister_object($src1$$reg);
2829 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2830 : reg_to_DoubleFloatRegister_object($src2$$reg);
2831
2832 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2833 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2834 %}
2835
2836 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2837 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2838 MacroAssembler _masm(&cbuf);
2839 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2840 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2841 Register base_pointer_arg = reg_to_register_object($base$$reg);
2842
2843 Label loop;
2844 __ mov(nof_bytes_arg, nof_bytes_tmp);
2845
2846 // Loop and clear, walking backwards through the array.
2847 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2848 __ bind(loop);
2849 __ deccc(nof_bytes_tmp, 8);
2850 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2851 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2852 // %%%% this mini-loop must not cross a cache boundary!
2853 %}
2854
2855
3625 // Long Immediate: 13-bit minus 7
3626 operand immL13m7() %{
3627 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3628 match(ConL);
3629 op_cost(0);
3630
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 // Long Immediate: low 32-bit mask
3636 operand immL_32bits() %{
3637 predicate(n->get_long() == 0xFFFFFFFFL);
3638 match(ConL);
3639 op_cost(0);
3640
3641 format %{ %}
3642 interface(CONST_INTER);
3643 %}
3644
3645 // Long Immediate: cheap (materialize in <= 3 instructions)
3646 operand immL_cheap() %{
3647 predicate(MacroAssembler::size_of_set64(n->get_long()) <= 3);
3648 match(ConL);
3649 op_cost(0);
3650
3651 format %{ %}
3652 interface(CONST_INTER);
3653 %}
3654
3655 // Long Immediate: expensive (materialize in > 3 instructions)
3656 operand immL_expensive() %{
3657 predicate(MacroAssembler::size_of_set64(n->get_long()) > 3);
3658 match(ConL);
3659 op_cost(0);
3660
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3664
3665 // Double Immediate
3666 operand immD() %{
3667 match(ConD);
3668
3669 op_cost(40);
3670 format %{ %}
3671 interface(CONST_INTER);
3672 %}
3673
3674 operand immD0() %{
3675 #ifdef _LP64
3676 // on 64-bit architectures this comparision is faster
3677 predicate(jlong_cast(n->getd()) == 0);
3678 #else
3679 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3680 #endif
3681 match(ConD);
3682
3683 op_cost(0);
3684 format %{ %}
6010 %}
6011
6012 // Load Constant
6013 instruct loadConI( iRegI dst, immI src ) %{
6014 match(Set dst src);
6015 ins_cost(DEFAULT_COST * 3/2);
6016 format %{ "SET $src,$dst" %}
6017 ins_encode( Set32(src, dst) );
6018 ins_pipe(ialu_hi_lo_reg);
6019 %}
6020
6021 instruct loadConI13( iRegI dst, immI13 src ) %{
6022 match(Set dst src);
6023
6024 size(4);
6025 format %{ "MOV $src,$dst" %}
6026 ins_encode( Set13( src, dst ) );
6027 ins_pipe(ialu_imm);
6028 %}
6029
6030 instruct loadConP(iRegP dst, immP con) %{
6031 match(Set dst con);
6032 #ifndef _LP64
6033 ins_cost(DEFAULT_COST * 3/2);
6034 format %{ "SET $con,$dst\t!ptr" %}
6035 ins_encode %{
6036 // [RGV] This next line should be generated from ADLC
6037 if (_opnds[1]->constant_is_oop()) {
6038 intptr_t val = $con$$constant;
6039 __ set_oop_constant((jobject) val, $dst$$Register);
6040 } else { // non-oop pointers, e.g. card mark base, heap top
6041 __ set($con$$constant, $dst$$Register);
6042 }
6043 %}
6044 #else
6045 ins_cost(MEMORY_REF_COST);
6046 size(4);
6047 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6048 ins_encode %{
6049 __ ld_ptr($constanttablebase, $constantoffset($con), $dst$$Register);
6050 %}
6051 #endif
6052 ins_pipe(loadConP);
6053 %}
6054
6055 instruct loadConP0(iRegP dst, immP0 src) %{
6056 match(Set dst src);
6057
6058 size(4);
6059 format %{ "CLR $dst\t!ptr" %}
6060 ins_encode %{
6061 __ clr($dst$$Register);
6062 %}
6063 ins_pipe(ialu_imm);
6064 %}
6065
6066 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6067 match(Set dst src);
6068 ins_cost(DEFAULT_COST);
6069 format %{ "SET $src,$dst\t!ptr" %}
6070 ins_encode %{
6071 AddressLiteral polling_page(os::get_polling_page());
6072 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6073 %}
6074 ins_pipe(loadConP_poll);
6075 %}
6076
6077 instruct loadConN0(iRegN dst, immN0 src) %{
6078 match(Set dst src);
6079
6080 size(4);
6081 format %{ "CLR $dst\t! compressed NULL ptr" %}
6082 ins_encode %{
6083 __ clr($dst$$Register);
6084 %}
6085 ins_pipe(ialu_imm);
6086 %}
6087
6088 instruct loadConN(iRegN dst, immN src) %{
6089 match(Set dst src);
6090 ins_cost(DEFAULT_COST * 3/2);
6091 format %{ "SET $src,$dst\t! compressed ptr" %}
6092 ins_encode %{
6093 Register dst = $dst$$Register;
6094 __ set_narrow_oop((jobject)$src$$constant, dst);
6095 %}
6096 ins_pipe(ialu_hi_lo_reg);
6097 %}
6098
6099 // Materialize long value (predicated by immL_cheap).
6100 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6101 match(Set dst con);
6102 effect(KILL tmp);
6103 ins_cost(DEFAULT_COST * 3);
6104 format %{ "SET64 $con,$dst KILL $tmp\t! long" %}
6105 ins_encode %{
6106 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6107 %}
6108 ins_pipe(loadConL);
6109 %}
6110
6111 // Load long value from constant table (predicated by immL_expensive).
6112 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6113 match(Set dst con);
6114 ins_cost(MEMORY_REF_COST);
6115 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6116 ins_encode %{
6117 __ ldx($constanttablebase, $constantoffset($con), $dst$$Register);
6118 %}
6119 ins_pipe(loadConL);
6120 %}
6121
6122 instruct loadConL0( iRegL dst, immL0 src ) %{
6123 match(Set dst src);
6124 ins_cost(DEFAULT_COST);
6125 size(4);
6126 format %{ "CLR $dst\t! long" %}
6127 ins_encode( Set13( src, dst ) );
6128 ins_pipe(ialu_imm);
6129 %}
6130
6131 instruct loadConL13( iRegL dst, immL13 src ) %{
6132 match(Set dst src);
6133 ins_cost(DEFAULT_COST * 2);
6134
6135 size(4);
6136 format %{ "MOV $src,$dst\t! long" %}
6137 ins_encode( Set13( src, dst ) );
6138 ins_pipe(ialu_imm);
6139 %}
6140
6141 instruct loadConF(regF dst, immF con) %{
6142 match(Set dst con);
6143 size(4);
6144 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6145 ins_encode %{
6146 __ ldf(FloatRegisterImpl::S, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6147 %}
6148 ins_pipe(loadConFD);
6149 %}
6150
6151 instruct loadConD(regD dst, immD con) %{
6152 match(Set dst con);
6153 size(4);
6154 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6155 ins_encode %{
6156 // XXX This is a quick fix for 6833573.
6157 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6158 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), as_DoubleFloatRegister($dst$$reg));
6159 %}
6160 ins_pipe(loadConFD);
6161 %}
6162
6163 // Prefetch instructions.
6164 // Must be safe to execute with invalid address (cannot fault).
6165
6166 instruct prefetchr( memory mem ) %{
6167 match( PrefetchRead mem );
6168 ins_cost(MEMORY_REF_COST);
6169
6170 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6171 opcode(Assembler::prefetch_op3);
6172 ins_encode( form3_mem_prefetch_read( mem ) );
6173 ins_pipe(iload_mem);
6174 %}
6175
6176 instruct prefetchw( memory mem ) %{
6177 predicate(AllocatePrefetchStyle != 3 );
6178 match( PrefetchWrite mem );
8590 "OR $dst,O7,$dst\n\t"
8591 "SRLX $dst,16,O7\n\t"
8592 "OR $dst,O7,$dst\n\t"
8593 "SRLX $dst,32,O7\n\t"
8594 "OR $dst,O7,$dst\t! replicate8B" %}
8595 ins_encode( enc_repl8b(src, dst));
8596 ins_pipe(ialu_reg);
8597 %}
8598
8599 // Replicate scalar to packed byte values in Double register
8600 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8601 match(Set dst (Replicate8B src));
8602 expand %{
8603 iRegL tmp;
8604 Repl8B_reg_helper(tmp, src);
8605 regL_to_stkD(dst, tmp);
8606 %}
8607 %}
8608
8609 // Replicate scalar constant to packed byte values in Double register
8610 instruct Repl8B_immI(regD dst, immI13 con) %{
8611 match(Set dst (Replicate8B con));
8612 size(4);
8613 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8614 ins_encode %{
8615 // XXX This is a quick fix for 6833573.
8616 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8617 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), as_DoubleFloatRegister($dst$$reg));
8618 %}
8619 ins_pipe(loadConFD);
8620 %}
8621
8622 // Replicate scalar to packed char values into stack slot
8623 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8624 effect(DEF dst, USE src);
8625 format %{ "SLLX $src,48,$dst\n\t"
8626 "SRLX $dst,16,O7\n\t"
8627 "OR $dst,O7,$dst\n\t"
8628 "SRLX $dst,32,O7\n\t"
8629 "OR $dst,O7,$dst\t! replicate4C" %}
8630 ins_encode( enc_repl4s(src, dst) );
8631 ins_pipe(ialu_reg);
8632 %}
8633
8634 // Replicate scalar to packed char values into stack slot
8635 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8636 match(Set dst (Replicate4C src));
8637 expand %{
8638 iRegL tmp;
8639 Repl4C_reg_helper(tmp, src);
8640 regL_to_stkD(dst, tmp);
8641 %}
8642 %}
8643
8644 // Replicate scalar constant to packed char values in Double register
8645 instruct Repl4C_immI(regD dst, immI con) %{
8646 match(Set dst (Replicate4C con));
8647 size(4);
8648 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8649 ins_encode %{
8650 // XXX This is a quick fix for 6833573.
8651 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8652 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg));
8653 %}
8654 ins_pipe(loadConFD);
8655 %}
8656
8657 // Replicate scalar to packed short values into stack slot
8658 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8659 effect(DEF dst, USE src);
8660 format %{ "SLLX $src,48,$dst\n\t"
8661 "SRLX $dst,16,O7\n\t"
8662 "OR $dst,O7,$dst\n\t"
8663 "SRLX $dst,32,O7\n\t"
8664 "OR $dst,O7,$dst\t! replicate4S" %}
8665 ins_encode( enc_repl4s(src, dst) );
8666 ins_pipe(ialu_reg);
8667 %}
8668
8669 // Replicate scalar to packed short values into stack slot
8670 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8671 match(Set dst (Replicate4S src));
8672 expand %{
8673 iRegL tmp;
8674 Repl4S_reg_helper(tmp, src);
8675 regL_to_stkD(dst, tmp);
8676 %}
8677 %}
8678
8679 // Replicate scalar constant to packed short values in Double register
8680 instruct Repl4S_immI(regD dst, immI con) %{
8681 match(Set dst (Replicate4S con));
8682 size(4);
8683 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8684 ins_encode %{
8685 // XXX This is a quick fix for 6833573.
8686 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8687 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg));
8688 %}
8689 ins_pipe(loadConFD);
8690 %}
8691
8692 // Replicate scalar to packed int values in Double register
8693 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8694 effect(DEF dst, USE src);
8695 format %{ "SLLX $src,32,$dst\n\t"
8696 "SRLX $dst,32,O7\n\t"
8697 "OR $dst,O7,$dst\t! replicate2I" %}
8698 ins_encode( enc_repl2i(src, dst));
8699 ins_pipe(ialu_reg);
8700 %}
8701
8702 // Replicate scalar to packed int values in Double register
8703 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8704 match(Set dst (Replicate2I src));
8705 expand %{
8706 iRegL tmp;
8707 Repl2I_reg_helper(tmp, src);
8708 regL_to_stkD(dst, tmp);
8709 %}
8710 %}
8711
8712 // Replicate scalar zero constant to packed int values in Double register
8713 instruct Repl2I_immI(regD dst, immI con) %{
8714 match(Set dst (Replicate2I con));
8715 size(4);
8716 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8717 ins_encode %{
8718 // XXX This is a quick fix for 6833573.
8719 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8720 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), as_DoubleFloatRegister($dst$$reg));
8721 %}
8722 ins_pipe(loadConFD);
8723 %}
8724
8725 //----------Control Flow Instructions------------------------------------------
8726 // Compare Instructions
8727 // Compare Integers
8728 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8729 match(Set icc (CmpI op1 op2));
8730 effect( DEF icc, USE op1, USE op2 );
8731
8732 size(4);
8733 format %{ "CMP $op1,$op2" %}
8734 opcode(Assembler::subcc_op3, Assembler::arith_op);
8735 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8736 ins_pipe(ialu_cconly_reg_reg);
8737 %}
8738
8739 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8740 match(Set icc (CmpU op1 op2));
8741
8957
8958 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8959 match(Set dst (CmpD3 src1 src2));
8960 effect(KILL fcc0);
8961 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8962 format %{ "dcmpl $dst,$src1,$src2" %}
8963 // Primary = double (not float)
8964 opcode( false );
8965 ins_encode( floating_cmp( dst, src1, src2 ) );
8966 ins_pipe( floating_cmp );
8967 %}
8968
8969 //----------Branches---------------------------------------------------------
8970 // Jump
8971 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8972 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8973 match(Jump switch_val);
8974
8975 ins_cost(350);
8976
8977 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8978 "LD [O7 + $switch_val], O7\n\t"
8979 "JUMP O7"
8980 %}
8981 ins_encode %{
8982 // Calculate table address into a register.
8983 Register table_reg;
8984 Register label_reg = O7;
8985 if (constant_offset() == 0) {
8986 table_reg = $constanttablebase;
8987 } else {
8988 table_reg = O7;
8989 __ add($constanttablebase, $constantoffset, table_reg);
8990 }
8991
8992 // Jump to base address + switch value
8993 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8994 __ jmp(label_reg, G0);
8995 __ delayed()->nop();
8996 %}
8997 ins_pc_relative(1);
8998 ins_pipe(ialu_reg_reg);
8999 %}
9000
9001 // Direct Branch. Use V8 version with longer range.
9002 instruct branch(label labl) %{
9003 match(Goto);
9004 effect(USE labl);
9005
9006 size(8);
9007 ins_cost(BRANCH_COST);
9008 format %{ "BA $labl" %}
9009 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
9010 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
9011 ins_encode( enc_ba( labl ) );
9012 ins_pc_relative(1);
9013 ins_pipe(br);
9014 %}
9015
9016 // Conditional Direct Branch
|