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rev 1838 : 6961690: load oops from constant table on SPARC
Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
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--- old/src/cpu/sparc/vm/sparc.ad
+++ new/src/cpu/sparc/vm/sparc.ad
1 1 //
2 2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
3 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 //
5 5 // This code is free software; you can redistribute it and/or modify it
6 6 // under the terms of the GNU General Public License version 2 only, as
7 7 // published by the Free Software Foundation.
8 8 //
9 9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 // version 2 for more details (a copy is included in the LICENSE file that
13 13 // accompanied this code).
14 14 //
15 15 // You should have received a copy of the GNU General Public License version
16 16 // 2 along with this work; if not, write to the Free Software Foundation,
17 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 //
19 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 // or visit www.oracle.com if you need additional information or have any
21 21 // questions.
22 22 //
23 23 //
24 24
25 25 // SPARC Architecture Description File
26 26
27 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 28 // This information is used by the matcher and the register allocator to
29 29 // describe individual registers and classes of registers within the target
30 30 // archtecture.
31 31 register %{
32 32 //----------Architecture Description Register Definitions----------------------
33 33 // General Registers
34 34 // "reg_def" name ( register save type, C convention save type,
35 35 // ideal register type, encoding, vm name );
36 36 // Register Save Types:
37 37 //
38 38 // NS = No-Save: The register allocator assumes that these registers
39 39 // can be used without saving upon entry to the method, &
40 40 // that they do not need to be saved at call sites.
41 41 //
42 42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 43 // can be used without saving upon entry to the method,
44 44 // but that they must be saved at call sites.
45 45 //
46 46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 47 // must be saved before using them upon entry to the
48 48 // method, but they do not need to be saved at call
49 49 // sites.
50 50 //
51 51 // AS = Always-Save: The register allocator assumes that these registers
52 52 // must be saved before using them upon entry to the
53 53 // method, & that they must be saved at call sites.
54 54 //
55 55 // Ideal Register Type is used to determine how to save & restore a
56 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 58 //
59 59 // The encoding number is the actual bit-pattern placed into the opcodes.
60 60
61 61
62 62 // ----------------------------
63 63 // Integer/Long Registers
64 64 // ----------------------------
65 65
66 66 // Need to expose the hi/lo aspect of 64-bit registers
67 67 // This register set is used for both the 64-bit build and
68 68 // the 32-bit build with 1-register longs.
69 69
70 70 // Global Registers 0-7
71 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87 87
88 88 // Output Registers 0-7
89 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105 105
106 106 // Local Registers 0-7
107 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123 123
124 124 // Input Registers 0-7
125 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141 141
142 142 // ----------------------------
143 143 // Float/Double Registers
144 144 // ----------------------------
145 145
146 146 // Float Registers
147 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179 179
180 180 // Double Registers
181 181 // The rules of ADL require that double registers be defined in pairs.
182 182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 183 // single float registers. In each pair, ADLC-assigned register numbers
184 184 // must be adjacent, with the lower number even. Finally, when the
185 185 // CPU stores such a register pair to memory, the word associated with
186 186 // the lower ADLC-assigned number must be stored to the lower address.
187 187
188 188 // These definitions specify the actual bit encodings of the sparc
189 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 190 // wants 0-63, so we have to convert every time we want to use fp regs
191 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 192 // 255 is a flag meaning "don't go here".
193 193 // I believe we can't handle callee-save doubles D32 and up until
194 194 // the place in the sparc stack crawler that asserts on the 255 is
195 195 // fixed up.
196 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228 228
229 229
230 230 // ----------------------------
231 231 // Special Registers
232 232 // Condition Codes Flag Registers
233 233 // I tried to break out ICC and XCC but it's not very pretty.
234 234 // Every Sparc instruction which defs/kills one also kills the other.
235 235 // Hence every compare instruction which defs one kind of flags ends
236 236 // up needing a kill of the other.
237 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238 238
239 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243 243
244 244 // ----------------------------
245 245 // Specify the enum values for the registers. These enums are only used by the
246 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 247 // for visibility to the rest of the vm. The order of this enum influences the
248 248 // register allocator so having the freedom to set this order and not be stuck
249 249 // with the order that is natural for the rest of the vm is worth it.
250 250 alloc_class chunk0(
251 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255 255
256 256 // Note that a register is not allocatable unless it is also mentioned
257 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258 258
259 259 alloc_class chunk1(
260 260 // The first registers listed here are those most likely to be used
261 261 // as temporaries. We move F0..F7 away from the front of the list,
262 262 // to reduce the likelihood of interferences with parameters and
263 263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 264 // since they are used for return values.
265 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274 274
275 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276 276
277 277 //----------Architecture Description Register Classes--------------------------
278 278 // Several register classes are automatically defined based upon information in
279 279 // this architecture description.
280 280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 283 //
284 284
285 285 // G0 is not included in integer class since it has special meaning.
286 286 reg_class g0_reg(R_G0);
287 287
288 288 // ----------------------------
289 289 // Integer Register Classes
290 290 // ----------------------------
291 291 // Exclusions from i_reg:
292 292 // R_G0: hardwired zero
293 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 294 // R_G6: reserved by Solaris ABI to tools
295 295 // R_G7: reserved by Solaris ABI to libthread
296 296 // R_O7: Used as a temp in many encodings
297 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298 298
299 299 // Class for all integer registers, except the G registers. This is used for
300 300 // encodings which use G registers as temps. The regular inputs to such
301 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 302 // will not put an input into a temp register.
303 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304 304
305 305 reg_class g1_regI(R_G1);
306 306 reg_class g3_regI(R_G3);
307 307 reg_class g4_regI(R_G4);
308 308 reg_class o0_regI(R_O0);
309 309 reg_class o7_regI(R_O7);
310 310
311 311 // ----------------------------
312 312 // Pointer Register Classes
313 313 // ----------------------------
314 314 #ifdef _LP64
315 315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 320 // Lock encodings use G3 and G4 internally
321 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 326 // It is also used for memory addressing, allowing direct TLS addressing.
327 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 332 // We use it to save R_G2 across calls out of Java.
333 333 reg_class l7_regP(R_L7H,R_L7);
334 334
335 335 // Other special pointer regs
336 336 reg_class g1_regP(R_G1H,R_G1);
337 337 reg_class g2_regP(R_G2H,R_G2);
338 338 reg_class g3_regP(R_G3H,R_G3);
339 339 reg_class g4_regP(R_G4H,R_G4);
340 340 reg_class g5_regP(R_G5H,R_G5);
341 341 reg_class i0_regP(R_I0H,R_I0);
342 342 reg_class o0_regP(R_O0H,R_O0);
343 343 reg_class o1_regP(R_O1H,R_O1);
344 344 reg_class o2_regP(R_O2H,R_O2);
345 345 reg_class o7_regP(R_O7H,R_O7);
346 346
347 347 #else // _LP64
348 348 // 32-bit build means 32-bit pointers means 1 register.
349 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 353 // Lock encodings use G3 and G4 internally
354 354 reg_class lock_ptr_reg(R_G1, R_G5,
355 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 359 // It is also used for memory addressing, allowing direct TLS addressing.
360 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 365 // We use it to save R_G2 across calls out of Java.
366 366 reg_class l7_regP(R_L7);
367 367
368 368 // Other special pointer regs
369 369 reg_class g1_regP(R_G1);
370 370 reg_class g2_regP(R_G2);
371 371 reg_class g3_regP(R_G3);
372 372 reg_class g4_regP(R_G4);
373 373 reg_class g5_regP(R_G5);
374 374 reg_class i0_regP(R_I0);
375 375 reg_class o0_regP(R_O0);
376 376 reg_class o1_regP(R_O1);
377 377 reg_class o2_regP(R_O2);
378 378 reg_class o7_regP(R_O7);
379 379 #endif // _LP64
380 380
381 381
382 382 // ----------------------------
383 383 // Long Register Classes
384 384 // ----------------------------
385 385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 389 #ifdef _LP64
390 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 394 #endif // _LP64
395 395 );
396 396
397 397 reg_class g1_regL(R_G1H,R_G1);
398 398 reg_class g3_regL(R_G3H,R_G3);
399 399 reg_class o2_regL(R_O2H,R_O2);
400 400 reg_class o7_regL(R_O7H,R_O7);
401 401
402 402 // ----------------------------
403 403 // Special Class for Condition Code Flags Register
404 404 reg_class int_flags(CCR);
405 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 406 reg_class float_flag0(FCC0);
407 407
408 408
409 409 // ----------------------------
410 410 // Float Point Register Classes
411 411 // ----------------------------
412 412 // Skip F30/F31, they are reserved for mem-mem copies
413 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414 414
415 415 // Paired floating point registers--they show up in the same order as the floats,
416 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 419 /* Use extra V9 double registers; this AD file does not support V8 */
420 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 422 );
423 423
424 424 // Paired floating point registers--they show up in the same order as the floats,
425 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 429 %}
430 430
431 431 //----------DEFINITION BLOCK---------------------------------------------------
432 432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 434 // Format:
435 435 // int_def <name> ( <int_value>, <expression>);
436 436 // Generated Code in ad_<arch>.hpp
437 437 // #define <name> (<expression>)
438 438 // // value == <int_value>
439 439 // Generated code in ad_<arch>.cpp adlc_verification()
440 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 441 //
442 442 definitions %{
443 443 // The default cost (of an ALU instruction).
444 444 int_def DEFAULT_COST ( 100, 100);
445 445 int_def HUGE_COST (1000000, 1000000);
446 446
447 447 // Memory refs are twice as expensive as run-of-the-mill.
448 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449 449
450 450 // Branches are even more expensive.
451 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 453 %}
454 454
455 455
456 456 //----------SOURCE BLOCK-------------------------------------------------------
457 457 // This is a block of C++ code which provides values, functions, and
458 458 // definitions necessary in the rest of the architecture description
459 459 source_hpp %{
460 460 // Must be visible to the DFA in dfa_sparc.cpp
461 461 extern bool can_branch_register( Node *bol, Node *cmp );
462 462
463 463 // Macros to extract hi & lo halves from a long pair.
464 464 // G0 is not part of any long pair, so assert on that.
465 465 // Prevents accidentally using G1 instead of G0.
466 466 #define LONG_HI_REG(x) (x)
467 467 #define LONG_LO_REG(x) (x)
468 468
469 469 %}
470 470
471 471 source %{
472 472 #define __ _masm.
473 473
474 474 // Block initializing store
475 475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476 476
477 477 // tertiary op of a LoadP or StoreP encoding
478 478 #define REGP_OP true
479 479
480 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 482 static Register reg_to_register_object(int register_encoding);
483 483
484 484 // Used by the DFA in dfa_sparc.cpp.
485 485 // Check for being able to use a V9 branch-on-register. Requires a
486 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 487 // extended. Doesn't work following an integer ADD, for example, because of
488 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 490 // replace them with zero, which could become sign-extension in a different OS
491 491 // release. There's no obvious reason why an interrupt will ever fill these
492 492 // bits with non-zero junk (the registers are reloaded with standard LD
493 493 // instructions which either zero-fill or sign-fill).
494 494 bool can_branch_register( Node *bol, Node *cmp ) {
495 495 if( !BranchOnRegister ) return false;
496 496 #ifdef _LP64
497 497 if( cmp->Opcode() == Op_CmpP )
498 498 return true; // No problems with pointer compares
499 499 #endif
500 500 if( cmp->Opcode() == Op_CmpL )
501 501 return true; // No problems with long compares
502 502
503 503 if( !SparcV9RegsHiBitsZero ) return false;
504 504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 505 bol->as_Bool()->_test._test != BoolTest::eq )
506 506 return false;
507 507
508 508 // Check for comparing against a 'safe' value. Any operation which
509 509 // clears out the high word is safe. Thus, loads and certain shifts
510 510 // are safe, as are non-negative constants. Any operation which
511 511 // preserves zero bits in the high word is safe as long as each of its
512 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 513 // inputs are safe. At present, the only important case to recognize
514 514 // seems to be loads. Constants should fold away, and shifts &
515 515 // logicals can use the 'cc' forms.
516 516 Node *x = cmp->in(1);
517 517 if( x->is_Load() ) return true;
518 518 if( x->is_Phi() ) {
519 519 for( uint i = 1; i < x->req(); i++ )
520 520 if( !x->in(i)->is_Load() )
521 521 return false;
522 522 return true;
523 523 }
524 524 return false;
525 525 }
526 526
527 527 // ****************************************************************************
528 528
529 529 // REQUIRED FUNCTIONALITY
530 530
531 531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 532 // from the start of the call to the point where the return address
533 533 // will point.
534 534 // The "return address" is the address of the call instruction, plus 8.
535 535
536 536 int MachCallStaticJavaNode::ret_addr_offset() {
537 537 int offset = NativeCall::instruction_size; // call; delay slot
538 538 if (_method_handle_invoke)
539 539 offset += 4; // restore SP
540 540 return offset;
541 541 }
542 542
543 543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 544 int vtable_index = this->_vtable_index;
545 545 if (vtable_index < 0) {
546 546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 548 return (NativeMovConstReg::instruction_size +
549 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 550 } else {
551 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 554 int klass_load_size;
555 555 if (UseCompressedOops) {
556 556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 557 if (Universe::narrow_oop_base() == NULL)
558 558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 559 else
560 560 klass_load_size = 3*BytesPerInstWord;
561 561 } else {
562 562 klass_load_size = 1*BytesPerInstWord;
563 563 }
564 564 if( Assembler::is_simm13(v_off) ) {
565 565 return klass_load_size +
566 566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 567 NativeCall::instruction_size); // call; delay slot
568 568 } else {
569 569 return klass_load_size +
570 570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 571 NativeCall::instruction_size); // call; delay slot
572 572 }
573 573 }
574 574 }
575 575
576 576 int MachCallRuntimeNode::ret_addr_offset() {
577 577 #ifdef _LP64
578 578 return NativeFarCall::instruction_size; // farcall; delay slot
579 579 #else
580 580 return NativeCall::instruction_size; // call; delay slot
581 581 #endif
582 582 }
583 583
584 584 // Indicate if the safepoint node needs the polling page as an input.
585 585 // Since Sparc does not have absolute addressing, it does.
586 586 bool SafePointNode::needs_polling_address_input() {
587 587 return true;
588 588 }
589 589
590 590 // emit an interrupt that is caught by the debugger (for debugging compiler)
591 591 void emit_break(CodeBuffer &cbuf) {
592 592 MacroAssembler _masm(&cbuf);
593 593 __ breakpoint_trap();
594 594 }
595 595
596 596 #ifndef PRODUCT
597 597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
598 598 st->print("TA");
599 599 }
600 600 #endif
601 601
602 602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 603 emit_break(cbuf);
604 604 }
605 605
606 606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
607 607 return MachNode::size(ra_);
608 608 }
609 609
610 610 // Traceable jump
611 611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
612 612 MacroAssembler _masm(&cbuf);
613 613 Register rdest = reg_to_register_object(jump_target);
614 614 __ JMP(rdest, 0);
615 615 __ delayed()->nop();
616 616 }
617 617
618 618 // Traceable jump and set exception pc
619 619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
620 620 MacroAssembler _masm(&cbuf);
621 621 Register rdest = reg_to_register_object(jump_target);
622 622 __ JMP(rdest, 0);
623 623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
624 624 }
625 625
626 626 void emit_nop(CodeBuffer &cbuf) {
627 627 MacroAssembler _masm(&cbuf);
628 628 __ nop();
629 629 }
630 630
631 631 void emit_illtrap(CodeBuffer &cbuf) {
632 632 MacroAssembler _masm(&cbuf);
633 633 __ illtrap(0);
634 634 }
635 635
636 636
637 637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
638 638 assert(n->rule() != loadUB_rule, "");
639 639
640 640 intptr_t offset = 0;
641 641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
642 642 const Node* addr = n->get_base_and_disp(offset, adr_type);
643 643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
644 644 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
645 645 assert(addr->bottom_type()->isa_oopptr() == atype, "");
646 646 atype = atype->add_offset(offset);
647 647 assert(disp32 == offset, "wrong disp32");
648 648 return atype->_offset;
649 649 }
650 650
651 651
652 652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
653 653 assert(n->rule() != loadUB_rule, "");
654 654
655 655 intptr_t offset = 0;
656 656 Node* addr = n->in(2);
657 657 assert(addr->bottom_type()->isa_oopptr() == atype, "");
658 658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
659 659 Node* a = addr->in(2/*AddPNode::Address*/);
↓ open down ↓ |
659 lines elided |
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660 660 Node* o = addr->in(3/*AddPNode::Offset*/);
661 661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
662 662 atype = a->bottom_type()->is_ptr()->add_offset(offset);
663 663 assert(atype->isa_oop_ptr(), "still an oop");
664 664 }
665 665 offset = atype->is_ptr()->_offset;
666 666 if (offset != Type::OffsetBot) offset += disp32;
667 667 return offset;
668 668 }
669 669
670 +static inline jdouble replicate_immI(int con, int count, int width) {
671 + // Load a constant replicated "count" times with width "width"
672 + int bit_width = width * 8;
673 + jlong elt_val = con;
674 + elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
675 + jlong val = elt_val;
676 + for (int i = 0; i < count - 1; i++) {
677 + val <<= bit_width;
678 + val |= elt_val;
679 + }
680 + jdouble dval = *((jdouble*) &val); // coerce to double type
681 + return dval;
682 +}
683 +
670 684 // Standard Sparc opcode form2 field breakdown
671 685 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
672 686 f0 &= (1<<19)-1; // Mask displacement to 19 bits
673 687 int op = (f30 << 30) |
674 688 (f29 << 29) |
675 689 (f25 << 25) |
676 690 (f22 << 22) |
677 691 (f20 << 20) |
678 692 (f19 << 19) |
679 693 (f0 << 0);
680 694 cbuf.insts()->emit_int32(op);
681 695 }
682 696
683 697 // Standard Sparc opcode form2 field breakdown
684 698 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
685 699 f0 >>= 10; // Drop 10 bits
686 700 f0 &= (1<<22)-1; // Mask displacement to 22 bits
687 701 int op = (f30 << 30) |
688 702 (f25 << 25) |
689 703 (f22 << 22) |
690 704 (f0 << 0);
691 705 cbuf.insts()->emit_int32(op);
692 706 }
693 707
694 708 // Standard Sparc opcode form3 field breakdown
695 709 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
696 710 int op = (f30 << 30) |
697 711 (f25 << 25) |
698 712 (f19 << 19) |
699 713 (f14 << 14) |
700 714 (f5 << 5) |
701 715 (f0 << 0);
702 716 cbuf.insts()->emit_int32(op);
703 717 }
704 718
705 719 // Standard Sparc opcode form3 field breakdown
706 720 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
707 721 simm13 &= (1<<13)-1; // Mask to 13 bits
708 722 int op = (f30 << 30) |
709 723 (f25 << 25) |
710 724 (f19 << 19) |
711 725 (f14 << 14) |
712 726 (1 << 13) | // bit to indicate immediate-mode
713 727 (simm13<<0);
714 728 cbuf.insts()->emit_int32(op);
715 729 }
716 730
717 731 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
718 732 simm10 &= (1<<10)-1; // Mask to 10 bits
719 733 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
720 734 }
721 735
722 736 #ifdef ASSERT
723 737 // Helper function for VerifyOops in emit_form3_mem_reg
724 738 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
725 739 warning("VerifyOops encountered unexpected instruction:");
726 740 n->dump(2);
727 741 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
728 742 }
729 743 #endif
730 744
731 745
732 746 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
733 747 int src1_enc, int disp32, int src2_enc, int dst_enc) {
734 748
735 749 #ifdef ASSERT
736 750 // The following code implements the +VerifyOops feature.
737 751 // It verifies oop values which are loaded into or stored out of
738 752 // the current method activation. +VerifyOops complements techniques
739 753 // like ScavengeALot, because it eagerly inspects oops in transit,
740 754 // as they enter or leave the stack, as opposed to ScavengeALot,
741 755 // which inspects oops "at rest", in the stack or heap, at safepoints.
742 756 // For this reason, +VerifyOops can sometimes detect bugs very close
743 757 // to their point of creation. It can also serve as a cross-check
744 758 // on the validity of oop maps, when used toegether with ScavengeALot.
745 759
746 760 // It would be good to verify oops at other points, especially
747 761 // when an oop is used as a base pointer for a load or store.
748 762 // This is presently difficult, because it is hard to know when
749 763 // a base address is biased or not. (If we had such information,
750 764 // it would be easy and useful to make a two-argument version of
751 765 // verify_oop which unbiases the base, and performs verification.)
752 766
753 767 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
754 768 bool is_verified_oop_base = false;
755 769 bool is_verified_oop_load = false;
756 770 bool is_verified_oop_store = false;
757 771 int tmp_enc = -1;
758 772 if (VerifyOops && src1_enc != R_SP_enc) {
759 773 // classify the op, mainly for an assert check
760 774 int st_op = 0, ld_op = 0;
761 775 switch (primary) {
762 776 case Assembler::stb_op3: st_op = Op_StoreB; break;
763 777 case Assembler::sth_op3: st_op = Op_StoreC; break;
764 778 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
765 779 case Assembler::stw_op3: st_op = Op_StoreI; break;
766 780 case Assembler::std_op3: st_op = Op_StoreL; break;
767 781 case Assembler::stf_op3: st_op = Op_StoreF; break;
768 782 case Assembler::stdf_op3: st_op = Op_StoreD; break;
769 783
770 784 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
771 785 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
772 786 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
773 787 case Assembler::ldx_op3: // may become LoadP or stay LoadI
774 788 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
775 789 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
776 790 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
777 791 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
778 792 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
779 793 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
780 794 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
781 795
782 796 default: ShouldNotReachHere();
783 797 }
784 798 if (tertiary == REGP_OP) {
785 799 if (st_op == Op_StoreI) st_op = Op_StoreP;
786 800 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
787 801 else ShouldNotReachHere();
788 802 if (st_op) {
789 803 // a store
790 804 // inputs are (0:control, 1:memory, 2:address, 3:value)
791 805 Node* n2 = n->in(3);
792 806 if (n2 != NULL) {
793 807 const Type* t = n2->bottom_type();
794 808 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
795 809 }
796 810 } else {
797 811 // a load
798 812 const Type* t = n->bottom_type();
799 813 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
800 814 }
801 815 }
802 816
803 817 if (ld_op) {
804 818 // a Load
805 819 // inputs are (0:control, 1:memory, 2:address)
806 820 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
807 821 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
808 822 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
809 823 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
810 824 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
811 825 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
812 826 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
813 827 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
814 828 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
815 829 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
816 830 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
817 831 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
818 832 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
819 833 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
820 834 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
821 835 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
822 836 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
823 837 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
824 838 !(n->rule() == loadUB_rule)) {
825 839 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
826 840 }
827 841 } else if (st_op) {
828 842 // a Store
829 843 // inputs are (0:control, 1:memory, 2:address, 3:value)
830 844 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
831 845 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
832 846 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
833 847 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
834 848 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
835 849 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
836 850 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
837 851 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
838 852 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
839 853 verify_oops_warning(n, n->ideal_Opcode(), st_op);
840 854 }
841 855 }
842 856
843 857 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
844 858 Node* addr = n->in(2);
845 859 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
846 860 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
847 861 if (atype != NULL) {
848 862 intptr_t offset = get_offset_from_base(n, atype, disp32);
849 863 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
850 864 if (offset != offset_2) {
851 865 get_offset_from_base(n, atype, disp32);
852 866 get_offset_from_base_2(n, atype, disp32);
853 867 }
854 868 assert(offset == offset_2, "different offsets");
855 869 if (offset == disp32) {
856 870 // we now know that src1 is a true oop pointer
857 871 is_verified_oop_base = true;
858 872 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
859 873 if( primary == Assembler::ldd_op3 ) {
860 874 is_verified_oop_base = false; // Cannot 'ldd' into O7
861 875 } else {
862 876 tmp_enc = dst_enc;
863 877 dst_enc = R_O7_enc; // Load into O7; preserve source oop
864 878 assert(src1_enc != dst_enc, "");
865 879 }
866 880 }
867 881 }
868 882 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
869 883 || offset == oopDesc::mark_offset_in_bytes())) {
870 884 // loading the mark should not be allowed either, but
871 885 // we don't check this since it conflicts with InlineObjectHash
872 886 // usage of LoadINode to get the mark. We could keep the
873 887 // check if we create a new LoadMarkNode
874 888 // but do not verify the object before its header is initialized
875 889 ShouldNotReachHere();
876 890 }
877 891 }
878 892 }
879 893 }
880 894 }
881 895 #endif
882 896
883 897 uint instr;
884 898 instr = (Assembler::ldst_op << 30)
885 899 | (dst_enc << 25)
886 900 | (primary << 19)
887 901 | (src1_enc << 14);
888 902
889 903 uint index = src2_enc;
890 904 int disp = disp32;
891 905
892 906 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
893 907 disp += STACK_BIAS;
894 908
895 909 // We should have a compiler bailout here rather than a guarantee.
896 910 // Better yet would be some mechanism to handle variable-size matches correctly.
897 911 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
898 912
899 913 if( disp == 0 ) {
900 914 // use reg-reg form
901 915 // bit 13 is already zero
902 916 instr |= index;
903 917 } else {
904 918 // use reg-imm form
905 919 instr |= 0x00002000; // set bit 13 to one
906 920 instr |= disp & 0x1FFF;
907 921 }
908 922
909 923 cbuf.insts()->emit_int32(instr);
910 924
911 925 #ifdef ASSERT
912 926 {
913 927 MacroAssembler _masm(&cbuf);
914 928 if (is_verified_oop_base) {
915 929 __ verify_oop(reg_to_register_object(src1_enc));
916 930 }
917 931 if (is_verified_oop_store) {
918 932 __ verify_oop(reg_to_register_object(dst_enc));
919 933 }
920 934 if (tmp_enc != -1) {
921 935 __ mov(O7, reg_to_register_object(tmp_enc));
922 936 }
923 937 if (is_verified_oop_load) {
924 938 __ verify_oop(reg_to_register_object(dst_enc));
925 939 }
926 940 }
927 941 #endif
928 942 }
929 943
930 944 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
931 945 // The method which records debug information at every safepoint
932 946 // expects the call to be the first instruction in the snippet as
933 947 // it creates a PcDesc structure which tracks the offset of a call
934 948 // from the start of the codeBlob. This offset is computed as
935 949 // code_end() - code_begin() of the code which has been emitted
936 950 // so far.
937 951 // In this particular case we have skirted around the problem by
938 952 // putting the "mov" instruction in the delay slot but the problem
939 953 // may bite us again at some other point and a cleaner/generic
940 954 // solution using relocations would be needed.
941 955 MacroAssembler _masm(&cbuf);
942 956 __ set_inst_mark();
943 957
944 958 // We flush the current window just so that there is a valid stack copy
945 959 // the fact that the current window becomes active again instantly is
946 960 // not a problem there is nothing live in it.
947 961
948 962 #ifdef ASSERT
949 963 int startpos = __ offset();
950 964 #endif /* ASSERT */
951 965
952 966 #ifdef _LP64
953 967 // Calls to the runtime or native may not be reachable from compiled code,
954 968 // so we generate the far call sequence on 64 bit sparc.
955 969 // This code sequence is relocatable to any address, even on LP64.
956 970 if ( force_far_call ) {
957 971 __ relocate(rtype);
958 972 AddressLiteral dest(entry_point);
959 973 __ jumpl_to(dest, O7, O7);
960 974 }
961 975 else
962 976 #endif
963 977 {
964 978 __ call((address)entry_point, rtype);
965 979 }
966 980
967 981 if (preserve_g2) __ delayed()->mov(G2, L7);
968 982 else __ delayed()->nop();
969 983
970 984 if (preserve_g2) __ mov(L7, G2);
971 985
972 986 #ifdef ASSERT
973 987 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
974 988 #ifdef _LP64
975 989 // Trash argument dump slots.
976 990 __ set(0xb0b8ac0db0b8ac0d, G1);
977 991 __ mov(G1, G5);
978 992 __ stx(G1, SP, STACK_BIAS + 0x80);
979 993 __ stx(G1, SP, STACK_BIAS + 0x88);
980 994 __ stx(G1, SP, STACK_BIAS + 0x90);
981 995 __ stx(G1, SP, STACK_BIAS + 0x98);
982 996 __ stx(G1, SP, STACK_BIAS + 0xA0);
983 997 __ stx(G1, SP, STACK_BIAS + 0xA8);
984 998 #else // _LP64
985 999 // this is also a native call, so smash the first 7 stack locations,
986 1000 // and the various registers
987 1001
988 1002 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
989 1003 // while [SP+0x44..0x58] are the argument dump slots.
990 1004 __ set((intptr_t)0xbaadf00d, G1);
991 1005 __ mov(G1, G5);
992 1006 __ sllx(G1, 32, G1);
993 1007 __ or3(G1, G5, G1);
994 1008 __ mov(G1, G5);
995 1009 __ stx(G1, SP, 0x40);
996 1010 __ stx(G1, SP, 0x48);
997 1011 __ stx(G1, SP, 0x50);
998 1012 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
999 1013 #endif // _LP64
1000 1014 }
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1001 1015 #endif /*ASSERT*/
1002 1016 }
1003 1017
1004 1018 //=============================================================================
1005 1019 // REQUIRED FUNCTIONALITY for encoding
1006 1020 void emit_lo(CodeBuffer &cbuf, int val) { }
1007 1021 void emit_hi(CodeBuffer &cbuf, int val) { }
1008 1022
1009 1023
1010 1024 //=============================================================================
1025 +const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1026 +
1027 +void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1028 + emit_constant_table(cbuf);
1029 + MacroAssembler _masm(&cbuf);
1030 +
1031 + Register r = as_Register(ra_->get_encode(this));
1032 + CodeSection* cs = __ code()->consts();
1033 + int consts_size = cs->align_at_start(cs->size());
1034 +
1035 + if (UseRDPCForConstantTableBase) {
1036 + int offset = __ offset();
1037 + int disp;
1038 +
1039 + // If the displacement from the current PC to the constant table
1040 + // base fits into simm13 we set the constant table base to the
1041 + // current PC.
1042 + if (__ is_simm13(-(consts_size + offset))) {
1043 + set_table_base_offset(-(consts_size + offset));
1044 + disp = 0;
1045 + } else {
1046 + // If the offset of the top constant (last entry in the table)
1047 + // fits into simm13 we set the constant table base to the actual
1048 + // table base.
1049 + if (__ is_simm13(top_constant_offset())) {
1050 + set_table_base_offset(0);
1051 + disp = consts_size + offset;
1052 + } else {
1053 + // Otherwise we set the constant table base in the middle of the
1054 + // constant table.
1055 + int half_consts_size = consts_size / 2;
1056 + assert(half_consts_size * 2 == consts_size, "sanity");
1057 + set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1058 + disp = half_consts_size + offset;
1059 + }
1060 + }
1061 +
1062 + __ get_pc(r);
1063 +
1064 + if (disp != 0) {
1065 + assert(r != O7, "need temporary");
1066 + __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1067 + }
1068 + }
1069 + else {
1070 + // Materialize the constant table base.
1071 + // Set the constant table base in the middle of the constant
1072 + // table.
1073 + int half_consts_size = consts_size / 2;
1074 + assert(half_consts_size * 2 == consts_size, "sanity");
1075 + set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1076 +
1077 + address baseaddr = cs->start() + half_consts_size;
1078 + RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1079 + AddressLiteral base(baseaddr, rspec);
1080 + __ set(base, r);
1081 + }
1082 +}
1083 +
1084 +uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1085 + Unimplemented();
1086 + return 0;
1087 +}
1088 +
1089 +#ifndef PRODUCT
1090 +void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1091 + char reg[128];
1092 + ra_->dump_register(this, reg);
1093 + if (UseRDPCForConstantTableBase) {
1094 + st->print("RDPC %s\t! constant table base", reg);
1095 + } else {
1096 + st->print("SET &constanttable,%s\t! constant table base", reg);
1097 + }
1098 +}
1099 +#endif
1100 +
1101 +
1102 +//=============================================================================
1011 1103
1012 1104 #ifndef PRODUCT
1013 1105 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1014 1106 Compile* C = ra_->C;
1015 1107
1016 1108 for (int i = 0; i < OptoPrologueNops; i++) {
1017 1109 st->print_cr("NOP"); st->print("\t");
1018 1110 }
1019 1111
1020 1112 if( VerifyThread ) {
1021 1113 st->print_cr("Verify_Thread"); st->print("\t");
1022 1114 }
1023 1115
1024 1116 size_t framesize = C->frame_slots() << LogBytesPerInt;
1025 1117
1026 1118 // Calls to C2R adapters often do not accept exceptional returns.
1027 1119 // We require that their callers must bang for them. But be careful, because
1028 1120 // some VM calls (such as call site linkage) can use several kilobytes of
1029 1121 // stack. But the stack safety zone should account for that.
1030 1122 // See bugs 4446381, 4468289, 4497237.
1031 1123 if (C->need_stack_bang(framesize)) {
1032 1124 st->print_cr("! stack bang"); st->print("\t");
1033 1125 }
1034 1126
1035 1127 if (Assembler::is_simm13(-framesize)) {
1036 1128 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1037 1129 } else {
1038 1130 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1039 1131 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1040 1132 st->print ("SAVE R_SP,R_G3,R_SP");
1041 1133 }
1042 1134
1043 1135 }
1044 1136 #endif
1045 1137
1046 1138 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1047 1139 Compile* C = ra_->C;
1048 1140 MacroAssembler _masm(&cbuf);
1049 1141
1050 1142 for (int i = 0; i < OptoPrologueNops; i++) {
1051 1143 __ nop();
1052 1144 }
1053 1145
1054 1146 __ verify_thread();
1055 1147
1056 1148 size_t framesize = C->frame_slots() << LogBytesPerInt;
1057 1149 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1058 1150 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1059 1151
1060 1152 // Calls to C2R adapters often do not accept exceptional returns.
1061 1153 // We require that their callers must bang for them. But be careful, because
1062 1154 // some VM calls (such as call site linkage) can use several kilobytes of
1063 1155 // stack. But the stack safety zone should account for that.
1064 1156 // See bugs 4446381, 4468289, 4497237.
1065 1157 if (C->need_stack_bang(framesize)) {
1066 1158 __ generate_stack_overflow_check(framesize);
1067 1159 }
1068 1160
1069 1161 if (Assembler::is_simm13(-framesize)) {
1070 1162 __ save(SP, -framesize, SP);
1071 1163 } else {
1072 1164 __ sethi(-framesize & ~0x3ff, G3);
1073 1165 __ add(G3, -framesize & 0x3ff, G3);
1074 1166 __ save(SP, G3, SP);
1075 1167 }
1076 1168 C->set_frame_complete( __ offset() );
1077 1169 }
1078 1170
1079 1171 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1080 1172 return MachNode::size(ra_);
1081 1173 }
1082 1174
1083 1175 int MachPrologNode::reloc() const {
1084 1176 return 10; // a large enough number
1085 1177 }
1086 1178
1087 1179 //=============================================================================
1088 1180 #ifndef PRODUCT
1089 1181 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1090 1182 Compile* C = ra_->C;
1091 1183
1092 1184 if( do_polling() && ra_->C->is_method_compilation() ) {
1093 1185 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1094 1186 #ifdef _LP64
1095 1187 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1096 1188 #else
1097 1189 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1098 1190 #endif
1099 1191 }
1100 1192
1101 1193 if( do_polling() )
1102 1194 st->print("RET\n\t");
1103 1195
1104 1196 st->print("RESTORE");
1105 1197 }
1106 1198 #endif
1107 1199
1108 1200 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1109 1201 MacroAssembler _masm(&cbuf);
1110 1202 Compile* C = ra_->C;
1111 1203
1112 1204 __ verify_thread();
1113 1205
1114 1206 // If this does safepoint polling, then do it here
1115 1207 if( do_polling() && ra_->C->is_method_compilation() ) {
1116 1208 AddressLiteral polling_page(os::get_polling_page());
1117 1209 __ sethi(polling_page, L0);
1118 1210 __ relocate(relocInfo::poll_return_type);
1119 1211 __ ld_ptr( L0, 0, G0 );
1120 1212 }
1121 1213
1122 1214 // If this is a return, then stuff the restore in the delay slot
1123 1215 if( do_polling() ) {
1124 1216 __ ret();
1125 1217 __ delayed()->restore();
1126 1218 } else {
1127 1219 __ restore();
1128 1220 }
1129 1221 }
1130 1222
1131 1223 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1132 1224 return MachNode::size(ra_);
1133 1225 }
1134 1226
1135 1227 int MachEpilogNode::reloc() const {
1136 1228 return 16; // a large enough number
1137 1229 }
1138 1230
1139 1231 const Pipeline * MachEpilogNode::pipeline() const {
1140 1232 return MachNode::pipeline_class();
1141 1233 }
1142 1234
1143 1235 int MachEpilogNode::safepoint_offset() const {
1144 1236 assert( do_polling(), "no return for this epilog node");
1145 1237 return MacroAssembler::size_of_sethi(os::get_polling_page());
1146 1238 }
1147 1239
1148 1240 //=============================================================================
1149 1241
1150 1242 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1151 1243 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1152 1244 static enum RC rc_class( OptoReg::Name reg ) {
1153 1245 if( !OptoReg::is_valid(reg) ) return rc_bad;
1154 1246 if (OptoReg::is_stack(reg)) return rc_stack;
1155 1247 VMReg r = OptoReg::as_VMReg(reg);
1156 1248 if (r->is_Register()) return rc_int;
1157 1249 assert(r->is_FloatRegister(), "must be");
1158 1250 return rc_float;
1159 1251 }
1160 1252
1161 1253 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1162 1254 if( cbuf ) {
1163 1255 // Better yet would be some mechanism to handle variable-size matches correctly
1164 1256 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1165 1257 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1166 1258 } else {
1167 1259 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1168 1260 }
1169 1261 }
1170 1262 #ifndef PRODUCT
1171 1263 else if( !do_size ) {
1172 1264 if( size != 0 ) st->print("\n\t");
1173 1265 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1174 1266 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1175 1267 }
1176 1268 #endif
1177 1269 return size+4;
1178 1270 }
1179 1271
1180 1272 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1181 1273 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1182 1274 #ifndef PRODUCT
1183 1275 else if( !do_size ) {
1184 1276 if( size != 0 ) st->print("\n\t");
1185 1277 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1186 1278 }
1187 1279 #endif
1188 1280 return size+4;
1189 1281 }
1190 1282
1191 1283 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1192 1284 PhaseRegAlloc *ra_,
1193 1285 bool do_size,
1194 1286 outputStream* st ) const {
1195 1287 // Get registers to move
1196 1288 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1197 1289 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1198 1290 OptoReg::Name dst_second = ra_->get_reg_second(this );
1199 1291 OptoReg::Name dst_first = ra_->get_reg_first(this );
1200 1292
1201 1293 enum RC src_second_rc = rc_class(src_second);
1202 1294 enum RC src_first_rc = rc_class(src_first);
1203 1295 enum RC dst_second_rc = rc_class(dst_second);
1204 1296 enum RC dst_first_rc = rc_class(dst_first);
1205 1297
1206 1298 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1207 1299
1208 1300 // Generate spill code!
1209 1301 int size = 0;
1210 1302
1211 1303 if( src_first == dst_first && src_second == dst_second )
1212 1304 return size; // Self copy, no move
1213 1305
1214 1306 // --------------------------------------
1215 1307 // Check for mem-mem move. Load into unused float registers and fall into
1216 1308 // the float-store case.
1217 1309 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1218 1310 int offset = ra_->reg2offset(src_first);
1219 1311 // Further check for aligned-adjacent pair, so we can use a double load
1220 1312 if( (src_first&1)==0 && src_first+1 == src_second ) {
1221 1313 src_second = OptoReg::Name(R_F31_num);
1222 1314 src_second_rc = rc_float;
1223 1315 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1224 1316 } else {
1225 1317 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1226 1318 }
1227 1319 src_first = OptoReg::Name(R_F30_num);
1228 1320 src_first_rc = rc_float;
1229 1321 }
1230 1322
1231 1323 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1232 1324 int offset = ra_->reg2offset(src_second);
1233 1325 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1234 1326 src_second = OptoReg::Name(R_F31_num);
1235 1327 src_second_rc = rc_float;
1236 1328 }
1237 1329
1238 1330 // --------------------------------------
1239 1331 // Check for float->int copy; requires a trip through memory
1240 1332 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1241 1333 int offset = frame::register_save_words*wordSize;
1242 1334 if( cbuf ) {
1243 1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1244 1336 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1245 1337 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1246 1338 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1247 1339 }
1248 1340 #ifndef PRODUCT
1249 1341 else if( !do_size ) {
1250 1342 if( size != 0 ) st->print("\n\t");
1251 1343 st->print( "SUB R_SP,16,R_SP\n");
1252 1344 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1253 1345 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1254 1346 st->print("\tADD R_SP,16,R_SP\n");
1255 1347 }
1256 1348 #endif
1257 1349 size += 16;
1258 1350 }
1259 1351
1260 1352 // --------------------------------------
1261 1353 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1262 1354 // In such cases, I have to do the big-endian swap. For aligned targets, the
1263 1355 // hardware does the flop for me. Doubles are always aligned, so no problem
1264 1356 // there. Misaligned sources only come from native-long-returns (handled
1265 1357 // special below).
1266 1358 #ifndef _LP64
1267 1359 if( src_first_rc == rc_int && // source is already big-endian
1268 1360 src_second_rc != rc_bad && // 64-bit move
1269 1361 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1270 1362 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1271 1363 // Do the big-endian flop.
1272 1364 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1273 1365 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1274 1366 }
1275 1367 #endif
1276 1368
1277 1369 // --------------------------------------
1278 1370 // Check for integer reg-reg copy
1279 1371 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1280 1372 #ifndef _LP64
1281 1373 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1282 1374 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1283 1375 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1284 1376 // operand contains the least significant word of the 64-bit value and vice versa.
1285 1377 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1286 1378 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1287 1379 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1288 1380 if( cbuf ) {
1289 1381 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1290 1382 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1291 1383 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1292 1384 #ifndef PRODUCT
1293 1385 } else if( !do_size ) {
1294 1386 if( size != 0 ) st->print("\n\t");
1295 1387 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1296 1388 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1297 1389 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1298 1390 #endif
1299 1391 }
1300 1392 return size+12;
1301 1393 }
1302 1394 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1303 1395 // returning a long value in I0/I1
1304 1396 // a SpillCopy must be able to target a return instruction's reg_class
1305 1397 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1306 1398 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1307 1399 // operand contains the least significant word of the 64-bit value and vice versa.
1308 1400 OptoReg::Name tdest = dst_first;
1309 1401
1310 1402 if (src_first == dst_first) {
1311 1403 tdest = OptoReg::Name(R_O7_num);
1312 1404 size += 4;
1313 1405 }
1314 1406
1315 1407 if( cbuf ) {
1316 1408 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1317 1409 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1318 1410 // ShrL_reg_imm6
1319 1411 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1320 1412 // ShrR_reg_imm6 src, 0, dst
1321 1413 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1322 1414 if (tdest != dst_first) {
1323 1415 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1324 1416 }
1325 1417 }
1326 1418 #ifndef PRODUCT
1327 1419 else if( !do_size ) {
1328 1420 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1329 1421 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1330 1422 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1331 1423 if (tdest != dst_first) {
1332 1424 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1333 1425 }
1334 1426 }
1335 1427 #endif // PRODUCT
1336 1428 return size+8;
1337 1429 }
1338 1430 #endif // !_LP64
1339 1431 // Else normal reg-reg copy
1340 1432 assert( src_second != dst_first, "smashed second before evacuating it" );
1341 1433 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1342 1434 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1343 1435 // This moves an aligned adjacent pair.
1344 1436 // See if we are done.
1345 1437 if( src_first+1 == src_second && dst_first+1 == dst_second )
1346 1438 return size;
1347 1439 }
1348 1440
1349 1441 // Check for integer store
1350 1442 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1351 1443 int offset = ra_->reg2offset(dst_first);
1352 1444 // Further check for aligned-adjacent pair, so we can use a double store
1353 1445 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1354 1446 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1355 1447 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1356 1448 }
1357 1449
1358 1450 // Check for integer load
1359 1451 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1360 1452 int offset = ra_->reg2offset(src_first);
1361 1453 // Further check for aligned-adjacent pair, so we can use a double load
1362 1454 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1363 1455 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1364 1456 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1365 1457 }
1366 1458
1367 1459 // Check for float reg-reg copy
1368 1460 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1369 1461 // Further check for aligned-adjacent pair, so we can use a double move
1370 1462 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1371 1463 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1372 1464 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1373 1465 }
1374 1466
1375 1467 // Check for float store
1376 1468 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1377 1469 int offset = ra_->reg2offset(dst_first);
1378 1470 // Further check for aligned-adjacent pair, so we can use a double store
1379 1471 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1380 1472 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1381 1473 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1382 1474 }
1383 1475
1384 1476 // Check for float load
1385 1477 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1386 1478 int offset = ra_->reg2offset(src_first);
1387 1479 // Further check for aligned-adjacent pair, so we can use a double load
1388 1480 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1389 1481 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1390 1482 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1391 1483 }
1392 1484
1393 1485 // --------------------------------------------------------------------
1394 1486 // Check for hi bits still needing moving. Only happens for misaligned
1395 1487 // arguments to native calls.
1396 1488 if( src_second == dst_second )
1397 1489 return size; // Self copy; no move
1398 1490 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1399 1491
1400 1492 #ifndef _LP64
1401 1493 // In the LP64 build, all registers can be moved as aligned/adjacent
1402 1494 // pairs, so there's never any need to move the high bits separately.
1403 1495 // The 32-bit builds have to deal with the 32-bit ABI which can force
1404 1496 // all sorts of silly alignment problems.
1405 1497
1406 1498 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1407 1499 // 32-bits of a 64-bit register, but are needed in low bits of another
1408 1500 // register (else it's a hi-bits-to-hi-bits copy which should have
1409 1501 // happened already as part of a 64-bit move)
1410 1502 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1411 1503 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1412 1504 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1413 1505 // Shift src_second down to dst_second's low bits.
1414 1506 if( cbuf ) {
1415 1507 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1416 1508 #ifndef PRODUCT
1417 1509 } else if( !do_size ) {
1418 1510 if( size != 0 ) st->print("\n\t");
1419 1511 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1420 1512 #endif
1421 1513 }
1422 1514 return size+4;
1423 1515 }
1424 1516
1425 1517 // Check for high word integer store. Must down-shift the hi bits
1426 1518 // into a temp register, then fall into the case of storing int bits.
1427 1519 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1428 1520 // Shift src_second down to dst_second's low bits.
1429 1521 if( cbuf ) {
1430 1522 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1431 1523 #ifndef PRODUCT
1432 1524 } else if( !do_size ) {
1433 1525 if( size != 0 ) st->print("\n\t");
1434 1526 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1435 1527 #endif
1436 1528 }
1437 1529 size+=4;
1438 1530 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1439 1531 }
1440 1532
1441 1533 // Check for high word integer load
1442 1534 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1443 1535 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1444 1536
1445 1537 // Check for high word integer store
1446 1538 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1447 1539 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1448 1540
1449 1541 // Check for high word float store
1450 1542 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1451 1543 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1452 1544
1453 1545 #endif // !_LP64
1454 1546
1455 1547 Unimplemented();
1456 1548 }
1457 1549
1458 1550 #ifndef PRODUCT
1459 1551 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1460 1552 implementation( NULL, ra_, false, st );
1461 1553 }
1462 1554 #endif
1463 1555
1464 1556 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1465 1557 implementation( &cbuf, ra_, false, NULL );
1466 1558 }
1467 1559
1468 1560 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1469 1561 return implementation( NULL, ra_, true, NULL );
1470 1562 }
1471 1563
1472 1564 //=============================================================================
1473 1565 #ifndef PRODUCT
1474 1566 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1475 1567 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1476 1568 }
1477 1569 #endif
1478 1570
1479 1571 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1480 1572 MacroAssembler _masm(&cbuf);
1481 1573 for(int i = 0; i < _count; i += 1) {
1482 1574 __ nop();
1483 1575 }
1484 1576 }
1485 1577
1486 1578 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1487 1579 return 4 * _count;
1488 1580 }
1489 1581
1490 1582
1491 1583 //=============================================================================
1492 1584 #ifndef PRODUCT
1493 1585 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1494 1586 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1495 1587 int reg = ra_->get_reg_first(this);
1496 1588 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1497 1589 }
1498 1590 #endif
1499 1591
1500 1592 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 1593 MacroAssembler _masm(&cbuf);
1502 1594 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1503 1595 int reg = ra_->get_encode(this);
1504 1596
1505 1597 if (Assembler::is_simm13(offset)) {
1506 1598 __ add(SP, offset, reg_to_register_object(reg));
1507 1599 } else {
1508 1600 __ set(offset, O7);
1509 1601 __ add(SP, O7, reg_to_register_object(reg));
1510 1602 }
1511 1603 }
1512 1604
1513 1605 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1514 1606 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1515 1607 assert(ra_ == ra_->C->regalloc(), "sanity");
1516 1608 return ra_->C->scratch_emit_size(this);
1517 1609 }
1518 1610
1519 1611 //=============================================================================
1520 1612
1521 1613 // emit call stub, compiled java to interpretor
1522 1614 void emit_java_to_interp(CodeBuffer &cbuf ) {
1523 1615
1524 1616 // Stub is fixed up when the corresponding call is converted from calling
1525 1617 // compiled code to calling interpreted code.
1526 1618 // set (empty), G5
1527 1619 // jmp -1
1528 1620
1529 1621 address mark = cbuf.insts_mark(); // get mark within main instrs section
1530 1622
1531 1623 MacroAssembler _masm(&cbuf);
1532 1624
1533 1625 address base =
1534 1626 __ start_a_stub(Compile::MAX_stubs_size);
1535 1627 if (base == NULL) return; // CodeBuffer::expand failed
1536 1628
1537 1629 // static stub relocation stores the instruction address of the call
1538 1630 __ relocate(static_stub_Relocation::spec(mark));
1539 1631
1540 1632 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1541 1633
1542 1634 __ set_inst_mark();
1543 1635 AddressLiteral addrlit(-1);
1544 1636 __ JUMP(addrlit, G3, 0);
1545 1637
1546 1638 __ delayed()->nop();
1547 1639
1548 1640 // Update current stubs pointer and restore code_end.
1549 1641 __ end_a_stub();
1550 1642 }
1551 1643
1552 1644 // size of call stub, compiled java to interpretor
1553 1645 uint size_java_to_interp() {
1554 1646 // This doesn't need to be accurate but it must be larger or equal to
1555 1647 // the real size of the stub.
1556 1648 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1557 1649 NativeJump::instruction_size + // sethi; jmp; nop
1558 1650 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1559 1651 }
1560 1652 // relocation entries for call stub, compiled java to interpretor
1561 1653 uint reloc_java_to_interp() {
1562 1654 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1563 1655 }
1564 1656
1565 1657
1566 1658 //=============================================================================
1567 1659 #ifndef PRODUCT
1568 1660 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1569 1661 st->print_cr("\nUEP:");
1570 1662 #ifdef _LP64
1571 1663 if (UseCompressedOops) {
1572 1664 assert(Universe::heap() != NULL, "java heap should be initialized");
1573 1665 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1574 1666 st->print_cr("\tSLL R_G5,3,R_G5");
1575 1667 if (Universe::narrow_oop_base() != NULL)
1576 1668 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1577 1669 } else {
1578 1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1579 1671 }
1580 1672 st->print_cr("\tCMP R_G5,R_G3" );
1581 1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1582 1674 #else // _LP64
1583 1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1584 1676 st->print_cr("\tCMP R_G5,R_G3" );
1585 1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1586 1678 #endif // _LP64
1587 1679 }
1588 1680 #endif
1589 1681
1590 1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1591 1683 MacroAssembler _masm(&cbuf);
1592 1684 Label L;
1593 1685 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1594 1686 Register temp_reg = G3;
1595 1687 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1596 1688
1597 1689 // Load klass from receiver
1598 1690 __ load_klass(O0, temp_reg);
1599 1691 // Compare against expected klass
1600 1692 __ cmp(temp_reg, G5_ic_reg);
1601 1693 // Branch to miss code, checks xcc or icc depending
1602 1694 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1603 1695 }
1604 1696
1605 1697 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1606 1698 return MachNode::size(ra_);
1607 1699 }
1608 1700
1609 1701
1610 1702 //=============================================================================
1611 1703
1612 1704 uint size_exception_handler() {
1613 1705 if (TraceJumps) {
1614 1706 return (400); // just a guess
1615 1707 }
1616 1708 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1617 1709 }
1618 1710
1619 1711 uint size_deopt_handler() {
1620 1712 if (TraceJumps) {
1621 1713 return (400); // just a guess
1622 1714 }
1623 1715 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1624 1716 }
1625 1717
1626 1718 // Emit exception handler code.
1627 1719 int emit_exception_handler(CodeBuffer& cbuf) {
1628 1720 Register temp_reg = G3;
1629 1721 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1630 1722 MacroAssembler _masm(&cbuf);
1631 1723
1632 1724 address base =
1633 1725 __ start_a_stub(size_exception_handler());
1634 1726 if (base == NULL) return 0; // CodeBuffer::expand failed
1635 1727
1636 1728 int offset = __ offset();
1637 1729
1638 1730 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1639 1731 __ delayed()->nop();
1640 1732
1641 1733 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1642 1734
1643 1735 __ end_a_stub();
1644 1736
1645 1737 return offset;
1646 1738 }
1647 1739
1648 1740 int emit_deopt_handler(CodeBuffer& cbuf) {
1649 1741 // Can't use any of the current frame's registers as we may have deopted
1650 1742 // at a poll and everything (including G3) can be live.
1651 1743 Register temp_reg = L0;
1652 1744 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1653 1745 MacroAssembler _masm(&cbuf);
1654 1746
1655 1747 address base =
1656 1748 __ start_a_stub(size_deopt_handler());
1657 1749 if (base == NULL) return 0; // CodeBuffer::expand failed
1658 1750
1659 1751 int offset = __ offset();
1660 1752 __ save_frame(0);
1661 1753 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1662 1754 __ delayed()->restore();
1663 1755
1664 1756 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1665 1757
1666 1758 __ end_a_stub();
1667 1759 return offset;
1668 1760
1669 1761 }
1670 1762
1671 1763 // Given a register encoding, produce a Integer Register object
1672 1764 static Register reg_to_register_object(int register_encoding) {
1673 1765 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1674 1766 return as_Register(register_encoding);
1675 1767 }
1676 1768
1677 1769 // Given a register encoding, produce a single-precision Float Register object
1678 1770 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1679 1771 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1680 1772 return as_SingleFloatRegister(register_encoding);
1681 1773 }
1682 1774
1683 1775 // Given a register encoding, produce a double-precision Float Register object
1684 1776 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1685 1777 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1686 1778 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1687 1779 return as_DoubleFloatRegister(register_encoding);
1688 1780 }
1689 1781
1690 1782 const bool Matcher::match_rule_supported(int opcode) {
1691 1783 if (!has_match_rule(opcode))
1692 1784 return false;
1693 1785
1694 1786 switch (opcode) {
1695 1787 case Op_CountLeadingZerosI:
1696 1788 case Op_CountLeadingZerosL:
1697 1789 case Op_CountTrailingZerosI:
1698 1790 case Op_CountTrailingZerosL:
1699 1791 if (!UsePopCountInstruction)
1700 1792 return false;
1701 1793 break;
1702 1794 }
1703 1795
1704 1796 return true; // Per default match rules are supported.
1705 1797 }
1706 1798
1707 1799 int Matcher::regnum_to_fpu_offset(int regnum) {
1708 1800 return regnum - 32; // The FP registers are in the second chunk
1709 1801 }
1710 1802
1711 1803 #ifdef ASSERT
1712 1804 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1713 1805 #endif
1714 1806
1715 1807 // Vector width in bytes
1716 1808 const uint Matcher::vector_width_in_bytes(void) {
1717 1809 return 8;
1718 1810 }
1719 1811
1720 1812 // Vector ideal reg
1721 1813 const uint Matcher::vector_ideal_reg(void) {
1722 1814 return Op_RegD;
1723 1815 }
1724 1816
1725 1817 // USII supports fxtof through the whole range of number, USIII doesn't
1726 1818 const bool Matcher::convL2FSupported(void) {
1727 1819 return VM_Version::has_fast_fxtof();
1728 1820 }
1729 1821
1730 1822 // Is this branch offset short enough that a short branch can be used?
1731 1823 //
1732 1824 // NOTE: If the platform does not provide any short branch variants, then
1733 1825 // this method should return false for offset 0.
1734 1826 bool Matcher::is_short_branch_offset(int rule, int offset) {
1735 1827 return false;
1736 1828 }
1737 1829
1738 1830 const bool Matcher::isSimpleConstant64(jlong value) {
1739 1831 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1740 1832 // Depends on optimizations in MacroAssembler::setx.
1741 1833 int hi = (int)(value >> 32);
1742 1834 int lo = (int)(value & ~0);
1743 1835 return (hi == 0) || (hi == -1) || (lo == 0);
1744 1836 }
1745 1837
1746 1838 // No scaling for the parameter the ClearArray node.
1747 1839 const bool Matcher::init_array_count_is_in_bytes = true;
1748 1840
1749 1841 // Threshold size for cleararray.
1750 1842 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1751 1843
1752 1844 // Should the Matcher clone shifts on addressing modes, expecting them to
1753 1845 // be subsumed into complex addressing expressions or compute them into
1754 1846 // registers? True for Intel but false for most RISCs
1755 1847 const bool Matcher::clone_shift_expressions = false;
1756 1848
1757 1849 bool Matcher::narrow_oop_use_complex_address() {
1758 1850 NOT_LP64(ShouldNotCallThis());
1759 1851 assert(UseCompressedOops, "only for compressed oops code");
1760 1852 return false;
1761 1853 }
1762 1854
1763 1855 // Is it better to copy float constants, or load them directly from memory?
1764 1856 // Intel can load a float constant from a direct address, requiring no
1765 1857 // extra registers. Most RISCs will have to materialize an address into a
1766 1858 // register first, so they would do better to copy the constant from stack.
1767 1859 const bool Matcher::rematerialize_float_constants = false;
1768 1860
1769 1861 // If CPU can load and store mis-aligned doubles directly then no fixup is
1770 1862 // needed. Else we split the double into 2 integer pieces and move it
1771 1863 // piece-by-piece. Only happens when passing doubles into C code as the
1772 1864 // Java calling convention forces doubles to be aligned.
1773 1865 #ifdef _LP64
1774 1866 const bool Matcher::misaligned_doubles_ok = true;
1775 1867 #else
1776 1868 const bool Matcher::misaligned_doubles_ok = false;
1777 1869 #endif
1778 1870
1779 1871 // No-op on SPARC.
1780 1872 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1781 1873 }
1782 1874
1783 1875 // Advertise here if the CPU requires explicit rounding operations
1784 1876 // to implement the UseStrictFP mode.
1785 1877 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1786 1878
1787 1879 // Are floats conerted to double when stored to stack during deoptimization?
1788 1880 // Sparc does not handle callee-save floats.
1789 1881 bool Matcher::float_in_double() { return false; }
1790 1882
1791 1883 // Do ints take an entire long register or just half?
1792 1884 // Note that we if-def off of _LP64.
1793 1885 // The relevant question is how the int is callee-saved. In _LP64
1794 1886 // the whole long is written but de-opt'ing will have to extract
1795 1887 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1796 1888 #ifdef _LP64
1797 1889 const bool Matcher::int_in_long = true;
1798 1890 #else
1799 1891 const bool Matcher::int_in_long = false;
1800 1892 #endif
1801 1893
1802 1894 // Return whether or not this register is ever used as an argument. This
1803 1895 // function is used on startup to build the trampoline stubs in generateOptoStub.
1804 1896 // Registers not mentioned will be killed by the VM call in the trampoline, and
1805 1897 // arguments in those registers not be available to the callee.
1806 1898 bool Matcher::can_be_java_arg( int reg ) {
1807 1899 // Standard sparc 6 args in registers
1808 1900 if( reg == R_I0_num ||
1809 1901 reg == R_I1_num ||
1810 1902 reg == R_I2_num ||
1811 1903 reg == R_I3_num ||
1812 1904 reg == R_I4_num ||
1813 1905 reg == R_I5_num ) return true;
1814 1906 #ifdef _LP64
1815 1907 // 64-bit builds can pass 64-bit pointers and longs in
1816 1908 // the high I registers
1817 1909 if( reg == R_I0H_num ||
1818 1910 reg == R_I1H_num ||
1819 1911 reg == R_I2H_num ||
1820 1912 reg == R_I3H_num ||
1821 1913 reg == R_I4H_num ||
1822 1914 reg == R_I5H_num ) return true;
1823 1915
1824 1916 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1825 1917 return true;
1826 1918 }
1827 1919
1828 1920 #else
1829 1921 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1830 1922 // Longs cannot be passed in O regs, because O regs become I regs
1831 1923 // after a 'save' and I regs get their high bits chopped off on
1832 1924 // interrupt.
1833 1925 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1834 1926 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1835 1927 #endif
1836 1928 // A few float args in registers
1837 1929 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1838 1930
1839 1931 return false;
1840 1932 }
1841 1933
1842 1934 bool Matcher::is_spillable_arg( int reg ) {
1843 1935 return can_be_java_arg(reg);
1844 1936 }
1845 1937
1846 1938 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1847 1939 // Use hardware SDIVX instruction when it is
1848 1940 // faster than a code which use multiply.
1849 1941 return VM_Version::has_fast_idiv();
1850 1942 }
1851 1943
1852 1944 // Register for DIVI projection of divmodI
1853 1945 RegMask Matcher::divI_proj_mask() {
1854 1946 ShouldNotReachHere();
1855 1947 return RegMask();
1856 1948 }
1857 1949
1858 1950 // Register for MODI projection of divmodI
1859 1951 RegMask Matcher::modI_proj_mask() {
1860 1952 ShouldNotReachHere();
1861 1953 return RegMask();
1862 1954 }
1863 1955
1864 1956 // Register for DIVL projection of divmodL
1865 1957 RegMask Matcher::divL_proj_mask() {
1866 1958 ShouldNotReachHere();
1867 1959 return RegMask();
1868 1960 }
1869 1961
1870 1962 // Register for MODL projection of divmodL
1871 1963 RegMask Matcher::modL_proj_mask() {
1872 1964 ShouldNotReachHere();
1873 1965 return RegMask();
1874 1966 }
1875 1967
1876 1968 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1877 1969 return L7_REGP_mask;
1878 1970 }
1879 1971
1880 1972 %}
1881 1973
1882 1974
1883 1975 // The intptr_t operand types, defined by textual substitution.
1884 1976 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1885 1977 #ifdef _LP64
1886 1978 #define immX immL
1887 1979 #define immX13 immL13
1888 1980 #define immX13m7 immL13m7
1889 1981 #define iRegX iRegL
1890 1982 #define g1RegX g1RegL
1891 1983 #else
1892 1984 #define immX immI
1893 1985 #define immX13 immI13
1894 1986 #define immX13m7 immI13m7
1895 1987 #define iRegX iRegI
1896 1988 #define g1RegX g1RegI
1897 1989 #endif
1898 1990
1899 1991 //----------ENCODING BLOCK-----------------------------------------------------
1900 1992 // This block specifies the encoding classes used by the compiler to output
1901 1993 // byte streams. Encoding classes are parameterized macros used by
1902 1994 // Machine Instruction Nodes in order to generate the bit encoding of the
1903 1995 // instruction. Operands specify their base encoding interface with the
1904 1996 // interface keyword. There are currently supported four interfaces,
1905 1997 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1906 1998 // operand to generate a function which returns its register number when
1907 1999 // queried. CONST_INTER causes an operand to generate a function which
1908 2000 // returns the value of the constant when queried. MEMORY_INTER causes an
1909 2001 // operand to generate four functions which return the Base Register, the
1910 2002 // Index Register, the Scale Value, and the Offset Value of the operand when
1911 2003 // queried. COND_INTER causes an operand to generate six functions which
1912 2004 // return the encoding code (ie - encoding bits for the instruction)
1913 2005 // associated with each basic boolean condition for a conditional instruction.
1914 2006 //
1915 2007 // Instructions specify two basic values for encoding. Again, a function
1916 2008 // is available to check if the constant displacement is an oop. They use the
1917 2009 // ins_encode keyword to specify their encoding classes (which must be
1918 2010 // a sequence of enc_class names, and their parameters, specified in
1919 2011 // the encoding block), and they use the
1920 2012 // opcode keyword to specify, in order, their primary, secondary, and
1921 2013 // tertiary opcode. Only the opcode sections which a particular instruction
1922 2014 // needs for encoding need to be specified.
1923 2015 encode %{
1924 2016 enc_class enc_untested %{
1925 2017 #ifdef ASSERT
1926 2018 MacroAssembler _masm(&cbuf);
1927 2019 __ untested("encoding");
1928 2020 #endif
1929 2021 %}
1930 2022
1931 2023 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1932 2024 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1933 2025 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1934 2026 %}
1935 2027
1936 2028 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1937 2029 emit_form3_mem_reg(cbuf, this, $primary, -1,
1938 2030 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1939 2031 %}
1940 2032
1941 2033 enc_class form3_mem_prefetch_read( memory mem ) %{
1942 2034 emit_form3_mem_reg(cbuf, this, $primary, -1,
1943 2035 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1944 2036 %}
1945 2037
1946 2038 enc_class form3_mem_prefetch_write( memory mem ) %{
1947 2039 emit_form3_mem_reg(cbuf, this, $primary, -1,
1948 2040 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1949 2041 %}
1950 2042
1951 2043 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1952 2044 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1953 2045 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1954 2046 guarantee($mem$$index == R_G0_enc, "double index?");
1955 2047 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1956 2048 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1957 2049 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1958 2050 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1959 2051 %}
1960 2052
1961 2053 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1962 2054 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1963 2055 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1964 2056 guarantee($mem$$index == R_G0_enc, "double index?");
1965 2057 // Load long with 2 instructions
1966 2058 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1967 2059 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1968 2060 %}
1969 2061
1970 2062 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1971 2063 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1972 2064 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1973 2065 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1974 2066 %}
1975 2067
1976 2068 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1977 2069 // Encode a reg-reg copy. If it is useless, then empty encoding.
1978 2070 if( $rs2$$reg != $rd$$reg )
1979 2071 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1980 2072 %}
1981 2073
1982 2074 // Target lo half of long
1983 2075 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1984 2076 // Encode a reg-reg copy. If it is useless, then empty encoding.
1985 2077 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1986 2078 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1987 2079 %}
1988 2080
1989 2081 // Source lo half of long
1990 2082 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1991 2083 // Encode a reg-reg copy. If it is useless, then empty encoding.
1992 2084 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1993 2085 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1994 2086 %}
1995 2087
1996 2088 // Target hi half of long
1997 2089 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1998 2090 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1999 2091 %}
2000 2092
2001 2093 // Source lo half of long, and leave it sign extended.
2002 2094 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2003 2095 // Sign extend low half
2004 2096 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2005 2097 %}
2006 2098
2007 2099 // Source hi half of long, and leave it sign extended.
2008 2100 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2009 2101 // Shift high half to low half
2010 2102 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2011 2103 %}
2012 2104
2013 2105 // Source hi half of long
2014 2106 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2015 2107 // Encode a reg-reg copy. If it is useless, then empty encoding.
2016 2108 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2017 2109 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2018 2110 %}
2019 2111
2020 2112 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2021 2113 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2022 2114 %}
2023 2115
2024 2116 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2025 2117 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2026 2118 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2027 2119 %}
2028 2120
2029 2121 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2030 2122 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2031 2123 // clear if nothing else is happening
2032 2124 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2033 2125 // blt,a,pn done
2034 2126 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2035 2127 // mov dst,-1 in delay slot
2036 2128 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2037 2129 %}
2038 2130
2039 2131 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2040 2132 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2041 2133 %}
2042 2134
2043 2135 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2044 2136 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2045 2137 %}
2046 2138
2047 2139 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2048 2140 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2049 2141 %}
2050 2142
2051 2143 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2052 2144 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2053 2145 %}
2054 2146
2055 2147 enc_class move_return_pc_to_o1() %{
2056 2148 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2057 2149 %}
2058 2150
2059 2151 #ifdef _LP64
2060 2152 /* %%% merge with enc_to_bool */
2061 2153 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2062 2154 MacroAssembler _masm(&cbuf);
2063 2155
2064 2156 Register src_reg = reg_to_register_object($src$$reg);
2065 2157 Register dst_reg = reg_to_register_object($dst$$reg);
2066 2158 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2067 2159 %}
2068 2160 #endif
2069 2161
2070 2162 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2071 2163 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2072 2164 MacroAssembler _masm(&cbuf);
2073 2165
2074 2166 Register p_reg = reg_to_register_object($p$$reg);
2075 2167 Register q_reg = reg_to_register_object($q$$reg);
2076 2168 Register y_reg = reg_to_register_object($y$$reg);
2077 2169 Register tmp_reg = reg_to_register_object($tmp$$reg);
2078 2170
2079 2171 __ subcc( p_reg, q_reg, p_reg );
2080 2172 __ add ( p_reg, y_reg, tmp_reg );
2081 2173 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2082 2174 %}
2083 2175
2084 2176 enc_class form_d2i_helper(regD src, regF dst) %{
2085 2177 // fcmp %fcc0,$src,$src
2086 2178 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2087 2179 // branch %fcc0 not-nan, predict taken
2088 2180 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2089 2181 // fdtoi $src,$dst
2090 2182 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2091 2183 // fitos $dst,$dst (if nan)
2092 2184 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2093 2185 // clear $dst (if nan)
2094 2186 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2095 2187 // carry on here...
2096 2188 %}
2097 2189
2098 2190 enc_class form_d2l_helper(regD src, regD dst) %{
2099 2191 // fcmp %fcc0,$src,$src check for NAN
2100 2192 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2101 2193 // branch %fcc0 not-nan, predict taken
2102 2194 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2103 2195 // fdtox $src,$dst convert in delay slot
2104 2196 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2105 2197 // fxtod $dst,$dst (if nan)
2106 2198 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2107 2199 // clear $dst (if nan)
2108 2200 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2109 2201 // carry on here...
2110 2202 %}
2111 2203
2112 2204 enc_class form_f2i_helper(regF src, regF dst) %{
2113 2205 // fcmps %fcc0,$src,$src
2114 2206 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2115 2207 // branch %fcc0 not-nan, predict taken
2116 2208 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2117 2209 // fstoi $src,$dst
2118 2210 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2119 2211 // fitos $dst,$dst (if nan)
2120 2212 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2121 2213 // clear $dst (if nan)
2122 2214 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2123 2215 // carry on here...
2124 2216 %}
2125 2217
2126 2218 enc_class form_f2l_helper(regF src, regD dst) %{
2127 2219 // fcmps %fcc0,$src,$src
2128 2220 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2129 2221 // branch %fcc0 not-nan, predict taken
2130 2222 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2131 2223 // fstox $src,$dst
2132 2224 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2133 2225 // fxtod $dst,$dst (if nan)
2134 2226 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2135 2227 // clear $dst (if nan)
2136 2228 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2137 2229 // carry on here...
2138 2230 %}
2139 2231
2140 2232 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2141 2233 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2142 2234 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2143 2235 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2144 2236
2145 2237 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2146 2238
2147 2239 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2148 2240 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2149 2241
2150 2242 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2151 2243 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2152 2244 %}
2153 2245
2154 2246 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2155 2247 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2156 2248 %}
2157 2249
2158 2250 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2159 2251 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2160 2252 %}
2161 2253
2162 2254 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2163 2255 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2164 2256 %}
2165 2257
2166 2258 enc_class form3_convI2F(regF rs2, regF rd) %{
2167 2259 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2168 2260 %}
2169 2261
2170 2262 // Encloding class for traceable jumps
2171 2263 enc_class form_jmpl(g3RegP dest) %{
2172 2264 emit_jmpl(cbuf, $dest$$reg);
2173 2265 %}
2174 2266
2175 2267 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2176 2268 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2177 2269 %}
2178 2270
2179 2271 enc_class form2_nop() %{
2180 2272 emit_nop(cbuf);
2181 2273 %}
2182 2274
2183 2275 enc_class form2_illtrap() %{
2184 2276 emit_illtrap(cbuf);
2185 2277 %}
2186 2278
2187 2279
2188 2280 // Compare longs and convert into -1, 0, 1.
2189 2281 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2190 2282 // CMP $src1,$src2
2191 2283 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2192 2284 // blt,a,pn done
2193 2285 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2194 2286 // mov dst,-1 in delay slot
2195 2287 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2196 2288 // bgt,a,pn done
2197 2289 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2198 2290 // mov dst,1 in delay slot
2199 2291 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2200 2292 // CLR $dst
2201 2293 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2202 2294 %}
2203 2295
2204 2296 enc_class enc_PartialSubtypeCheck() %{
2205 2297 MacroAssembler _masm(&cbuf);
2206 2298 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2207 2299 __ delayed()->nop();
2208 2300 %}
2209 2301
2210 2302 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2211 2303 MacroAssembler _masm(&cbuf);
2212 2304 Label &L = *($labl$$label);
2213 2305 Assembler::Predict predict_taken =
2214 2306 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2215 2307
2216 2308 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2217 2309 __ delayed()->nop();
2218 2310 %}
2219 2311
2220 2312 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2221 2313 MacroAssembler _masm(&cbuf);
2222 2314 Label &L = *($labl$$label);
2223 2315 Assembler::Predict predict_taken =
2224 2316 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2225 2317
2226 2318 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2227 2319 __ delayed()->nop();
2228 2320 %}
2229 2321
2230 2322 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2231 2323 MacroAssembler _masm(&cbuf);
2232 2324 Label &L = *($labl$$label);
2233 2325 Assembler::Predict predict_taken =
2234 2326 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2235 2327
2236 2328 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2237 2329 __ delayed()->nop();
2238 2330 %}
2239 2331
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2240 2332 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2241 2333 MacroAssembler _masm(&cbuf);
2242 2334 Label &L = *($labl$$label);
2243 2335 Assembler::Predict predict_taken =
2244 2336 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2245 2337
2246 2338 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2247 2339 __ delayed()->nop();
2248 2340 %}
2249 2341
2250 - enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2251 - MacroAssembler _masm(&cbuf);
2252 -
2253 - Register switch_reg = as_Register($switch_val$$reg);
2254 - Register table_reg = O7;
2255 -
2256 - address table_base = __ address_table_constant(_index2label);
2257 - RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2258 -
2259 - // Move table address into a register.
2260 - __ set(table_base, table_reg, rspec);
2261 -
2262 - // Jump to base address + switch value
2263 - __ ld_ptr(table_reg, switch_reg, table_reg);
2264 - __ jmp(table_reg, G0);
2265 - __ delayed()->nop();
2266 -
2267 - %}
2268 -
2269 2342 enc_class enc_ba( Label labl ) %{
2270 2343 MacroAssembler _masm(&cbuf);
2271 2344 Label &L = *($labl$$label);
2272 2345 __ ba(false, L);
2273 2346 __ delayed()->nop();
2274 2347 %}
2275 2348
2276 2349 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2277 2350 MacroAssembler _masm(&cbuf);
2278 2351 Label &L = *$labl$$label;
2279 2352 Assembler::Predict predict_taken =
2280 2353 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2281 2354
2282 2355 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2283 2356 __ delayed()->nop();
2284 2357 %}
2285 2358
2286 2359 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2287 2360 int op = (Assembler::arith_op << 30) |
2288 2361 ($dst$$reg << 25) |
2289 2362 (Assembler::movcc_op3 << 19) |
2290 2363 (1 << 18) | // cc2 bit for 'icc'
2291 2364 ($cmp$$cmpcode << 14) |
2292 2365 (0 << 13) | // select register move
2293 2366 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2294 2367 ($src$$reg << 0);
2295 2368 cbuf.insts()->emit_int32(op);
2296 2369 %}
2297 2370
2298 2371 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2299 2372 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2300 2373 int op = (Assembler::arith_op << 30) |
2301 2374 ($dst$$reg << 25) |
2302 2375 (Assembler::movcc_op3 << 19) |
2303 2376 (1 << 18) | // cc2 bit for 'icc'
2304 2377 ($cmp$$cmpcode << 14) |
2305 2378 (1 << 13) | // select immediate move
2306 2379 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2307 2380 (simm11 << 0);
2308 2381 cbuf.insts()->emit_int32(op);
2309 2382 %}
2310 2383
2311 2384 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2312 2385 int op = (Assembler::arith_op << 30) |
2313 2386 ($dst$$reg << 25) |
2314 2387 (Assembler::movcc_op3 << 19) |
2315 2388 (0 << 18) | // cc2 bit for 'fccX'
2316 2389 ($cmp$$cmpcode << 14) |
2317 2390 (0 << 13) | // select register move
2318 2391 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2319 2392 ($src$$reg << 0);
2320 2393 cbuf.insts()->emit_int32(op);
2321 2394 %}
2322 2395
2323 2396 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2324 2397 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2325 2398 int op = (Assembler::arith_op << 30) |
2326 2399 ($dst$$reg << 25) |
2327 2400 (Assembler::movcc_op3 << 19) |
2328 2401 (0 << 18) | // cc2 bit for 'fccX'
2329 2402 ($cmp$$cmpcode << 14) |
2330 2403 (1 << 13) | // select immediate move
2331 2404 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2332 2405 (simm11 << 0);
2333 2406 cbuf.insts()->emit_int32(op);
2334 2407 %}
2335 2408
2336 2409 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2337 2410 int op = (Assembler::arith_op << 30) |
2338 2411 ($dst$$reg << 25) |
2339 2412 (Assembler::fpop2_op3 << 19) |
2340 2413 (0 << 18) |
2341 2414 ($cmp$$cmpcode << 14) |
2342 2415 (1 << 13) | // select register move
2343 2416 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2344 2417 ($primary << 5) | // select single, double or quad
2345 2418 ($src$$reg << 0);
2346 2419 cbuf.insts()->emit_int32(op);
2347 2420 %}
2348 2421
2349 2422 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2350 2423 int op = (Assembler::arith_op << 30) |
2351 2424 ($dst$$reg << 25) |
2352 2425 (Assembler::fpop2_op3 << 19) |
2353 2426 (0 << 18) |
2354 2427 ($cmp$$cmpcode << 14) |
2355 2428 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2356 2429 ($primary << 5) | // select single, double or quad
2357 2430 ($src$$reg << 0);
2358 2431 cbuf.insts()->emit_int32(op);
2359 2432 %}
2360 2433
2361 2434 // Used by the MIN/MAX encodings. Same as a CMOV, but
2362 2435 // the condition comes from opcode-field instead of an argument.
2363 2436 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2364 2437 int op = (Assembler::arith_op << 30) |
2365 2438 ($dst$$reg << 25) |
2366 2439 (Assembler::movcc_op3 << 19) |
2367 2440 (1 << 18) | // cc2 bit for 'icc'
2368 2441 ($primary << 14) |
2369 2442 (0 << 13) | // select register move
2370 2443 (0 << 11) | // cc1, cc0 bits for 'icc'
2371 2444 ($src$$reg << 0);
2372 2445 cbuf.insts()->emit_int32(op);
2373 2446 %}
2374 2447
2375 2448 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2376 2449 int op = (Assembler::arith_op << 30) |
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2377 2450 ($dst$$reg << 25) |
2378 2451 (Assembler::movcc_op3 << 19) |
2379 2452 (6 << 16) | // cc2 bit for 'xcc'
2380 2453 ($primary << 14) |
2381 2454 (0 << 13) | // select register move
2382 2455 (0 << 11) | // cc1, cc0 bits for 'icc'
2383 2456 ($src$$reg << 0);
2384 2457 cbuf.insts()->emit_int32(op);
2385 2458 %}
2386 2459
2387 - // Utility encoding for loading a 64 bit Pointer into a register
2388 - // The 64 bit pointer is stored in the generated code stream
2389 - enc_class SetPtr( immP src, iRegP rd ) %{
2390 - Register dest = reg_to_register_object($rd$$reg);
2391 - MacroAssembler _masm(&cbuf);
2392 - // [RGV] This next line should be generated from ADLC
2393 - if ( _opnds[1]->constant_is_oop() ) {
2394 - intptr_t val = $src$$constant;
2395 - __ set_oop_constant((jobject)val, dest);
2396 - } else { // non-oop pointers, e.g. card mark base, heap top
2397 - __ set($src$$constant, dest);
2398 - }
2399 - %}
2400 -
2401 2460 enc_class Set13( immI13 src, iRegI rd ) %{
2402 2461 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2403 2462 %}
2404 2463
2405 2464 enc_class SetHi22( immI src, iRegI rd ) %{
2406 2465 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2407 2466 %}
2408 2467
2409 2468 enc_class Set32( immI src, iRegI rd ) %{
2410 2469 MacroAssembler _masm(&cbuf);
2411 2470 __ set($src$$constant, reg_to_register_object($rd$$reg));
2412 2471 %}
2413 2472
2414 - enc_class SetNull( iRegI rd ) %{
2415 - emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2416 - %}
2417 -
2418 2473 enc_class call_epilog %{
2419 2474 if( VerifyStackAtCalls ) {
2420 2475 MacroAssembler _masm(&cbuf);
2421 2476 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2422 2477 Register temp_reg = G3;
2423 2478 __ add(SP, framesize, temp_reg);
2424 2479 __ cmp(temp_reg, FP);
2425 2480 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2426 2481 }
2427 2482 %}
2428 2483
2429 2484 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2430 2485 // to G1 so the register allocator will not have to deal with the misaligned register
2431 2486 // pair.
2432 2487 enc_class adjust_long_from_native_call %{
2433 2488 #ifndef _LP64
2434 2489 if (returns_long()) {
2435 2490 // sllx O0,32,O0
2436 2491 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2437 2492 // srl O1,0,O1
2438 2493 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2439 2494 // or O0,O1,G1
2440 2495 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2441 2496 }
2442 2497 #endif
2443 2498 %}
2444 2499
2445 2500 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2446 2501 // CALL directly to the runtime
2447 2502 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2448 2503 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2449 2504 /*preserve_g2=*/true, /*force far call*/true);
2450 2505 %}
2451 2506
2452 2507 enc_class preserve_SP %{
2453 2508 MacroAssembler _masm(&cbuf);
2454 2509 __ mov(SP, L7_mh_SP_save);
2455 2510 %}
2456 2511
2457 2512 enc_class restore_SP %{
2458 2513 MacroAssembler _masm(&cbuf);
2459 2514 __ mov(L7_mh_SP_save, SP);
2460 2515 %}
2461 2516
2462 2517 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2463 2518 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2464 2519 // who we intended to call.
2465 2520 if ( !_method ) {
2466 2521 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2467 2522 } else if (_optimized_virtual) {
2468 2523 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2469 2524 } else {
2470 2525 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2471 2526 }
2472 2527 if( _method ) { // Emit stub for static call
2473 2528 emit_java_to_interp(cbuf);
2474 2529 }
2475 2530 %}
2476 2531
2477 2532 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2478 2533 MacroAssembler _masm(&cbuf);
2479 2534 __ set_inst_mark();
2480 2535 int vtable_index = this->_vtable_index;
2481 2536 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2482 2537 if (vtable_index < 0) {
2483 2538 // must be invalid_vtable_index, not nonvirtual_vtable_index
2484 2539 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2485 2540 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2486 2541 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2487 2542 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2488 2543 // !!!!!
2489 2544 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2490 2545 // emit_call_dynamic_prologue( cbuf );
2491 2546 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2492 2547
2493 2548 address virtual_call_oop_addr = __ inst_mark();
2494 2549 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2495 2550 // who we intended to call.
2496 2551 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2497 2552 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2498 2553 } else {
2499 2554 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2500 2555 // Just go thru the vtable
2501 2556 // get receiver klass (receiver already checked for non-null)
2502 2557 // If we end up going thru a c2i adapter interpreter expects method in G5
2503 2558 int off = __ offset();
2504 2559 __ load_klass(O0, G3_scratch);
2505 2560 int klass_load_size;
2506 2561 if (UseCompressedOops) {
2507 2562 assert(Universe::heap() != NULL, "java heap should be initialized");
2508 2563 if (Universe::narrow_oop_base() == NULL)
2509 2564 klass_load_size = 2*BytesPerInstWord;
2510 2565 else
2511 2566 klass_load_size = 3*BytesPerInstWord;
2512 2567 } else {
2513 2568 klass_load_size = 1*BytesPerInstWord;
2514 2569 }
2515 2570 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2516 2571 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2517 2572 if( __ is_simm13(v_off) ) {
2518 2573 __ ld_ptr(G3, v_off, G5_method);
2519 2574 } else {
2520 2575 // Generate 2 instructions
2521 2576 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2522 2577 __ or3(G5_method, v_off & 0x3ff, G5_method);
2523 2578 // ld_ptr, set_hi, set
2524 2579 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2525 2580 "Unexpected instruction size(s)");
2526 2581 __ ld_ptr(G3, G5_method, G5_method);
2527 2582 }
2528 2583 // NOTE: for vtable dispatches, the vtable entry will never be null.
2529 2584 // However it may very well end up in handle_wrong_method if the
2530 2585 // method is abstract for the particular class.
2531 2586 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2532 2587 // jump to target (either compiled code or c2iadapter)
2533 2588 __ jmpl(G3_scratch, G0, O7);
2534 2589 __ delayed()->nop();
2535 2590 }
2536 2591 %}
2537 2592
2538 2593 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2539 2594 MacroAssembler _masm(&cbuf);
2540 2595
2541 2596 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2542 2597 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2543 2598 // we might be calling a C2I adapter which needs it.
2544 2599
2545 2600 assert(temp_reg != G5_ic_reg, "conflicting registers");
2546 2601 // Load nmethod
2547 2602 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2548 2603
2549 2604 // CALL to compiled java, indirect the contents of G3
2550 2605 __ set_inst_mark();
2551 2606 __ callr(temp_reg, G0);
2552 2607 __ delayed()->nop();
2553 2608 %}
2554 2609
2555 2610 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2556 2611 MacroAssembler _masm(&cbuf);
2557 2612 Register Rdividend = reg_to_register_object($src1$$reg);
2558 2613 Register Rdivisor = reg_to_register_object($src2$$reg);
2559 2614 Register Rresult = reg_to_register_object($dst$$reg);
2560 2615
2561 2616 __ sra(Rdivisor, 0, Rdivisor);
2562 2617 __ sra(Rdividend, 0, Rdividend);
2563 2618 __ sdivx(Rdividend, Rdivisor, Rresult);
2564 2619 %}
2565 2620
2566 2621 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2567 2622 MacroAssembler _masm(&cbuf);
2568 2623
2569 2624 Register Rdividend = reg_to_register_object($src1$$reg);
2570 2625 int divisor = $imm$$constant;
2571 2626 Register Rresult = reg_to_register_object($dst$$reg);
2572 2627
2573 2628 __ sra(Rdividend, 0, Rdividend);
2574 2629 __ sdivx(Rdividend, divisor, Rresult);
2575 2630 %}
2576 2631
2577 2632 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2578 2633 MacroAssembler _masm(&cbuf);
2579 2634 Register Rsrc1 = reg_to_register_object($src1$$reg);
2580 2635 Register Rsrc2 = reg_to_register_object($src2$$reg);
2581 2636 Register Rdst = reg_to_register_object($dst$$reg);
2582 2637
2583 2638 __ sra( Rsrc1, 0, Rsrc1 );
2584 2639 __ sra( Rsrc2, 0, Rsrc2 );
2585 2640 __ mulx( Rsrc1, Rsrc2, Rdst );
2586 2641 __ srlx( Rdst, 32, Rdst );
2587 2642 %}
2588 2643
2589 2644 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2590 2645 MacroAssembler _masm(&cbuf);
2591 2646 Register Rdividend = reg_to_register_object($src1$$reg);
2592 2647 Register Rdivisor = reg_to_register_object($src2$$reg);
2593 2648 Register Rresult = reg_to_register_object($dst$$reg);
2594 2649 Register Rscratch = reg_to_register_object($scratch$$reg);
2595 2650
2596 2651 assert(Rdividend != Rscratch, "");
2597 2652 assert(Rdivisor != Rscratch, "");
2598 2653
2599 2654 __ sra(Rdividend, 0, Rdividend);
2600 2655 __ sra(Rdivisor, 0, Rdivisor);
2601 2656 __ sdivx(Rdividend, Rdivisor, Rscratch);
2602 2657 __ mulx(Rscratch, Rdivisor, Rscratch);
2603 2658 __ sub(Rdividend, Rscratch, Rresult);
2604 2659 %}
2605 2660
2606 2661 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2607 2662 MacroAssembler _masm(&cbuf);
2608 2663
2609 2664 Register Rdividend = reg_to_register_object($src1$$reg);
2610 2665 int divisor = $imm$$constant;
2611 2666 Register Rresult = reg_to_register_object($dst$$reg);
2612 2667 Register Rscratch = reg_to_register_object($scratch$$reg);
2613 2668
2614 2669 assert(Rdividend != Rscratch, "");
2615 2670
2616 2671 __ sra(Rdividend, 0, Rdividend);
2617 2672 __ sdivx(Rdividend, divisor, Rscratch);
2618 2673 __ mulx(Rscratch, divisor, Rscratch);
2619 2674 __ sub(Rdividend, Rscratch, Rresult);
2620 2675 %}
2621 2676
2622 2677 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2623 2678 MacroAssembler _masm(&cbuf);
2624 2679
2625 2680 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2626 2681 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2627 2682
2628 2683 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2629 2684 %}
2630 2685
2631 2686 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2632 2687 MacroAssembler _masm(&cbuf);
2633 2688
2634 2689 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2635 2690 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2636 2691
2637 2692 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2638 2693 %}
2639 2694
2640 2695 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2641 2696 MacroAssembler _masm(&cbuf);
2642 2697
2643 2698 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2644 2699 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2645 2700
2646 2701 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2647 2702 %}
2648 2703
2649 2704 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2650 2705 MacroAssembler _masm(&cbuf);
2651 2706
2652 2707 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2653 2708 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2654 2709
2655 2710 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2656 2711 %}
2657 2712
2658 2713 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2659 2714 MacroAssembler _masm(&cbuf);
2660 2715
2661 2716 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2662 2717 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2663 2718
2664 2719 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2665 2720 %}
2666 2721
2667 2722 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2668 2723 MacroAssembler _masm(&cbuf);
2669 2724
2670 2725 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2671 2726 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2672 2727
2673 2728 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2674 2729 %}
2675 2730
2676 2731 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2677 2732 MacroAssembler _masm(&cbuf);
2678 2733
2679 2734 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2680 2735 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2681 2736
2682 2737 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2683 2738 %}
2684 2739
2685 2740 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2686 2741 MacroAssembler _masm(&cbuf);
2687 2742
2688 2743 Register Roop = reg_to_register_object($oop$$reg);
2689 2744 Register Rbox = reg_to_register_object($box$$reg);
2690 2745 Register Rscratch = reg_to_register_object($scratch$$reg);
2691 2746 Register Rmark = reg_to_register_object($scratch2$$reg);
2692 2747
2693 2748 assert(Roop != Rscratch, "");
2694 2749 assert(Roop != Rmark, "");
2695 2750 assert(Rbox != Rscratch, "");
2696 2751 assert(Rbox != Rmark, "");
2697 2752
2698 2753 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2699 2754 %}
2700 2755
2701 2756 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2702 2757 MacroAssembler _masm(&cbuf);
2703 2758
2704 2759 Register Roop = reg_to_register_object($oop$$reg);
2705 2760 Register Rbox = reg_to_register_object($box$$reg);
2706 2761 Register Rscratch = reg_to_register_object($scratch$$reg);
2707 2762 Register Rmark = reg_to_register_object($scratch2$$reg);
2708 2763
2709 2764 assert(Roop != Rscratch, "");
2710 2765 assert(Roop != Rmark, "");
2711 2766 assert(Rbox != Rscratch, "");
2712 2767 assert(Rbox != Rmark, "");
2713 2768
2714 2769 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2715 2770 %}
2716 2771
2717 2772 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2718 2773 MacroAssembler _masm(&cbuf);
2719 2774 Register Rmem = reg_to_register_object($mem$$reg);
2720 2775 Register Rold = reg_to_register_object($old$$reg);
2721 2776 Register Rnew = reg_to_register_object($new$$reg);
2722 2777
2723 2778 // casx_under_lock picks 1 of 3 encodings:
2724 2779 // For 32-bit pointers you get a 32-bit CAS
2725 2780 // For 64-bit pointers you get a 64-bit CASX
2726 2781 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2727 2782 __ cmp( Rold, Rnew );
2728 2783 %}
2729 2784
2730 2785 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2731 2786 Register Rmem = reg_to_register_object($mem$$reg);
2732 2787 Register Rold = reg_to_register_object($old$$reg);
2733 2788 Register Rnew = reg_to_register_object($new$$reg);
2734 2789
2735 2790 MacroAssembler _masm(&cbuf);
2736 2791 __ mov(Rnew, O7);
2737 2792 __ casx(Rmem, Rold, O7);
2738 2793 __ cmp( Rold, O7 );
2739 2794 %}
2740 2795
2741 2796 // raw int cas, used for compareAndSwap
2742 2797 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2743 2798 Register Rmem = reg_to_register_object($mem$$reg);
2744 2799 Register Rold = reg_to_register_object($old$$reg);
2745 2800 Register Rnew = reg_to_register_object($new$$reg);
2746 2801
2747 2802 MacroAssembler _masm(&cbuf);
2748 2803 __ mov(Rnew, O7);
2749 2804 __ cas(Rmem, Rold, O7);
2750 2805 __ cmp( Rold, O7 );
2751 2806 %}
2752 2807
2753 2808 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2754 2809 Register Rres = reg_to_register_object($res$$reg);
2755 2810
2756 2811 MacroAssembler _masm(&cbuf);
2757 2812 __ mov(1, Rres);
2758 2813 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2759 2814 %}
2760 2815
2761 2816 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2762 2817 Register Rres = reg_to_register_object($res$$reg);
2763 2818
2764 2819 MacroAssembler _masm(&cbuf);
2765 2820 __ mov(1, Rres);
2766 2821 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2767 2822 %}
2768 2823
2769 2824 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2770 2825 MacroAssembler _masm(&cbuf);
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2771 2826 Register Rdst = reg_to_register_object($dst$$reg);
2772 2827 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2773 2828 : reg_to_DoubleFloatRegister_object($src1$$reg);
2774 2829 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2775 2830 : reg_to_DoubleFloatRegister_object($src2$$reg);
2776 2831
2777 2832 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2778 2833 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2779 2834 %}
2780 2835
2781 - enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2782 - MacroAssembler _masm(&cbuf);
2783 - Register dest = reg_to_register_object($dst$$reg);
2784 - Register temp = reg_to_register_object($tmp$$reg);
2785 - __ set64( $src$$constant, dest, temp );
2786 - %}
2787 -
2788 - enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2789 - // Load a constant replicated "count" times with width "width"
2790 - int bit_width = $width$$constant * 8;
2791 - jlong elt_val = $src$$constant;
2792 - elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2793 - jlong val = elt_val;
2794 - for (int i = 0; i < $count$$constant - 1; i++) {
2795 - val <<= bit_width;
2796 - val |= elt_val;
2797 - }
2798 - jdouble dval = *(jdouble*)&val; // coerce to double type
2799 - MacroAssembler _masm(&cbuf);
2800 - address double_address = __ double_constant(dval);
2801 - RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2802 - AddressLiteral addrlit(double_address, rspec);
2803 -
2804 - __ sethi(addrlit, $tmp$$Register);
2805 - // XXX This is a quick fix for 6833573.
2806 - //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2807 - __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2808 - %}
2809 -
2810 2836 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2811 2837 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2812 2838 MacroAssembler _masm(&cbuf);
2813 2839 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2814 2840 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2815 2841 Register base_pointer_arg = reg_to_register_object($base$$reg);
2816 2842
2817 2843 Label loop;
2818 2844 __ mov(nof_bytes_arg, nof_bytes_tmp);
2819 2845
2820 2846 // Loop and clear, walking backwards through the array.
2821 2847 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2822 2848 __ bind(loop);
2823 2849 __ deccc(nof_bytes_tmp, 8);
2824 2850 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2825 2851 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2826 2852 // %%%% this mini-loop must not cross a cache boundary!
2827 2853 %}
2828 2854
2829 2855
2830 2856 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2831 2857 Label Ldone, Lloop;
2832 2858 MacroAssembler _masm(&cbuf);
2833 2859
2834 2860 Register str1_reg = reg_to_register_object($str1$$reg);
2835 2861 Register str2_reg = reg_to_register_object($str2$$reg);
2836 2862 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2837 2863 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2838 2864 Register result_reg = reg_to_register_object($result$$reg);
2839 2865
2840 2866 assert(result_reg != str1_reg &&
2841 2867 result_reg != str2_reg &&
2842 2868 result_reg != cnt1_reg &&
2843 2869 result_reg != cnt2_reg ,
2844 2870 "need different registers");
2845 2871
2846 2872 // Compute the minimum of the string lengths(str1_reg) and the
2847 2873 // difference of the string lengths (stack)
2848 2874
2849 2875 // See if the lengths are different, and calculate min in str1_reg.
2850 2876 // Stash diff in O7 in case we need it for a tie-breaker.
2851 2877 Label Lskip;
2852 2878 __ subcc(cnt1_reg, cnt2_reg, O7);
2853 2879 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2854 2880 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2855 2881 // cnt2 is shorter, so use its count:
2856 2882 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2857 2883 __ bind(Lskip);
2858 2884
2859 2885 // reallocate cnt1_reg, cnt2_reg, result_reg
2860 2886 // Note: limit_reg holds the string length pre-scaled by 2
2861 2887 Register limit_reg = cnt1_reg;
2862 2888 Register chr2_reg = cnt2_reg;
2863 2889 Register chr1_reg = result_reg;
2864 2890 // str{12} are the base pointers
2865 2891
2866 2892 // Is the minimum length zero?
2867 2893 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2868 2894 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2869 2895 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2870 2896
2871 2897 // Load first characters
2872 2898 __ lduh(str1_reg, 0, chr1_reg);
2873 2899 __ lduh(str2_reg, 0, chr2_reg);
2874 2900
2875 2901 // Compare first characters
2876 2902 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2877 2903 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2878 2904 assert(chr1_reg == result_reg, "result must be pre-placed");
2879 2905 __ delayed()->nop();
2880 2906
2881 2907 {
2882 2908 // Check after comparing first character to see if strings are equivalent
2883 2909 Label LSkip2;
2884 2910 // Check if the strings start at same location
2885 2911 __ cmp(str1_reg, str2_reg);
2886 2912 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2887 2913 __ delayed()->nop();
2888 2914
2889 2915 // Check if the length difference is zero (in O7)
2890 2916 __ cmp(G0, O7);
2891 2917 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2892 2918 __ delayed()->mov(G0, result_reg); // result is zero
2893 2919
2894 2920 // Strings might not be equal
2895 2921 __ bind(LSkip2);
2896 2922 }
2897 2923
2898 2924 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2899 2925 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2900 2926 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2901 2927
2902 2928 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2903 2929 __ add(str1_reg, limit_reg, str1_reg);
2904 2930 __ add(str2_reg, limit_reg, str2_reg);
2905 2931 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2906 2932
2907 2933 // Compare the rest of the characters
2908 2934 __ lduh(str1_reg, limit_reg, chr1_reg);
2909 2935 __ bind(Lloop);
2910 2936 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2911 2937 __ lduh(str2_reg, limit_reg, chr2_reg);
2912 2938 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2913 2939 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2914 2940 assert(chr1_reg == result_reg, "result must be pre-placed");
2915 2941 __ delayed()->inccc(limit_reg, sizeof(jchar));
2916 2942 // annul LDUH if branch is not taken to prevent access past end of string
2917 2943 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2918 2944 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2919 2945
2920 2946 // If strings are equal up to min length, return the length difference.
2921 2947 __ mov(O7, result_reg);
2922 2948
2923 2949 // Otherwise, return the difference between the first mismatched chars.
2924 2950 __ bind(Ldone);
2925 2951 %}
2926 2952
2927 2953 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2928 2954 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2929 2955 MacroAssembler _masm(&cbuf);
2930 2956
2931 2957 Register str1_reg = reg_to_register_object($str1$$reg);
2932 2958 Register str2_reg = reg_to_register_object($str2$$reg);
2933 2959 Register cnt_reg = reg_to_register_object($cnt$$reg);
2934 2960 Register tmp1_reg = O7;
2935 2961 Register result_reg = reg_to_register_object($result$$reg);
2936 2962
2937 2963 assert(result_reg != str1_reg &&
2938 2964 result_reg != str2_reg &&
2939 2965 result_reg != cnt_reg &&
2940 2966 result_reg != tmp1_reg ,
2941 2967 "need different registers");
2942 2968
2943 2969 __ cmp(str1_reg, str2_reg); //same char[] ?
2944 2970 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2945 2971 __ delayed()->add(G0, 1, result_reg);
2946 2972
2947 2973 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2948 2974 __ delayed()->add(G0, 1, result_reg); // count == 0
2949 2975
2950 2976 //rename registers
2951 2977 Register limit_reg = cnt_reg;
2952 2978 Register chr1_reg = result_reg;
2953 2979 Register chr2_reg = tmp1_reg;
2954 2980
2955 2981 //check for alignment and position the pointers to the ends
2956 2982 __ or3(str1_reg, str2_reg, chr1_reg);
2957 2983 __ andcc(chr1_reg, 0x3, chr1_reg);
2958 2984 // notZero means at least one not 4-byte aligned.
2959 2985 // We could optimize the case when both arrays are not aligned
2960 2986 // but it is not frequent case and it requires additional checks.
2961 2987 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2962 2988 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2963 2989
2964 2990 // Compare char[] arrays aligned to 4 bytes.
2965 2991 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2966 2992 chr1_reg, chr2_reg, Ldone);
2967 2993 __ ba(false,Ldone);
2968 2994 __ delayed()->add(G0, 1, result_reg);
2969 2995
2970 2996 // char by char compare
2971 2997 __ bind(Lchar);
2972 2998 __ add(str1_reg, limit_reg, str1_reg);
2973 2999 __ add(str2_reg, limit_reg, str2_reg);
2974 3000 __ neg(limit_reg); //negate count
2975 3001
2976 3002 __ lduh(str1_reg, limit_reg, chr1_reg);
2977 3003 // Lchar_loop
2978 3004 __ bind(Lchar_loop);
2979 3005 __ lduh(str2_reg, limit_reg, chr2_reg);
2980 3006 __ cmp(chr1_reg, chr2_reg);
2981 3007 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2982 3008 __ delayed()->mov(G0, result_reg); //not equal
2983 3009 __ inccc(limit_reg, sizeof(jchar));
2984 3010 // annul LDUH if branch is not taken to prevent access past end of string
2985 3011 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2986 3012 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2987 3013
2988 3014 __ add(G0, 1, result_reg); //equal
2989 3015
2990 3016 __ bind(Ldone);
2991 3017 %}
2992 3018
2993 3019 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2994 3020 Label Lvector, Ldone, Lloop;
2995 3021 MacroAssembler _masm(&cbuf);
2996 3022
2997 3023 Register ary1_reg = reg_to_register_object($ary1$$reg);
2998 3024 Register ary2_reg = reg_to_register_object($ary2$$reg);
2999 3025 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3000 3026 Register tmp2_reg = O7;
3001 3027 Register result_reg = reg_to_register_object($result$$reg);
3002 3028
3003 3029 int length_offset = arrayOopDesc::length_offset_in_bytes();
3004 3030 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3005 3031
3006 3032 // return true if the same array
3007 3033 __ cmp(ary1_reg, ary2_reg);
3008 3034 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3009 3035 __ delayed()->add(G0, 1, result_reg); // equal
3010 3036
3011 3037 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3012 3038 __ delayed()->mov(G0, result_reg); // not equal
3013 3039
3014 3040 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3015 3041 __ delayed()->mov(G0, result_reg); // not equal
3016 3042
3017 3043 //load the lengths of arrays
3018 3044 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3019 3045 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3020 3046
3021 3047 // return false if the two arrays are not equal length
3022 3048 __ cmp(tmp1_reg, tmp2_reg);
3023 3049 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3024 3050 __ delayed()->mov(G0, result_reg); // not equal
3025 3051
3026 3052 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3027 3053 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3028 3054
3029 3055 // load array addresses
3030 3056 __ add(ary1_reg, base_offset, ary1_reg);
3031 3057 __ add(ary2_reg, base_offset, ary2_reg);
3032 3058
3033 3059 // renaming registers
3034 3060 Register chr1_reg = result_reg; // for characters in ary1
3035 3061 Register chr2_reg = tmp2_reg; // for characters in ary2
3036 3062 Register limit_reg = tmp1_reg; // length
3037 3063
3038 3064 // set byte count
3039 3065 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3040 3066
3041 3067 // Compare char[] arrays aligned to 4 bytes.
3042 3068 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3043 3069 chr1_reg, chr2_reg, Ldone);
3044 3070 __ add(G0, 1, result_reg); // equals
3045 3071
3046 3072 __ bind(Ldone);
3047 3073 %}
3048 3074
3049 3075 enc_class enc_rethrow() %{
3050 3076 cbuf.set_insts_mark();
3051 3077 Register temp_reg = G3;
3052 3078 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3053 3079 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3054 3080 MacroAssembler _masm(&cbuf);
3055 3081 #ifdef ASSERT
3056 3082 __ save_frame(0);
3057 3083 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3058 3084 __ sethi(last_rethrow_addrlit, L1);
3059 3085 Address addr(L1, last_rethrow_addrlit.low10());
3060 3086 __ get_pc(L2);
3061 3087 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3062 3088 __ st_ptr(L2, addr);
3063 3089 __ restore();
3064 3090 #endif
3065 3091 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3066 3092 __ delayed()->nop();
3067 3093 %}
3068 3094
3069 3095 enc_class emit_mem_nop() %{
3070 3096 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3071 3097 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3072 3098 %}
3073 3099
3074 3100 enc_class emit_fadd_nop() %{
3075 3101 // Generates the instruction FMOVS f31,f31
3076 3102 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3077 3103 %}
3078 3104
3079 3105 enc_class emit_br_nop() %{
3080 3106 // Generates the instruction BPN,PN .
3081 3107 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3082 3108 %}
3083 3109
3084 3110 enc_class enc_membar_acquire %{
3085 3111 MacroAssembler _masm(&cbuf);
3086 3112 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3087 3113 %}
3088 3114
3089 3115 enc_class enc_membar_release %{
3090 3116 MacroAssembler _masm(&cbuf);
3091 3117 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3092 3118 %}
3093 3119
3094 3120 enc_class enc_membar_volatile %{
3095 3121 MacroAssembler _masm(&cbuf);
3096 3122 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3097 3123 %}
3098 3124
3099 3125 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3100 3126 MacroAssembler _masm(&cbuf);
3101 3127 Register src_reg = reg_to_register_object($src$$reg);
3102 3128 Register dst_reg = reg_to_register_object($dst$$reg);
3103 3129 __ sllx(src_reg, 56, dst_reg);
3104 3130 __ srlx(dst_reg, 8, O7);
3105 3131 __ or3 (dst_reg, O7, dst_reg);
3106 3132 __ srlx(dst_reg, 16, O7);
3107 3133 __ or3 (dst_reg, O7, dst_reg);
3108 3134 __ srlx(dst_reg, 32, O7);
3109 3135 __ or3 (dst_reg, O7, dst_reg);
3110 3136 %}
3111 3137
3112 3138 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3113 3139 MacroAssembler _masm(&cbuf);
3114 3140 Register src_reg = reg_to_register_object($src$$reg);
3115 3141 Register dst_reg = reg_to_register_object($dst$$reg);
3116 3142 __ sll(src_reg, 24, dst_reg);
3117 3143 __ srl(dst_reg, 8, O7);
3118 3144 __ or3(dst_reg, O7, dst_reg);
3119 3145 __ srl(dst_reg, 16, O7);
3120 3146 __ or3(dst_reg, O7, dst_reg);
3121 3147 %}
3122 3148
3123 3149 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3124 3150 MacroAssembler _masm(&cbuf);
3125 3151 Register src_reg = reg_to_register_object($src$$reg);
3126 3152 Register dst_reg = reg_to_register_object($dst$$reg);
3127 3153 __ sllx(src_reg, 48, dst_reg);
3128 3154 __ srlx(dst_reg, 16, O7);
3129 3155 __ or3 (dst_reg, O7, dst_reg);
3130 3156 __ srlx(dst_reg, 32, O7);
3131 3157 __ or3 (dst_reg, O7, dst_reg);
3132 3158 %}
3133 3159
3134 3160 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3135 3161 MacroAssembler _masm(&cbuf);
3136 3162 Register src_reg = reg_to_register_object($src$$reg);
3137 3163 Register dst_reg = reg_to_register_object($dst$$reg);
3138 3164 __ sllx(src_reg, 32, dst_reg);
3139 3165 __ srlx(dst_reg, 32, O7);
3140 3166 __ or3 (dst_reg, O7, dst_reg);
3141 3167 %}
3142 3168
3143 3169 %}
3144 3170
3145 3171 //----------FRAME--------------------------------------------------------------
3146 3172 // Definition of frame structure and management information.
3147 3173 //
3148 3174 // S T A C K L A Y O U T Allocators stack-slot number
3149 3175 // | (to get allocators register number
3150 3176 // G Owned by | | v add VMRegImpl::stack0)
3151 3177 // r CALLER | |
3152 3178 // o | +--------+ pad to even-align allocators stack-slot
3153 3179 // w V | pad0 | numbers; owned by CALLER
3154 3180 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3155 3181 // h ^ | in | 5
3156 3182 // | | args | 4 Holes in incoming args owned by SELF
3157 3183 // | | | | 3
3158 3184 // | | +--------+
3159 3185 // V | | old out| Empty on Intel, window on Sparc
3160 3186 // | old |preserve| Must be even aligned.
3161 3187 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3162 3188 // | | in | 3 area for Intel ret address
3163 3189 // Owned by |preserve| Empty on Sparc.
3164 3190 // SELF +--------+
3165 3191 // | | pad2 | 2 pad to align old SP
3166 3192 // | +--------+ 1
3167 3193 // | | locks | 0
3168 3194 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3169 3195 // | | pad1 | 11 pad to align new SP
3170 3196 // | +--------+
3171 3197 // | | | 10
3172 3198 // | | spills | 9 spills
3173 3199 // V | | 8 (pad0 slot for callee)
3174 3200 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3175 3201 // ^ | out | 7
3176 3202 // | | args | 6 Holes in outgoing args owned by CALLEE
3177 3203 // Owned by +--------+
3178 3204 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3179 3205 // | new |preserve| Must be even-aligned.
3180 3206 // | SP-+--------+----> Matcher::_new_SP, even aligned
3181 3207 // | | |
3182 3208 //
3183 3209 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3184 3210 // known from SELF's arguments and the Java calling convention.
3185 3211 // Region 6-7 is determined per call site.
3186 3212 // Note 2: If the calling convention leaves holes in the incoming argument
3187 3213 // area, those holes are owned by SELF. Holes in the outgoing area
3188 3214 // are owned by the CALLEE. Holes should not be nessecary in the
3189 3215 // incoming area, as the Java calling convention is completely under
3190 3216 // the control of the AD file. Doubles can be sorted and packed to
3191 3217 // avoid holes. Holes in the outgoing arguments may be nessecary for
3192 3218 // varargs C calling conventions.
3193 3219 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3194 3220 // even aligned with pad0 as needed.
3195 3221 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3196 3222 // region 6-11 is even aligned; it may be padded out more so that
3197 3223 // the region from SP to FP meets the minimum stack alignment.
3198 3224
3199 3225 frame %{
3200 3226 // What direction does stack grow in (assumed to be same for native & Java)
3201 3227 stack_direction(TOWARDS_LOW);
3202 3228
3203 3229 // These two registers define part of the calling convention
3204 3230 // between compiled code and the interpreter.
3205 3231 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3206 3232 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3207 3233
3208 3234 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3209 3235 cisc_spilling_operand_name(indOffset);
3210 3236
3211 3237 // Number of stack slots consumed by a Monitor enter
3212 3238 #ifdef _LP64
3213 3239 sync_stack_slots(2);
3214 3240 #else
3215 3241 sync_stack_slots(1);
3216 3242 #endif
3217 3243
3218 3244 // Compiled code's Frame Pointer
3219 3245 frame_pointer(R_SP);
3220 3246
3221 3247 // Stack alignment requirement
3222 3248 stack_alignment(StackAlignmentInBytes);
3223 3249 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3224 3250 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3225 3251
3226 3252 // Number of stack slots between incoming argument block and the start of
3227 3253 // a new frame. The PROLOG must add this many slots to the stack. The
3228 3254 // EPILOG must remove this many slots.
3229 3255 in_preserve_stack_slots(0);
3230 3256
3231 3257 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3232 3258 // for calls to C. Supports the var-args backing area for register parms.
3233 3259 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3234 3260 #ifdef _LP64
3235 3261 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3236 3262 varargs_C_out_slots_killed(12);
3237 3263 #else
3238 3264 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3239 3265 varargs_C_out_slots_killed( 7);
3240 3266 #endif
3241 3267
3242 3268 // The after-PROLOG location of the return address. Location of
3243 3269 // return address specifies a type (REG or STACK) and a number
3244 3270 // representing the register number (i.e. - use a register name) or
3245 3271 // stack slot.
3246 3272 return_addr(REG R_I7); // Ret Addr is in register I7
3247 3273
3248 3274 // Body of function which returns an OptoRegs array locating
3249 3275 // arguments either in registers or in stack slots for calling
3250 3276 // java
3251 3277 calling_convention %{
3252 3278 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3253 3279
3254 3280 %}
3255 3281
3256 3282 // Body of function which returns an OptoRegs array locating
3257 3283 // arguments either in registers or in stack slots for callin
3258 3284 // C.
3259 3285 c_calling_convention %{
3260 3286 // This is obviously always outgoing
3261 3287 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3262 3288 %}
3263 3289
3264 3290 // Location of native (C/C++) and interpreter return values. This is specified to
3265 3291 // be the same as Java. In the 32-bit VM, long values are actually returned from
3266 3292 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3267 3293 // to and from the register pairs is done by the appropriate call and epilog
3268 3294 // opcodes. This simplifies the register allocator.
3269 3295 c_return_value %{
3270 3296 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3271 3297 #ifdef _LP64
3272 3298 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3273 3299 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3274 3300 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3275 3301 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3276 3302 #else // !_LP64
3277 3303 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3278 3304 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3279 3305 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3280 3306 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3281 3307 #endif
3282 3308 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3283 3309 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3284 3310 %}
3285 3311
3286 3312 // Location of compiled Java return values. Same as C
3287 3313 return_value %{
3288 3314 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3289 3315 #ifdef _LP64
3290 3316 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3291 3317 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3292 3318 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3293 3319 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3294 3320 #else // !_LP64
3295 3321 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3296 3322 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3297 3323 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3298 3324 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3299 3325 #endif
3300 3326 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3301 3327 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3302 3328 %}
3303 3329
3304 3330 %}
3305 3331
3306 3332
3307 3333 //----------ATTRIBUTES---------------------------------------------------------
3308 3334 //----------Operand Attributes-------------------------------------------------
3309 3335 op_attrib op_cost(1); // Required cost attribute
3310 3336
3311 3337 //----------Instruction Attributes---------------------------------------------
3312 3338 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3313 3339 ins_attrib ins_size(32); // Required size attribute (in bits)
3314 3340 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3315 3341 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3316 3342 // non-matching short branch variant of some
3317 3343 // long branch?
3318 3344
3319 3345 //----------OPERANDS-----------------------------------------------------------
3320 3346 // Operand definitions must precede instruction definitions for correct parsing
3321 3347 // in the ADLC because operands constitute user defined types which are used in
3322 3348 // instruction definitions.
3323 3349
3324 3350 //----------Simple Operands----------------------------------------------------
3325 3351 // Immediate Operands
3326 3352 // Integer Immediate: 32-bit
3327 3353 operand immI() %{
3328 3354 match(ConI);
3329 3355
3330 3356 op_cost(0);
3331 3357 // formats are generated automatically for constants and base registers
3332 3358 format %{ %}
3333 3359 interface(CONST_INTER);
3334 3360 %}
3335 3361
3336 3362 // Integer Immediate: 8-bit
3337 3363 operand immI8() %{
3338 3364 predicate(Assembler::is_simm(n->get_int(), 8));
3339 3365 match(ConI);
3340 3366 op_cost(0);
3341 3367 format %{ %}
3342 3368 interface(CONST_INTER);
3343 3369 %}
3344 3370
3345 3371 // Integer Immediate: 13-bit
3346 3372 operand immI13() %{
3347 3373 predicate(Assembler::is_simm13(n->get_int()));
3348 3374 match(ConI);
3349 3375 op_cost(0);
3350 3376
3351 3377 format %{ %}
3352 3378 interface(CONST_INTER);
3353 3379 %}
3354 3380
3355 3381 // Integer Immediate: 13-bit minus 7
3356 3382 operand immI13m7() %{
3357 3383 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3358 3384 match(ConI);
3359 3385 op_cost(0);
3360 3386
3361 3387 format %{ %}
3362 3388 interface(CONST_INTER);
3363 3389 %}
3364 3390
3365 3391 // Integer Immediate: 16-bit
3366 3392 operand immI16() %{
3367 3393 predicate(Assembler::is_simm(n->get_int(), 16));
3368 3394 match(ConI);
3369 3395 op_cost(0);
3370 3396 format %{ %}
3371 3397 interface(CONST_INTER);
3372 3398 %}
3373 3399
3374 3400 // Unsigned (positive) Integer Immediate: 13-bit
3375 3401 operand immU13() %{
3376 3402 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3377 3403 match(ConI);
3378 3404 op_cost(0);
3379 3405
3380 3406 format %{ %}
3381 3407 interface(CONST_INTER);
3382 3408 %}
3383 3409
3384 3410 // Integer Immediate: 6-bit
3385 3411 operand immU6() %{
3386 3412 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3387 3413 match(ConI);
3388 3414 op_cost(0);
3389 3415 format %{ %}
3390 3416 interface(CONST_INTER);
3391 3417 %}
3392 3418
3393 3419 // Integer Immediate: 11-bit
3394 3420 operand immI11() %{
3395 3421 predicate(Assembler::is_simm(n->get_int(),11));
3396 3422 match(ConI);
3397 3423 op_cost(0);
3398 3424 format %{ %}
3399 3425 interface(CONST_INTER);
3400 3426 %}
3401 3427
3402 3428 // Integer Immediate: 0-bit
3403 3429 operand immI0() %{
3404 3430 predicate(n->get_int() == 0);
3405 3431 match(ConI);
3406 3432 op_cost(0);
3407 3433
3408 3434 format %{ %}
3409 3435 interface(CONST_INTER);
3410 3436 %}
3411 3437
3412 3438 // Integer Immediate: the value 10
3413 3439 operand immI10() %{
3414 3440 predicate(n->get_int() == 10);
3415 3441 match(ConI);
3416 3442 op_cost(0);
3417 3443
3418 3444 format %{ %}
3419 3445 interface(CONST_INTER);
3420 3446 %}
3421 3447
3422 3448 // Integer Immediate: the values 0-31
3423 3449 operand immU5() %{
3424 3450 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3425 3451 match(ConI);
3426 3452 op_cost(0);
3427 3453
3428 3454 format %{ %}
3429 3455 interface(CONST_INTER);
3430 3456 %}
3431 3457
3432 3458 // Integer Immediate: the values 1-31
3433 3459 operand immI_1_31() %{
3434 3460 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3435 3461 match(ConI);
3436 3462 op_cost(0);
3437 3463
3438 3464 format %{ %}
3439 3465 interface(CONST_INTER);
3440 3466 %}
3441 3467
3442 3468 // Integer Immediate: the values 32-63
3443 3469 operand immI_32_63() %{
3444 3470 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3445 3471 match(ConI);
3446 3472 op_cost(0);
3447 3473
3448 3474 format %{ %}
3449 3475 interface(CONST_INTER);
3450 3476 %}
3451 3477
3452 3478 // Immediates for special shifts (sign extend)
3453 3479
3454 3480 // Integer Immediate: the value 16
3455 3481 operand immI_16() %{
3456 3482 predicate(n->get_int() == 16);
3457 3483 match(ConI);
3458 3484 op_cost(0);
3459 3485
3460 3486 format %{ %}
3461 3487 interface(CONST_INTER);
3462 3488 %}
3463 3489
3464 3490 // Integer Immediate: the value 24
3465 3491 operand immI_24() %{
3466 3492 predicate(n->get_int() == 24);
3467 3493 match(ConI);
3468 3494 op_cost(0);
3469 3495
3470 3496 format %{ %}
3471 3497 interface(CONST_INTER);
3472 3498 %}
3473 3499
3474 3500 // Integer Immediate: the value 255
3475 3501 operand immI_255() %{
3476 3502 predicate( n->get_int() == 255 );
3477 3503 match(ConI);
3478 3504 op_cost(0);
3479 3505
3480 3506 format %{ %}
3481 3507 interface(CONST_INTER);
3482 3508 %}
3483 3509
3484 3510 // Integer Immediate: the value 65535
3485 3511 operand immI_65535() %{
3486 3512 predicate(n->get_int() == 65535);
3487 3513 match(ConI);
3488 3514 op_cost(0);
3489 3515
3490 3516 format %{ %}
3491 3517 interface(CONST_INTER);
3492 3518 %}
3493 3519
3494 3520 // Long Immediate: the value FF
3495 3521 operand immL_FF() %{
3496 3522 predicate( n->get_long() == 0xFFL );
3497 3523 match(ConL);
3498 3524 op_cost(0);
3499 3525
3500 3526 format %{ %}
3501 3527 interface(CONST_INTER);
3502 3528 %}
3503 3529
3504 3530 // Long Immediate: the value FFFF
3505 3531 operand immL_FFFF() %{
3506 3532 predicate( n->get_long() == 0xFFFFL );
3507 3533 match(ConL);
3508 3534 op_cost(0);
3509 3535
3510 3536 format %{ %}
3511 3537 interface(CONST_INTER);
3512 3538 %}
3513 3539
3514 3540 // Pointer Immediate: 32 or 64-bit
3515 3541 operand immP() %{
3516 3542 match(ConP);
3517 3543
3518 3544 op_cost(5);
3519 3545 // formats are generated automatically for constants and base registers
3520 3546 format %{ %}
3521 3547 interface(CONST_INTER);
3522 3548 %}
3523 3549
3524 3550 operand immP13() %{
3525 3551 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3526 3552 match(ConP);
3527 3553 op_cost(0);
3528 3554
3529 3555 format %{ %}
3530 3556 interface(CONST_INTER);
3531 3557 %}
3532 3558
3533 3559 operand immP0() %{
3534 3560 predicate(n->get_ptr() == 0);
3535 3561 match(ConP);
3536 3562 op_cost(0);
3537 3563
3538 3564 format %{ %}
3539 3565 interface(CONST_INTER);
3540 3566 %}
3541 3567
3542 3568 operand immP_poll() %{
3543 3569 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3544 3570 match(ConP);
3545 3571
3546 3572 // formats are generated automatically for constants and base registers
3547 3573 format %{ %}
3548 3574 interface(CONST_INTER);
3549 3575 %}
3550 3576
3551 3577 // Pointer Immediate
3552 3578 operand immN()
3553 3579 %{
3554 3580 match(ConN);
3555 3581
3556 3582 op_cost(10);
3557 3583 format %{ %}
3558 3584 interface(CONST_INTER);
3559 3585 %}
3560 3586
3561 3587 // NULL Pointer Immediate
3562 3588 operand immN0()
3563 3589 %{
3564 3590 predicate(n->get_narrowcon() == 0);
3565 3591 match(ConN);
3566 3592
3567 3593 op_cost(0);
3568 3594 format %{ %}
3569 3595 interface(CONST_INTER);
3570 3596 %}
3571 3597
3572 3598 operand immL() %{
3573 3599 match(ConL);
3574 3600 op_cost(40);
3575 3601 // formats are generated automatically for constants and base registers
3576 3602 format %{ %}
3577 3603 interface(CONST_INTER);
3578 3604 %}
3579 3605
3580 3606 operand immL0() %{
3581 3607 predicate(n->get_long() == 0L);
3582 3608 match(ConL);
3583 3609 op_cost(0);
3584 3610 // formats are generated automatically for constants and base registers
3585 3611 format %{ %}
3586 3612 interface(CONST_INTER);
3587 3613 %}
3588 3614
3589 3615 // Long Immediate: 13-bit
3590 3616 operand immL13() %{
3591 3617 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3592 3618 match(ConL);
3593 3619 op_cost(0);
3594 3620
3595 3621 format %{ %}
3596 3622 interface(CONST_INTER);
3597 3623 %}
3598 3624
3599 3625 // Long Immediate: 13-bit minus 7
3600 3626 operand immL13m7() %{
3601 3627 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3602 3628 match(ConL);
3603 3629 op_cost(0);
3604 3630
3605 3631 format %{ %}
3606 3632 interface(CONST_INTER);
3607 3633 %}
3608 3634
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3609 3635 // Long Immediate: low 32-bit mask
3610 3636 operand immL_32bits() %{
3611 3637 predicate(n->get_long() == 0xFFFFFFFFL);
3612 3638 match(ConL);
3613 3639 op_cost(0);
3614 3640
3615 3641 format %{ %}
3616 3642 interface(CONST_INTER);
3617 3643 %}
3618 3644
3645 +// Long Immediate: cheap (materialize in <= 3 instructions)
3646 +operand immL_cheap() %{
3647 + predicate(MacroAssembler::size_of_set64(n->get_long()) <= 3);
3648 + match(ConL);
3649 + op_cost(0);
3650 +
3651 + format %{ %}
3652 + interface(CONST_INTER);
3653 +%}
3654 +
3655 +// Long Immediate: expensive (materialize in > 3 instructions)
3656 +operand immL_expensive() %{
3657 + predicate(MacroAssembler::size_of_set64(n->get_long()) > 3);
3658 + match(ConL);
3659 + op_cost(0);
3660 +
3661 + format %{ %}
3662 + interface(CONST_INTER);
3663 +%}
3664 +
3619 3665 // Double Immediate
3620 3666 operand immD() %{
3621 3667 match(ConD);
3622 3668
3623 3669 op_cost(40);
3624 3670 format %{ %}
3625 3671 interface(CONST_INTER);
3626 3672 %}
3627 3673
3628 3674 operand immD0() %{
3629 3675 #ifdef _LP64
3630 3676 // on 64-bit architectures this comparision is faster
3631 3677 predicate(jlong_cast(n->getd()) == 0);
3632 3678 #else
3633 3679 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3634 3680 #endif
3635 3681 match(ConD);
3636 3682
3637 3683 op_cost(0);
3638 3684 format %{ %}
3639 3685 interface(CONST_INTER);
3640 3686 %}
3641 3687
3642 3688 // Float Immediate
3643 3689 operand immF() %{
3644 3690 match(ConF);
3645 3691
3646 3692 op_cost(20);
3647 3693 format %{ %}
3648 3694 interface(CONST_INTER);
3649 3695 %}
3650 3696
3651 3697 // Float Immediate: 0
3652 3698 operand immF0() %{
3653 3699 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3654 3700 match(ConF);
3655 3701
3656 3702 op_cost(0);
3657 3703 format %{ %}
3658 3704 interface(CONST_INTER);
3659 3705 %}
3660 3706
3661 3707 // Integer Register Operands
3662 3708 // Integer Register
3663 3709 operand iRegI() %{
3664 3710 constraint(ALLOC_IN_RC(int_reg));
3665 3711 match(RegI);
3666 3712
3667 3713 match(notemp_iRegI);
3668 3714 match(g1RegI);
3669 3715 match(o0RegI);
3670 3716 match(iRegIsafe);
3671 3717
3672 3718 format %{ %}
3673 3719 interface(REG_INTER);
3674 3720 %}
3675 3721
3676 3722 operand notemp_iRegI() %{
3677 3723 constraint(ALLOC_IN_RC(notemp_int_reg));
3678 3724 match(RegI);
3679 3725
3680 3726 match(o0RegI);
3681 3727
3682 3728 format %{ %}
3683 3729 interface(REG_INTER);
3684 3730 %}
3685 3731
3686 3732 operand o0RegI() %{
3687 3733 constraint(ALLOC_IN_RC(o0_regI));
3688 3734 match(iRegI);
3689 3735
3690 3736 format %{ %}
3691 3737 interface(REG_INTER);
3692 3738 %}
3693 3739
3694 3740 // Pointer Register
3695 3741 operand iRegP() %{
3696 3742 constraint(ALLOC_IN_RC(ptr_reg));
3697 3743 match(RegP);
3698 3744
3699 3745 match(lock_ptr_RegP);
3700 3746 match(g1RegP);
3701 3747 match(g2RegP);
3702 3748 match(g3RegP);
3703 3749 match(g4RegP);
3704 3750 match(i0RegP);
3705 3751 match(o0RegP);
3706 3752 match(o1RegP);
3707 3753 match(l7RegP);
3708 3754
3709 3755 format %{ %}
3710 3756 interface(REG_INTER);
3711 3757 %}
3712 3758
3713 3759 operand sp_ptr_RegP() %{
3714 3760 constraint(ALLOC_IN_RC(sp_ptr_reg));
3715 3761 match(RegP);
3716 3762 match(iRegP);
3717 3763
3718 3764 format %{ %}
3719 3765 interface(REG_INTER);
3720 3766 %}
3721 3767
3722 3768 operand lock_ptr_RegP() %{
3723 3769 constraint(ALLOC_IN_RC(lock_ptr_reg));
3724 3770 match(RegP);
3725 3771 match(i0RegP);
3726 3772 match(o0RegP);
3727 3773 match(o1RegP);
3728 3774 match(l7RegP);
3729 3775
3730 3776 format %{ %}
3731 3777 interface(REG_INTER);
3732 3778 %}
3733 3779
3734 3780 operand g1RegP() %{
3735 3781 constraint(ALLOC_IN_RC(g1_regP));
3736 3782 match(iRegP);
3737 3783
3738 3784 format %{ %}
3739 3785 interface(REG_INTER);
3740 3786 %}
3741 3787
3742 3788 operand g2RegP() %{
3743 3789 constraint(ALLOC_IN_RC(g2_regP));
3744 3790 match(iRegP);
3745 3791
3746 3792 format %{ %}
3747 3793 interface(REG_INTER);
3748 3794 %}
3749 3795
3750 3796 operand g3RegP() %{
3751 3797 constraint(ALLOC_IN_RC(g3_regP));
3752 3798 match(iRegP);
3753 3799
3754 3800 format %{ %}
3755 3801 interface(REG_INTER);
3756 3802 %}
3757 3803
3758 3804 operand g1RegI() %{
3759 3805 constraint(ALLOC_IN_RC(g1_regI));
3760 3806 match(iRegI);
3761 3807
3762 3808 format %{ %}
3763 3809 interface(REG_INTER);
3764 3810 %}
3765 3811
3766 3812 operand g3RegI() %{
3767 3813 constraint(ALLOC_IN_RC(g3_regI));
3768 3814 match(iRegI);
3769 3815
3770 3816 format %{ %}
3771 3817 interface(REG_INTER);
3772 3818 %}
3773 3819
3774 3820 operand g4RegI() %{
3775 3821 constraint(ALLOC_IN_RC(g4_regI));
3776 3822 match(iRegI);
3777 3823
3778 3824 format %{ %}
3779 3825 interface(REG_INTER);
3780 3826 %}
3781 3827
3782 3828 operand g4RegP() %{
3783 3829 constraint(ALLOC_IN_RC(g4_regP));
3784 3830 match(iRegP);
3785 3831
3786 3832 format %{ %}
3787 3833 interface(REG_INTER);
3788 3834 %}
3789 3835
3790 3836 operand i0RegP() %{
3791 3837 constraint(ALLOC_IN_RC(i0_regP));
3792 3838 match(iRegP);
3793 3839
3794 3840 format %{ %}
3795 3841 interface(REG_INTER);
3796 3842 %}
3797 3843
3798 3844 operand o0RegP() %{
3799 3845 constraint(ALLOC_IN_RC(o0_regP));
3800 3846 match(iRegP);
3801 3847
3802 3848 format %{ %}
3803 3849 interface(REG_INTER);
3804 3850 %}
3805 3851
3806 3852 operand o1RegP() %{
3807 3853 constraint(ALLOC_IN_RC(o1_regP));
3808 3854 match(iRegP);
3809 3855
3810 3856 format %{ %}
3811 3857 interface(REG_INTER);
3812 3858 %}
3813 3859
3814 3860 operand o2RegP() %{
3815 3861 constraint(ALLOC_IN_RC(o2_regP));
3816 3862 match(iRegP);
3817 3863
3818 3864 format %{ %}
3819 3865 interface(REG_INTER);
3820 3866 %}
3821 3867
3822 3868 operand o7RegP() %{
3823 3869 constraint(ALLOC_IN_RC(o7_regP));
3824 3870 match(iRegP);
3825 3871
3826 3872 format %{ %}
3827 3873 interface(REG_INTER);
3828 3874 %}
3829 3875
3830 3876 operand l7RegP() %{
3831 3877 constraint(ALLOC_IN_RC(l7_regP));
3832 3878 match(iRegP);
3833 3879
3834 3880 format %{ %}
3835 3881 interface(REG_INTER);
3836 3882 %}
3837 3883
3838 3884 operand o7RegI() %{
3839 3885 constraint(ALLOC_IN_RC(o7_regI));
3840 3886 match(iRegI);
3841 3887
3842 3888 format %{ %}
3843 3889 interface(REG_INTER);
3844 3890 %}
3845 3891
3846 3892 operand iRegN() %{
3847 3893 constraint(ALLOC_IN_RC(int_reg));
3848 3894 match(RegN);
3849 3895
3850 3896 format %{ %}
3851 3897 interface(REG_INTER);
3852 3898 %}
3853 3899
3854 3900 // Long Register
3855 3901 operand iRegL() %{
3856 3902 constraint(ALLOC_IN_RC(long_reg));
3857 3903 match(RegL);
3858 3904
3859 3905 format %{ %}
3860 3906 interface(REG_INTER);
3861 3907 %}
3862 3908
3863 3909 operand o2RegL() %{
3864 3910 constraint(ALLOC_IN_RC(o2_regL));
3865 3911 match(iRegL);
3866 3912
3867 3913 format %{ %}
3868 3914 interface(REG_INTER);
3869 3915 %}
3870 3916
3871 3917 operand o7RegL() %{
3872 3918 constraint(ALLOC_IN_RC(o7_regL));
3873 3919 match(iRegL);
3874 3920
3875 3921 format %{ %}
3876 3922 interface(REG_INTER);
3877 3923 %}
3878 3924
3879 3925 operand g1RegL() %{
3880 3926 constraint(ALLOC_IN_RC(g1_regL));
3881 3927 match(iRegL);
3882 3928
3883 3929 format %{ %}
3884 3930 interface(REG_INTER);
3885 3931 %}
3886 3932
3887 3933 operand g3RegL() %{
3888 3934 constraint(ALLOC_IN_RC(g3_regL));
3889 3935 match(iRegL);
3890 3936
3891 3937 format %{ %}
3892 3938 interface(REG_INTER);
3893 3939 %}
3894 3940
3895 3941 // Int Register safe
3896 3942 // This is 64bit safe
3897 3943 operand iRegIsafe() %{
3898 3944 constraint(ALLOC_IN_RC(long_reg));
3899 3945
3900 3946 match(iRegI);
3901 3947
3902 3948 format %{ %}
3903 3949 interface(REG_INTER);
3904 3950 %}
3905 3951
3906 3952 // Condition Code Flag Register
3907 3953 operand flagsReg() %{
3908 3954 constraint(ALLOC_IN_RC(int_flags));
3909 3955 match(RegFlags);
3910 3956
3911 3957 format %{ "ccr" %} // both ICC and XCC
3912 3958 interface(REG_INTER);
3913 3959 %}
3914 3960
3915 3961 // Condition Code Register, unsigned comparisons.
3916 3962 operand flagsRegU() %{
3917 3963 constraint(ALLOC_IN_RC(int_flags));
3918 3964 match(RegFlags);
3919 3965
3920 3966 format %{ "icc_U" %}
3921 3967 interface(REG_INTER);
3922 3968 %}
3923 3969
3924 3970 // Condition Code Register, pointer comparisons.
3925 3971 operand flagsRegP() %{
3926 3972 constraint(ALLOC_IN_RC(int_flags));
3927 3973 match(RegFlags);
3928 3974
3929 3975 #ifdef _LP64
3930 3976 format %{ "xcc_P" %}
3931 3977 #else
3932 3978 format %{ "icc_P" %}
3933 3979 #endif
3934 3980 interface(REG_INTER);
3935 3981 %}
3936 3982
3937 3983 // Condition Code Register, long comparisons.
3938 3984 operand flagsRegL() %{
3939 3985 constraint(ALLOC_IN_RC(int_flags));
3940 3986 match(RegFlags);
3941 3987
3942 3988 format %{ "xcc_L" %}
3943 3989 interface(REG_INTER);
3944 3990 %}
3945 3991
3946 3992 // Condition Code Register, floating comparisons, unordered same as "less".
3947 3993 operand flagsRegF() %{
3948 3994 constraint(ALLOC_IN_RC(float_flags));
3949 3995 match(RegFlags);
3950 3996 match(flagsRegF0);
3951 3997
3952 3998 format %{ %}
3953 3999 interface(REG_INTER);
3954 4000 %}
3955 4001
3956 4002 operand flagsRegF0() %{
3957 4003 constraint(ALLOC_IN_RC(float_flag0));
3958 4004 match(RegFlags);
3959 4005
3960 4006 format %{ %}
3961 4007 interface(REG_INTER);
3962 4008 %}
3963 4009
3964 4010
3965 4011 // Condition Code Flag Register used by long compare
3966 4012 operand flagsReg_long_LTGE() %{
3967 4013 constraint(ALLOC_IN_RC(int_flags));
3968 4014 match(RegFlags);
3969 4015 format %{ "icc_LTGE" %}
3970 4016 interface(REG_INTER);
3971 4017 %}
3972 4018 operand flagsReg_long_EQNE() %{
3973 4019 constraint(ALLOC_IN_RC(int_flags));
3974 4020 match(RegFlags);
3975 4021 format %{ "icc_EQNE" %}
3976 4022 interface(REG_INTER);
3977 4023 %}
3978 4024 operand flagsReg_long_LEGT() %{
3979 4025 constraint(ALLOC_IN_RC(int_flags));
3980 4026 match(RegFlags);
3981 4027 format %{ "icc_LEGT" %}
3982 4028 interface(REG_INTER);
3983 4029 %}
3984 4030
3985 4031
3986 4032 operand regD() %{
3987 4033 constraint(ALLOC_IN_RC(dflt_reg));
3988 4034 match(RegD);
3989 4035
3990 4036 match(regD_low);
3991 4037
3992 4038 format %{ %}
3993 4039 interface(REG_INTER);
3994 4040 %}
3995 4041
3996 4042 operand regF() %{
3997 4043 constraint(ALLOC_IN_RC(sflt_reg));
3998 4044 match(RegF);
3999 4045
4000 4046 format %{ %}
4001 4047 interface(REG_INTER);
4002 4048 %}
4003 4049
4004 4050 operand regD_low() %{
4005 4051 constraint(ALLOC_IN_RC(dflt_low_reg));
4006 4052 match(regD);
4007 4053
4008 4054 format %{ %}
4009 4055 interface(REG_INTER);
4010 4056 %}
4011 4057
4012 4058 // Special Registers
4013 4059
4014 4060 // Method Register
4015 4061 operand inline_cache_regP(iRegP reg) %{
4016 4062 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4017 4063 match(reg);
4018 4064 format %{ %}
4019 4065 interface(REG_INTER);
4020 4066 %}
4021 4067
4022 4068 operand interpreter_method_oop_regP(iRegP reg) %{
4023 4069 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4024 4070 match(reg);
4025 4071 format %{ %}
4026 4072 interface(REG_INTER);
4027 4073 %}
4028 4074
4029 4075
4030 4076 //----------Complex Operands---------------------------------------------------
4031 4077 // Indirect Memory Reference
4032 4078 operand indirect(sp_ptr_RegP reg) %{
4033 4079 constraint(ALLOC_IN_RC(sp_ptr_reg));
4034 4080 match(reg);
4035 4081
4036 4082 op_cost(100);
4037 4083 format %{ "[$reg]" %}
4038 4084 interface(MEMORY_INTER) %{
4039 4085 base($reg);
4040 4086 index(0x0);
4041 4087 scale(0x0);
4042 4088 disp(0x0);
4043 4089 %}
4044 4090 %}
4045 4091
4046 4092 // Indirect with simm13 Offset
4047 4093 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4048 4094 constraint(ALLOC_IN_RC(sp_ptr_reg));
4049 4095 match(AddP reg offset);
4050 4096
4051 4097 op_cost(100);
4052 4098 format %{ "[$reg + $offset]" %}
4053 4099 interface(MEMORY_INTER) %{
4054 4100 base($reg);
4055 4101 index(0x0);
4056 4102 scale(0x0);
4057 4103 disp($offset);
4058 4104 %}
4059 4105 %}
4060 4106
4061 4107 // Indirect with simm13 Offset minus 7
4062 4108 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4063 4109 constraint(ALLOC_IN_RC(sp_ptr_reg));
4064 4110 match(AddP reg offset);
4065 4111
4066 4112 op_cost(100);
4067 4113 format %{ "[$reg + $offset]" %}
4068 4114 interface(MEMORY_INTER) %{
4069 4115 base($reg);
4070 4116 index(0x0);
4071 4117 scale(0x0);
4072 4118 disp($offset);
4073 4119 %}
4074 4120 %}
4075 4121
4076 4122 // Note: Intel has a swapped version also, like this:
4077 4123 //operand indOffsetX(iRegI reg, immP offset) %{
4078 4124 // constraint(ALLOC_IN_RC(int_reg));
4079 4125 // match(AddP offset reg);
4080 4126 //
4081 4127 // op_cost(100);
4082 4128 // format %{ "[$reg + $offset]" %}
4083 4129 // interface(MEMORY_INTER) %{
4084 4130 // base($reg);
4085 4131 // index(0x0);
4086 4132 // scale(0x0);
4087 4133 // disp($offset);
4088 4134 // %}
4089 4135 //%}
4090 4136 //// However, it doesn't make sense for SPARC, since
4091 4137 // we have no particularly good way to embed oops in
4092 4138 // single instructions.
4093 4139
4094 4140 // Indirect with Register Index
4095 4141 operand indIndex(iRegP addr, iRegX index) %{
4096 4142 constraint(ALLOC_IN_RC(ptr_reg));
4097 4143 match(AddP addr index);
4098 4144
4099 4145 op_cost(100);
4100 4146 format %{ "[$addr + $index]" %}
4101 4147 interface(MEMORY_INTER) %{
4102 4148 base($addr);
4103 4149 index($index);
4104 4150 scale(0x0);
4105 4151 disp(0x0);
4106 4152 %}
4107 4153 %}
4108 4154
4109 4155 //----------Special Memory Operands--------------------------------------------
4110 4156 // Stack Slot Operand - This operand is used for loading and storing temporary
4111 4157 // values on the stack where a match requires a value to
4112 4158 // flow through memory.
4113 4159 operand stackSlotI(sRegI reg) %{
4114 4160 constraint(ALLOC_IN_RC(stack_slots));
4115 4161 op_cost(100);
4116 4162 //match(RegI);
4117 4163 format %{ "[$reg]" %}
4118 4164 interface(MEMORY_INTER) %{
4119 4165 base(0xE); // R_SP
4120 4166 index(0x0);
4121 4167 scale(0x0);
4122 4168 disp($reg); // Stack Offset
4123 4169 %}
4124 4170 %}
4125 4171
4126 4172 operand stackSlotP(sRegP reg) %{
4127 4173 constraint(ALLOC_IN_RC(stack_slots));
4128 4174 op_cost(100);
4129 4175 //match(RegP);
4130 4176 format %{ "[$reg]" %}
4131 4177 interface(MEMORY_INTER) %{
4132 4178 base(0xE); // R_SP
4133 4179 index(0x0);
4134 4180 scale(0x0);
4135 4181 disp($reg); // Stack Offset
4136 4182 %}
4137 4183 %}
4138 4184
4139 4185 operand stackSlotF(sRegF reg) %{
4140 4186 constraint(ALLOC_IN_RC(stack_slots));
4141 4187 op_cost(100);
4142 4188 //match(RegF);
4143 4189 format %{ "[$reg]" %}
4144 4190 interface(MEMORY_INTER) %{
4145 4191 base(0xE); // R_SP
4146 4192 index(0x0);
4147 4193 scale(0x0);
4148 4194 disp($reg); // Stack Offset
4149 4195 %}
4150 4196 %}
4151 4197 operand stackSlotD(sRegD reg) %{
4152 4198 constraint(ALLOC_IN_RC(stack_slots));
4153 4199 op_cost(100);
4154 4200 //match(RegD);
4155 4201 format %{ "[$reg]" %}
4156 4202 interface(MEMORY_INTER) %{
4157 4203 base(0xE); // R_SP
4158 4204 index(0x0);
4159 4205 scale(0x0);
4160 4206 disp($reg); // Stack Offset
4161 4207 %}
4162 4208 %}
4163 4209 operand stackSlotL(sRegL reg) %{
4164 4210 constraint(ALLOC_IN_RC(stack_slots));
4165 4211 op_cost(100);
4166 4212 //match(RegL);
4167 4213 format %{ "[$reg]" %}
4168 4214 interface(MEMORY_INTER) %{
4169 4215 base(0xE); // R_SP
4170 4216 index(0x0);
4171 4217 scale(0x0);
4172 4218 disp($reg); // Stack Offset
4173 4219 %}
4174 4220 %}
4175 4221
4176 4222 // Operands for expressing Control Flow
4177 4223 // NOTE: Label is a predefined operand which should not be redefined in
4178 4224 // the AD file. It is generically handled within the ADLC.
4179 4225
4180 4226 //----------Conditional Branch Operands----------------------------------------
4181 4227 // Comparison Op - This is the operation of the comparison, and is limited to
4182 4228 // the following set of codes:
4183 4229 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4184 4230 //
4185 4231 // Other attributes of the comparison, such as unsignedness, are specified
4186 4232 // by the comparison instruction that sets a condition code flags register.
4187 4233 // That result is represented by a flags operand whose subtype is appropriate
4188 4234 // to the unsignedness (etc.) of the comparison.
4189 4235 //
4190 4236 // Later, the instruction which matches both the Comparison Op (a Bool) and
4191 4237 // the flags (produced by the Cmp) specifies the coding of the comparison op
4192 4238 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4193 4239
4194 4240 operand cmpOp() %{
4195 4241 match(Bool);
4196 4242
4197 4243 format %{ "" %}
4198 4244 interface(COND_INTER) %{
4199 4245 equal(0x1);
4200 4246 not_equal(0x9);
4201 4247 less(0x3);
4202 4248 greater_equal(0xB);
4203 4249 less_equal(0x2);
4204 4250 greater(0xA);
4205 4251 %}
4206 4252 %}
4207 4253
4208 4254 // Comparison Op, unsigned
4209 4255 operand cmpOpU() %{
4210 4256 match(Bool);
4211 4257
4212 4258 format %{ "u" %}
4213 4259 interface(COND_INTER) %{
4214 4260 equal(0x1);
4215 4261 not_equal(0x9);
4216 4262 less(0x5);
4217 4263 greater_equal(0xD);
4218 4264 less_equal(0x4);
4219 4265 greater(0xC);
4220 4266 %}
4221 4267 %}
4222 4268
4223 4269 // Comparison Op, pointer (same as unsigned)
4224 4270 operand cmpOpP() %{
4225 4271 match(Bool);
4226 4272
4227 4273 format %{ "p" %}
4228 4274 interface(COND_INTER) %{
4229 4275 equal(0x1);
4230 4276 not_equal(0x9);
4231 4277 less(0x5);
4232 4278 greater_equal(0xD);
4233 4279 less_equal(0x4);
4234 4280 greater(0xC);
4235 4281 %}
4236 4282 %}
4237 4283
4238 4284 // Comparison Op, branch-register encoding
4239 4285 operand cmpOp_reg() %{
4240 4286 match(Bool);
4241 4287
4242 4288 format %{ "" %}
4243 4289 interface(COND_INTER) %{
4244 4290 equal (0x1);
4245 4291 not_equal (0x5);
4246 4292 less (0x3);
4247 4293 greater_equal(0x7);
4248 4294 less_equal (0x2);
4249 4295 greater (0x6);
4250 4296 %}
4251 4297 %}
4252 4298
4253 4299 // Comparison Code, floating, unordered same as less
4254 4300 operand cmpOpF() %{
4255 4301 match(Bool);
4256 4302
4257 4303 format %{ "fl" %}
4258 4304 interface(COND_INTER) %{
4259 4305 equal(0x9);
4260 4306 not_equal(0x1);
4261 4307 less(0x3);
4262 4308 greater_equal(0xB);
4263 4309 less_equal(0xE);
4264 4310 greater(0x6);
4265 4311 %}
4266 4312 %}
4267 4313
4268 4314 // Used by long compare
4269 4315 operand cmpOp_commute() %{
4270 4316 match(Bool);
4271 4317
4272 4318 format %{ "" %}
4273 4319 interface(COND_INTER) %{
4274 4320 equal(0x1);
4275 4321 not_equal(0x9);
4276 4322 less(0xA);
4277 4323 greater_equal(0x2);
4278 4324 less_equal(0xB);
4279 4325 greater(0x3);
4280 4326 %}
4281 4327 %}
4282 4328
4283 4329 //----------OPERAND CLASSES----------------------------------------------------
4284 4330 // Operand Classes are groups of operands that are used to simplify
4285 4331 // instruction definitions by not requiring the AD writer to specify separate
4286 4332 // instructions for every form of operand when the instruction accepts
4287 4333 // multiple operand types with the same basic encoding and format. The classic
4288 4334 // case of this is memory operands.
4289 4335 opclass memory( indirect, indOffset13, indIndex );
4290 4336 opclass indIndexMemory( indIndex );
4291 4337
4292 4338 //----------PIPELINE-----------------------------------------------------------
4293 4339 pipeline %{
4294 4340
4295 4341 //----------ATTRIBUTES---------------------------------------------------------
4296 4342 attributes %{
4297 4343 fixed_size_instructions; // Fixed size instructions
4298 4344 branch_has_delay_slot; // Branch has delay slot following
4299 4345 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4300 4346 instruction_unit_size = 4; // An instruction is 4 bytes long
4301 4347 instruction_fetch_unit_size = 16; // The processor fetches one line
4302 4348 instruction_fetch_units = 1; // of 16 bytes
4303 4349
4304 4350 // List of nop instructions
4305 4351 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4306 4352 %}
4307 4353
4308 4354 //----------RESOURCES----------------------------------------------------------
4309 4355 // Resources are the functional units available to the machine
4310 4356 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4311 4357
4312 4358 //----------PIPELINE DESCRIPTION-----------------------------------------------
4313 4359 // Pipeline Description specifies the stages in the machine's pipeline
4314 4360
4315 4361 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4316 4362
4317 4363 //----------PIPELINE CLASSES---------------------------------------------------
4318 4364 // Pipeline Classes describe the stages in which input and output are
4319 4365 // referenced by the hardware pipeline.
4320 4366
4321 4367 // Integer ALU reg-reg operation
4322 4368 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4323 4369 single_instruction;
4324 4370 dst : E(write);
4325 4371 src1 : R(read);
4326 4372 src2 : R(read);
4327 4373 IALU : R;
4328 4374 %}
4329 4375
4330 4376 // Integer ALU reg-reg long operation
4331 4377 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4332 4378 instruction_count(2);
4333 4379 dst : E(write);
4334 4380 src1 : R(read);
4335 4381 src2 : R(read);
4336 4382 IALU : R;
4337 4383 IALU : R;
4338 4384 %}
4339 4385
4340 4386 // Integer ALU reg-reg long dependent operation
4341 4387 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4342 4388 instruction_count(1); multiple_bundles;
4343 4389 dst : E(write);
4344 4390 src1 : R(read);
4345 4391 src2 : R(read);
4346 4392 cr : E(write);
4347 4393 IALU : R(2);
4348 4394 %}
4349 4395
4350 4396 // Integer ALU reg-imm operaion
4351 4397 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4352 4398 single_instruction;
4353 4399 dst : E(write);
4354 4400 src1 : R(read);
4355 4401 IALU : R;
4356 4402 %}
4357 4403
4358 4404 // Integer ALU reg-reg operation with condition code
4359 4405 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4360 4406 single_instruction;
4361 4407 dst : E(write);
4362 4408 cr : E(write);
4363 4409 src1 : R(read);
4364 4410 src2 : R(read);
4365 4411 IALU : R;
4366 4412 %}
4367 4413
4368 4414 // Integer ALU reg-imm operation with condition code
4369 4415 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4370 4416 single_instruction;
4371 4417 dst : E(write);
4372 4418 cr : E(write);
4373 4419 src1 : R(read);
4374 4420 IALU : R;
4375 4421 %}
4376 4422
4377 4423 // Integer ALU zero-reg operation
4378 4424 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4379 4425 single_instruction;
4380 4426 dst : E(write);
4381 4427 src2 : R(read);
4382 4428 IALU : R;
4383 4429 %}
4384 4430
4385 4431 // Integer ALU zero-reg operation with condition code only
4386 4432 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4387 4433 single_instruction;
4388 4434 cr : E(write);
4389 4435 src : R(read);
4390 4436 IALU : R;
4391 4437 %}
4392 4438
4393 4439 // Integer ALU reg-reg operation with condition code only
4394 4440 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4395 4441 single_instruction;
4396 4442 cr : E(write);
4397 4443 src1 : R(read);
4398 4444 src2 : R(read);
4399 4445 IALU : R;
4400 4446 %}
4401 4447
4402 4448 // Integer ALU reg-imm operation with condition code only
4403 4449 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4404 4450 single_instruction;
4405 4451 cr : E(write);
4406 4452 src1 : R(read);
4407 4453 IALU : R;
4408 4454 %}
4409 4455
4410 4456 // Integer ALU reg-reg-zero operation with condition code only
4411 4457 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4412 4458 single_instruction;
4413 4459 cr : E(write);
4414 4460 src1 : R(read);
4415 4461 src2 : R(read);
4416 4462 IALU : R;
4417 4463 %}
4418 4464
4419 4465 // Integer ALU reg-imm-zero operation with condition code only
4420 4466 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4421 4467 single_instruction;
4422 4468 cr : E(write);
4423 4469 src1 : R(read);
4424 4470 IALU : R;
4425 4471 %}
4426 4472
4427 4473 // Integer ALU reg-reg operation with condition code, src1 modified
4428 4474 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4429 4475 single_instruction;
4430 4476 cr : E(write);
4431 4477 src1 : E(write);
4432 4478 src1 : R(read);
4433 4479 src2 : R(read);
4434 4480 IALU : R;
4435 4481 %}
4436 4482
4437 4483 // Integer ALU reg-imm operation with condition code, src1 modified
4438 4484 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4439 4485 single_instruction;
4440 4486 cr : E(write);
4441 4487 src1 : E(write);
4442 4488 src1 : R(read);
4443 4489 IALU : R;
4444 4490 %}
4445 4491
4446 4492 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4447 4493 multiple_bundles;
4448 4494 dst : E(write)+4;
4449 4495 cr : E(write);
4450 4496 src1 : R(read);
4451 4497 src2 : R(read);
4452 4498 IALU : R(3);
4453 4499 BR : R(2);
4454 4500 %}
4455 4501
4456 4502 // Integer ALU operation
4457 4503 pipe_class ialu_none(iRegI dst) %{
4458 4504 single_instruction;
4459 4505 dst : E(write);
4460 4506 IALU : R;
4461 4507 %}
4462 4508
4463 4509 // Integer ALU reg operation
4464 4510 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4465 4511 single_instruction; may_have_no_code;
4466 4512 dst : E(write);
4467 4513 src : R(read);
4468 4514 IALU : R;
4469 4515 %}
4470 4516
4471 4517 // Integer ALU reg conditional operation
4472 4518 // This instruction has a 1 cycle stall, and cannot execute
4473 4519 // in the same cycle as the instruction setting the condition
4474 4520 // code. We kludge this by pretending to read the condition code
4475 4521 // 1 cycle earlier, and by marking the functional units as busy
4476 4522 // for 2 cycles with the result available 1 cycle later than
4477 4523 // is really the case.
4478 4524 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4479 4525 single_instruction;
4480 4526 op2_out : C(write);
4481 4527 op1 : R(read);
4482 4528 cr : R(read); // This is really E, with a 1 cycle stall
4483 4529 BR : R(2);
4484 4530 MS : R(2);
4485 4531 %}
4486 4532
4487 4533 #ifdef _LP64
4488 4534 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4489 4535 instruction_count(1); multiple_bundles;
4490 4536 dst : C(write)+1;
4491 4537 src : R(read)+1;
4492 4538 IALU : R(1);
4493 4539 BR : E(2);
4494 4540 MS : E(2);
4495 4541 %}
4496 4542 #endif
4497 4543
4498 4544 // Integer ALU reg operation
4499 4545 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4500 4546 single_instruction; may_have_no_code;
4501 4547 dst : E(write);
4502 4548 src : R(read);
4503 4549 IALU : R;
4504 4550 %}
4505 4551 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4506 4552 single_instruction; may_have_no_code;
4507 4553 dst : E(write);
4508 4554 src : R(read);
4509 4555 IALU : R;
4510 4556 %}
4511 4557
4512 4558 // Two integer ALU reg operations
4513 4559 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4514 4560 instruction_count(2);
4515 4561 dst : E(write);
4516 4562 src : R(read);
4517 4563 A0 : R;
4518 4564 A1 : R;
4519 4565 %}
4520 4566
4521 4567 // Two integer ALU reg operations
4522 4568 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4523 4569 instruction_count(2); may_have_no_code;
4524 4570 dst : E(write);
4525 4571 src : R(read);
4526 4572 A0 : R;
4527 4573 A1 : R;
4528 4574 %}
4529 4575
4530 4576 // Integer ALU imm operation
4531 4577 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4532 4578 single_instruction;
4533 4579 dst : E(write);
4534 4580 IALU : R;
4535 4581 %}
4536 4582
4537 4583 // Integer ALU reg-reg with carry operation
4538 4584 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4539 4585 single_instruction;
4540 4586 dst : E(write);
4541 4587 src1 : R(read);
4542 4588 src2 : R(read);
4543 4589 IALU : R;
4544 4590 %}
4545 4591
4546 4592 // Integer ALU cc operation
4547 4593 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4548 4594 single_instruction;
4549 4595 dst : E(write);
4550 4596 cc : R(read);
4551 4597 IALU : R;
4552 4598 %}
4553 4599
4554 4600 // Integer ALU cc / second IALU operation
4555 4601 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4556 4602 instruction_count(1); multiple_bundles;
4557 4603 dst : E(write)+1;
4558 4604 src : R(read);
4559 4605 IALU : R;
4560 4606 %}
4561 4607
4562 4608 // Integer ALU cc / second IALU operation
4563 4609 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4564 4610 instruction_count(1); multiple_bundles;
4565 4611 dst : E(write)+1;
4566 4612 p : R(read);
4567 4613 q : R(read);
4568 4614 IALU : R;
4569 4615 %}
4570 4616
4571 4617 // Integer ALU hi-lo-reg operation
4572 4618 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4573 4619 instruction_count(1); multiple_bundles;
4574 4620 dst : E(write)+1;
4575 4621 IALU : R(2);
4576 4622 %}
4577 4623
4578 4624 // Float ALU hi-lo-reg operation (with temp)
4579 4625 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4580 4626 instruction_count(1); multiple_bundles;
4581 4627 dst : E(write)+1;
4582 4628 IALU : R(2);
4583 4629 %}
4584 4630
4585 4631 // Long Constant
4586 4632 pipe_class loadConL( iRegL dst, immL src ) %{
4587 4633 instruction_count(2); multiple_bundles;
4588 4634 dst : E(write)+1;
4589 4635 IALU : R(2);
4590 4636 IALU : R(2);
4591 4637 %}
4592 4638
4593 4639 // Pointer Constant
4594 4640 pipe_class loadConP( iRegP dst, immP src ) %{
4595 4641 instruction_count(0); multiple_bundles;
4596 4642 fixed_latency(6);
4597 4643 %}
4598 4644
4599 4645 // Polling Address
4600 4646 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4601 4647 #ifdef _LP64
4602 4648 instruction_count(0); multiple_bundles;
4603 4649 fixed_latency(6);
4604 4650 #else
4605 4651 dst : E(write);
4606 4652 IALU : R;
4607 4653 #endif
4608 4654 %}
4609 4655
4610 4656 // Long Constant small
4611 4657 pipe_class loadConLlo( iRegL dst, immL src ) %{
4612 4658 instruction_count(2);
4613 4659 dst : E(write);
4614 4660 IALU : R;
4615 4661 IALU : R;
4616 4662 %}
4617 4663
4618 4664 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4619 4665 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4620 4666 instruction_count(1); multiple_bundles;
4621 4667 src : R(read);
4622 4668 dst : M(write)+1;
4623 4669 IALU : R;
4624 4670 MS : E;
4625 4671 %}
4626 4672
4627 4673 // Integer ALU nop operation
4628 4674 pipe_class ialu_nop() %{
4629 4675 single_instruction;
4630 4676 IALU : R;
4631 4677 %}
4632 4678
4633 4679 // Integer ALU nop operation
4634 4680 pipe_class ialu_nop_A0() %{
4635 4681 single_instruction;
4636 4682 A0 : R;
4637 4683 %}
4638 4684
4639 4685 // Integer ALU nop operation
4640 4686 pipe_class ialu_nop_A1() %{
4641 4687 single_instruction;
4642 4688 A1 : R;
4643 4689 %}
4644 4690
4645 4691 // Integer Multiply reg-reg operation
4646 4692 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4647 4693 single_instruction;
4648 4694 dst : E(write);
4649 4695 src1 : R(read);
4650 4696 src2 : R(read);
4651 4697 MS : R(5);
4652 4698 %}
4653 4699
4654 4700 // Integer Multiply reg-imm operation
4655 4701 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4656 4702 single_instruction;
4657 4703 dst : E(write);
4658 4704 src1 : R(read);
4659 4705 MS : R(5);
4660 4706 %}
4661 4707
4662 4708 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4663 4709 single_instruction;
4664 4710 dst : E(write)+4;
4665 4711 src1 : R(read);
4666 4712 src2 : R(read);
4667 4713 MS : R(6);
4668 4714 %}
4669 4715
4670 4716 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4671 4717 single_instruction;
4672 4718 dst : E(write)+4;
4673 4719 src1 : R(read);
4674 4720 MS : R(6);
4675 4721 %}
4676 4722
4677 4723 // Integer Divide reg-reg
4678 4724 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4679 4725 instruction_count(1); multiple_bundles;
4680 4726 dst : E(write);
4681 4727 temp : E(write);
4682 4728 src1 : R(read);
4683 4729 src2 : R(read);
4684 4730 temp : R(read);
4685 4731 MS : R(38);
4686 4732 %}
4687 4733
4688 4734 // Integer Divide reg-imm
4689 4735 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4690 4736 instruction_count(1); multiple_bundles;
4691 4737 dst : E(write);
4692 4738 temp : E(write);
4693 4739 src1 : R(read);
4694 4740 temp : R(read);
4695 4741 MS : R(38);
4696 4742 %}
4697 4743
4698 4744 // Long Divide
4699 4745 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4700 4746 dst : E(write)+71;
4701 4747 src1 : R(read);
4702 4748 src2 : R(read)+1;
4703 4749 MS : R(70);
4704 4750 %}
4705 4751
4706 4752 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4707 4753 dst : E(write)+71;
4708 4754 src1 : R(read);
4709 4755 MS : R(70);
4710 4756 %}
4711 4757
4712 4758 // Floating Point Add Float
4713 4759 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4714 4760 single_instruction;
4715 4761 dst : X(write);
4716 4762 src1 : E(read);
4717 4763 src2 : E(read);
4718 4764 FA : R;
4719 4765 %}
4720 4766
4721 4767 // Floating Point Add Double
4722 4768 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4723 4769 single_instruction;
4724 4770 dst : X(write);
4725 4771 src1 : E(read);
4726 4772 src2 : E(read);
4727 4773 FA : R;
4728 4774 %}
4729 4775
4730 4776 // Floating Point Conditional Move based on integer flags
4731 4777 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4732 4778 single_instruction;
4733 4779 dst : X(write);
4734 4780 src : E(read);
4735 4781 cr : R(read);
4736 4782 FA : R(2);
4737 4783 BR : R(2);
4738 4784 %}
4739 4785
4740 4786 // Floating Point Conditional Move based on integer flags
4741 4787 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4742 4788 single_instruction;
4743 4789 dst : X(write);
4744 4790 src : E(read);
4745 4791 cr : R(read);
4746 4792 FA : R(2);
4747 4793 BR : R(2);
4748 4794 %}
4749 4795
4750 4796 // Floating Point Multiply Float
4751 4797 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4752 4798 single_instruction;
4753 4799 dst : X(write);
4754 4800 src1 : E(read);
4755 4801 src2 : E(read);
4756 4802 FM : R;
4757 4803 %}
4758 4804
4759 4805 // Floating Point Multiply Double
4760 4806 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4761 4807 single_instruction;
4762 4808 dst : X(write);
4763 4809 src1 : E(read);
4764 4810 src2 : E(read);
4765 4811 FM : R;
4766 4812 %}
4767 4813
4768 4814 // Floating Point Divide Float
4769 4815 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4770 4816 single_instruction;
4771 4817 dst : X(write);
4772 4818 src1 : E(read);
4773 4819 src2 : E(read);
4774 4820 FM : R;
4775 4821 FDIV : C(14);
4776 4822 %}
4777 4823
4778 4824 // Floating Point Divide Double
4779 4825 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4780 4826 single_instruction;
4781 4827 dst : X(write);
4782 4828 src1 : E(read);
4783 4829 src2 : E(read);
4784 4830 FM : R;
4785 4831 FDIV : C(17);
4786 4832 %}
4787 4833
4788 4834 // Floating Point Move/Negate/Abs Float
4789 4835 pipe_class faddF_reg(regF dst, regF src) %{
4790 4836 single_instruction;
4791 4837 dst : W(write);
4792 4838 src : E(read);
4793 4839 FA : R(1);
4794 4840 %}
4795 4841
4796 4842 // Floating Point Move/Negate/Abs Double
4797 4843 pipe_class faddD_reg(regD dst, regD src) %{
4798 4844 single_instruction;
4799 4845 dst : W(write);
4800 4846 src : E(read);
4801 4847 FA : R;
4802 4848 %}
4803 4849
4804 4850 // Floating Point Convert F->D
4805 4851 pipe_class fcvtF2D(regD dst, regF src) %{
4806 4852 single_instruction;
4807 4853 dst : X(write);
4808 4854 src : E(read);
4809 4855 FA : R;
4810 4856 %}
4811 4857
4812 4858 // Floating Point Convert I->D
4813 4859 pipe_class fcvtI2D(regD dst, regF src) %{
4814 4860 single_instruction;
4815 4861 dst : X(write);
4816 4862 src : E(read);
4817 4863 FA : R;
4818 4864 %}
4819 4865
4820 4866 // Floating Point Convert LHi->D
4821 4867 pipe_class fcvtLHi2D(regD dst, regD src) %{
4822 4868 single_instruction;
4823 4869 dst : X(write);
4824 4870 src : E(read);
4825 4871 FA : R;
4826 4872 %}
4827 4873
4828 4874 // Floating Point Convert L->D
4829 4875 pipe_class fcvtL2D(regD dst, regF src) %{
4830 4876 single_instruction;
4831 4877 dst : X(write);
4832 4878 src : E(read);
4833 4879 FA : R;
4834 4880 %}
4835 4881
4836 4882 // Floating Point Convert L->F
4837 4883 pipe_class fcvtL2F(regD dst, regF src) %{
4838 4884 single_instruction;
4839 4885 dst : X(write);
4840 4886 src : E(read);
4841 4887 FA : R;
4842 4888 %}
4843 4889
4844 4890 // Floating Point Convert D->F
4845 4891 pipe_class fcvtD2F(regD dst, regF src) %{
4846 4892 single_instruction;
4847 4893 dst : X(write);
4848 4894 src : E(read);
4849 4895 FA : R;
4850 4896 %}
4851 4897
4852 4898 // Floating Point Convert I->L
4853 4899 pipe_class fcvtI2L(regD dst, regF src) %{
4854 4900 single_instruction;
4855 4901 dst : X(write);
4856 4902 src : E(read);
4857 4903 FA : R;
4858 4904 %}
4859 4905
4860 4906 // Floating Point Convert D->F
4861 4907 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4862 4908 instruction_count(1); multiple_bundles;
4863 4909 dst : X(write)+6;
4864 4910 src : E(read);
4865 4911 FA : R;
4866 4912 %}
4867 4913
4868 4914 // Floating Point Convert D->L
4869 4915 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4870 4916 instruction_count(1); multiple_bundles;
4871 4917 dst : X(write)+6;
4872 4918 src : E(read);
4873 4919 FA : R;
4874 4920 %}
4875 4921
4876 4922 // Floating Point Convert F->I
4877 4923 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4878 4924 instruction_count(1); multiple_bundles;
4879 4925 dst : X(write)+6;
4880 4926 src : E(read);
4881 4927 FA : R;
4882 4928 %}
4883 4929
4884 4930 // Floating Point Convert F->L
4885 4931 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4886 4932 instruction_count(1); multiple_bundles;
4887 4933 dst : X(write)+6;
4888 4934 src : E(read);
4889 4935 FA : R;
4890 4936 %}
4891 4937
4892 4938 // Floating Point Convert I->F
4893 4939 pipe_class fcvtI2F(regF dst, regF src) %{
4894 4940 single_instruction;
4895 4941 dst : X(write);
4896 4942 src : E(read);
4897 4943 FA : R;
4898 4944 %}
4899 4945
4900 4946 // Floating Point Compare
4901 4947 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4902 4948 single_instruction;
4903 4949 cr : X(write);
4904 4950 src1 : E(read);
4905 4951 src2 : E(read);
4906 4952 FA : R;
4907 4953 %}
4908 4954
4909 4955 // Floating Point Compare
4910 4956 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4911 4957 single_instruction;
4912 4958 cr : X(write);
4913 4959 src1 : E(read);
4914 4960 src2 : E(read);
4915 4961 FA : R;
4916 4962 %}
4917 4963
4918 4964 // Floating Add Nop
4919 4965 pipe_class fadd_nop() %{
4920 4966 single_instruction;
4921 4967 FA : R;
4922 4968 %}
4923 4969
4924 4970 // Integer Store to Memory
4925 4971 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4926 4972 single_instruction;
4927 4973 mem : R(read);
4928 4974 src : C(read);
4929 4975 MS : R;
4930 4976 %}
4931 4977
4932 4978 // Integer Store to Memory
4933 4979 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4934 4980 single_instruction;
4935 4981 mem : R(read);
4936 4982 src : C(read);
4937 4983 MS : R;
4938 4984 %}
4939 4985
4940 4986 // Integer Store Zero to Memory
4941 4987 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4942 4988 single_instruction;
4943 4989 mem : R(read);
4944 4990 MS : R;
4945 4991 %}
4946 4992
4947 4993 // Special Stack Slot Store
4948 4994 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4949 4995 single_instruction;
4950 4996 stkSlot : R(read);
4951 4997 src : C(read);
4952 4998 MS : R;
4953 4999 %}
4954 5000
4955 5001 // Special Stack Slot Store
4956 5002 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4957 5003 instruction_count(2); multiple_bundles;
4958 5004 stkSlot : R(read);
4959 5005 src : C(read);
4960 5006 MS : R(2);
4961 5007 %}
4962 5008
4963 5009 // Float Store
4964 5010 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4965 5011 single_instruction;
4966 5012 mem : R(read);
4967 5013 src : C(read);
4968 5014 MS : R;
4969 5015 %}
4970 5016
4971 5017 // Float Store
4972 5018 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4973 5019 single_instruction;
4974 5020 mem : R(read);
4975 5021 MS : R;
4976 5022 %}
4977 5023
4978 5024 // Double Store
4979 5025 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4980 5026 instruction_count(1);
4981 5027 mem : R(read);
4982 5028 src : C(read);
4983 5029 MS : R;
4984 5030 %}
4985 5031
4986 5032 // Double Store
4987 5033 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4988 5034 single_instruction;
4989 5035 mem : R(read);
4990 5036 MS : R;
4991 5037 %}
4992 5038
4993 5039 // Special Stack Slot Float Store
4994 5040 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4995 5041 single_instruction;
4996 5042 stkSlot : R(read);
4997 5043 src : C(read);
4998 5044 MS : R;
4999 5045 %}
5000 5046
5001 5047 // Special Stack Slot Double Store
5002 5048 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5003 5049 single_instruction;
5004 5050 stkSlot : R(read);
5005 5051 src : C(read);
5006 5052 MS : R;
5007 5053 %}
5008 5054
5009 5055 // Integer Load (when sign bit propagation not needed)
5010 5056 pipe_class iload_mem(iRegI dst, memory mem) %{
5011 5057 single_instruction;
5012 5058 mem : R(read);
5013 5059 dst : C(write);
5014 5060 MS : R;
5015 5061 %}
5016 5062
5017 5063 // Integer Load from stack operand
5018 5064 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5019 5065 single_instruction;
5020 5066 mem : R(read);
5021 5067 dst : C(write);
5022 5068 MS : R;
5023 5069 %}
5024 5070
5025 5071 // Integer Load (when sign bit propagation or masking is needed)
5026 5072 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5027 5073 single_instruction;
5028 5074 mem : R(read);
5029 5075 dst : M(write);
5030 5076 MS : R;
5031 5077 %}
5032 5078
5033 5079 // Float Load
5034 5080 pipe_class floadF_mem(regF dst, memory mem) %{
5035 5081 single_instruction;
5036 5082 mem : R(read);
5037 5083 dst : M(write);
5038 5084 MS : R;
5039 5085 %}
5040 5086
5041 5087 // Float Load
5042 5088 pipe_class floadD_mem(regD dst, memory mem) %{
5043 5089 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5044 5090 mem : R(read);
5045 5091 dst : M(write);
5046 5092 MS : R;
5047 5093 %}
5048 5094
5049 5095 // Float Load
5050 5096 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5051 5097 single_instruction;
5052 5098 stkSlot : R(read);
5053 5099 dst : M(write);
5054 5100 MS : R;
5055 5101 %}
5056 5102
5057 5103 // Float Load
5058 5104 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5059 5105 single_instruction;
5060 5106 stkSlot : R(read);
5061 5107 dst : M(write);
5062 5108 MS : R;
5063 5109 %}
5064 5110
5065 5111 // Memory Nop
5066 5112 pipe_class mem_nop() %{
5067 5113 single_instruction;
5068 5114 MS : R;
5069 5115 %}
5070 5116
5071 5117 pipe_class sethi(iRegP dst, immI src) %{
5072 5118 single_instruction;
5073 5119 dst : E(write);
5074 5120 IALU : R;
5075 5121 %}
5076 5122
5077 5123 pipe_class loadPollP(iRegP poll) %{
5078 5124 single_instruction;
5079 5125 poll : R(read);
5080 5126 MS : R;
5081 5127 %}
5082 5128
5083 5129 pipe_class br(Universe br, label labl) %{
5084 5130 single_instruction_with_delay_slot;
5085 5131 BR : R;
5086 5132 %}
5087 5133
5088 5134 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5089 5135 single_instruction_with_delay_slot;
5090 5136 cr : E(read);
5091 5137 BR : R;
5092 5138 %}
5093 5139
5094 5140 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5095 5141 single_instruction_with_delay_slot;
5096 5142 op1 : E(read);
5097 5143 BR : R;
5098 5144 MS : R;
5099 5145 %}
5100 5146
5101 5147 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5102 5148 single_instruction_with_delay_slot;
5103 5149 cr : E(read);
5104 5150 BR : R;
5105 5151 %}
5106 5152
5107 5153 pipe_class br_nop() %{
5108 5154 single_instruction;
5109 5155 BR : R;
5110 5156 %}
5111 5157
5112 5158 pipe_class simple_call(method meth) %{
5113 5159 instruction_count(2); multiple_bundles; force_serialization;
5114 5160 fixed_latency(100);
5115 5161 BR : R(1);
5116 5162 MS : R(1);
5117 5163 A0 : R(1);
5118 5164 %}
5119 5165
5120 5166 pipe_class compiled_call(method meth) %{
5121 5167 instruction_count(1); multiple_bundles; force_serialization;
5122 5168 fixed_latency(100);
5123 5169 MS : R(1);
5124 5170 %}
5125 5171
5126 5172 pipe_class call(method meth) %{
5127 5173 instruction_count(0); multiple_bundles; force_serialization;
5128 5174 fixed_latency(100);
5129 5175 %}
5130 5176
5131 5177 pipe_class tail_call(Universe ignore, label labl) %{
5132 5178 single_instruction; has_delay_slot;
5133 5179 fixed_latency(100);
5134 5180 BR : R(1);
5135 5181 MS : R(1);
5136 5182 %}
5137 5183
5138 5184 pipe_class ret(Universe ignore) %{
5139 5185 single_instruction; has_delay_slot;
5140 5186 BR : R(1);
5141 5187 MS : R(1);
5142 5188 %}
5143 5189
5144 5190 pipe_class ret_poll(g3RegP poll) %{
5145 5191 instruction_count(3); has_delay_slot;
5146 5192 poll : E(read);
5147 5193 MS : R;
5148 5194 %}
5149 5195
5150 5196 // The real do-nothing guy
5151 5197 pipe_class empty( ) %{
5152 5198 instruction_count(0);
5153 5199 %}
5154 5200
5155 5201 pipe_class long_memory_op() %{
5156 5202 instruction_count(0); multiple_bundles; force_serialization;
5157 5203 fixed_latency(25);
5158 5204 MS : R(1);
5159 5205 %}
5160 5206
5161 5207 // Check-cast
5162 5208 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5163 5209 array : R(read);
5164 5210 match : R(read);
5165 5211 IALU : R(2);
5166 5212 BR : R(2);
5167 5213 MS : R;
5168 5214 %}
5169 5215
5170 5216 // Convert FPU flags into +1,0,-1
5171 5217 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5172 5218 src1 : E(read);
5173 5219 src2 : E(read);
5174 5220 dst : E(write);
5175 5221 FA : R;
5176 5222 MS : R(2);
5177 5223 BR : R(2);
5178 5224 %}
5179 5225
5180 5226 // Compare for p < q, and conditionally add y
5181 5227 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5182 5228 p : E(read);
5183 5229 q : E(read);
5184 5230 y : E(read);
5185 5231 IALU : R(3)
5186 5232 %}
5187 5233
5188 5234 // Perform a compare, then move conditionally in a branch delay slot.
5189 5235 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5190 5236 src2 : E(read);
5191 5237 srcdst : E(read);
5192 5238 IALU : R;
5193 5239 BR : R;
5194 5240 %}
5195 5241
5196 5242 // Define the class for the Nop node
5197 5243 define %{
5198 5244 MachNop = ialu_nop;
5199 5245 %}
5200 5246
5201 5247 %}
5202 5248
5203 5249 //----------INSTRUCTIONS-------------------------------------------------------
5204 5250
5205 5251 //------------Special Stack Slot instructions - no match rules-----------------
5206 5252 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5207 5253 // No match rule to avoid chain rule match.
5208 5254 effect(DEF dst, USE src);
5209 5255 ins_cost(MEMORY_REF_COST);
5210 5256 size(4);
5211 5257 format %{ "LDF $src,$dst\t! stkI to regF" %}
5212 5258 opcode(Assembler::ldf_op3);
5213 5259 ins_encode(simple_form3_mem_reg(src, dst));
5214 5260 ins_pipe(floadF_stk);
5215 5261 %}
5216 5262
5217 5263 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5218 5264 // No match rule to avoid chain rule match.
5219 5265 effect(DEF dst, USE src);
5220 5266 ins_cost(MEMORY_REF_COST);
5221 5267 size(4);
5222 5268 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5223 5269 opcode(Assembler::lddf_op3);
5224 5270 ins_encode(simple_form3_mem_reg(src, dst));
5225 5271 ins_pipe(floadD_stk);
5226 5272 %}
5227 5273
5228 5274 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5229 5275 // No match rule to avoid chain rule match.
5230 5276 effect(DEF dst, USE src);
5231 5277 ins_cost(MEMORY_REF_COST);
5232 5278 size(4);
5233 5279 format %{ "STF $src,$dst\t! regF to stkI" %}
5234 5280 opcode(Assembler::stf_op3);
5235 5281 ins_encode(simple_form3_mem_reg(dst, src));
5236 5282 ins_pipe(fstoreF_stk_reg);
5237 5283 %}
5238 5284
5239 5285 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5240 5286 // No match rule to avoid chain rule match.
5241 5287 effect(DEF dst, USE src);
5242 5288 ins_cost(MEMORY_REF_COST);
5243 5289 size(4);
5244 5290 format %{ "STDF $src,$dst\t! regD to stkL" %}
5245 5291 opcode(Assembler::stdf_op3);
5246 5292 ins_encode(simple_form3_mem_reg(dst, src));
5247 5293 ins_pipe(fstoreD_stk_reg);
5248 5294 %}
5249 5295
5250 5296 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5251 5297 effect(DEF dst, USE src);
5252 5298 ins_cost(MEMORY_REF_COST*2);
5253 5299 size(8);
5254 5300 format %{ "STW $src,$dst.hi\t! long\n\t"
5255 5301 "STW R_G0,$dst.lo" %}
5256 5302 opcode(Assembler::stw_op3);
5257 5303 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5258 5304 ins_pipe(lstoreI_stk_reg);
5259 5305 %}
5260 5306
5261 5307 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5262 5308 // No match rule to avoid chain rule match.
5263 5309 effect(DEF dst, USE src);
5264 5310 ins_cost(MEMORY_REF_COST);
5265 5311 size(4);
5266 5312 format %{ "STX $src,$dst\t! regL to stkD" %}
5267 5313 opcode(Assembler::stx_op3);
5268 5314 ins_encode(simple_form3_mem_reg( dst, src ) );
5269 5315 ins_pipe(istore_stk_reg);
5270 5316 %}
5271 5317
5272 5318 //---------- Chain stack slots between similar types --------
5273 5319
5274 5320 // Load integer from stack slot
5275 5321 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5276 5322 match(Set dst src);
5277 5323 ins_cost(MEMORY_REF_COST);
5278 5324
5279 5325 size(4);
5280 5326 format %{ "LDUW $src,$dst\t!stk" %}
5281 5327 opcode(Assembler::lduw_op3);
5282 5328 ins_encode(simple_form3_mem_reg( src, dst ) );
5283 5329 ins_pipe(iload_mem);
5284 5330 %}
5285 5331
5286 5332 // Store integer to stack slot
5287 5333 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5288 5334 match(Set dst src);
5289 5335 ins_cost(MEMORY_REF_COST);
5290 5336
5291 5337 size(4);
5292 5338 format %{ "STW $src,$dst\t!stk" %}
5293 5339 opcode(Assembler::stw_op3);
5294 5340 ins_encode(simple_form3_mem_reg( dst, src ) );
5295 5341 ins_pipe(istore_mem_reg);
5296 5342 %}
5297 5343
5298 5344 // Load long from stack slot
5299 5345 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5300 5346 match(Set dst src);
5301 5347
5302 5348 ins_cost(MEMORY_REF_COST);
5303 5349 size(4);
5304 5350 format %{ "LDX $src,$dst\t! long" %}
5305 5351 opcode(Assembler::ldx_op3);
5306 5352 ins_encode(simple_form3_mem_reg( src, dst ) );
5307 5353 ins_pipe(iload_mem);
5308 5354 %}
5309 5355
5310 5356 // Store long to stack slot
5311 5357 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5312 5358 match(Set dst src);
5313 5359
5314 5360 ins_cost(MEMORY_REF_COST);
5315 5361 size(4);
5316 5362 format %{ "STX $src,$dst\t! long" %}
5317 5363 opcode(Assembler::stx_op3);
5318 5364 ins_encode(simple_form3_mem_reg( dst, src ) );
5319 5365 ins_pipe(istore_mem_reg);
5320 5366 %}
5321 5367
5322 5368 #ifdef _LP64
5323 5369 // Load pointer from stack slot, 64-bit encoding
5324 5370 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5325 5371 match(Set dst src);
5326 5372 ins_cost(MEMORY_REF_COST);
5327 5373 size(4);
5328 5374 format %{ "LDX $src,$dst\t!ptr" %}
5329 5375 opcode(Assembler::ldx_op3);
5330 5376 ins_encode(simple_form3_mem_reg( src, dst ) );
5331 5377 ins_pipe(iload_mem);
5332 5378 %}
5333 5379
5334 5380 // Store pointer to stack slot
5335 5381 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5336 5382 match(Set dst src);
5337 5383 ins_cost(MEMORY_REF_COST);
5338 5384 size(4);
5339 5385 format %{ "STX $src,$dst\t!ptr" %}
5340 5386 opcode(Assembler::stx_op3);
5341 5387 ins_encode(simple_form3_mem_reg( dst, src ) );
5342 5388 ins_pipe(istore_mem_reg);
5343 5389 %}
5344 5390 #else // _LP64
5345 5391 // Load pointer from stack slot, 32-bit encoding
5346 5392 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5347 5393 match(Set dst src);
5348 5394 ins_cost(MEMORY_REF_COST);
5349 5395 format %{ "LDUW $src,$dst\t!ptr" %}
5350 5396 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5351 5397 ins_encode(simple_form3_mem_reg( src, dst ) );
5352 5398 ins_pipe(iload_mem);
5353 5399 %}
5354 5400
5355 5401 // Store pointer to stack slot
5356 5402 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5357 5403 match(Set dst src);
5358 5404 ins_cost(MEMORY_REF_COST);
5359 5405 format %{ "STW $src,$dst\t!ptr" %}
5360 5406 opcode(Assembler::stw_op3, Assembler::ldst_op);
5361 5407 ins_encode(simple_form3_mem_reg( dst, src ) );
5362 5408 ins_pipe(istore_mem_reg);
5363 5409 %}
5364 5410 #endif // _LP64
5365 5411
5366 5412 //------------Special Nop instructions for bundling - no match rules-----------
5367 5413 // Nop using the A0 functional unit
5368 5414 instruct Nop_A0() %{
5369 5415 ins_cost(0);
5370 5416
5371 5417 format %{ "NOP ! Alu Pipeline" %}
5372 5418 opcode(Assembler::or_op3, Assembler::arith_op);
5373 5419 ins_encode( form2_nop() );
5374 5420 ins_pipe(ialu_nop_A0);
5375 5421 %}
5376 5422
5377 5423 // Nop using the A1 functional unit
5378 5424 instruct Nop_A1( ) %{
5379 5425 ins_cost(0);
5380 5426
5381 5427 format %{ "NOP ! Alu Pipeline" %}
5382 5428 opcode(Assembler::or_op3, Assembler::arith_op);
5383 5429 ins_encode( form2_nop() );
5384 5430 ins_pipe(ialu_nop_A1);
5385 5431 %}
5386 5432
5387 5433 // Nop using the memory functional unit
5388 5434 instruct Nop_MS( ) %{
5389 5435 ins_cost(0);
5390 5436
5391 5437 format %{ "NOP ! Memory Pipeline" %}
5392 5438 ins_encode( emit_mem_nop );
5393 5439 ins_pipe(mem_nop);
5394 5440 %}
5395 5441
5396 5442 // Nop using the floating add functional unit
5397 5443 instruct Nop_FA( ) %{
5398 5444 ins_cost(0);
5399 5445
5400 5446 format %{ "NOP ! Floating Add Pipeline" %}
5401 5447 ins_encode( emit_fadd_nop );
5402 5448 ins_pipe(fadd_nop);
5403 5449 %}
5404 5450
5405 5451 // Nop using the branch functional unit
5406 5452 instruct Nop_BR( ) %{
5407 5453 ins_cost(0);
5408 5454
5409 5455 format %{ "NOP ! Branch Pipeline" %}
5410 5456 ins_encode( emit_br_nop );
5411 5457 ins_pipe(br_nop);
5412 5458 %}
5413 5459
5414 5460 //----------Load/Store/Move Instructions---------------------------------------
5415 5461 //----------Load Instructions--------------------------------------------------
5416 5462 // Load Byte (8bit signed)
5417 5463 instruct loadB(iRegI dst, memory mem) %{
5418 5464 match(Set dst (LoadB mem));
5419 5465 ins_cost(MEMORY_REF_COST);
5420 5466
5421 5467 size(4);
5422 5468 format %{ "LDSB $mem,$dst\t! byte" %}
5423 5469 ins_encode %{
5424 5470 __ ldsb($mem$$Address, $dst$$Register);
5425 5471 %}
5426 5472 ins_pipe(iload_mask_mem);
5427 5473 %}
5428 5474
5429 5475 // Load Byte (8bit signed) into a Long Register
5430 5476 instruct loadB2L(iRegL dst, memory mem) %{
5431 5477 match(Set dst (ConvI2L (LoadB mem)));
5432 5478 ins_cost(MEMORY_REF_COST);
5433 5479
5434 5480 size(4);
5435 5481 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5436 5482 ins_encode %{
5437 5483 __ ldsb($mem$$Address, $dst$$Register);
5438 5484 %}
5439 5485 ins_pipe(iload_mask_mem);
5440 5486 %}
5441 5487
5442 5488 // Load Unsigned Byte (8bit UNsigned) into an int reg
5443 5489 instruct loadUB(iRegI dst, memory mem) %{
5444 5490 match(Set dst (LoadUB mem));
5445 5491 ins_cost(MEMORY_REF_COST);
5446 5492
5447 5493 size(4);
5448 5494 format %{ "LDUB $mem,$dst\t! ubyte" %}
5449 5495 ins_encode %{
5450 5496 __ ldub($mem$$Address, $dst$$Register);
5451 5497 %}
5452 5498 ins_pipe(iload_mem);
5453 5499 %}
5454 5500
5455 5501 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5456 5502 instruct loadUB2L(iRegL dst, memory mem) %{
5457 5503 match(Set dst (ConvI2L (LoadUB mem)));
5458 5504 ins_cost(MEMORY_REF_COST);
5459 5505
5460 5506 size(4);
5461 5507 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5462 5508 ins_encode %{
5463 5509 __ ldub($mem$$Address, $dst$$Register);
5464 5510 %}
5465 5511 ins_pipe(iload_mem);
5466 5512 %}
5467 5513
5468 5514 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5469 5515 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5470 5516 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5471 5517 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5472 5518
5473 5519 size(2*4);
5474 5520 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5475 5521 "AND $dst,$mask,$dst" %}
5476 5522 ins_encode %{
5477 5523 __ ldub($mem$$Address, $dst$$Register);
5478 5524 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5479 5525 %}
5480 5526 ins_pipe(iload_mem);
5481 5527 %}
5482 5528
5483 5529 // Load Short (16bit signed)
5484 5530 instruct loadS(iRegI dst, memory mem) %{
5485 5531 match(Set dst (LoadS mem));
5486 5532 ins_cost(MEMORY_REF_COST);
5487 5533
5488 5534 size(4);
5489 5535 format %{ "LDSH $mem,$dst\t! short" %}
5490 5536 ins_encode %{
5491 5537 __ ldsh($mem$$Address, $dst$$Register);
5492 5538 %}
5493 5539 ins_pipe(iload_mask_mem);
5494 5540 %}
5495 5541
5496 5542 // Load Short (16 bit signed) to Byte (8 bit signed)
5497 5543 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5498 5544 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5499 5545 ins_cost(MEMORY_REF_COST);
5500 5546
5501 5547 size(4);
5502 5548
5503 5549 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5504 5550 ins_encode %{
5505 5551 __ ldsb($mem$$Address, $dst$$Register, 1);
5506 5552 %}
5507 5553 ins_pipe(iload_mask_mem);
5508 5554 %}
5509 5555
5510 5556 // Load Short (16bit signed) into a Long Register
5511 5557 instruct loadS2L(iRegL dst, memory mem) %{
5512 5558 match(Set dst (ConvI2L (LoadS mem)));
5513 5559 ins_cost(MEMORY_REF_COST);
5514 5560
5515 5561 size(4);
5516 5562 format %{ "LDSH $mem,$dst\t! short -> long" %}
5517 5563 ins_encode %{
5518 5564 __ ldsh($mem$$Address, $dst$$Register);
5519 5565 %}
5520 5566 ins_pipe(iload_mask_mem);
5521 5567 %}
5522 5568
5523 5569 // Load Unsigned Short/Char (16bit UNsigned)
5524 5570 instruct loadUS(iRegI dst, memory mem) %{
5525 5571 match(Set dst (LoadUS mem));
5526 5572 ins_cost(MEMORY_REF_COST);
5527 5573
5528 5574 size(4);
5529 5575 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5530 5576 ins_encode %{
5531 5577 __ lduh($mem$$Address, $dst$$Register);
5532 5578 %}
5533 5579 ins_pipe(iload_mem);
5534 5580 %}
5535 5581
5536 5582 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5537 5583 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5538 5584 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5539 5585 ins_cost(MEMORY_REF_COST);
5540 5586
5541 5587 size(4);
5542 5588 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5543 5589 ins_encode %{
5544 5590 __ ldsb($mem$$Address, $dst$$Register, 1);
5545 5591 %}
5546 5592 ins_pipe(iload_mask_mem);
5547 5593 %}
5548 5594
5549 5595 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5550 5596 instruct loadUS2L(iRegL dst, memory mem) %{
5551 5597 match(Set dst (ConvI2L (LoadUS mem)));
5552 5598 ins_cost(MEMORY_REF_COST);
5553 5599
5554 5600 size(4);
5555 5601 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5556 5602 ins_encode %{
5557 5603 __ lduh($mem$$Address, $dst$$Register);
5558 5604 %}
5559 5605 ins_pipe(iload_mem);
5560 5606 %}
5561 5607
5562 5608 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5563 5609 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5564 5610 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5565 5611 ins_cost(MEMORY_REF_COST);
5566 5612
5567 5613 size(4);
5568 5614 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5569 5615 ins_encode %{
5570 5616 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5571 5617 %}
5572 5618 ins_pipe(iload_mem);
5573 5619 %}
5574 5620
5575 5621 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5576 5622 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5577 5623 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5578 5624 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5579 5625
5580 5626 size(2*4);
5581 5627 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5582 5628 "AND $dst,$mask,$dst" %}
5583 5629 ins_encode %{
5584 5630 Register Rdst = $dst$$Register;
5585 5631 __ lduh($mem$$Address, Rdst);
5586 5632 __ and3(Rdst, $mask$$constant, Rdst);
5587 5633 %}
5588 5634 ins_pipe(iload_mem);
5589 5635 %}
5590 5636
5591 5637 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5592 5638 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5593 5639 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5594 5640 effect(TEMP dst, TEMP tmp);
5595 5641 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5596 5642
5597 5643 size((3+1)*4); // set may use two instructions.
5598 5644 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5599 5645 "SET $mask,$tmp\n\t"
5600 5646 "AND $dst,$tmp,$dst" %}
5601 5647 ins_encode %{
5602 5648 Register Rdst = $dst$$Register;
5603 5649 Register Rtmp = $tmp$$Register;
5604 5650 __ lduh($mem$$Address, Rdst);
5605 5651 __ set($mask$$constant, Rtmp);
5606 5652 __ and3(Rdst, Rtmp, Rdst);
5607 5653 %}
5608 5654 ins_pipe(iload_mem);
5609 5655 %}
5610 5656
5611 5657 // Load Integer
5612 5658 instruct loadI(iRegI dst, memory mem) %{
5613 5659 match(Set dst (LoadI mem));
5614 5660 ins_cost(MEMORY_REF_COST);
5615 5661
5616 5662 size(4);
5617 5663 format %{ "LDUW $mem,$dst\t! int" %}
5618 5664 ins_encode %{
5619 5665 __ lduw($mem$$Address, $dst$$Register);
5620 5666 %}
5621 5667 ins_pipe(iload_mem);
5622 5668 %}
5623 5669
5624 5670 // Load Integer to Byte (8 bit signed)
5625 5671 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5626 5672 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5627 5673 ins_cost(MEMORY_REF_COST);
5628 5674
5629 5675 size(4);
5630 5676
5631 5677 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5632 5678 ins_encode %{
5633 5679 __ ldsb($mem$$Address, $dst$$Register, 3);
5634 5680 %}
5635 5681 ins_pipe(iload_mask_mem);
5636 5682 %}
5637 5683
5638 5684 // Load Integer to Unsigned Byte (8 bit UNsigned)
5639 5685 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5640 5686 match(Set dst (AndI (LoadI mem) mask));
5641 5687 ins_cost(MEMORY_REF_COST);
5642 5688
5643 5689 size(4);
5644 5690
5645 5691 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5646 5692 ins_encode %{
5647 5693 __ ldub($mem$$Address, $dst$$Register, 3);
5648 5694 %}
5649 5695 ins_pipe(iload_mask_mem);
5650 5696 %}
5651 5697
5652 5698 // Load Integer to Short (16 bit signed)
5653 5699 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5654 5700 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5655 5701 ins_cost(MEMORY_REF_COST);
5656 5702
5657 5703 size(4);
5658 5704
5659 5705 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5660 5706 ins_encode %{
5661 5707 __ ldsh($mem$$Address, $dst$$Register, 2);
5662 5708 %}
5663 5709 ins_pipe(iload_mask_mem);
5664 5710 %}
5665 5711
5666 5712 // Load Integer to Unsigned Short (16 bit UNsigned)
5667 5713 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5668 5714 match(Set dst (AndI (LoadI mem) mask));
5669 5715 ins_cost(MEMORY_REF_COST);
5670 5716
5671 5717 size(4);
5672 5718
5673 5719 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5674 5720 ins_encode %{
5675 5721 __ lduh($mem$$Address, $dst$$Register, 2);
5676 5722 %}
5677 5723 ins_pipe(iload_mask_mem);
5678 5724 %}
5679 5725
5680 5726 // Load Integer into a Long Register
5681 5727 instruct loadI2L(iRegL dst, memory mem) %{
5682 5728 match(Set dst (ConvI2L (LoadI mem)));
5683 5729 ins_cost(MEMORY_REF_COST);
5684 5730
5685 5731 size(4);
5686 5732 format %{ "LDSW $mem,$dst\t! int -> long" %}
5687 5733 ins_encode %{
5688 5734 __ ldsw($mem$$Address, $dst$$Register);
5689 5735 %}
5690 5736 ins_pipe(iload_mask_mem);
5691 5737 %}
5692 5738
5693 5739 // Load Integer with mask 0xFF into a Long Register
5694 5740 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5695 5741 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5696 5742 ins_cost(MEMORY_REF_COST);
5697 5743
5698 5744 size(4);
5699 5745 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5700 5746 ins_encode %{
5701 5747 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5702 5748 %}
5703 5749 ins_pipe(iload_mem);
5704 5750 %}
5705 5751
5706 5752 // Load Integer with mask 0xFFFF into a Long Register
5707 5753 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5708 5754 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5709 5755 ins_cost(MEMORY_REF_COST);
5710 5756
5711 5757 size(4);
5712 5758 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5713 5759 ins_encode %{
5714 5760 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5715 5761 %}
5716 5762 ins_pipe(iload_mem);
5717 5763 %}
5718 5764
5719 5765 // Load Integer with a 13-bit mask into a Long Register
5720 5766 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5721 5767 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5722 5768 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5723 5769
5724 5770 size(2*4);
5725 5771 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5726 5772 "AND $dst,$mask,$dst" %}
5727 5773 ins_encode %{
5728 5774 Register Rdst = $dst$$Register;
5729 5775 __ lduw($mem$$Address, Rdst);
5730 5776 __ and3(Rdst, $mask$$constant, Rdst);
5731 5777 %}
5732 5778 ins_pipe(iload_mem);
5733 5779 %}
5734 5780
5735 5781 // Load Integer with a 32-bit mask into a Long Register
5736 5782 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5737 5783 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5738 5784 effect(TEMP dst, TEMP tmp);
5739 5785 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5740 5786
5741 5787 size((3+1)*4); // set may use two instructions.
5742 5788 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5743 5789 "SET $mask,$tmp\n\t"
5744 5790 "AND $dst,$tmp,$dst" %}
5745 5791 ins_encode %{
5746 5792 Register Rdst = $dst$$Register;
5747 5793 Register Rtmp = $tmp$$Register;
5748 5794 __ lduw($mem$$Address, Rdst);
5749 5795 __ set($mask$$constant, Rtmp);
5750 5796 __ and3(Rdst, Rtmp, Rdst);
5751 5797 %}
5752 5798 ins_pipe(iload_mem);
5753 5799 %}
5754 5800
5755 5801 // Load Unsigned Integer into a Long Register
5756 5802 instruct loadUI2L(iRegL dst, memory mem) %{
5757 5803 match(Set dst (LoadUI2L mem));
5758 5804 ins_cost(MEMORY_REF_COST);
5759 5805
5760 5806 size(4);
5761 5807 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5762 5808 ins_encode %{
5763 5809 __ lduw($mem$$Address, $dst$$Register);
5764 5810 %}
5765 5811 ins_pipe(iload_mem);
5766 5812 %}
5767 5813
5768 5814 // Load Long - aligned
5769 5815 instruct loadL(iRegL dst, memory mem ) %{
5770 5816 match(Set dst (LoadL mem));
5771 5817 ins_cost(MEMORY_REF_COST);
5772 5818
5773 5819 size(4);
5774 5820 format %{ "LDX $mem,$dst\t! long" %}
5775 5821 ins_encode %{
5776 5822 __ ldx($mem$$Address, $dst$$Register);
5777 5823 %}
5778 5824 ins_pipe(iload_mem);
5779 5825 %}
5780 5826
5781 5827 // Load Long - UNaligned
5782 5828 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5783 5829 match(Set dst (LoadL_unaligned mem));
5784 5830 effect(KILL tmp);
5785 5831 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5786 5832 size(16);
5787 5833 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5788 5834 "\tLDUW $mem ,$dst\n"
5789 5835 "\tSLLX #32, $dst, $dst\n"
5790 5836 "\tOR $dst, R_O7, $dst" %}
5791 5837 opcode(Assembler::lduw_op3);
5792 5838 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5793 5839 ins_pipe(iload_mem);
5794 5840 %}
5795 5841
5796 5842 // Load Aligned Packed Byte into a Double Register
5797 5843 instruct loadA8B(regD dst, memory mem) %{
5798 5844 match(Set dst (Load8B mem));
5799 5845 ins_cost(MEMORY_REF_COST);
5800 5846 size(4);
5801 5847 format %{ "LDDF $mem,$dst\t! packed8B" %}
5802 5848 opcode(Assembler::lddf_op3);
5803 5849 ins_encode(simple_form3_mem_reg( mem, dst ) );
5804 5850 ins_pipe(floadD_mem);
5805 5851 %}
5806 5852
5807 5853 // Load Aligned Packed Char into a Double Register
5808 5854 instruct loadA4C(regD dst, memory mem) %{
5809 5855 match(Set dst (Load4C mem));
5810 5856 ins_cost(MEMORY_REF_COST);
5811 5857 size(4);
5812 5858 format %{ "LDDF $mem,$dst\t! packed4C" %}
5813 5859 opcode(Assembler::lddf_op3);
5814 5860 ins_encode(simple_form3_mem_reg( mem, dst ) );
5815 5861 ins_pipe(floadD_mem);
5816 5862 %}
5817 5863
5818 5864 // Load Aligned Packed Short into a Double Register
5819 5865 instruct loadA4S(regD dst, memory mem) %{
5820 5866 match(Set dst (Load4S mem));
5821 5867 ins_cost(MEMORY_REF_COST);
5822 5868 size(4);
5823 5869 format %{ "LDDF $mem,$dst\t! packed4S" %}
5824 5870 opcode(Assembler::lddf_op3);
5825 5871 ins_encode(simple_form3_mem_reg( mem, dst ) );
5826 5872 ins_pipe(floadD_mem);
5827 5873 %}
5828 5874
5829 5875 // Load Aligned Packed Int into a Double Register
5830 5876 instruct loadA2I(regD dst, memory mem) %{
5831 5877 match(Set dst (Load2I mem));
5832 5878 ins_cost(MEMORY_REF_COST);
5833 5879 size(4);
5834 5880 format %{ "LDDF $mem,$dst\t! packed2I" %}
5835 5881 opcode(Assembler::lddf_op3);
5836 5882 ins_encode(simple_form3_mem_reg( mem, dst ) );
5837 5883 ins_pipe(floadD_mem);
5838 5884 %}
5839 5885
5840 5886 // Load Range
5841 5887 instruct loadRange(iRegI dst, memory mem) %{
5842 5888 match(Set dst (LoadRange mem));
5843 5889 ins_cost(MEMORY_REF_COST);
5844 5890
5845 5891 size(4);
5846 5892 format %{ "LDUW $mem,$dst\t! range" %}
5847 5893 opcode(Assembler::lduw_op3);
5848 5894 ins_encode(simple_form3_mem_reg( mem, dst ) );
5849 5895 ins_pipe(iload_mem);
5850 5896 %}
5851 5897
5852 5898 // Load Integer into %f register (for fitos/fitod)
5853 5899 instruct loadI_freg(regF dst, memory mem) %{
5854 5900 match(Set dst (LoadI mem));
5855 5901 ins_cost(MEMORY_REF_COST);
5856 5902 size(4);
5857 5903
5858 5904 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5859 5905 opcode(Assembler::ldf_op3);
5860 5906 ins_encode(simple_form3_mem_reg( mem, dst ) );
5861 5907 ins_pipe(floadF_mem);
5862 5908 %}
5863 5909
5864 5910 // Load Pointer
5865 5911 instruct loadP(iRegP dst, memory mem) %{
5866 5912 match(Set dst (LoadP mem));
5867 5913 ins_cost(MEMORY_REF_COST);
5868 5914 size(4);
5869 5915
5870 5916 #ifndef _LP64
5871 5917 format %{ "LDUW $mem,$dst\t! ptr" %}
5872 5918 ins_encode %{
5873 5919 __ lduw($mem$$Address, $dst$$Register);
5874 5920 %}
5875 5921 #else
5876 5922 format %{ "LDX $mem,$dst\t! ptr" %}
5877 5923 ins_encode %{
5878 5924 __ ldx($mem$$Address, $dst$$Register);
5879 5925 %}
5880 5926 #endif
5881 5927 ins_pipe(iload_mem);
5882 5928 %}
5883 5929
5884 5930 // Load Compressed Pointer
5885 5931 instruct loadN(iRegN dst, memory mem) %{
5886 5932 match(Set dst (LoadN mem));
5887 5933 ins_cost(MEMORY_REF_COST);
5888 5934 size(4);
5889 5935
5890 5936 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5891 5937 ins_encode %{
5892 5938 __ lduw($mem$$Address, $dst$$Register);
5893 5939 %}
5894 5940 ins_pipe(iload_mem);
5895 5941 %}
5896 5942
5897 5943 // Load Klass Pointer
5898 5944 instruct loadKlass(iRegP dst, memory mem) %{
5899 5945 match(Set dst (LoadKlass mem));
5900 5946 ins_cost(MEMORY_REF_COST);
5901 5947 size(4);
5902 5948
5903 5949 #ifndef _LP64
5904 5950 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5905 5951 ins_encode %{
5906 5952 __ lduw($mem$$Address, $dst$$Register);
5907 5953 %}
5908 5954 #else
5909 5955 format %{ "LDX $mem,$dst\t! klass ptr" %}
5910 5956 ins_encode %{
5911 5957 __ ldx($mem$$Address, $dst$$Register);
5912 5958 %}
5913 5959 #endif
5914 5960 ins_pipe(iload_mem);
5915 5961 %}
5916 5962
5917 5963 // Load narrow Klass Pointer
5918 5964 instruct loadNKlass(iRegN dst, memory mem) %{
5919 5965 match(Set dst (LoadNKlass mem));
5920 5966 ins_cost(MEMORY_REF_COST);
5921 5967 size(4);
5922 5968
5923 5969 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5924 5970 ins_encode %{
5925 5971 __ lduw($mem$$Address, $dst$$Register);
5926 5972 %}
5927 5973 ins_pipe(iload_mem);
5928 5974 %}
5929 5975
5930 5976 // Load Double
5931 5977 instruct loadD(regD dst, memory mem) %{
5932 5978 match(Set dst (LoadD mem));
5933 5979 ins_cost(MEMORY_REF_COST);
5934 5980
5935 5981 size(4);
5936 5982 format %{ "LDDF $mem,$dst" %}
5937 5983 opcode(Assembler::lddf_op3);
5938 5984 ins_encode(simple_form3_mem_reg( mem, dst ) );
5939 5985 ins_pipe(floadD_mem);
5940 5986 %}
5941 5987
5942 5988 // Load Double - UNaligned
5943 5989 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5944 5990 match(Set dst (LoadD_unaligned mem));
5945 5991 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5946 5992 size(8);
5947 5993 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5948 5994 "\tLDF $mem+4,$dst.lo\t!" %}
5949 5995 opcode(Assembler::ldf_op3);
5950 5996 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5951 5997 ins_pipe(iload_mem);
5952 5998 %}
5953 5999
5954 6000 // Load Float
5955 6001 instruct loadF(regF dst, memory mem) %{
5956 6002 match(Set dst (LoadF mem));
5957 6003 ins_cost(MEMORY_REF_COST);
5958 6004
5959 6005 size(4);
5960 6006 format %{ "LDF $mem,$dst" %}
5961 6007 opcode(Assembler::ldf_op3);
5962 6008 ins_encode(simple_form3_mem_reg( mem, dst ) );
5963 6009 ins_pipe(floadF_mem);
5964 6010 %}
5965 6011
5966 6012 // Load Constant
5967 6013 instruct loadConI( iRegI dst, immI src ) %{
5968 6014 match(Set dst src);
5969 6015 ins_cost(DEFAULT_COST * 3/2);
5970 6016 format %{ "SET $src,$dst" %}
5971 6017 ins_encode( Set32(src, dst) );
5972 6018 ins_pipe(ialu_hi_lo_reg);
5973 6019 %}
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5974 6020
5975 6021 instruct loadConI13( iRegI dst, immI13 src ) %{
5976 6022 match(Set dst src);
5977 6023
5978 6024 size(4);
5979 6025 format %{ "MOV $src,$dst" %}
5980 6026 ins_encode( Set13( src, dst ) );
5981 6027 ins_pipe(ialu_imm);
5982 6028 %}
5983 6029
5984 -instruct loadConP(iRegP dst, immP src) %{
5985 - match(Set dst src);
6030 +instruct loadConP(iRegP dst, immP con) %{
6031 + match(Set dst con);
6032 +#ifndef _LP64
5986 6033 ins_cost(DEFAULT_COST * 3/2);
5987 - format %{ "SET $src,$dst\t!ptr" %}
5988 - // This rule does not use "expand" unlike loadConI because then
5989 - // the result type is not known to be an Oop. An ADLC
5990 - // enhancement will be needed to make that work - not worth it!
5991 -
5992 - ins_encode( SetPtr( src, dst ) );
6034 + format %{ "SET $con,$dst\t!ptr" %}
6035 + ins_encode %{
6036 + // [RGV] This next line should be generated from ADLC
6037 + if (_opnds[1]->constant_is_oop()) {
6038 + intptr_t val = $con$$constant;
6039 + __ set_oop_constant((jobject) val, $dst$$Register);
6040 + } else { // non-oop pointers, e.g. card mark base, heap top
6041 + __ set($con$$constant, $dst$$Register);
6042 + }
6043 + %}
6044 +#else
6045 + ins_cost(MEMORY_REF_COST);
6046 + size(4);
6047 + format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6048 + ins_encode %{
6049 + __ ld_ptr($constanttablebase, $constantoffset($con), $dst$$Register);
6050 + %}
6051 +#endif
5993 6052 ins_pipe(loadConP);
5994 -
5995 6053 %}
5996 6054
5997 6055 instruct loadConP0(iRegP dst, immP0 src) %{
5998 6056 match(Set dst src);
5999 6057
6000 6058 size(4);
6001 6059 format %{ "CLR $dst\t!ptr" %}
6002 - ins_encode( SetNull( dst ) );
6060 + ins_encode %{
6061 + __ clr($dst$$Register);
6062 + %}
6003 6063 ins_pipe(ialu_imm);
6004 6064 %}
6005 6065
6006 6066 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6007 6067 match(Set dst src);
6008 6068 ins_cost(DEFAULT_COST);
6009 6069 format %{ "SET $src,$dst\t!ptr" %}
6010 6070 ins_encode %{
6011 6071 AddressLiteral polling_page(os::get_polling_page());
6012 6072 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6013 6073 %}
6014 6074 ins_pipe(loadConP_poll);
6015 6075 %}
6016 6076
6017 6077 instruct loadConN0(iRegN dst, immN0 src) %{
6018 6078 match(Set dst src);
6019 6079
6020 6080 size(4);
6021 6081 format %{ "CLR $dst\t! compressed NULL ptr" %}
6022 - ins_encode( SetNull( dst ) );
6082 + ins_encode %{
6083 + __ clr($dst$$Register);
6084 + %}
6023 6085 ins_pipe(ialu_imm);
6024 6086 %}
6025 6087
6026 6088 instruct loadConN(iRegN dst, immN src) %{
6027 6089 match(Set dst src);
6028 6090 ins_cost(DEFAULT_COST * 3/2);
6029 6091 format %{ "SET $src,$dst\t! compressed ptr" %}
6030 6092 ins_encode %{
6031 6093 Register dst = $dst$$Register;
6032 6094 __ set_narrow_oop((jobject)$src$$constant, dst);
6033 6095 %}
6034 6096 ins_pipe(ialu_hi_lo_reg);
6035 6097 %}
6036 6098
6037 -instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6038 - // %%% maybe this should work like loadConD
6039 - match(Set dst src);
6099 +// Materialize long value (predicated by immL_cheap).
6100 +instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6101 + match(Set dst con);
6040 6102 effect(KILL tmp);
6041 - ins_cost(DEFAULT_COST * 4);
6042 - format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6043 - ins_encode( LdImmL(src, dst, tmp) );
6103 + ins_cost(DEFAULT_COST * 3);
6104 + format %{ "SET64 $con,$dst KILL $tmp\t! long" %}
6105 + ins_encode %{
6106 + __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6107 + %}
6108 + ins_pipe(loadConL);
6109 +%}
6110 +
6111 +// Load long value from constant table (predicated by immL_expensive).
6112 +instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6113 + match(Set dst con);
6114 + ins_cost(MEMORY_REF_COST);
6115 + format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6116 + ins_encode %{
6117 + __ ldx($constanttablebase, $constantoffset($con), $dst$$Register);
6118 + %}
6044 6119 ins_pipe(loadConL);
6045 6120 %}
6046 6121
6047 6122 instruct loadConL0( iRegL dst, immL0 src ) %{
6048 6123 match(Set dst src);
6049 6124 ins_cost(DEFAULT_COST);
6050 6125 size(4);
6051 6126 format %{ "CLR $dst\t! long" %}
6052 6127 ins_encode( Set13( src, dst ) );
6053 6128 ins_pipe(ialu_imm);
6054 6129 %}
6055 6130
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6056 6131 instruct loadConL13( iRegL dst, immL13 src ) %{
6057 6132 match(Set dst src);
6058 6133 ins_cost(DEFAULT_COST * 2);
6059 6134
6060 6135 size(4);
6061 6136 format %{ "MOV $src,$dst\t! long" %}
6062 6137 ins_encode( Set13( src, dst ) );
6063 6138 ins_pipe(ialu_imm);
6064 6139 %}
6065 6140
6066 -instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6067 - match(Set dst src);
6068 - effect(KILL tmp);
6069 -
6070 -#ifdef _LP64
6071 - size(8*4);
6072 -#else
6073 - size(2*4);
6074 -#endif
6075 -
6076 - format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6077 - "LDF [$tmp+lo(&$src)],$dst" %}
6141 +instruct loadConF(regF dst, immF con) %{
6142 + match(Set dst con);
6143 + size(4);
6144 + format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6078 6145 ins_encode %{
6079 - address float_address = __ float_constant($src$$constant);
6080 - RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6081 - AddressLiteral addrlit(float_address, rspec);
6082 -
6083 - __ sethi(addrlit, $tmp$$Register);
6084 - __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6146 + __ ldf(FloatRegisterImpl::S, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6085 6147 %}
6086 6148 ins_pipe(loadConFD);
6087 6149 %}
6088 6150
6089 -instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6090 - match(Set dst src);
6091 - effect(KILL tmp);
6092 -
6093 -#ifdef _LP64
6094 - size(8*4);
6095 -#else
6096 - size(2*4);
6097 -#endif
6098 -
6099 - format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6100 - "LDDF [$tmp+lo(&$src)],$dst" %}
6151 +instruct loadConD(regD dst, immD con) %{
6152 + match(Set dst con);
6153 + size(4);
6154 + format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6101 6155 ins_encode %{
6102 - address double_address = __ double_constant($src$$constant);
6103 - RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6104 - AddressLiteral addrlit(double_address, rspec);
6105 -
6106 - __ sethi(addrlit, $tmp$$Register);
6107 6156 // XXX This is a quick fix for 6833573.
6108 - //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6109 - __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6157 + //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6158 + __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), as_DoubleFloatRegister($dst$$reg));
6110 6159 %}
6111 6160 ins_pipe(loadConFD);
6112 6161 %}
6113 6162
6114 6163 // Prefetch instructions.
6115 6164 // Must be safe to execute with invalid address (cannot fault).
6116 6165
6117 6166 instruct prefetchr( memory mem ) %{
6118 6167 match( PrefetchRead mem );
6119 6168 ins_cost(MEMORY_REF_COST);
6120 6169
6121 6170 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6122 6171 opcode(Assembler::prefetch_op3);
6123 6172 ins_encode( form3_mem_prefetch_read( mem ) );
6124 6173 ins_pipe(iload_mem);
6125 6174 %}
6126 6175
6127 6176 instruct prefetchw( memory mem ) %{
6128 6177 predicate(AllocatePrefetchStyle != 3 );
6129 6178 match( PrefetchWrite mem );
6130 6179 ins_cost(MEMORY_REF_COST);
6131 6180
6132 6181 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6133 6182 opcode(Assembler::prefetch_op3);
6134 6183 ins_encode( form3_mem_prefetch_write( mem ) );
6135 6184 ins_pipe(iload_mem);
6136 6185 %}
6137 6186
6138 6187 // Use BIS instruction to prefetch.
6139 6188 instruct prefetchw_bis( memory mem ) %{
6140 6189 predicate(AllocatePrefetchStyle == 3);
6141 6190 match( PrefetchWrite mem );
6142 6191 ins_cost(MEMORY_REF_COST);
6143 6192
6144 6193 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6145 6194 ins_encode %{
6146 6195 Register base = as_Register($mem$$base);
6147 6196 int disp = $mem$$disp;
6148 6197 if (disp != 0) {
6149 6198 __ add(base, AllocatePrefetchStepSize, base);
6150 6199 }
6151 6200 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6152 6201 %}
6153 6202 ins_pipe(istore_mem_reg);
6154 6203 %}
6155 6204
6156 6205 //----------Store Instructions-------------------------------------------------
6157 6206 // Store Byte
6158 6207 instruct storeB(memory mem, iRegI src) %{
6159 6208 match(Set mem (StoreB mem src));
6160 6209 ins_cost(MEMORY_REF_COST);
6161 6210
6162 6211 size(4);
6163 6212 format %{ "STB $src,$mem\t! byte" %}
6164 6213 opcode(Assembler::stb_op3);
6165 6214 ins_encode(simple_form3_mem_reg( mem, src ) );
6166 6215 ins_pipe(istore_mem_reg);
6167 6216 %}
6168 6217
6169 6218 instruct storeB0(memory mem, immI0 src) %{
6170 6219 match(Set mem (StoreB mem src));
6171 6220 ins_cost(MEMORY_REF_COST);
6172 6221
6173 6222 size(4);
6174 6223 format %{ "STB $src,$mem\t! byte" %}
6175 6224 opcode(Assembler::stb_op3);
6176 6225 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6177 6226 ins_pipe(istore_mem_zero);
6178 6227 %}
6179 6228
6180 6229 instruct storeCM0(memory mem, immI0 src) %{
6181 6230 match(Set mem (StoreCM mem src));
6182 6231 ins_cost(MEMORY_REF_COST);
6183 6232
6184 6233 size(4);
6185 6234 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6186 6235 opcode(Assembler::stb_op3);
6187 6236 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6188 6237 ins_pipe(istore_mem_zero);
6189 6238 %}
6190 6239
6191 6240 // Store Char/Short
6192 6241 instruct storeC(memory mem, iRegI src) %{
6193 6242 match(Set mem (StoreC mem src));
6194 6243 ins_cost(MEMORY_REF_COST);
6195 6244
6196 6245 size(4);
6197 6246 format %{ "STH $src,$mem\t! short" %}
6198 6247 opcode(Assembler::sth_op3);
6199 6248 ins_encode(simple_form3_mem_reg( mem, src ) );
6200 6249 ins_pipe(istore_mem_reg);
6201 6250 %}
6202 6251
6203 6252 instruct storeC0(memory mem, immI0 src) %{
6204 6253 match(Set mem (StoreC mem src));
6205 6254 ins_cost(MEMORY_REF_COST);
6206 6255
6207 6256 size(4);
6208 6257 format %{ "STH $src,$mem\t! short" %}
6209 6258 opcode(Assembler::sth_op3);
6210 6259 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6211 6260 ins_pipe(istore_mem_zero);
6212 6261 %}
6213 6262
6214 6263 // Store Integer
6215 6264 instruct storeI(memory mem, iRegI src) %{
6216 6265 match(Set mem (StoreI mem src));
6217 6266 ins_cost(MEMORY_REF_COST);
6218 6267
6219 6268 size(4);
6220 6269 format %{ "STW $src,$mem" %}
6221 6270 opcode(Assembler::stw_op3);
6222 6271 ins_encode(simple_form3_mem_reg( mem, src ) );
6223 6272 ins_pipe(istore_mem_reg);
6224 6273 %}
6225 6274
6226 6275 // Store Long
6227 6276 instruct storeL(memory mem, iRegL src) %{
6228 6277 match(Set mem (StoreL mem src));
6229 6278 ins_cost(MEMORY_REF_COST);
6230 6279 size(4);
6231 6280 format %{ "STX $src,$mem\t! long" %}
6232 6281 opcode(Assembler::stx_op3);
6233 6282 ins_encode(simple_form3_mem_reg( mem, src ) );
6234 6283 ins_pipe(istore_mem_reg);
6235 6284 %}
6236 6285
6237 6286 instruct storeI0(memory mem, immI0 src) %{
6238 6287 match(Set mem (StoreI mem src));
6239 6288 ins_cost(MEMORY_REF_COST);
6240 6289
6241 6290 size(4);
6242 6291 format %{ "STW $src,$mem" %}
6243 6292 opcode(Assembler::stw_op3);
6244 6293 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6245 6294 ins_pipe(istore_mem_zero);
6246 6295 %}
6247 6296
6248 6297 instruct storeL0(memory mem, immL0 src) %{
6249 6298 match(Set mem (StoreL mem src));
6250 6299 ins_cost(MEMORY_REF_COST);
6251 6300
6252 6301 size(4);
6253 6302 format %{ "STX $src,$mem" %}
6254 6303 opcode(Assembler::stx_op3);
6255 6304 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6256 6305 ins_pipe(istore_mem_zero);
6257 6306 %}
6258 6307
6259 6308 // Store Integer from float register (used after fstoi)
6260 6309 instruct storeI_Freg(memory mem, regF src) %{
6261 6310 match(Set mem (StoreI mem src));
6262 6311 ins_cost(MEMORY_REF_COST);
6263 6312
6264 6313 size(4);
6265 6314 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6266 6315 opcode(Assembler::stf_op3);
6267 6316 ins_encode(simple_form3_mem_reg( mem, src ) );
6268 6317 ins_pipe(fstoreF_mem_reg);
6269 6318 %}
6270 6319
6271 6320 // Store Pointer
6272 6321 instruct storeP(memory dst, sp_ptr_RegP src) %{
6273 6322 match(Set dst (StoreP dst src));
6274 6323 ins_cost(MEMORY_REF_COST);
6275 6324 size(4);
6276 6325
6277 6326 #ifndef _LP64
6278 6327 format %{ "STW $src,$dst\t! ptr" %}
6279 6328 opcode(Assembler::stw_op3, 0, REGP_OP);
6280 6329 #else
6281 6330 format %{ "STX $src,$dst\t! ptr" %}
6282 6331 opcode(Assembler::stx_op3, 0, REGP_OP);
6283 6332 #endif
6284 6333 ins_encode( form3_mem_reg( dst, src ) );
6285 6334 ins_pipe(istore_mem_spORreg);
6286 6335 %}
6287 6336
6288 6337 instruct storeP0(memory dst, immP0 src) %{
6289 6338 match(Set dst (StoreP dst src));
6290 6339 ins_cost(MEMORY_REF_COST);
6291 6340 size(4);
6292 6341
6293 6342 #ifndef _LP64
6294 6343 format %{ "STW $src,$dst\t! ptr" %}
6295 6344 opcode(Assembler::stw_op3, 0, REGP_OP);
6296 6345 #else
6297 6346 format %{ "STX $src,$dst\t! ptr" %}
6298 6347 opcode(Assembler::stx_op3, 0, REGP_OP);
6299 6348 #endif
6300 6349 ins_encode( form3_mem_reg( dst, R_G0 ) );
6301 6350 ins_pipe(istore_mem_zero);
6302 6351 %}
6303 6352
6304 6353 // Store Compressed Pointer
6305 6354 instruct storeN(memory dst, iRegN src) %{
6306 6355 match(Set dst (StoreN dst src));
6307 6356 ins_cost(MEMORY_REF_COST);
6308 6357 size(4);
6309 6358
6310 6359 format %{ "STW $src,$dst\t! compressed ptr" %}
6311 6360 ins_encode %{
6312 6361 Register base = as_Register($dst$$base);
6313 6362 Register index = as_Register($dst$$index);
6314 6363 Register src = $src$$Register;
6315 6364 if (index != G0) {
6316 6365 __ stw(src, base, index);
6317 6366 } else {
6318 6367 __ stw(src, base, $dst$$disp);
6319 6368 }
6320 6369 %}
6321 6370 ins_pipe(istore_mem_spORreg);
6322 6371 %}
6323 6372
6324 6373 instruct storeN0(memory dst, immN0 src) %{
6325 6374 match(Set dst (StoreN dst src));
6326 6375 ins_cost(MEMORY_REF_COST);
6327 6376 size(4);
6328 6377
6329 6378 format %{ "STW $src,$dst\t! compressed ptr" %}
6330 6379 ins_encode %{
6331 6380 Register base = as_Register($dst$$base);
6332 6381 Register index = as_Register($dst$$index);
6333 6382 if (index != G0) {
6334 6383 __ stw(0, base, index);
6335 6384 } else {
6336 6385 __ stw(0, base, $dst$$disp);
6337 6386 }
6338 6387 %}
6339 6388 ins_pipe(istore_mem_zero);
6340 6389 %}
6341 6390
6342 6391 // Store Double
6343 6392 instruct storeD( memory mem, regD src) %{
6344 6393 match(Set mem (StoreD mem src));
6345 6394 ins_cost(MEMORY_REF_COST);
6346 6395
6347 6396 size(4);
6348 6397 format %{ "STDF $src,$mem" %}
6349 6398 opcode(Assembler::stdf_op3);
6350 6399 ins_encode(simple_form3_mem_reg( mem, src ) );
6351 6400 ins_pipe(fstoreD_mem_reg);
6352 6401 %}
6353 6402
6354 6403 instruct storeD0( memory mem, immD0 src) %{
6355 6404 match(Set mem (StoreD mem src));
6356 6405 ins_cost(MEMORY_REF_COST);
6357 6406
6358 6407 size(4);
6359 6408 format %{ "STX $src,$mem" %}
6360 6409 opcode(Assembler::stx_op3);
6361 6410 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6362 6411 ins_pipe(fstoreD_mem_zero);
6363 6412 %}
6364 6413
6365 6414 // Store Float
6366 6415 instruct storeF( memory mem, regF src) %{
6367 6416 match(Set mem (StoreF mem src));
6368 6417 ins_cost(MEMORY_REF_COST);
6369 6418
6370 6419 size(4);
6371 6420 format %{ "STF $src,$mem" %}
6372 6421 opcode(Assembler::stf_op3);
6373 6422 ins_encode(simple_form3_mem_reg( mem, src ) );
6374 6423 ins_pipe(fstoreF_mem_reg);
6375 6424 %}
6376 6425
6377 6426 instruct storeF0( memory mem, immF0 src) %{
6378 6427 match(Set mem (StoreF mem src));
6379 6428 ins_cost(MEMORY_REF_COST);
6380 6429
6381 6430 size(4);
6382 6431 format %{ "STW $src,$mem\t! storeF0" %}
6383 6432 opcode(Assembler::stw_op3);
6384 6433 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6385 6434 ins_pipe(fstoreF_mem_zero);
6386 6435 %}
6387 6436
6388 6437 // Store Aligned Packed Bytes in Double register to memory
6389 6438 instruct storeA8B(memory mem, regD src) %{
6390 6439 match(Set mem (Store8B mem src));
6391 6440 ins_cost(MEMORY_REF_COST);
6392 6441 size(4);
6393 6442 format %{ "STDF $src,$mem\t! packed8B" %}
6394 6443 opcode(Assembler::stdf_op3);
6395 6444 ins_encode(simple_form3_mem_reg( mem, src ) );
6396 6445 ins_pipe(fstoreD_mem_reg);
6397 6446 %}
6398 6447
6399 6448 // Convert oop pointer into compressed form
6400 6449 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6401 6450 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6402 6451 match(Set dst (EncodeP src));
6403 6452 format %{ "encode_heap_oop $src, $dst" %}
6404 6453 ins_encode %{
6405 6454 __ encode_heap_oop($src$$Register, $dst$$Register);
6406 6455 %}
6407 6456 ins_pipe(ialu_reg);
6408 6457 %}
6409 6458
6410 6459 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6411 6460 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6412 6461 match(Set dst (EncodeP src));
6413 6462 format %{ "encode_heap_oop_not_null $src, $dst" %}
6414 6463 ins_encode %{
6415 6464 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6416 6465 %}
6417 6466 ins_pipe(ialu_reg);
6418 6467 %}
6419 6468
6420 6469 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6421 6470 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6422 6471 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6423 6472 match(Set dst (DecodeN src));
6424 6473 format %{ "decode_heap_oop $src, $dst" %}
6425 6474 ins_encode %{
6426 6475 __ decode_heap_oop($src$$Register, $dst$$Register);
6427 6476 %}
6428 6477 ins_pipe(ialu_reg);
6429 6478 %}
6430 6479
6431 6480 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6432 6481 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6433 6482 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6434 6483 match(Set dst (DecodeN src));
6435 6484 format %{ "decode_heap_oop_not_null $src, $dst" %}
6436 6485 ins_encode %{
6437 6486 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6438 6487 %}
6439 6488 ins_pipe(ialu_reg);
6440 6489 %}
6441 6490
6442 6491
6443 6492 // Store Zero into Aligned Packed Bytes
6444 6493 instruct storeA8B0(memory mem, immI0 zero) %{
6445 6494 match(Set mem (Store8B mem zero));
6446 6495 ins_cost(MEMORY_REF_COST);
6447 6496 size(4);
6448 6497 format %{ "STX $zero,$mem\t! packed8B" %}
6449 6498 opcode(Assembler::stx_op3);
6450 6499 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6451 6500 ins_pipe(fstoreD_mem_zero);
6452 6501 %}
6453 6502
6454 6503 // Store Aligned Packed Chars/Shorts in Double register to memory
6455 6504 instruct storeA4C(memory mem, regD src) %{
6456 6505 match(Set mem (Store4C mem src));
6457 6506 ins_cost(MEMORY_REF_COST);
6458 6507 size(4);
6459 6508 format %{ "STDF $src,$mem\t! packed4C" %}
6460 6509 opcode(Assembler::stdf_op3);
6461 6510 ins_encode(simple_form3_mem_reg( mem, src ) );
6462 6511 ins_pipe(fstoreD_mem_reg);
6463 6512 %}
6464 6513
6465 6514 // Store Zero into Aligned Packed Chars/Shorts
6466 6515 instruct storeA4C0(memory mem, immI0 zero) %{
6467 6516 match(Set mem (Store4C mem (Replicate4C zero)));
6468 6517 ins_cost(MEMORY_REF_COST);
6469 6518 size(4);
6470 6519 format %{ "STX $zero,$mem\t! packed4C" %}
6471 6520 opcode(Assembler::stx_op3);
6472 6521 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6473 6522 ins_pipe(fstoreD_mem_zero);
6474 6523 %}
6475 6524
6476 6525 // Store Aligned Packed Ints in Double register to memory
6477 6526 instruct storeA2I(memory mem, regD src) %{
6478 6527 match(Set mem (Store2I mem src));
6479 6528 ins_cost(MEMORY_REF_COST);
6480 6529 size(4);
6481 6530 format %{ "STDF $src,$mem\t! packed2I" %}
6482 6531 opcode(Assembler::stdf_op3);
6483 6532 ins_encode(simple_form3_mem_reg( mem, src ) );
6484 6533 ins_pipe(fstoreD_mem_reg);
6485 6534 %}
6486 6535
6487 6536 // Store Zero into Aligned Packed Ints
6488 6537 instruct storeA2I0(memory mem, immI0 zero) %{
6489 6538 match(Set mem (Store2I mem zero));
6490 6539 ins_cost(MEMORY_REF_COST);
6491 6540 size(4);
6492 6541 format %{ "STX $zero,$mem\t! packed2I" %}
6493 6542 opcode(Assembler::stx_op3);
6494 6543 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6495 6544 ins_pipe(fstoreD_mem_zero);
6496 6545 %}
6497 6546
6498 6547
6499 6548 //----------MemBar Instructions-----------------------------------------------
6500 6549 // Memory barrier flavors
6501 6550
6502 6551 instruct membar_acquire() %{
6503 6552 match(MemBarAcquire);
6504 6553 ins_cost(4*MEMORY_REF_COST);
6505 6554
6506 6555 size(0);
6507 6556 format %{ "MEMBAR-acquire" %}
6508 6557 ins_encode( enc_membar_acquire );
6509 6558 ins_pipe(long_memory_op);
6510 6559 %}
6511 6560
6512 6561 instruct membar_acquire_lock() %{
6513 6562 match(MemBarAcquire);
6514 6563 predicate(Matcher::prior_fast_lock(n));
6515 6564 ins_cost(0);
6516 6565
6517 6566 size(0);
6518 6567 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6519 6568 ins_encode( );
6520 6569 ins_pipe(empty);
6521 6570 %}
6522 6571
6523 6572 instruct membar_release() %{
6524 6573 match(MemBarRelease);
6525 6574 ins_cost(4*MEMORY_REF_COST);
6526 6575
6527 6576 size(0);
6528 6577 format %{ "MEMBAR-release" %}
6529 6578 ins_encode( enc_membar_release );
6530 6579 ins_pipe(long_memory_op);
6531 6580 %}
6532 6581
6533 6582 instruct membar_release_lock() %{
6534 6583 match(MemBarRelease);
6535 6584 predicate(Matcher::post_fast_unlock(n));
6536 6585 ins_cost(0);
6537 6586
6538 6587 size(0);
6539 6588 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6540 6589 ins_encode( );
6541 6590 ins_pipe(empty);
6542 6591 %}
6543 6592
6544 6593 instruct membar_volatile() %{
6545 6594 match(MemBarVolatile);
6546 6595 ins_cost(4*MEMORY_REF_COST);
6547 6596
6548 6597 size(4);
6549 6598 format %{ "MEMBAR-volatile" %}
6550 6599 ins_encode( enc_membar_volatile );
6551 6600 ins_pipe(long_memory_op);
6552 6601 %}
6553 6602
6554 6603 instruct unnecessary_membar_volatile() %{
6555 6604 match(MemBarVolatile);
6556 6605 predicate(Matcher::post_store_load_barrier(n));
6557 6606 ins_cost(0);
6558 6607
6559 6608 size(0);
6560 6609 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6561 6610 ins_encode( );
6562 6611 ins_pipe(empty);
6563 6612 %}
6564 6613
6565 6614 //----------Register Move Instructions-----------------------------------------
6566 6615 instruct roundDouble_nop(regD dst) %{
6567 6616 match(Set dst (RoundDouble dst));
6568 6617 ins_cost(0);
6569 6618 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6570 6619 ins_encode( );
6571 6620 ins_pipe(empty);
6572 6621 %}
6573 6622
6574 6623
6575 6624 instruct roundFloat_nop(regF dst) %{
6576 6625 match(Set dst (RoundFloat dst));
6577 6626 ins_cost(0);
6578 6627 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6579 6628 ins_encode( );
6580 6629 ins_pipe(empty);
6581 6630 %}
6582 6631
6583 6632
6584 6633 // Cast Index to Pointer for unsafe natives
6585 6634 instruct castX2P(iRegX src, iRegP dst) %{
6586 6635 match(Set dst (CastX2P src));
6587 6636
6588 6637 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6589 6638 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6590 6639 ins_pipe(ialu_reg);
6591 6640 %}
6592 6641
6593 6642 // Cast Pointer to Index for unsafe natives
6594 6643 instruct castP2X(iRegP src, iRegX dst) %{
6595 6644 match(Set dst (CastP2X src));
6596 6645
6597 6646 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6598 6647 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6599 6648 ins_pipe(ialu_reg);
6600 6649 %}
6601 6650
6602 6651 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6603 6652 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6604 6653 match(Set stkSlot src); // chain rule
6605 6654 ins_cost(MEMORY_REF_COST);
6606 6655 format %{ "STDF $src,$stkSlot\t!stk" %}
6607 6656 opcode(Assembler::stdf_op3);
6608 6657 ins_encode(simple_form3_mem_reg(stkSlot, src));
6609 6658 ins_pipe(fstoreD_stk_reg);
6610 6659 %}
6611 6660
6612 6661 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6613 6662 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6614 6663 match(Set dst stkSlot); // chain rule
6615 6664 ins_cost(MEMORY_REF_COST);
6616 6665 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6617 6666 opcode(Assembler::lddf_op3);
6618 6667 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6619 6668 ins_pipe(floadD_stk);
6620 6669 %}
6621 6670
6622 6671 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6623 6672 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6624 6673 match(Set stkSlot src); // chain rule
6625 6674 ins_cost(MEMORY_REF_COST);
6626 6675 format %{ "STF $src,$stkSlot\t!stk" %}
6627 6676 opcode(Assembler::stf_op3);
6628 6677 ins_encode(simple_form3_mem_reg(stkSlot, src));
6629 6678 ins_pipe(fstoreF_stk_reg);
6630 6679 %}
6631 6680
6632 6681 //----------Conditional Move---------------------------------------------------
6633 6682 // Conditional move
6634 6683 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6635 6684 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6636 6685 ins_cost(150);
6637 6686 format %{ "MOV$cmp $pcc,$src,$dst" %}
6638 6687 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6639 6688 ins_pipe(ialu_reg);
6640 6689 %}
6641 6690
6642 6691 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6643 6692 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6644 6693 ins_cost(140);
6645 6694 format %{ "MOV$cmp $pcc,$src,$dst" %}
6646 6695 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6647 6696 ins_pipe(ialu_imm);
6648 6697 %}
6649 6698
6650 6699 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6651 6700 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6652 6701 ins_cost(150);
6653 6702 size(4);
6654 6703 format %{ "MOV$cmp $icc,$src,$dst" %}
6655 6704 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6656 6705 ins_pipe(ialu_reg);
6657 6706 %}
6658 6707
6659 6708 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6660 6709 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6661 6710 ins_cost(140);
6662 6711 size(4);
6663 6712 format %{ "MOV$cmp $icc,$src,$dst" %}
6664 6713 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6665 6714 ins_pipe(ialu_imm);
6666 6715 %}
6667 6716
6668 6717 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6669 6718 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6670 6719 ins_cost(150);
6671 6720 size(4);
6672 6721 format %{ "MOV$cmp $icc,$src,$dst" %}
6673 6722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6674 6723 ins_pipe(ialu_reg);
6675 6724 %}
6676 6725
6677 6726 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6678 6727 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6679 6728 ins_cost(140);
6680 6729 size(4);
6681 6730 format %{ "MOV$cmp $icc,$src,$dst" %}
6682 6731 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6683 6732 ins_pipe(ialu_imm);
6684 6733 %}
6685 6734
6686 6735 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6687 6736 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6688 6737 ins_cost(150);
6689 6738 size(4);
6690 6739 format %{ "MOV$cmp $fcc,$src,$dst" %}
6691 6740 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6692 6741 ins_pipe(ialu_reg);
6693 6742 %}
6694 6743
6695 6744 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6696 6745 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6697 6746 ins_cost(140);
6698 6747 size(4);
6699 6748 format %{ "MOV$cmp $fcc,$src,$dst" %}
6700 6749 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6701 6750 ins_pipe(ialu_imm);
6702 6751 %}
6703 6752
6704 6753 // Conditional move for RegN. Only cmov(reg,reg).
6705 6754 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6706 6755 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6707 6756 ins_cost(150);
6708 6757 format %{ "MOV$cmp $pcc,$src,$dst" %}
6709 6758 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6710 6759 ins_pipe(ialu_reg);
6711 6760 %}
6712 6761
6713 6762 // This instruction also works with CmpN so we don't need cmovNN_reg.
6714 6763 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6715 6764 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6716 6765 ins_cost(150);
6717 6766 size(4);
6718 6767 format %{ "MOV$cmp $icc,$src,$dst" %}
6719 6768 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6720 6769 ins_pipe(ialu_reg);
6721 6770 %}
6722 6771
6723 6772 // This instruction also works with CmpN so we don't need cmovNN_reg.
6724 6773 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6725 6774 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6726 6775 ins_cost(150);
6727 6776 size(4);
6728 6777 format %{ "MOV$cmp $icc,$src,$dst" %}
6729 6778 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6730 6779 ins_pipe(ialu_reg);
6731 6780 %}
6732 6781
6733 6782 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6734 6783 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6735 6784 ins_cost(150);
6736 6785 size(4);
6737 6786 format %{ "MOV$cmp $fcc,$src,$dst" %}
6738 6787 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6739 6788 ins_pipe(ialu_reg);
6740 6789 %}
6741 6790
6742 6791 // Conditional move
6743 6792 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6744 6793 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6745 6794 ins_cost(150);
6746 6795 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6747 6796 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6748 6797 ins_pipe(ialu_reg);
6749 6798 %}
6750 6799
6751 6800 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6752 6801 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6753 6802 ins_cost(140);
6754 6803 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6755 6804 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6756 6805 ins_pipe(ialu_imm);
6757 6806 %}
6758 6807
6759 6808 // This instruction also works with CmpN so we don't need cmovPN_reg.
6760 6809 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6761 6810 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6762 6811 ins_cost(150);
6763 6812
6764 6813 size(4);
6765 6814 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6766 6815 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6767 6816 ins_pipe(ialu_reg);
6768 6817 %}
6769 6818
6770 6819 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6771 6820 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6772 6821 ins_cost(150);
6773 6822
6774 6823 size(4);
6775 6824 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6776 6825 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6777 6826 ins_pipe(ialu_reg);
6778 6827 %}
6779 6828
6780 6829 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6781 6830 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6782 6831 ins_cost(140);
6783 6832
6784 6833 size(4);
6785 6834 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6786 6835 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6787 6836 ins_pipe(ialu_imm);
6788 6837 %}
6789 6838
6790 6839 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6791 6840 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6792 6841 ins_cost(140);
6793 6842
6794 6843 size(4);
6795 6844 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6796 6845 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6797 6846 ins_pipe(ialu_imm);
6798 6847 %}
6799 6848
6800 6849 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6801 6850 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6802 6851 ins_cost(150);
6803 6852 size(4);
6804 6853 format %{ "MOV$cmp $fcc,$src,$dst" %}
6805 6854 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6806 6855 ins_pipe(ialu_imm);
6807 6856 %}
6808 6857
6809 6858 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6810 6859 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6811 6860 ins_cost(140);
6812 6861 size(4);
6813 6862 format %{ "MOV$cmp $fcc,$src,$dst" %}
6814 6863 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6815 6864 ins_pipe(ialu_imm);
6816 6865 %}
6817 6866
6818 6867 // Conditional move
6819 6868 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6820 6869 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6821 6870 ins_cost(150);
6822 6871 opcode(0x101);
6823 6872 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6824 6873 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6825 6874 ins_pipe(int_conditional_float_move);
6826 6875 %}
6827 6876
6828 6877 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6829 6878 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6830 6879 ins_cost(150);
6831 6880
6832 6881 size(4);
6833 6882 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6834 6883 opcode(0x101);
6835 6884 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6836 6885 ins_pipe(int_conditional_float_move);
6837 6886 %}
6838 6887
6839 6888 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6840 6889 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6841 6890 ins_cost(150);
6842 6891
6843 6892 size(4);
6844 6893 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6845 6894 opcode(0x101);
6846 6895 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6847 6896 ins_pipe(int_conditional_float_move);
6848 6897 %}
6849 6898
6850 6899 // Conditional move,
6851 6900 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6852 6901 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6853 6902 ins_cost(150);
6854 6903 size(4);
6855 6904 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6856 6905 opcode(0x1);
6857 6906 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6858 6907 ins_pipe(int_conditional_double_move);
6859 6908 %}
6860 6909
6861 6910 // Conditional move
6862 6911 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6863 6912 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6864 6913 ins_cost(150);
6865 6914 size(4);
6866 6915 opcode(0x102);
6867 6916 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6868 6917 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6869 6918 ins_pipe(int_conditional_double_move);
6870 6919 %}
6871 6920
6872 6921 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6873 6922 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6874 6923 ins_cost(150);
6875 6924
6876 6925 size(4);
6877 6926 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6878 6927 opcode(0x102);
6879 6928 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6880 6929 ins_pipe(int_conditional_double_move);
6881 6930 %}
6882 6931
6883 6932 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6884 6933 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6885 6934 ins_cost(150);
6886 6935
6887 6936 size(4);
6888 6937 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6889 6938 opcode(0x102);
6890 6939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6891 6940 ins_pipe(int_conditional_double_move);
6892 6941 %}
6893 6942
6894 6943 // Conditional move,
6895 6944 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6896 6945 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6897 6946 ins_cost(150);
6898 6947 size(4);
6899 6948 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6900 6949 opcode(0x2);
6901 6950 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6902 6951 ins_pipe(int_conditional_double_move);
6903 6952 %}
6904 6953
6905 6954 // Conditional move
6906 6955 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6907 6956 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6908 6957 ins_cost(150);
6909 6958 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6910 6959 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6911 6960 ins_pipe(ialu_reg);
6912 6961 %}
6913 6962
6914 6963 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6915 6964 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6916 6965 ins_cost(140);
6917 6966 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6918 6967 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6919 6968 ins_pipe(ialu_imm);
6920 6969 %}
6921 6970
6922 6971 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6923 6972 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6924 6973 ins_cost(150);
6925 6974
6926 6975 size(4);
6927 6976 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6928 6977 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6929 6978 ins_pipe(ialu_reg);
6930 6979 %}
6931 6980
6932 6981
6933 6982 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6934 6983 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6935 6984 ins_cost(150);
6936 6985
6937 6986 size(4);
6938 6987 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6939 6988 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6940 6989 ins_pipe(ialu_reg);
6941 6990 %}
6942 6991
6943 6992
6944 6993 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6945 6994 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6946 6995 ins_cost(150);
6947 6996
6948 6997 size(4);
6949 6998 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6950 6999 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6951 7000 ins_pipe(ialu_reg);
6952 7001 %}
6953 7002
6954 7003
6955 7004
6956 7005 //----------OS and Locking Instructions----------------------------------------
6957 7006
6958 7007 // This name is KNOWN by the ADLC and cannot be changed.
6959 7008 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6960 7009 // for this guy.
6961 7010 instruct tlsLoadP(g2RegP dst) %{
6962 7011 match(Set dst (ThreadLocal));
6963 7012
6964 7013 size(0);
6965 7014 ins_cost(0);
6966 7015 format %{ "# TLS is in G2" %}
6967 7016 ins_encode( /*empty encoding*/ );
6968 7017 ins_pipe(ialu_none);
6969 7018 %}
6970 7019
6971 7020 instruct checkCastPP( iRegP dst ) %{
6972 7021 match(Set dst (CheckCastPP dst));
6973 7022
6974 7023 size(0);
6975 7024 format %{ "# checkcastPP of $dst" %}
6976 7025 ins_encode( /*empty encoding*/ );
6977 7026 ins_pipe(empty);
6978 7027 %}
6979 7028
6980 7029
6981 7030 instruct castPP( iRegP dst ) %{
6982 7031 match(Set dst (CastPP dst));
6983 7032 format %{ "# castPP of $dst" %}
6984 7033 ins_encode( /*empty encoding*/ );
6985 7034 ins_pipe(empty);
6986 7035 %}
6987 7036
6988 7037 instruct castII( iRegI dst ) %{
6989 7038 match(Set dst (CastII dst));
6990 7039 format %{ "# castII of $dst" %}
6991 7040 ins_encode( /*empty encoding*/ );
6992 7041 ins_cost(0);
6993 7042 ins_pipe(empty);
6994 7043 %}
6995 7044
6996 7045 //----------Arithmetic Instructions--------------------------------------------
6997 7046 // Addition Instructions
6998 7047 // Register Addition
6999 7048 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7000 7049 match(Set dst (AddI src1 src2));
7001 7050
7002 7051 size(4);
7003 7052 format %{ "ADD $src1,$src2,$dst" %}
7004 7053 ins_encode %{
7005 7054 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7006 7055 %}
7007 7056 ins_pipe(ialu_reg_reg);
7008 7057 %}
7009 7058
7010 7059 // Immediate Addition
7011 7060 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7012 7061 match(Set dst (AddI src1 src2));
7013 7062
7014 7063 size(4);
7015 7064 format %{ "ADD $src1,$src2,$dst" %}
7016 7065 opcode(Assembler::add_op3, Assembler::arith_op);
7017 7066 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7018 7067 ins_pipe(ialu_reg_imm);
7019 7068 %}
7020 7069
7021 7070 // Pointer Register Addition
7022 7071 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7023 7072 match(Set dst (AddP src1 src2));
7024 7073
7025 7074 size(4);
7026 7075 format %{ "ADD $src1,$src2,$dst" %}
7027 7076 opcode(Assembler::add_op3, Assembler::arith_op);
7028 7077 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7029 7078 ins_pipe(ialu_reg_reg);
7030 7079 %}
7031 7080
7032 7081 // Pointer Immediate Addition
7033 7082 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7034 7083 match(Set dst (AddP src1 src2));
7035 7084
7036 7085 size(4);
7037 7086 format %{ "ADD $src1,$src2,$dst" %}
7038 7087 opcode(Assembler::add_op3, Assembler::arith_op);
7039 7088 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7040 7089 ins_pipe(ialu_reg_imm);
7041 7090 %}
7042 7091
7043 7092 // Long Addition
7044 7093 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7045 7094 match(Set dst (AddL src1 src2));
7046 7095
7047 7096 size(4);
7048 7097 format %{ "ADD $src1,$src2,$dst\t! long" %}
7049 7098 opcode(Assembler::add_op3, Assembler::arith_op);
7050 7099 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7051 7100 ins_pipe(ialu_reg_reg);
7052 7101 %}
7053 7102
7054 7103 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7055 7104 match(Set dst (AddL src1 con));
7056 7105
7057 7106 size(4);
7058 7107 format %{ "ADD $src1,$con,$dst" %}
7059 7108 opcode(Assembler::add_op3, Assembler::arith_op);
7060 7109 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7061 7110 ins_pipe(ialu_reg_imm);
7062 7111 %}
7063 7112
7064 7113 //----------Conditional_store--------------------------------------------------
7065 7114 // Conditional-store of the updated heap-top.
7066 7115 // Used during allocation of the shared heap.
7067 7116 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7068 7117
7069 7118 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7070 7119 instruct loadPLocked(iRegP dst, memory mem) %{
7071 7120 match(Set dst (LoadPLocked mem));
7072 7121 ins_cost(MEMORY_REF_COST);
7073 7122
7074 7123 #ifndef _LP64
7075 7124 size(4);
7076 7125 format %{ "LDUW $mem,$dst\t! ptr" %}
7077 7126 opcode(Assembler::lduw_op3, 0, REGP_OP);
7078 7127 #else
7079 7128 format %{ "LDX $mem,$dst\t! ptr" %}
7080 7129 opcode(Assembler::ldx_op3, 0, REGP_OP);
7081 7130 #endif
7082 7131 ins_encode( form3_mem_reg( mem, dst ) );
7083 7132 ins_pipe(iload_mem);
7084 7133 %}
7085 7134
7086 7135 // LoadL-locked. Same as a regular long load when used with a compare-swap
7087 7136 instruct loadLLocked(iRegL dst, memory mem) %{
7088 7137 match(Set dst (LoadLLocked mem));
7089 7138 ins_cost(MEMORY_REF_COST);
7090 7139 size(4);
7091 7140 format %{ "LDX $mem,$dst\t! long" %}
7092 7141 opcode(Assembler::ldx_op3);
7093 7142 ins_encode(simple_form3_mem_reg( mem, dst ) );
7094 7143 ins_pipe(iload_mem);
7095 7144 %}
7096 7145
7097 7146 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7098 7147 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7099 7148 effect( KILL newval );
7100 7149 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7101 7150 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7102 7151 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7103 7152 ins_pipe( long_memory_op );
7104 7153 %}
7105 7154
7106 7155 // Conditional-store of an int value.
7107 7156 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7108 7157 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7109 7158 effect( KILL newval );
7110 7159 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7111 7160 "CMP $oldval,$newval\t\t! See if we made progress" %}
7112 7161 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7113 7162 ins_pipe( long_memory_op );
7114 7163 %}
7115 7164
7116 7165 // Conditional-store of a long value.
7117 7166 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7118 7167 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7119 7168 effect( KILL newval );
7120 7169 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7121 7170 "CMP $oldval,$newval\t\t! See if we made progress" %}
7122 7171 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7123 7172 ins_pipe( long_memory_op );
7124 7173 %}
7125 7174
7126 7175 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7127 7176
7128 7177 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7129 7178 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7130 7179 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7131 7180 format %{
7132 7181 "MOV $newval,O7\n\t"
7133 7182 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7134 7183 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7135 7184 "MOV 1,$res\n\t"
7136 7185 "MOVne xcc,R_G0,$res"
7137 7186 %}
7138 7187 ins_encode( enc_casx(mem_ptr, oldval, newval),
7139 7188 enc_lflags_ne_to_boolean(res) );
7140 7189 ins_pipe( long_memory_op );
7141 7190 %}
7142 7191
7143 7192
7144 7193 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7145 7194 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7146 7195 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7147 7196 format %{
7148 7197 "MOV $newval,O7\n\t"
7149 7198 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7150 7199 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7151 7200 "MOV 1,$res\n\t"
7152 7201 "MOVne icc,R_G0,$res"
7153 7202 %}
7154 7203 ins_encode( enc_casi(mem_ptr, oldval, newval),
7155 7204 enc_iflags_ne_to_boolean(res) );
7156 7205 ins_pipe( long_memory_op );
7157 7206 %}
7158 7207
7159 7208 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7160 7209 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7161 7210 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7162 7211 format %{
7163 7212 "MOV $newval,O7\n\t"
7164 7213 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7165 7214 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7166 7215 "MOV 1,$res\n\t"
7167 7216 "MOVne xcc,R_G0,$res"
7168 7217 %}
7169 7218 #ifdef _LP64
7170 7219 ins_encode( enc_casx(mem_ptr, oldval, newval),
7171 7220 enc_lflags_ne_to_boolean(res) );
7172 7221 #else
7173 7222 ins_encode( enc_casi(mem_ptr, oldval, newval),
7174 7223 enc_iflags_ne_to_boolean(res) );
7175 7224 #endif
7176 7225 ins_pipe( long_memory_op );
7177 7226 %}
7178 7227
7179 7228 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7180 7229 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7181 7230 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7182 7231 format %{
7183 7232 "MOV $newval,O7\n\t"
7184 7233 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7185 7234 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7186 7235 "MOV 1,$res\n\t"
7187 7236 "MOVne icc,R_G0,$res"
7188 7237 %}
7189 7238 ins_encode( enc_casi(mem_ptr, oldval, newval),
7190 7239 enc_iflags_ne_to_boolean(res) );
7191 7240 ins_pipe( long_memory_op );
7192 7241 %}
7193 7242
7194 7243 //---------------------
7195 7244 // Subtraction Instructions
7196 7245 // Register Subtraction
7197 7246 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7198 7247 match(Set dst (SubI src1 src2));
7199 7248
7200 7249 size(4);
7201 7250 format %{ "SUB $src1,$src2,$dst" %}
7202 7251 opcode(Assembler::sub_op3, Assembler::arith_op);
7203 7252 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7204 7253 ins_pipe(ialu_reg_reg);
7205 7254 %}
7206 7255
7207 7256 // Immediate Subtraction
7208 7257 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7209 7258 match(Set dst (SubI src1 src2));
7210 7259
7211 7260 size(4);
7212 7261 format %{ "SUB $src1,$src2,$dst" %}
7213 7262 opcode(Assembler::sub_op3, Assembler::arith_op);
7214 7263 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7215 7264 ins_pipe(ialu_reg_imm);
7216 7265 %}
7217 7266
7218 7267 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7219 7268 match(Set dst (SubI zero src2));
7220 7269
7221 7270 size(4);
7222 7271 format %{ "NEG $src2,$dst" %}
7223 7272 opcode(Assembler::sub_op3, Assembler::arith_op);
7224 7273 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7225 7274 ins_pipe(ialu_zero_reg);
7226 7275 %}
7227 7276
7228 7277 // Long subtraction
7229 7278 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7230 7279 match(Set dst (SubL src1 src2));
7231 7280
7232 7281 size(4);
7233 7282 format %{ "SUB $src1,$src2,$dst\t! long" %}
7234 7283 opcode(Assembler::sub_op3, Assembler::arith_op);
7235 7284 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7236 7285 ins_pipe(ialu_reg_reg);
7237 7286 %}
7238 7287
7239 7288 // Immediate Subtraction
7240 7289 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7241 7290 match(Set dst (SubL src1 con));
7242 7291
7243 7292 size(4);
7244 7293 format %{ "SUB $src1,$con,$dst\t! long" %}
7245 7294 opcode(Assembler::sub_op3, Assembler::arith_op);
7246 7295 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7247 7296 ins_pipe(ialu_reg_imm);
7248 7297 %}
7249 7298
7250 7299 // Long negation
7251 7300 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7252 7301 match(Set dst (SubL zero src2));
7253 7302
7254 7303 size(4);
7255 7304 format %{ "NEG $src2,$dst\t! long" %}
7256 7305 opcode(Assembler::sub_op3, Assembler::arith_op);
7257 7306 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7258 7307 ins_pipe(ialu_zero_reg);
7259 7308 %}
7260 7309
7261 7310 // Multiplication Instructions
7262 7311 // Integer Multiplication
7263 7312 // Register Multiplication
7264 7313 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7265 7314 match(Set dst (MulI src1 src2));
7266 7315
7267 7316 size(4);
7268 7317 format %{ "MULX $src1,$src2,$dst" %}
7269 7318 opcode(Assembler::mulx_op3, Assembler::arith_op);
7270 7319 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7271 7320 ins_pipe(imul_reg_reg);
7272 7321 %}
7273 7322
7274 7323 // Immediate Multiplication
7275 7324 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7276 7325 match(Set dst (MulI src1 src2));
7277 7326
7278 7327 size(4);
7279 7328 format %{ "MULX $src1,$src2,$dst" %}
7280 7329 opcode(Assembler::mulx_op3, Assembler::arith_op);
7281 7330 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7282 7331 ins_pipe(imul_reg_imm);
7283 7332 %}
7284 7333
7285 7334 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7286 7335 match(Set dst (MulL src1 src2));
7287 7336 ins_cost(DEFAULT_COST * 5);
7288 7337 size(4);
7289 7338 format %{ "MULX $src1,$src2,$dst\t! long" %}
7290 7339 opcode(Assembler::mulx_op3, Assembler::arith_op);
7291 7340 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7292 7341 ins_pipe(mulL_reg_reg);
7293 7342 %}
7294 7343
7295 7344 // Immediate Multiplication
7296 7345 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7297 7346 match(Set dst (MulL src1 src2));
7298 7347 ins_cost(DEFAULT_COST * 5);
7299 7348 size(4);
7300 7349 format %{ "MULX $src1,$src2,$dst" %}
7301 7350 opcode(Assembler::mulx_op3, Assembler::arith_op);
7302 7351 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7303 7352 ins_pipe(mulL_reg_imm);
7304 7353 %}
7305 7354
7306 7355 // Integer Division
7307 7356 // Register Division
7308 7357 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7309 7358 match(Set dst (DivI src1 src2));
7310 7359 ins_cost((2+71)*DEFAULT_COST);
7311 7360
7312 7361 format %{ "SRA $src2,0,$src2\n\t"
7313 7362 "SRA $src1,0,$src1\n\t"
7314 7363 "SDIVX $src1,$src2,$dst" %}
7315 7364 ins_encode( idiv_reg( src1, src2, dst ) );
7316 7365 ins_pipe(sdiv_reg_reg);
7317 7366 %}
7318 7367
7319 7368 // Immediate Division
7320 7369 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7321 7370 match(Set dst (DivI src1 src2));
7322 7371 ins_cost((2+71)*DEFAULT_COST);
7323 7372
7324 7373 format %{ "SRA $src1,0,$src1\n\t"
7325 7374 "SDIVX $src1,$src2,$dst" %}
7326 7375 ins_encode( idiv_imm( src1, src2, dst ) );
7327 7376 ins_pipe(sdiv_reg_imm);
7328 7377 %}
7329 7378
7330 7379 //----------Div-By-10-Expansion------------------------------------------------
7331 7380 // Extract hi bits of a 32x32->64 bit multiply.
7332 7381 // Expand rule only, not matched
7333 7382 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7334 7383 effect( DEF dst, USE src1, USE src2 );
7335 7384 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7336 7385 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7337 7386 ins_encode( enc_mul_hi(dst,src1,src2));
7338 7387 ins_pipe(sdiv_reg_reg);
7339 7388 %}
7340 7389
7341 7390 // Magic constant, reciprocal of 10
7342 7391 instruct loadConI_x66666667(iRegIsafe dst) %{
7343 7392 effect( DEF dst );
7344 7393
7345 7394 size(8);
7346 7395 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7347 7396 ins_encode( Set32(0x66666667, dst) );
7348 7397 ins_pipe(ialu_hi_lo_reg);
7349 7398 %}
7350 7399
7351 7400 // Register Shift Right Arithmetic Long by 32-63
7352 7401 instruct sra_31( iRegI dst, iRegI src ) %{
7353 7402 effect( DEF dst, USE src );
7354 7403 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7355 7404 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7356 7405 ins_pipe(ialu_reg_reg);
7357 7406 %}
7358 7407
7359 7408 // Arithmetic Shift Right by 8-bit immediate
7360 7409 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7361 7410 effect( DEF dst, USE src );
7362 7411 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7363 7412 opcode(Assembler::sra_op3, Assembler::arith_op);
7364 7413 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7365 7414 ins_pipe(ialu_reg_imm);
7366 7415 %}
7367 7416
7368 7417 // Integer DIV with 10
7369 7418 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7370 7419 match(Set dst (DivI src div));
7371 7420 ins_cost((6+6)*DEFAULT_COST);
7372 7421 expand %{
7373 7422 iRegIsafe tmp1; // Killed temps;
7374 7423 iRegIsafe tmp2; // Killed temps;
7375 7424 iRegI tmp3; // Killed temps;
7376 7425 iRegI tmp4; // Killed temps;
7377 7426 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7378 7427 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7379 7428 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7380 7429 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7381 7430 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7382 7431 %}
7383 7432 %}
7384 7433
7385 7434 // Register Long Division
7386 7435 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7387 7436 match(Set dst (DivL src1 src2));
7388 7437 ins_cost(DEFAULT_COST*71);
7389 7438 size(4);
7390 7439 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7391 7440 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7392 7441 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7393 7442 ins_pipe(divL_reg_reg);
7394 7443 %}
7395 7444
7396 7445 // Register Long Division
7397 7446 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7398 7447 match(Set dst (DivL src1 src2));
7399 7448 ins_cost(DEFAULT_COST*71);
7400 7449 size(4);
7401 7450 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7402 7451 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7403 7452 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7404 7453 ins_pipe(divL_reg_imm);
7405 7454 %}
7406 7455
7407 7456 // Integer Remainder
7408 7457 // Register Remainder
7409 7458 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7410 7459 match(Set dst (ModI src1 src2));
7411 7460 effect( KILL ccr, KILL temp);
7412 7461
7413 7462 format %{ "SREM $src1,$src2,$dst" %}
7414 7463 ins_encode( irem_reg(src1, src2, dst, temp) );
7415 7464 ins_pipe(sdiv_reg_reg);
7416 7465 %}
7417 7466
7418 7467 // Immediate Remainder
7419 7468 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7420 7469 match(Set dst (ModI src1 src2));
7421 7470 effect( KILL ccr, KILL temp);
7422 7471
7423 7472 format %{ "SREM $src1,$src2,$dst" %}
7424 7473 ins_encode( irem_imm(src1, src2, dst, temp) );
7425 7474 ins_pipe(sdiv_reg_imm);
7426 7475 %}
7427 7476
7428 7477 // Register Long Remainder
7429 7478 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7430 7479 effect(DEF dst, USE src1, USE src2);
7431 7480 size(4);
7432 7481 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7433 7482 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7434 7483 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7435 7484 ins_pipe(divL_reg_reg);
7436 7485 %}
7437 7486
7438 7487 // Register Long Division
7439 7488 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7440 7489 effect(DEF dst, USE src1, USE src2);
7441 7490 size(4);
7442 7491 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7443 7492 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7444 7493 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7445 7494 ins_pipe(divL_reg_imm);
7446 7495 %}
7447 7496
7448 7497 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7449 7498 effect(DEF dst, USE src1, USE src2);
7450 7499 size(4);
7451 7500 format %{ "MULX $src1,$src2,$dst\t! long" %}
7452 7501 opcode(Assembler::mulx_op3, Assembler::arith_op);
7453 7502 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7454 7503 ins_pipe(mulL_reg_reg);
7455 7504 %}
7456 7505
7457 7506 // Immediate Multiplication
7458 7507 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7459 7508 effect(DEF dst, USE src1, USE src2);
7460 7509 size(4);
7461 7510 format %{ "MULX $src1,$src2,$dst" %}
7462 7511 opcode(Assembler::mulx_op3, Assembler::arith_op);
7463 7512 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7464 7513 ins_pipe(mulL_reg_imm);
7465 7514 %}
7466 7515
7467 7516 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7468 7517 effect(DEF dst, USE src1, USE src2);
7469 7518 size(4);
7470 7519 format %{ "SUB $src1,$src2,$dst\t! long" %}
7471 7520 opcode(Assembler::sub_op3, Assembler::arith_op);
7472 7521 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7473 7522 ins_pipe(ialu_reg_reg);
7474 7523 %}
7475 7524
7476 7525 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7477 7526 effect(DEF dst, USE src1, USE src2);
7478 7527 size(4);
7479 7528 format %{ "SUB $src1,$src2,$dst\t! long" %}
7480 7529 opcode(Assembler::sub_op3, Assembler::arith_op);
7481 7530 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7482 7531 ins_pipe(ialu_reg_reg);
7483 7532 %}
7484 7533
7485 7534 // Register Long Remainder
7486 7535 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7487 7536 match(Set dst (ModL src1 src2));
7488 7537 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7489 7538 expand %{
7490 7539 iRegL tmp1;
7491 7540 iRegL tmp2;
7492 7541 divL_reg_reg_1(tmp1, src1, src2);
7493 7542 mulL_reg_reg_1(tmp2, tmp1, src2);
7494 7543 subL_reg_reg_1(dst, src1, tmp2);
7495 7544 %}
7496 7545 %}
7497 7546
7498 7547 // Register Long Remainder
7499 7548 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7500 7549 match(Set dst (ModL src1 src2));
7501 7550 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7502 7551 expand %{
7503 7552 iRegL tmp1;
7504 7553 iRegL tmp2;
7505 7554 divL_reg_imm13_1(tmp1, src1, src2);
7506 7555 mulL_reg_imm13_1(tmp2, tmp1, src2);
7507 7556 subL_reg_reg_2 (dst, src1, tmp2);
7508 7557 %}
7509 7558 %}
7510 7559
7511 7560 // Integer Shift Instructions
7512 7561 // Register Shift Left
7513 7562 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7514 7563 match(Set dst (LShiftI src1 src2));
7515 7564
7516 7565 size(4);
7517 7566 format %{ "SLL $src1,$src2,$dst" %}
7518 7567 opcode(Assembler::sll_op3, Assembler::arith_op);
7519 7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7520 7569 ins_pipe(ialu_reg_reg);
7521 7570 %}
7522 7571
7523 7572 // Register Shift Left Immediate
7524 7573 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7525 7574 match(Set dst (LShiftI src1 src2));
7526 7575
7527 7576 size(4);
7528 7577 format %{ "SLL $src1,$src2,$dst" %}
7529 7578 opcode(Assembler::sll_op3, Assembler::arith_op);
7530 7579 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7531 7580 ins_pipe(ialu_reg_imm);
7532 7581 %}
7533 7582
7534 7583 // Register Shift Left
7535 7584 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7536 7585 match(Set dst (LShiftL src1 src2));
7537 7586
7538 7587 size(4);
7539 7588 format %{ "SLLX $src1,$src2,$dst" %}
7540 7589 opcode(Assembler::sllx_op3, Assembler::arith_op);
7541 7590 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7542 7591 ins_pipe(ialu_reg_reg);
7543 7592 %}
7544 7593
7545 7594 // Register Shift Left Immediate
7546 7595 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7547 7596 match(Set dst (LShiftL src1 src2));
7548 7597
7549 7598 size(4);
7550 7599 format %{ "SLLX $src1,$src2,$dst" %}
7551 7600 opcode(Assembler::sllx_op3, Assembler::arith_op);
7552 7601 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7553 7602 ins_pipe(ialu_reg_imm);
7554 7603 %}
7555 7604
7556 7605 // Register Arithmetic Shift Right
7557 7606 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7558 7607 match(Set dst (RShiftI src1 src2));
7559 7608 size(4);
7560 7609 format %{ "SRA $src1,$src2,$dst" %}
7561 7610 opcode(Assembler::sra_op3, Assembler::arith_op);
7562 7611 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7563 7612 ins_pipe(ialu_reg_reg);
7564 7613 %}
7565 7614
7566 7615 // Register Arithmetic Shift Right Immediate
7567 7616 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7568 7617 match(Set dst (RShiftI src1 src2));
7569 7618
7570 7619 size(4);
7571 7620 format %{ "SRA $src1,$src2,$dst" %}
7572 7621 opcode(Assembler::sra_op3, Assembler::arith_op);
7573 7622 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7574 7623 ins_pipe(ialu_reg_imm);
7575 7624 %}
7576 7625
7577 7626 // Register Shift Right Arithmatic Long
7578 7627 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7579 7628 match(Set dst (RShiftL src1 src2));
7580 7629
7581 7630 size(4);
7582 7631 format %{ "SRAX $src1,$src2,$dst" %}
7583 7632 opcode(Assembler::srax_op3, Assembler::arith_op);
7584 7633 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7585 7634 ins_pipe(ialu_reg_reg);
7586 7635 %}
7587 7636
7588 7637 // Register Shift Left Immediate
7589 7638 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7590 7639 match(Set dst (RShiftL src1 src2));
7591 7640
7592 7641 size(4);
7593 7642 format %{ "SRAX $src1,$src2,$dst" %}
7594 7643 opcode(Assembler::srax_op3, Assembler::arith_op);
7595 7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7596 7645 ins_pipe(ialu_reg_imm);
7597 7646 %}
7598 7647
7599 7648 // Register Shift Right
7600 7649 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7601 7650 match(Set dst (URShiftI src1 src2));
7602 7651
7603 7652 size(4);
7604 7653 format %{ "SRL $src1,$src2,$dst" %}
7605 7654 opcode(Assembler::srl_op3, Assembler::arith_op);
7606 7655 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7607 7656 ins_pipe(ialu_reg_reg);
7608 7657 %}
7609 7658
7610 7659 // Register Shift Right Immediate
7611 7660 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7612 7661 match(Set dst (URShiftI src1 src2));
7613 7662
7614 7663 size(4);
7615 7664 format %{ "SRL $src1,$src2,$dst" %}
7616 7665 opcode(Assembler::srl_op3, Assembler::arith_op);
7617 7666 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7618 7667 ins_pipe(ialu_reg_imm);
7619 7668 %}
7620 7669
7621 7670 // Register Shift Right
7622 7671 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7623 7672 match(Set dst (URShiftL src1 src2));
7624 7673
7625 7674 size(4);
7626 7675 format %{ "SRLX $src1,$src2,$dst" %}
7627 7676 opcode(Assembler::srlx_op3, Assembler::arith_op);
7628 7677 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7629 7678 ins_pipe(ialu_reg_reg);
7630 7679 %}
7631 7680
7632 7681 // Register Shift Right Immediate
7633 7682 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7634 7683 match(Set dst (URShiftL src1 src2));
7635 7684
7636 7685 size(4);
7637 7686 format %{ "SRLX $src1,$src2,$dst" %}
7638 7687 opcode(Assembler::srlx_op3, Assembler::arith_op);
7639 7688 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7640 7689 ins_pipe(ialu_reg_imm);
7641 7690 %}
7642 7691
7643 7692 // Register Shift Right Immediate with a CastP2X
7644 7693 #ifdef _LP64
7645 7694 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7646 7695 match(Set dst (URShiftL (CastP2X src1) src2));
7647 7696 size(4);
7648 7697 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7649 7698 opcode(Assembler::srlx_op3, Assembler::arith_op);
7650 7699 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7651 7700 ins_pipe(ialu_reg_imm);
7652 7701 %}
7653 7702 #else
7654 7703 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7655 7704 match(Set dst (URShiftI (CastP2X src1) src2));
7656 7705 size(4);
7657 7706 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7658 7707 opcode(Assembler::srl_op3, Assembler::arith_op);
7659 7708 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7660 7709 ins_pipe(ialu_reg_imm);
7661 7710 %}
7662 7711 #endif
7663 7712
7664 7713
7665 7714 //----------Floating Point Arithmetic Instructions-----------------------------
7666 7715
7667 7716 // Add float single precision
7668 7717 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7669 7718 match(Set dst (AddF src1 src2));
7670 7719
7671 7720 size(4);
7672 7721 format %{ "FADDS $src1,$src2,$dst" %}
7673 7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7674 7723 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7675 7724 ins_pipe(faddF_reg_reg);
7676 7725 %}
7677 7726
7678 7727 // Add float double precision
7679 7728 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7680 7729 match(Set dst (AddD src1 src2));
7681 7730
7682 7731 size(4);
7683 7732 format %{ "FADDD $src1,$src2,$dst" %}
7684 7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7685 7734 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7686 7735 ins_pipe(faddD_reg_reg);
7687 7736 %}
7688 7737
7689 7738 // Sub float single precision
7690 7739 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7691 7740 match(Set dst (SubF src1 src2));
7692 7741
7693 7742 size(4);
7694 7743 format %{ "FSUBS $src1,$src2,$dst" %}
7695 7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7696 7745 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7697 7746 ins_pipe(faddF_reg_reg);
7698 7747 %}
7699 7748
7700 7749 // Sub float double precision
7701 7750 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7702 7751 match(Set dst (SubD src1 src2));
7703 7752
7704 7753 size(4);
7705 7754 format %{ "FSUBD $src1,$src2,$dst" %}
7706 7755 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7707 7756 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7708 7757 ins_pipe(faddD_reg_reg);
7709 7758 %}
7710 7759
7711 7760 // Mul float single precision
7712 7761 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7713 7762 match(Set dst (MulF src1 src2));
7714 7763
7715 7764 size(4);
7716 7765 format %{ "FMULS $src1,$src2,$dst" %}
7717 7766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7718 7767 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7719 7768 ins_pipe(fmulF_reg_reg);
7720 7769 %}
7721 7770
7722 7771 // Mul float double precision
7723 7772 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7724 7773 match(Set dst (MulD src1 src2));
7725 7774
7726 7775 size(4);
7727 7776 format %{ "FMULD $src1,$src2,$dst" %}
7728 7777 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7729 7778 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7730 7779 ins_pipe(fmulD_reg_reg);
7731 7780 %}
7732 7781
7733 7782 // Div float single precision
7734 7783 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7735 7784 match(Set dst (DivF src1 src2));
7736 7785
7737 7786 size(4);
7738 7787 format %{ "FDIVS $src1,$src2,$dst" %}
7739 7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7740 7789 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7741 7790 ins_pipe(fdivF_reg_reg);
7742 7791 %}
7743 7792
7744 7793 // Div float double precision
7745 7794 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7746 7795 match(Set dst (DivD src1 src2));
7747 7796
7748 7797 size(4);
7749 7798 format %{ "FDIVD $src1,$src2,$dst" %}
7750 7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7751 7800 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7752 7801 ins_pipe(fdivD_reg_reg);
7753 7802 %}
7754 7803
7755 7804 // Absolute float double precision
7756 7805 instruct absD_reg(regD dst, regD src) %{
7757 7806 match(Set dst (AbsD src));
7758 7807
7759 7808 format %{ "FABSd $src,$dst" %}
7760 7809 ins_encode(fabsd(dst, src));
7761 7810 ins_pipe(faddD_reg);
7762 7811 %}
7763 7812
7764 7813 // Absolute float single precision
7765 7814 instruct absF_reg(regF dst, regF src) %{
7766 7815 match(Set dst (AbsF src));
7767 7816
7768 7817 format %{ "FABSs $src,$dst" %}
7769 7818 ins_encode(fabss(dst, src));
7770 7819 ins_pipe(faddF_reg);
7771 7820 %}
7772 7821
7773 7822 instruct negF_reg(regF dst, regF src) %{
7774 7823 match(Set dst (NegF src));
7775 7824
7776 7825 size(4);
7777 7826 format %{ "FNEGs $src,$dst" %}
7778 7827 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7779 7828 ins_encode(form3_opf_rs2F_rdF(src, dst));
7780 7829 ins_pipe(faddF_reg);
7781 7830 %}
7782 7831
7783 7832 instruct negD_reg(regD dst, regD src) %{
7784 7833 match(Set dst (NegD src));
7785 7834
7786 7835 format %{ "FNEGd $src,$dst" %}
7787 7836 ins_encode(fnegd(dst, src));
7788 7837 ins_pipe(faddD_reg);
7789 7838 %}
7790 7839
7791 7840 // Sqrt float double precision
7792 7841 instruct sqrtF_reg_reg(regF dst, regF src) %{
7793 7842 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7794 7843
7795 7844 size(4);
7796 7845 format %{ "FSQRTS $src,$dst" %}
7797 7846 ins_encode(fsqrts(dst, src));
7798 7847 ins_pipe(fdivF_reg_reg);
7799 7848 %}
7800 7849
7801 7850 // Sqrt float double precision
7802 7851 instruct sqrtD_reg_reg(regD dst, regD src) %{
7803 7852 match(Set dst (SqrtD src));
7804 7853
7805 7854 size(4);
7806 7855 format %{ "FSQRTD $src,$dst" %}
7807 7856 ins_encode(fsqrtd(dst, src));
7808 7857 ins_pipe(fdivD_reg_reg);
7809 7858 %}
7810 7859
7811 7860 //----------Logical Instructions-----------------------------------------------
7812 7861 // And Instructions
7813 7862 // Register And
7814 7863 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7815 7864 match(Set dst (AndI src1 src2));
7816 7865
7817 7866 size(4);
7818 7867 format %{ "AND $src1,$src2,$dst" %}
7819 7868 opcode(Assembler::and_op3, Assembler::arith_op);
7820 7869 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7821 7870 ins_pipe(ialu_reg_reg);
7822 7871 %}
7823 7872
7824 7873 // Immediate And
7825 7874 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7826 7875 match(Set dst (AndI src1 src2));
7827 7876
7828 7877 size(4);
7829 7878 format %{ "AND $src1,$src2,$dst" %}
7830 7879 opcode(Assembler::and_op3, Assembler::arith_op);
7831 7880 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7832 7881 ins_pipe(ialu_reg_imm);
7833 7882 %}
7834 7883
7835 7884 // Register And Long
7836 7885 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7837 7886 match(Set dst (AndL src1 src2));
7838 7887
7839 7888 ins_cost(DEFAULT_COST);
7840 7889 size(4);
7841 7890 format %{ "AND $src1,$src2,$dst\t! long" %}
7842 7891 opcode(Assembler::and_op3, Assembler::arith_op);
7843 7892 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7844 7893 ins_pipe(ialu_reg_reg);
7845 7894 %}
7846 7895
7847 7896 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7848 7897 match(Set dst (AndL src1 con));
7849 7898
7850 7899 ins_cost(DEFAULT_COST);
7851 7900 size(4);
7852 7901 format %{ "AND $src1,$con,$dst\t! long" %}
7853 7902 opcode(Assembler::and_op3, Assembler::arith_op);
7854 7903 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7855 7904 ins_pipe(ialu_reg_imm);
7856 7905 %}
7857 7906
7858 7907 // Or Instructions
7859 7908 // Register Or
7860 7909 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7861 7910 match(Set dst (OrI src1 src2));
7862 7911
7863 7912 size(4);
7864 7913 format %{ "OR $src1,$src2,$dst" %}
7865 7914 opcode(Assembler::or_op3, Assembler::arith_op);
7866 7915 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7867 7916 ins_pipe(ialu_reg_reg);
7868 7917 %}
7869 7918
7870 7919 // Immediate Or
7871 7920 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7872 7921 match(Set dst (OrI src1 src2));
7873 7922
7874 7923 size(4);
7875 7924 format %{ "OR $src1,$src2,$dst" %}
7876 7925 opcode(Assembler::or_op3, Assembler::arith_op);
7877 7926 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7878 7927 ins_pipe(ialu_reg_imm);
7879 7928 %}
7880 7929
7881 7930 // Register Or Long
7882 7931 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7883 7932 match(Set dst (OrL src1 src2));
7884 7933
7885 7934 ins_cost(DEFAULT_COST);
7886 7935 size(4);
7887 7936 format %{ "OR $src1,$src2,$dst\t! long" %}
7888 7937 opcode(Assembler::or_op3, Assembler::arith_op);
7889 7938 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7890 7939 ins_pipe(ialu_reg_reg);
7891 7940 %}
7892 7941
7893 7942 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7894 7943 match(Set dst (OrL src1 con));
7895 7944 ins_cost(DEFAULT_COST*2);
7896 7945
7897 7946 ins_cost(DEFAULT_COST);
7898 7947 size(4);
7899 7948 format %{ "OR $src1,$con,$dst\t! long" %}
7900 7949 opcode(Assembler::or_op3, Assembler::arith_op);
7901 7950 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7902 7951 ins_pipe(ialu_reg_imm);
7903 7952 %}
7904 7953
7905 7954 #ifndef _LP64
7906 7955
7907 7956 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7908 7957 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7909 7958 match(Set dst (OrI src1 (CastP2X src2)));
7910 7959
7911 7960 size(4);
7912 7961 format %{ "OR $src1,$src2,$dst" %}
7913 7962 opcode(Assembler::or_op3, Assembler::arith_op);
7914 7963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7915 7964 ins_pipe(ialu_reg_reg);
7916 7965 %}
7917 7966
7918 7967 #else
7919 7968
7920 7969 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7921 7970 match(Set dst (OrL src1 (CastP2X src2)));
7922 7971
7923 7972 ins_cost(DEFAULT_COST);
7924 7973 size(4);
7925 7974 format %{ "OR $src1,$src2,$dst\t! long" %}
7926 7975 opcode(Assembler::or_op3, Assembler::arith_op);
7927 7976 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7928 7977 ins_pipe(ialu_reg_reg);
7929 7978 %}
7930 7979
7931 7980 #endif
7932 7981
7933 7982 // Xor Instructions
7934 7983 // Register Xor
7935 7984 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7936 7985 match(Set dst (XorI src1 src2));
7937 7986
7938 7987 size(4);
7939 7988 format %{ "XOR $src1,$src2,$dst" %}
7940 7989 opcode(Assembler::xor_op3, Assembler::arith_op);
7941 7990 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7942 7991 ins_pipe(ialu_reg_reg);
7943 7992 %}
7944 7993
7945 7994 // Immediate Xor
7946 7995 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7947 7996 match(Set dst (XorI src1 src2));
7948 7997
7949 7998 size(4);
7950 7999 format %{ "XOR $src1,$src2,$dst" %}
7951 8000 opcode(Assembler::xor_op3, Assembler::arith_op);
7952 8001 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7953 8002 ins_pipe(ialu_reg_imm);
7954 8003 %}
7955 8004
7956 8005 // Register Xor Long
7957 8006 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7958 8007 match(Set dst (XorL src1 src2));
7959 8008
7960 8009 ins_cost(DEFAULT_COST);
7961 8010 size(4);
7962 8011 format %{ "XOR $src1,$src2,$dst\t! long" %}
7963 8012 opcode(Assembler::xor_op3, Assembler::arith_op);
7964 8013 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7965 8014 ins_pipe(ialu_reg_reg);
7966 8015 %}
7967 8016
7968 8017 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7969 8018 match(Set dst (XorL src1 con));
7970 8019
7971 8020 ins_cost(DEFAULT_COST);
7972 8021 size(4);
7973 8022 format %{ "XOR $src1,$con,$dst\t! long" %}
7974 8023 opcode(Assembler::xor_op3, Assembler::arith_op);
7975 8024 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7976 8025 ins_pipe(ialu_reg_imm);
7977 8026 %}
7978 8027
7979 8028 //----------Convert to Boolean-------------------------------------------------
7980 8029 // Nice hack for 32-bit tests but doesn't work for
7981 8030 // 64-bit pointers.
7982 8031 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7983 8032 match(Set dst (Conv2B src));
7984 8033 effect( KILL ccr );
7985 8034 ins_cost(DEFAULT_COST*2);
7986 8035 format %{ "CMP R_G0,$src\n\t"
7987 8036 "ADDX R_G0,0,$dst" %}
7988 8037 ins_encode( enc_to_bool( src, dst ) );
7989 8038 ins_pipe(ialu_reg_ialu);
7990 8039 %}
7991 8040
7992 8041 #ifndef _LP64
7993 8042 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7994 8043 match(Set dst (Conv2B src));
7995 8044 effect( KILL ccr );
7996 8045 ins_cost(DEFAULT_COST*2);
7997 8046 format %{ "CMP R_G0,$src\n\t"
7998 8047 "ADDX R_G0,0,$dst" %}
7999 8048 ins_encode( enc_to_bool( src, dst ) );
8000 8049 ins_pipe(ialu_reg_ialu);
8001 8050 %}
8002 8051 #else
8003 8052 instruct convP2B( iRegI dst, iRegP src ) %{
8004 8053 match(Set dst (Conv2B src));
8005 8054 ins_cost(DEFAULT_COST*2);
8006 8055 format %{ "MOV $src,$dst\n\t"
8007 8056 "MOVRNZ $src,1,$dst" %}
8008 8057 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8009 8058 ins_pipe(ialu_clr_and_mover);
8010 8059 %}
8011 8060 #endif
8012 8061
8013 8062 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8014 8063 match(Set dst (CmpLTMask p q));
8015 8064 effect( KILL ccr );
8016 8065 ins_cost(DEFAULT_COST*4);
8017 8066 format %{ "CMP $p,$q\n\t"
8018 8067 "MOV #0,$dst\n\t"
8019 8068 "BLT,a .+8\n\t"
8020 8069 "MOV #-1,$dst" %}
8021 8070 ins_encode( enc_ltmask(p,q,dst) );
8022 8071 ins_pipe(ialu_reg_reg_ialu);
8023 8072 %}
8024 8073
8025 8074 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8026 8075 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8027 8076 effect(KILL ccr, TEMP tmp);
8028 8077 ins_cost(DEFAULT_COST*3);
8029 8078
8030 8079 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8031 8080 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8032 8081 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8033 8082 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8034 8083 ins_pipe( cadd_cmpltmask );
8035 8084 %}
8036 8085
8037 8086 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8038 8087 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
8039 8088 effect( KILL ccr, TEMP tmp);
8040 8089 ins_cost(DEFAULT_COST*3);
8041 8090
8042 8091 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8043 8092 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8044 8093 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8045 8094 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8046 8095 ins_pipe( cadd_cmpltmask );
8047 8096 %}
8048 8097
8049 8098 //----------Arithmetic Conversion Instructions---------------------------------
8050 8099 // The conversions operations are all Alpha sorted. Please keep it that way!
8051 8100
8052 8101 instruct convD2F_reg(regF dst, regD src) %{
8053 8102 match(Set dst (ConvD2F src));
8054 8103 size(4);
8055 8104 format %{ "FDTOS $src,$dst" %}
8056 8105 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8057 8106 ins_encode(form3_opf_rs2D_rdF(src, dst));
8058 8107 ins_pipe(fcvtD2F);
8059 8108 %}
8060 8109
8061 8110
8062 8111 // Convert a double to an int in a float register.
8063 8112 // If the double is a NAN, stuff a zero in instead.
8064 8113 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8065 8114 effect(DEF dst, USE src, KILL fcc0);
8066 8115 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8067 8116 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8068 8117 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8069 8118 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8070 8119 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8071 8120 "skip:" %}
8072 8121 ins_encode(form_d2i_helper(src,dst));
8073 8122 ins_pipe(fcvtD2I);
8074 8123 %}
8075 8124
8076 8125 instruct convD2I_reg(stackSlotI dst, regD src) %{
8077 8126 match(Set dst (ConvD2I src));
8078 8127 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8079 8128 expand %{
8080 8129 regF tmp;
8081 8130 convD2I_helper(tmp, src);
8082 8131 regF_to_stkI(dst, tmp);
8083 8132 %}
8084 8133 %}
8085 8134
8086 8135 // Convert a double to a long in a double register.
8087 8136 // If the double is a NAN, stuff a zero in instead.
8088 8137 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8089 8138 effect(DEF dst, USE src, KILL fcc0);
8090 8139 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8091 8140 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8092 8141 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8093 8142 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8094 8143 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8095 8144 "skip:" %}
8096 8145 ins_encode(form_d2l_helper(src,dst));
8097 8146 ins_pipe(fcvtD2L);
8098 8147 %}
8099 8148
8100 8149
8101 8150 // Double to Long conversion
8102 8151 instruct convD2L_reg(stackSlotL dst, regD src) %{
8103 8152 match(Set dst (ConvD2L src));
8104 8153 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8105 8154 expand %{
8106 8155 regD tmp;
8107 8156 convD2L_helper(tmp, src);
8108 8157 regD_to_stkL(dst, tmp);
8109 8158 %}
8110 8159 %}
8111 8160
8112 8161
8113 8162 instruct convF2D_reg(regD dst, regF src) %{
8114 8163 match(Set dst (ConvF2D src));
8115 8164 format %{ "FSTOD $src,$dst" %}
8116 8165 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8117 8166 ins_encode(form3_opf_rs2F_rdD(src, dst));
8118 8167 ins_pipe(fcvtF2D);
8119 8168 %}
8120 8169
8121 8170
8122 8171 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8123 8172 effect(DEF dst, USE src, KILL fcc0);
8124 8173 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8125 8174 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8126 8175 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8127 8176 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8128 8177 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8129 8178 "skip:" %}
8130 8179 ins_encode(form_f2i_helper(src,dst));
8131 8180 ins_pipe(fcvtF2I);
8132 8181 %}
8133 8182
8134 8183 instruct convF2I_reg(stackSlotI dst, regF src) %{
8135 8184 match(Set dst (ConvF2I src));
8136 8185 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8137 8186 expand %{
8138 8187 regF tmp;
8139 8188 convF2I_helper(tmp, src);
8140 8189 regF_to_stkI(dst, tmp);
8141 8190 %}
8142 8191 %}
8143 8192
8144 8193
8145 8194 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8146 8195 effect(DEF dst, USE src, KILL fcc0);
8147 8196 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8148 8197 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8149 8198 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8150 8199 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8151 8200 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8152 8201 "skip:" %}
8153 8202 ins_encode(form_f2l_helper(src,dst));
8154 8203 ins_pipe(fcvtF2L);
8155 8204 %}
8156 8205
8157 8206 // Float to Long conversion
8158 8207 instruct convF2L_reg(stackSlotL dst, regF src) %{
8159 8208 match(Set dst (ConvF2L src));
8160 8209 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8161 8210 expand %{
8162 8211 regD tmp;
8163 8212 convF2L_helper(tmp, src);
8164 8213 regD_to_stkL(dst, tmp);
8165 8214 %}
8166 8215 %}
8167 8216
8168 8217
8169 8218 instruct convI2D_helper(regD dst, regF tmp) %{
8170 8219 effect(USE tmp, DEF dst);
8171 8220 format %{ "FITOD $tmp,$dst" %}
8172 8221 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8173 8222 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8174 8223 ins_pipe(fcvtI2D);
8175 8224 %}
8176 8225
8177 8226 instruct convI2D_reg(stackSlotI src, regD dst) %{
8178 8227 match(Set dst (ConvI2D src));
8179 8228 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8180 8229 expand %{
8181 8230 regF tmp;
8182 8231 stkI_to_regF( tmp, src);
8183 8232 convI2D_helper( dst, tmp);
8184 8233 %}
8185 8234 %}
8186 8235
8187 8236 instruct convI2D_mem( regD_low dst, memory mem ) %{
8188 8237 match(Set dst (ConvI2D (LoadI mem)));
8189 8238 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8190 8239 size(8);
8191 8240 format %{ "LDF $mem,$dst\n\t"
8192 8241 "FITOD $dst,$dst" %}
8193 8242 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8194 8243 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8195 8244 ins_pipe(floadF_mem);
8196 8245 %}
8197 8246
8198 8247
8199 8248 instruct convI2F_helper(regF dst, regF tmp) %{
8200 8249 effect(DEF dst, USE tmp);
8201 8250 format %{ "FITOS $tmp,$dst" %}
8202 8251 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8203 8252 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8204 8253 ins_pipe(fcvtI2F);
8205 8254 %}
8206 8255
8207 8256 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8208 8257 match(Set dst (ConvI2F src));
8209 8258 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8210 8259 expand %{
8211 8260 regF tmp;
8212 8261 stkI_to_regF(tmp,src);
8213 8262 convI2F_helper(dst, tmp);
8214 8263 %}
8215 8264 %}
8216 8265
8217 8266 instruct convI2F_mem( regF dst, memory mem ) %{
8218 8267 match(Set dst (ConvI2F (LoadI mem)));
8219 8268 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8220 8269 size(8);
8221 8270 format %{ "LDF $mem,$dst\n\t"
8222 8271 "FITOS $dst,$dst" %}
8223 8272 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8224 8273 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8225 8274 ins_pipe(floadF_mem);
8226 8275 %}
8227 8276
8228 8277
8229 8278 instruct convI2L_reg(iRegL dst, iRegI src) %{
8230 8279 match(Set dst (ConvI2L src));
8231 8280 size(4);
8232 8281 format %{ "SRA $src,0,$dst\t! int->long" %}
8233 8282 opcode(Assembler::sra_op3, Assembler::arith_op);
8234 8283 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8235 8284 ins_pipe(ialu_reg_reg);
8236 8285 %}
8237 8286
8238 8287 // Zero-extend convert int to long
8239 8288 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8240 8289 match(Set dst (AndL (ConvI2L src) mask) );
8241 8290 size(4);
8242 8291 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8243 8292 opcode(Assembler::srl_op3, Assembler::arith_op);
8244 8293 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8245 8294 ins_pipe(ialu_reg_reg);
8246 8295 %}
8247 8296
8248 8297 // Zero-extend long
8249 8298 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8250 8299 match(Set dst (AndL src mask) );
8251 8300 size(4);
8252 8301 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8253 8302 opcode(Assembler::srl_op3, Assembler::arith_op);
8254 8303 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8255 8304 ins_pipe(ialu_reg_reg);
8256 8305 %}
8257 8306
8258 8307 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8259 8308 match(Set dst (MoveF2I src));
8260 8309 effect(DEF dst, USE src);
8261 8310 ins_cost(MEMORY_REF_COST);
8262 8311
8263 8312 size(4);
8264 8313 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8265 8314 opcode(Assembler::lduw_op3);
8266 8315 ins_encode(simple_form3_mem_reg( src, dst ) );
8267 8316 ins_pipe(iload_mem);
8268 8317 %}
8269 8318
8270 8319 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8271 8320 match(Set dst (MoveI2F src));
8272 8321 effect(DEF dst, USE src);
8273 8322 ins_cost(MEMORY_REF_COST);
8274 8323
8275 8324 size(4);
8276 8325 format %{ "LDF $src,$dst\t! MoveI2F" %}
8277 8326 opcode(Assembler::ldf_op3);
8278 8327 ins_encode(simple_form3_mem_reg(src, dst));
8279 8328 ins_pipe(floadF_stk);
8280 8329 %}
8281 8330
8282 8331 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8283 8332 match(Set dst (MoveD2L src));
8284 8333 effect(DEF dst, USE src);
8285 8334 ins_cost(MEMORY_REF_COST);
8286 8335
8287 8336 size(4);
8288 8337 format %{ "LDX $src,$dst\t! MoveD2L" %}
8289 8338 opcode(Assembler::ldx_op3);
8290 8339 ins_encode(simple_form3_mem_reg( src, dst ) );
8291 8340 ins_pipe(iload_mem);
8292 8341 %}
8293 8342
8294 8343 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8295 8344 match(Set dst (MoveL2D src));
8296 8345 effect(DEF dst, USE src);
8297 8346 ins_cost(MEMORY_REF_COST);
8298 8347
8299 8348 size(4);
8300 8349 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8301 8350 opcode(Assembler::lddf_op3);
8302 8351 ins_encode(simple_form3_mem_reg(src, dst));
8303 8352 ins_pipe(floadD_stk);
8304 8353 %}
8305 8354
8306 8355 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8307 8356 match(Set dst (MoveF2I src));
8308 8357 effect(DEF dst, USE src);
8309 8358 ins_cost(MEMORY_REF_COST);
8310 8359
8311 8360 size(4);
8312 8361 format %{ "STF $src,$dst\t!MoveF2I" %}
8313 8362 opcode(Assembler::stf_op3);
8314 8363 ins_encode(simple_form3_mem_reg(dst, src));
8315 8364 ins_pipe(fstoreF_stk_reg);
8316 8365 %}
8317 8366
8318 8367 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8319 8368 match(Set dst (MoveI2F src));
8320 8369 effect(DEF dst, USE src);
8321 8370 ins_cost(MEMORY_REF_COST);
8322 8371
8323 8372 size(4);
8324 8373 format %{ "STW $src,$dst\t!MoveI2F" %}
8325 8374 opcode(Assembler::stw_op3);
8326 8375 ins_encode(simple_form3_mem_reg( dst, src ) );
8327 8376 ins_pipe(istore_mem_reg);
8328 8377 %}
8329 8378
8330 8379 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8331 8380 match(Set dst (MoveD2L src));
8332 8381 effect(DEF dst, USE src);
8333 8382 ins_cost(MEMORY_REF_COST);
8334 8383
8335 8384 size(4);
8336 8385 format %{ "STDF $src,$dst\t!MoveD2L" %}
8337 8386 opcode(Assembler::stdf_op3);
8338 8387 ins_encode(simple_form3_mem_reg(dst, src));
8339 8388 ins_pipe(fstoreD_stk_reg);
8340 8389 %}
8341 8390
8342 8391 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8343 8392 match(Set dst (MoveL2D src));
8344 8393 effect(DEF dst, USE src);
8345 8394 ins_cost(MEMORY_REF_COST);
8346 8395
8347 8396 size(4);
8348 8397 format %{ "STX $src,$dst\t!MoveL2D" %}
8349 8398 opcode(Assembler::stx_op3);
8350 8399 ins_encode(simple_form3_mem_reg( dst, src ) );
8351 8400 ins_pipe(istore_mem_reg);
8352 8401 %}
8353 8402
8354 8403
8355 8404 //-----------
8356 8405 // Long to Double conversion using V8 opcodes.
8357 8406 // Still useful because cheetah traps and becomes
8358 8407 // amazingly slow for some common numbers.
8359 8408
8360 8409 // Magic constant, 0x43300000
8361 8410 instruct loadConI_x43300000(iRegI dst) %{
8362 8411 effect(DEF dst);
8363 8412 size(4);
8364 8413 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8365 8414 ins_encode(SetHi22(0x43300000, dst));
8366 8415 ins_pipe(ialu_none);
8367 8416 %}
8368 8417
8369 8418 // Magic constant, 0x41f00000
8370 8419 instruct loadConI_x41f00000(iRegI dst) %{
8371 8420 effect(DEF dst);
8372 8421 size(4);
8373 8422 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8374 8423 ins_encode(SetHi22(0x41f00000, dst));
8375 8424 ins_pipe(ialu_none);
8376 8425 %}
8377 8426
8378 8427 // Construct a double from two float halves
8379 8428 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8380 8429 effect(DEF dst, USE src1, USE src2);
8381 8430 size(8);
8382 8431 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8383 8432 "FMOVS $src2.lo,$dst.lo" %}
8384 8433 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8385 8434 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8386 8435 ins_pipe(faddD_reg_reg);
8387 8436 %}
8388 8437
8389 8438 // Convert integer in high half of a double register (in the lower half of
8390 8439 // the double register file) to double
8391 8440 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8392 8441 effect(DEF dst, USE src);
8393 8442 size(4);
8394 8443 format %{ "FITOD $src,$dst" %}
8395 8444 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8396 8445 ins_encode(form3_opf_rs2D_rdD(src, dst));
8397 8446 ins_pipe(fcvtLHi2D);
8398 8447 %}
8399 8448
8400 8449 // Add float double precision
8401 8450 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8402 8451 effect(DEF dst, USE src1, USE src2);
8403 8452 size(4);
8404 8453 format %{ "FADDD $src1,$src2,$dst" %}
8405 8454 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8406 8455 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8407 8456 ins_pipe(faddD_reg_reg);
8408 8457 %}
8409 8458
8410 8459 // Sub float double precision
8411 8460 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8412 8461 effect(DEF dst, USE src1, USE src2);
8413 8462 size(4);
8414 8463 format %{ "FSUBD $src1,$src2,$dst" %}
8415 8464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8416 8465 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8417 8466 ins_pipe(faddD_reg_reg);
8418 8467 %}
8419 8468
8420 8469 // Mul float double precision
8421 8470 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8422 8471 effect(DEF dst, USE src1, USE src2);
8423 8472 size(4);
8424 8473 format %{ "FMULD $src1,$src2,$dst" %}
8425 8474 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8426 8475 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8427 8476 ins_pipe(fmulD_reg_reg);
8428 8477 %}
8429 8478
8430 8479 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8431 8480 match(Set dst (ConvL2D src));
8432 8481 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8433 8482
8434 8483 expand %{
8435 8484 regD_low tmpsrc;
8436 8485 iRegI ix43300000;
8437 8486 iRegI ix41f00000;
8438 8487 stackSlotL lx43300000;
8439 8488 stackSlotL lx41f00000;
8440 8489 regD_low dx43300000;
8441 8490 regD dx41f00000;
8442 8491 regD tmp1;
8443 8492 regD_low tmp2;
8444 8493 regD tmp3;
8445 8494 regD tmp4;
8446 8495
8447 8496 stkL_to_regD(tmpsrc, src);
8448 8497
8449 8498 loadConI_x43300000(ix43300000);
8450 8499 loadConI_x41f00000(ix41f00000);
8451 8500 regI_to_stkLHi(lx43300000, ix43300000);
8452 8501 regI_to_stkLHi(lx41f00000, ix41f00000);
8453 8502 stkL_to_regD(dx43300000, lx43300000);
8454 8503 stkL_to_regD(dx41f00000, lx41f00000);
8455 8504
8456 8505 convI2D_regDHi_regD(tmp1, tmpsrc);
8457 8506 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8458 8507 subD_regD_regD(tmp3, tmp2, dx43300000);
8459 8508 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8460 8509 addD_regD_regD(dst, tmp3, tmp4);
8461 8510 %}
8462 8511 %}
8463 8512
8464 8513 // Long to Double conversion using fast fxtof
8465 8514 instruct convL2D_helper(regD dst, regD tmp) %{
8466 8515 effect(DEF dst, USE tmp);
8467 8516 size(4);
8468 8517 format %{ "FXTOD $tmp,$dst" %}
8469 8518 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8470 8519 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8471 8520 ins_pipe(fcvtL2D);
8472 8521 %}
8473 8522
8474 8523 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8475 8524 predicate(VM_Version::has_fast_fxtof());
8476 8525 match(Set dst (ConvL2D src));
8477 8526 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8478 8527 expand %{
8479 8528 regD tmp;
8480 8529 stkL_to_regD(tmp, src);
8481 8530 convL2D_helper(dst, tmp);
8482 8531 %}
8483 8532 %}
8484 8533
8485 8534 //-----------
8486 8535 // Long to Float conversion using V8 opcodes.
8487 8536 // Still useful because cheetah traps and becomes
8488 8537 // amazingly slow for some common numbers.
8489 8538
8490 8539 // Long to Float conversion using fast fxtof
8491 8540 instruct convL2F_helper(regF dst, regD tmp) %{
8492 8541 effect(DEF dst, USE tmp);
8493 8542 size(4);
8494 8543 format %{ "FXTOS $tmp,$dst" %}
8495 8544 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8496 8545 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8497 8546 ins_pipe(fcvtL2F);
8498 8547 %}
8499 8548
8500 8549 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8501 8550 match(Set dst (ConvL2F src));
8502 8551 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8503 8552 expand %{
8504 8553 regD tmp;
8505 8554 stkL_to_regD(tmp, src);
8506 8555 convL2F_helper(dst, tmp);
8507 8556 %}
8508 8557 %}
8509 8558 //-----------
8510 8559
8511 8560 instruct convL2I_reg(iRegI dst, iRegL src) %{
8512 8561 match(Set dst (ConvL2I src));
8513 8562 #ifndef _LP64
8514 8563 format %{ "MOV $src.lo,$dst\t! long->int" %}
8515 8564 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8516 8565 ins_pipe(ialu_move_reg_I_to_L);
8517 8566 #else
8518 8567 size(4);
8519 8568 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8520 8569 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8521 8570 ins_pipe(ialu_reg);
8522 8571 #endif
8523 8572 %}
8524 8573
8525 8574 // Register Shift Right Immediate
8526 8575 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8527 8576 match(Set dst (ConvL2I (RShiftL src cnt)));
8528 8577
8529 8578 size(4);
8530 8579 format %{ "SRAX $src,$cnt,$dst" %}
8531 8580 opcode(Assembler::srax_op3, Assembler::arith_op);
8532 8581 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8533 8582 ins_pipe(ialu_reg_imm);
8534 8583 %}
8535 8584
8536 8585 // Replicate scalar to packed byte values in Double register
8537 8586 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8538 8587 effect(DEF dst, USE src);
8539 8588 format %{ "SLLX $src,56,$dst\n\t"
8540 8589 "SRLX $dst, 8,O7\n\t"
8541 8590 "OR $dst,O7,$dst\n\t"
8542 8591 "SRLX $dst,16,O7\n\t"
8543 8592 "OR $dst,O7,$dst\n\t"
8544 8593 "SRLX $dst,32,O7\n\t"
8545 8594 "OR $dst,O7,$dst\t! replicate8B" %}
8546 8595 ins_encode( enc_repl8b(src, dst));
8547 8596 ins_pipe(ialu_reg);
8548 8597 %}
8549 8598
8550 8599 // Replicate scalar to packed byte values in Double register
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8551 8600 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8552 8601 match(Set dst (Replicate8B src));
8553 8602 expand %{
8554 8603 iRegL tmp;
8555 8604 Repl8B_reg_helper(tmp, src);
8556 8605 regL_to_stkD(dst, tmp);
8557 8606 %}
8558 8607 %}
8559 8608
8560 8609 // Replicate scalar constant to packed byte values in Double register
8561 -instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8562 - match(Set dst (Replicate8B src));
8563 -#ifdef _LP64
8564 - size(36);
8565 -#else
8566 - size(8);
8567 -#endif
8568 - format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8569 - "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8570 - ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8610 +instruct Repl8B_immI(regD dst, immI13 con) %{
8611 + match(Set dst (Replicate8B con));
8612 + size(4);
8613 + format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8614 + ins_encode %{
8615 + // XXX This is a quick fix for 6833573.
8616 + //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8617 + __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), as_DoubleFloatRegister($dst$$reg));
8618 + %}
8571 8619 ins_pipe(loadConFD);
8572 8620 %}
8573 8621
8574 8622 // Replicate scalar to packed char values into stack slot
8575 8623 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8576 8624 effect(DEF dst, USE src);
8577 8625 format %{ "SLLX $src,48,$dst\n\t"
8578 8626 "SRLX $dst,16,O7\n\t"
8579 8627 "OR $dst,O7,$dst\n\t"
8580 8628 "SRLX $dst,32,O7\n\t"
8581 8629 "OR $dst,O7,$dst\t! replicate4C" %}
8582 8630 ins_encode( enc_repl4s(src, dst) );
8583 8631 ins_pipe(ialu_reg);
8584 8632 %}
8585 8633
8586 8634 // Replicate scalar to packed char values into stack slot
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8587 8635 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8588 8636 match(Set dst (Replicate4C src));
8589 8637 expand %{
8590 8638 iRegL tmp;
8591 8639 Repl4C_reg_helper(tmp, src);
8592 8640 regL_to_stkD(dst, tmp);
8593 8641 %}
8594 8642 %}
8595 8643
8596 8644 // Replicate scalar constant to packed char values in Double register
8597 -instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8598 - match(Set dst (Replicate4C src));
8599 -#ifdef _LP64
8600 - size(36);
8601 -#else
8602 - size(8);
8603 -#endif
8604 - format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8605 - "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8606 - ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8645 +instruct Repl4C_immI(regD dst, immI con) %{
8646 + match(Set dst (Replicate4C con));
8647 + size(4);
8648 + format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8649 + ins_encode %{
8650 + // XXX This is a quick fix for 6833573.
8651 + //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8652 + __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg));
8653 + %}
8607 8654 ins_pipe(loadConFD);
8608 8655 %}
8609 8656
8610 8657 // Replicate scalar to packed short values into stack slot
8611 8658 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8612 8659 effect(DEF dst, USE src);
8613 8660 format %{ "SLLX $src,48,$dst\n\t"
8614 8661 "SRLX $dst,16,O7\n\t"
8615 8662 "OR $dst,O7,$dst\n\t"
8616 8663 "SRLX $dst,32,O7\n\t"
8617 8664 "OR $dst,O7,$dst\t! replicate4S" %}
8618 8665 ins_encode( enc_repl4s(src, dst) );
8619 8666 ins_pipe(ialu_reg);
8620 8667 %}
8621 8668
8622 8669 // Replicate scalar to packed short values into stack slot
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8623 8670 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8624 8671 match(Set dst (Replicate4S src));
8625 8672 expand %{
8626 8673 iRegL tmp;
8627 8674 Repl4S_reg_helper(tmp, src);
8628 8675 regL_to_stkD(dst, tmp);
8629 8676 %}
8630 8677 %}
8631 8678
8632 8679 // Replicate scalar constant to packed short values in Double register
8633 -instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8634 - match(Set dst (Replicate4S src));
8635 -#ifdef _LP64
8636 - size(36);
8637 -#else
8638 - size(8);
8639 -#endif
8640 - format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8641 - "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8642 - ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8680 +instruct Repl4S_immI(regD dst, immI con) %{
8681 + match(Set dst (Replicate4S con));
8682 + size(4);
8683 + format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8684 + ins_encode %{
8685 + // XXX This is a quick fix for 6833573.
8686 + //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8687 + __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg));
8688 + %}
8643 8689 ins_pipe(loadConFD);
8644 8690 %}
8645 8691
8646 8692 // Replicate scalar to packed int values in Double register
8647 8693 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8648 8694 effect(DEF dst, USE src);
8649 8695 format %{ "SLLX $src,32,$dst\n\t"
8650 8696 "SRLX $dst,32,O7\n\t"
8651 8697 "OR $dst,O7,$dst\t! replicate2I" %}
8652 8698 ins_encode( enc_repl2i(src, dst));
8653 8699 ins_pipe(ialu_reg);
8654 8700 %}
8655 8701
8656 8702 // Replicate scalar to packed int values in Double register
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8657 8703 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8658 8704 match(Set dst (Replicate2I src));
8659 8705 expand %{
8660 8706 iRegL tmp;
8661 8707 Repl2I_reg_helper(tmp, src);
8662 8708 regL_to_stkD(dst, tmp);
8663 8709 %}
8664 8710 %}
8665 8711
8666 8712 // Replicate scalar zero constant to packed int values in Double register
8667 -instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8668 - match(Set dst (Replicate2I src));
8669 -#ifdef _LP64
8670 - size(36);
8671 -#else
8672 - size(8);
8673 -#endif
8674 - format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8675 - "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8676 - ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8713 +instruct Repl2I_immI(regD dst, immI con) %{
8714 + match(Set dst (Replicate2I con));
8715 + size(4);
8716 + format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8717 + ins_encode %{
8718 + // XXX This is a quick fix for 6833573.
8719 + //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8720 + __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), as_DoubleFloatRegister($dst$$reg));
8721 + %}
8677 8722 ins_pipe(loadConFD);
8678 8723 %}
8679 8724
8680 8725 //----------Control Flow Instructions------------------------------------------
8681 8726 // Compare Instructions
8682 8727 // Compare Integers
8683 8728 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8684 8729 match(Set icc (CmpI op1 op2));
8685 8730 effect( DEF icc, USE op1, USE op2 );
8686 8731
8687 8732 size(4);
8688 8733 format %{ "CMP $op1,$op2" %}
8689 8734 opcode(Assembler::subcc_op3, Assembler::arith_op);
8690 8735 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8691 8736 ins_pipe(ialu_cconly_reg_reg);
8692 8737 %}
8693 8738
8694 8739 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8695 8740 match(Set icc (CmpU op1 op2));
8696 8741
8697 8742 size(4);
8698 8743 format %{ "CMP $op1,$op2\t! unsigned" %}
8699 8744 opcode(Assembler::subcc_op3, Assembler::arith_op);
8700 8745 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8701 8746 ins_pipe(ialu_cconly_reg_reg);
8702 8747 %}
8703 8748
8704 8749 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8705 8750 match(Set icc (CmpI op1 op2));
8706 8751 effect( DEF icc, USE op1 );
8707 8752
8708 8753 size(4);
8709 8754 format %{ "CMP $op1,$op2" %}
8710 8755 opcode(Assembler::subcc_op3, Assembler::arith_op);
8711 8756 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8712 8757 ins_pipe(ialu_cconly_reg_imm);
8713 8758 %}
8714 8759
8715 8760 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8716 8761 match(Set icc (CmpI (AndI op1 op2) zero));
8717 8762
8718 8763 size(4);
8719 8764 format %{ "BTST $op2,$op1" %}
8720 8765 opcode(Assembler::andcc_op3, Assembler::arith_op);
8721 8766 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8722 8767 ins_pipe(ialu_cconly_reg_reg_zero);
8723 8768 %}
8724 8769
8725 8770 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8726 8771 match(Set icc (CmpI (AndI op1 op2) zero));
8727 8772
8728 8773 size(4);
8729 8774 format %{ "BTST $op2,$op1" %}
8730 8775 opcode(Assembler::andcc_op3, Assembler::arith_op);
8731 8776 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8732 8777 ins_pipe(ialu_cconly_reg_imm_zero);
8733 8778 %}
8734 8779
8735 8780 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8736 8781 match(Set xcc (CmpL op1 op2));
8737 8782 effect( DEF xcc, USE op1, USE op2 );
8738 8783
8739 8784 size(4);
8740 8785 format %{ "CMP $op1,$op2\t\t! long" %}
8741 8786 opcode(Assembler::subcc_op3, Assembler::arith_op);
8742 8787 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8743 8788 ins_pipe(ialu_cconly_reg_reg);
8744 8789 %}
8745 8790
8746 8791 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8747 8792 match(Set xcc (CmpL op1 con));
8748 8793 effect( DEF xcc, USE op1, USE con );
8749 8794
8750 8795 size(4);
8751 8796 format %{ "CMP $op1,$con\t\t! long" %}
8752 8797 opcode(Assembler::subcc_op3, Assembler::arith_op);
8753 8798 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8754 8799 ins_pipe(ialu_cconly_reg_reg);
8755 8800 %}
8756 8801
8757 8802 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8758 8803 match(Set xcc (CmpL (AndL op1 op2) zero));
8759 8804 effect( DEF xcc, USE op1, USE op2 );
8760 8805
8761 8806 size(4);
8762 8807 format %{ "BTST $op1,$op2\t\t! long" %}
8763 8808 opcode(Assembler::andcc_op3, Assembler::arith_op);
8764 8809 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8765 8810 ins_pipe(ialu_cconly_reg_reg);
8766 8811 %}
8767 8812
8768 8813 // useful for checking the alignment of a pointer:
8769 8814 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8770 8815 match(Set xcc (CmpL (AndL op1 con) zero));
8771 8816 effect( DEF xcc, USE op1, USE con );
8772 8817
8773 8818 size(4);
8774 8819 format %{ "BTST $op1,$con\t\t! long" %}
8775 8820 opcode(Assembler::andcc_op3, Assembler::arith_op);
8776 8821 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8777 8822 ins_pipe(ialu_cconly_reg_reg);
8778 8823 %}
8779 8824
8780 8825 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8781 8826 match(Set icc (CmpU op1 op2));
8782 8827
8783 8828 size(4);
8784 8829 format %{ "CMP $op1,$op2\t! unsigned" %}
8785 8830 opcode(Assembler::subcc_op3, Assembler::arith_op);
8786 8831 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8787 8832 ins_pipe(ialu_cconly_reg_imm);
8788 8833 %}
8789 8834
8790 8835 // Compare Pointers
8791 8836 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8792 8837 match(Set pcc (CmpP op1 op2));
8793 8838
8794 8839 size(4);
8795 8840 format %{ "CMP $op1,$op2\t! ptr" %}
8796 8841 opcode(Assembler::subcc_op3, Assembler::arith_op);
8797 8842 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8798 8843 ins_pipe(ialu_cconly_reg_reg);
8799 8844 %}
8800 8845
8801 8846 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8802 8847 match(Set pcc (CmpP op1 op2));
8803 8848
8804 8849 size(4);
8805 8850 format %{ "CMP $op1,$op2\t! ptr" %}
8806 8851 opcode(Assembler::subcc_op3, Assembler::arith_op);
8807 8852 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8808 8853 ins_pipe(ialu_cconly_reg_imm);
8809 8854 %}
8810 8855
8811 8856 // Compare Narrow oops
8812 8857 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8813 8858 match(Set icc (CmpN op1 op2));
8814 8859
8815 8860 size(4);
8816 8861 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8817 8862 opcode(Assembler::subcc_op3, Assembler::arith_op);
8818 8863 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8819 8864 ins_pipe(ialu_cconly_reg_reg);
8820 8865 %}
8821 8866
8822 8867 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8823 8868 match(Set icc (CmpN op1 op2));
8824 8869
8825 8870 size(4);
8826 8871 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8827 8872 opcode(Assembler::subcc_op3, Assembler::arith_op);
8828 8873 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8829 8874 ins_pipe(ialu_cconly_reg_imm);
8830 8875 %}
8831 8876
8832 8877 //----------Max and Min--------------------------------------------------------
8833 8878 // Min Instructions
8834 8879 // Conditional move for min
8835 8880 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8836 8881 effect( USE_DEF op2, USE op1, USE icc );
8837 8882
8838 8883 size(4);
8839 8884 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8840 8885 opcode(Assembler::less);
8841 8886 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8842 8887 ins_pipe(ialu_reg_flags);
8843 8888 %}
8844 8889
8845 8890 // Min Register with Register.
8846 8891 instruct minI_eReg(iRegI op1, iRegI op2) %{
8847 8892 match(Set op2 (MinI op1 op2));
8848 8893 ins_cost(DEFAULT_COST*2);
8849 8894 expand %{
8850 8895 flagsReg icc;
8851 8896 compI_iReg(icc,op1,op2);
8852 8897 cmovI_reg_lt(op2,op1,icc);
8853 8898 %}
8854 8899 %}
8855 8900
8856 8901 // Max Instructions
8857 8902 // Conditional move for max
8858 8903 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8859 8904 effect( USE_DEF op2, USE op1, USE icc );
8860 8905 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8861 8906 opcode(Assembler::greater);
8862 8907 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8863 8908 ins_pipe(ialu_reg_flags);
8864 8909 %}
8865 8910
8866 8911 // Max Register with Register
8867 8912 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8868 8913 match(Set op2 (MaxI op1 op2));
8869 8914 ins_cost(DEFAULT_COST*2);
8870 8915 expand %{
8871 8916 flagsReg icc;
8872 8917 compI_iReg(icc,op1,op2);
8873 8918 cmovI_reg_gt(op2,op1,icc);
8874 8919 %}
8875 8920 %}
8876 8921
8877 8922
8878 8923 //----------Float Compares----------------------------------------------------
8879 8924 // Compare floating, generate condition code
8880 8925 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8881 8926 match(Set fcc (CmpF src1 src2));
8882 8927
8883 8928 size(4);
8884 8929 format %{ "FCMPs $fcc,$src1,$src2" %}
8885 8930 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8886 8931 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8887 8932 ins_pipe(faddF_fcc_reg_reg_zero);
8888 8933 %}
8889 8934
8890 8935 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8891 8936 match(Set fcc (CmpD src1 src2));
8892 8937
8893 8938 size(4);
8894 8939 format %{ "FCMPd $fcc,$src1,$src2" %}
8895 8940 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8896 8941 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8897 8942 ins_pipe(faddD_fcc_reg_reg_zero);
8898 8943 %}
8899 8944
8900 8945
8901 8946 // Compare floating, generate -1,0,1
8902 8947 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8903 8948 match(Set dst (CmpF3 src1 src2));
8904 8949 effect(KILL fcc0);
8905 8950 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8906 8951 format %{ "fcmpl $dst,$src1,$src2" %}
8907 8952 // Primary = float
8908 8953 opcode( true );
8909 8954 ins_encode( floating_cmp( dst, src1, src2 ) );
8910 8955 ins_pipe( floating_cmp );
8911 8956 %}
8912 8957
8913 8958 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8914 8959 match(Set dst (CmpD3 src1 src2));
8915 8960 effect(KILL fcc0);
8916 8961 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8917 8962 format %{ "dcmpl $dst,$src1,$src2" %}
8918 8963 // Primary = double (not float)
8919 8964 opcode( false );
8920 8965 ins_encode( floating_cmp( dst, src1, src2 ) );
8921 8966 ins_pipe( floating_cmp );
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8922 8967 %}
8923 8968
8924 8969 //----------Branches---------------------------------------------------------
8925 8970 // Jump
8926 8971 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8927 8972 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8928 8973 match(Jump switch_val);
8929 8974
8930 8975 ins_cost(350);
8931 8976
8932 - format %{ "SETHI [hi(table_base)],O7\n\t"
8933 - "ADD O7, lo(table_base), O7\n\t"
8934 - "LD [O7+$switch_val], O7\n\t"
8977 + format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8978 + "LD [O7 + $switch_val], O7\n\t"
8935 8979 "JUMP O7"
8936 8980 %}
8937 - ins_encode( jump_enc( switch_val, table) );
8981 + ins_encode %{
8982 + // Calculate table address into a register.
8983 + Register table_reg;
8984 + Register label_reg = O7;
8985 + if (constant_offset() == 0) {
8986 + table_reg = $constanttablebase;
8987 + } else {
8988 + table_reg = O7;
8989 + __ add($constanttablebase, $constantoffset, table_reg);
8990 + }
8991 +
8992 + // Jump to base address + switch value
8993 + __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8994 + __ jmp(label_reg, G0);
8995 + __ delayed()->nop();
8996 + %}
8938 8997 ins_pc_relative(1);
8939 8998 ins_pipe(ialu_reg_reg);
8940 8999 %}
8941 9000
8942 9001 // Direct Branch. Use V8 version with longer range.
8943 9002 instruct branch(label labl) %{
8944 9003 match(Goto);
8945 9004 effect(USE labl);
8946 9005
8947 9006 size(8);
8948 9007 ins_cost(BRANCH_COST);
8949 9008 format %{ "BA $labl" %}
8950 9009 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8951 9010 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8952 9011 ins_encode( enc_ba( labl ) );
8953 9012 ins_pc_relative(1);
8954 9013 ins_pipe(br);
8955 9014 %}
8956 9015
8957 9016 // Conditional Direct Branch
8958 9017 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8959 9018 match(If cmp icc);
8960 9019 effect(USE labl);
8961 9020
8962 9021 size(8);
8963 9022 ins_cost(BRANCH_COST);
8964 9023 format %{ "BP$cmp $icc,$labl" %}
8965 9024 // Prim = bits 24-22, Secnd = bits 31-30
8966 9025 ins_encode( enc_bp( labl, cmp, icc ) );
8967 9026 ins_pc_relative(1);
8968 9027 ins_pipe(br_cc);
8969 9028 %}
8970 9029
8971 9030 // Branch-on-register tests all 64 bits. We assume that values
8972 9031 // in 64-bit registers always remains zero or sign extended
8973 9032 // unless our code munges the high bits. Interrupts can chop
8974 9033 // the high order bits to zero or sign at any time.
8975 9034 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8976 9035 match(If cmp (CmpI op1 zero));
8977 9036 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8978 9037 effect(USE labl);
8979 9038
8980 9039 size(8);
8981 9040 ins_cost(BRANCH_COST);
8982 9041 format %{ "BR$cmp $op1,$labl" %}
8983 9042 ins_encode( enc_bpr( labl, cmp, op1 ) );
8984 9043 ins_pc_relative(1);
8985 9044 ins_pipe(br_reg);
8986 9045 %}
8987 9046
8988 9047 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8989 9048 match(If cmp (CmpP op1 null));
8990 9049 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8991 9050 effect(USE labl);
8992 9051
8993 9052 size(8);
8994 9053 ins_cost(BRANCH_COST);
8995 9054 format %{ "BR$cmp $op1,$labl" %}
8996 9055 ins_encode( enc_bpr( labl, cmp, op1 ) );
8997 9056 ins_pc_relative(1);
8998 9057 ins_pipe(br_reg);
8999 9058 %}
9000 9059
9001 9060 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9002 9061 match(If cmp (CmpL op1 zero));
9003 9062 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9004 9063 effect(USE labl);
9005 9064
9006 9065 size(8);
9007 9066 ins_cost(BRANCH_COST);
9008 9067 format %{ "BR$cmp $op1,$labl" %}
9009 9068 ins_encode( enc_bpr( labl, cmp, op1 ) );
9010 9069 ins_pc_relative(1);
9011 9070 ins_pipe(br_reg);
9012 9071 %}
9013 9072
9014 9073 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9015 9074 match(If cmp icc);
9016 9075 effect(USE labl);
9017 9076
9018 9077 format %{ "BP$cmp $icc,$labl" %}
9019 9078 // Prim = bits 24-22, Secnd = bits 31-30
9020 9079 ins_encode( enc_bp( labl, cmp, icc ) );
9021 9080 ins_pc_relative(1);
9022 9081 ins_pipe(br_cc);
9023 9082 %}
9024 9083
9025 9084 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9026 9085 match(If cmp pcc);
9027 9086 effect(USE labl);
9028 9087
9029 9088 size(8);
9030 9089 ins_cost(BRANCH_COST);
9031 9090 format %{ "BP$cmp $pcc,$labl" %}
9032 9091 // Prim = bits 24-22, Secnd = bits 31-30
9033 9092 ins_encode( enc_bpx( labl, cmp, pcc ) );
9034 9093 ins_pc_relative(1);
9035 9094 ins_pipe(br_cc);
9036 9095 %}
9037 9096
9038 9097 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9039 9098 match(If cmp fcc);
9040 9099 effect(USE labl);
9041 9100
9042 9101 size(8);
9043 9102 ins_cost(BRANCH_COST);
9044 9103 format %{ "FBP$cmp $fcc,$labl" %}
9045 9104 // Prim = bits 24-22, Secnd = bits 31-30
9046 9105 ins_encode( enc_fbp( labl, cmp, fcc ) );
9047 9106 ins_pc_relative(1);
9048 9107 ins_pipe(br_fcc);
9049 9108 %}
9050 9109
9051 9110 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9052 9111 match(CountedLoopEnd cmp icc);
9053 9112 effect(USE labl);
9054 9113
9055 9114 size(8);
9056 9115 ins_cost(BRANCH_COST);
9057 9116 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9058 9117 // Prim = bits 24-22, Secnd = bits 31-30
9059 9118 ins_encode( enc_bp( labl, cmp, icc ) );
9060 9119 ins_pc_relative(1);
9061 9120 ins_pipe(br_cc);
9062 9121 %}
9063 9122
9064 9123 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9065 9124 match(CountedLoopEnd cmp icc);
9066 9125 effect(USE labl);
9067 9126
9068 9127 size(8);
9069 9128 ins_cost(BRANCH_COST);
9070 9129 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9071 9130 // Prim = bits 24-22, Secnd = bits 31-30
9072 9131 ins_encode( enc_bp( labl, cmp, icc ) );
9073 9132 ins_pc_relative(1);
9074 9133 ins_pipe(br_cc);
9075 9134 %}
9076 9135
9077 9136 // ============================================================================
9078 9137 // Long Compare
9079 9138 //
9080 9139 // Currently we hold longs in 2 registers. Comparing such values efficiently
9081 9140 // is tricky. The flavor of compare used depends on whether we are testing
9082 9141 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9083 9142 // The GE test is the negated LT test. The LE test can be had by commuting
9084 9143 // the operands (yielding a GE test) and then negating; negate again for the
9085 9144 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9086 9145 // NE test is negated from that.
9087 9146
9088 9147 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9089 9148 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9090 9149 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9091 9150 // are collapsed internally in the ADLC's dfa-gen code. The match for
9092 9151 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9093 9152 // foo match ends up with the wrong leaf. One fix is to not match both
9094 9153 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9095 9154 // both forms beat the trinary form of long-compare and both are very useful
9096 9155 // on Intel which has so few registers.
9097 9156
9098 9157 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9099 9158 match(If cmp xcc);
9100 9159 effect(USE labl);
9101 9160
9102 9161 size(8);
9103 9162 ins_cost(BRANCH_COST);
9104 9163 format %{ "BP$cmp $xcc,$labl" %}
9105 9164 // Prim = bits 24-22, Secnd = bits 31-30
9106 9165 ins_encode( enc_bpl( labl, cmp, xcc ) );
9107 9166 ins_pc_relative(1);
9108 9167 ins_pipe(br_cc);
9109 9168 %}
9110 9169
9111 9170 // Manifest a CmpL3 result in an integer register. Very painful.
9112 9171 // This is the test to avoid.
9113 9172 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9114 9173 match(Set dst (CmpL3 src1 src2) );
9115 9174 effect( KILL ccr );
9116 9175 ins_cost(6*DEFAULT_COST);
9117 9176 size(24);
9118 9177 format %{ "CMP $src1,$src2\t\t! long\n"
9119 9178 "\tBLT,a,pn done\n"
9120 9179 "\tMOV -1,$dst\t! delay slot\n"
9121 9180 "\tBGT,a,pn done\n"
9122 9181 "\tMOV 1,$dst\t! delay slot\n"
9123 9182 "\tCLR $dst\n"
9124 9183 "done:" %}
9125 9184 ins_encode( cmpl_flag(src1,src2,dst) );
9126 9185 ins_pipe(cmpL_reg);
9127 9186 %}
9128 9187
9129 9188 // Conditional move
9130 9189 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9131 9190 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9132 9191 ins_cost(150);
9133 9192 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9134 9193 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9135 9194 ins_pipe(ialu_reg);
9136 9195 %}
9137 9196
9138 9197 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9139 9198 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9140 9199 ins_cost(140);
9141 9200 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9142 9201 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9143 9202 ins_pipe(ialu_imm);
9144 9203 %}
9145 9204
9146 9205 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9147 9206 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9148 9207 ins_cost(150);
9149 9208 format %{ "MOV$cmp $xcc,$src,$dst" %}
9150 9209 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9151 9210 ins_pipe(ialu_reg);
9152 9211 %}
9153 9212
9154 9213 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9155 9214 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9156 9215 ins_cost(140);
9157 9216 format %{ "MOV$cmp $xcc,$src,$dst" %}
9158 9217 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9159 9218 ins_pipe(ialu_imm);
9160 9219 %}
9161 9220
9162 9221 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9163 9222 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9164 9223 ins_cost(150);
9165 9224 format %{ "MOV$cmp $xcc,$src,$dst" %}
9166 9225 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9167 9226 ins_pipe(ialu_reg);
9168 9227 %}
9169 9228
9170 9229 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9171 9230 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9172 9231 ins_cost(150);
9173 9232 format %{ "MOV$cmp $xcc,$src,$dst" %}
9174 9233 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9175 9234 ins_pipe(ialu_reg);
9176 9235 %}
9177 9236
9178 9237 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9179 9238 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9180 9239 ins_cost(140);
9181 9240 format %{ "MOV$cmp $xcc,$src,$dst" %}
9182 9241 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9183 9242 ins_pipe(ialu_imm);
9184 9243 %}
9185 9244
9186 9245 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9187 9246 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9188 9247 ins_cost(150);
9189 9248 opcode(0x101);
9190 9249 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9191 9250 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9192 9251 ins_pipe(int_conditional_float_move);
9193 9252 %}
9194 9253
9195 9254 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9196 9255 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9197 9256 ins_cost(150);
9198 9257 opcode(0x102);
9199 9258 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9200 9259 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9201 9260 ins_pipe(int_conditional_float_move);
9202 9261 %}
9203 9262
9204 9263 // ============================================================================
9205 9264 // Safepoint Instruction
9206 9265 instruct safePoint_poll(iRegP poll) %{
9207 9266 match(SafePoint poll);
9208 9267 effect(USE poll);
9209 9268
9210 9269 size(4);
9211 9270 #ifdef _LP64
9212 9271 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9213 9272 #else
9214 9273 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9215 9274 #endif
9216 9275 ins_encode %{
9217 9276 __ relocate(relocInfo::poll_type);
9218 9277 __ ld_ptr($poll$$Register, 0, G0);
9219 9278 %}
9220 9279 ins_pipe(loadPollP);
9221 9280 %}
9222 9281
9223 9282 // ============================================================================
9224 9283 // Call Instructions
9225 9284 // Call Java Static Instruction
9226 9285 instruct CallStaticJavaDirect( method meth ) %{
9227 9286 match(CallStaticJava);
9228 9287 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9229 9288 effect(USE meth);
9230 9289
9231 9290 size(8);
9232 9291 ins_cost(CALL_COST);
9233 9292 format %{ "CALL,static ; NOP ==> " %}
9234 9293 ins_encode( Java_Static_Call( meth ), call_epilog );
9235 9294 ins_pc_relative(1);
9236 9295 ins_pipe(simple_call);
9237 9296 %}
9238 9297
9239 9298 // Call Java Static Instruction (method handle version)
9240 9299 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9241 9300 match(CallStaticJava);
9242 9301 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9243 9302 effect(USE meth, KILL l7_mh_SP_save);
9244 9303
9245 9304 size(8);
9246 9305 ins_cost(CALL_COST);
9247 9306 format %{ "CALL,static/MethodHandle" %}
9248 9307 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9249 9308 ins_pc_relative(1);
9250 9309 ins_pipe(simple_call);
9251 9310 %}
9252 9311
9253 9312 // Call Java Dynamic Instruction
9254 9313 instruct CallDynamicJavaDirect( method meth ) %{
9255 9314 match(CallDynamicJava);
9256 9315 effect(USE meth);
9257 9316
9258 9317 ins_cost(CALL_COST);
9259 9318 format %{ "SET (empty),R_G5\n\t"
9260 9319 "CALL,dynamic ; NOP ==> " %}
9261 9320 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9262 9321 ins_pc_relative(1);
9263 9322 ins_pipe(call);
9264 9323 %}
9265 9324
9266 9325 // Call Runtime Instruction
9267 9326 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9268 9327 match(CallRuntime);
9269 9328 effect(USE meth, KILL l7);
9270 9329 ins_cost(CALL_COST);
9271 9330 format %{ "CALL,runtime" %}
9272 9331 ins_encode( Java_To_Runtime( meth ),
9273 9332 call_epilog, adjust_long_from_native_call );
9274 9333 ins_pc_relative(1);
9275 9334 ins_pipe(simple_call);
9276 9335 %}
9277 9336
9278 9337 // Call runtime without safepoint - same as CallRuntime
9279 9338 instruct CallLeafDirect(method meth, l7RegP l7) %{
9280 9339 match(CallLeaf);
9281 9340 effect(USE meth, KILL l7);
9282 9341 ins_cost(CALL_COST);
9283 9342 format %{ "CALL,runtime leaf" %}
9284 9343 ins_encode( Java_To_Runtime( meth ),
9285 9344 call_epilog,
9286 9345 adjust_long_from_native_call );
9287 9346 ins_pc_relative(1);
9288 9347 ins_pipe(simple_call);
9289 9348 %}
9290 9349
9291 9350 // Call runtime without safepoint - same as CallLeaf
9292 9351 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9293 9352 match(CallLeafNoFP);
9294 9353 effect(USE meth, KILL l7);
9295 9354 ins_cost(CALL_COST);
9296 9355 format %{ "CALL,runtime leaf nofp" %}
9297 9356 ins_encode( Java_To_Runtime( meth ),
9298 9357 call_epilog,
9299 9358 adjust_long_from_native_call );
9300 9359 ins_pc_relative(1);
9301 9360 ins_pipe(simple_call);
9302 9361 %}
9303 9362
9304 9363 // Tail Call; Jump from runtime stub to Java code.
9305 9364 // Also known as an 'interprocedural jump'.
9306 9365 // Target of jump will eventually return to caller.
9307 9366 // TailJump below removes the return address.
9308 9367 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9309 9368 match(TailCall jump_target method_oop );
9310 9369
9311 9370 ins_cost(CALL_COST);
9312 9371 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9313 9372 ins_encode(form_jmpl(jump_target));
9314 9373 ins_pipe(tail_call);
9315 9374 %}
9316 9375
9317 9376
9318 9377 // Return Instruction
9319 9378 instruct Ret() %{
9320 9379 match(Return);
9321 9380
9322 9381 // The epilogue node did the ret already.
9323 9382 size(0);
9324 9383 format %{ "! return" %}
9325 9384 ins_encode();
9326 9385 ins_pipe(empty);
9327 9386 %}
9328 9387
9329 9388
9330 9389 // Tail Jump; remove the return address; jump to target.
9331 9390 // TailCall above leaves the return address around.
9332 9391 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9333 9392 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9334 9393 // "restore" before this instruction (in Epilogue), we need to materialize it
9335 9394 // in %i0.
9336 9395 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9337 9396 match( TailJump jump_target ex_oop );
9338 9397 ins_cost(CALL_COST);
9339 9398 format %{ "! discard R_O7\n\t"
9340 9399 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9341 9400 ins_encode(form_jmpl_set_exception_pc(jump_target));
9342 9401 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9343 9402 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9344 9403 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9345 9404 ins_pipe(tail_call);
9346 9405 %}
9347 9406
9348 9407 // Create exception oop: created by stack-crawling runtime code.
9349 9408 // Created exception is now available to this handler, and is setup
9350 9409 // just prior to jumping to this handler. No code emitted.
9351 9410 instruct CreateException( o0RegP ex_oop )
9352 9411 %{
9353 9412 match(Set ex_oop (CreateEx));
9354 9413 ins_cost(0);
9355 9414
9356 9415 size(0);
9357 9416 // use the following format syntax
9358 9417 format %{ "! exception oop is in R_O0; no code emitted" %}
9359 9418 ins_encode();
9360 9419 ins_pipe(empty);
9361 9420 %}
9362 9421
9363 9422
9364 9423 // Rethrow exception:
9365 9424 // The exception oop will come in the first argument position.
9366 9425 // Then JUMP (not call) to the rethrow stub code.
9367 9426 instruct RethrowException()
9368 9427 %{
9369 9428 match(Rethrow);
9370 9429 ins_cost(CALL_COST);
9371 9430
9372 9431 // use the following format syntax
9373 9432 format %{ "Jmp rethrow_stub" %}
9374 9433 ins_encode(enc_rethrow);
9375 9434 ins_pipe(tail_call);
9376 9435 %}
9377 9436
9378 9437
9379 9438 // Die now
9380 9439 instruct ShouldNotReachHere( )
9381 9440 %{
9382 9441 match(Halt);
9383 9442 ins_cost(CALL_COST);
9384 9443
9385 9444 size(4);
9386 9445 // Use the following format syntax
9387 9446 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9388 9447 ins_encode( form2_illtrap() );
9389 9448 ins_pipe(tail_call);
9390 9449 %}
9391 9450
9392 9451 // ============================================================================
9393 9452 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9394 9453 // array for an instance of the superklass. Set a hidden internal cache on a
9395 9454 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9396 9455 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9397 9456 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9398 9457 match(Set index (PartialSubtypeCheck sub super));
9399 9458 effect( KILL pcc, KILL o7 );
9400 9459 ins_cost(DEFAULT_COST*10);
9401 9460 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9402 9461 ins_encode( enc_PartialSubtypeCheck() );
9403 9462 ins_pipe(partial_subtype_check_pipe);
9404 9463 %}
9405 9464
9406 9465 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9407 9466 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9408 9467 effect( KILL idx, KILL o7 );
9409 9468 ins_cost(DEFAULT_COST*10);
9410 9469 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9411 9470 ins_encode( enc_PartialSubtypeCheck() );
9412 9471 ins_pipe(partial_subtype_check_pipe);
9413 9472 %}
9414 9473
9415 9474
9416 9475 // ============================================================================
9417 9476 // inlined locking and unlocking
9418 9477
9419 9478 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9420 9479 match(Set pcc (FastLock object box));
9421 9480
9422 9481 effect(KILL scratch, TEMP scratch2);
9423 9482 ins_cost(100);
9424 9483
9425 9484 size(4*112); // conservative overestimation ...
9426 9485 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9427 9486 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9428 9487 ins_pipe(long_memory_op);
9429 9488 %}
9430 9489
9431 9490
9432 9491 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9433 9492 match(Set pcc (FastUnlock object box));
9434 9493 effect(KILL scratch, TEMP scratch2);
9435 9494 ins_cost(100);
9436 9495
9437 9496 size(4*120); // conservative overestimation ...
9438 9497 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9439 9498 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9440 9499 ins_pipe(long_memory_op);
9441 9500 %}
9442 9501
9443 9502 // Count and Base registers are fixed because the allocator cannot
9444 9503 // kill unknown registers. The encodings are generic.
9445 9504 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9446 9505 match(Set dummy (ClearArray cnt base));
9447 9506 effect(TEMP temp, KILL ccr);
9448 9507 ins_cost(300);
9449 9508 format %{ "MOV $cnt,$temp\n"
9450 9509 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9451 9510 " BRge loop\t\t! Clearing loop\n"
9452 9511 " STX G0,[$base+$temp]\t! delay slot" %}
9453 9512 ins_encode( enc_Clear_Array(cnt, base, temp) );
9454 9513 ins_pipe(long_memory_op);
9455 9514 %}
9456 9515
9457 9516 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9458 9517 o7RegI tmp, flagsReg ccr) %{
9459 9518 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9460 9519 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9461 9520 ins_cost(300);
9462 9521 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9463 9522 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9464 9523 ins_pipe(long_memory_op);
9465 9524 %}
9466 9525
9467 9526 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9468 9527 o7RegI tmp, flagsReg ccr) %{
9469 9528 match(Set result (StrEquals (Binary str1 str2) cnt));
9470 9529 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9471 9530 ins_cost(300);
9472 9531 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9473 9532 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9474 9533 ins_pipe(long_memory_op);
9475 9534 %}
9476 9535
9477 9536 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9478 9537 o7RegI tmp2, flagsReg ccr) %{
9479 9538 match(Set result (AryEq ary1 ary2));
9480 9539 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9481 9540 ins_cost(300);
9482 9541 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9483 9542 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9484 9543 ins_pipe(long_memory_op);
9485 9544 %}
9486 9545
9487 9546
9488 9547 //---------- Zeros Count Instructions ------------------------------------------
9489 9548
9490 9549 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9491 9550 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9492 9551 match(Set dst (CountLeadingZerosI src));
9493 9552 effect(TEMP dst, TEMP tmp, KILL cr);
9494 9553
9495 9554 // x |= (x >> 1);
9496 9555 // x |= (x >> 2);
9497 9556 // x |= (x >> 4);
9498 9557 // x |= (x >> 8);
9499 9558 // x |= (x >> 16);
9500 9559 // return (WORDBITS - popc(x));
9501 9560 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9502 9561 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9503 9562 "OR $dst,$tmp,$dst\n\t"
9504 9563 "SRL $dst,2,$tmp\n\t"
9505 9564 "OR $dst,$tmp,$dst\n\t"
9506 9565 "SRL $dst,4,$tmp\n\t"
9507 9566 "OR $dst,$tmp,$dst\n\t"
9508 9567 "SRL $dst,8,$tmp\n\t"
9509 9568 "OR $dst,$tmp,$dst\n\t"
9510 9569 "SRL $dst,16,$tmp\n\t"
9511 9570 "OR $dst,$tmp,$dst\n\t"
9512 9571 "POPC $dst,$dst\n\t"
9513 9572 "MOV 32,$tmp\n\t"
9514 9573 "SUB $tmp,$dst,$dst" %}
9515 9574 ins_encode %{
9516 9575 Register Rdst = $dst$$Register;
9517 9576 Register Rsrc = $src$$Register;
9518 9577 Register Rtmp = $tmp$$Register;
9519 9578 __ srl(Rsrc, 1, Rtmp);
9520 9579 __ srl(Rsrc, 0, Rdst);
9521 9580 __ or3(Rdst, Rtmp, Rdst);
9522 9581 __ srl(Rdst, 2, Rtmp);
9523 9582 __ or3(Rdst, Rtmp, Rdst);
9524 9583 __ srl(Rdst, 4, Rtmp);
9525 9584 __ or3(Rdst, Rtmp, Rdst);
9526 9585 __ srl(Rdst, 8, Rtmp);
9527 9586 __ or3(Rdst, Rtmp, Rdst);
9528 9587 __ srl(Rdst, 16, Rtmp);
9529 9588 __ or3(Rdst, Rtmp, Rdst);
9530 9589 __ popc(Rdst, Rdst);
9531 9590 __ mov(BitsPerInt, Rtmp);
9532 9591 __ sub(Rtmp, Rdst, Rdst);
9533 9592 %}
9534 9593 ins_pipe(ialu_reg);
9535 9594 %}
9536 9595
9537 9596 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9538 9597 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9539 9598 match(Set dst (CountLeadingZerosL src));
9540 9599 effect(TEMP dst, TEMP tmp, KILL cr);
9541 9600
9542 9601 // x |= (x >> 1);
9543 9602 // x |= (x >> 2);
9544 9603 // x |= (x >> 4);
9545 9604 // x |= (x >> 8);
9546 9605 // x |= (x >> 16);
9547 9606 // x |= (x >> 32);
9548 9607 // return (WORDBITS - popc(x));
9549 9608 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9550 9609 "OR $src,$tmp,$dst\n\t"
9551 9610 "SRLX $dst,2,$tmp\n\t"
9552 9611 "OR $dst,$tmp,$dst\n\t"
9553 9612 "SRLX $dst,4,$tmp\n\t"
9554 9613 "OR $dst,$tmp,$dst\n\t"
9555 9614 "SRLX $dst,8,$tmp\n\t"
9556 9615 "OR $dst,$tmp,$dst\n\t"
9557 9616 "SRLX $dst,16,$tmp\n\t"
9558 9617 "OR $dst,$tmp,$dst\n\t"
9559 9618 "SRLX $dst,32,$tmp\n\t"
9560 9619 "OR $dst,$tmp,$dst\n\t"
9561 9620 "POPC $dst,$dst\n\t"
9562 9621 "MOV 64,$tmp\n\t"
9563 9622 "SUB $tmp,$dst,$dst" %}
9564 9623 ins_encode %{
9565 9624 Register Rdst = $dst$$Register;
9566 9625 Register Rsrc = $src$$Register;
9567 9626 Register Rtmp = $tmp$$Register;
9568 9627 __ srlx(Rsrc, 1, Rtmp);
9569 9628 __ or3( Rsrc, Rtmp, Rdst);
9570 9629 __ srlx(Rdst, 2, Rtmp);
9571 9630 __ or3( Rdst, Rtmp, Rdst);
9572 9631 __ srlx(Rdst, 4, Rtmp);
9573 9632 __ or3( Rdst, Rtmp, Rdst);
9574 9633 __ srlx(Rdst, 8, Rtmp);
9575 9634 __ or3( Rdst, Rtmp, Rdst);
9576 9635 __ srlx(Rdst, 16, Rtmp);
9577 9636 __ or3( Rdst, Rtmp, Rdst);
9578 9637 __ srlx(Rdst, 32, Rtmp);
9579 9638 __ or3( Rdst, Rtmp, Rdst);
9580 9639 __ popc(Rdst, Rdst);
9581 9640 __ mov(BitsPerLong, Rtmp);
9582 9641 __ sub(Rtmp, Rdst, Rdst);
9583 9642 %}
9584 9643 ins_pipe(ialu_reg);
9585 9644 %}
9586 9645
9587 9646 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9588 9647 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9589 9648 match(Set dst (CountTrailingZerosI src));
9590 9649 effect(TEMP dst, KILL cr);
9591 9650
9592 9651 // return popc(~x & (x - 1));
9593 9652 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9594 9653 "ANDN $dst,$src,$dst\n\t"
9595 9654 "SRL $dst,R_G0,$dst\n\t"
9596 9655 "POPC $dst,$dst" %}
9597 9656 ins_encode %{
9598 9657 Register Rdst = $dst$$Register;
9599 9658 Register Rsrc = $src$$Register;
9600 9659 __ sub(Rsrc, 1, Rdst);
9601 9660 __ andn(Rdst, Rsrc, Rdst);
9602 9661 __ srl(Rdst, G0, Rdst);
9603 9662 __ popc(Rdst, Rdst);
9604 9663 %}
9605 9664 ins_pipe(ialu_reg);
9606 9665 %}
9607 9666
9608 9667 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9609 9668 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9610 9669 match(Set dst (CountTrailingZerosL src));
9611 9670 effect(TEMP dst, KILL cr);
9612 9671
9613 9672 // return popc(~x & (x - 1));
9614 9673 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9615 9674 "ANDN $dst,$src,$dst\n\t"
9616 9675 "POPC $dst,$dst" %}
9617 9676 ins_encode %{
9618 9677 Register Rdst = $dst$$Register;
9619 9678 Register Rsrc = $src$$Register;
9620 9679 __ sub(Rsrc, 1, Rdst);
9621 9680 __ andn(Rdst, Rsrc, Rdst);
9622 9681 __ popc(Rdst, Rdst);
9623 9682 %}
9624 9683 ins_pipe(ialu_reg);
9625 9684 %}
9626 9685
9627 9686
9628 9687 //---------- Population Count Instructions -------------------------------------
9629 9688
9630 9689 instruct popCountI(iRegI dst, iRegI src) %{
9631 9690 predicate(UsePopCountInstruction);
9632 9691 match(Set dst (PopCountI src));
9633 9692
9634 9693 format %{ "POPC $src, $dst" %}
9635 9694 ins_encode %{
9636 9695 __ popc($src$$Register, $dst$$Register);
9637 9696 %}
9638 9697 ins_pipe(ialu_reg);
9639 9698 %}
9640 9699
9641 9700 // Note: Long.bitCount(long) returns an int.
9642 9701 instruct popCountL(iRegI dst, iRegL src) %{
9643 9702 predicate(UsePopCountInstruction);
9644 9703 match(Set dst (PopCountL src));
9645 9704
9646 9705 format %{ "POPC $src, $dst" %}
9647 9706 ins_encode %{
9648 9707 __ popc($src$$Register, $dst$$Register);
9649 9708 %}
9650 9709 ins_pipe(ialu_reg);
9651 9710 %}
9652 9711
9653 9712
9654 9713 // ============================================================================
9655 9714 //------------Bytes reverse--------------------------------------------------
9656 9715
9657 9716 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9658 9717 match(Set dst (ReverseBytesI src));
9659 9718
9660 9719 // Op cost is artificially doubled to make sure that load or store
9661 9720 // instructions are preferred over this one which requires a spill
9662 9721 // onto a stack slot.
9663 9722 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9664 9723 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9665 9724
9666 9725 ins_encode %{
9667 9726 __ set($src$$disp + STACK_BIAS, O7);
9668 9727 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9669 9728 %}
9670 9729 ins_pipe( iload_mem );
9671 9730 %}
9672 9731
9673 9732 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9674 9733 match(Set dst (ReverseBytesL src));
9675 9734
9676 9735 // Op cost is artificially doubled to make sure that load or store
9677 9736 // instructions are preferred over this one which requires a spill
9678 9737 // onto a stack slot.
9679 9738 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9680 9739 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9681 9740
9682 9741 ins_encode %{
9683 9742 __ set($src$$disp + STACK_BIAS, O7);
9684 9743 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9685 9744 %}
9686 9745 ins_pipe( iload_mem );
9687 9746 %}
9688 9747
9689 9748 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9690 9749 match(Set dst (ReverseBytesUS src));
9691 9750
9692 9751 // Op cost is artificially doubled to make sure that load or store
9693 9752 // instructions are preferred over this one which requires a spill
9694 9753 // onto a stack slot.
9695 9754 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9696 9755 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9697 9756
9698 9757 ins_encode %{
9699 9758 // the value was spilled as an int so bias the load
9700 9759 __ set($src$$disp + STACK_BIAS + 2, O7);
9701 9760 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9702 9761 %}
9703 9762 ins_pipe( iload_mem );
9704 9763 %}
9705 9764
9706 9765 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9707 9766 match(Set dst (ReverseBytesS src));
9708 9767
9709 9768 // Op cost is artificially doubled to make sure that load or store
9710 9769 // instructions are preferred over this one which requires a spill
9711 9770 // onto a stack slot.
9712 9771 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9713 9772 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9714 9773
9715 9774 ins_encode %{
9716 9775 // the value was spilled as an int so bias the load
9717 9776 __ set($src$$disp + STACK_BIAS + 2, O7);
9718 9777 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9719 9778 %}
9720 9779 ins_pipe( iload_mem );
9721 9780 %}
9722 9781
9723 9782 // Load Integer reversed byte order
9724 9783 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9725 9784 match(Set dst (ReverseBytesI (LoadI src)));
9726 9785
9727 9786 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9728 9787 size(4);
9729 9788 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9730 9789
9731 9790 ins_encode %{
9732 9791 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9733 9792 %}
9734 9793 ins_pipe(iload_mem);
9735 9794 %}
9736 9795
9737 9796 // Load Long - aligned and reversed
9738 9797 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9739 9798 match(Set dst (ReverseBytesL (LoadL src)));
9740 9799
9741 9800 ins_cost(MEMORY_REF_COST);
9742 9801 size(4);
9743 9802 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9744 9803
9745 9804 ins_encode %{
9746 9805 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9747 9806 %}
9748 9807 ins_pipe(iload_mem);
9749 9808 %}
9750 9809
9751 9810 // Load unsigned short / char reversed byte order
9752 9811 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9753 9812 match(Set dst (ReverseBytesUS (LoadUS src)));
9754 9813
9755 9814 ins_cost(MEMORY_REF_COST);
9756 9815 size(4);
9757 9816 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9758 9817
9759 9818 ins_encode %{
9760 9819 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9761 9820 %}
9762 9821 ins_pipe(iload_mem);
9763 9822 %}
9764 9823
9765 9824 // Load short reversed byte order
9766 9825 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
9767 9826 match(Set dst (ReverseBytesS (LoadS src)));
9768 9827
9769 9828 ins_cost(MEMORY_REF_COST);
9770 9829 size(4);
9771 9830 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9772 9831
9773 9832 ins_encode %{
9774 9833 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9775 9834 %}
9776 9835 ins_pipe(iload_mem);
9777 9836 %}
9778 9837
9779 9838 // Store Integer reversed byte order
9780 9839 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
9781 9840 match(Set dst (StoreI dst (ReverseBytesI src)));
9782 9841
9783 9842 ins_cost(MEMORY_REF_COST);
9784 9843 size(4);
9785 9844 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9786 9845
9787 9846 ins_encode %{
9788 9847 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9789 9848 %}
9790 9849 ins_pipe(istore_mem_reg);
9791 9850 %}
9792 9851
9793 9852 // Store Long reversed byte order
9794 9853 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
9795 9854 match(Set dst (StoreL dst (ReverseBytesL src)));
9796 9855
9797 9856 ins_cost(MEMORY_REF_COST);
9798 9857 size(4);
9799 9858 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9800 9859
9801 9860 ins_encode %{
9802 9861 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9803 9862 %}
9804 9863 ins_pipe(istore_mem_reg);
9805 9864 %}
9806 9865
9807 9866 // Store unsighed short/char reversed byte order
9808 9867 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
9809 9868 match(Set dst (StoreC dst (ReverseBytesUS src)));
9810 9869
9811 9870 ins_cost(MEMORY_REF_COST);
9812 9871 size(4);
9813 9872 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9814 9873
9815 9874 ins_encode %{
9816 9875 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9817 9876 %}
9818 9877 ins_pipe(istore_mem_reg);
9819 9878 %}
9820 9879
9821 9880 // Store short reversed byte order
9822 9881 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
9823 9882 match(Set dst (StoreC dst (ReverseBytesS src)));
9824 9883
9825 9884 ins_cost(MEMORY_REF_COST);
9826 9885 size(4);
9827 9886 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9828 9887
9829 9888 ins_encode %{
9830 9889 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9831 9890 %}
9832 9891 ins_pipe(istore_mem_reg);
9833 9892 %}
9834 9893
9835 9894 //----------PEEPHOLE RULES-----------------------------------------------------
9836 9895 // These must follow all instruction definitions as they use the names
9837 9896 // defined in the instructions definitions.
9838 9897 //
9839 9898 // peepmatch ( root_instr_name [preceding_instruction]* );
9840 9899 //
9841 9900 // peepconstraint %{
9842 9901 // (instruction_number.operand_name relational_op instruction_number.operand_name
9843 9902 // [, ...] );
9844 9903 // // instruction numbers are zero-based using left to right order in peepmatch
9845 9904 //
9846 9905 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9847 9906 // // provide an instruction_number.operand_name for each operand that appears
9848 9907 // // in the replacement instruction's match rule
9849 9908 //
9850 9909 // ---------VM FLAGS---------------------------------------------------------
9851 9910 //
9852 9911 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9853 9912 //
9854 9913 // Each peephole rule is given an identifying number starting with zero and
9855 9914 // increasing by one in the order seen by the parser. An individual peephole
9856 9915 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9857 9916 // on the command-line.
9858 9917 //
9859 9918 // ---------CURRENT LIMITATIONS----------------------------------------------
9860 9919 //
9861 9920 // Only match adjacent instructions in same basic block
9862 9921 // Only equality constraints
9863 9922 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9864 9923 // Only one replacement instruction
9865 9924 //
9866 9925 // ---------EXAMPLE----------------------------------------------------------
9867 9926 //
9868 9927 // // pertinent parts of existing instructions in architecture description
9869 9928 // instruct movI(eRegI dst, eRegI src) %{
9870 9929 // match(Set dst (CopyI src));
9871 9930 // %}
9872 9931 //
9873 9932 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9874 9933 // match(Set dst (AddI dst src));
9875 9934 // effect(KILL cr);
9876 9935 // %}
9877 9936 //
9878 9937 // // Change (inc mov) to lea
9879 9938 // peephole %{
9880 9939 // // increment preceeded by register-register move
9881 9940 // peepmatch ( incI_eReg movI );
9882 9941 // // require that the destination register of the increment
9883 9942 // // match the destination register of the move
9884 9943 // peepconstraint ( 0.dst == 1.dst );
9885 9944 // // construct a replacement instruction that sets
9886 9945 // // the destination to ( move's source register + one )
9887 9946 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9888 9947 // %}
9889 9948 //
9890 9949
9891 9950 // // Change load of spilled value to only a spill
9892 9951 // instruct storeI(memory mem, eRegI src) %{
9893 9952 // match(Set mem (StoreI mem src));
9894 9953 // %}
9895 9954 //
9896 9955 // instruct loadI(eRegI dst, memory mem) %{
9897 9956 // match(Set dst (LoadI mem));
9898 9957 // %}
9899 9958 //
9900 9959 // peephole %{
9901 9960 // peepmatch ( loadI storeI );
9902 9961 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9903 9962 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9904 9963 // %}
9905 9964
9906 9965 //----------SMARTSPILL RULES---------------------------------------------------
9907 9966 // These must follow all instruction definitions as they use the names
9908 9967 // defined in the instructions definitions.
9909 9968 //
9910 9969 // SPARC will probably not have any of these rules due to RISC instruction set.
9911 9970
9912 9971 //----------PIPELINE-----------------------------------------------------------
9913 9972 // Rules which define the behavior of the target architectures pipeline.
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