1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_assembler_x86.cpp.incl"
27
28 // Implementation of AddressLiteral
29
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
31 _is_lval = false;
32 _target = target;
33 switch (rtype) {
34 case relocInfo::oop_type:
35 // Oops are a special case. Normally they would be their own section
36 // but in cases like icBuffer they are literals in the code stream that
37 // we don't have a section for. We use none so that we get a literal address
38 // which is always patchable.
39 break;
40 case relocInfo::external_word_type:
41 _rspec = external_word_Relocation::spec(target);
42 break;
43 case relocInfo::internal_word_type:
44 _rspec = internal_word_Relocation::spec(target);
45 break;
46 case relocInfo::opt_virtual_call_type:
47 _rspec = opt_virtual_call_Relocation::spec();
48 break;
49 case relocInfo::static_call_type:
50 _rspec = static_call_Relocation::spec();
51 break;
52 case relocInfo::runtime_call_type:
53 _rspec = runtime_call_Relocation::spec();
54 break;
55 case relocInfo::poll_type:
56 case relocInfo::poll_return_type:
57 _rspec = Relocation::spec_simple(rtype);
58 break;
59 case relocInfo::none:
60 break;
61 default:
62 ShouldNotReachHere();
63 break;
64 }
65 }
66
67 // Implementation of Address
68
69 #ifdef _LP64
70
71 Address Address::make_array(ArrayAddress adr) {
72 // Not implementable on 64bit machines
73 // Should have been handled higher up the call chain.
74 ShouldNotReachHere();
75 return Address();
76 }
77
78 // exceedingly dangerous constructor
79 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
80 _base = noreg;
81 _index = noreg;
82 _scale = no_scale;
83 _disp = disp;
84 switch (rtype) {
85 case relocInfo::external_word_type:
86 _rspec = external_word_Relocation::spec(loc);
87 break;
88 case relocInfo::internal_word_type:
89 _rspec = internal_word_Relocation::spec(loc);
90 break;
91 case relocInfo::runtime_call_type:
92 // HMM
93 _rspec = runtime_call_Relocation::spec();
94 break;
95 case relocInfo::poll_type:
96 case relocInfo::poll_return_type:
97 _rspec = Relocation::spec_simple(rtype);
98 break;
99 case relocInfo::none:
100 break;
101 default:
102 ShouldNotReachHere();
103 }
104 }
105 #else // LP64
106
107 Address Address::make_array(ArrayAddress adr) {
108 AddressLiteral base = adr.base();
109 Address index = adr.index();
110 assert(index._disp == 0, "must not have disp"); // maybe it can?
111 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
112 array._rspec = base._rspec;
113 return array;
114 }
115
116 // exceedingly dangerous constructor
117 Address::Address(address loc, RelocationHolder spec) {
118 _base = noreg;
119 _index = noreg;
120 _scale = no_scale;
121 _disp = (intptr_t) loc;
122 _rspec = spec;
123 }
124
125 #endif // _LP64
126
127
128
129 // Convert the raw encoding form into the form expected by the constructor for
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert
131 // that to noreg for the Address constructor.
132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
133 RelocationHolder rspec;
134 if (disp_is_oop) {
135 rspec = Relocation::spec_simple(relocInfo::oop_type);
136 }
137 bool valid_index = index != rsp->encoding();
138 if (valid_index) {
139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
140 madr._rspec = rspec;
141 return madr;
142 } else {
143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
144 madr._rspec = rspec;
145 return madr;
146 }
147 }
148
149 // Implementation of Assembler
150
151 int AbstractAssembler::code_fill_byte() {
152 return (u_char)'\xF4'; // hlt
153 }
154
155 // make this go away someday
156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
157 if (rtype == relocInfo::none)
158 emit_long(data);
159 else emit_data(data, Relocation::spec_simple(rtype), format);
160 }
161
162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
163 assert(imm_operand == 0, "default format must be immediate in this file");
164 assert(inst_mark() != NULL, "must be inside InstructionMark");
165 if (rspec.type() != relocInfo::none) {
166 #ifdef ASSERT
167 check_relocation(rspec, format);
168 #endif
169 // Do not use AbstractAssembler::relocate, which is not intended for
170 // embedded words. Instead, relocate to the enclosing instruction.
171
172 // hack. call32 is too wide for mask so use disp32
173 if (format == call32_operand)
174 code_section()->relocate(inst_mark(), rspec, disp32_operand);
175 else
176 code_section()->relocate(inst_mark(), rspec, format);
177 }
178 emit_long(data);
179 }
180
181 static int encode(Register r) {
182 int enc = r->encoding();
183 if (enc >= 8) {
184 enc -= 8;
185 }
186 return enc;
187 }
188
189 static int encode(XMMRegister r) {
190 int enc = r->encoding();
191 if (enc >= 8) {
192 enc -= 8;
193 }
194 return enc;
195 }
196
197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
198 assert(dst->has_byte_register(), "must have byte register");
199 assert(isByte(op1) && isByte(op2), "wrong opcode");
200 assert(isByte(imm8), "not a byte");
201 assert((op1 & 0x01) == 0, "should be 8bit operation");
202 emit_byte(op1);
203 emit_byte(op2 | encode(dst));
204 emit_byte(imm8);
205 }
206
207
208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
209 assert(isByte(op1) && isByte(op2), "wrong opcode");
210 assert((op1 & 0x01) == 1, "should be 32bit operation");
211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
212 if (is8bit(imm32)) {
213 emit_byte(op1 | 0x02); // set sign bit
214 emit_byte(op2 | encode(dst));
215 emit_byte(imm32 & 0xFF);
216 } else {
217 emit_byte(op1);
218 emit_byte(op2 | encode(dst));
219 emit_long(imm32);
220 }
221 }
222
223 // immediate-to-memory forms
224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
225 assert((op1 & 0x01) == 1, "should be 32bit operation");
226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
227 if (is8bit(imm32)) {
228 emit_byte(op1 | 0x02); // set sign bit
229 emit_operand(rm, adr, 1);
230 emit_byte(imm32 & 0xFF);
231 } else {
232 emit_byte(op1);
233 emit_operand(rm, adr, 4);
234 emit_long(imm32);
235 }
236 }
237
238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
239 LP64_ONLY(ShouldNotReachHere());
240 assert(isByte(op1) && isByte(op2), "wrong opcode");
241 assert((op1 & 0x01) == 1, "should be 32bit operation");
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
243 InstructionMark im(this);
244 emit_byte(op1);
245 emit_byte(op2 | encode(dst));
246 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
247 }
248
249
250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
251 assert(isByte(op1) && isByte(op2), "wrong opcode");
252 emit_byte(op1);
253 emit_byte(op2 | encode(dst) << 3 | encode(src));
254 }
255
256
257 void Assembler::emit_operand(Register reg, Register base, Register index,
258 Address::ScaleFactor scale, int disp,
259 RelocationHolder const& rspec,
260 int rip_relative_correction) {
261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
262
263 // Encode the registers as needed in the fields they are used in
264
265 int regenc = encode(reg) << 3;
266 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
267 int baseenc = base->is_valid() ? encode(base) : 0;
268
269 if (base->is_valid()) {
270 if (index->is_valid()) {
271 assert(scale != Address::no_scale, "inconsistent address");
272 // [base + index*scale + disp]
273 if (disp == 0 && rtype == relocInfo::none &&
274 base != rbp LP64_ONLY(&& base != r13)) {
275 // [base + index*scale]
276 // [00 reg 100][ss index base]
277 assert(index != rsp, "illegal addressing mode");
278 emit_byte(0x04 | regenc);
279 emit_byte(scale << 6 | indexenc | baseenc);
280 } else if (is8bit(disp) && rtype == relocInfo::none) {
281 // [base + index*scale + imm8]
282 // [01 reg 100][ss index base] imm8
283 assert(index != rsp, "illegal addressing mode");
284 emit_byte(0x44 | regenc);
285 emit_byte(scale << 6 | indexenc | baseenc);
286 emit_byte(disp & 0xFF);
287 } else {
288 // [base + index*scale + disp32]
289 // [10 reg 100][ss index base] disp32
290 assert(index != rsp, "illegal addressing mode");
291 emit_byte(0x84 | regenc);
292 emit_byte(scale << 6 | indexenc | baseenc);
293 emit_data(disp, rspec, disp32_operand);
294 }
295 } else if (base == rsp LP64_ONLY(|| base == r12)) {
296 // [rsp + disp]
297 if (disp == 0 && rtype == relocInfo::none) {
298 // [rsp]
299 // [00 reg 100][00 100 100]
300 emit_byte(0x04 | regenc);
301 emit_byte(0x24);
302 } else if (is8bit(disp) && rtype == relocInfo::none) {
303 // [rsp + imm8]
304 // [01 reg 100][00 100 100] disp8
305 emit_byte(0x44 | regenc);
306 emit_byte(0x24);
307 emit_byte(disp & 0xFF);
308 } else {
309 // [rsp + imm32]
310 // [10 reg 100][00 100 100] disp32
311 emit_byte(0x84 | regenc);
312 emit_byte(0x24);
313 emit_data(disp, rspec, disp32_operand);
314 }
315 } else {
316 // [base + disp]
317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
318 if (disp == 0 && rtype == relocInfo::none &&
319 base != rbp LP64_ONLY(&& base != r13)) {
320 // [base]
321 // [00 reg base]
322 emit_byte(0x00 | regenc | baseenc);
323 } else if (is8bit(disp) && rtype == relocInfo::none) {
324 // [base + disp8]
325 // [01 reg base] disp8
326 emit_byte(0x40 | regenc | baseenc);
327 emit_byte(disp & 0xFF);
328 } else {
329 // [base + disp32]
330 // [10 reg base] disp32
331 emit_byte(0x80 | regenc | baseenc);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 }
335 } else {
336 if (index->is_valid()) {
337 assert(scale != Address::no_scale, "inconsistent address");
338 // [index*scale + disp]
339 // [00 reg 100][ss index 101] disp32
340 assert(index != rsp, "illegal addressing mode");
341 emit_byte(0x04 | regenc);
342 emit_byte(scale << 6 | indexenc | 0x05);
343 emit_data(disp, rspec, disp32_operand);
344 } else if (rtype != relocInfo::none ) {
345 // [disp] (64bit) RIP-RELATIVE (32bit) abs
346 // [00 000 101] disp32
347
348 emit_byte(0x05 | regenc);
349 // Note that the RIP-rel. correction applies to the generated
350 // disp field, but _not_ to the target address in the rspec.
351
352 // disp was created by converting the target address minus the pc
353 // at the start of the instruction. That needs more correction here.
354 // intptr_t disp = target - next_ip;
355 assert(inst_mark() != NULL, "must be inside InstructionMark");
356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
357 int64_t adjusted = disp;
358 // Do rip-rel adjustment for 64bit
359 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
360 assert(is_simm32(adjusted),
361 "must be 32bit offset (RIP relative address)");
362 emit_data((int32_t) adjusted, rspec, disp32_operand);
363
364 } else {
365 // 32bit never did this, did everything as the rip-rel/disp code above
366 // [disp] ABSOLUTE
367 // [00 reg 100][00 100 101] disp32
368 emit_byte(0x04 | regenc);
369 emit_byte(0x25);
370 emit_data(disp, rspec, disp32_operand);
371 }
372 }
373 }
374
375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
376 Address::ScaleFactor scale, int disp,
377 RelocationHolder const& rspec) {
378 emit_operand((Register)reg, base, index, scale, disp, rspec);
379 }
380
381 // Secret local extension to Assembler::WhichOperand:
382 #define end_pc_operand (_WhichOperand_limit)
383
384 address Assembler::locate_operand(address inst, WhichOperand which) {
385 // Decode the given instruction, and return the address of
386 // an embedded 32-bit operand word.
387
388 // If "which" is disp32_operand, selects the displacement portion
389 // of an effective address specifier.
390 // If "which" is imm64_operand, selects the trailing immediate constant.
391 // If "which" is call32_operand, selects the displacement of a call or jump.
392 // Caller is responsible for ensuring that there is such an operand,
393 // and that it is 32/64 bits wide.
394
395 // If "which" is end_pc_operand, find the end of the instruction.
396
397 address ip = inst;
398 bool is_64bit = false;
399
400 debug_only(bool has_disp32 = false);
401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
402
403 again_after_prefix:
404 switch (0xFF & *ip++) {
405
406 // These convenience macros generate groups of "case" labels for the switch.
407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
409 case (x)+4: case (x)+5: case (x)+6: case (x)+7
410 #define REP16(x) REP8((x)+0): \
411 case REP8((x)+8)
412
413 case CS_segment:
414 case SS_segment:
415 case DS_segment:
416 case ES_segment:
417 case FS_segment:
418 case GS_segment:
419 // Seems dubious
420 LP64_ONLY(assert(false, "shouldn't have that prefix"));
421 assert(ip == inst+1, "only one prefix allowed");
422 goto again_after_prefix;
423
424 case 0x67:
425 case REX:
426 case REX_B:
427 case REX_X:
428 case REX_XB:
429 case REX_R:
430 case REX_RB:
431 case REX_RX:
432 case REX_RXB:
433 NOT_LP64(assert(false, "64bit prefixes"));
434 goto again_after_prefix;
435
436 case REX_W:
437 case REX_WB:
438 case REX_WX:
439 case REX_WXB:
440 case REX_WR:
441 case REX_WRB:
442 case REX_WRX:
443 case REX_WRXB:
444 NOT_LP64(assert(false, "64bit prefixes"));
445 is_64bit = true;
446 goto again_after_prefix;
447
448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
449 case 0x88: // movb a, r
450 case 0x89: // movl a, r
451 case 0x8A: // movb r, a
452 case 0x8B: // movl r, a
453 case 0x8F: // popl a
454 debug_only(has_disp32 = true);
455 break;
456
457 case 0x68: // pushq #32
458 if (which == end_pc_operand) {
459 return ip + 4;
460 }
461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
462 return ip; // not produced by emit_operand
463
464 case 0x66: // movw ... (size prefix)
465 again_after_size_prefix2:
466 switch (0xFF & *ip++) {
467 case REX:
468 case REX_B:
469 case REX_X:
470 case REX_XB:
471 case REX_R:
472 case REX_RB:
473 case REX_RX:
474 case REX_RXB:
475 case REX_W:
476 case REX_WB:
477 case REX_WX:
478 case REX_WXB:
479 case REX_WR:
480 case REX_WRB:
481 case REX_WRX:
482 case REX_WRXB:
483 NOT_LP64(assert(false, "64bit prefix found"));
484 goto again_after_size_prefix2;
485 case 0x8B: // movw r, a
486 case 0x89: // movw a, r
487 debug_only(has_disp32 = true);
488 break;
489 case 0xC7: // movw a, #16
490 debug_only(has_disp32 = true);
491 tail_size = 2; // the imm16
492 break;
493 case 0x0F: // several SSE/SSE2 variants
494 ip--; // reparse the 0x0F
495 goto again_after_prefix;
496 default:
497 ShouldNotReachHere();
498 }
499 break;
500
501 case REP8(0xB8): // movl/q r, #32/#64(oop?)
502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
503 // these asserts are somewhat nonsensical
504 #ifndef _LP64
505 assert(which == imm_operand || which == disp32_operand, "");
506 #else
507 assert((which == call32_operand || which == imm_operand) && is_64bit ||
508 which == narrow_oop_operand && !is_64bit, "");
509 #endif // _LP64
510 return ip;
511
512 case 0x69: // imul r, a, #32
513 case 0xC7: // movl a, #32(oop?)
514 tail_size = 4;
515 debug_only(has_disp32 = true); // has both kinds of operands!
516 break;
517
518 case 0x0F: // movx..., etc.
519 switch (0xFF & *ip++) {
520 case 0x12: // movlps
521 case 0x28: // movaps
522 case 0x2E: // ucomiss
523 case 0x2F: // comiss
524 case 0x54: // andps
525 case 0x55: // andnps
526 case 0x56: // orps
527 case 0x57: // xorps
528 case 0x6E: // movd
529 case 0x7E: // movd
530 case 0xAE: // ldmxcsr a
531 // 64bit side says it these have both operands but that doesn't
532 // appear to be true
533 debug_only(has_disp32 = true);
534 break;
535
536 case 0xAD: // shrd r, a, %cl
537 case 0xAF: // imul r, a
538 case 0xBE: // movsbl r, a (movsxb)
539 case 0xBF: // movswl r, a (movsxw)
540 case 0xB6: // movzbl r, a (movzxb)
541 case 0xB7: // movzwl r, a (movzxw)
542 case REP16(0x40): // cmovl cc, r, a
543 case 0xB0: // cmpxchgb
544 case 0xB1: // cmpxchg
545 case 0xC1: // xaddl
546 case 0xC7: // cmpxchg8
547 case REP16(0x90): // setcc a
548 debug_only(has_disp32 = true);
549 // fall out of the switch to decode the address
550 break;
551
552 case 0xAC: // shrd r, a, #8
553 debug_only(has_disp32 = true);
554 tail_size = 1; // the imm8
555 break;
556
557 case REP16(0x80): // jcc rdisp32
558 if (which == end_pc_operand) return ip + 4;
559 assert(which == call32_operand, "jcc has no disp32 or imm");
560 return ip;
561 default:
562 ShouldNotReachHere();
563 }
564 break;
565
566 case 0x81: // addl a, #32; addl r, #32
567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
568 // on 32bit in the case of cmpl, the imm might be an oop
569 tail_size = 4;
570 debug_only(has_disp32 = true); // has both kinds of operands!
571 break;
572
573 case 0x83: // addl a, #8; addl r, #8
574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
575 debug_only(has_disp32 = true); // has both kinds of operands!
576 tail_size = 1;
577 break;
578
579 case 0x9B:
580 switch (0xFF & *ip++) {
581 case 0xD9: // fnstcw a
582 debug_only(has_disp32 = true);
583 break;
584 default:
585 ShouldNotReachHere();
586 }
587 break;
588
589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
590 case REP4(0x10): // adc...
591 case REP4(0x20): // and...
592 case REP4(0x30): // xor...
593 case REP4(0x08): // or...
594 case REP4(0x18): // sbb...
595 case REP4(0x28): // sub...
596 case 0xF7: // mull a
597 case 0x8D: // lea r, a
598 case 0x87: // xchg r, a
599 case REP4(0x38): // cmp...
600 case 0x85: // test r, a
601 debug_only(has_disp32 = true); // has both kinds of operands!
602 break;
603
604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
605 case 0xC6: // movb a, #8
606 case 0x80: // cmpb a, #8
607 case 0x6B: // imul r, a, #8
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 tail_size = 1; // the imm8
610 break;
611
612 case 0xE8: // call rdisp32
613 case 0xE9: // jmp rdisp32
614 if (which == end_pc_operand) return ip + 4;
615 assert(which == call32_operand, "call has no disp32 or imm");
616 return ip;
617
618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
621 case 0xDD: // fld_d a; fst_d a; fstp_d a
622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
623 case 0xDF: // fild_d a; fistp_d a
624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
627 debug_only(has_disp32 = true);
628 break;
629
630 case 0xF0: // Lock
631 assert(os::is_MP(), "only on MP");
632 goto again_after_prefix;
633
634 case 0xF3: // For SSE
635 case 0xF2: // For SSE2
636 switch (0xFF & *ip++) {
637 case REX:
638 case REX_B:
639 case REX_X:
640 case REX_XB:
641 case REX_R:
642 case REX_RB:
643 case REX_RX:
644 case REX_RXB:
645 case REX_W:
646 case REX_WB:
647 case REX_WX:
648 case REX_WXB:
649 case REX_WR:
650 case REX_WRB:
651 case REX_WRX:
652 case REX_WRXB:
653 NOT_LP64(assert(false, "found 64bit prefix"));
654 ip++;
655 default:
656 ip++;
657 }
658 debug_only(has_disp32 = true); // has both kinds of operands!
659 break;
660
661 default:
662 ShouldNotReachHere();
663
664 #undef REP8
665 #undef REP16
666 }
667
668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
669 #ifdef _LP64
670 assert(which != imm_operand, "instruction is not a movq reg, imm64");
671 #else
672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
674 #endif // LP64
675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
676
677 // parse the output of emit_operand
678 int op2 = 0xFF & *ip++;
679 int base = op2 & 0x07;
680 int op3 = -1;
681 const int b100 = 4;
682 const int b101 = 5;
683 if (base == b100 && (op2 >> 6) != 3) {
684 op3 = 0xFF & *ip++;
685 base = op3 & 0x07; // refetch the base
686 }
687 // now ip points at the disp (if any)
688
689 switch (op2 >> 6) {
690 case 0:
691 // [00 reg 100][ss index base]
692 // [00 reg 100][00 100 esp]
693 // [00 reg base]
694 // [00 reg 100][ss index 101][disp32]
695 // [00 reg 101] [disp32]
696
697 if (base == b101) {
698 if (which == disp32_operand)
699 return ip; // caller wants the disp32
700 ip += 4; // skip the disp32
701 }
702 break;
703
704 case 1:
705 // [01 reg 100][ss index base][disp8]
706 // [01 reg 100][00 100 esp][disp8]
707 // [01 reg base] [disp8]
708 ip += 1; // skip the disp8
709 break;
710
711 case 2:
712 // [10 reg 100][ss index base][disp32]
713 // [10 reg 100][00 100 esp][disp32]
714 // [10 reg base] [disp32]
715 if (which == disp32_operand)
716 return ip; // caller wants the disp32
717 ip += 4; // skip the disp32
718 break;
719
720 case 3:
721 // [11 reg base] (not a memory addressing mode)
722 break;
723 }
724
725 if (which == end_pc_operand) {
726 return ip + tail_size;
727 }
728
729 #ifdef _LP64
730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
731 #else
732 assert(which == imm_operand, "instruction has only an imm field");
733 #endif // LP64
734 return ip;
735 }
736
737 address Assembler::locate_next_instruction(address inst) {
738 // Secretly share code with locate_operand:
739 return locate_operand(inst, end_pc_operand);
740 }
741
742
743 #ifdef ASSERT
744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
745 address inst = inst_mark();
746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
747 address opnd;
748
749 Relocation* r = rspec.reloc();
750 if (r->type() == relocInfo::none) {
751 return;
752 } else if (r->is_call() || format == call32_operand) {
753 // assert(format == imm32_operand, "cannot specify a nonzero format");
754 opnd = locate_operand(inst, call32_operand);
755 } else if (r->is_data()) {
756 assert(format == imm_operand || format == disp32_operand
757 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
758 opnd = locate_operand(inst, (WhichOperand)format);
759 } else {
760 assert(format == imm_operand, "cannot specify a format");
761 return;
762 }
763 assert(opnd == pc(), "must put operand where relocs can find it");
764 }
765 #endif // ASSERT
766
767 void Assembler::emit_operand32(Register reg, Address adr) {
768 assert(reg->encoding() < 8, "no extended registers");
769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
771 adr._rspec);
772 }
773
774 void Assembler::emit_operand(Register reg, Address adr,
775 int rip_relative_correction) {
776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
777 adr._rspec,
778 rip_relative_correction);
779 }
780
781 void Assembler::emit_operand(XMMRegister reg, Address adr) {
782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
783 adr._rspec);
784 }
785
786 // MMX operations
787 void Assembler::emit_operand(MMXRegister reg, Address adr) {
788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
790 }
791
792 // work around gcc (3.2.1-7a) bug
793 void Assembler::emit_operand(Address adr, MMXRegister reg) {
794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
796 }
797
798
799 void Assembler::emit_farith(int b1, int b2, int i) {
800 assert(isByte(b1) && isByte(b2), "wrong opcode");
801 assert(0 <= i && i < 8, "illegal stack offset");
802 emit_byte(b1);
803 emit_byte(b2 + i);
804 }
805
806
807 // Now the Assembler instruction (identical for 32/64 bits)
808
809 void Assembler::adcl(Register dst, int32_t imm32) {
810 prefix(dst);
811 emit_arith(0x81, 0xD0, dst, imm32);
812 }
813
814 void Assembler::adcl(Register dst, Address src) {
815 InstructionMark im(this);
816 prefix(src, dst);
817 emit_byte(0x13);
818 emit_operand(dst, src);
819 }
820
821 void Assembler::adcl(Register dst, Register src) {
822 (void) prefix_and_encode(dst->encoding(), src->encoding());
823 emit_arith(0x13, 0xC0, dst, src);
824 }
825
826 void Assembler::addl(Address dst, int32_t imm32) {
827 InstructionMark im(this);
828 prefix(dst);
829 emit_arith_operand(0x81, rax, dst, imm32);
830 }
831
832 void Assembler::addl(Address dst, Register src) {
833 InstructionMark im(this);
834 prefix(dst, src);
835 emit_byte(0x01);
836 emit_operand(src, dst);
837 }
838
839 void Assembler::addl(Register dst, int32_t imm32) {
840 prefix(dst);
841 emit_arith(0x81, 0xC0, dst, imm32);
842 }
843
844 void Assembler::addl(Register dst, Address src) {
845 InstructionMark im(this);
846 prefix(src, dst);
847 emit_byte(0x03);
848 emit_operand(dst, src);
849 }
850
851 void Assembler::addl(Register dst, Register src) {
852 (void) prefix_and_encode(dst->encoding(), src->encoding());
853 emit_arith(0x03, 0xC0, dst, src);
854 }
855
856 void Assembler::addr_nop_4() {
857 // 4 bytes: NOP DWORD PTR [EAX+0]
858 emit_byte(0x0F);
859 emit_byte(0x1F);
860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
861 emit_byte(0); // 8-bits offset (1 byte)
862 }
863
864 void Assembler::addr_nop_5() {
865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
866 emit_byte(0x0F);
867 emit_byte(0x1F);
868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
870 emit_byte(0); // 8-bits offset (1 byte)
871 }
872
873 void Assembler::addr_nop_7() {
874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
875 emit_byte(0x0F);
876 emit_byte(0x1F);
877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
878 emit_long(0); // 32-bits offset (4 bytes)
879 }
880
881 void Assembler::addr_nop_8() {
882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
883 emit_byte(0x0F);
884 emit_byte(0x1F);
885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
887 emit_long(0); // 32-bits offset (4 bytes)
888 }
889
890 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
892 emit_byte(0xF2);
893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
894 emit_byte(0x0F);
895 emit_byte(0x58);
896 emit_byte(0xC0 | encode);
897 }
898
899 void Assembler::addsd(XMMRegister dst, Address src) {
900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
901 InstructionMark im(this);
902 emit_byte(0xF2);
903 prefix(src, dst);
904 emit_byte(0x0F);
905 emit_byte(0x58);
906 emit_operand(dst, src);
907 }
908
909 void Assembler::addss(XMMRegister dst, XMMRegister src) {
910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
911 emit_byte(0xF3);
912 int encode = prefix_and_encode(dst->encoding(), src->encoding());
913 emit_byte(0x0F);
914 emit_byte(0x58);
915 emit_byte(0xC0 | encode);
916 }
917
918 void Assembler::addss(XMMRegister dst, Address src) {
919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
920 InstructionMark im(this);
921 emit_byte(0xF3);
922 prefix(src, dst);
923 emit_byte(0x0F);
924 emit_byte(0x58);
925 emit_operand(dst, src);
926 }
927
928 void Assembler::andl(Register dst, int32_t imm32) {
929 prefix(dst);
930 emit_arith(0x81, 0xE0, dst, imm32);
931 }
932
933 void Assembler::andl(Register dst, Address src) {
934 InstructionMark im(this);
935 prefix(src, dst);
936 emit_byte(0x23);
937 emit_operand(dst, src);
938 }
939
940 void Assembler::andl(Register dst, Register src) {
941 (void) prefix_and_encode(dst->encoding(), src->encoding());
942 emit_arith(0x23, 0xC0, dst, src);
943 }
944
945 void Assembler::andpd(XMMRegister dst, Address src) {
946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
947 InstructionMark im(this);
948 emit_byte(0x66);
949 prefix(src, dst);
950 emit_byte(0x0F);
951 emit_byte(0x54);
952 emit_operand(dst, src);
953 }
954
955 void Assembler::bsfl(Register dst, Register src) {
956 int encode = prefix_and_encode(dst->encoding(), src->encoding());
957 emit_byte(0x0F);
958 emit_byte(0xBC);
959 emit_byte(0xC0 | encode);
960 }
961
962 void Assembler::bsrl(Register dst, Register src) {
963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
964 int encode = prefix_and_encode(dst->encoding(), src->encoding());
965 emit_byte(0x0F);
966 emit_byte(0xBD);
967 emit_byte(0xC0 | encode);
968 }
969
970 void Assembler::bswapl(Register reg) { // bswap
971 int encode = prefix_and_encode(reg->encoding());
972 emit_byte(0x0F);
973 emit_byte(0xC8 | encode);
974 }
975
976 void Assembler::call(Label& L, relocInfo::relocType rtype) {
977 // suspect disp32 is always good
978 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
979
980 if (L.is_bound()) {
981 const int long_size = 5;
982 int offs = (int)( target(L) - pc() );
983 assert(offs <= 0, "assembler error");
984 InstructionMark im(this);
985 // 1110 1000 #32-bit disp
986 emit_byte(0xE8);
987 emit_data(offs - long_size, rtype, operand);
988 } else {
989 InstructionMark im(this);
990 // 1110 1000 #32-bit disp
991 L.add_patch_at(code(), locator());
992
993 emit_byte(0xE8);
994 emit_data(int(0), rtype, operand);
995 }
996 }
997
998 void Assembler::call(Register dst) {
999 // This was originally using a 32bit register encoding
1000 // and surely we want 64bit!
1001 // this is a 32bit encoding but in 64bit mode the default
1002 // operand size is 64bit so there is no need for the
1003 // wide prefix. So prefix only happens if we use the
1004 // new registers. Much like push/pop.
1005 int x = offset();
1006 // this may be true but dbx disassembles it as if it
1007 // were 32bits...
1008 // int encode = prefix_and_encode(dst->encoding());
1009 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
1010 int encode = prefixq_and_encode(dst->encoding());
1011
1012 emit_byte(0xFF);
1013 emit_byte(0xD0 | encode);
1014 }
1015
1016
1017 void Assembler::call(Address adr) {
1018 InstructionMark im(this);
1019 prefix(adr);
1020 emit_byte(0xFF);
1021 emit_operand(rdx, adr);
1022 }
1023
1024 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1025 assert(entry != NULL, "call most probably wrong");
1026 InstructionMark im(this);
1027 emit_byte(0xE8);
1028 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1029 assert(is_simm32(disp), "must be 32bit offset (call2)");
1030 // Technically, should use call32_operand, but this format is
1031 // implied by the fact that we're emitting a call instruction.
1032
1033 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1034 emit_data((int) disp, rspec, operand);
1035 }
1036
1037 void Assembler::cdql() {
1038 emit_byte(0x99);
1039 }
1040
1041 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1042 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1043 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1044 emit_byte(0x0F);
1045 emit_byte(0x40 | cc);
1046 emit_byte(0xC0 | encode);
1047 }
1048
1049
1050 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1051 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1052 prefix(src, dst);
1053 emit_byte(0x0F);
1054 emit_byte(0x40 | cc);
1055 emit_operand(dst, src);
1056 }
1057
1058 void Assembler::cmpb(Address dst, int imm8) {
1059 InstructionMark im(this);
1060 prefix(dst);
1061 emit_byte(0x80);
1062 emit_operand(rdi, dst, 1);
1063 emit_byte(imm8);
1064 }
1065
1066 void Assembler::cmpl(Address dst, int32_t imm32) {
1067 InstructionMark im(this);
1068 prefix(dst);
1069 emit_byte(0x81);
1070 emit_operand(rdi, dst, 4);
1071 emit_long(imm32);
1072 }
1073
1074 void Assembler::cmpl(Register dst, int32_t imm32) {
1075 prefix(dst);
1076 emit_arith(0x81, 0xF8, dst, imm32);
1077 }
1078
1079 void Assembler::cmpl(Register dst, Register src) {
1080 (void) prefix_and_encode(dst->encoding(), src->encoding());
1081 emit_arith(0x3B, 0xC0, dst, src);
1082 }
1083
1084
1085 void Assembler::cmpl(Register dst, Address src) {
1086 InstructionMark im(this);
1087 prefix(src, dst);
1088 emit_byte(0x3B);
1089 emit_operand(dst, src);
1090 }
1091
1092 void Assembler::cmpw(Address dst, int imm16) {
1093 InstructionMark im(this);
1094 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1095 emit_byte(0x66);
1096 emit_byte(0x81);
1097 emit_operand(rdi, dst, 2);
1098 emit_word(imm16);
1099 }
1100
1101 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1102 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1103 // The ZF is set if the compared values were equal, and cleared otherwise.
1104 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1105 if (Atomics & 2) {
1106 // caveat: no instructionmark, so this isn't relocatable.
1107 // Emit a synthetic, non-atomic, CAS equivalent.
1108 // Beware. The synthetic form sets all ICCs, not just ZF.
1109 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1110 cmpl(rax, adr);
1111 movl(rax, adr);
1112 if (reg != rax) {
1113 Label L ;
1114 jcc(Assembler::notEqual, L);
1115 movl(adr, reg);
1116 bind(L);
1117 }
1118 } else {
1119 InstructionMark im(this);
1120 prefix(adr, reg);
1121 emit_byte(0x0F);
1122 emit_byte(0xB1);
1123 emit_operand(reg, adr);
1124 }
1125 }
1126
1127 void Assembler::comisd(XMMRegister dst, Address src) {
1128 // NOTE: dbx seems to decode this as comiss even though the
1129 // 0x66 is there. Strangly ucomisd comes out correct
1130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1131 emit_byte(0x66);
1132 comiss(dst, src);
1133 }
1134
1135 void Assembler::comiss(XMMRegister dst, Address src) {
1136 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1137
1138 InstructionMark im(this);
1139 prefix(src, dst);
1140 emit_byte(0x0F);
1141 emit_byte(0x2F);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1147 emit_byte(0xF3);
1148 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1149 emit_byte(0x0F);
1150 emit_byte(0xE6);
1151 emit_byte(0xC0 | encode);
1152 }
1153
1154 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1156 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1157 emit_byte(0x0F);
1158 emit_byte(0x5B);
1159 emit_byte(0xC0 | encode);
1160 }
1161
1162 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1164 emit_byte(0xF2);
1165 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1166 emit_byte(0x0F);
1167 emit_byte(0x5A);
1168 emit_byte(0xC0 | encode);
1169 }
1170
1171 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1173 emit_byte(0xF2);
1174 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1175 emit_byte(0x0F);
1176 emit_byte(0x2A);
1177 emit_byte(0xC0 | encode);
1178 }
1179
1180 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1181 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1182 emit_byte(0xF3);
1183 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1184 emit_byte(0x0F);
1185 emit_byte(0x2A);
1186 emit_byte(0xC0 | encode);
1187 }
1188
1189 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1191 emit_byte(0xF3);
1192 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1193 emit_byte(0x0F);
1194 emit_byte(0x5A);
1195 emit_byte(0xC0 | encode);
1196 }
1197
1198 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1200 emit_byte(0xF2);
1201 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1202 emit_byte(0x0F);
1203 emit_byte(0x2C);
1204 emit_byte(0xC0 | encode);
1205 }
1206
1207 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1208 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1209 emit_byte(0xF3);
1210 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1211 emit_byte(0x0F);
1212 emit_byte(0x2C);
1213 emit_byte(0xC0 | encode);
1214 }
1215
1216 void Assembler::decl(Address dst) {
1217 // Don't use it directly. Use MacroAssembler::decrement() instead.
1218 InstructionMark im(this);
1219 prefix(dst);
1220 emit_byte(0xFF);
1221 emit_operand(rcx, dst);
1222 }
1223
1224 void Assembler::divsd(XMMRegister dst, Address src) {
1225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1226 InstructionMark im(this);
1227 emit_byte(0xF2);
1228 prefix(src, dst);
1229 emit_byte(0x0F);
1230 emit_byte(0x5E);
1231 emit_operand(dst, src);
1232 }
1233
1234 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1236 emit_byte(0xF2);
1237 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1238 emit_byte(0x0F);
1239 emit_byte(0x5E);
1240 emit_byte(0xC0 | encode);
1241 }
1242
1243 void Assembler::divss(XMMRegister dst, Address src) {
1244 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1245 InstructionMark im(this);
1246 emit_byte(0xF3);
1247 prefix(src, dst);
1248 emit_byte(0x0F);
1249 emit_byte(0x5E);
1250 emit_operand(dst, src);
1251 }
1252
1253 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1254 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1255 emit_byte(0xF3);
1256 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1257 emit_byte(0x0F);
1258 emit_byte(0x5E);
1259 emit_byte(0xC0 | encode);
1260 }
1261
1262 void Assembler::emms() {
1263 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1264 emit_byte(0x0F);
1265 emit_byte(0x77);
1266 }
1267
1268 void Assembler::hlt() {
1269 emit_byte(0xF4);
1270 }
1271
1272 void Assembler::idivl(Register src) {
1273 int encode = prefix_and_encode(src->encoding());
1274 emit_byte(0xF7);
1275 emit_byte(0xF8 | encode);
1276 }
1277
1278 void Assembler::divl(Register src) { // Unsigned
1279 int encode = prefix_and_encode(src->encoding());
1280 emit_byte(0xF7);
1281 emit_byte(0xF0 | encode);
1282 }
1283
1284 void Assembler::imull(Register dst, Register src) {
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1286 emit_byte(0x0F);
1287 emit_byte(0xAF);
1288 emit_byte(0xC0 | encode);
1289 }
1290
1291
1292 void Assembler::imull(Register dst, Register src, int value) {
1293 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1294 if (is8bit(value)) {
1295 emit_byte(0x6B);
1296 emit_byte(0xC0 | encode);
1297 emit_byte(value & 0xFF);
1298 } else {
1299 emit_byte(0x69);
1300 emit_byte(0xC0 | encode);
1301 emit_long(value);
1302 }
1303 }
1304
1305 void Assembler::incl(Address dst) {
1306 // Don't use it directly. Use MacroAssembler::increment() instead.
1307 InstructionMark im(this);
1308 prefix(dst);
1309 emit_byte(0xFF);
1310 emit_operand(rax, dst);
1311 }
1312
1313 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1314 InstructionMark im(this);
1315 relocate(rtype);
1316 assert((0 <= cc) && (cc < 16), "illegal cc");
1317 if (L.is_bound()) {
1318 address dst = target(L);
1319 assert(dst != NULL, "jcc most probably wrong");
1320
1321 const int short_size = 2;
1322 const int long_size = 6;
1323 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1324 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1325 // 0111 tttn #8-bit disp
1326 emit_byte(0x70 | cc);
1327 emit_byte((offs - short_size) & 0xFF);
1328 } else {
1329 // 0000 1111 1000 tttn #32-bit disp
1330 assert(is_simm32(offs - long_size),
1331 "must be 32bit offset (call4)");
1332 emit_byte(0x0F);
1333 emit_byte(0x80 | cc);
1334 emit_long(offs - long_size);
1335 }
1336 } else {
1337 // Note: could eliminate cond. jumps to this jump if condition
1338 // is the same however, seems to be rather unlikely case.
1339 // Note: use jccb() if label to be bound is very close to get
1340 // an 8-bit displacement
1341 L.add_patch_at(code(), locator());
1342 emit_byte(0x0F);
1343 emit_byte(0x80 | cc);
1344 emit_long(0);
1345 }
1346 }
1347
1348 void Assembler::jccb(Condition cc, Label& L) {
1349 if (L.is_bound()) {
1350 const int short_size = 2;
1351 address entry = target(L);
1352 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1353 "Dispacement too large for a short jmp");
1354 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1355 // 0111 tttn #8-bit disp
1356 emit_byte(0x70 | cc);
1357 emit_byte((offs - short_size) & 0xFF);
1358 } else {
1359 InstructionMark im(this);
1360 L.add_patch_at(code(), locator());
1361 emit_byte(0x70 | cc);
1362 emit_byte(0);
1363 }
1364 }
1365
1366 void Assembler::jmp(Address adr) {
1367 InstructionMark im(this);
1368 prefix(adr);
1369 emit_byte(0xFF);
1370 emit_operand(rsp, adr);
1371 }
1372
1373 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1374 if (L.is_bound()) {
1375 address entry = target(L);
1376 assert(entry != NULL, "jmp most probably wrong");
1377 InstructionMark im(this);
1378 const int short_size = 2;
1379 const int long_size = 5;
1380 intptr_t offs = entry - _code_pos;
1381 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1382 emit_byte(0xEB);
1383 emit_byte((offs - short_size) & 0xFF);
1384 } else {
1385 emit_byte(0xE9);
1386 emit_long(offs - long_size);
1387 }
1388 } else {
1389 // By default, forward jumps are always 32-bit displacements, since
1390 // we can't yet know where the label will be bound. If you're sure that
1391 // the forward jump will not run beyond 256 bytes, use jmpb to
1392 // force an 8-bit displacement.
1393 InstructionMark im(this);
1394 relocate(rtype);
1395 L.add_patch_at(code(), locator());
1396 emit_byte(0xE9);
1397 emit_long(0);
1398 }
1399 }
1400
1401 void Assembler::jmp(Register entry) {
1402 int encode = prefix_and_encode(entry->encoding());
1403 emit_byte(0xFF);
1404 emit_byte(0xE0 | encode);
1405 }
1406
1407 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1408 InstructionMark im(this);
1409 emit_byte(0xE9);
1410 assert(dest != NULL, "must have a target");
1411 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1412 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1413 emit_data(disp, rspec.reloc(), call32_operand);
1414 }
1415
1416 void Assembler::jmpb(Label& L) {
1417 if (L.is_bound()) {
1418 const int short_size = 2;
1419 address entry = target(L);
1420 assert(is8bit((entry - _code_pos) + short_size),
1421 "Dispacement too large for a short jmp");
1422 assert(entry != NULL, "jmp most probably wrong");
1423 intptr_t offs = entry - _code_pos;
1424 emit_byte(0xEB);
1425 emit_byte((offs - short_size) & 0xFF);
1426 } else {
1427 InstructionMark im(this);
1428 L.add_patch_at(code(), locator());
1429 emit_byte(0xEB);
1430 emit_byte(0);
1431 }
1432 }
1433
1434 void Assembler::ldmxcsr( Address src) {
1435 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1436 InstructionMark im(this);
1437 prefix(src);
1438 emit_byte(0x0F);
1439 emit_byte(0xAE);
1440 emit_operand(as_Register(2), src);
1441 }
1442
1443 void Assembler::leal(Register dst, Address src) {
1444 InstructionMark im(this);
1445 #ifdef _LP64
1446 emit_byte(0x67); // addr32
1447 prefix(src, dst);
1448 #endif // LP64
1449 emit_byte(0x8D);
1450 emit_operand(dst, src);
1451 }
1452
1453 void Assembler::lock() {
1454 if (Atomics & 1) {
1455 // Emit either nothing, a NOP, or a NOP: prefix
1456 emit_byte(0x90) ;
1457 } else {
1458 emit_byte(0xF0);
1459 }
1460 }
1461
1462 void Assembler::lzcntl(Register dst, Register src) {
1463 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1464 emit_byte(0xF3);
1465 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1466 emit_byte(0x0F);
1467 emit_byte(0xBD);
1468 emit_byte(0xC0 | encode);
1469 }
1470
1471 // Emit mfence instruction
1472 void Assembler::mfence() {
1473 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1474 emit_byte( 0x0F );
1475 emit_byte( 0xAE );
1476 emit_byte( 0xF0 );
1477 }
1478
1479 void Assembler::mov(Register dst, Register src) {
1480 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1481 }
1482
1483 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1485 int dstenc = dst->encoding();
1486 int srcenc = src->encoding();
1487 emit_byte(0x66);
1488 if (dstenc < 8) {
1489 if (srcenc >= 8) {
1490 prefix(REX_B);
1491 srcenc -= 8;
1492 }
1493 } else {
1494 if (srcenc < 8) {
1495 prefix(REX_R);
1496 } else {
1497 prefix(REX_RB);
1498 srcenc -= 8;
1499 }
1500 dstenc -= 8;
1501 }
1502 emit_byte(0x0F);
1503 emit_byte(0x28);
1504 emit_byte(0xC0 | dstenc << 3 | srcenc);
1505 }
1506
1507 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1508 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1509 int dstenc = dst->encoding();
1510 int srcenc = src->encoding();
1511 if (dstenc < 8) {
1512 if (srcenc >= 8) {
1513 prefix(REX_B);
1514 srcenc -= 8;
1515 }
1516 } else {
1517 if (srcenc < 8) {
1518 prefix(REX_R);
1519 } else {
1520 prefix(REX_RB);
1521 srcenc -= 8;
1522 }
1523 dstenc -= 8;
1524 }
1525 emit_byte(0x0F);
1526 emit_byte(0x28);
1527 emit_byte(0xC0 | dstenc << 3 | srcenc);
1528 }
1529
1530 void Assembler::movb(Register dst, Address src) {
1531 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1532 InstructionMark im(this);
1533 prefix(src, dst, true);
1534 emit_byte(0x8A);
1535 emit_operand(dst, src);
1536 }
1537
1538
1539 void Assembler::movb(Address dst, int imm8) {
1540 InstructionMark im(this);
1541 prefix(dst);
1542 emit_byte(0xC6);
1543 emit_operand(rax, dst, 1);
1544 emit_byte(imm8);
1545 }
1546
1547
1548 void Assembler::movb(Address dst, Register src) {
1549 assert(src->has_byte_register(), "must have byte register");
1550 InstructionMark im(this);
1551 prefix(dst, src, true);
1552 emit_byte(0x88);
1553 emit_operand(src, dst);
1554 }
1555
1556 void Assembler::movdl(XMMRegister dst, Register src) {
1557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1558 emit_byte(0x66);
1559 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1560 emit_byte(0x0F);
1561 emit_byte(0x6E);
1562 emit_byte(0xC0 | encode);
1563 }
1564
1565 void Assembler::movdl(Register dst, XMMRegister src) {
1566 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1567 emit_byte(0x66);
1568 // swap src/dst to get correct prefix
1569 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1570 emit_byte(0x0F);
1571 emit_byte(0x7E);
1572 emit_byte(0xC0 | encode);
1573 }
1574
1575 void Assembler::movdqa(XMMRegister dst, Address src) {
1576 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1577 InstructionMark im(this);
1578 emit_byte(0x66);
1579 prefix(src, dst);
1580 emit_byte(0x0F);
1581 emit_byte(0x6F);
1582 emit_operand(dst, src);
1583 }
1584
1585 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1587 emit_byte(0x66);
1588 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1589 emit_byte(0x0F);
1590 emit_byte(0x6F);
1591 emit_byte(0xC0 | encode);
1592 }
1593
1594 void Assembler::movdqa(Address dst, XMMRegister src) {
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 InstructionMark im(this);
1597 emit_byte(0x66);
1598 prefix(dst, src);
1599 emit_byte(0x0F);
1600 emit_byte(0x7F);
1601 emit_operand(src, dst);
1602 }
1603
1604 void Assembler::movdqu(XMMRegister dst, Address src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionMark im(this);
1607 emit_byte(0xF3);
1608 prefix(src, dst);
1609 emit_byte(0x0F);
1610 emit_byte(0x6F);
1611 emit_operand(dst, src);
1612 }
1613
1614 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1616 emit_byte(0xF3);
1617 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1618 emit_byte(0x0F);
1619 emit_byte(0x6F);
1620 emit_byte(0xC0 | encode);
1621 }
1622
1623 void Assembler::movdqu(Address dst, XMMRegister src) {
1624 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1625 InstructionMark im(this);
1626 emit_byte(0xF3);
1627 prefix(dst, src);
1628 emit_byte(0x0F);
1629 emit_byte(0x7F);
1630 emit_operand(src, dst);
1631 }
1632
1633 // Uses zero extension on 64bit
1634
1635 void Assembler::movl(Register dst, int32_t imm32) {
1636 int encode = prefix_and_encode(dst->encoding());
1637 emit_byte(0xB8 | encode);
1638 emit_long(imm32);
1639 }
1640
1641 void Assembler::movl(Register dst, Register src) {
1642 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1643 emit_byte(0x8B);
1644 emit_byte(0xC0 | encode);
1645 }
1646
1647 void Assembler::movl(Register dst, Address src) {
1648 InstructionMark im(this);
1649 prefix(src, dst);
1650 emit_byte(0x8B);
1651 emit_operand(dst, src);
1652 }
1653
1654 void Assembler::movl(Address dst, int32_t imm32) {
1655 InstructionMark im(this);
1656 prefix(dst);
1657 emit_byte(0xC7);
1658 emit_operand(rax, dst, 4);
1659 emit_long(imm32);
1660 }
1661
1662 void Assembler::movl(Address dst, Register src) {
1663 InstructionMark im(this);
1664 prefix(dst, src);
1665 emit_byte(0x89);
1666 emit_operand(src, dst);
1667 }
1668
1669 // New cpus require to use movsd and movss to avoid partial register stall
1670 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1671 // The selection is done in MacroAssembler::movdbl() and movflt().
1672 void Assembler::movlpd(XMMRegister dst, Address src) {
1673 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1674 InstructionMark im(this);
1675 emit_byte(0x66);
1676 prefix(src, dst);
1677 emit_byte(0x0F);
1678 emit_byte(0x12);
1679 emit_operand(dst, src);
1680 }
1681
1682 void Assembler::movq( MMXRegister dst, Address src ) {
1683 assert( VM_Version::supports_mmx(), "" );
1684 emit_byte(0x0F);
1685 emit_byte(0x6F);
1686 emit_operand(dst, src);
1687 }
1688
1689 void Assembler::movq( Address dst, MMXRegister src ) {
1690 assert( VM_Version::supports_mmx(), "" );
1691 emit_byte(0x0F);
1692 emit_byte(0x7F);
1693 // workaround gcc (3.2.1-7a) bug
1694 // In that version of gcc with only an emit_operand(MMX, Address)
1695 // gcc will tail jump and try and reverse the parameters completely
1696 // obliterating dst in the process. By having a version available
1697 // that doesn't need to swap the args at the tail jump the bug is
1698 // avoided.
1699 emit_operand(dst, src);
1700 }
1701
1702 void Assembler::movq(XMMRegister dst, Address src) {
1703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1704 InstructionMark im(this);
1705 emit_byte(0xF3);
1706 prefix(src, dst);
1707 emit_byte(0x0F);
1708 emit_byte(0x7E);
1709 emit_operand(dst, src);
1710 }
1711
1712 void Assembler::movq(Address dst, XMMRegister src) {
1713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1714 InstructionMark im(this);
1715 emit_byte(0x66);
1716 prefix(dst, src);
1717 emit_byte(0x0F);
1718 emit_byte(0xD6);
1719 emit_operand(src, dst);
1720 }
1721
1722 void Assembler::movsbl(Register dst, Address src) { // movsxb
1723 InstructionMark im(this);
1724 prefix(src, dst);
1725 emit_byte(0x0F);
1726 emit_byte(0xBE);
1727 emit_operand(dst, src);
1728 }
1729
1730 void Assembler::movsbl(Register dst, Register src) { // movsxb
1731 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1732 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1733 emit_byte(0x0F);
1734 emit_byte(0xBE);
1735 emit_byte(0xC0 | encode);
1736 }
1737
1738 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1739 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1740 emit_byte(0xF2);
1741 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1742 emit_byte(0x0F);
1743 emit_byte(0x10);
1744 emit_byte(0xC0 | encode);
1745 }
1746
1747 void Assembler::movsd(XMMRegister dst, Address src) {
1748 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1749 InstructionMark im(this);
1750 emit_byte(0xF2);
1751 prefix(src, dst);
1752 emit_byte(0x0F);
1753 emit_byte(0x10);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::movsd(Address dst, XMMRegister src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionMark im(this);
1760 emit_byte(0xF2);
1761 prefix(dst, src);
1762 emit_byte(0x0F);
1763 emit_byte(0x11);
1764 emit_operand(src, dst);
1765 }
1766
1767 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1768 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1769 emit_byte(0xF3);
1770 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1771 emit_byte(0x0F);
1772 emit_byte(0x10);
1773 emit_byte(0xC0 | encode);
1774 }
1775
1776 void Assembler::movss(XMMRegister dst, Address src) {
1777 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1778 InstructionMark im(this);
1779 emit_byte(0xF3);
1780 prefix(src, dst);
1781 emit_byte(0x0F);
1782 emit_byte(0x10);
1783 emit_operand(dst, src);
1784 }
1785
1786 void Assembler::movss(Address dst, XMMRegister src) {
1787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1788 InstructionMark im(this);
1789 emit_byte(0xF3);
1790 prefix(dst, src);
1791 emit_byte(0x0F);
1792 emit_byte(0x11);
1793 emit_operand(src, dst);
1794 }
1795
1796 void Assembler::movswl(Register dst, Address src) { // movsxw
1797 InstructionMark im(this);
1798 prefix(src, dst);
1799 emit_byte(0x0F);
1800 emit_byte(0xBF);
1801 emit_operand(dst, src);
1802 }
1803
1804 void Assembler::movswl(Register dst, Register src) { // movsxw
1805 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1806 emit_byte(0x0F);
1807 emit_byte(0xBF);
1808 emit_byte(0xC0 | encode);
1809 }
1810
1811 void Assembler::movw(Address dst, int imm16) {
1812 InstructionMark im(this);
1813
1814 emit_byte(0x66); // switch to 16-bit mode
1815 prefix(dst);
1816 emit_byte(0xC7);
1817 emit_operand(rax, dst, 2);
1818 emit_word(imm16);
1819 }
1820
1821 void Assembler::movw(Register dst, Address src) {
1822 InstructionMark im(this);
1823 emit_byte(0x66);
1824 prefix(src, dst);
1825 emit_byte(0x8B);
1826 emit_operand(dst, src);
1827 }
1828
1829 void Assembler::movw(Address dst, Register src) {
1830 InstructionMark im(this);
1831 emit_byte(0x66);
1832 prefix(dst, src);
1833 emit_byte(0x89);
1834 emit_operand(src, dst);
1835 }
1836
1837 void Assembler::movzbl(Register dst, Address src) { // movzxb
1838 InstructionMark im(this);
1839 prefix(src, dst);
1840 emit_byte(0x0F);
1841 emit_byte(0xB6);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::movzbl(Register dst, Register src) { // movzxb
1846 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1847 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1848 emit_byte(0x0F);
1849 emit_byte(0xB6);
1850 emit_byte(0xC0 | encode);
1851 }
1852
1853 void Assembler::movzwl(Register dst, Address src) { // movzxw
1854 InstructionMark im(this);
1855 prefix(src, dst);
1856 emit_byte(0x0F);
1857 emit_byte(0xB7);
1858 emit_operand(dst, src);
1859 }
1860
1861 void Assembler::movzwl(Register dst, Register src) { // movzxw
1862 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1863 emit_byte(0x0F);
1864 emit_byte(0xB7);
1865 emit_byte(0xC0 | encode);
1866 }
1867
1868 void Assembler::mull(Address src) {
1869 InstructionMark im(this);
1870 prefix(src);
1871 emit_byte(0xF7);
1872 emit_operand(rsp, src);
1873 }
1874
1875 void Assembler::mull(Register src) {
1876 int encode = prefix_and_encode(src->encoding());
1877 emit_byte(0xF7);
1878 emit_byte(0xE0 | encode);
1879 }
1880
1881 void Assembler::mulsd(XMMRegister dst, Address src) {
1882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1883 InstructionMark im(this);
1884 emit_byte(0xF2);
1885 prefix(src, dst);
1886 emit_byte(0x0F);
1887 emit_byte(0x59);
1888 emit_operand(dst, src);
1889 }
1890
1891 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1892 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1893 emit_byte(0xF2);
1894 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1895 emit_byte(0x0F);
1896 emit_byte(0x59);
1897 emit_byte(0xC0 | encode);
1898 }
1899
1900 void Assembler::mulss(XMMRegister dst, Address src) {
1901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1902 InstructionMark im(this);
1903 emit_byte(0xF3);
1904 prefix(src, dst);
1905 emit_byte(0x0F);
1906 emit_byte(0x59);
1907 emit_operand(dst, src);
1908 }
1909
1910 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1912 emit_byte(0xF3);
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1914 emit_byte(0x0F);
1915 emit_byte(0x59);
1916 emit_byte(0xC0 | encode);
1917 }
1918
1919 void Assembler::negl(Register dst) {
1920 int encode = prefix_and_encode(dst->encoding());
1921 emit_byte(0xF7);
1922 emit_byte(0xD8 | encode);
1923 }
1924
1925 void Assembler::nop(int i) {
1926 #ifdef ASSERT
1927 assert(i > 0, " ");
1928 // The fancy nops aren't currently recognized by debuggers making it a
1929 // pain to disassemble code while debugging. If asserts are on clearly
1930 // speed is not an issue so simply use the single byte traditional nop
1931 // to do alignment.
1932
1933 for (; i > 0 ; i--) emit_byte(0x90);
1934 return;
1935
1936 #endif // ASSERT
1937
1938 if (UseAddressNop && VM_Version::is_intel()) {
1939 //
1940 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1941 // 1: 0x90
1942 // 2: 0x66 0x90
1943 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1944 // 4: 0x0F 0x1F 0x40 0x00
1945 // 5: 0x0F 0x1F 0x44 0x00 0x00
1946 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1947 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1948 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1949 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1950 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1951 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1952
1953 // The rest coding is Intel specific - don't use consecutive address nops
1954
1955 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1956 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1957 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1958 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1959
1960 while(i >= 15) {
1961 // For Intel don't generate consecutive addess nops (mix with regular nops)
1962 i -= 15;
1963 emit_byte(0x66); // size prefix
1964 emit_byte(0x66); // size prefix
1965 emit_byte(0x66); // size prefix
1966 addr_nop_8();
1967 emit_byte(0x66); // size prefix
1968 emit_byte(0x66); // size prefix
1969 emit_byte(0x66); // size prefix
1970 emit_byte(0x90); // nop
1971 }
1972 switch (i) {
1973 case 14:
1974 emit_byte(0x66); // size prefix
1975 case 13:
1976 emit_byte(0x66); // size prefix
1977 case 12:
1978 addr_nop_8();
1979 emit_byte(0x66); // size prefix
1980 emit_byte(0x66); // size prefix
1981 emit_byte(0x66); // size prefix
1982 emit_byte(0x90); // nop
1983 break;
1984 case 11:
1985 emit_byte(0x66); // size prefix
1986 case 10:
1987 emit_byte(0x66); // size prefix
1988 case 9:
1989 emit_byte(0x66); // size prefix
1990 case 8:
1991 addr_nop_8();
1992 break;
1993 case 7:
1994 addr_nop_7();
1995 break;
1996 case 6:
1997 emit_byte(0x66); // size prefix
1998 case 5:
1999 addr_nop_5();
2000 break;
2001 case 4:
2002 addr_nop_4();
2003 break;
2004 case 3:
2005 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2006 emit_byte(0x66); // size prefix
2007 case 2:
2008 emit_byte(0x66); // size prefix
2009 case 1:
2010 emit_byte(0x90); // nop
2011 break;
2012 default:
2013 assert(i == 0, " ");
2014 }
2015 return;
2016 }
2017 if (UseAddressNop && VM_Version::is_amd()) {
2018 //
2019 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2020 // 1: 0x90
2021 // 2: 0x66 0x90
2022 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2023 // 4: 0x0F 0x1F 0x40 0x00
2024 // 5: 0x0F 0x1F 0x44 0x00 0x00
2025 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2026 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2027 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2028 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2029 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2030 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2031
2032 // The rest coding is AMD specific - use consecutive address nops
2033
2034 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2035 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2036 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2037 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2038 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2039 // Size prefixes (0x66) are added for larger sizes
2040
2041 while(i >= 22) {
2042 i -= 11;
2043 emit_byte(0x66); // size prefix
2044 emit_byte(0x66); // size prefix
2045 emit_byte(0x66); // size prefix
2046 addr_nop_8();
2047 }
2048 // Generate first nop for size between 21-12
2049 switch (i) {
2050 case 21:
2051 i -= 1;
2052 emit_byte(0x66); // size prefix
2053 case 20:
2054 case 19:
2055 i -= 1;
2056 emit_byte(0x66); // size prefix
2057 case 18:
2058 case 17:
2059 i -= 1;
2060 emit_byte(0x66); // size prefix
2061 case 16:
2062 case 15:
2063 i -= 8;
2064 addr_nop_8();
2065 break;
2066 case 14:
2067 case 13:
2068 i -= 7;
2069 addr_nop_7();
2070 break;
2071 case 12:
2072 i -= 6;
2073 emit_byte(0x66); // size prefix
2074 addr_nop_5();
2075 break;
2076 default:
2077 assert(i < 12, " ");
2078 }
2079
2080 // Generate second nop for size between 11-1
2081 switch (i) {
2082 case 11:
2083 emit_byte(0x66); // size prefix
2084 case 10:
2085 emit_byte(0x66); // size prefix
2086 case 9:
2087 emit_byte(0x66); // size prefix
2088 case 8:
2089 addr_nop_8();
2090 break;
2091 case 7:
2092 addr_nop_7();
2093 break;
2094 case 6:
2095 emit_byte(0x66); // size prefix
2096 case 5:
2097 addr_nop_5();
2098 break;
2099 case 4:
2100 addr_nop_4();
2101 break;
2102 case 3:
2103 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2104 emit_byte(0x66); // size prefix
2105 case 2:
2106 emit_byte(0x66); // size prefix
2107 case 1:
2108 emit_byte(0x90); // nop
2109 break;
2110 default:
2111 assert(i == 0, " ");
2112 }
2113 return;
2114 }
2115
2116 // Using nops with size prefixes "0x66 0x90".
2117 // From AMD Optimization Guide:
2118 // 1: 0x90
2119 // 2: 0x66 0x90
2120 // 3: 0x66 0x66 0x90
2121 // 4: 0x66 0x66 0x66 0x90
2122 // 5: 0x66 0x66 0x90 0x66 0x90
2123 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2124 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2125 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2126 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2127 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2128 //
2129 while(i > 12) {
2130 i -= 4;
2131 emit_byte(0x66); // size prefix
2132 emit_byte(0x66);
2133 emit_byte(0x66);
2134 emit_byte(0x90); // nop
2135 }
2136 // 1 - 12 nops
2137 if(i > 8) {
2138 if(i > 9) {
2139 i -= 1;
2140 emit_byte(0x66);
2141 }
2142 i -= 3;
2143 emit_byte(0x66);
2144 emit_byte(0x66);
2145 emit_byte(0x90);
2146 }
2147 // 1 - 8 nops
2148 if(i > 4) {
2149 if(i > 6) {
2150 i -= 1;
2151 emit_byte(0x66);
2152 }
2153 i -= 3;
2154 emit_byte(0x66);
2155 emit_byte(0x66);
2156 emit_byte(0x90);
2157 }
2158 switch (i) {
2159 case 4:
2160 emit_byte(0x66);
2161 case 3:
2162 emit_byte(0x66);
2163 case 2:
2164 emit_byte(0x66);
2165 case 1:
2166 emit_byte(0x90);
2167 break;
2168 default:
2169 assert(i == 0, " ");
2170 }
2171 }
2172
2173 void Assembler::notl(Register dst) {
2174 int encode = prefix_and_encode(dst->encoding());
2175 emit_byte(0xF7);
2176 emit_byte(0xD0 | encode );
2177 }
2178
2179 void Assembler::orl(Address dst, int32_t imm32) {
2180 InstructionMark im(this);
2181 prefix(dst);
2182 emit_byte(0x81);
2183 emit_operand(rcx, dst, 4);
2184 emit_long(imm32);
2185 }
2186
2187 void Assembler::orl(Register dst, int32_t imm32) {
2188 prefix(dst);
2189 emit_arith(0x81, 0xC8, dst, imm32);
2190 }
2191
2192
2193 void Assembler::orl(Register dst, Address src) {
2194 InstructionMark im(this);
2195 prefix(src, dst);
2196 emit_byte(0x0B);
2197 emit_operand(dst, src);
2198 }
2199
2200
2201 void Assembler::orl(Register dst, Register src) {
2202 (void) prefix_and_encode(dst->encoding(), src->encoding());
2203 emit_arith(0x0B, 0xC0, dst, src);
2204 }
2205
2206 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2207 assert(VM_Version::supports_sse4_2(), "");
2208
2209 InstructionMark im(this);
2210 emit_byte(0x66);
2211 prefix(src, dst);
2212 emit_byte(0x0F);
2213 emit_byte(0x3A);
2214 emit_byte(0x61);
2215 emit_operand(dst, src);
2216 emit_byte(imm8);
2217 }
2218
2219 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2220 assert(VM_Version::supports_sse4_2(), "");
2221
2222 emit_byte(0x66);
2223 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2224 emit_byte(0x0F);
2225 emit_byte(0x3A);
2226 emit_byte(0x61);
2227 emit_byte(0xC0 | encode);
2228 emit_byte(imm8);
2229 }
2230
2231 // generic
2232 void Assembler::pop(Register dst) {
2233 int encode = prefix_and_encode(dst->encoding());
2234 emit_byte(0x58 | encode);
2235 }
2236
2237 void Assembler::popcntl(Register dst, Address src) {
2238 assert(VM_Version::supports_popcnt(), "must support");
2239 InstructionMark im(this);
2240 emit_byte(0xF3);
2241 prefix(src, dst);
2242 emit_byte(0x0F);
2243 emit_byte(0xB8);
2244 emit_operand(dst, src);
2245 }
2246
2247 void Assembler::popcntl(Register dst, Register src) {
2248 assert(VM_Version::supports_popcnt(), "must support");
2249 emit_byte(0xF3);
2250 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2251 emit_byte(0x0F);
2252 emit_byte(0xB8);
2253 emit_byte(0xC0 | encode);
2254 }
2255
2256 void Assembler::popf() {
2257 emit_byte(0x9D);
2258 }
2259
2260 #ifndef _LP64 // no 32bit push/pop on amd64
2261 void Assembler::popl(Address dst) {
2262 // NOTE: this will adjust stack by 8byte on 64bits
2263 InstructionMark im(this);
2264 prefix(dst);
2265 emit_byte(0x8F);
2266 emit_operand(rax, dst);
2267 }
2268 #endif
2269
2270 void Assembler::prefetch_prefix(Address src) {
2271 prefix(src);
2272 emit_byte(0x0F);
2273 }
2274
2275 void Assembler::prefetchnta(Address src) {
2276 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
2277 InstructionMark im(this);
2278 prefetch_prefix(src);
2279 emit_byte(0x18);
2280 emit_operand(rax, src); // 0, src
2281 }
2282
2283 void Assembler::prefetchr(Address src) {
2284 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2285 InstructionMark im(this);
2286 prefetch_prefix(src);
2287 emit_byte(0x0D);
2288 emit_operand(rax, src); // 0, src
2289 }
2290
2291 void Assembler::prefetcht0(Address src) {
2292 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2293 InstructionMark im(this);
2294 prefetch_prefix(src);
2295 emit_byte(0x18);
2296 emit_operand(rcx, src); // 1, src
2297 }
2298
2299 void Assembler::prefetcht1(Address src) {
2300 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2301 InstructionMark im(this);
2302 prefetch_prefix(src);
2303 emit_byte(0x18);
2304 emit_operand(rdx, src); // 2, src
2305 }
2306
2307 void Assembler::prefetcht2(Address src) {
2308 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2309 InstructionMark im(this);
2310 prefetch_prefix(src);
2311 emit_byte(0x18);
2312 emit_operand(rbx, src); // 3, src
2313 }
2314
2315 void Assembler::prefetchw(Address src) {
2316 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2317 InstructionMark im(this);
2318 prefetch_prefix(src);
2319 emit_byte(0x0D);
2320 emit_operand(rcx, src); // 1, src
2321 }
2322
2323 void Assembler::prefix(Prefix p) {
2324 a_byte(p);
2325 }
2326
2327 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2328 assert(isByte(mode), "invalid value");
2329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330
2331 emit_byte(0x66);
2332 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2333 emit_byte(0x0F);
2334 emit_byte(0x70);
2335 emit_byte(0xC0 | encode);
2336 emit_byte(mode & 0xFF);
2337
2338 }
2339
2340 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2341 assert(isByte(mode), "invalid value");
2342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2343
2344 InstructionMark im(this);
2345 emit_byte(0x66);
2346 prefix(src, dst);
2347 emit_byte(0x0F);
2348 emit_byte(0x70);
2349 emit_operand(dst, src);
2350 emit_byte(mode & 0xFF);
2351 }
2352
2353 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2354 assert(isByte(mode), "invalid value");
2355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2356
2357 emit_byte(0xF2);
2358 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2359 emit_byte(0x0F);
2360 emit_byte(0x70);
2361 emit_byte(0xC0 | encode);
2362 emit_byte(mode & 0xFF);
2363 }
2364
2365 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2366 assert(isByte(mode), "invalid value");
2367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2368
2369 InstructionMark im(this);
2370 emit_byte(0xF2);
2371 prefix(src, dst); // QQ new
2372 emit_byte(0x0F);
2373 emit_byte(0x70);
2374 emit_operand(dst, src);
2375 emit_byte(mode & 0xFF);
2376 }
2377
2378 void Assembler::psrlq(XMMRegister dst, int shift) {
2379 // HMM Table D-1 says sse2 or mmx
2380 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2381
2382 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2383 emit_byte(0x66);
2384 emit_byte(0x0F);
2385 emit_byte(0x73);
2386 emit_byte(0xC0 | encode);
2387 emit_byte(shift);
2388 }
2389
2390 void Assembler::ptest(XMMRegister dst, Address src) {
2391 assert(VM_Version::supports_sse4_1(), "");
2392
2393 InstructionMark im(this);
2394 emit_byte(0x66);
2395 prefix(src, dst);
2396 emit_byte(0x0F);
2397 emit_byte(0x38);
2398 emit_byte(0x17);
2399 emit_operand(dst, src);
2400 }
2401
2402 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2403 assert(VM_Version::supports_sse4_1(), "");
2404
2405 emit_byte(0x66);
2406 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2407 emit_byte(0x0F);
2408 emit_byte(0x38);
2409 emit_byte(0x17);
2410 emit_byte(0xC0 | encode);
2411 }
2412
2413 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2415 emit_byte(0x66);
2416 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2417 emit_byte(0x0F);
2418 emit_byte(0x60);
2419 emit_byte(0xC0 | encode);
2420 }
2421
2422 void Assembler::push(int32_t imm32) {
2423 // in 64bits we push 64bits onto the stack but only
2424 // take a 32bit immediate
2425 emit_byte(0x68);
2426 emit_long(imm32);
2427 }
2428
2429 void Assembler::push(Register src) {
2430 int encode = prefix_and_encode(src->encoding());
2431
2432 emit_byte(0x50 | encode);
2433 }
2434
2435 void Assembler::pushf() {
2436 emit_byte(0x9C);
2437 }
2438
2439 #ifndef _LP64 // no 32bit push/pop on amd64
2440 void Assembler::pushl(Address src) {
2441 // Note this will push 64bit on 64bit
2442 InstructionMark im(this);
2443 prefix(src);
2444 emit_byte(0xFF);
2445 emit_operand(rsi, src);
2446 }
2447 #endif
2448
2449 void Assembler::pxor(XMMRegister dst, Address src) {
2450 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2451 InstructionMark im(this);
2452 emit_byte(0x66);
2453 prefix(src, dst);
2454 emit_byte(0x0F);
2455 emit_byte(0xEF);
2456 emit_operand(dst, src);
2457 }
2458
2459 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2461 InstructionMark im(this);
2462 emit_byte(0x66);
2463 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2464 emit_byte(0x0F);
2465 emit_byte(0xEF);
2466 emit_byte(0xC0 | encode);
2467 }
2468
2469 void Assembler::rcll(Register dst, int imm8) {
2470 assert(isShiftCount(imm8), "illegal shift count");
2471 int encode = prefix_and_encode(dst->encoding());
2472 if (imm8 == 1) {
2473 emit_byte(0xD1);
2474 emit_byte(0xD0 | encode);
2475 } else {
2476 emit_byte(0xC1);
2477 emit_byte(0xD0 | encode);
2478 emit_byte(imm8);
2479 }
2480 }
2481
2482 // copies data from [esi] to [edi] using rcx pointer sized words
2483 // generic
2484 void Assembler::rep_mov() {
2485 emit_byte(0xF3);
2486 // MOVSQ
2487 LP64_ONLY(prefix(REX_W));
2488 emit_byte(0xA5);
2489 }
2490
2491 // sets rcx pointer sized words with rax, value at [edi]
2492 // generic
2493 void Assembler::rep_set() { // rep_set
2494 emit_byte(0xF3);
2495 // STOSQ
2496 LP64_ONLY(prefix(REX_W));
2497 emit_byte(0xAB);
2498 }
2499
2500 // scans rcx pointer sized words at [edi] for occurance of rax,
2501 // generic
2502 void Assembler::repne_scan() { // repne_scan
2503 emit_byte(0xF2);
2504 // SCASQ
2505 LP64_ONLY(prefix(REX_W));
2506 emit_byte(0xAF);
2507 }
2508
2509 #ifdef _LP64
2510 // scans rcx 4 byte words at [edi] for occurance of rax,
2511 // generic
2512 void Assembler::repne_scanl() { // repne_scan
2513 emit_byte(0xF2);
2514 // SCASL
2515 emit_byte(0xAF);
2516 }
2517 #endif
2518
2519 void Assembler::ret(int imm16) {
2520 if (imm16 == 0) {
2521 emit_byte(0xC3);
2522 } else {
2523 emit_byte(0xC2);
2524 emit_word(imm16);
2525 }
2526 }
2527
2528 void Assembler::sahf() {
2529 #ifdef _LP64
2530 // Not supported in 64bit mode
2531 ShouldNotReachHere();
2532 #endif
2533 emit_byte(0x9E);
2534 }
2535
2536 void Assembler::sarl(Register dst, int imm8) {
2537 int encode = prefix_and_encode(dst->encoding());
2538 assert(isShiftCount(imm8), "illegal shift count");
2539 if (imm8 == 1) {
2540 emit_byte(0xD1);
2541 emit_byte(0xF8 | encode);
2542 } else {
2543 emit_byte(0xC1);
2544 emit_byte(0xF8 | encode);
2545 emit_byte(imm8);
2546 }
2547 }
2548
2549 void Assembler::sarl(Register dst) {
2550 int encode = prefix_and_encode(dst->encoding());
2551 emit_byte(0xD3);
2552 emit_byte(0xF8 | encode);
2553 }
2554
2555 void Assembler::sbbl(Address dst, int32_t imm32) {
2556 InstructionMark im(this);
2557 prefix(dst);
2558 emit_arith_operand(0x81, rbx, dst, imm32);
2559 }
2560
2561 void Assembler::sbbl(Register dst, int32_t imm32) {
2562 prefix(dst);
2563 emit_arith(0x81, 0xD8, dst, imm32);
2564 }
2565
2566
2567 void Assembler::sbbl(Register dst, Address src) {
2568 InstructionMark im(this);
2569 prefix(src, dst);
2570 emit_byte(0x1B);
2571 emit_operand(dst, src);
2572 }
2573
2574 void Assembler::sbbl(Register dst, Register src) {
2575 (void) prefix_and_encode(dst->encoding(), src->encoding());
2576 emit_arith(0x1B, 0xC0, dst, src);
2577 }
2578
2579 void Assembler::setb(Condition cc, Register dst) {
2580 assert(0 <= cc && cc < 16, "illegal cc");
2581 int encode = prefix_and_encode(dst->encoding(), true);
2582 emit_byte(0x0F);
2583 emit_byte(0x90 | cc);
2584 emit_byte(0xC0 | encode);
2585 }
2586
2587 void Assembler::shll(Register dst, int imm8) {
2588 assert(isShiftCount(imm8), "illegal shift count");
2589 int encode = prefix_and_encode(dst->encoding());
2590 if (imm8 == 1 ) {
2591 emit_byte(0xD1);
2592 emit_byte(0xE0 | encode);
2593 } else {
2594 emit_byte(0xC1);
2595 emit_byte(0xE0 | encode);
2596 emit_byte(imm8);
2597 }
2598 }
2599
2600 void Assembler::shll(Register dst) {
2601 int encode = prefix_and_encode(dst->encoding());
2602 emit_byte(0xD3);
2603 emit_byte(0xE0 | encode);
2604 }
2605
2606 void Assembler::shrl(Register dst, int imm8) {
2607 assert(isShiftCount(imm8), "illegal shift count");
2608 int encode = prefix_and_encode(dst->encoding());
2609 emit_byte(0xC1);
2610 emit_byte(0xE8 | encode);
2611 emit_byte(imm8);
2612 }
2613
2614 void Assembler::shrl(Register dst) {
2615 int encode = prefix_and_encode(dst->encoding());
2616 emit_byte(0xD3);
2617 emit_byte(0xE8 | encode);
2618 }
2619
2620 // copies a single word from [esi] to [edi]
2621 void Assembler::smovl() {
2622 emit_byte(0xA5);
2623 }
2624
2625 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2626 // HMM Table D-1 says sse2
2627 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2629 emit_byte(0xF2);
2630 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2631 emit_byte(0x0F);
2632 emit_byte(0x51);
2633 emit_byte(0xC0 | encode);
2634 }
2635
2636 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2638 InstructionMark im(this);
2639 emit_byte(0xF2);
2640 prefix(src, dst);
2641 emit_byte(0x0F);
2642 emit_byte(0x51);
2643 emit_operand(dst, src);
2644 }
2645
2646 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2647 // HMM Table D-1 says sse2
2648 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2649 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2650 emit_byte(0xF3);
2651 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2652 emit_byte(0x0F);
2653 emit_byte(0x51);
2654 emit_byte(0xC0 | encode);
2655 }
2656
2657 void Assembler::sqrtss(XMMRegister dst, Address src) {
2658 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2659 InstructionMark im(this);
2660 emit_byte(0xF3);
2661 prefix(src, dst);
2662 emit_byte(0x0F);
2663 emit_byte(0x51);
2664 emit_operand(dst, src);
2665 }
2666
2667 void Assembler::stmxcsr( Address dst) {
2668 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2669 InstructionMark im(this);
2670 prefix(dst);
2671 emit_byte(0x0F);
2672 emit_byte(0xAE);
2673 emit_operand(as_Register(3), dst);
2674 }
2675
2676 void Assembler::subl(Address dst, int32_t imm32) {
2677 InstructionMark im(this);
2678 prefix(dst);
2679 if (is8bit(imm32)) {
2680 emit_byte(0x83);
2681 emit_operand(rbp, dst, 1);
2682 emit_byte(imm32 & 0xFF);
2683 } else {
2684 emit_byte(0x81);
2685 emit_operand(rbp, dst, 4);
2686 emit_long(imm32);
2687 }
2688 }
2689
2690 void Assembler::subl(Register dst, int32_t imm32) {
2691 prefix(dst);
2692 emit_arith(0x81, 0xE8, dst, imm32);
2693 }
2694
2695 void Assembler::subl(Address dst, Register src) {
2696 InstructionMark im(this);
2697 prefix(dst, src);
2698 emit_byte(0x29);
2699 emit_operand(src, dst);
2700 }
2701
2702 void Assembler::subl(Register dst, Address src) {
2703 InstructionMark im(this);
2704 prefix(src, dst);
2705 emit_byte(0x2B);
2706 emit_operand(dst, src);
2707 }
2708
2709 void Assembler::subl(Register dst, Register src) {
2710 (void) prefix_and_encode(dst->encoding(), src->encoding());
2711 emit_arith(0x2B, 0xC0, dst, src);
2712 }
2713
2714 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2716 emit_byte(0xF2);
2717 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2718 emit_byte(0x0F);
2719 emit_byte(0x5C);
2720 emit_byte(0xC0 | encode);
2721 }
2722
2723 void Assembler::subsd(XMMRegister dst, Address src) {
2724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2725 InstructionMark im(this);
2726 emit_byte(0xF2);
2727 prefix(src, dst);
2728 emit_byte(0x0F);
2729 emit_byte(0x5C);
2730 emit_operand(dst, src);
2731 }
2732
2733 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2734 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2735 emit_byte(0xF3);
2736 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2737 emit_byte(0x0F);
2738 emit_byte(0x5C);
2739 emit_byte(0xC0 | encode);
2740 }
2741
2742 void Assembler::subss(XMMRegister dst, Address src) {
2743 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2744 InstructionMark im(this);
2745 emit_byte(0xF3);
2746 prefix(src, dst);
2747 emit_byte(0x0F);
2748 emit_byte(0x5C);
2749 emit_operand(dst, src);
2750 }
2751
2752 void Assembler::testb(Register dst, int imm8) {
2753 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2754 (void) prefix_and_encode(dst->encoding(), true);
2755 emit_arith_b(0xF6, 0xC0, dst, imm8);
2756 }
2757
2758 void Assembler::testl(Register dst, int32_t imm32) {
2759 // not using emit_arith because test
2760 // doesn't support sign-extension of
2761 // 8bit operands
2762 int encode = dst->encoding();
2763 if (encode == 0) {
2764 emit_byte(0xA9);
2765 } else {
2766 encode = prefix_and_encode(encode);
2767 emit_byte(0xF7);
2768 emit_byte(0xC0 | encode);
2769 }
2770 emit_long(imm32);
2771 }
2772
2773 void Assembler::testl(Register dst, Register src) {
2774 (void) prefix_and_encode(dst->encoding(), src->encoding());
2775 emit_arith(0x85, 0xC0, dst, src);
2776 }
2777
2778 void Assembler::testl(Register dst, Address src) {
2779 InstructionMark im(this);
2780 prefix(src, dst);
2781 emit_byte(0x85);
2782 emit_operand(dst, src);
2783 }
2784
2785 void Assembler::ucomisd(XMMRegister dst, Address src) {
2786 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2787 emit_byte(0x66);
2788 ucomiss(dst, src);
2789 }
2790
2791 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2793 emit_byte(0x66);
2794 ucomiss(dst, src);
2795 }
2796
2797 void Assembler::ucomiss(XMMRegister dst, Address src) {
2798 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2799
2800 InstructionMark im(this);
2801 prefix(src, dst);
2802 emit_byte(0x0F);
2803 emit_byte(0x2E);
2804 emit_operand(dst, src);
2805 }
2806
2807 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2808 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2809 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2810 emit_byte(0x0F);
2811 emit_byte(0x2E);
2812 emit_byte(0xC0 | encode);
2813 }
2814
2815
2816 void Assembler::xaddl(Address dst, Register src) {
2817 InstructionMark im(this);
2818 prefix(dst, src);
2819 emit_byte(0x0F);
2820 emit_byte(0xC1);
2821 emit_operand(src, dst);
2822 }
2823
2824 void Assembler::xchgl(Register dst, Address src) { // xchg
2825 InstructionMark im(this);
2826 prefix(src, dst);
2827 emit_byte(0x87);
2828 emit_operand(dst, src);
2829 }
2830
2831 void Assembler::xchgl(Register dst, Register src) {
2832 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2833 emit_byte(0x87);
2834 emit_byte(0xc0 | encode);
2835 }
2836
2837 void Assembler::xorl(Register dst, int32_t imm32) {
2838 prefix(dst);
2839 emit_arith(0x81, 0xF0, dst, imm32);
2840 }
2841
2842 void Assembler::xorl(Register dst, Address src) {
2843 InstructionMark im(this);
2844 prefix(src, dst);
2845 emit_byte(0x33);
2846 emit_operand(dst, src);
2847 }
2848
2849 void Assembler::xorl(Register dst, Register src) {
2850 (void) prefix_and_encode(dst->encoding(), src->encoding());
2851 emit_arith(0x33, 0xC0, dst, src);
2852 }
2853
2854 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2856 emit_byte(0x66);
2857 xorps(dst, src);
2858 }
2859
2860 void Assembler::xorpd(XMMRegister dst, Address src) {
2861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2862 InstructionMark im(this);
2863 emit_byte(0x66);
2864 prefix(src, dst);
2865 emit_byte(0x0F);
2866 emit_byte(0x57);
2867 emit_operand(dst, src);
2868 }
2869
2870
2871 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2872 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2873 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2874 emit_byte(0x0F);
2875 emit_byte(0x57);
2876 emit_byte(0xC0 | encode);
2877 }
2878
2879 void Assembler::xorps(XMMRegister dst, Address src) {
2880 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2881 InstructionMark im(this);
2882 prefix(src, dst);
2883 emit_byte(0x0F);
2884 emit_byte(0x57);
2885 emit_operand(dst, src);
2886 }
2887
2888 #ifndef _LP64
2889 // 32bit only pieces of the assembler
2890
2891 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2892 // NO PREFIX AS NEVER 64BIT
2893 InstructionMark im(this);
2894 emit_byte(0x81);
2895 emit_byte(0xF8 | src1->encoding());
2896 emit_data(imm32, rspec, 0);
2897 }
2898
2899 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2900 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2901 InstructionMark im(this);
2902 emit_byte(0x81);
2903 emit_operand(rdi, src1);
2904 emit_data(imm32, rspec, 0);
2905 }
2906
2907 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
2908 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
2909 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
2910 void Assembler::cmpxchg8(Address adr) {
2911 InstructionMark im(this);
2912 emit_byte(0x0F);
2913 emit_byte(0xc7);
2914 emit_operand(rcx, adr);
2915 }
2916
2917 void Assembler::decl(Register dst) {
2918 // Don't use it directly. Use MacroAssembler::decrementl() instead.
2919 emit_byte(0x48 | dst->encoding());
2920 }
2921
2922 #endif // _LP64
2923
2924 // 64bit typically doesn't use the x87 but needs to for the trig funcs
2925
2926 void Assembler::fabs() {
2927 emit_byte(0xD9);
2928 emit_byte(0xE1);
2929 }
2930
2931 void Assembler::fadd(int i) {
2932 emit_farith(0xD8, 0xC0, i);
2933 }
2934
2935 void Assembler::fadd_d(Address src) {
2936 InstructionMark im(this);
2937 emit_byte(0xDC);
2938 emit_operand32(rax, src);
2939 }
2940
2941 void Assembler::fadd_s(Address src) {
2942 InstructionMark im(this);
2943 emit_byte(0xD8);
2944 emit_operand32(rax, src);
2945 }
2946
2947 void Assembler::fadda(int i) {
2948 emit_farith(0xDC, 0xC0, i);
2949 }
2950
2951 void Assembler::faddp(int i) {
2952 emit_farith(0xDE, 0xC0, i);
2953 }
2954
2955 void Assembler::fchs() {
2956 emit_byte(0xD9);
2957 emit_byte(0xE0);
2958 }
2959
2960 void Assembler::fcom(int i) {
2961 emit_farith(0xD8, 0xD0, i);
2962 }
2963
2964 void Assembler::fcomp(int i) {
2965 emit_farith(0xD8, 0xD8, i);
2966 }
2967
2968 void Assembler::fcomp_d(Address src) {
2969 InstructionMark im(this);
2970 emit_byte(0xDC);
2971 emit_operand32(rbx, src);
2972 }
2973
2974 void Assembler::fcomp_s(Address src) {
2975 InstructionMark im(this);
2976 emit_byte(0xD8);
2977 emit_operand32(rbx, src);
2978 }
2979
2980 void Assembler::fcompp() {
2981 emit_byte(0xDE);
2982 emit_byte(0xD9);
2983 }
2984
2985 void Assembler::fcos() {
2986 emit_byte(0xD9);
2987 emit_byte(0xFF);
2988 }
2989
2990 void Assembler::fdecstp() {
2991 emit_byte(0xD9);
2992 emit_byte(0xF6);
2993 }
2994
2995 void Assembler::fdiv(int i) {
2996 emit_farith(0xD8, 0xF0, i);
2997 }
2998
2999 void Assembler::fdiv_d(Address src) {
3000 InstructionMark im(this);
3001 emit_byte(0xDC);
3002 emit_operand32(rsi, src);
3003 }
3004
3005 void Assembler::fdiv_s(Address src) {
3006 InstructionMark im(this);
3007 emit_byte(0xD8);
3008 emit_operand32(rsi, src);
3009 }
3010
3011 void Assembler::fdiva(int i) {
3012 emit_farith(0xDC, 0xF8, i);
3013 }
3014
3015 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3016 // is erroneous for some of the floating-point instructions below.
3017
3018 void Assembler::fdivp(int i) {
3019 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3020 }
3021
3022 void Assembler::fdivr(int i) {
3023 emit_farith(0xD8, 0xF8, i);
3024 }
3025
3026 void Assembler::fdivr_d(Address src) {
3027 InstructionMark im(this);
3028 emit_byte(0xDC);
3029 emit_operand32(rdi, src);
3030 }
3031
3032 void Assembler::fdivr_s(Address src) {
3033 InstructionMark im(this);
3034 emit_byte(0xD8);
3035 emit_operand32(rdi, src);
3036 }
3037
3038 void Assembler::fdivra(int i) {
3039 emit_farith(0xDC, 0xF0, i);
3040 }
3041
3042 void Assembler::fdivrp(int i) {
3043 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3044 }
3045
3046 void Assembler::ffree(int i) {
3047 emit_farith(0xDD, 0xC0, i);
3048 }
3049
3050 void Assembler::fild_d(Address adr) {
3051 InstructionMark im(this);
3052 emit_byte(0xDF);
3053 emit_operand32(rbp, adr);
3054 }
3055
3056 void Assembler::fild_s(Address adr) {
3057 InstructionMark im(this);
3058 emit_byte(0xDB);
3059 emit_operand32(rax, adr);
3060 }
3061
3062 void Assembler::fincstp() {
3063 emit_byte(0xD9);
3064 emit_byte(0xF7);
3065 }
3066
3067 void Assembler::finit() {
3068 emit_byte(0x9B);
3069 emit_byte(0xDB);
3070 emit_byte(0xE3);
3071 }
3072
3073 void Assembler::fist_s(Address adr) {
3074 InstructionMark im(this);
3075 emit_byte(0xDB);
3076 emit_operand32(rdx, adr);
3077 }
3078
3079 void Assembler::fistp_d(Address adr) {
3080 InstructionMark im(this);
3081 emit_byte(0xDF);
3082 emit_operand32(rdi, adr);
3083 }
3084
3085 void Assembler::fistp_s(Address adr) {
3086 InstructionMark im(this);
3087 emit_byte(0xDB);
3088 emit_operand32(rbx, adr);
3089 }
3090
3091 void Assembler::fld1() {
3092 emit_byte(0xD9);
3093 emit_byte(0xE8);
3094 }
3095
3096 void Assembler::fld_d(Address adr) {
3097 InstructionMark im(this);
3098 emit_byte(0xDD);
3099 emit_operand32(rax, adr);
3100 }
3101
3102 void Assembler::fld_s(Address adr) {
3103 InstructionMark im(this);
3104 emit_byte(0xD9);
3105 emit_operand32(rax, adr);
3106 }
3107
3108
3109 void Assembler::fld_s(int index) {
3110 emit_farith(0xD9, 0xC0, index);
3111 }
3112
3113 void Assembler::fld_x(Address adr) {
3114 InstructionMark im(this);
3115 emit_byte(0xDB);
3116 emit_operand32(rbp, adr);
3117 }
3118
3119 void Assembler::fldcw(Address src) {
3120 InstructionMark im(this);
3121 emit_byte(0xd9);
3122 emit_operand32(rbp, src);
3123 }
3124
3125 void Assembler::fldenv(Address src) {
3126 InstructionMark im(this);
3127 emit_byte(0xD9);
3128 emit_operand32(rsp, src);
3129 }
3130
3131 void Assembler::fldlg2() {
3132 emit_byte(0xD9);
3133 emit_byte(0xEC);
3134 }
3135
3136 void Assembler::fldln2() {
3137 emit_byte(0xD9);
3138 emit_byte(0xED);
3139 }
3140
3141 void Assembler::fldz() {
3142 emit_byte(0xD9);
3143 emit_byte(0xEE);
3144 }
3145
3146 void Assembler::flog() {
3147 fldln2();
3148 fxch();
3149 fyl2x();
3150 }
3151
3152 void Assembler::flog10() {
3153 fldlg2();
3154 fxch();
3155 fyl2x();
3156 }
3157
3158 void Assembler::fmul(int i) {
3159 emit_farith(0xD8, 0xC8, i);
3160 }
3161
3162 void Assembler::fmul_d(Address src) {
3163 InstructionMark im(this);
3164 emit_byte(0xDC);
3165 emit_operand32(rcx, src);
3166 }
3167
3168 void Assembler::fmul_s(Address src) {
3169 InstructionMark im(this);
3170 emit_byte(0xD8);
3171 emit_operand32(rcx, src);
3172 }
3173
3174 void Assembler::fmula(int i) {
3175 emit_farith(0xDC, 0xC8, i);
3176 }
3177
3178 void Assembler::fmulp(int i) {
3179 emit_farith(0xDE, 0xC8, i);
3180 }
3181
3182 void Assembler::fnsave(Address dst) {
3183 InstructionMark im(this);
3184 emit_byte(0xDD);
3185 emit_operand32(rsi, dst);
3186 }
3187
3188 void Assembler::fnstcw(Address src) {
3189 InstructionMark im(this);
3190 emit_byte(0x9B);
3191 emit_byte(0xD9);
3192 emit_operand32(rdi, src);
3193 }
3194
3195 void Assembler::fnstsw_ax() {
3196 emit_byte(0xdF);
3197 emit_byte(0xE0);
3198 }
3199
3200 void Assembler::fprem() {
3201 emit_byte(0xD9);
3202 emit_byte(0xF8);
3203 }
3204
3205 void Assembler::fprem1() {
3206 emit_byte(0xD9);
3207 emit_byte(0xF5);
3208 }
3209
3210 void Assembler::frstor(Address src) {
3211 InstructionMark im(this);
3212 emit_byte(0xDD);
3213 emit_operand32(rsp, src);
3214 }
3215
3216 void Assembler::fsin() {
3217 emit_byte(0xD9);
3218 emit_byte(0xFE);
3219 }
3220
3221 void Assembler::fsqrt() {
3222 emit_byte(0xD9);
3223 emit_byte(0xFA);
3224 }
3225
3226 void Assembler::fst_d(Address adr) {
3227 InstructionMark im(this);
3228 emit_byte(0xDD);
3229 emit_operand32(rdx, adr);
3230 }
3231
3232 void Assembler::fst_s(Address adr) {
3233 InstructionMark im(this);
3234 emit_byte(0xD9);
3235 emit_operand32(rdx, adr);
3236 }
3237
3238 void Assembler::fstp_d(Address adr) {
3239 InstructionMark im(this);
3240 emit_byte(0xDD);
3241 emit_operand32(rbx, adr);
3242 }
3243
3244 void Assembler::fstp_d(int index) {
3245 emit_farith(0xDD, 0xD8, index);
3246 }
3247
3248 void Assembler::fstp_s(Address adr) {
3249 InstructionMark im(this);
3250 emit_byte(0xD9);
3251 emit_operand32(rbx, adr);
3252 }
3253
3254 void Assembler::fstp_x(Address adr) {
3255 InstructionMark im(this);
3256 emit_byte(0xDB);
3257 emit_operand32(rdi, adr);
3258 }
3259
3260 void Assembler::fsub(int i) {
3261 emit_farith(0xD8, 0xE0, i);
3262 }
3263
3264 void Assembler::fsub_d(Address src) {
3265 InstructionMark im(this);
3266 emit_byte(0xDC);
3267 emit_operand32(rsp, src);
3268 }
3269
3270 void Assembler::fsub_s(Address src) {
3271 InstructionMark im(this);
3272 emit_byte(0xD8);
3273 emit_operand32(rsp, src);
3274 }
3275
3276 void Assembler::fsuba(int i) {
3277 emit_farith(0xDC, 0xE8, i);
3278 }
3279
3280 void Assembler::fsubp(int i) {
3281 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3282 }
3283
3284 void Assembler::fsubr(int i) {
3285 emit_farith(0xD8, 0xE8, i);
3286 }
3287
3288 void Assembler::fsubr_d(Address src) {
3289 InstructionMark im(this);
3290 emit_byte(0xDC);
3291 emit_operand32(rbp, src);
3292 }
3293
3294 void Assembler::fsubr_s(Address src) {
3295 InstructionMark im(this);
3296 emit_byte(0xD8);
3297 emit_operand32(rbp, src);
3298 }
3299
3300 void Assembler::fsubra(int i) {
3301 emit_farith(0xDC, 0xE0, i);
3302 }
3303
3304 void Assembler::fsubrp(int i) {
3305 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3306 }
3307
3308 void Assembler::ftan() {
3309 emit_byte(0xD9);
3310 emit_byte(0xF2);
3311 emit_byte(0xDD);
3312 emit_byte(0xD8);
3313 }
3314
3315 void Assembler::ftst() {
3316 emit_byte(0xD9);
3317 emit_byte(0xE4);
3318 }
3319
3320 void Assembler::fucomi(int i) {
3321 // make sure the instruction is supported (introduced for P6, together with cmov)
3322 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3323 emit_farith(0xDB, 0xE8, i);
3324 }
3325
3326 void Assembler::fucomip(int i) {
3327 // make sure the instruction is supported (introduced for P6, together with cmov)
3328 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3329 emit_farith(0xDF, 0xE8, i);
3330 }
3331
3332 void Assembler::fwait() {
3333 emit_byte(0x9B);
3334 }
3335
3336 void Assembler::fxch(int i) {
3337 emit_farith(0xD9, 0xC8, i);
3338 }
3339
3340 void Assembler::fyl2x() {
3341 emit_byte(0xD9);
3342 emit_byte(0xF1);
3343 }
3344
3345
3346 #ifndef _LP64
3347
3348 void Assembler::incl(Register dst) {
3349 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3350 emit_byte(0x40 | dst->encoding());
3351 }
3352
3353 void Assembler::lea(Register dst, Address src) {
3354 leal(dst, src);
3355 }
3356
3357 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3358 InstructionMark im(this);
3359 emit_byte(0xC7);
3360 emit_operand(rax, dst);
3361 emit_data((int)imm32, rspec, 0);
3362 }
3363
3364 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3365 InstructionMark im(this);
3366 int encode = prefix_and_encode(dst->encoding());
3367 emit_byte(0xB8 | encode);
3368 emit_data((int)imm32, rspec, 0);
3369 }
3370
3371 void Assembler::popa() { // 32bit
3372 emit_byte(0x61);
3373 }
3374
3375 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3376 InstructionMark im(this);
3377 emit_byte(0x68);
3378 emit_data(imm32, rspec, 0);
3379 }
3380
3381 void Assembler::pusha() { // 32bit
3382 emit_byte(0x60);
3383 }
3384
3385 void Assembler::set_byte_if_not_zero(Register dst) {
3386 emit_byte(0x0F);
3387 emit_byte(0x95);
3388 emit_byte(0xE0 | dst->encoding());
3389 }
3390
3391 void Assembler::shldl(Register dst, Register src) {
3392 emit_byte(0x0F);
3393 emit_byte(0xA5);
3394 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3395 }
3396
3397 void Assembler::shrdl(Register dst, Register src) {
3398 emit_byte(0x0F);
3399 emit_byte(0xAD);
3400 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3401 }
3402
3403 #else // LP64
3404
3405 void Assembler::set_byte_if_not_zero(Register dst) {
3406 int enc = prefix_and_encode(dst->encoding(), true);
3407 emit_byte(0x0F);
3408 emit_byte(0x95);
3409 emit_byte(0xE0 | enc);
3410 }
3411
3412 // 64bit only pieces of the assembler
3413 // This should only be used by 64bit instructions that can use rip-relative
3414 // it cannot be used by instructions that want an immediate value.
3415
3416 bool Assembler::reachable(AddressLiteral adr) {
3417 int64_t disp;
3418 // None will force a 64bit literal to the code stream. Likely a placeholder
3419 // for something that will be patched later and we need to certain it will
3420 // always be reachable.
3421 if (adr.reloc() == relocInfo::none) {
3422 return false;
3423 }
3424 if (adr.reloc() == relocInfo::internal_word_type) {
3425 // This should be rip relative and easily reachable.
3426 return true;
3427 }
3428 if (adr.reloc() == relocInfo::virtual_call_type ||
3429 adr.reloc() == relocInfo::opt_virtual_call_type ||
3430 adr.reloc() == relocInfo::static_call_type ||
3431 adr.reloc() == relocInfo::static_stub_type ) {
3432 // This should be rip relative within the code cache and easily
3433 // reachable until we get huge code caches. (At which point
3434 // ic code is going to have issues).
3435 return true;
3436 }
3437 if (adr.reloc() != relocInfo::external_word_type &&
3438 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3439 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3440 adr.reloc() != relocInfo::runtime_call_type ) {
3441 return false;
3442 }
3443
3444 // Stress the correction code
3445 if (ForceUnreachable) {
3446 // Must be runtimecall reloc, see if it is in the codecache
3447 // Flipping stuff in the codecache to be unreachable causes issues
3448 // with things like inline caches where the additional instructions
3449 // are not handled.
3450 if (CodeCache::find_blob(adr._target) == NULL) {
3451 return false;
3452 }
3453 }
3454 // For external_word_type/runtime_call_type if it is reachable from where we
3455 // are now (possibly a temp buffer) and where we might end up
3456 // anywhere in the codeCache then we are always reachable.
3457 // This would have to change if we ever save/restore shared code
3458 // to be more pessimistic.
3459
3460 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3461 if (!is_simm32(disp)) return false;
3462 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3463 if (!is_simm32(disp)) return false;
3464
3465 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3466
3467 // Because rip relative is a disp + address_of_next_instruction and we
3468 // don't know the value of address_of_next_instruction we apply a fudge factor
3469 // to make sure we will be ok no matter the size of the instruction we get placed into.
3470 // We don't have to fudge the checks above here because they are already worst case.
3471
3472 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3473 // + 4 because better safe than sorry.
3474 const int fudge = 12 + 4;
3475 if (disp < 0) {
3476 disp -= fudge;
3477 } else {
3478 disp += fudge;
3479 }
3480 return is_simm32(disp);
3481 }
3482
3483 void Assembler::emit_data64(jlong data,
3484 relocInfo::relocType rtype,
3485 int format) {
3486 if (rtype == relocInfo::none) {
3487 emit_long64(data);
3488 } else {
3489 emit_data64(data, Relocation::spec_simple(rtype), format);
3490 }
3491 }
3492
3493 void Assembler::emit_data64(jlong data,
3494 RelocationHolder const& rspec,
3495 int format) {
3496 assert(imm_operand == 0, "default format must be immediate in this file");
3497 assert(imm_operand == format, "must be immediate");
3498 assert(inst_mark() != NULL, "must be inside InstructionMark");
3499 // Do not use AbstractAssembler::relocate, which is not intended for
3500 // embedded words. Instead, relocate to the enclosing instruction.
3501 code_section()->relocate(inst_mark(), rspec, format);
3502 #ifdef ASSERT
3503 check_relocation(rspec, format);
3504 #endif
3505 emit_long64(data);
3506 }
3507
3508 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3509 if (reg_enc >= 8) {
3510 prefix(REX_B);
3511 reg_enc -= 8;
3512 } else if (byteinst && reg_enc >= 4) {
3513 prefix(REX);
3514 }
3515 return reg_enc;
3516 }
3517
3518 int Assembler::prefixq_and_encode(int reg_enc) {
3519 if (reg_enc < 8) {
3520 prefix(REX_W);
3521 } else {
3522 prefix(REX_WB);
3523 reg_enc -= 8;
3524 }
3525 return reg_enc;
3526 }
3527
3528 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3529 if (dst_enc < 8) {
3530 if (src_enc >= 8) {
3531 prefix(REX_B);
3532 src_enc -= 8;
3533 } else if (byteinst && src_enc >= 4) {
3534 prefix(REX);
3535 }
3536 } else {
3537 if (src_enc < 8) {
3538 prefix(REX_R);
3539 } else {
3540 prefix(REX_RB);
3541 src_enc -= 8;
3542 }
3543 dst_enc -= 8;
3544 }
3545 return dst_enc << 3 | src_enc;
3546 }
3547
3548 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3549 if (dst_enc < 8) {
3550 if (src_enc < 8) {
3551 prefix(REX_W);
3552 } else {
3553 prefix(REX_WB);
3554 src_enc -= 8;
3555 }
3556 } else {
3557 if (src_enc < 8) {
3558 prefix(REX_WR);
3559 } else {
3560 prefix(REX_WRB);
3561 src_enc -= 8;
3562 }
3563 dst_enc -= 8;
3564 }
3565 return dst_enc << 3 | src_enc;
3566 }
3567
3568 void Assembler::prefix(Register reg) {
3569 if (reg->encoding() >= 8) {
3570 prefix(REX_B);
3571 }
3572 }
3573
3574 void Assembler::prefix(Address adr) {
3575 if (adr.base_needs_rex()) {
3576 if (adr.index_needs_rex()) {
3577 prefix(REX_XB);
3578 } else {
3579 prefix(REX_B);
3580 }
3581 } else {
3582 if (adr.index_needs_rex()) {
3583 prefix(REX_X);
3584 }
3585 }
3586 }
3587
3588 void Assembler::prefixq(Address adr) {
3589 if (adr.base_needs_rex()) {
3590 if (adr.index_needs_rex()) {
3591 prefix(REX_WXB);
3592 } else {
3593 prefix(REX_WB);
3594 }
3595 } else {
3596 if (adr.index_needs_rex()) {
3597 prefix(REX_WX);
3598 } else {
3599 prefix(REX_W);
3600 }
3601 }
3602 }
3603
3604
3605 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3606 if (reg->encoding() < 8) {
3607 if (adr.base_needs_rex()) {
3608 if (adr.index_needs_rex()) {
3609 prefix(REX_XB);
3610 } else {
3611 prefix(REX_B);
3612 }
3613 } else {
3614 if (adr.index_needs_rex()) {
3615 prefix(REX_X);
3616 } else if (reg->encoding() >= 4 ) {
3617 prefix(REX);
3618 }
3619 }
3620 } else {
3621 if (adr.base_needs_rex()) {
3622 if (adr.index_needs_rex()) {
3623 prefix(REX_RXB);
3624 } else {
3625 prefix(REX_RB);
3626 }
3627 } else {
3628 if (adr.index_needs_rex()) {
3629 prefix(REX_RX);
3630 } else {
3631 prefix(REX_R);
3632 }
3633 }
3634 }
3635 }
3636
3637 void Assembler::prefixq(Address adr, Register src) {
3638 if (src->encoding() < 8) {
3639 if (adr.base_needs_rex()) {
3640 if (adr.index_needs_rex()) {
3641 prefix(REX_WXB);
3642 } else {
3643 prefix(REX_WB);
3644 }
3645 } else {
3646 if (adr.index_needs_rex()) {
3647 prefix(REX_WX);
3648 } else {
3649 prefix(REX_W);
3650 }
3651 }
3652 } else {
3653 if (adr.base_needs_rex()) {
3654 if (adr.index_needs_rex()) {
3655 prefix(REX_WRXB);
3656 } else {
3657 prefix(REX_WRB);
3658 }
3659 } else {
3660 if (adr.index_needs_rex()) {
3661 prefix(REX_WRX);
3662 } else {
3663 prefix(REX_WR);
3664 }
3665 }
3666 }
3667 }
3668
3669 void Assembler::prefix(Address adr, XMMRegister reg) {
3670 if (reg->encoding() < 8) {
3671 if (adr.base_needs_rex()) {
3672 if (adr.index_needs_rex()) {
3673 prefix(REX_XB);
3674 } else {
3675 prefix(REX_B);
3676 }
3677 } else {
3678 if (adr.index_needs_rex()) {
3679 prefix(REX_X);
3680 }
3681 }
3682 } else {
3683 if (adr.base_needs_rex()) {
3684 if (adr.index_needs_rex()) {
3685 prefix(REX_RXB);
3686 } else {
3687 prefix(REX_RB);
3688 }
3689 } else {
3690 if (adr.index_needs_rex()) {
3691 prefix(REX_RX);
3692 } else {
3693 prefix(REX_R);
3694 }
3695 }
3696 }
3697 }
3698
3699 void Assembler::adcq(Register dst, int32_t imm32) {
3700 (void) prefixq_and_encode(dst->encoding());
3701 emit_arith(0x81, 0xD0, dst, imm32);
3702 }
3703
3704 void Assembler::adcq(Register dst, Address src) {
3705 InstructionMark im(this);
3706 prefixq(src, dst);
3707 emit_byte(0x13);
3708 emit_operand(dst, src);
3709 }
3710
3711 void Assembler::adcq(Register dst, Register src) {
3712 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3713 emit_arith(0x13, 0xC0, dst, src);
3714 }
3715
3716 void Assembler::addq(Address dst, int32_t imm32) {
3717 InstructionMark im(this);
3718 prefixq(dst);
3719 emit_arith_operand(0x81, rax, dst,imm32);
3720 }
3721
3722 void Assembler::addq(Address dst, Register src) {
3723 InstructionMark im(this);
3724 prefixq(dst, src);
3725 emit_byte(0x01);
3726 emit_operand(src, dst);
3727 }
3728
3729 void Assembler::addq(Register dst, int32_t imm32) {
3730 (void) prefixq_and_encode(dst->encoding());
3731 emit_arith(0x81, 0xC0, dst, imm32);
3732 }
3733
3734 void Assembler::addq(Register dst, Address src) {
3735 InstructionMark im(this);
3736 prefixq(src, dst);
3737 emit_byte(0x03);
3738 emit_operand(dst, src);
3739 }
3740
3741 void Assembler::addq(Register dst, Register src) {
3742 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3743 emit_arith(0x03, 0xC0, dst, src);
3744 }
3745
3746 void Assembler::andq(Register dst, int32_t imm32) {
3747 (void) prefixq_and_encode(dst->encoding());
3748 emit_arith(0x81, 0xE0, dst, imm32);
3749 }
3750
3751 void Assembler::andq(Register dst, Address src) {
3752 InstructionMark im(this);
3753 prefixq(src, dst);
3754 emit_byte(0x23);
3755 emit_operand(dst, src);
3756 }
3757
3758 void Assembler::andq(Register dst, Register src) {
3759 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3760 emit_arith(0x23, 0xC0, dst, src);
3761 }
3762
3763 void Assembler::bsfq(Register dst, Register src) {
3764 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3765 emit_byte(0x0F);
3766 emit_byte(0xBC);
3767 emit_byte(0xC0 | encode);
3768 }
3769
3770 void Assembler::bsrq(Register dst, Register src) {
3771 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3772 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3773 emit_byte(0x0F);
3774 emit_byte(0xBD);
3775 emit_byte(0xC0 | encode);
3776 }
3777
3778 void Assembler::bswapq(Register reg) {
3779 int encode = prefixq_and_encode(reg->encoding());
3780 emit_byte(0x0F);
3781 emit_byte(0xC8 | encode);
3782 }
3783
3784 void Assembler::cdqq() {
3785 prefix(REX_W);
3786 emit_byte(0x99);
3787 }
3788
3789 void Assembler::clflush(Address adr) {
3790 prefix(adr);
3791 emit_byte(0x0F);
3792 emit_byte(0xAE);
3793 emit_operand(rdi, adr);
3794 }
3795
3796 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3797 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3798 emit_byte(0x0F);
3799 emit_byte(0x40 | cc);
3800 emit_byte(0xC0 | encode);
3801 }
3802
3803 void Assembler::cmovq(Condition cc, Register dst, Address src) {
3804 InstructionMark im(this);
3805 prefixq(src, dst);
3806 emit_byte(0x0F);
3807 emit_byte(0x40 | cc);
3808 emit_operand(dst, src);
3809 }
3810
3811 void Assembler::cmpq(Address dst, int32_t imm32) {
3812 InstructionMark im(this);
3813 prefixq(dst);
3814 emit_byte(0x81);
3815 emit_operand(rdi, dst, 4);
3816 emit_long(imm32);
3817 }
3818
3819 void Assembler::cmpq(Register dst, int32_t imm32) {
3820 (void) prefixq_and_encode(dst->encoding());
3821 emit_arith(0x81, 0xF8, dst, imm32);
3822 }
3823
3824 void Assembler::cmpq(Address dst, Register src) {
3825 InstructionMark im(this);
3826 prefixq(dst, src);
3827 emit_byte(0x3B);
3828 emit_operand(src, dst);
3829 }
3830
3831 void Assembler::cmpq(Register dst, Register src) {
3832 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3833 emit_arith(0x3B, 0xC0, dst, src);
3834 }
3835
3836 void Assembler::cmpq(Register dst, Address src) {
3837 InstructionMark im(this);
3838 prefixq(src, dst);
3839 emit_byte(0x3B);
3840 emit_operand(dst, src);
3841 }
3842
3843 void Assembler::cmpxchgq(Register reg, Address adr) {
3844 InstructionMark im(this);
3845 prefixq(adr, reg);
3846 emit_byte(0x0F);
3847 emit_byte(0xB1);
3848 emit_operand(reg, adr);
3849 }
3850
3851 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3852 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3853 emit_byte(0xF2);
3854 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3855 emit_byte(0x0F);
3856 emit_byte(0x2A);
3857 emit_byte(0xC0 | encode);
3858 }
3859
3860 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3861 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3862 emit_byte(0xF3);
3863 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3864 emit_byte(0x0F);
3865 emit_byte(0x2A);
3866 emit_byte(0xC0 | encode);
3867 }
3868
3869 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3871 emit_byte(0xF2);
3872 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3873 emit_byte(0x0F);
3874 emit_byte(0x2C);
3875 emit_byte(0xC0 | encode);
3876 }
3877
3878 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3879 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3880 emit_byte(0xF3);
3881 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3882 emit_byte(0x0F);
3883 emit_byte(0x2C);
3884 emit_byte(0xC0 | encode);
3885 }
3886
3887 void Assembler::decl(Register dst) {
3888 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3889 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3890 int encode = prefix_and_encode(dst->encoding());
3891 emit_byte(0xFF);
3892 emit_byte(0xC8 | encode);
3893 }
3894
3895 void Assembler::decq(Register dst) {
3896 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3897 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3898 int encode = prefixq_and_encode(dst->encoding());
3899 emit_byte(0xFF);
3900 emit_byte(0xC8 | encode);
3901 }
3902
3903 void Assembler::decq(Address dst) {
3904 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3905 InstructionMark im(this);
3906 prefixq(dst);
3907 emit_byte(0xFF);
3908 emit_operand(rcx, dst);
3909 }
3910
3911 void Assembler::fxrstor(Address src) {
3912 prefixq(src);
3913 emit_byte(0x0F);
3914 emit_byte(0xAE);
3915 emit_operand(as_Register(1), src);
3916 }
3917
3918 void Assembler::fxsave(Address dst) {
3919 prefixq(dst);
3920 emit_byte(0x0F);
3921 emit_byte(0xAE);
3922 emit_operand(as_Register(0), dst);
3923 }
3924
3925 void Assembler::idivq(Register src) {
3926 int encode = prefixq_and_encode(src->encoding());
3927 emit_byte(0xF7);
3928 emit_byte(0xF8 | encode);
3929 }
3930
3931 void Assembler::imulq(Register dst, Register src) {
3932 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3933 emit_byte(0x0F);
3934 emit_byte(0xAF);
3935 emit_byte(0xC0 | encode);
3936 }
3937
3938 void Assembler::imulq(Register dst, Register src, int value) {
3939 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3940 if (is8bit(value)) {
3941 emit_byte(0x6B);
3942 emit_byte(0xC0 | encode);
3943 emit_byte(value & 0xFF);
3944 } else {
3945 emit_byte(0x69);
3946 emit_byte(0xC0 | encode);
3947 emit_long(value);
3948 }
3949 }
3950
3951 void Assembler::incl(Register dst) {
3952 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3953 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3954 int encode = prefix_and_encode(dst->encoding());
3955 emit_byte(0xFF);
3956 emit_byte(0xC0 | encode);
3957 }
3958
3959 void Assembler::incq(Register dst) {
3960 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3961 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3962 int encode = prefixq_and_encode(dst->encoding());
3963 emit_byte(0xFF);
3964 emit_byte(0xC0 | encode);
3965 }
3966
3967 void Assembler::incq(Address dst) {
3968 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3969 InstructionMark im(this);
3970 prefixq(dst);
3971 emit_byte(0xFF);
3972 emit_operand(rax, dst);
3973 }
3974
3975 void Assembler::lea(Register dst, Address src) {
3976 leaq(dst, src);
3977 }
3978
3979 void Assembler::leaq(Register dst, Address src) {
3980 InstructionMark im(this);
3981 prefixq(src, dst);
3982 emit_byte(0x8D);
3983 emit_operand(dst, src);
3984 }
3985
3986 void Assembler::mov64(Register dst, int64_t imm64) {
3987 InstructionMark im(this);
3988 int encode = prefixq_and_encode(dst->encoding());
3989 emit_byte(0xB8 | encode);
3990 emit_long64(imm64);
3991 }
3992
3993 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
3994 InstructionMark im(this);
3995 int encode = prefixq_and_encode(dst->encoding());
3996 emit_byte(0xB8 | encode);
3997 emit_data64(imm64, rspec);
3998 }
3999
4000 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4001 InstructionMark im(this);
4002 int encode = prefix_and_encode(dst->encoding());
4003 emit_byte(0xB8 | encode);
4004 emit_data((int)imm32, rspec, narrow_oop_operand);
4005 }
4006
4007 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4008 InstructionMark im(this);
4009 prefix(dst);
4010 emit_byte(0xC7);
4011 emit_operand(rax, dst, 4);
4012 emit_data((int)imm32, rspec, narrow_oop_operand);
4013 }
4014
4015 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
4016 InstructionMark im(this);
4017 int encode = prefix_and_encode(src1->encoding());
4018 emit_byte(0x81);
4019 emit_byte(0xF8 | encode);
4020 emit_data((int)imm32, rspec, narrow_oop_operand);
4021 }
4022
4023 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4024 InstructionMark im(this);
4025 prefix(src1);
4026 emit_byte(0x81);
4027 emit_operand(rax, src1, 4);
4028 emit_data((int)imm32, rspec, narrow_oop_operand);
4029 }
4030
4031 void Assembler::lzcntq(Register dst, Register src) {
4032 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4033 emit_byte(0xF3);
4034 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4035 emit_byte(0x0F);
4036 emit_byte(0xBD);
4037 emit_byte(0xC0 | encode);
4038 }
4039
4040 void Assembler::movdq(XMMRegister dst, Register src) {
4041 // table D-1 says MMX/SSE2
4042 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4043 emit_byte(0x66);
4044 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4045 emit_byte(0x0F);
4046 emit_byte(0x6E);
4047 emit_byte(0xC0 | encode);
4048 }
4049
4050 void Assembler::movdq(Register dst, XMMRegister src) {
4051 // table D-1 says MMX/SSE2
4052 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4053 emit_byte(0x66);
4054 // swap src/dst to get correct prefix
4055 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4056 emit_byte(0x0F);
4057 emit_byte(0x7E);
4058 emit_byte(0xC0 | encode);
4059 }
4060
4061 void Assembler::movq(Register dst, Register src) {
4062 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4063 emit_byte(0x8B);
4064 emit_byte(0xC0 | encode);
4065 }
4066
4067 void Assembler::movq(Register dst, Address src) {
4068 InstructionMark im(this);
4069 prefixq(src, dst);
4070 emit_byte(0x8B);
4071 emit_operand(dst, src);
4072 }
4073
4074 void Assembler::movq(Address dst, Register src) {
4075 InstructionMark im(this);
4076 prefixq(dst, src);
4077 emit_byte(0x89);
4078 emit_operand(src, dst);
4079 }
4080
4081 void Assembler::movsbq(Register dst, Address src) {
4082 InstructionMark im(this);
4083 prefixq(src, dst);
4084 emit_byte(0x0F);
4085 emit_byte(0xBE);
4086 emit_operand(dst, src);
4087 }
4088
4089 void Assembler::movsbq(Register dst, Register src) {
4090 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4091 emit_byte(0x0F);
4092 emit_byte(0xBE);
4093 emit_byte(0xC0 | encode);
4094 }
4095
4096 void Assembler::movslq(Register dst, int32_t imm32) {
4097 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4098 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4099 // as a result we shouldn't use until tested at runtime...
4100 ShouldNotReachHere();
4101 InstructionMark im(this);
4102 int encode = prefixq_and_encode(dst->encoding());
4103 emit_byte(0xC7 | encode);
4104 emit_long(imm32);
4105 }
4106
4107 void Assembler::movslq(Address dst, int32_t imm32) {
4108 assert(is_simm32(imm32), "lost bits");
4109 InstructionMark im(this);
4110 prefixq(dst);
4111 emit_byte(0xC7);
4112 emit_operand(rax, dst, 4);
4113 emit_long(imm32);
4114 }
4115
4116 void Assembler::movslq(Register dst, Address src) {
4117 InstructionMark im(this);
4118 prefixq(src, dst);
4119 emit_byte(0x63);
4120 emit_operand(dst, src);
4121 }
4122
4123 void Assembler::movslq(Register dst, Register src) {
4124 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4125 emit_byte(0x63);
4126 emit_byte(0xC0 | encode);
4127 }
4128
4129 void Assembler::movswq(Register dst, Address src) {
4130 InstructionMark im(this);
4131 prefixq(src, dst);
4132 emit_byte(0x0F);
4133 emit_byte(0xBF);
4134 emit_operand(dst, src);
4135 }
4136
4137 void Assembler::movswq(Register dst, Register src) {
4138 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4139 emit_byte(0x0F);
4140 emit_byte(0xBF);
4141 emit_byte(0xC0 | encode);
4142 }
4143
4144 void Assembler::movzbq(Register dst, Address src) {
4145 InstructionMark im(this);
4146 prefixq(src, dst);
4147 emit_byte(0x0F);
4148 emit_byte(0xB6);
4149 emit_operand(dst, src);
4150 }
4151
4152 void Assembler::movzbq(Register dst, Register src) {
4153 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4154 emit_byte(0x0F);
4155 emit_byte(0xB6);
4156 emit_byte(0xC0 | encode);
4157 }
4158
4159 void Assembler::movzwq(Register dst, Address src) {
4160 InstructionMark im(this);
4161 prefixq(src, dst);
4162 emit_byte(0x0F);
4163 emit_byte(0xB7);
4164 emit_operand(dst, src);
4165 }
4166
4167 void Assembler::movzwq(Register dst, Register src) {
4168 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4169 emit_byte(0x0F);
4170 emit_byte(0xB7);
4171 emit_byte(0xC0 | encode);
4172 }
4173
4174 void Assembler::negq(Register dst) {
4175 int encode = prefixq_and_encode(dst->encoding());
4176 emit_byte(0xF7);
4177 emit_byte(0xD8 | encode);
4178 }
4179
4180 void Assembler::notq(Register dst) {
4181 int encode = prefixq_and_encode(dst->encoding());
4182 emit_byte(0xF7);
4183 emit_byte(0xD0 | encode);
4184 }
4185
4186 void Assembler::orq(Address dst, int32_t imm32) {
4187 InstructionMark im(this);
4188 prefixq(dst);
4189 emit_byte(0x81);
4190 emit_operand(rcx, dst, 4);
4191 emit_long(imm32);
4192 }
4193
4194 void Assembler::orq(Register dst, int32_t imm32) {
4195 (void) prefixq_and_encode(dst->encoding());
4196 emit_arith(0x81, 0xC8, dst, imm32);
4197 }
4198
4199 void Assembler::orq(Register dst, Address src) {
4200 InstructionMark im(this);
4201 prefixq(src, dst);
4202 emit_byte(0x0B);
4203 emit_operand(dst, src);
4204 }
4205
4206 void Assembler::orq(Register dst, Register src) {
4207 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4208 emit_arith(0x0B, 0xC0, dst, src);
4209 }
4210
4211 void Assembler::popa() { // 64bit
4212 movq(r15, Address(rsp, 0));
4213 movq(r14, Address(rsp, wordSize));
4214 movq(r13, Address(rsp, 2 * wordSize));
4215 movq(r12, Address(rsp, 3 * wordSize));
4216 movq(r11, Address(rsp, 4 * wordSize));
4217 movq(r10, Address(rsp, 5 * wordSize));
4218 movq(r9, Address(rsp, 6 * wordSize));
4219 movq(r8, Address(rsp, 7 * wordSize));
4220 movq(rdi, Address(rsp, 8 * wordSize));
4221 movq(rsi, Address(rsp, 9 * wordSize));
4222 movq(rbp, Address(rsp, 10 * wordSize));
4223 // skip rsp
4224 movq(rbx, Address(rsp, 12 * wordSize));
4225 movq(rdx, Address(rsp, 13 * wordSize));
4226 movq(rcx, Address(rsp, 14 * wordSize));
4227 movq(rax, Address(rsp, 15 * wordSize));
4228
4229 addq(rsp, 16 * wordSize);
4230 }
4231
4232 void Assembler::popcntq(Register dst, Address src) {
4233 assert(VM_Version::supports_popcnt(), "must support");
4234 InstructionMark im(this);
4235 emit_byte(0xF3);
4236 prefixq(src, dst);
4237 emit_byte(0x0F);
4238 emit_byte(0xB8);
4239 emit_operand(dst, src);
4240 }
4241
4242 void Assembler::popcntq(Register dst, Register src) {
4243 assert(VM_Version::supports_popcnt(), "must support");
4244 emit_byte(0xF3);
4245 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4246 emit_byte(0x0F);
4247 emit_byte(0xB8);
4248 emit_byte(0xC0 | encode);
4249 }
4250
4251 void Assembler::popq(Address dst) {
4252 InstructionMark im(this);
4253 prefixq(dst);
4254 emit_byte(0x8F);
4255 emit_operand(rax, dst);
4256 }
4257
4258 void Assembler::pusha() { // 64bit
4259 // we have to store original rsp. ABI says that 128 bytes
4260 // below rsp are local scratch.
4261 movq(Address(rsp, -5 * wordSize), rsp);
4262
4263 subq(rsp, 16 * wordSize);
4264
4265 movq(Address(rsp, 15 * wordSize), rax);
4266 movq(Address(rsp, 14 * wordSize), rcx);
4267 movq(Address(rsp, 13 * wordSize), rdx);
4268 movq(Address(rsp, 12 * wordSize), rbx);
4269 // skip rsp
4270 movq(Address(rsp, 10 * wordSize), rbp);
4271 movq(Address(rsp, 9 * wordSize), rsi);
4272 movq(Address(rsp, 8 * wordSize), rdi);
4273 movq(Address(rsp, 7 * wordSize), r8);
4274 movq(Address(rsp, 6 * wordSize), r9);
4275 movq(Address(rsp, 5 * wordSize), r10);
4276 movq(Address(rsp, 4 * wordSize), r11);
4277 movq(Address(rsp, 3 * wordSize), r12);
4278 movq(Address(rsp, 2 * wordSize), r13);
4279 movq(Address(rsp, wordSize), r14);
4280 movq(Address(rsp, 0), r15);
4281 }
4282
4283 void Assembler::pushq(Address src) {
4284 InstructionMark im(this);
4285 prefixq(src);
4286 emit_byte(0xFF);
4287 emit_operand(rsi, src);
4288 }
4289
4290 void Assembler::rclq(Register dst, int imm8) {
4291 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4292 int encode = prefixq_and_encode(dst->encoding());
4293 if (imm8 == 1) {
4294 emit_byte(0xD1);
4295 emit_byte(0xD0 | encode);
4296 } else {
4297 emit_byte(0xC1);
4298 emit_byte(0xD0 | encode);
4299 emit_byte(imm8);
4300 }
4301 }
4302 void Assembler::sarq(Register dst, int imm8) {
4303 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4304 int encode = prefixq_and_encode(dst->encoding());
4305 if (imm8 == 1) {
4306 emit_byte(0xD1);
4307 emit_byte(0xF8 | encode);
4308 } else {
4309 emit_byte(0xC1);
4310 emit_byte(0xF8 | encode);
4311 emit_byte(imm8);
4312 }
4313 }
4314
4315 void Assembler::sarq(Register dst) {
4316 int encode = prefixq_and_encode(dst->encoding());
4317 emit_byte(0xD3);
4318 emit_byte(0xF8 | encode);
4319 }
4320 void Assembler::sbbq(Address dst, int32_t imm32) {
4321 InstructionMark im(this);
4322 prefixq(dst);
4323 emit_arith_operand(0x81, rbx, dst, imm32);
4324 }
4325
4326 void Assembler::sbbq(Register dst, int32_t imm32) {
4327 (void) prefixq_and_encode(dst->encoding());
4328 emit_arith(0x81, 0xD8, dst, imm32);
4329 }
4330
4331 void Assembler::sbbq(Register dst, Address src) {
4332 InstructionMark im(this);
4333 prefixq(src, dst);
4334 emit_byte(0x1B);
4335 emit_operand(dst, src);
4336 }
4337
4338 void Assembler::sbbq(Register dst, Register src) {
4339 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4340 emit_arith(0x1B, 0xC0, dst, src);
4341 }
4342
4343 void Assembler::shlq(Register dst, int imm8) {
4344 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4345 int encode = prefixq_and_encode(dst->encoding());
4346 if (imm8 == 1) {
4347 emit_byte(0xD1);
4348 emit_byte(0xE0 | encode);
4349 } else {
4350 emit_byte(0xC1);
4351 emit_byte(0xE0 | encode);
4352 emit_byte(imm8);
4353 }
4354 }
4355
4356 void Assembler::shlq(Register dst) {
4357 int encode = prefixq_and_encode(dst->encoding());
4358 emit_byte(0xD3);
4359 emit_byte(0xE0 | encode);
4360 }
4361
4362 void Assembler::shrq(Register dst, int imm8) {
4363 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4364 int encode = prefixq_and_encode(dst->encoding());
4365 emit_byte(0xC1);
4366 emit_byte(0xE8 | encode);
4367 emit_byte(imm8);
4368 }
4369
4370 void Assembler::shrq(Register dst) {
4371 int encode = prefixq_and_encode(dst->encoding());
4372 emit_byte(0xD3);
4373 emit_byte(0xE8 | encode);
4374 }
4375
4376 void Assembler::subq(Address dst, int32_t imm32) {
4377 InstructionMark im(this);
4378 prefixq(dst);
4379 if (is8bit(imm32)) {
4380 emit_byte(0x83);
4381 emit_operand(rbp, dst, 1);
4382 emit_byte(imm32 & 0xFF);
4383 } else {
4384 emit_byte(0x81);
4385 emit_operand(rbp, dst, 4);
4386 emit_long(imm32);
4387 }
4388 }
4389
4390 void Assembler::subq(Register dst, int32_t imm32) {
4391 (void) prefixq_and_encode(dst->encoding());
4392 emit_arith(0x81, 0xE8, dst, imm32);
4393 }
4394
4395 void Assembler::subq(Address dst, Register src) {
4396 InstructionMark im(this);
4397 prefixq(dst, src);
4398 emit_byte(0x29);
4399 emit_operand(src, dst);
4400 }
4401
4402 void Assembler::subq(Register dst, Address src) {
4403 InstructionMark im(this);
4404 prefixq(src, dst);
4405 emit_byte(0x2B);
4406 emit_operand(dst, src);
4407 }
4408
4409 void Assembler::subq(Register dst, Register src) {
4410 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4411 emit_arith(0x2B, 0xC0, dst, src);
4412 }
4413
4414 void Assembler::testq(Register dst, int32_t imm32) {
4415 // not using emit_arith because test
4416 // doesn't support sign-extension of
4417 // 8bit operands
4418 int encode = dst->encoding();
4419 if (encode == 0) {
4420 prefix(REX_W);
4421 emit_byte(0xA9);
4422 } else {
4423 encode = prefixq_and_encode(encode);
4424 emit_byte(0xF7);
4425 emit_byte(0xC0 | encode);
4426 }
4427 emit_long(imm32);
4428 }
4429
4430 void Assembler::testq(Register dst, Register src) {
4431 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4432 emit_arith(0x85, 0xC0, dst, src);
4433 }
4434
4435 void Assembler::xaddq(Address dst, Register src) {
4436 InstructionMark im(this);
4437 prefixq(dst, src);
4438 emit_byte(0x0F);
4439 emit_byte(0xC1);
4440 emit_operand(src, dst);
4441 }
4442
4443 void Assembler::xchgq(Register dst, Address src) {
4444 InstructionMark im(this);
4445 prefixq(src, dst);
4446 emit_byte(0x87);
4447 emit_operand(dst, src);
4448 }
4449
4450 void Assembler::xchgq(Register dst, Register src) {
4451 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4452 emit_byte(0x87);
4453 emit_byte(0xc0 | encode);
4454 }
4455
4456 void Assembler::xorq(Register dst, Register src) {
4457 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4458 emit_arith(0x33, 0xC0, dst, src);
4459 }
4460
4461 void Assembler::xorq(Register dst, Address src) {
4462 InstructionMark im(this);
4463 prefixq(src, dst);
4464 emit_byte(0x33);
4465 emit_operand(dst, src);
4466 }
4467
4468 #endif // !LP64
4469
4470 static Assembler::Condition reverse[] = {
4471 Assembler::noOverflow /* overflow = 0x0 */ ,
4472 Assembler::overflow /* noOverflow = 0x1 */ ,
4473 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4474 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4475 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4476 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4477 Assembler::above /* belowEqual = 0x6 */ ,
4478 Assembler::belowEqual /* above = 0x7 */ ,
4479 Assembler::positive /* negative = 0x8 */ ,
4480 Assembler::negative /* positive = 0x9 */ ,
4481 Assembler::noParity /* parity = 0xa */ ,
4482 Assembler::parity /* noParity = 0xb */ ,
4483 Assembler::greaterEqual /* less = 0xc */ ,
4484 Assembler::less /* greaterEqual = 0xd */ ,
4485 Assembler::greater /* lessEqual = 0xe */ ,
4486 Assembler::lessEqual /* greater = 0xf, */
4487
4488 };
4489
4490
4491 // Implementation of MacroAssembler
4492
4493 // First all the versions that have distinct versions depending on 32/64 bit
4494 // Unless the difference is trivial (1 line or so).
4495
4496 #ifndef _LP64
4497
4498 // 32bit versions
4499
4500 Address MacroAssembler::as_Address(AddressLiteral adr) {
4501 return Address(adr.target(), adr.rspec());
4502 }
4503
4504 Address MacroAssembler::as_Address(ArrayAddress adr) {
4505 return Address::make_array(adr);
4506 }
4507
4508 int MacroAssembler::biased_locking_enter(Register lock_reg,
4509 Register obj_reg,
4510 Register swap_reg,
4511 Register tmp_reg,
4512 bool swap_reg_contains_mark,
4513 Label& done,
4514 Label* slow_case,
4515 BiasedLockingCounters* counters) {
4516 assert(UseBiasedLocking, "why call this otherwise?");
4517 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4518 assert_different_registers(lock_reg, obj_reg, swap_reg);
4519
4520 if (PrintBiasedLockingStatistics && counters == NULL)
4521 counters = BiasedLocking::counters();
4522
4523 bool need_tmp_reg = false;
4524 if (tmp_reg == noreg) {
4525 need_tmp_reg = true;
4526 tmp_reg = lock_reg;
4527 } else {
4528 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4529 }
4530 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4531 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4532 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4533 Address saved_mark_addr(lock_reg, 0);
4534
4535 // Biased locking
4536 // See whether the lock is currently biased toward our thread and
4537 // whether the epoch is still valid
4538 // Note that the runtime guarantees sufficient alignment of JavaThread
4539 // pointers to allow age to be placed into low bits
4540 // First check to see whether biasing is even enabled for this object
4541 Label cas_label;
4542 int null_check_offset = -1;
4543 if (!swap_reg_contains_mark) {
4544 null_check_offset = offset();
4545 movl(swap_reg, mark_addr);
4546 }
4547 if (need_tmp_reg) {
4548 push(tmp_reg);
4549 }
4550 movl(tmp_reg, swap_reg);
4551 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4552 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4553 if (need_tmp_reg) {
4554 pop(tmp_reg);
4555 }
4556 jcc(Assembler::notEqual, cas_label);
4557 // The bias pattern is present in the object's header. Need to check
4558 // whether the bias owner and the epoch are both still current.
4559 // Note that because there is no current thread register on x86 we
4560 // need to store off the mark word we read out of the object to
4561 // avoid reloading it and needing to recheck invariants below. This
4562 // store is unfortunate but it makes the overall code shorter and
4563 // simpler.
4564 movl(saved_mark_addr, swap_reg);
4565 if (need_tmp_reg) {
4566 push(tmp_reg);
4567 }
4568 get_thread(tmp_reg);
4569 xorl(swap_reg, tmp_reg);
4570 if (swap_reg_contains_mark) {
4571 null_check_offset = offset();
4572 }
4573 movl(tmp_reg, klass_addr);
4574 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4575 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4576 if (need_tmp_reg) {
4577 pop(tmp_reg);
4578 }
4579 if (counters != NULL) {
4580 cond_inc32(Assembler::zero,
4581 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4582 }
4583 jcc(Assembler::equal, done);
4584
4585 Label try_revoke_bias;
4586 Label try_rebias;
4587
4588 // At this point we know that the header has the bias pattern and
4589 // that we are not the bias owner in the current epoch. We need to
4590 // figure out more details about the state of the header in order to
4591 // know what operations can be legally performed on the object's
4592 // header.
4593
4594 // If the low three bits in the xor result aren't clear, that means
4595 // the prototype header is no longer biased and we have to revoke
4596 // the bias on this object.
4597 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4598 jcc(Assembler::notZero, try_revoke_bias);
4599
4600 // Biasing is still enabled for this data type. See whether the
4601 // epoch of the current bias is still valid, meaning that the epoch
4602 // bits of the mark word are equal to the epoch bits of the
4603 // prototype header. (Note that the prototype header's epoch bits
4604 // only change at a safepoint.) If not, attempt to rebias the object
4605 // toward the current thread. Note that we must be absolutely sure
4606 // that the current epoch is invalid in order to do this because
4607 // otherwise the manipulations it performs on the mark word are
4608 // illegal.
4609 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4610 jcc(Assembler::notZero, try_rebias);
4611
4612 // The epoch of the current bias is still valid but we know nothing
4613 // about the owner; it might be set or it might be clear. Try to
4614 // acquire the bias of the object using an atomic operation. If this
4615 // fails we will go in to the runtime to revoke the object's bias.
4616 // Note that we first construct the presumed unbiased header so we
4617 // don't accidentally blow away another thread's valid bias.
4618 movl(swap_reg, saved_mark_addr);
4619 andl(swap_reg,
4620 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4621 if (need_tmp_reg) {
4622 push(tmp_reg);
4623 }
4624 get_thread(tmp_reg);
4625 orl(tmp_reg, swap_reg);
4626 if (os::is_MP()) {
4627 lock();
4628 }
4629 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4630 if (need_tmp_reg) {
4631 pop(tmp_reg);
4632 }
4633 // If the biasing toward our thread failed, this means that
4634 // another thread succeeded in biasing it toward itself and we
4635 // need to revoke that bias. The revocation will occur in the
4636 // interpreter runtime in the slow case.
4637 if (counters != NULL) {
4638 cond_inc32(Assembler::zero,
4639 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4640 }
4641 if (slow_case != NULL) {
4642 jcc(Assembler::notZero, *slow_case);
4643 }
4644 jmp(done);
4645
4646 bind(try_rebias);
4647 // At this point we know the epoch has expired, meaning that the
4648 // current "bias owner", if any, is actually invalid. Under these
4649 // circumstances _only_, we are allowed to use the current header's
4650 // value as the comparison value when doing the cas to acquire the
4651 // bias in the current epoch. In other words, we allow transfer of
4652 // the bias from one thread to another directly in this situation.
4653 //
4654 // FIXME: due to a lack of registers we currently blow away the age
4655 // bits in this situation. Should attempt to preserve them.
4656 if (need_tmp_reg) {
4657 push(tmp_reg);
4658 }
4659 get_thread(tmp_reg);
4660 movl(swap_reg, klass_addr);
4661 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4662 movl(swap_reg, saved_mark_addr);
4663 if (os::is_MP()) {
4664 lock();
4665 }
4666 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4667 if (need_tmp_reg) {
4668 pop(tmp_reg);
4669 }
4670 // If the biasing toward our thread failed, then another thread
4671 // succeeded in biasing it toward itself and we need to revoke that
4672 // bias. The revocation will occur in the runtime in the slow case.
4673 if (counters != NULL) {
4674 cond_inc32(Assembler::zero,
4675 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4676 }
4677 if (slow_case != NULL) {
4678 jcc(Assembler::notZero, *slow_case);
4679 }
4680 jmp(done);
4681
4682 bind(try_revoke_bias);
4683 // The prototype mark in the klass doesn't have the bias bit set any
4684 // more, indicating that objects of this data type are not supposed
4685 // to be biased any more. We are going to try to reset the mark of
4686 // this object to the prototype value and fall through to the
4687 // CAS-based locking scheme. Note that if our CAS fails, it means
4688 // that another thread raced us for the privilege of revoking the
4689 // bias of this particular object, so it's okay to continue in the
4690 // normal locking code.
4691 //
4692 // FIXME: due to a lack of registers we currently blow away the age
4693 // bits in this situation. Should attempt to preserve them.
4694 movl(swap_reg, saved_mark_addr);
4695 if (need_tmp_reg) {
4696 push(tmp_reg);
4697 }
4698 movl(tmp_reg, klass_addr);
4699 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4700 if (os::is_MP()) {
4701 lock();
4702 }
4703 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4704 if (need_tmp_reg) {
4705 pop(tmp_reg);
4706 }
4707 // Fall through to the normal CAS-based lock, because no matter what
4708 // the result of the above CAS, some thread must have succeeded in
4709 // removing the bias bit from the object's header.
4710 if (counters != NULL) {
4711 cond_inc32(Assembler::zero,
4712 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4713 }
4714
4715 bind(cas_label);
4716
4717 return null_check_offset;
4718 }
4719 void MacroAssembler::call_VM_leaf_base(address entry_point,
4720 int number_of_arguments) {
4721 call(RuntimeAddress(entry_point));
4722 increment(rsp, number_of_arguments * wordSize);
4723 }
4724
4725 void MacroAssembler::cmpoop(Address src1, jobject obj) {
4726 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4727 }
4728
4729 void MacroAssembler::cmpoop(Register src1, jobject obj) {
4730 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4731 }
4732
4733 void MacroAssembler::extend_sign(Register hi, Register lo) {
4734 // According to Intel Doc. AP-526, "Integer Divide", p.18.
4735 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
4736 cdql();
4737 } else {
4738 movl(hi, lo);
4739 sarl(hi, 31);
4740 }
4741 }
4742
4743 void MacroAssembler::fat_nop() {
4744 // A 5 byte nop that is safe for patching (see patch_verified_entry)
4745 emit_byte(0x26); // es:
4746 emit_byte(0x2e); // cs:
4747 emit_byte(0x64); // fs:
4748 emit_byte(0x65); // gs:
4749 emit_byte(0x90);
4750 }
4751
4752 void MacroAssembler::jC2(Register tmp, Label& L) {
4753 // set parity bit if FPU flag C2 is set (via rax)
4754 save_rax(tmp);
4755 fwait(); fnstsw_ax();
4756 sahf();
4757 restore_rax(tmp);
4758 // branch
4759 jcc(Assembler::parity, L);
4760 }
4761
4762 void MacroAssembler::jnC2(Register tmp, Label& L) {
4763 // set parity bit if FPU flag C2 is set (via rax)
4764 save_rax(tmp);
4765 fwait(); fnstsw_ax();
4766 sahf();
4767 restore_rax(tmp);
4768 // branch
4769 jcc(Assembler::noParity, L);
4770 }
4771
4772 // 32bit can do a case table jump in one instruction but we no longer allow the base
4773 // to be installed in the Address class
4774 void MacroAssembler::jump(ArrayAddress entry) {
4775 jmp(as_Address(entry));
4776 }
4777
4778 // Note: y_lo will be destroyed
4779 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
4780 // Long compare for Java (semantics as described in JVM spec.)
4781 Label high, low, done;
4782
4783 cmpl(x_hi, y_hi);
4784 jcc(Assembler::less, low);
4785 jcc(Assembler::greater, high);
4786 // x_hi is the return register
4787 xorl(x_hi, x_hi);
4788 cmpl(x_lo, y_lo);
4789 jcc(Assembler::below, low);
4790 jcc(Assembler::equal, done);
4791
4792 bind(high);
4793 xorl(x_hi, x_hi);
4794 increment(x_hi);
4795 jmp(done);
4796
4797 bind(low);
4798 xorl(x_hi, x_hi);
4799 decrementl(x_hi);
4800
4801 bind(done);
4802 }
4803
4804 void MacroAssembler::lea(Register dst, AddressLiteral src) {
4805 mov_literal32(dst, (int32_t)src.target(), src.rspec());
4806 }
4807
4808 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
4809 // leal(dst, as_Address(adr));
4810 // see note in movl as to why we must use a move
4811 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
4812 }
4813
4814 void MacroAssembler::leave() {
4815 mov(rsp, rbp);
4816 pop(rbp);
4817 }
4818
4819 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
4820 // Multiplication of two Java long values stored on the stack
4821 // as illustrated below. Result is in rdx:rax.
4822 //
4823 // rsp ---> [ ?? ] \ \
4824 // .... | y_rsp_offset |
4825 // [ y_lo ] / (in bytes) | x_rsp_offset
4826 // [ y_hi ] | (in bytes)
4827 // .... |
4828 // [ x_lo ] /
4829 // [ x_hi ]
4830 // ....
4831 //
4832 // Basic idea: lo(result) = lo(x_lo * y_lo)
4833 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
4834 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
4835 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
4836 Label quick;
4837 // load x_hi, y_hi and check if quick
4838 // multiplication is possible
4839 movl(rbx, x_hi);
4840 movl(rcx, y_hi);
4841 movl(rax, rbx);
4842 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
4843 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
4844 // do full multiplication
4845 // 1st step
4846 mull(y_lo); // x_hi * y_lo
4847 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
4848 // 2nd step
4849 movl(rax, x_lo);
4850 mull(rcx); // x_lo * y_hi
4851 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
4852 // 3rd step
4853 bind(quick); // note: rbx, = 0 if quick multiply!
4854 movl(rax, x_lo);
4855 mull(y_lo); // x_lo * y_lo
4856 addl(rdx, rbx); // correct hi(x_lo * y_lo)
4857 }
4858
4859 void MacroAssembler::lneg(Register hi, Register lo) {
4860 negl(lo);
4861 adcl(hi, 0);
4862 negl(hi);
4863 }
4864
4865 void MacroAssembler::lshl(Register hi, Register lo) {
4866 // Java shift left long support (semantics as described in JVM spec., p.305)
4867 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
4868 // shift value is in rcx !
4869 assert(hi != rcx, "must not use rcx");
4870 assert(lo != rcx, "must not use rcx");
4871 const Register s = rcx; // shift count
4872 const int n = BitsPerWord;
4873 Label L;
4874 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4875 cmpl(s, n); // if (s < n)
4876 jcc(Assembler::less, L); // else (s >= n)
4877 movl(hi, lo); // x := x << n
4878 xorl(lo, lo);
4879 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4880 bind(L); // s (mod n) < n
4881 shldl(hi, lo); // x := x << s
4882 shll(lo);
4883 }
4884
4885
4886 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
4887 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
4888 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
4889 assert(hi != rcx, "must not use rcx");
4890 assert(lo != rcx, "must not use rcx");
4891 const Register s = rcx; // shift count
4892 const int n = BitsPerWord;
4893 Label L;
4894 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4895 cmpl(s, n); // if (s < n)
4896 jcc(Assembler::less, L); // else (s >= n)
4897 movl(lo, hi); // x := x >> n
4898 if (sign_extension) sarl(hi, 31);
4899 else xorl(hi, hi);
4900 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4901 bind(L); // s (mod n) < n
4902 shrdl(lo, hi); // x := x >> s
4903 if (sign_extension) sarl(hi);
4904 else shrl(hi);
4905 }
4906
4907 void MacroAssembler::movoop(Register dst, jobject obj) {
4908 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4909 }
4910
4911 void MacroAssembler::movoop(Address dst, jobject obj) {
4912 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4913 }
4914
4915 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
4916 if (src.is_lval()) {
4917 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
4918 } else {
4919 movl(dst, as_Address(src));
4920 }
4921 }
4922
4923 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
4924 movl(as_Address(dst), src);
4925 }
4926
4927 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
4928 movl(dst, as_Address(src));
4929 }
4930
4931 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
4932 void MacroAssembler::movptr(Address dst, intptr_t src) {
4933 movl(dst, src);
4934 }
4935
4936
4937 void MacroAssembler::pop_callee_saved_registers() {
4938 pop(rcx);
4939 pop(rdx);
4940 pop(rdi);
4941 pop(rsi);
4942 }
4943
4944 void MacroAssembler::pop_fTOS() {
4945 fld_d(Address(rsp, 0));
4946 addl(rsp, 2 * wordSize);
4947 }
4948
4949 void MacroAssembler::push_callee_saved_registers() {
4950 push(rsi);
4951 push(rdi);
4952 push(rdx);
4953 push(rcx);
4954 }
4955
4956 void MacroAssembler::push_fTOS() {
4957 subl(rsp, 2 * wordSize);
4958 fstp_d(Address(rsp, 0));
4959 }
4960
4961
4962 void MacroAssembler::pushoop(jobject obj) {
4963 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
4964 }
4965
4966
4967 void MacroAssembler::pushptr(AddressLiteral src) {
4968 if (src.is_lval()) {
4969 push_literal32((int32_t)src.target(), src.rspec());
4970 } else {
4971 pushl(as_Address(src));
4972 }
4973 }
4974
4975 void MacroAssembler::set_word_if_not_zero(Register dst) {
4976 xorl(dst, dst);
4977 set_byte_if_not_zero(dst);
4978 }
4979
4980 static void pass_arg0(MacroAssembler* masm, Register arg) {
4981 masm->push(arg);
4982 }
4983
4984 static void pass_arg1(MacroAssembler* masm, Register arg) {
4985 masm->push(arg);
4986 }
4987
4988 static void pass_arg2(MacroAssembler* masm, Register arg) {
4989 masm->push(arg);
4990 }
4991
4992 static void pass_arg3(MacroAssembler* masm, Register arg) {
4993 masm->push(arg);
4994 }
4995
4996 #ifndef PRODUCT
4997 extern "C" void findpc(intptr_t x);
4998 #endif
4999
5000 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
5001 // In order to get locks to work, we need to fake a in_VM state
5002 JavaThread* thread = JavaThread::current();
5003 JavaThreadState saved_state = thread->thread_state();
5004 thread->set_thread_state(_thread_in_vm);
5005 if (ShowMessageBoxOnError) {
5006 JavaThread* thread = JavaThread::current();
5007 JavaThreadState saved_state = thread->thread_state();
5008 thread->set_thread_state(_thread_in_vm);
5009 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5010 ttyLocker ttyl;
5011 BytecodeCounter::print();
5012 }
5013 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5014 // This is the value of eip which points to where verify_oop will return.
5015 if (os::message_box(msg, "Execution stopped, print registers?")) {
5016 ttyLocker ttyl;
5017 tty->print_cr("eip = 0x%08x", eip);
5018 #ifndef PRODUCT
5019 if ((WizardMode || Verbose) && PrintMiscellaneous) {
5020 tty->cr();
5021 findpc(eip);
5022 tty->cr();
5023 }
5024 #endif
5025 tty->print_cr("rax = 0x%08x", rax);
5026 tty->print_cr("rbx = 0x%08x", rbx);
5027 tty->print_cr("rcx = 0x%08x", rcx);
5028 tty->print_cr("rdx = 0x%08x", rdx);
5029 tty->print_cr("rdi = 0x%08x", rdi);
5030 tty->print_cr("rsi = 0x%08x", rsi);
5031 tty->print_cr("rbp = 0x%08x", rbp);
5032 tty->print_cr("rsp = 0x%08x", rsp);
5033 BREAKPOINT;
5034 assert(false, "start up GDB");
5035 }
5036 } else {
5037 ttyLocker ttyl;
5038 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5039 assert(false, "DEBUG MESSAGE");
5040 }
5041 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5042 }
5043
5044 void MacroAssembler::stop(const char* msg) {
5045 ExternalAddress message((address)msg);
5046 // push address of message
5047 pushptr(message.addr());
5048 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5049 pusha(); // push registers
5050 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5051 hlt();
5052 }
5053
5054 void MacroAssembler::warn(const char* msg) {
5055 push_CPU_state();
5056
5057 ExternalAddress message((address) msg);
5058 // push address of message
5059 pushptr(message.addr());
5060
5061 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5062 addl(rsp, wordSize); // discard argument
5063 pop_CPU_state();
5064 }
5065
5066 #else // _LP64
5067
5068 // 64 bit versions
5069
5070 Address MacroAssembler::as_Address(AddressLiteral adr) {
5071 // amd64 always does this as a pc-rel
5072 // we can be absolute or disp based on the instruction type
5073 // jmp/call are displacements others are absolute
5074 assert(!adr.is_lval(), "must be rval");
5075 assert(reachable(adr), "must be");
5076 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5077
5078 }
5079
5080 Address MacroAssembler::as_Address(ArrayAddress adr) {
5081 AddressLiteral base = adr.base();
5082 lea(rscratch1, base);
5083 Address index = adr.index();
5084 assert(index._disp == 0, "must not have disp"); // maybe it can?
5085 Address array(rscratch1, index._index, index._scale, index._disp);
5086 return array;
5087 }
5088
5089 int MacroAssembler::biased_locking_enter(Register lock_reg,
5090 Register obj_reg,
5091 Register swap_reg,
5092 Register tmp_reg,
5093 bool swap_reg_contains_mark,
5094 Label& done,
5095 Label* slow_case,
5096 BiasedLockingCounters* counters) {
5097 assert(UseBiasedLocking, "why call this otherwise?");
5098 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5099 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5100 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5101 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5102 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5103 Address saved_mark_addr(lock_reg, 0);
5104
5105 if (PrintBiasedLockingStatistics && counters == NULL)
5106 counters = BiasedLocking::counters();
5107
5108 // Biased locking
5109 // See whether the lock is currently biased toward our thread and
5110 // whether the epoch is still valid
5111 // Note that the runtime guarantees sufficient alignment of JavaThread
5112 // pointers to allow age to be placed into low bits
5113 // First check to see whether biasing is even enabled for this object
5114 Label cas_label;
5115 int null_check_offset = -1;
5116 if (!swap_reg_contains_mark) {
5117 null_check_offset = offset();
5118 movq(swap_reg, mark_addr);
5119 }
5120 movq(tmp_reg, swap_reg);
5121 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5122 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5123 jcc(Assembler::notEqual, cas_label);
5124 // The bias pattern is present in the object's header. Need to check
5125 // whether the bias owner and the epoch are both still current.
5126 load_prototype_header(tmp_reg, obj_reg);
5127 orq(tmp_reg, r15_thread);
5128 xorq(tmp_reg, swap_reg);
5129 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5130 if (counters != NULL) {
5131 cond_inc32(Assembler::zero,
5132 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5133 }
5134 jcc(Assembler::equal, done);
5135
5136 Label try_revoke_bias;
5137 Label try_rebias;
5138
5139 // At this point we know that the header has the bias pattern and
5140 // that we are not the bias owner in the current epoch. We need to
5141 // figure out more details about the state of the header in order to
5142 // know what operations can be legally performed on the object's
5143 // header.
5144
5145 // If the low three bits in the xor result aren't clear, that means
5146 // the prototype header is no longer biased and we have to revoke
5147 // the bias on this object.
5148 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5149 jcc(Assembler::notZero, try_revoke_bias);
5150
5151 // Biasing is still enabled for this data type. See whether the
5152 // epoch of the current bias is still valid, meaning that the epoch
5153 // bits of the mark word are equal to the epoch bits of the
5154 // prototype header. (Note that the prototype header's epoch bits
5155 // only change at a safepoint.) If not, attempt to rebias the object
5156 // toward the current thread. Note that we must be absolutely sure
5157 // that the current epoch is invalid in order to do this because
5158 // otherwise the manipulations it performs on the mark word are
5159 // illegal.
5160 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5161 jcc(Assembler::notZero, try_rebias);
5162
5163 // The epoch of the current bias is still valid but we know nothing
5164 // about the owner; it might be set or it might be clear. Try to
5165 // acquire the bias of the object using an atomic operation. If this
5166 // fails we will go in to the runtime to revoke the object's bias.
5167 // Note that we first construct the presumed unbiased header so we
5168 // don't accidentally blow away another thread's valid bias.
5169 andq(swap_reg,
5170 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5171 movq(tmp_reg, swap_reg);
5172 orq(tmp_reg, r15_thread);
5173 if (os::is_MP()) {
5174 lock();
5175 }
5176 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5177 // If the biasing toward our thread failed, this means that
5178 // another thread succeeded in biasing it toward itself and we
5179 // need to revoke that bias. The revocation will occur in the
5180 // interpreter runtime in the slow case.
5181 if (counters != NULL) {
5182 cond_inc32(Assembler::zero,
5183 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5184 }
5185 if (slow_case != NULL) {
5186 jcc(Assembler::notZero, *slow_case);
5187 }
5188 jmp(done);
5189
5190 bind(try_rebias);
5191 // At this point we know the epoch has expired, meaning that the
5192 // current "bias owner", if any, is actually invalid. Under these
5193 // circumstances _only_, we are allowed to use the current header's
5194 // value as the comparison value when doing the cas to acquire the
5195 // bias in the current epoch. In other words, we allow transfer of
5196 // the bias from one thread to another directly in this situation.
5197 //
5198 // FIXME: due to a lack of registers we currently blow away the age
5199 // bits in this situation. Should attempt to preserve them.
5200 load_prototype_header(tmp_reg, obj_reg);
5201 orq(tmp_reg, r15_thread);
5202 if (os::is_MP()) {
5203 lock();
5204 }
5205 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5206 // If the biasing toward our thread failed, then another thread
5207 // succeeded in biasing it toward itself and we need to revoke that
5208 // bias. The revocation will occur in the runtime in the slow case.
5209 if (counters != NULL) {
5210 cond_inc32(Assembler::zero,
5211 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5212 }
5213 if (slow_case != NULL) {
5214 jcc(Assembler::notZero, *slow_case);
5215 }
5216 jmp(done);
5217
5218 bind(try_revoke_bias);
5219 // The prototype mark in the klass doesn't have the bias bit set any
5220 // more, indicating that objects of this data type are not supposed
5221 // to be biased any more. We are going to try to reset the mark of
5222 // this object to the prototype value and fall through to the
5223 // CAS-based locking scheme. Note that if our CAS fails, it means
5224 // that another thread raced us for the privilege of revoking the
5225 // bias of this particular object, so it's okay to continue in the
5226 // normal locking code.
5227 //
5228 // FIXME: due to a lack of registers we currently blow away the age
5229 // bits in this situation. Should attempt to preserve them.
5230 load_prototype_header(tmp_reg, obj_reg);
5231 if (os::is_MP()) {
5232 lock();
5233 }
5234 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5235 // Fall through to the normal CAS-based lock, because no matter what
5236 // the result of the above CAS, some thread must have succeeded in
5237 // removing the bias bit from the object's header.
5238 if (counters != NULL) {
5239 cond_inc32(Assembler::zero,
5240 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5241 }
5242
5243 bind(cas_label);
5244
5245 return null_check_offset;
5246 }
5247
5248 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5249 Label L, E;
5250
5251 #ifdef _WIN64
5252 // Windows always allocates space for it's register args
5253 assert(num_args <= 4, "only register arguments supported");
5254 subq(rsp, frame::arg_reg_save_area_bytes);
5255 #endif
5256
5257 // Align stack if necessary
5258 testl(rsp, 15);
5259 jcc(Assembler::zero, L);
5260
5261 subq(rsp, 8);
5262 {
5263 call(RuntimeAddress(entry_point));
5264 }
5265 addq(rsp, 8);
5266 jmp(E);
5267
5268 bind(L);
5269 {
5270 call(RuntimeAddress(entry_point));
5271 }
5272
5273 bind(E);
5274
5275 #ifdef _WIN64
5276 // restore stack pointer
5277 addq(rsp, frame::arg_reg_save_area_bytes);
5278 #endif
5279
5280 }
5281
5282 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5283 assert(!src2.is_lval(), "should use cmpptr");
5284
5285 if (reachable(src2)) {
5286 cmpq(src1, as_Address(src2));
5287 } else {
5288 lea(rscratch1, src2);
5289 Assembler::cmpq(src1, Address(rscratch1, 0));
5290 }
5291 }
5292
5293 int MacroAssembler::corrected_idivq(Register reg) {
5294 // Full implementation of Java ldiv and lrem; checks for special
5295 // case as described in JVM spec., p.243 & p.271. The function
5296 // returns the (pc) offset of the idivl instruction - may be needed
5297 // for implicit exceptions.
5298 //
5299 // normal case special case
5300 //
5301 // input : rax: dividend min_long
5302 // reg: divisor (may not be eax/edx) -1
5303 //
5304 // output: rax: quotient (= rax idiv reg) min_long
5305 // rdx: remainder (= rax irem reg) 0
5306 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5307 static const int64_t min_long = 0x8000000000000000;
5308 Label normal_case, special_case;
5309
5310 // check for special case
5311 cmp64(rax, ExternalAddress((address) &min_long));
5312 jcc(Assembler::notEqual, normal_case);
5313 xorl(rdx, rdx); // prepare rdx for possible special case (where
5314 // remainder = 0)
5315 cmpq(reg, -1);
5316 jcc(Assembler::equal, special_case);
5317
5318 // handle normal case
5319 bind(normal_case);
5320 cdqq();
5321 int idivq_offset = offset();
5322 idivq(reg);
5323
5324 // normal and special case exit
5325 bind(special_case);
5326
5327 return idivq_offset;
5328 }
5329
5330 void MacroAssembler::decrementq(Register reg, int value) {
5331 if (value == min_jint) { subq(reg, value); return; }
5332 if (value < 0) { incrementq(reg, -value); return; }
5333 if (value == 0) { ; return; }
5334 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5335 /* else */ { subq(reg, value) ; return; }
5336 }
5337
5338 void MacroAssembler::decrementq(Address dst, int value) {
5339 if (value == min_jint) { subq(dst, value); return; }
5340 if (value < 0) { incrementq(dst, -value); return; }
5341 if (value == 0) { ; return; }
5342 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5343 /* else */ { subq(dst, value) ; return; }
5344 }
5345
5346 void MacroAssembler::fat_nop() {
5347 // A 5 byte nop that is safe for patching (see patch_verified_entry)
5348 // Recommened sequence from 'Software Optimization Guide for the AMD
5349 // Hammer Processor'
5350 emit_byte(0x66);
5351 emit_byte(0x66);
5352 emit_byte(0x90);
5353 emit_byte(0x66);
5354 emit_byte(0x90);
5355 }
5356
5357 void MacroAssembler::incrementq(Register reg, int value) {
5358 if (value == min_jint) { addq(reg, value); return; }
5359 if (value < 0) { decrementq(reg, -value); return; }
5360 if (value == 0) { ; return; }
5361 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5362 /* else */ { addq(reg, value) ; return; }
5363 }
5364
5365 void MacroAssembler::incrementq(Address dst, int value) {
5366 if (value == min_jint) { addq(dst, value); return; }
5367 if (value < 0) { decrementq(dst, -value); return; }
5368 if (value == 0) { ; return; }
5369 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5370 /* else */ { addq(dst, value) ; return; }
5371 }
5372
5373 // 32bit can do a case table jump in one instruction but we no longer allow the base
5374 // to be installed in the Address class
5375 void MacroAssembler::jump(ArrayAddress entry) {
5376 lea(rscratch1, entry.base());
5377 Address dispatch = entry.index();
5378 assert(dispatch._base == noreg, "must be");
5379 dispatch._base = rscratch1;
5380 jmp(dispatch);
5381 }
5382
5383 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5384 ShouldNotReachHere(); // 64bit doesn't use two regs
5385 cmpq(x_lo, y_lo);
5386 }
5387
5388 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5389 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5390 }
5391
5392 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5393 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5394 movptr(dst, rscratch1);
5395 }
5396
5397 void MacroAssembler::leave() {
5398 // %%% is this really better? Why not on 32bit too?
5399 emit_byte(0xC9); // LEAVE
5400 }
5401
5402 void MacroAssembler::lneg(Register hi, Register lo) {
5403 ShouldNotReachHere(); // 64bit doesn't use two regs
5404 negq(lo);
5405 }
5406
5407 void MacroAssembler::movoop(Register dst, jobject obj) {
5408 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5409 }
5410
5411 void MacroAssembler::movoop(Address dst, jobject obj) {
5412 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5413 movq(dst, rscratch1);
5414 }
5415
5416 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5417 if (src.is_lval()) {
5418 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5419 } else {
5420 if (reachable(src)) {
5421 movq(dst, as_Address(src));
5422 } else {
5423 lea(rscratch1, src);
5424 movq(dst, Address(rscratch1,0));
5425 }
5426 }
5427 }
5428
5429 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5430 movq(as_Address(dst), src);
5431 }
5432
5433 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5434 movq(dst, as_Address(src));
5435 }
5436
5437 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5438 void MacroAssembler::movptr(Address dst, intptr_t src) {
5439 mov64(rscratch1, src);
5440 movq(dst, rscratch1);
5441 }
5442
5443 // These are mostly for initializing NULL
5444 void MacroAssembler::movptr(Address dst, int32_t src) {
5445 movslq(dst, src);
5446 }
5447
5448 void MacroAssembler::movptr(Register dst, int32_t src) {
5449 mov64(dst, (intptr_t)src);
5450 }
5451
5452 void MacroAssembler::pushoop(jobject obj) {
5453 movoop(rscratch1, obj);
5454 push(rscratch1);
5455 }
5456
5457 void MacroAssembler::pushptr(AddressLiteral src) {
5458 lea(rscratch1, src);
5459 if (src.is_lval()) {
5460 push(rscratch1);
5461 } else {
5462 pushq(Address(rscratch1, 0));
5463 }
5464 }
5465
5466 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5467 bool clear_pc) {
5468 // we must set sp to zero to clear frame
5469 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5470 // must clear fp, so that compiled frames are not confused; it is
5471 // possible that we need it only for debugging
5472 if (clear_fp) {
5473 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5474 }
5475
5476 if (clear_pc) {
5477 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5478 }
5479 }
5480
5481 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5482 Register last_java_fp,
5483 address last_java_pc) {
5484 // determine last_java_sp register
5485 if (!last_java_sp->is_valid()) {
5486 last_java_sp = rsp;
5487 }
5488
5489 // last_java_fp is optional
5490 if (last_java_fp->is_valid()) {
5491 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5492 last_java_fp);
5493 }
5494
5495 // last_java_pc is optional
5496 if (last_java_pc != NULL) {
5497 Address java_pc(r15_thread,
5498 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5499 lea(rscratch1, InternalAddress(last_java_pc));
5500 movptr(java_pc, rscratch1);
5501 }
5502
5503 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5504 }
5505
5506 static void pass_arg0(MacroAssembler* masm, Register arg) {
5507 if (c_rarg0 != arg ) {
5508 masm->mov(c_rarg0, arg);
5509 }
5510 }
5511
5512 static void pass_arg1(MacroAssembler* masm, Register arg) {
5513 if (c_rarg1 != arg ) {
5514 masm->mov(c_rarg1, arg);
5515 }
5516 }
5517
5518 static void pass_arg2(MacroAssembler* masm, Register arg) {
5519 if (c_rarg2 != arg ) {
5520 masm->mov(c_rarg2, arg);
5521 }
5522 }
5523
5524 static void pass_arg3(MacroAssembler* masm, Register arg) {
5525 if (c_rarg3 != arg ) {
5526 masm->mov(c_rarg3, arg);
5527 }
5528 }
5529
5530 void MacroAssembler::stop(const char* msg) {
5531 address rip = pc();
5532 pusha(); // get regs on stack
5533 lea(c_rarg0, ExternalAddress((address) msg));
5534 lea(c_rarg1, InternalAddress(rip));
5535 movq(c_rarg2, rsp); // pass pointer to regs array
5536 andq(rsp, -16); // align stack as required by ABI
5537 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5538 hlt();
5539 }
5540
5541 void MacroAssembler::warn(const char* msg) {
5542 push(r12);
5543 movq(r12, rsp);
5544 andq(rsp, -16); // align stack as required by push_CPU_state and call
5545
5546 push_CPU_state(); // keeps alignment at 16 bytes
5547 lea(c_rarg0, ExternalAddress((address) msg));
5548 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5549 pop_CPU_state();
5550
5551 movq(rsp, r12);
5552 pop(r12);
5553 }
5554
5555 #ifndef PRODUCT
5556 extern "C" void findpc(intptr_t x);
5557 #endif
5558
5559 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5560 // In order to get locks to work, we need to fake a in_VM state
5561 if (ShowMessageBoxOnError ) {
5562 JavaThread* thread = JavaThread::current();
5563 JavaThreadState saved_state = thread->thread_state();
5564 thread->set_thread_state(_thread_in_vm);
5565 #ifndef PRODUCT
5566 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5567 ttyLocker ttyl;
5568 BytecodeCounter::print();
5569 }
5570 #endif
5571 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5572 // XXX correct this offset for amd64
5573 // This is the value of eip which points to where verify_oop will return.
5574 if (os::message_box(msg, "Execution stopped, print registers?")) {
5575 ttyLocker ttyl;
5576 tty->print_cr("rip = 0x%016lx", pc);
5577 #ifndef PRODUCT
5578 tty->cr();
5579 findpc(pc);
5580 tty->cr();
5581 #endif
5582 tty->print_cr("rax = 0x%016lx", regs[15]);
5583 tty->print_cr("rbx = 0x%016lx", regs[12]);
5584 tty->print_cr("rcx = 0x%016lx", regs[14]);
5585 tty->print_cr("rdx = 0x%016lx", regs[13]);
5586 tty->print_cr("rdi = 0x%016lx", regs[8]);
5587 tty->print_cr("rsi = 0x%016lx", regs[9]);
5588 tty->print_cr("rbp = 0x%016lx", regs[10]);
5589 tty->print_cr("rsp = 0x%016lx", regs[11]);
5590 tty->print_cr("r8 = 0x%016lx", regs[7]);
5591 tty->print_cr("r9 = 0x%016lx", regs[6]);
5592 tty->print_cr("r10 = 0x%016lx", regs[5]);
5593 tty->print_cr("r11 = 0x%016lx", regs[4]);
5594 tty->print_cr("r12 = 0x%016lx", regs[3]);
5595 tty->print_cr("r13 = 0x%016lx", regs[2]);
5596 tty->print_cr("r14 = 0x%016lx", regs[1]);
5597 tty->print_cr("r15 = 0x%016lx", regs[0]);
5598 BREAKPOINT;
5599 }
5600 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5601 } else {
5602 ttyLocker ttyl;
5603 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5604 msg);
5605 }
5606 }
5607
5608 #endif // _LP64
5609
5610 // Now versions that are common to 32/64 bit
5611
5612 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5613 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5614 }
5615
5616 void MacroAssembler::addptr(Register dst, Register src) {
5617 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5618 }
5619
5620 void MacroAssembler::addptr(Address dst, Register src) {
5621 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5622 }
5623
5624 void MacroAssembler::align(int modulus) {
5625 if (offset() % modulus != 0) {
5626 nop(modulus - (offset() % modulus));
5627 }
5628 }
5629
5630 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5631 if (reachable(src)) {
5632 andpd(dst, as_Address(src));
5633 } else {
5634 lea(rscratch1, src);
5635 andpd(dst, Address(rscratch1, 0));
5636 }
5637 }
5638
5639 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5640 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5641 }
5642
5643 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5644 pushf();
5645 if (os::is_MP())
5646 lock();
5647 incrementl(counter_addr);
5648 popf();
5649 }
5650
5651 // Writes to stack successive pages until offset reached to check for
5652 // stack overflow + shadow pages. This clobbers tmp.
5653 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5654 movptr(tmp, rsp);
5655 // Bang stack for total size given plus shadow page size.
5656 // Bang one page at a time because large size can bang beyond yellow and
5657 // red zones.
5658 Label loop;
5659 bind(loop);
5660 movl(Address(tmp, (-os::vm_page_size())), size );
5661 subptr(tmp, os::vm_page_size());
5662 subl(size, os::vm_page_size());
5663 jcc(Assembler::greater, loop);
5664
5665 // Bang down shadow pages too.
5666 // The -1 because we already subtracted 1 page.
5667 for (int i = 0; i< StackShadowPages-1; i++) {
5668 // this could be any sized move but this is can be a debugging crumb
5669 // so the bigger the better.
5670 movptr(Address(tmp, (-i*os::vm_page_size())), size );
5671 }
5672 }
5673
5674 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
5675 assert(UseBiasedLocking, "why call this otherwise?");
5676
5677 // Check for biased locking unlock case, which is a no-op
5678 // Note: we do not have to check the thread ID for two reasons.
5679 // First, the interpreter checks for IllegalMonitorStateException at
5680 // a higher level. Second, if the bias was revoked while we held the
5681 // lock, the object could not be rebiased toward another thread, so
5682 // the bias bit would be clear.
5683 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
5684 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
5685 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
5686 jcc(Assembler::equal, done);
5687 }
5688
5689 void MacroAssembler::c2bool(Register x) {
5690 // implements x == 0 ? 0 : 1
5691 // note: must only look at least-significant byte of x
5692 // since C-style booleans are stored in one byte
5693 // only! (was bug)
5694 andl(x, 0xFF);
5695 setb(Assembler::notZero, x);
5696 }
5697
5698 // Wouldn't need if AddressLiteral version had new name
5699 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
5700 Assembler::call(L, rtype);
5701 }
5702
5703 void MacroAssembler::call(Register entry) {
5704 Assembler::call(entry);
5705 }
5706
5707 void MacroAssembler::call(AddressLiteral entry) {
5708 if (reachable(entry)) {
5709 Assembler::call_literal(entry.target(), entry.rspec());
5710 } else {
5711 lea(rscratch1, entry);
5712 Assembler::call(rscratch1);
5713 }
5714 }
5715
5716 // Implementation of call_VM versions
5717
5718 void MacroAssembler::call_VM(Register oop_result,
5719 address entry_point,
5720 bool check_exceptions) {
5721 Label C, E;
5722 call(C, relocInfo::none);
5723 jmp(E);
5724
5725 bind(C);
5726 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
5727 ret(0);
5728
5729 bind(E);
5730 }
5731
5732 void MacroAssembler::call_VM(Register oop_result,
5733 address entry_point,
5734 Register arg_1,
5735 bool check_exceptions) {
5736 Label C, E;
5737 call(C, relocInfo::none);
5738 jmp(E);
5739
5740 bind(C);
5741 pass_arg1(this, arg_1);
5742 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
5743 ret(0);
5744
5745 bind(E);
5746 }
5747
5748 void MacroAssembler::call_VM(Register oop_result,
5749 address entry_point,
5750 Register arg_1,
5751 Register arg_2,
5752 bool check_exceptions) {
5753 Label C, E;
5754 call(C, relocInfo::none);
5755 jmp(E);
5756
5757 bind(C);
5758
5759 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5760
5761 pass_arg2(this, arg_2);
5762 pass_arg1(this, arg_1);
5763 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
5764 ret(0);
5765
5766 bind(E);
5767 }
5768
5769 void MacroAssembler::call_VM(Register oop_result,
5770 address entry_point,
5771 Register arg_1,
5772 Register arg_2,
5773 Register arg_3,
5774 bool check_exceptions) {
5775 Label C, E;
5776 call(C, relocInfo::none);
5777 jmp(E);
5778
5779 bind(C);
5780
5781 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5782 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5783 pass_arg3(this, arg_3);
5784
5785 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5786 pass_arg2(this, arg_2);
5787
5788 pass_arg1(this, arg_1);
5789 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
5790 ret(0);
5791
5792 bind(E);
5793 }
5794
5795 void MacroAssembler::call_VM(Register oop_result,
5796 Register last_java_sp,
5797 address entry_point,
5798 int number_of_arguments,
5799 bool check_exceptions) {
5800 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5801 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5802 }
5803
5804 void MacroAssembler::call_VM(Register oop_result,
5805 Register last_java_sp,
5806 address entry_point,
5807 Register arg_1,
5808 bool check_exceptions) {
5809 pass_arg1(this, arg_1);
5810 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5811 }
5812
5813 void MacroAssembler::call_VM(Register oop_result,
5814 Register last_java_sp,
5815 address entry_point,
5816 Register arg_1,
5817 Register arg_2,
5818 bool check_exceptions) {
5819
5820 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5821 pass_arg2(this, arg_2);
5822 pass_arg1(this, arg_1);
5823 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5824 }
5825
5826 void MacroAssembler::call_VM(Register oop_result,
5827 Register last_java_sp,
5828 address entry_point,
5829 Register arg_1,
5830 Register arg_2,
5831 Register arg_3,
5832 bool check_exceptions) {
5833 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5834 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5835 pass_arg3(this, arg_3);
5836 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5837 pass_arg2(this, arg_2);
5838 pass_arg1(this, arg_1);
5839 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5840 }
5841
5842 void MacroAssembler::call_VM_base(Register oop_result,
5843 Register java_thread,
5844 Register last_java_sp,
5845 address entry_point,
5846 int number_of_arguments,
5847 bool check_exceptions) {
5848 // determine java_thread register
5849 if (!java_thread->is_valid()) {
5850 #ifdef _LP64
5851 java_thread = r15_thread;
5852 #else
5853 java_thread = rdi;
5854 get_thread(java_thread);
5855 #endif // LP64
5856 }
5857 // determine last_java_sp register
5858 if (!last_java_sp->is_valid()) {
5859 last_java_sp = rsp;
5860 }
5861 // debugging support
5862 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
5863 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
5864 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
5865 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
5866
5867 // push java thread (becomes first argument of C function)
5868
5869 NOT_LP64(push(java_thread); number_of_arguments++);
5870 LP64_ONLY(mov(c_rarg0, r15_thread));
5871
5872 // set last Java frame before call
5873 assert(last_java_sp != rbp, "can't use ebp/rbp");
5874
5875 // Only interpreter should have to set fp
5876 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
5877
5878 // do the call, remove parameters
5879 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
5880
5881 // restore the thread (cannot use the pushed argument since arguments
5882 // may be overwritten by C code generated by an optimizing compiler);
5883 // however can use the register value directly if it is callee saved.
5884 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
5885 // rdi & rsi (also r15) are callee saved -> nothing to do
5886 #ifdef ASSERT
5887 guarantee(java_thread != rax, "change this code");
5888 push(rax);
5889 { Label L;
5890 get_thread(rax);
5891 cmpptr(java_thread, rax);
5892 jcc(Assembler::equal, L);
5893 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
5894 bind(L);
5895 }
5896 pop(rax);
5897 #endif
5898 } else {
5899 get_thread(java_thread);
5900 }
5901 // reset last Java frame
5902 // Only interpreter should have to clear fp
5903 reset_last_Java_frame(java_thread, true, false);
5904
5905 #ifndef CC_INTERP
5906 // C++ interp handles this in the interpreter
5907 check_and_handle_popframe(java_thread);
5908 check_and_handle_earlyret(java_thread);
5909 #endif /* CC_INTERP */
5910
5911 if (check_exceptions) {
5912 // check for pending exceptions (java_thread is set upon return)
5913 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
5914 #ifndef _LP64
5915 jump_cc(Assembler::notEqual,
5916 RuntimeAddress(StubRoutines::forward_exception_entry()));
5917 #else
5918 // This used to conditionally jump to forward_exception however it is
5919 // possible if we relocate that the branch will not reach. So we must jump
5920 // around so we can always reach
5921
5922 Label ok;
5923 jcc(Assembler::equal, ok);
5924 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
5925 bind(ok);
5926 #endif // LP64
5927 }
5928
5929 // get oop result if there is one and reset the value in the thread
5930 if (oop_result->is_valid()) {
5931 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
5932 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
5933 verify_oop(oop_result, "broken oop in call_VM_base");
5934 }
5935 }
5936
5937 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
5938
5939 // Calculate the value for last_Java_sp
5940 // somewhat subtle. call_VM does an intermediate call
5941 // which places a return address on the stack just under the
5942 // stack pointer as the user finsihed with it. This allows
5943 // use to retrieve last_Java_pc from last_Java_sp[-1].
5944 // On 32bit we then have to push additional args on the stack to accomplish
5945 // the actual requested call. On 64bit call_VM only can use register args
5946 // so the only extra space is the return address that call_VM created.
5947 // This hopefully explains the calculations here.
5948
5949 #ifdef _LP64
5950 // We've pushed one address, correct last_Java_sp
5951 lea(rax, Address(rsp, wordSize));
5952 #else
5953 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
5954 #endif // LP64
5955
5956 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
5957
5958 }
5959
5960 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
5961 call_VM_leaf_base(entry_point, number_of_arguments);
5962 }
5963
5964 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
5965 pass_arg0(this, arg_0);
5966 call_VM_leaf(entry_point, 1);
5967 }
5968
5969 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
5970
5971 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5972 pass_arg1(this, arg_1);
5973 pass_arg0(this, arg_0);
5974 call_VM_leaf(entry_point, 2);
5975 }
5976
5977 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
5978 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
5979 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5980 pass_arg2(this, arg_2);
5981 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5982 pass_arg1(this, arg_1);
5983 pass_arg0(this, arg_0);
5984 call_VM_leaf(entry_point, 3);
5985 }
5986
5987 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
5988 }
5989
5990 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
5991 }
5992
5993 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
5994 if (reachable(src1)) {
5995 cmpl(as_Address(src1), imm);
5996 } else {
5997 lea(rscratch1, src1);
5998 cmpl(Address(rscratch1, 0), imm);
5999 }
6000 }
6001
6002 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
6003 assert(!src2.is_lval(), "use cmpptr");
6004 if (reachable(src2)) {
6005 cmpl(src1, as_Address(src2));
6006 } else {
6007 lea(rscratch1, src2);
6008 cmpl(src1, Address(rscratch1, 0));
6009 }
6010 }
6011
6012 void MacroAssembler::cmp32(Register src1, int32_t imm) {
6013 Assembler::cmpl(src1, imm);
6014 }
6015
6016 void MacroAssembler::cmp32(Register src1, Address src2) {
6017 Assembler::cmpl(src1, src2);
6018 }
6019
6020 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6021 ucomisd(opr1, opr2);
6022
6023 Label L;
6024 if (unordered_is_less) {
6025 movl(dst, -1);
6026 jcc(Assembler::parity, L);
6027 jcc(Assembler::below , L);
6028 movl(dst, 0);
6029 jcc(Assembler::equal , L);
6030 increment(dst);
6031 } else { // unordered is greater
6032 movl(dst, 1);
6033 jcc(Assembler::parity, L);
6034 jcc(Assembler::above , L);
6035 movl(dst, 0);
6036 jcc(Assembler::equal , L);
6037 decrementl(dst);
6038 }
6039 bind(L);
6040 }
6041
6042 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6043 ucomiss(opr1, opr2);
6044
6045 Label L;
6046 if (unordered_is_less) {
6047 movl(dst, -1);
6048 jcc(Assembler::parity, L);
6049 jcc(Assembler::below , L);
6050 movl(dst, 0);
6051 jcc(Assembler::equal , L);
6052 increment(dst);
6053 } else { // unordered is greater
6054 movl(dst, 1);
6055 jcc(Assembler::parity, L);
6056 jcc(Assembler::above , L);
6057 movl(dst, 0);
6058 jcc(Assembler::equal , L);
6059 decrementl(dst);
6060 }
6061 bind(L);
6062 }
6063
6064
6065 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6066 if (reachable(src1)) {
6067 cmpb(as_Address(src1), imm);
6068 } else {
6069 lea(rscratch1, src1);
6070 cmpb(Address(rscratch1, 0), imm);
6071 }
6072 }
6073
6074 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6075 #ifdef _LP64
6076 if (src2.is_lval()) {
6077 movptr(rscratch1, src2);
6078 Assembler::cmpq(src1, rscratch1);
6079 } else if (reachable(src2)) {
6080 cmpq(src1, as_Address(src2));
6081 } else {
6082 lea(rscratch1, src2);
6083 Assembler::cmpq(src1, Address(rscratch1, 0));
6084 }
6085 #else
6086 if (src2.is_lval()) {
6087 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6088 } else {
6089 cmpl(src1, as_Address(src2));
6090 }
6091 #endif // _LP64
6092 }
6093
6094 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6095 assert(src2.is_lval(), "not a mem-mem compare");
6096 #ifdef _LP64
6097 // moves src2's literal address
6098 movptr(rscratch1, src2);
6099 Assembler::cmpq(src1, rscratch1);
6100 #else
6101 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6102 #endif // _LP64
6103 }
6104
6105 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6106 if (reachable(adr)) {
6107 if (os::is_MP())
6108 lock();
6109 cmpxchgptr(reg, as_Address(adr));
6110 } else {
6111 lea(rscratch1, adr);
6112 if (os::is_MP())
6113 lock();
6114 cmpxchgptr(reg, Address(rscratch1, 0));
6115 }
6116 }
6117
6118 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6119 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6120 }
6121
6122 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6123 if (reachable(src)) {
6124 comisd(dst, as_Address(src));
6125 } else {
6126 lea(rscratch1, src);
6127 comisd(dst, Address(rscratch1, 0));
6128 }
6129 }
6130
6131 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6132 if (reachable(src)) {
6133 comiss(dst, as_Address(src));
6134 } else {
6135 lea(rscratch1, src);
6136 comiss(dst, Address(rscratch1, 0));
6137 }
6138 }
6139
6140
6141 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6142 Condition negated_cond = negate_condition(cond);
6143 Label L;
6144 jcc(negated_cond, L);
6145 atomic_incl(counter_addr);
6146 bind(L);
6147 }
6148
6149 int MacroAssembler::corrected_idivl(Register reg) {
6150 // Full implementation of Java idiv and irem; checks for
6151 // special case as described in JVM spec., p.243 & p.271.
6152 // The function returns the (pc) offset of the idivl
6153 // instruction - may be needed for implicit exceptions.
6154 //
6155 // normal case special case
6156 //
6157 // input : rax,: dividend min_int
6158 // reg: divisor (may not be rax,/rdx) -1
6159 //
6160 // output: rax,: quotient (= rax, idiv reg) min_int
6161 // rdx: remainder (= rax, irem reg) 0
6162 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6163 const int min_int = 0x80000000;
6164 Label normal_case, special_case;
6165
6166 // check for special case
6167 cmpl(rax, min_int);
6168 jcc(Assembler::notEqual, normal_case);
6169 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6170 cmpl(reg, -1);
6171 jcc(Assembler::equal, special_case);
6172
6173 // handle normal case
6174 bind(normal_case);
6175 cdql();
6176 int idivl_offset = offset();
6177 idivl(reg);
6178
6179 // normal and special case exit
6180 bind(special_case);
6181
6182 return idivl_offset;
6183 }
6184
6185
6186
6187 void MacroAssembler::decrementl(Register reg, int value) {
6188 if (value == min_jint) {subl(reg, value) ; return; }
6189 if (value < 0) { incrementl(reg, -value); return; }
6190 if (value == 0) { ; return; }
6191 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6192 /* else */ { subl(reg, value) ; return; }
6193 }
6194
6195 void MacroAssembler::decrementl(Address dst, int value) {
6196 if (value == min_jint) {subl(dst, value) ; return; }
6197 if (value < 0) { incrementl(dst, -value); return; }
6198 if (value == 0) { ; return; }
6199 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6200 /* else */ { subl(dst, value) ; return; }
6201 }
6202
6203 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6204 assert (shift_value > 0, "illegal shift value");
6205 Label _is_positive;
6206 testl (reg, reg);
6207 jcc (Assembler::positive, _is_positive);
6208 int offset = (1 << shift_value) - 1 ;
6209
6210 if (offset == 1) {
6211 incrementl(reg);
6212 } else {
6213 addl(reg, offset);
6214 }
6215
6216 bind (_is_positive);
6217 sarl(reg, shift_value);
6218 }
6219
6220 // !defined(COMPILER2) is because of stupid core builds
6221 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6222 void MacroAssembler::empty_FPU_stack() {
6223 if (VM_Version::supports_mmx()) {
6224 emms();
6225 } else {
6226 for (int i = 8; i-- > 0; ) ffree(i);
6227 }
6228 }
6229 #endif // !LP64 || C1 || !C2
6230
6231
6232 // Defines obj, preserves var_size_in_bytes
6233 void MacroAssembler::eden_allocate(Register obj,
6234 Register var_size_in_bytes,
6235 int con_size_in_bytes,
6236 Register t1,
6237 Label& slow_case) {
6238 assert(obj == rax, "obj must be in rax, for cmpxchg");
6239 assert_different_registers(obj, var_size_in_bytes, t1);
6240 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6241 jmp(slow_case);
6242 } else {
6243 Register end = t1;
6244 Label retry;
6245 bind(retry);
6246 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6247 movptr(obj, heap_top);
6248 if (var_size_in_bytes == noreg) {
6249 lea(end, Address(obj, con_size_in_bytes));
6250 } else {
6251 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6252 }
6253 // if end < obj then we wrapped around => object too long => slow case
6254 cmpptr(end, obj);
6255 jcc(Assembler::below, slow_case);
6256 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6257 jcc(Assembler::above, slow_case);
6258 // Compare obj with the top addr, and if still equal, store the new top addr in
6259 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6260 // it otherwise. Use lock prefix for atomicity on MPs.
6261 locked_cmpxchgptr(end, heap_top);
6262 jcc(Assembler::notEqual, retry);
6263 }
6264 }
6265
6266 void MacroAssembler::enter() {
6267 push(rbp);
6268 mov(rbp, rsp);
6269 }
6270
6271 void MacroAssembler::fcmp(Register tmp) {
6272 fcmp(tmp, 1, true, true);
6273 }
6274
6275 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6276 assert(!pop_right || pop_left, "usage error");
6277 if (VM_Version::supports_cmov()) {
6278 assert(tmp == noreg, "unneeded temp");
6279 if (pop_left) {
6280 fucomip(index);
6281 } else {
6282 fucomi(index);
6283 }
6284 if (pop_right) {
6285 fpop();
6286 }
6287 } else {
6288 assert(tmp != noreg, "need temp");
6289 if (pop_left) {
6290 if (pop_right) {
6291 fcompp();
6292 } else {
6293 fcomp(index);
6294 }
6295 } else {
6296 fcom(index);
6297 }
6298 // convert FPU condition into eflags condition via rax,
6299 save_rax(tmp);
6300 fwait(); fnstsw_ax();
6301 sahf();
6302 restore_rax(tmp);
6303 }
6304 // condition codes set as follows:
6305 //
6306 // CF (corresponds to C0) if x < y
6307 // PF (corresponds to C2) if unordered
6308 // ZF (corresponds to C3) if x = y
6309 }
6310
6311 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6312 fcmp2int(dst, unordered_is_less, 1, true, true);
6313 }
6314
6315 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6316 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6317 Label L;
6318 if (unordered_is_less) {
6319 movl(dst, -1);
6320 jcc(Assembler::parity, L);
6321 jcc(Assembler::below , L);
6322 movl(dst, 0);
6323 jcc(Assembler::equal , L);
6324 increment(dst);
6325 } else { // unordered is greater
6326 movl(dst, 1);
6327 jcc(Assembler::parity, L);
6328 jcc(Assembler::above , L);
6329 movl(dst, 0);
6330 jcc(Assembler::equal , L);
6331 decrementl(dst);
6332 }
6333 bind(L);
6334 }
6335
6336 void MacroAssembler::fld_d(AddressLiteral src) {
6337 fld_d(as_Address(src));
6338 }
6339
6340 void MacroAssembler::fld_s(AddressLiteral src) {
6341 fld_s(as_Address(src));
6342 }
6343
6344 void MacroAssembler::fld_x(AddressLiteral src) {
6345 Assembler::fld_x(as_Address(src));
6346 }
6347
6348 void MacroAssembler::fldcw(AddressLiteral src) {
6349 Assembler::fldcw(as_Address(src));
6350 }
6351
6352 void MacroAssembler::fpop() {
6353 ffree();
6354 fincstp();
6355 }
6356
6357 void MacroAssembler::fremr(Register tmp) {
6358 save_rax(tmp);
6359 { Label L;
6360 bind(L);
6361 fprem();
6362 fwait(); fnstsw_ax();
6363 #ifdef _LP64
6364 testl(rax, 0x400);
6365 jcc(Assembler::notEqual, L);
6366 #else
6367 sahf();
6368 jcc(Assembler::parity, L);
6369 #endif // _LP64
6370 }
6371 restore_rax(tmp);
6372 // Result is in ST0.
6373 // Note: fxch & fpop to get rid of ST1
6374 // (otherwise FPU stack could overflow eventually)
6375 fxch(1);
6376 fpop();
6377 }
6378
6379
6380 void MacroAssembler::incrementl(AddressLiteral dst) {
6381 if (reachable(dst)) {
6382 incrementl(as_Address(dst));
6383 } else {
6384 lea(rscratch1, dst);
6385 incrementl(Address(rscratch1, 0));
6386 }
6387 }
6388
6389 void MacroAssembler::incrementl(ArrayAddress dst) {
6390 incrementl(as_Address(dst));
6391 }
6392
6393 void MacroAssembler::incrementl(Register reg, int value) {
6394 if (value == min_jint) {addl(reg, value) ; return; }
6395 if (value < 0) { decrementl(reg, -value); return; }
6396 if (value == 0) { ; return; }
6397 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6398 /* else */ { addl(reg, value) ; return; }
6399 }
6400
6401 void MacroAssembler::incrementl(Address dst, int value) {
6402 if (value == min_jint) {addl(dst, value) ; return; }
6403 if (value < 0) { decrementl(dst, -value); return; }
6404 if (value == 0) { ; return; }
6405 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6406 /* else */ { addl(dst, value) ; return; }
6407 }
6408
6409 void MacroAssembler::jump(AddressLiteral dst) {
6410 if (reachable(dst)) {
6411 jmp_literal(dst.target(), dst.rspec());
6412 } else {
6413 lea(rscratch1, dst);
6414 jmp(rscratch1);
6415 }
6416 }
6417
6418 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6419 if (reachable(dst)) {
6420 InstructionMark im(this);
6421 relocate(dst.reloc());
6422 const int short_size = 2;
6423 const int long_size = 6;
6424 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6425 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6426 // 0111 tttn #8-bit disp
6427 emit_byte(0x70 | cc);
6428 emit_byte((offs - short_size) & 0xFF);
6429 } else {
6430 // 0000 1111 1000 tttn #32-bit disp
6431 emit_byte(0x0F);
6432 emit_byte(0x80 | cc);
6433 emit_long(offs - long_size);
6434 }
6435 } else {
6436 #ifdef ASSERT
6437 warning("reversing conditional branch");
6438 #endif /* ASSERT */
6439 Label skip;
6440 jccb(reverse[cc], skip);
6441 lea(rscratch1, dst);
6442 Assembler::jmp(rscratch1);
6443 bind(skip);
6444 }
6445 }
6446
6447 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6448 if (reachable(src)) {
6449 Assembler::ldmxcsr(as_Address(src));
6450 } else {
6451 lea(rscratch1, src);
6452 Assembler::ldmxcsr(Address(rscratch1, 0));
6453 }
6454 }
6455
6456 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6457 int off;
6458 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6459 off = offset();
6460 movsbl(dst, src); // movsxb
6461 } else {
6462 off = load_unsigned_byte(dst, src);
6463 shll(dst, 24);
6464 sarl(dst, 24);
6465 }
6466 return off;
6467 }
6468
6469 // Note: load_signed_short used to be called load_signed_word.
6470 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6471 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6472 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6473 int MacroAssembler::load_signed_short(Register dst, Address src) {
6474 int off;
6475 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6476 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6477 // version but this is what 64bit has always done. This seems to imply
6478 // that users are only using 32bits worth.
6479 off = offset();
6480 movswl(dst, src); // movsxw
6481 } else {
6482 off = load_unsigned_short(dst, src);
6483 shll(dst, 16);
6484 sarl(dst, 16);
6485 }
6486 return off;
6487 }
6488
6489 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
6490 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6491 // and "3.9 Partial Register Penalties", p. 22).
6492 int off;
6493 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
6494 off = offset();
6495 movzbl(dst, src); // movzxb
6496 } else {
6497 xorl(dst, dst);
6498 off = offset();
6499 movb(dst, src);
6500 }
6501 return off;
6502 }
6503
6504 // Note: load_unsigned_short used to be called load_unsigned_word.
6505 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
6506 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6507 // and "3.9 Partial Register Penalties", p. 22).
6508 int off;
6509 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
6510 off = offset();
6511 movzwl(dst, src); // movzxw
6512 } else {
6513 xorl(dst, dst);
6514 off = offset();
6515 movw(dst, src);
6516 }
6517 return off;
6518 }
6519
6520 void MacroAssembler::load_sized_value(Register dst, Address src,
6521 size_t size_in_bytes, bool is_signed) {
6522 switch (size_in_bytes) {
6523 #ifndef _LP64
6524 // For case 8, caller is responsible for manually loading
6525 // the second word into another register.
6526 case 8: movl(dst, src); break;
6527 #else
6528 case 8: movq(dst, src); break;
6529 #endif
6530 case 4: movl(dst, src); break;
6531 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
6532 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
6533 default: ShouldNotReachHere();
6534 }
6535 }
6536
6537 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
6538 if (reachable(dst)) {
6539 movl(as_Address(dst), src);
6540 } else {
6541 lea(rscratch1, dst);
6542 movl(Address(rscratch1, 0), src);
6543 }
6544 }
6545
6546 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
6547 if (reachable(src)) {
6548 movl(dst, as_Address(src));
6549 } else {
6550 lea(rscratch1, src);
6551 movl(dst, Address(rscratch1, 0));
6552 }
6553 }
6554
6555 // C++ bool manipulation
6556
6557 void MacroAssembler::movbool(Register dst, Address src) {
6558 if(sizeof(bool) == 1)
6559 movb(dst, src);
6560 else if(sizeof(bool) == 2)
6561 movw(dst, src);
6562 else if(sizeof(bool) == 4)
6563 movl(dst, src);
6564 else
6565 // unsupported
6566 ShouldNotReachHere();
6567 }
6568
6569 void MacroAssembler::movbool(Address dst, bool boolconst) {
6570 if(sizeof(bool) == 1)
6571 movb(dst, (int) boolconst);
6572 else if(sizeof(bool) == 2)
6573 movw(dst, (int) boolconst);
6574 else if(sizeof(bool) == 4)
6575 movl(dst, (int) boolconst);
6576 else
6577 // unsupported
6578 ShouldNotReachHere();
6579 }
6580
6581 void MacroAssembler::movbool(Address dst, Register src) {
6582 if(sizeof(bool) == 1)
6583 movb(dst, src);
6584 else if(sizeof(bool) == 2)
6585 movw(dst, src);
6586 else if(sizeof(bool) == 4)
6587 movl(dst, src);
6588 else
6589 // unsupported
6590 ShouldNotReachHere();
6591 }
6592
6593 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
6594 movb(as_Address(dst), src);
6595 }
6596
6597 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
6598 if (reachable(src)) {
6599 if (UseXmmLoadAndClearUpper) {
6600 movsd (dst, as_Address(src));
6601 } else {
6602 movlpd(dst, as_Address(src));
6603 }
6604 } else {
6605 lea(rscratch1, src);
6606 if (UseXmmLoadAndClearUpper) {
6607 movsd (dst, Address(rscratch1, 0));
6608 } else {
6609 movlpd(dst, Address(rscratch1, 0));
6610 }
6611 }
6612 }
6613
6614 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
6615 if (reachable(src)) {
6616 movss(dst, as_Address(src));
6617 } else {
6618 lea(rscratch1, src);
6619 movss(dst, Address(rscratch1, 0));
6620 }
6621 }
6622
6623 void MacroAssembler::movptr(Register dst, Register src) {
6624 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6625 }
6626
6627 void MacroAssembler::movptr(Register dst, Address src) {
6628 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6629 }
6630
6631 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6632 void MacroAssembler::movptr(Register dst, intptr_t src) {
6633 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6634 }
6635
6636 void MacroAssembler::movptr(Address dst, Register src) {
6637 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6638 }
6639
6640 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6641 if (reachable(src)) {
6642 movss(dst, as_Address(src));
6643 } else {
6644 lea(rscratch1, src);
6645 movss(dst, Address(rscratch1, 0));
6646 }
6647 }
6648
6649 void MacroAssembler::null_check(Register reg, int offset) {
6650 if (needs_explicit_null_check(offset)) {
6651 // provoke OS NULL exception if reg = NULL by
6652 // accessing M[reg] w/o changing any (non-CC) registers
6653 // NOTE: cmpl is plenty here to provoke a segv
6654 cmpptr(rax, Address(reg, 0));
6655 // Note: should probably use testl(rax, Address(reg, 0));
6656 // may be shorter code (however, this version of
6657 // testl needs to be implemented first)
6658 } else {
6659 // nothing to do, (later) access of M[reg + offset]
6660 // will provoke OS NULL exception if reg = NULL
6661 }
6662 }
6663
6664 void MacroAssembler::os_breakpoint() {
6665 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6666 // (e.g., MSVC can't call ps() otherwise)
6667 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6668 }
6669
6670 void MacroAssembler::pop_CPU_state() {
6671 pop_FPU_state();
6672 pop_IU_state();
6673 }
6674
6675 void MacroAssembler::pop_FPU_state() {
6676 NOT_LP64(frstor(Address(rsp, 0));)
6677 LP64_ONLY(fxrstor(Address(rsp, 0));)
6678 addptr(rsp, FPUStateSizeInWords * wordSize);
6679 }
6680
6681 void MacroAssembler::pop_IU_state() {
6682 popa();
6683 LP64_ONLY(addq(rsp, 8));
6684 popf();
6685 }
6686
6687 // Save Integer and Float state
6688 // Warning: Stack must be 16 byte aligned (64bit)
6689 void MacroAssembler::push_CPU_state() {
6690 push_IU_state();
6691 push_FPU_state();
6692 }
6693
6694 void MacroAssembler::push_FPU_state() {
6695 subptr(rsp, FPUStateSizeInWords * wordSize);
6696 #ifndef _LP64
6697 fnsave(Address(rsp, 0));
6698 fwait();
6699 #else
6700 fxsave(Address(rsp, 0));
6701 #endif // LP64
6702 }
6703
6704 void MacroAssembler::push_IU_state() {
6705 // Push flags first because pusha kills them
6706 pushf();
6707 // Make sure rsp stays 16-byte aligned
6708 LP64_ONLY(subq(rsp, 8));
6709 pusha();
6710 }
6711
6712 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
6713 // determine java_thread register
6714 if (!java_thread->is_valid()) {
6715 java_thread = rdi;
6716 get_thread(java_thread);
6717 }
6718 // we must set sp to zero to clear frame
6719 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6720 if (clear_fp) {
6721 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6722 }
6723
6724 if (clear_pc)
6725 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6726
6727 }
6728
6729 void MacroAssembler::restore_rax(Register tmp) {
6730 if (tmp == noreg) pop(rax);
6731 else if (tmp != rax) mov(rax, tmp);
6732 }
6733
6734 void MacroAssembler::round_to(Register reg, int modulus) {
6735 addptr(reg, modulus - 1);
6736 andptr(reg, -modulus);
6737 }
6738
6739 void MacroAssembler::save_rax(Register tmp) {
6740 if (tmp == noreg) push(rax);
6741 else if (tmp != rax) mov(tmp, rax);
6742 }
6743
6744 // Write serialization page so VM thread can do a pseudo remote membar.
6745 // We use the current thread pointer to calculate a thread specific
6746 // offset to write to within the page. This minimizes bus traffic
6747 // due to cache line collision.
6748 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
6749 movl(tmp, thread);
6750 shrl(tmp, os::get_serialize_page_shift_count());
6751 andl(tmp, (os::vm_page_size() - sizeof(int)));
6752
6753 Address index(noreg, tmp, Address::times_1);
6754 ExternalAddress page(os::get_memory_serialize_page());
6755
6756 // Size of store must match masking code above
6757 movl(as_Address(ArrayAddress(page, index)), tmp);
6758 }
6759
6760 // Calls to C land
6761 //
6762 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
6763 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
6764 // has to be reset to 0. This is required to allow proper stack traversal.
6765 void MacroAssembler::set_last_Java_frame(Register java_thread,
6766 Register last_java_sp,
6767 Register last_java_fp,
6768 address last_java_pc) {
6769 // determine java_thread register
6770 if (!java_thread->is_valid()) {
6771 java_thread = rdi;
6772 get_thread(java_thread);
6773 }
6774 // determine last_java_sp register
6775 if (!last_java_sp->is_valid()) {
6776 last_java_sp = rsp;
6777 }
6778
6779 // last_java_fp is optional
6780
6781 if (last_java_fp->is_valid()) {
6782 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
6783 }
6784
6785 // last_java_pc is optional
6786
6787 if (last_java_pc != NULL) {
6788 lea(Address(java_thread,
6789 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
6790 InternalAddress(last_java_pc));
6791
6792 }
6793 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6794 }
6795
6796 void MacroAssembler::shlptr(Register dst, int imm8) {
6797 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
6798 }
6799
6800 void MacroAssembler::shrptr(Register dst, int imm8) {
6801 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
6802 }
6803
6804 void MacroAssembler::sign_extend_byte(Register reg) {
6805 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
6806 movsbl(reg, reg); // movsxb
6807 } else {
6808 shll(reg, 24);
6809 sarl(reg, 24);
6810 }
6811 }
6812
6813 void MacroAssembler::sign_extend_short(Register reg) {
6814 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6815 movswl(reg, reg); // movsxw
6816 } else {
6817 shll(reg, 16);
6818 sarl(reg, 16);
6819 }
6820 }
6821
6822 //////////////////////////////////////////////////////////////////////////////////
6823 #ifndef SERIALGC
6824
6825 void MacroAssembler::g1_write_barrier_pre(Register obj,
6826 #ifndef _LP64
6827 Register thread,
6828 #endif
6829 Register tmp,
6830 Register tmp2,
6831 bool tosca_live) {
6832 LP64_ONLY(Register thread = r15_thread;)
6833 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6834 PtrQueue::byte_offset_of_active()));
6835
6836 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6837 PtrQueue::byte_offset_of_index()));
6838 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6839 PtrQueue::byte_offset_of_buf()));
6840
6841
6842 Label done;
6843 Label runtime;
6844
6845 // if (!marking_in_progress) goto done;
6846 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
6847 cmpl(in_progress, 0);
6848 } else {
6849 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
6850 cmpb(in_progress, 0);
6851 }
6852 jcc(Assembler::equal, done);
6853
6854 // if (x.f == NULL) goto done;
6855 #ifdef _LP64
6856 load_heap_oop(tmp2, Address(obj, 0));
6857 #else
6858 movptr(tmp2, Address(obj, 0));
6859 #endif
6860 cmpptr(tmp2, (int32_t) NULL_WORD);
6861 jcc(Assembler::equal, done);
6862
6863 // Can we store original value in the thread's buffer?
6864
6865 #ifdef _LP64
6866 movslq(tmp, index);
6867 cmpq(tmp, 0);
6868 #else
6869 cmpl(index, 0);
6870 #endif
6871 jcc(Assembler::equal, runtime);
6872 #ifdef _LP64
6873 subq(tmp, wordSize);
6874 movl(index, tmp);
6875 addq(tmp, buffer);
6876 #else
6877 subl(index, wordSize);
6878 movl(tmp, buffer);
6879 addl(tmp, index);
6880 #endif
6881 movptr(Address(tmp, 0), tmp2);
6882 jmp(done);
6883 bind(runtime);
6884 // save the live input values
6885 if(tosca_live) push(rax);
6886 push(obj);
6887 #ifdef _LP64
6888 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread);
6889 #else
6890 push(thread);
6891 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread);
6892 pop(thread);
6893 #endif
6894 pop(obj);
6895 if(tosca_live) pop(rax);
6896 bind(done);
6897
6898 }
6899
6900 void MacroAssembler::g1_write_barrier_post(Register store_addr,
6901 Register new_val,
6902 #ifndef _LP64
6903 Register thread,
6904 #endif
6905 Register tmp,
6906 Register tmp2) {
6907
6908 LP64_ONLY(Register thread = r15_thread;)
6909 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6910 PtrQueue::byte_offset_of_index()));
6911 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6912 PtrQueue::byte_offset_of_buf()));
6913 BarrierSet* bs = Universe::heap()->barrier_set();
6914 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6915 Label done;
6916 Label runtime;
6917
6918 // Does store cross heap regions?
6919
6920 movptr(tmp, store_addr);
6921 xorptr(tmp, new_val);
6922 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
6923 jcc(Assembler::equal, done);
6924
6925 // crosses regions, storing NULL?
6926
6927 cmpptr(new_val, (int32_t) NULL_WORD);
6928 jcc(Assembler::equal, done);
6929
6930 // storing region crossing non-NULL, is card already dirty?
6931
6932 ExternalAddress cardtable((address) ct->byte_map_base);
6933 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
6934 #ifdef _LP64
6935 const Register card_addr = tmp;
6936
6937 movq(card_addr, store_addr);
6938 shrq(card_addr, CardTableModRefBS::card_shift);
6939
6940 lea(tmp2, cardtable);
6941
6942 // get the address of the card
6943 addq(card_addr, tmp2);
6944 #else
6945 const Register card_index = tmp;
6946
6947 movl(card_index, store_addr);
6948 shrl(card_index, CardTableModRefBS::card_shift);
6949
6950 Address index(noreg, card_index, Address::times_1);
6951 const Register card_addr = tmp;
6952 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
6953 #endif
6954 cmpb(Address(card_addr, 0), 0);
6955 jcc(Assembler::equal, done);
6956
6957 // storing a region crossing, non-NULL oop, card is clean.
6958 // dirty card and log.
6959
6960 movb(Address(card_addr, 0), 0);
6961
6962 cmpl(queue_index, 0);
6963 jcc(Assembler::equal, runtime);
6964 subl(queue_index, wordSize);
6965 movptr(tmp2, buffer);
6966 #ifdef _LP64
6967 movslq(rscratch1, queue_index);
6968 addq(tmp2, rscratch1);
6969 movq(Address(tmp2, 0), card_addr);
6970 #else
6971 addl(tmp2, queue_index);
6972 movl(Address(tmp2, 0), card_index);
6973 #endif
6974 jmp(done);
6975
6976 bind(runtime);
6977 // save the live input values
6978 push(store_addr);
6979 push(new_val);
6980 #ifdef _LP64
6981 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
6982 #else
6983 push(thread);
6984 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
6985 pop(thread);
6986 #endif
6987 pop(new_val);
6988 pop(store_addr);
6989
6990 bind(done);
6991
6992 }
6993
6994 #endif // SERIALGC
6995 //////////////////////////////////////////////////////////////////////////////////
6996
6997
6998 void MacroAssembler::store_check(Register obj) {
6999 // Does a store check for the oop in register obj. The content of
7000 // register obj is destroyed afterwards.
7001 store_check_part_1(obj);
7002 store_check_part_2(obj);
7003 }
7004
7005 void MacroAssembler::store_check(Register obj, Address dst) {
7006 store_check(obj);
7007 }
7008
7009
7010 // split the store check operation so that other instructions can be scheduled inbetween
7011 void MacroAssembler::store_check_part_1(Register obj) {
7012 BarrierSet* bs = Universe::heap()->barrier_set();
7013 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7014 shrptr(obj, CardTableModRefBS::card_shift);
7015 }
7016
7017 void MacroAssembler::store_check_part_2(Register obj) {
7018 BarrierSet* bs = Universe::heap()->barrier_set();
7019 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7020 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7021 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7022
7023 // The calculation for byte_map_base is as follows:
7024 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
7025 // So this essentially converts an address to a displacement and
7026 // it will never need to be relocated. On 64bit however the value may be too
7027 // large for a 32bit displacement
7028
7029 intptr_t disp = (intptr_t) ct->byte_map_base;
7030 if (is_simm32(disp)) {
7031 Address cardtable(noreg, obj, Address::times_1, disp);
7032 movb(cardtable, 0);
7033 } else {
7034 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7035 // displacement and done in a single instruction given favorable mapping and
7036 // a smarter version of as_Address. Worst case it is two instructions which
7037 // is no worse off then loading disp into a register and doing as a simple
7038 // Address() as above.
7039 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7040 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7041 // in some cases we'll get a single instruction version.
7042
7043 ExternalAddress cardtable((address)disp);
7044 Address index(noreg, obj, Address::times_1);
7045 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7046 }
7047 }
7048
7049 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7050 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7051 }
7052
7053 void MacroAssembler::subptr(Register dst, Register src) {
7054 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7055 }
7056
7057 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
7058 // src2 must be rval
7059
7060 if (reachable(src2)) {
7061 testl(src1, as_Address(src2));
7062 } else {
7063 lea(rscratch1, src2);
7064 testl(src1, Address(rscratch1, 0));
7065 }
7066 }
7067
7068 // C++ bool manipulation
7069 void MacroAssembler::testbool(Register dst) {
7070 if(sizeof(bool) == 1)
7071 testb(dst, 0xff);
7072 else if(sizeof(bool) == 2) {
7073 // testw implementation needed for two byte bools
7074 ShouldNotReachHere();
7075 } else if(sizeof(bool) == 4)
7076 testl(dst, dst);
7077 else
7078 // unsupported
7079 ShouldNotReachHere();
7080 }
7081
7082 void MacroAssembler::testptr(Register dst, Register src) {
7083 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7084 }
7085
7086 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7087 void MacroAssembler::tlab_allocate(Register obj,
7088 Register var_size_in_bytes,
7089 int con_size_in_bytes,
7090 Register t1,
7091 Register t2,
7092 Label& slow_case) {
7093 assert_different_registers(obj, t1, t2);
7094 assert_different_registers(obj, var_size_in_bytes, t1);
7095 Register end = t2;
7096 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7097
7098 verify_tlab();
7099
7100 NOT_LP64(get_thread(thread));
7101
7102 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7103 if (var_size_in_bytes == noreg) {
7104 lea(end, Address(obj, con_size_in_bytes));
7105 } else {
7106 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7107 }
7108 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7109 jcc(Assembler::above, slow_case);
7110
7111 // update the tlab top pointer
7112 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7113
7114 // recover var_size_in_bytes if necessary
7115 if (var_size_in_bytes == end) {
7116 subptr(var_size_in_bytes, obj);
7117 }
7118 verify_tlab();
7119 }
7120
7121 // Preserves rbx, and rdx.
7122 void MacroAssembler::tlab_refill(Label& retry,
7123 Label& try_eden,
7124 Label& slow_case) {
7125 Register top = rax;
7126 Register t1 = rcx;
7127 Register t2 = rsi;
7128 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7129 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7130 Label do_refill, discard_tlab;
7131
7132 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7133 // No allocation in the shared eden.
7134 jmp(slow_case);
7135 }
7136
7137 NOT_LP64(get_thread(thread_reg));
7138
7139 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7140 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7141
7142 // calculate amount of free space
7143 subptr(t1, top);
7144 shrptr(t1, LogHeapWordSize);
7145
7146 // Retain tlab and allocate object in shared space if
7147 // the amount free in the tlab is too large to discard.
7148 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7149 jcc(Assembler::lessEqual, discard_tlab);
7150
7151 // Retain
7152 // %%% yuck as movptr...
7153 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7154 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7155 if (TLABStats) {
7156 // increment number of slow_allocations
7157 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7158 }
7159 jmp(try_eden);
7160
7161 bind(discard_tlab);
7162 if (TLABStats) {
7163 // increment number of refills
7164 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7165 // accumulate wastage -- t1 is amount free in tlab
7166 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7167 }
7168
7169 // if tlab is currently allocated (top or end != null) then
7170 // fill [top, end + alignment_reserve) with array object
7171 testptr (top, top);
7172 jcc(Assembler::zero, do_refill);
7173
7174 // set up the mark word
7175 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7176 // set the length to the remaining space
7177 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7178 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7179 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7180 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7181 // set klass to intArrayKlass
7182 // dubious reloc why not an oop reloc?
7183 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
7184 // store klass last. concurrent gcs assumes klass length is valid if
7185 // klass field is not null.
7186 store_klass(top, t1);
7187
7188 // refill the tlab with an eden allocation
7189 bind(do_refill);
7190 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7191 shlptr(t1, LogHeapWordSize);
7192 // add object_size ??
7193 eden_allocate(top, t1, 0, t2, slow_case);
7194
7195 // Check that t1 was preserved in eden_allocate.
7196 #ifdef ASSERT
7197 if (UseTLAB) {
7198 Label ok;
7199 Register tsize = rsi;
7200 assert_different_registers(tsize, thread_reg, t1);
7201 push(tsize);
7202 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7203 shlptr(tsize, LogHeapWordSize);
7204 cmpptr(t1, tsize);
7205 jcc(Assembler::equal, ok);
7206 stop("assert(t1 != tlab size)");
7207 should_not_reach_here();
7208
7209 bind(ok);
7210 pop(tsize);
7211 }
7212 #endif
7213 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
7214 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
7215 addptr(top, t1);
7216 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
7217 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
7218 verify_tlab();
7219 jmp(retry);
7220 }
7221
7222 static const double pi_4 = 0.7853981633974483;
7223
7224 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
7225 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
7226 // was attempted in this code; unfortunately it appears that the
7227 // switch to 80-bit precision and back causes this to be
7228 // unprofitable compared with simply performing a runtime call if
7229 // the argument is out of the (-pi/4, pi/4) range.
7230
7231 Register tmp = noreg;
7232 if (!VM_Version::supports_cmov()) {
7233 // fcmp needs a temporary so preserve rbx,
7234 tmp = rbx;
7235 push(tmp);
7236 }
7237
7238 Label slow_case, done;
7239
7240 ExternalAddress pi4_adr = (address)&pi_4;
7241 if (reachable(pi4_adr)) {
7242 // x ?<= pi/4
7243 fld_d(pi4_adr);
7244 fld_s(1); // Stack: X PI/4 X
7245 fabs(); // Stack: |X| PI/4 X
7246 fcmp(tmp);
7247 jcc(Assembler::above, slow_case);
7248
7249 // fastest case: -pi/4 <= x <= pi/4
7250 switch(trig) {
7251 case 's':
7252 fsin();
7253 break;
7254 case 'c':
7255 fcos();
7256 break;
7257 case 't':
7258 ftan();
7259 break;
7260 default:
7261 assert(false, "bad intrinsic");
7262 break;
7263 }
7264 jmp(done);
7265 }
7266
7267 // slow case: runtime call
7268 bind(slow_case);
7269 // Preserve registers across runtime call
7270 pusha();
7271 int incoming_argument_and_return_value_offset = -1;
7272 if (num_fpu_regs_in_use > 1) {
7273 // Must preserve all other FPU regs (could alternatively convert
7274 // SharedRuntime::dsin and dcos into assembly routines known not to trash
7275 // FPU state, but can not trust C compiler)
7276 NEEDS_CLEANUP;
7277 // NOTE that in this case we also push the incoming argument to
7278 // the stack and restore it later; we also use this stack slot to
7279 // hold the return value from dsin or dcos.
7280 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7281 subptr(rsp, sizeof(jdouble));
7282 fstp_d(Address(rsp, 0));
7283 }
7284 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
7285 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
7286 }
7287 subptr(rsp, sizeof(jdouble));
7288 fstp_d(Address(rsp, 0));
7289 #ifdef _LP64
7290 movdbl(xmm0, Address(rsp, 0));
7291 #endif // _LP64
7292
7293 // NOTE: we must not use call_VM_leaf here because that requires a
7294 // complete interpreter frame in debug mode -- same bug as 4387334
7295 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
7296 // do proper 64bit abi
7297
7298 NEEDS_CLEANUP;
7299 // Need to add stack banging before this runtime call if it needs to
7300 // be taken; however, there is no generic stack banging routine at
7301 // the MacroAssembler level
7302 switch(trig) {
7303 case 's':
7304 {
7305 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
7306 }
7307 break;
7308 case 'c':
7309 {
7310 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
7311 }
7312 break;
7313 case 't':
7314 {
7315 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
7316 }
7317 break;
7318 default:
7319 assert(false, "bad intrinsic");
7320 break;
7321 }
7322 #ifdef _LP64
7323 movsd(Address(rsp, 0), xmm0);
7324 fld_d(Address(rsp, 0));
7325 #endif // _LP64
7326 addptr(rsp, sizeof(jdouble));
7327 if (num_fpu_regs_in_use > 1) {
7328 // Must save return value to stack and then restore entire FPU stack
7329 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
7330 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7331 fld_d(Address(rsp, 0));
7332 addptr(rsp, sizeof(jdouble));
7333 }
7334 }
7335 popa();
7336
7337 // Come here with result in F-TOS
7338 bind(done);
7339
7340 if (tmp != noreg) {
7341 pop(tmp);
7342 }
7343 }
7344
7345
7346 // Look up the method for a megamorphic invokeinterface call.
7347 // The target method is determined by <intf_klass, itable_index>.
7348 // The receiver klass is in recv_klass.
7349 // On success, the result will be in method_result, and execution falls through.
7350 // On failure, execution transfers to the given label.
7351 void MacroAssembler::lookup_interface_method(Register recv_klass,
7352 Register intf_klass,
7353 RegisterOrConstant itable_index,
7354 Register method_result,
7355 Register scan_temp,
7356 Label& L_no_such_interface) {
7357 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
7358 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
7359 "caller must use same register for non-constant itable index as for method");
7360
7361 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
7362 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
7363 int itentry_off = itableMethodEntry::method_offset_in_bytes();
7364 int scan_step = itableOffsetEntry::size() * wordSize;
7365 int vte_size = vtableEntry::size() * wordSize;
7366 Address::ScaleFactor times_vte_scale = Address::times_ptr;
7367 assert(vte_size == wordSize, "else adjust times_vte_scale");
7368
7369 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
7370
7371 // %%% Could store the aligned, prescaled offset in the klassoop.
7372 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
7373 if (HeapWordsPerLong > 1) {
7374 // Round up to align_object_offset boundary
7375 // see code for instanceKlass::start_of_itable!
7376 round_to(scan_temp, BytesPerLong);
7377 }
7378
7379 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
7380 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
7381 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
7382
7383 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
7384 // if (scan->interface() == intf) {
7385 // result = (klass + scan->offset() + itable_index);
7386 // }
7387 // }
7388 Label search, found_method;
7389
7390 for (int peel = 1; peel >= 0; peel--) {
7391 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
7392 cmpptr(intf_klass, method_result);
7393
7394 if (peel) {
7395 jccb(Assembler::equal, found_method);
7396 } else {
7397 jccb(Assembler::notEqual, search);
7398 // (invert the test to fall through to found_method...)
7399 }
7400
7401 if (!peel) break;
7402
7403 bind(search);
7404
7405 // Check that the previous entry is non-null. A null entry means that
7406 // the receiver class doesn't implement the interface, and wasn't the
7407 // same as when the caller was compiled.
7408 testptr(method_result, method_result);
7409 jcc(Assembler::zero, L_no_such_interface);
7410 addptr(scan_temp, scan_step);
7411 }
7412
7413 bind(found_method);
7414
7415 // Got a hit.
7416 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
7417 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
7418 }
7419
7420
7421 void MacroAssembler::check_klass_subtype(Register sub_klass,
7422 Register super_klass,
7423 Register temp_reg,
7424 Label& L_success) {
7425 Label L_failure;
7426 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
7427 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
7428 bind(L_failure);
7429 }
7430
7431
7432 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
7433 Register super_klass,
7434 Register temp_reg,
7435 Label* L_success,
7436 Label* L_failure,
7437 Label* L_slow_path,
7438 RegisterOrConstant super_check_offset) {
7439 assert_different_registers(sub_klass, super_klass, temp_reg);
7440 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
7441 if (super_check_offset.is_register()) {
7442 assert_different_registers(sub_klass, super_klass,
7443 super_check_offset.as_register());
7444 } else if (must_load_sco) {
7445 assert(temp_reg != noreg, "supply either a temp or a register offset");
7446 }
7447
7448 Label L_fallthrough;
7449 int label_nulls = 0;
7450 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7451 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7452 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
7453 assert(label_nulls <= 1, "at most one NULL in the batch");
7454
7455 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7456 Klass::secondary_super_cache_offset_in_bytes());
7457 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
7458 Klass::super_check_offset_offset_in_bytes());
7459 Address super_check_offset_addr(super_klass, sco_offset);
7460
7461 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
7462 // range of a jccb. If this routine grows larger, reconsider at
7463 // least some of these.
7464 #define local_jcc(assembler_cond, label) \
7465 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
7466 else jcc( assembler_cond, label) /*omit semi*/
7467
7468 // Hacked jmp, which may only be used just before L_fallthrough.
7469 #define final_jmp(label) \
7470 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
7471 else jmp(label) /*omit semi*/
7472
7473 // If the pointers are equal, we are done (e.g., String[] elements).
7474 // This self-check enables sharing of secondary supertype arrays among
7475 // non-primary types such as array-of-interface. Otherwise, each such
7476 // type would need its own customized SSA.
7477 // We move this check to the front of the fast path because many
7478 // type checks are in fact trivially successful in this manner,
7479 // so we get a nicely predicted branch right at the start of the check.
7480 cmpptr(sub_klass, super_klass);
7481 local_jcc(Assembler::equal, *L_success);
7482
7483 // Check the supertype display:
7484 if (must_load_sco) {
7485 // Positive movl does right thing on LP64.
7486 movl(temp_reg, super_check_offset_addr);
7487 super_check_offset = RegisterOrConstant(temp_reg);
7488 }
7489 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
7490 cmpptr(super_klass, super_check_addr); // load displayed supertype
7491
7492 // This check has worked decisively for primary supers.
7493 // Secondary supers are sought in the super_cache ('super_cache_addr').
7494 // (Secondary supers are interfaces and very deeply nested subtypes.)
7495 // This works in the same check above because of a tricky aliasing
7496 // between the super_cache and the primary super display elements.
7497 // (The 'super_check_addr' can address either, as the case requires.)
7498 // Note that the cache is updated below if it does not help us find
7499 // what we need immediately.
7500 // So if it was a primary super, we can just fail immediately.
7501 // Otherwise, it's the slow path for us (no success at this point).
7502
7503 if (super_check_offset.is_register()) {
7504 local_jcc(Assembler::equal, *L_success);
7505 cmpl(super_check_offset.as_register(), sc_offset);
7506 if (L_failure == &L_fallthrough) {
7507 local_jcc(Assembler::equal, *L_slow_path);
7508 } else {
7509 local_jcc(Assembler::notEqual, *L_failure);
7510 final_jmp(*L_slow_path);
7511 }
7512 } else if (super_check_offset.as_constant() == sc_offset) {
7513 // Need a slow path; fast failure is impossible.
7514 if (L_slow_path == &L_fallthrough) {
7515 local_jcc(Assembler::equal, *L_success);
7516 } else {
7517 local_jcc(Assembler::notEqual, *L_slow_path);
7518 final_jmp(*L_success);
7519 }
7520 } else {
7521 // No slow path; it's a fast decision.
7522 if (L_failure == &L_fallthrough) {
7523 local_jcc(Assembler::equal, *L_success);
7524 } else {
7525 local_jcc(Assembler::notEqual, *L_failure);
7526 final_jmp(*L_success);
7527 }
7528 }
7529
7530 bind(L_fallthrough);
7531
7532 #undef local_jcc
7533 #undef final_jmp
7534 }
7535
7536
7537 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
7538 Register super_klass,
7539 Register temp_reg,
7540 Register temp2_reg,
7541 Label* L_success,
7542 Label* L_failure,
7543 bool set_cond_codes) {
7544 assert_different_registers(sub_klass, super_klass, temp_reg);
7545 if (temp2_reg != noreg)
7546 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
7547 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
7548
7549 Label L_fallthrough;
7550 int label_nulls = 0;
7551 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7552 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7553 assert(label_nulls <= 1, "at most one NULL in the batch");
7554
7555 // a couple of useful fields in sub_klass:
7556 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
7557 Klass::secondary_supers_offset_in_bytes());
7558 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7559 Klass::secondary_super_cache_offset_in_bytes());
7560 Address secondary_supers_addr(sub_klass, ss_offset);
7561 Address super_cache_addr( sub_klass, sc_offset);
7562
7563 // Do a linear scan of the secondary super-klass chain.
7564 // This code is rarely used, so simplicity is a virtue here.
7565 // The repne_scan instruction uses fixed registers, which we must spill.
7566 // Don't worry too much about pre-existing connections with the input regs.
7567
7568 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
7569 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
7570
7571 // Get super_klass value into rax (even if it was in rdi or rcx).
7572 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
7573 if (super_klass != rax || UseCompressedOops) {
7574 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
7575 mov(rax, super_klass);
7576 }
7577 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
7578 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
7579
7580 #ifndef PRODUCT
7581 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
7582 ExternalAddress pst_counter_addr((address) pst_counter);
7583 NOT_LP64( incrementl(pst_counter_addr) );
7584 LP64_ONLY( lea(rcx, pst_counter_addr) );
7585 LP64_ONLY( incrementl(Address(rcx, 0)) );
7586 #endif //PRODUCT
7587
7588 // We will consult the secondary-super array.
7589 movptr(rdi, secondary_supers_addr);
7590 // Load the array length. (Positive movl does right thing on LP64.)
7591 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
7592 // Skip to start of data.
7593 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7594
7595 // Scan RCX words at [RDI] for an occurrence of RAX.
7596 // Set NZ/Z based on last compare.
7597 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
7598 // not change flags (only scas instruction which is repeated sets flags).
7599 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
7600 #ifdef _LP64
7601 // This part is tricky, as values in supers array could be 32 or 64 bit wide
7602 // and we store values in objArrays always encoded, thus we need to encode
7603 // the value of rax before repne. Note that rax is dead after the repne.
7604 if (UseCompressedOops) {
7605 encode_heap_oop_not_null(rax); // Changes flags.
7606 // The superclass is never null; it would be a basic system error if a null
7607 // pointer were to sneak in here. Note that we have already loaded the
7608 // Klass::super_check_offset from the super_klass in the fast path,
7609 // so if there is a null in that register, we are already in the afterlife.
7610 testl(rax,rax); // Set Z = 0
7611 repne_scanl();
7612 } else
7613 #endif // _LP64
7614 {
7615 testptr(rax,rax); // Set Z = 0
7616 repne_scan();
7617 }
7618 // Unspill the temp. registers:
7619 if (pushed_rdi) pop(rdi);
7620 if (pushed_rcx) pop(rcx);
7621 if (pushed_rax) pop(rax);
7622
7623 if (set_cond_codes) {
7624 // Special hack for the AD files: rdi is guaranteed non-zero.
7625 assert(!pushed_rdi, "rdi must be left non-NULL");
7626 // Also, the condition codes are properly set Z/NZ on succeed/failure.
7627 }
7628
7629 if (L_failure == &L_fallthrough)
7630 jccb(Assembler::notEqual, *L_failure);
7631 else jcc(Assembler::notEqual, *L_failure);
7632
7633 // Success. Cache the super we found and proceed in triumph.
7634 movptr(super_cache_addr, super_klass);
7635
7636 if (L_success != &L_fallthrough) {
7637 jmp(*L_success);
7638 }
7639
7640 #undef IS_A_TEMP
7641
7642 bind(L_fallthrough);
7643 }
7644
7645
7646 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7647 ucomisd(dst, as_Address(src));
7648 }
7649
7650 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7651 ucomiss(dst, as_Address(src));
7652 }
7653
7654 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7655 if (reachable(src)) {
7656 xorpd(dst, as_Address(src));
7657 } else {
7658 lea(rscratch1, src);
7659 xorpd(dst, Address(rscratch1, 0));
7660 }
7661 }
7662
7663 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7664 if (reachable(src)) {
7665 xorps(dst, as_Address(src));
7666 } else {
7667 lea(rscratch1, src);
7668 xorps(dst, Address(rscratch1, 0));
7669 }
7670 }
7671
7672 void MacroAssembler::verify_oop(Register reg, const char* s) {
7673 if (!VerifyOops) return;
7674
7675 // Pass register number to verify_oop_subroutine
7676 char* b = new char[strlen(s) + 50];
7677 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
7678 #ifdef _LP64
7679 push(rscratch1); // save r10, trashed by movptr()
7680 #endif
7681 push(rax); // save rax,
7682 push(reg); // pass register argument
7683 ExternalAddress buffer((address) b);
7684 // avoid using pushptr, as it modifies scratch registers
7685 // and our contract is not to modify anything
7686 movptr(rax, buffer.addr());
7687 push(rax);
7688 // call indirectly to solve generation ordering problem
7689 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7690 call(rax);
7691 // Caller pops the arguments (oop, message) and restores rax, r10
7692 }
7693
7694
7695 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
7696 Register tmp,
7697 int offset) {
7698 intptr_t value = *delayed_value_addr;
7699 if (value != 0)
7700 return RegisterOrConstant(value + offset);
7701
7702 // load indirectly to solve generation ordering problem
7703 movptr(tmp, ExternalAddress((address) delayed_value_addr));
7704
7705 #ifdef ASSERT
7706 { Label L;
7707 testptr(tmp, tmp);
7708 if (WizardMode) {
7709 jcc(Assembler::notZero, L);
7710 char* buf = new char[40];
7711 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
7712 stop(buf);
7713 } else {
7714 jccb(Assembler::notZero, L);
7715 hlt();
7716 }
7717 bind(L);
7718 }
7719 #endif
7720
7721 if (offset != 0)
7722 addptr(tmp, offset);
7723
7724 return RegisterOrConstant(tmp);
7725 }
7726
7727
7728 // registers on entry:
7729 // - rax ('check' register): required MethodType
7730 // - rcx: method handle
7731 // - rdx, rsi, or ?: killable temp
7732 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
7733 Register temp_reg,
7734 Label& wrong_method_type) {
7735 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg));
7736 // compare method type against that of the receiver
7737 if (UseCompressedOops) {
7738 load_heap_oop(temp_reg, type_addr);
7739 cmpptr(mtype_reg, temp_reg);
7740 } else {
7741 cmpptr(mtype_reg, type_addr);
7742 }
7743 jcc(Assembler::notEqual, wrong_method_type);
7744 }
7745
7746
7747 // A method handle has a "vmslots" field which gives the size of its
7748 // argument list in JVM stack slots. This field is either located directly
7749 // in every method handle, or else is indirectly accessed through the
7750 // method handle's MethodType. This macro hides the distinction.
7751 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
7752 Register temp_reg) {
7753 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
7754 // load mh.type.form.vmslots
7755 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
7756 // hoist vmslots into every mh to avoid dependent load chain
7757 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)));
7758 } else {
7759 Register temp2_reg = vmslots_reg;
7760 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)));
7761 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)));
7762 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
7763 }
7764 }
7765
7766
7767 // registers on entry:
7768 // - rcx: method handle
7769 // - rdx: killable temp (interpreted only)
7770 // - rax: killable temp (compiled only)
7771 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
7772 assert(mh_reg == rcx, "caller must put MH object in rcx");
7773 assert_different_registers(mh_reg, temp_reg);
7774
7775 // pick out the interpreted side of the handler
7776 // NOTE: vmentry is not an oop!
7777 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
7778
7779 // off we go...
7780 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
7781
7782 // for the various stubs which take control at this point,
7783 // see MethodHandles::generate_method_handle_stub
7784 }
7785
7786
7787 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
7788 int extra_slot_offset) {
7789 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
7790 int stackElementSize = Interpreter::stackElementSize;
7791 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
7792 #ifdef ASSERT
7793 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
7794 assert(offset1 - offset == stackElementSize, "correct arithmetic");
7795 #endif
7796 Register scale_reg = noreg;
7797 Address::ScaleFactor scale_factor = Address::no_scale;
7798 if (arg_slot.is_constant()) {
7799 offset += arg_slot.as_constant() * stackElementSize;
7800 } else {
7801 scale_reg = arg_slot.as_register();
7802 scale_factor = Address::times(stackElementSize);
7803 }
7804 offset += wordSize; // return PC is on stack
7805 return Address(rsp, scale_reg, scale_factor, offset);
7806 }
7807
7808
7809 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
7810 if (!VerifyOops) return;
7811
7812 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
7813 // Pass register number to verify_oop_subroutine
7814 char* b = new char[strlen(s) + 50];
7815 sprintf(b, "verify_oop_addr: %s", s);
7816
7817 #ifdef _LP64
7818 push(rscratch1); // save r10, trashed by movptr()
7819 #endif
7820 push(rax); // save rax,
7821 // addr may contain rsp so we will have to adjust it based on the push
7822 // we just did
7823 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
7824 // stores rax into addr which is backwards of what was intended.
7825 if (addr.uses(rsp)) {
7826 lea(rax, addr);
7827 pushptr(Address(rax, BytesPerWord));
7828 } else {
7829 pushptr(addr);
7830 }
7831
7832 ExternalAddress buffer((address) b);
7833 // pass msg argument
7834 // avoid using pushptr, as it modifies scratch registers
7835 // and our contract is not to modify anything
7836 movptr(rax, buffer.addr());
7837 push(rax);
7838
7839 // call indirectly to solve generation ordering problem
7840 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7841 call(rax);
7842 // Caller pops the arguments (addr, message) and restores rax, r10.
7843 }
7844
7845 void MacroAssembler::verify_tlab() {
7846 #ifdef ASSERT
7847 if (UseTLAB && VerifyOops) {
7848 Label next, ok;
7849 Register t1 = rsi;
7850 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
7851
7852 push(t1);
7853 NOT_LP64(push(thread_reg));
7854 NOT_LP64(get_thread(thread_reg));
7855
7856 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7857 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7858 jcc(Assembler::aboveEqual, next);
7859 stop("assert(top >= start)");
7860 should_not_reach_here();
7861
7862 bind(next);
7863 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7864 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7865 jcc(Assembler::aboveEqual, ok);
7866 stop("assert(top <= end)");
7867 should_not_reach_here();
7868
7869 bind(ok);
7870 NOT_LP64(pop(thread_reg));
7871 pop(t1);
7872 }
7873 #endif
7874 }
7875
7876 class ControlWord {
7877 public:
7878 int32_t _value;
7879
7880 int rounding_control() const { return (_value >> 10) & 3 ; }
7881 int precision_control() const { return (_value >> 8) & 3 ; }
7882 bool precision() const { return ((_value >> 5) & 1) != 0; }
7883 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7884 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7885 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7886 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7887 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7888
7889 void print() const {
7890 // rounding control
7891 const char* rc;
7892 switch (rounding_control()) {
7893 case 0: rc = "round near"; break;
7894 case 1: rc = "round down"; break;
7895 case 2: rc = "round up "; break;
7896 case 3: rc = "chop "; break;
7897 };
7898 // precision control
7899 const char* pc;
7900 switch (precision_control()) {
7901 case 0: pc = "24 bits "; break;
7902 case 1: pc = "reserved"; break;
7903 case 2: pc = "53 bits "; break;
7904 case 3: pc = "64 bits "; break;
7905 };
7906 // flags
7907 char f[9];
7908 f[0] = ' ';
7909 f[1] = ' ';
7910 f[2] = (precision ()) ? 'P' : 'p';
7911 f[3] = (underflow ()) ? 'U' : 'u';
7912 f[4] = (overflow ()) ? 'O' : 'o';
7913 f[5] = (zero_divide ()) ? 'Z' : 'z';
7914 f[6] = (denormalized()) ? 'D' : 'd';
7915 f[7] = (invalid ()) ? 'I' : 'i';
7916 f[8] = '\x0';
7917 // output
7918 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
7919 }
7920
7921 };
7922
7923 class StatusWord {
7924 public:
7925 int32_t _value;
7926
7927 bool busy() const { return ((_value >> 15) & 1) != 0; }
7928 bool C3() const { return ((_value >> 14) & 1) != 0; }
7929 bool C2() const { return ((_value >> 10) & 1) != 0; }
7930 bool C1() const { return ((_value >> 9) & 1) != 0; }
7931 bool C0() const { return ((_value >> 8) & 1) != 0; }
7932 int top() const { return (_value >> 11) & 7 ; }
7933 bool error_status() const { return ((_value >> 7) & 1) != 0; }
7934 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
7935 bool precision() const { return ((_value >> 5) & 1) != 0; }
7936 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7937 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7938 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7939 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7940 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7941
7942 void print() const {
7943 // condition codes
7944 char c[5];
7945 c[0] = (C3()) ? '3' : '-';
7946 c[1] = (C2()) ? '2' : '-';
7947 c[2] = (C1()) ? '1' : '-';
7948 c[3] = (C0()) ? '0' : '-';
7949 c[4] = '\x0';
7950 // flags
7951 char f[9];
7952 f[0] = (error_status()) ? 'E' : '-';
7953 f[1] = (stack_fault ()) ? 'S' : '-';
7954 f[2] = (precision ()) ? 'P' : '-';
7955 f[3] = (underflow ()) ? 'U' : '-';
7956 f[4] = (overflow ()) ? 'O' : '-';
7957 f[5] = (zero_divide ()) ? 'Z' : '-';
7958 f[6] = (denormalized()) ? 'D' : '-';
7959 f[7] = (invalid ()) ? 'I' : '-';
7960 f[8] = '\x0';
7961 // output
7962 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
7963 }
7964
7965 };
7966
7967 class TagWord {
7968 public:
7969 int32_t _value;
7970
7971 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
7972
7973 void print() const {
7974 printf("%04x", _value & 0xFFFF);
7975 }
7976
7977 };
7978
7979 class FPU_Register {
7980 public:
7981 int32_t _m0;
7982 int32_t _m1;
7983 int16_t _ex;
7984
7985 bool is_indefinite() const {
7986 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
7987 }
7988
7989 void print() const {
7990 char sign = (_ex < 0) ? '-' : '+';
7991 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
7992 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
7993 };
7994
7995 };
7996
7997 class FPU_State {
7998 public:
7999 enum {
8000 register_size = 10,
8001 number_of_registers = 8,
8002 register_mask = 7
8003 };
8004
8005 ControlWord _control_word;
8006 StatusWord _status_word;
8007 TagWord _tag_word;
8008 int32_t _error_offset;
8009 int32_t _error_selector;
8010 int32_t _data_offset;
8011 int32_t _data_selector;
8012 int8_t _register[register_size * number_of_registers];
8013
8014 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
8015 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
8016
8017 const char* tag_as_string(int tag) const {
8018 switch (tag) {
8019 case 0: return "valid";
8020 case 1: return "zero";
8021 case 2: return "special";
8022 case 3: return "empty";
8023 }
8024 ShouldNotReachHere();
8025 return NULL;
8026 }
8027
8028 void print() const {
8029 // print computation registers
8030 { int t = _status_word.top();
8031 for (int i = 0; i < number_of_registers; i++) {
8032 int j = (i - t) & register_mask;
8033 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
8034 st(j)->print();
8035 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
8036 }
8037 }
8038 printf("\n");
8039 // print control registers
8040 printf("ctrl = "); _control_word.print(); printf("\n");
8041 printf("stat = "); _status_word .print(); printf("\n");
8042 printf("tags = "); _tag_word .print(); printf("\n");
8043 }
8044
8045 };
8046
8047 class Flag_Register {
8048 public:
8049 int32_t _value;
8050
8051 bool overflow() const { return ((_value >> 11) & 1) != 0; }
8052 bool direction() const { return ((_value >> 10) & 1) != 0; }
8053 bool sign() const { return ((_value >> 7) & 1) != 0; }
8054 bool zero() const { return ((_value >> 6) & 1) != 0; }
8055 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8056 bool parity() const { return ((_value >> 2) & 1) != 0; }
8057 bool carry() const { return ((_value >> 0) & 1) != 0; }
8058
8059 void print() const {
8060 // flags
8061 char f[8];
8062 f[0] = (overflow ()) ? 'O' : '-';
8063 f[1] = (direction ()) ? 'D' : '-';
8064 f[2] = (sign ()) ? 'S' : '-';
8065 f[3] = (zero ()) ? 'Z' : '-';
8066 f[4] = (auxiliary_carry()) ? 'A' : '-';
8067 f[5] = (parity ()) ? 'P' : '-';
8068 f[6] = (carry ()) ? 'C' : '-';
8069 f[7] = '\x0';
8070 // output
8071 printf("%08x flags = %s", _value, f);
8072 }
8073
8074 };
8075
8076 class IU_Register {
8077 public:
8078 int32_t _value;
8079
8080 void print() const {
8081 printf("%08x %11d", _value, _value);
8082 }
8083
8084 };
8085
8086 class IU_State {
8087 public:
8088 Flag_Register _eflags;
8089 IU_Register _rdi;
8090 IU_Register _rsi;
8091 IU_Register _rbp;
8092 IU_Register _rsp;
8093 IU_Register _rbx;
8094 IU_Register _rdx;
8095 IU_Register _rcx;
8096 IU_Register _rax;
8097
8098 void print() const {
8099 // computation registers
8100 printf("rax, = "); _rax.print(); printf("\n");
8101 printf("rbx, = "); _rbx.print(); printf("\n");
8102 printf("rcx = "); _rcx.print(); printf("\n");
8103 printf("rdx = "); _rdx.print(); printf("\n");
8104 printf("rdi = "); _rdi.print(); printf("\n");
8105 printf("rsi = "); _rsi.print(); printf("\n");
8106 printf("rbp, = "); _rbp.print(); printf("\n");
8107 printf("rsp = "); _rsp.print(); printf("\n");
8108 printf("\n");
8109 // control registers
8110 printf("flgs = "); _eflags.print(); printf("\n");
8111 }
8112 };
8113
8114
8115 class CPU_State {
8116 public:
8117 FPU_State _fpu_state;
8118 IU_State _iu_state;
8119
8120 void print() const {
8121 printf("--------------------------------------------------\n");
8122 _iu_state .print();
8123 printf("\n");
8124 _fpu_state.print();
8125 printf("--------------------------------------------------\n");
8126 }
8127
8128 };
8129
8130
8131 static void _print_CPU_state(CPU_State* state) {
8132 state->print();
8133 };
8134
8135
8136 void MacroAssembler::print_CPU_state() {
8137 push_CPU_state();
8138 push(rsp); // pass CPU state
8139 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8140 addptr(rsp, wordSize); // discard argument
8141 pop_CPU_state();
8142 }
8143
8144
8145 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8146 static int counter = 0;
8147 FPU_State* fs = &state->_fpu_state;
8148 counter++;
8149 // For leaf calls, only verify that the top few elements remain empty.
8150 // We only need 1 empty at the top for C2 code.
8151 if( stack_depth < 0 ) {
8152 if( fs->tag_for_st(7) != 3 ) {
8153 printf("FPR7 not empty\n");
8154 state->print();
8155 assert(false, "error");
8156 return false;
8157 }
8158 return true; // All other stack states do not matter
8159 }
8160
8161 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8162 "bad FPU control word");
8163
8164 // compute stack depth
8165 int i = 0;
8166 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8167 int d = i;
8168 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8169 // verify findings
8170 if (i != FPU_State::number_of_registers) {
8171 // stack not contiguous
8172 printf("%s: stack not contiguous at ST%d\n", s, i);
8173 state->print();
8174 assert(false, "error");
8175 return false;
8176 }
8177 // check if computed stack depth corresponds to expected stack depth
8178 if (stack_depth < 0) {
8179 // expected stack depth is -stack_depth or less
8180 if (d > -stack_depth) {
8181 // too many elements on the stack
8182 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8183 state->print();
8184 assert(false, "error");
8185 return false;
8186 }
8187 } else {
8188 // expected stack depth is stack_depth
8189 if (d != stack_depth) {
8190 // wrong stack depth
8191 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
8192 state->print();
8193 assert(false, "error");
8194 return false;
8195 }
8196 }
8197 // everything is cool
8198 return true;
8199 }
8200
8201
8202 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
8203 if (!VerifyFPU) return;
8204 push_CPU_state();
8205 push(rsp); // pass CPU state
8206 ExternalAddress msg((address) s);
8207 // pass message string s
8208 pushptr(msg.addr());
8209 push(stack_depth); // pass stack depth
8210 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
8211 addptr(rsp, 3 * wordSize); // discard arguments
8212 // check for error
8213 { Label L;
8214 testl(rax, rax);
8215 jcc(Assembler::notZero, L);
8216 int3(); // break if error condition
8217 bind(L);
8218 }
8219 pop_CPU_state();
8220 }
8221
8222 void MacroAssembler::load_klass(Register dst, Register src) {
8223 #ifdef _LP64
8224 if (UseCompressedOops) {
8225 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8226 decode_heap_oop_not_null(dst);
8227 } else
8228 #endif
8229 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8230 }
8231
8232 void MacroAssembler::load_prototype_header(Register dst, Register src) {
8233 #ifdef _LP64
8234 if (UseCompressedOops) {
8235 assert (Universe::heap() != NULL, "java heap should be initialized");
8236 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8237 if (Universe::narrow_oop_shift() != 0) {
8238 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8239 if (LogMinObjAlignmentInBytes == Address::times_8) {
8240 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8241 } else {
8242 // OK to use shift since we don't need to preserve flags.
8243 shlq(dst, LogMinObjAlignmentInBytes);
8244 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8245 }
8246 } else {
8247 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8248 }
8249 } else
8250 #endif
8251 {
8252 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8253 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8254 }
8255 }
8256
8257 void MacroAssembler::store_klass(Register dst, Register src) {
8258 #ifdef _LP64
8259 if (UseCompressedOops) {
8260 encode_heap_oop_not_null(src);
8261 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8262 } else
8263 #endif
8264 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8265 }
8266
8267 void MacroAssembler::load_heap_oop(Register dst, Address src) {
8268 #ifdef _LP64
8269 if (UseCompressedOops) {
8270 movl(dst, src);
8271 decode_heap_oop(dst);
8272 } else
8273 #endif
8274 movptr(dst, src);
8275 }
8276
8277 void MacroAssembler::store_heap_oop(Address dst, Register src) {
8278 #ifdef _LP64
8279 if (UseCompressedOops) {
8280 assert(!dst.uses(src), "not enough registers");
8281 encode_heap_oop(src);
8282 movl(dst, src);
8283 } else
8284 #endif
8285 movptr(dst, src);
8286 }
8287
8288 // Used for storing NULLs.
8289 void MacroAssembler::store_heap_oop_null(Address dst) {
8290 #ifdef _LP64
8291 if (UseCompressedOops) {
8292 movl(dst, (int32_t)NULL_WORD);
8293 } else {
8294 movslq(dst, (int32_t)NULL_WORD);
8295 }
8296 #else
8297 movl(dst, (int32_t)NULL_WORD);
8298 #endif
8299 }
8300
8301 #ifdef _LP64
8302 void MacroAssembler::store_klass_gap(Register dst, Register src) {
8303 if (UseCompressedOops) {
8304 // Store to klass gap in destination
8305 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
8306 }
8307 }
8308
8309 #ifdef ASSERT
8310 void MacroAssembler::verify_heapbase(const char* msg) {
8311 assert (UseCompressedOops, "should be compressed");
8312 assert (Universe::heap() != NULL, "java heap should be initialized");
8313 if (CheckCompressedOops) {
8314 Label ok;
8315 push(rscratch1); // cmpptr trashes rscratch1
8316 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8317 jcc(Assembler::equal, ok);
8318 stop(msg);
8319 bind(ok);
8320 pop(rscratch1);
8321 }
8322 }
8323 #endif
8324
8325 // Algorithm must match oop.inline.hpp encode_heap_oop.
8326 void MacroAssembler::encode_heap_oop(Register r) {
8327 #ifdef ASSERT
8328 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
8329 #endif
8330 verify_oop(r, "broken oop in encode_heap_oop");
8331 if (Universe::narrow_oop_base() == NULL) {
8332 if (Universe::narrow_oop_shift() != 0) {
8333 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8334 shrq(r, LogMinObjAlignmentInBytes);
8335 }
8336 return;
8337 }
8338 testq(r, r);
8339 cmovq(Assembler::equal, r, r12_heapbase);
8340 subq(r, r12_heapbase);
8341 shrq(r, LogMinObjAlignmentInBytes);
8342 }
8343
8344 void MacroAssembler::encode_heap_oop_not_null(Register r) {
8345 #ifdef ASSERT
8346 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
8347 if (CheckCompressedOops) {
8348 Label ok;
8349 testq(r, r);
8350 jcc(Assembler::notEqual, ok);
8351 stop("null oop passed to encode_heap_oop_not_null");
8352 bind(ok);
8353 }
8354 #endif
8355 verify_oop(r, "broken oop in encode_heap_oop_not_null");
8356 if (Universe::narrow_oop_base() != NULL) {
8357 subq(r, r12_heapbase);
8358 }
8359 if (Universe::narrow_oop_shift() != 0) {
8360 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8361 shrq(r, LogMinObjAlignmentInBytes);
8362 }
8363 }
8364
8365 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
8366 #ifdef ASSERT
8367 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
8368 if (CheckCompressedOops) {
8369 Label ok;
8370 testq(src, src);
8371 jcc(Assembler::notEqual, ok);
8372 stop("null oop passed to encode_heap_oop_not_null2");
8373 bind(ok);
8374 }
8375 #endif
8376 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
8377 if (dst != src) {
8378 movq(dst, src);
8379 }
8380 if (Universe::narrow_oop_base() != NULL) {
8381 subq(dst, r12_heapbase);
8382 }
8383 if (Universe::narrow_oop_shift() != 0) {
8384 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8385 shrq(dst, LogMinObjAlignmentInBytes);
8386 }
8387 }
8388
8389 void MacroAssembler::decode_heap_oop(Register r) {
8390 #ifdef ASSERT
8391 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
8392 #endif
8393 if (Universe::narrow_oop_base() == NULL) {
8394 if (Universe::narrow_oop_shift() != 0) {
8395 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8396 shlq(r, LogMinObjAlignmentInBytes);
8397 }
8398 } else {
8399 Label done;
8400 shlq(r, LogMinObjAlignmentInBytes);
8401 jccb(Assembler::equal, done);
8402 addq(r, r12_heapbase);
8403 bind(done);
8404 }
8405 verify_oop(r, "broken oop in decode_heap_oop");
8406 }
8407
8408 void MacroAssembler::decode_heap_oop_not_null(Register r) {
8409 // Note: it will change flags
8410 assert (UseCompressedOops, "should only be used for compressed headers");
8411 assert (Universe::heap() != NULL, "java heap should be initialized");
8412 // Cannot assert, unverified entry point counts instructions (see .ad file)
8413 // vtableStubs also counts instructions in pd_code_size_limit.
8414 // Also do not verify_oop as this is called by verify_oop.
8415 if (Universe::narrow_oop_shift() != 0) {
8416 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8417 shlq(r, LogMinObjAlignmentInBytes);
8418 if (Universe::narrow_oop_base() != NULL) {
8419 addq(r, r12_heapbase);
8420 }
8421 } else {
8422 assert (Universe::narrow_oop_base() == NULL, "sanity");
8423 }
8424 }
8425
8426 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
8427 // Note: it will change flags
8428 assert (UseCompressedOops, "should only be used for compressed headers");
8429 assert (Universe::heap() != NULL, "java heap should be initialized");
8430 // Cannot assert, unverified entry point counts instructions (see .ad file)
8431 // vtableStubs also counts instructions in pd_code_size_limit.
8432 // Also do not verify_oop as this is called by verify_oop.
8433 if (Universe::narrow_oop_shift() != 0) {
8434 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8435 if (LogMinObjAlignmentInBytes == Address::times_8) {
8436 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
8437 } else {
8438 if (dst != src) {
8439 movq(dst, src);
8440 }
8441 shlq(dst, LogMinObjAlignmentInBytes);
8442 if (Universe::narrow_oop_base() != NULL) {
8443 addq(dst, r12_heapbase);
8444 }
8445 }
8446 } else {
8447 assert (Universe::narrow_oop_base() == NULL, "sanity");
8448 if (dst != src) {
8449 movq(dst, src);
8450 }
8451 }
8452 }
8453
8454 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
8455 assert (UseCompressedOops, "should only be used for compressed headers");
8456 assert (Universe::heap() != NULL, "java heap should be initialized");
8457 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8458 int oop_index = oop_recorder()->find_index(obj);
8459 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8460 mov_narrow_oop(dst, oop_index, rspec);
8461 }
8462
8463 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
8464 assert (UseCompressedOops, "should only be used for compressed headers");
8465 assert (Universe::heap() != NULL, "java heap should be initialized");
8466 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8467 int oop_index = oop_recorder()->find_index(obj);
8468 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8469 mov_narrow_oop(dst, oop_index, rspec);
8470 }
8471
8472 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
8473 assert (UseCompressedOops, "should only be used for compressed headers");
8474 assert (Universe::heap() != NULL, "java heap should be initialized");
8475 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8476 int oop_index = oop_recorder()->find_index(obj);
8477 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8478 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8479 }
8480
8481 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
8482 assert (UseCompressedOops, "should only be used for compressed headers");
8483 assert (Universe::heap() != NULL, "java heap should be initialized");
8484 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8485 int oop_index = oop_recorder()->find_index(obj);
8486 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8487 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8488 }
8489
8490 void MacroAssembler::reinit_heapbase() {
8491 if (UseCompressedOops) {
8492 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8493 }
8494 }
8495 #endif // _LP64
8496
8497 // IndexOf substring.
8498 void MacroAssembler::string_indexof(Register str1, Register str2,
8499 Register cnt1, Register cnt2, Register result,
8500 XMMRegister vec, Register tmp) {
8501 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8502
8503 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
8504 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP;
8505
8506 push(str1); // string addr
8507 push(str2); // substr addr
8508 push(cnt2); // substr count
8509 jmpb(PREP_FOR_SCAN);
8510
8511 // Substr count saved at sp
8512 // Substr saved at sp+1*wordSize
8513 // String saved at sp+2*wordSize
8514
8515 // Reload substr for rescan
8516 bind(RELOAD_SUBSTR);
8517 movl(cnt2, Address(rsp, 0));
8518 movptr(str2, Address(rsp, wordSize));
8519 // We came here after the beginninig of the substring was
8520 // matched but the rest of it was not so we need to search
8521 // again. Start from the next element after the previous match.
8522 subptr(str1, result); // Restore counter
8523 shrl(str1, 1);
8524 addl(cnt1, str1);
8525 decrementl(cnt1);
8526 lea(str1, Address(result, 2)); // Reload string
8527
8528 // Load substr
8529 bind(PREP_FOR_SCAN);
8530 movdqu(vec, Address(str2, 0));
8531 addl(cnt1, 8); // prime the loop
8532 subptr(str1, 16);
8533
8534 // Scan string for substr in 16-byte vectors
8535 bind(SCAN_TO_SUBSTR);
8536 subl(cnt1, 8);
8537 addptr(str1, 16);
8538
8539 // pcmpestri
8540 // inputs:
8541 // xmm - substring
8542 // rax - substring length (elements count)
8543 // mem - scaned string
8544 // rdx - string length (elements count)
8545 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8546 // outputs:
8547 // rcx - matched index in string
8548 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8549
8550 pcmpestri(vec, Address(str1, 0), 0x0d);
8551 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
8552 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
8553
8554 // Fallthrough: found a potential substr
8555
8556 // Make sure string is still long enough
8557 subl(cnt1, tmp);
8558 cmpl(cnt1, cnt2);
8559 jccb(Assembler::negative, RET_NOT_FOUND);
8560 // Compute start addr of substr
8561 lea(str1, Address(str1, tmp, Address::times_2));
8562 movptr(result, str1); // save
8563
8564 // Compare potential substr
8565 addl(cnt1, 8); // prime the loop
8566 addl(cnt2, 8);
8567 subptr(str1, 16);
8568 subptr(str2, 16);
8569
8570 // Scan 16-byte vectors of string and substr
8571 bind(SCAN_SUBSTR);
8572 subl(cnt1, 8);
8573 subl(cnt2, 8);
8574 addptr(str1, 16);
8575 addptr(str2, 16);
8576 movdqu(vec, Address(str2, 0));
8577 pcmpestri(vec, Address(str1, 0), 0x0d);
8578 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
8579 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
8580
8581 // Compute substr offset
8582 subptr(result, Address(rsp, 2*wordSize));
8583 shrl(result, 1); // index
8584 jmpb(CLEANUP);
8585
8586 bind(RET_NOT_FOUND);
8587 movl(result, -1);
8588
8589 bind(CLEANUP);
8590 addptr(rsp, 3*wordSize);
8591 }
8592
8593 // Compare strings.
8594 void MacroAssembler::string_compare(Register str1, Register str2,
8595 Register cnt1, Register cnt2, Register result,
8596 XMMRegister vec1, XMMRegister vec2) {
8597 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
8598
8599 // Compute the minimum of the string lengths and the
8600 // difference of the string lengths (stack).
8601 // Do the conditional move stuff
8602 movl(result, cnt1);
8603 subl(cnt1, cnt2);
8604 push(cnt1);
8605 if (VM_Version::supports_cmov()) {
8606 cmovl(Assembler::lessEqual, cnt2, result);
8607 } else {
8608 Label GT_LABEL;
8609 jccb(Assembler::greater, GT_LABEL);
8610 movl(cnt2, result);
8611 bind(GT_LABEL);
8612 }
8613
8614 // Is the minimum length zero?
8615 testl(cnt2, cnt2);
8616 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8617
8618 // Load first characters
8619 load_unsigned_short(result, Address(str1, 0));
8620 load_unsigned_short(cnt1, Address(str2, 0));
8621
8622 // Compare first characters
8623 subl(result, cnt1);
8624 jcc(Assembler::notZero, POP_LABEL);
8625 decrementl(cnt2);
8626 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8627
8628 {
8629 // Check after comparing first character to see if strings are equivalent
8630 Label LSkip2;
8631 // Check if the strings start at same location
8632 cmpptr(str1, str2);
8633 jccb(Assembler::notEqual, LSkip2);
8634
8635 // Check if the length difference is zero (from stack)
8636 cmpl(Address(rsp, 0), 0x0);
8637 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
8638
8639 // Strings might not be equivalent
8640 bind(LSkip2);
8641 }
8642
8643 // Advance to next character
8644 addptr(str1, 2);
8645 addptr(str2, 2);
8646
8647 if (UseSSE42Intrinsics) {
8648 // With SSE4.2, use double quad vector compare
8649 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8650 // Setup to compare 16-byte vectors
8651 movl(cnt1, cnt2);
8652 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count
8653 andl(cnt1, 0x00000007); // cnt1 holds the tail count
8654 testl(cnt2, cnt2);
8655 jccb(Assembler::zero, COMPARE_TAIL);
8656
8657 lea(str2, Address(str2, cnt2, Address::times_2));
8658 lea(str1, Address(str1, cnt2, Address::times_2));
8659 negptr(cnt2);
8660
8661 bind(COMPARE_VECTORS);
8662 movdqu(vec1, Address(str1, cnt2, Address::times_2));
8663 movdqu(vec2, Address(str2, cnt2, Address::times_2));
8664 pxor(vec1, vec2);
8665 ptest(vec1, vec1);
8666 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
8667 addptr(cnt2, 8);
8668 jcc(Assembler::notZero, COMPARE_VECTORS);
8669 jmpb(COMPARE_TAIL);
8670
8671 // Mismatched characters in the vectors
8672 bind(VECTOR_NOT_EQUAL);
8673 lea(str1, Address(str1, cnt2, Address::times_2));
8674 lea(str2, Address(str2, cnt2, Address::times_2));
8675 movl(cnt1, 8);
8676
8677 // Compare tail (< 8 chars), or rescan last vectors to
8678 // find 1st mismatched characters
8679 bind(COMPARE_TAIL);
8680 testl(cnt1, cnt1);
8681 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8682 movl(cnt2, cnt1);
8683 // Fallthru to tail compare
8684 }
8685
8686 // Shift str2 and str1 to the end of the arrays, negate min
8687 lea(str1, Address(str1, cnt2, Address::times_2, 0));
8688 lea(str2, Address(str2, cnt2, Address::times_2, 0));
8689 negptr(cnt2);
8690
8691 // Compare the rest of the characters
8692 bind(WHILE_HEAD_LABEL);
8693 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0));
8694 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0));
8695 subl(result, cnt1);
8696 jccb(Assembler::notZero, POP_LABEL);
8697 increment(cnt2);
8698 jcc(Assembler::notZero, WHILE_HEAD_LABEL);
8699
8700 // Strings are equal up to min length. Return the length difference.
8701 bind(LENGTH_DIFF_LABEL);
8702 pop(result);
8703 jmpb(DONE_LABEL);
8704
8705 // Discard the stored length difference
8706 bind(POP_LABEL);
8707 addptr(rsp, wordSize);
8708
8709 // That's it
8710 bind(DONE_LABEL);
8711 }
8712
8713 // Compare char[] arrays aligned to 4 bytes or substrings.
8714 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8715 Register limit, Register result, Register chr,
8716 XMMRegister vec1, XMMRegister vec2) {
8717 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
8718
8719 int length_offset = arrayOopDesc::length_offset_in_bytes();
8720 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
8721
8722 // Check the input args
8723 cmpptr(ary1, ary2);
8724 jcc(Assembler::equal, TRUE_LABEL);
8725
8726 if (is_array_equ) {
8727 // Need additional checks for arrays_equals.
8728 testptr(ary1, ary1);
8729 jcc(Assembler::zero, FALSE_LABEL);
8730 testptr(ary2, ary2);
8731 jcc(Assembler::zero, FALSE_LABEL);
8732
8733 // Check the lengths
8734 movl(limit, Address(ary1, length_offset));
8735 cmpl(limit, Address(ary2, length_offset));
8736 jcc(Assembler::notEqual, FALSE_LABEL);
8737 }
8738
8739 // count == 0
8740 testl(limit, limit);
8741 jcc(Assembler::zero, TRUE_LABEL);
8742
8743 if (is_array_equ) {
8744 // Load array address
8745 lea(ary1, Address(ary1, base_offset));
8746 lea(ary2, Address(ary2, base_offset));
8747 }
8748
8749 shll(limit, 1); // byte count != 0
8750 movl(result, limit); // copy
8751
8752 if (UseSSE42Intrinsics) {
8753 // With SSE4.2, use double quad vector compare
8754 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8755 // Compare 16-byte vectors
8756 andl(result, 0x0000000e); // tail count (in bytes)
8757 andl(limit, 0xfffffff0); // vector count (in bytes)
8758 jccb(Assembler::zero, COMPARE_TAIL);
8759
8760 lea(ary1, Address(ary1, limit, Address::times_1));
8761 lea(ary2, Address(ary2, limit, Address::times_1));
8762 negptr(limit);
8763
8764 bind(COMPARE_WIDE_VECTORS);
8765 movdqu(vec1, Address(ary1, limit, Address::times_1));
8766 movdqu(vec2, Address(ary2, limit, Address::times_1));
8767 pxor(vec1, vec2);
8768 ptest(vec1, vec1);
8769 jccb(Assembler::notZero, FALSE_LABEL);
8770 addptr(limit, 16);
8771 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8772
8773 bind(COMPARE_TAIL); // limit is zero
8774 movl(limit, result);
8775 // Fallthru to tail compare
8776 }
8777
8778 // Compare 4-byte vectors
8779 andl(limit, 0xfffffffc); // vector count (in bytes)
8780 jccb(Assembler::zero, COMPARE_CHAR);
8781
8782 lea(ary1, Address(ary1, limit, Address::times_1));
8783 lea(ary2, Address(ary2, limit, Address::times_1));
8784 negptr(limit);
8785
8786 bind(COMPARE_VECTORS);
8787 movl(chr, Address(ary1, limit, Address::times_1));
8788 cmpl(chr, Address(ary2, limit, Address::times_1));
8789 jccb(Assembler::notEqual, FALSE_LABEL);
8790 addptr(limit, 4);
8791 jcc(Assembler::notZero, COMPARE_VECTORS);
8792
8793 // Compare trailing char (final 2 bytes), if any
8794 bind(COMPARE_CHAR);
8795 testl(result, 0x2); // tail char
8796 jccb(Assembler::zero, TRUE_LABEL);
8797 load_unsigned_short(chr, Address(ary1, 0));
8798 load_unsigned_short(limit, Address(ary2, 0));
8799 cmpl(chr, limit);
8800 jccb(Assembler::notEqual, FALSE_LABEL);
8801
8802 bind(TRUE_LABEL);
8803 movl(result, 1); // return true
8804 jmpb(DONE);
8805
8806 bind(FALSE_LABEL);
8807 xorl(result, result); // return false
8808
8809 // That's it
8810 bind(DONE);
8811 }
8812
8813 #ifdef PRODUCT
8814 #define BLOCK_COMMENT(str) /* nothing */
8815 #else
8816 #define BLOCK_COMMENT(str) block_comment(str)
8817 #endif
8818
8819 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
8820 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8821 Register to, Register value, Register count,
8822 Register rtmp, XMMRegister xtmp) {
8823 assert_different_registers(to, value, count, rtmp);
8824 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8825 Label L_fill_2_bytes, L_fill_4_bytes;
8826
8827 int shift = -1;
8828 switch (t) {
8829 case T_BYTE:
8830 shift = 2;
8831 break;
8832 case T_SHORT:
8833 shift = 1;
8834 break;
8835 case T_INT:
8836 shift = 0;
8837 break;
8838 default: ShouldNotReachHere();
8839 }
8840
8841 if (t == T_BYTE) {
8842 andl(value, 0xff);
8843 movl(rtmp, value);
8844 shll(rtmp, 8);
8845 orl(value, rtmp);
8846 }
8847 if (t == T_SHORT) {
8848 andl(value, 0xffff);
8849 }
8850 if (t == T_BYTE || t == T_SHORT) {
8851 movl(rtmp, value);
8852 shll(rtmp, 16);
8853 orl(value, rtmp);
8854 }
8855
8856 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8857 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8858 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8859 // align source address at 4 bytes address boundary
8860 if (t == T_BYTE) {
8861 // One byte misalignment happens only for byte arrays
8862 testptr(to, 1);
8863 jccb(Assembler::zero, L_skip_align1);
8864 movb(Address(to, 0), value);
8865 increment(to);
8866 decrement(count);
8867 BIND(L_skip_align1);
8868 }
8869 // Two bytes misalignment happens only for byte and short (char) arrays
8870 testptr(to, 2);
8871 jccb(Assembler::zero, L_skip_align2);
8872 movw(Address(to, 0), value);
8873 addptr(to, 2);
8874 subl(count, 1<<(shift-1));
8875 BIND(L_skip_align2);
8876 }
8877 if (UseSSE < 2) {
8878 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8879 // Fill 32-byte chunks
8880 subl(count, 8 << shift);
8881 jcc(Assembler::less, L_check_fill_8_bytes);
8882 align(16);
8883
8884 BIND(L_fill_32_bytes_loop);
8885
8886 for (int i = 0; i < 32; i += 4) {
8887 movl(Address(to, i), value);
8888 }
8889
8890 addptr(to, 32);
8891 subl(count, 8 << shift);
8892 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8893 BIND(L_check_fill_8_bytes);
8894 addl(count, 8 << shift);
8895 jccb(Assembler::zero, L_exit);
8896 jmpb(L_fill_8_bytes);
8897
8898 //
8899 // length is too short, just fill qwords
8900 //
8901 BIND(L_fill_8_bytes_loop);
8902 movl(Address(to, 0), value);
8903 movl(Address(to, 4), value);
8904 addptr(to, 8);
8905 BIND(L_fill_8_bytes);
8906 subl(count, 1 << (shift + 1));
8907 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8908 // fall through to fill 4 bytes
8909 } else {
8910 Label L_fill_32_bytes;
8911 if (!UseUnalignedLoadStores) {
8912 // align to 8 bytes, we know we are 4 byte aligned to start
8913 testptr(to, 4);
8914 jccb(Assembler::zero, L_fill_32_bytes);
8915 movl(Address(to, 0), value);
8916 addptr(to, 4);
8917 subl(count, 1<<shift);
8918 }
8919 BIND(L_fill_32_bytes);
8920 {
8921 assert( UseSSE >= 2, "supported cpu only" );
8922 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8923 // Fill 32-byte chunks
8924 movdl(xtmp, value);
8925 pshufd(xtmp, xtmp, 0);
8926
8927 subl(count, 8 << shift);
8928 jcc(Assembler::less, L_check_fill_8_bytes);
8929 align(16);
8930
8931 BIND(L_fill_32_bytes_loop);
8932
8933 if (UseUnalignedLoadStores) {
8934 movdqu(Address(to, 0), xtmp);
8935 movdqu(Address(to, 16), xtmp);
8936 } else {
8937 movq(Address(to, 0), xtmp);
8938 movq(Address(to, 8), xtmp);
8939 movq(Address(to, 16), xtmp);
8940 movq(Address(to, 24), xtmp);
8941 }
8942
8943 addptr(to, 32);
8944 subl(count, 8 << shift);
8945 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8946 BIND(L_check_fill_8_bytes);
8947 addl(count, 8 << shift);
8948 jccb(Assembler::zero, L_exit);
8949 jmpb(L_fill_8_bytes);
8950
8951 //
8952 // length is too short, just fill qwords
8953 //
8954 BIND(L_fill_8_bytes_loop);
8955 movq(Address(to, 0), xtmp);
8956 addptr(to, 8);
8957 BIND(L_fill_8_bytes);
8958 subl(count, 1 << (shift + 1));
8959 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8960 }
8961 }
8962 // fill trailing 4 bytes
8963 BIND(L_fill_4_bytes);
8964 testl(count, 1<<shift);
8965 jccb(Assembler::zero, L_fill_2_bytes);
8966 movl(Address(to, 0), value);
8967 if (t == T_BYTE || t == T_SHORT) {
8968 addptr(to, 4);
8969 BIND(L_fill_2_bytes);
8970 // fill trailing 2 bytes
8971 testl(count, 1<<(shift-1));
8972 jccb(Assembler::zero, L_fill_byte);
8973 movw(Address(to, 0), value);
8974 if (t == T_BYTE) {
8975 addptr(to, 2);
8976 BIND(L_fill_byte);
8977 // fill trailing byte
8978 testl(count, 1);
8979 jccb(Assembler::zero, L_exit);
8980 movb(Address(to, 0), value);
8981 } else {
8982 BIND(L_fill_byte);
8983 }
8984 } else {
8985 BIND(L_fill_2_bytes);
8986 }
8987 BIND(L_exit);
8988 }
8989 #undef BIND
8990 #undef BLOCK_COMMENT
8991
8992
8993 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8994 switch (cond) {
8995 // Note some conditions are synonyms for others
8996 case Assembler::zero: return Assembler::notZero;
8997 case Assembler::notZero: return Assembler::zero;
8998 case Assembler::less: return Assembler::greaterEqual;
8999 case Assembler::lessEqual: return Assembler::greater;
9000 case Assembler::greater: return Assembler::lessEqual;
9001 case Assembler::greaterEqual: return Assembler::less;
9002 case Assembler::below: return Assembler::aboveEqual;
9003 case Assembler::belowEqual: return Assembler::above;
9004 case Assembler::above: return Assembler::belowEqual;
9005 case Assembler::aboveEqual: return Assembler::below;
9006 case Assembler::overflow: return Assembler::noOverflow;
9007 case Assembler::noOverflow: return Assembler::overflow;
9008 case Assembler::negative: return Assembler::positive;
9009 case Assembler::positive: return Assembler::negative;
9010 case Assembler::parity: return Assembler::noParity;
9011 case Assembler::noParity: return Assembler::parity;
9012 }
9013 ShouldNotReachHere(); return Assembler::overflow;
9014 }
9015
9016 SkipIfEqual::SkipIfEqual(
9017 MacroAssembler* masm, const bool* flag_addr, bool value) {
9018 _masm = masm;
9019 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9020 _masm->jcc(Assembler::equal, _label);
9021 }
9022
9023 SkipIfEqual::~SkipIfEqual() {
9024 _masm->bind(_label);
9025 }