src/cpu/sparc/vm/sparc.ad

*** 9526,9579 ****
      __ sub(Rtmp, Rdst, Rdst);
    %}
    ins_pipe(ialu_reg);
  %}
  
! instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
    predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
    match(Set dst (CountLeadingZerosL src));
!   effect(TEMP dst, TEMP tmp, KILL cr);
  
    // x |= (x >> 1);
    // x |= (x >> 2);
    // x |= (x >> 4);
    // x |= (x >> 8);
    // x |= (x >> 16);
    // x |= (x >> 32);
    // return (WORDBITS - popc(x));
    format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
!             "OR      $src,$tmp,$dst\n\t"
!             "SRLX    $dst,2,$tmp\n\t"
!             "OR      $dst,$tmp,$dst\n\t"
!             "SRLX    $dst,4,$tmp\n\t"
!             "OR      $dst,$tmp,$dst\n\t"
!             "SRLX    $dst,8,$tmp\n\t"
!             "OR      $dst,$tmp,$dst\n\t"
!             "SRLX    $dst,16,$tmp\n\t"
!             "OR      $dst,$tmp,$dst\n\t"
!             "SRLX    $dst,32,$tmp\n\t"
!             "OR      $dst,$tmp,$dst\n\t"
!             "POPC    $dst,$dst\n\t"
              "MOV     64,$tmp\n\t"
              "SUB     $tmp,$dst,$dst" %}
    ins_encode %{
      Register Rdst = $dst$$Register;
      Register Rsrc = $src$$Register;
      Register Rtmp = $tmp$$Register;
      __ srlx(Rsrc, 1, Rtmp);
!     __ or3(Rsrc, Rtmp, Rdst);
!     __ srlx(Rdst, 2, Rtmp);
!     __ or3(Rdst, Rtmp, Rdst);
!     __ srlx(Rdst, 4, Rtmp);
!     __ or3(Rdst, Rtmp, Rdst);
!     __ srlx(Rdst, 8, Rtmp);
!     __ or3(Rdst, Rtmp, Rdst);
!     __ srlx(Rdst, 16, Rtmp);
!     __ or3(Rdst, Rtmp, Rdst);
!     __ srlx(Rdst, 32, Rtmp);
!     __ or3(Rdst, Rtmp, Rdst);
!     __ popc(Rdst, Rdst);
      __ mov(BitsPerLong, Rtmp);
      __ sub(Rtmp, Rdst, Rdst);
    %}
    ins_pipe(ialu_reg);
  %}
--- 9526,9580 ----
      __ sub(Rtmp, Rdst, Rdst);
    %}
    ins_pipe(ialu_reg);
  %}
  
! instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, iRegL tmp2, flagsReg cr) %{
    predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
    match(Set dst (CountLeadingZerosL src));
!   effect(TEMP dst, TEMP tmp, TEMP tmp2, KILL cr);
  
    // x |= (x >> 1);
    // x |= (x >> 2);
    // x |= (x >> 4);
    // x |= (x >> 8);
    // x |= (x >> 16);
    // x |= (x >> 32);
    // return (WORDBITS - popc(x));
    format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
!             "OR      $src,$tmp,$tmp2\n\t"
!             "SRLX    $tmp2,2,$tmp\n\t"
!             "OR      $tmp2,$tmp,$tmp2\n\t"
!             "SRLX    $tmp2,4,$tmp\n\t"
!             "OR      $tmp2,$tmp,$tmp2\n\t"
!             "SRLX    $tmp2,8,$tmp\n\t"
!             "OR      $tmp2,$tmp,$tmp2\n\t"
!             "SRLX    $tmp2,16,$tmp\n\t"
!             "OR      $tmp2,$tmp,$tmp2\n\t"
!             "SRLX    $tmp2,32,$tmp\n\t"
!             "OR      $tmp2,$tmp,$tmp2\n\t"
!             "POPC    $tmp2,$dst\n\t"
              "MOV     64,$tmp\n\t"
              "SUB     $tmp,$dst,$dst" %}
    ins_encode %{
      Register Rdst  = $dst$$Register;
      Register Rsrc  = $src$$Register;
      Register Rtmp  = $tmp$$Register;
+     Register Rtmp2 = $tmp2$$Register;
      __ srlx(Rsrc,  1,    Rtmp);
!     __ or3( Rsrc,  Rtmp, Rtmp2);
!     __ srlx(Rtmp2, 2,    Rtmp);
!     __ or3( Rtmp2, Rtmp, Rtmp2);
!     __ srlx(Rtmp2, 4,    Rtmp);
!     __ or3( Rtmp2, Rtmp, Rtmp2);
!     __ srlx(Rtmp2, 8,    Rtmp);
!     __ or3( Rtmp2, Rtmp, Rtmp2);
!     __ srlx(Rtmp2, 16,   Rtmp);
!     __ or3( Rtmp2, Rtmp, Rtmp2);
!     __ srlx(Rtmp2, 32,   Rtmp);
!     __ or3( Rtmp2, Rtmp, Rtmp2);
!     __ popc(Rtmp2, Rdst);
      __ mov(BitsPerLong, Rtmp);
      __ sub(Rtmp, Rdst, Rdst);
    %}
    ins_pipe(ialu_reg);
  %}