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--- old/src/cpu/sparc/vm/sparc.ad
+++ new/src/cpu/sparc/vm/sparc.ad
1 1 //
2 2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
3 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 //
5 5 // This code is free software; you can redistribute it and/or modify it
6 6 // under the terms of the GNU General Public License version 2 only, as
7 7 // published by the Free Software Foundation.
8 8 //
9 9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 // version 2 for more details (a copy is included in the LICENSE file that
13 13 // accompanied this code).
14 14 //
15 15 // You should have received a copy of the GNU General Public License version
16 16 // 2 along with this work; if not, write to the Free Software Foundation,
17 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 //
19 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 // or visit www.oracle.com if you need additional information or have any
21 21 // questions.
22 22 //
23 23 //
24 24
25 25 // SPARC Architecture Description File
26 26
27 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 28 // This information is used by the matcher and the register allocator to
29 29 // describe individual registers and classes of registers within the target
30 30 // archtecture.
31 31 register %{
32 32 //----------Architecture Description Register Definitions----------------------
33 33 // General Registers
34 34 // "reg_def" name ( register save type, C convention save type,
35 35 // ideal register type, encoding, vm name );
36 36 // Register Save Types:
37 37 //
38 38 // NS = No-Save: The register allocator assumes that these registers
39 39 // can be used without saving upon entry to the method, &
40 40 // that they do not need to be saved at call sites.
41 41 //
42 42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 43 // can be used without saving upon entry to the method,
44 44 // but that they must be saved at call sites.
45 45 //
46 46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 47 // must be saved before using them upon entry to the
48 48 // method, but they do not need to be saved at call
49 49 // sites.
50 50 //
51 51 // AS = Always-Save: The register allocator assumes that these registers
52 52 // must be saved before using them upon entry to the
53 53 // method, & that they must be saved at call sites.
54 54 //
55 55 // Ideal Register Type is used to determine how to save & restore a
56 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 58 //
59 59 // The encoding number is the actual bit-pattern placed into the opcodes.
60 60
61 61
62 62 // ----------------------------
63 63 // Integer/Long Registers
64 64 // ----------------------------
65 65
66 66 // Need to expose the hi/lo aspect of 64-bit registers
67 67 // This register set is used for both the 64-bit build and
68 68 // the 32-bit build with 1-register longs.
69 69
70 70 // Global Registers 0-7
71 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87 87
88 88 // Output Registers 0-7
89 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105 105
106 106 // Local Registers 0-7
107 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123 123
124 124 // Input Registers 0-7
125 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141 141
142 142 // ----------------------------
143 143 // Float/Double Registers
144 144 // ----------------------------
145 145
146 146 // Float Registers
147 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179 179
180 180 // Double Registers
181 181 // The rules of ADL require that double registers be defined in pairs.
182 182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 183 // single float registers. In each pair, ADLC-assigned register numbers
184 184 // must be adjacent, with the lower number even. Finally, when the
185 185 // CPU stores such a register pair to memory, the word associated with
186 186 // the lower ADLC-assigned number must be stored to the lower address.
187 187
188 188 // These definitions specify the actual bit encodings of the sparc
189 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 190 // wants 0-63, so we have to convert every time we want to use fp regs
191 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 192 // 255 is a flag meaning "don't go here".
193 193 // I believe we can't handle callee-save doubles D32 and up until
194 194 // the place in the sparc stack crawler that asserts on the 255 is
195 195 // fixed up.
196 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228 228
229 229
230 230 // ----------------------------
231 231 // Special Registers
232 232 // Condition Codes Flag Registers
233 233 // I tried to break out ICC and XCC but it's not very pretty.
234 234 // Every Sparc instruction which defs/kills one also kills the other.
235 235 // Hence every compare instruction which defs one kind of flags ends
236 236 // up needing a kill of the other.
237 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238 238
239 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243 243
244 244 // ----------------------------
245 245 // Specify the enum values for the registers. These enums are only used by the
246 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 247 // for visibility to the rest of the vm. The order of this enum influences the
248 248 // register allocator so having the freedom to set this order and not be stuck
249 249 // with the order that is natural for the rest of the vm is worth it.
250 250 alloc_class chunk0(
251 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255 255
256 256 // Note that a register is not allocatable unless it is also mentioned
257 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258 258
259 259 alloc_class chunk1(
260 260 // The first registers listed here are those most likely to be used
261 261 // as temporaries. We move F0..F7 away from the front of the list,
262 262 // to reduce the likelihood of interferences with parameters and
263 263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 264 // since they are used for return values.
265 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274 274
275 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276 276
277 277 //----------Architecture Description Register Classes--------------------------
278 278 // Several register classes are automatically defined based upon information in
279 279 // this architecture description.
280 280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 283 //
284 284
285 285 // G0 is not included in integer class since it has special meaning.
286 286 reg_class g0_reg(R_G0);
287 287
288 288 // ----------------------------
289 289 // Integer Register Classes
290 290 // ----------------------------
291 291 // Exclusions from i_reg:
292 292 // R_G0: hardwired zero
293 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 294 // R_G6: reserved by Solaris ABI to tools
295 295 // R_G7: reserved by Solaris ABI to libthread
296 296 // R_O7: Used as a temp in many encodings
297 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298 298
299 299 // Class for all integer registers, except the G registers. This is used for
300 300 // encodings which use G registers as temps. The regular inputs to such
301 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 302 // will not put an input into a temp register.
303 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304 304
305 305 reg_class g1_regI(R_G1);
306 306 reg_class g3_regI(R_G3);
307 307 reg_class g4_regI(R_G4);
308 308 reg_class o0_regI(R_O0);
309 309 reg_class o7_regI(R_O7);
310 310
311 311 // ----------------------------
312 312 // Pointer Register Classes
313 313 // ----------------------------
314 314 #ifdef _LP64
315 315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 320 // Lock encodings use G3 and G4 internally
321 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 326 // It is also used for memory addressing, allowing direct TLS addressing.
327 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 332 // We use it to save R_G2 across calls out of Java.
333 333 reg_class l7_regP(R_L7H,R_L7);
334 334
335 335 // Other special pointer regs
336 336 reg_class g1_regP(R_G1H,R_G1);
337 337 reg_class g2_regP(R_G2H,R_G2);
338 338 reg_class g3_regP(R_G3H,R_G3);
339 339 reg_class g4_regP(R_G4H,R_G4);
340 340 reg_class g5_regP(R_G5H,R_G5);
341 341 reg_class i0_regP(R_I0H,R_I0);
342 342 reg_class o0_regP(R_O0H,R_O0);
343 343 reg_class o1_regP(R_O1H,R_O1);
344 344 reg_class o2_regP(R_O2H,R_O2);
345 345 reg_class o7_regP(R_O7H,R_O7);
346 346
347 347 #else // _LP64
348 348 // 32-bit build means 32-bit pointers means 1 register.
349 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 353 // Lock encodings use G3 and G4 internally
354 354 reg_class lock_ptr_reg(R_G1, R_G5,
355 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 359 // It is also used for memory addressing, allowing direct TLS addressing.
360 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 365 // We use it to save R_G2 across calls out of Java.
366 366 reg_class l7_regP(R_L7);
367 367
368 368 // Other special pointer regs
369 369 reg_class g1_regP(R_G1);
370 370 reg_class g2_regP(R_G2);
371 371 reg_class g3_regP(R_G3);
372 372 reg_class g4_regP(R_G4);
373 373 reg_class g5_regP(R_G5);
374 374 reg_class i0_regP(R_I0);
375 375 reg_class o0_regP(R_O0);
376 376 reg_class o1_regP(R_O1);
377 377 reg_class o2_regP(R_O2);
378 378 reg_class o7_regP(R_O7);
379 379 #endif // _LP64
380 380
381 381
382 382 // ----------------------------
383 383 // Long Register Classes
384 384 // ----------------------------
385 385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 389 #ifdef _LP64
390 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 394 #endif // _LP64
395 395 );
396 396
397 397 reg_class g1_regL(R_G1H,R_G1);
398 398 reg_class g3_regL(R_G3H,R_G3);
399 399 reg_class o2_regL(R_O2H,R_O2);
400 400 reg_class o7_regL(R_O7H,R_O7);
401 401
402 402 // ----------------------------
403 403 // Special Class for Condition Code Flags Register
404 404 reg_class int_flags(CCR);
405 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 406 reg_class float_flag0(FCC0);
407 407
408 408
409 409 // ----------------------------
410 410 // Float Point Register Classes
411 411 // ----------------------------
412 412 // Skip F30/F31, they are reserved for mem-mem copies
413 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414 414
415 415 // Paired floating point registers--they show up in the same order as the floats,
416 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 419 /* Use extra V9 double registers; this AD file does not support V8 */
420 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 422 );
423 423
424 424 // Paired floating point registers--they show up in the same order as the floats,
425 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 429 %}
430 430
431 431 //----------DEFINITION BLOCK---------------------------------------------------
432 432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 434 // Format:
435 435 // int_def <name> ( <int_value>, <expression>);
436 436 // Generated Code in ad_<arch>.hpp
437 437 // #define <name> (<expression>)
438 438 // // value == <int_value>
439 439 // Generated code in ad_<arch>.cpp adlc_verification()
440 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 441 //
442 442 definitions %{
443 443 // The default cost (of an ALU instruction).
444 444 int_def DEFAULT_COST ( 100, 100);
445 445 int_def HUGE_COST (1000000, 1000000);
446 446
447 447 // Memory refs are twice as expensive as run-of-the-mill.
448 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449 449
450 450 // Branches are even more expensive.
451 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 453 %}
454 454
455 455
456 456 //----------SOURCE BLOCK-------------------------------------------------------
457 457 // This is a block of C++ code which provides values, functions, and
458 458 // definitions necessary in the rest of the architecture description
459 459 source_hpp %{
460 460 // Must be visible to the DFA in dfa_sparc.cpp
461 461 extern bool can_branch_register( Node *bol, Node *cmp );
462 462
463 463 // Macros to extract hi & lo halves from a long pair.
464 464 // G0 is not part of any long pair, so assert on that.
465 465 // Prevents accidentally using G1 instead of G0.
466 466 #define LONG_HI_REG(x) (x)
467 467 #define LONG_LO_REG(x) (x)
468 468
469 469 %}
470 470
471 471 source %{
472 472 #define __ _masm.
473 473
474 474 // Block initializing store
475 475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476 476
477 477 // tertiary op of a LoadP or StoreP encoding
478 478 #define REGP_OP true
479 479
480 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 482 static Register reg_to_register_object(int register_encoding);
483 483
484 484 // Used by the DFA in dfa_sparc.cpp.
485 485 // Check for being able to use a V9 branch-on-register. Requires a
486 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 487 // extended. Doesn't work following an integer ADD, for example, because of
488 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 490 // replace them with zero, which could become sign-extension in a different OS
491 491 // release. There's no obvious reason why an interrupt will ever fill these
492 492 // bits with non-zero junk (the registers are reloaded with standard LD
493 493 // instructions which either zero-fill or sign-fill).
494 494 bool can_branch_register( Node *bol, Node *cmp ) {
495 495 if( !BranchOnRegister ) return false;
496 496 #ifdef _LP64
497 497 if( cmp->Opcode() == Op_CmpP )
498 498 return true; // No problems with pointer compares
499 499 #endif
500 500 if( cmp->Opcode() == Op_CmpL )
501 501 return true; // No problems with long compares
502 502
503 503 if( !SparcV9RegsHiBitsZero ) return false;
504 504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 505 bol->as_Bool()->_test._test != BoolTest::eq )
506 506 return false;
507 507
508 508 // Check for comparing against a 'safe' value. Any operation which
509 509 // clears out the high word is safe. Thus, loads and certain shifts
510 510 // are safe, as are non-negative constants. Any operation which
511 511 // preserves zero bits in the high word is safe as long as each of its
512 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 513 // inputs are safe. At present, the only important case to recognize
514 514 // seems to be loads. Constants should fold away, and shifts &
515 515 // logicals can use the 'cc' forms.
516 516 Node *x = cmp->in(1);
517 517 if( x->is_Load() ) return true;
518 518 if( x->is_Phi() ) {
519 519 for( uint i = 1; i < x->req(); i++ )
520 520 if( !x->in(i)->is_Load() )
521 521 return false;
522 522 return true;
523 523 }
524 524 return false;
525 525 }
526 526
527 527 // ****************************************************************************
528 528
529 529 // REQUIRED FUNCTIONALITY
530 530
531 531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 532 // from the start of the call to the point where the return address
533 533 // will point.
534 534 // The "return address" is the address of the call instruction, plus 8.
535 535
536 536 int MachCallStaticJavaNode::ret_addr_offset() {
537 537 int offset = NativeCall::instruction_size; // call; delay slot
538 538 if (_method_handle_invoke)
539 539 offset += 4; // restore SP
540 540 return offset;
541 541 }
542 542
543 543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 544 int vtable_index = this->_vtable_index;
545 545 if (vtable_index < 0) {
546 546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 548 return (NativeMovConstReg::instruction_size +
549 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 550 } else {
551 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 554 int klass_load_size;
555 555 if (UseCompressedOops) {
556 556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 557 if (Universe::narrow_oop_base() == NULL)
558 558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 559 else
560 560 klass_load_size = 3*BytesPerInstWord;
561 561 } else {
562 562 klass_load_size = 1*BytesPerInstWord;
563 563 }
564 564 if( Assembler::is_simm13(v_off) ) {
565 565 return klass_load_size +
566 566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 567 NativeCall::instruction_size); // call; delay slot
568 568 } else {
569 569 return klass_load_size +
570 570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 571 NativeCall::instruction_size); // call; delay slot
572 572 }
573 573 }
574 574 }
575 575
576 576 int MachCallRuntimeNode::ret_addr_offset() {
577 577 #ifdef _LP64
578 578 return NativeFarCall::instruction_size; // farcall; delay slot
579 579 #else
580 580 return NativeCall::instruction_size; // call; delay slot
581 581 #endif
582 582 }
583 583
584 584 // Indicate if the safepoint node needs the polling page as an input.
585 585 // Since Sparc does not have absolute addressing, it does.
586 586 bool SafePointNode::needs_polling_address_input() {
587 587 return true;
588 588 }
589 589
590 590 // emit an interrupt that is caught by the debugger (for debugging compiler)
591 591 void emit_break(CodeBuffer &cbuf) {
592 592 MacroAssembler _masm(&cbuf);
593 593 __ breakpoint_trap();
594 594 }
595 595
596 596 #ifndef PRODUCT
597 597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
598 598 st->print("TA");
599 599 }
600 600 #endif
601 601
602 602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 603 emit_break(cbuf);
604 604 }
605 605
606 606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
607 607 return MachNode::size(ra_);
608 608 }
609 609
610 610 // Traceable jump
611 611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
612 612 MacroAssembler _masm(&cbuf);
613 613 Register rdest = reg_to_register_object(jump_target);
614 614 __ JMP(rdest, 0);
615 615 __ delayed()->nop();
616 616 }
617 617
618 618 // Traceable jump and set exception pc
619 619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
620 620 MacroAssembler _masm(&cbuf);
621 621 Register rdest = reg_to_register_object(jump_target);
622 622 __ JMP(rdest, 0);
623 623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
624 624 }
625 625
626 626 void emit_nop(CodeBuffer &cbuf) {
627 627 MacroAssembler _masm(&cbuf);
628 628 __ nop();
629 629 }
630 630
631 631 void emit_illtrap(CodeBuffer &cbuf) {
632 632 MacroAssembler _masm(&cbuf);
633 633 __ illtrap(0);
634 634 }
635 635
636 636
637 637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
638 638 assert(n->rule() != loadUB_rule, "");
639 639
640 640 intptr_t offset = 0;
641 641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
642 642 const Node* addr = n->get_base_and_disp(offset, adr_type);
643 643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
644 644 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
645 645 assert(addr->bottom_type()->isa_oopptr() == atype, "");
646 646 atype = atype->add_offset(offset);
647 647 assert(disp32 == offset, "wrong disp32");
648 648 return atype->_offset;
649 649 }
650 650
651 651
652 652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
653 653 assert(n->rule() != loadUB_rule, "");
654 654
655 655 intptr_t offset = 0;
656 656 Node* addr = n->in(2);
657 657 assert(addr->bottom_type()->isa_oopptr() == atype, "");
658 658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
659 659 Node* a = addr->in(2/*AddPNode::Address*/);
660 660 Node* o = addr->in(3/*AddPNode::Offset*/);
661 661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
662 662 atype = a->bottom_type()->is_ptr()->add_offset(offset);
663 663 assert(atype->isa_oop_ptr(), "still an oop");
664 664 }
665 665 offset = atype->is_ptr()->_offset;
666 666 if (offset != Type::OffsetBot) offset += disp32;
667 667 return offset;
668 668 }
669 669
670 670 // Standard Sparc opcode form2 field breakdown
671 671 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
672 672 f0 &= (1<<19)-1; // Mask displacement to 19 bits
673 673 int op = (f30 << 30) |
674 674 (f29 << 29) |
675 675 (f25 << 25) |
676 676 (f22 << 22) |
677 677 (f20 << 20) |
678 678 (f19 << 19) |
679 679 (f0 << 0);
680 680 cbuf.insts()->emit_int32(op);
681 681 }
682 682
683 683 // Standard Sparc opcode form2 field breakdown
684 684 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
685 685 f0 >>= 10; // Drop 10 bits
686 686 f0 &= (1<<22)-1; // Mask displacement to 22 bits
687 687 int op = (f30 << 30) |
688 688 (f25 << 25) |
689 689 (f22 << 22) |
690 690 (f0 << 0);
691 691 cbuf.insts()->emit_int32(op);
692 692 }
693 693
694 694 // Standard Sparc opcode form3 field breakdown
695 695 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
696 696 int op = (f30 << 30) |
697 697 (f25 << 25) |
698 698 (f19 << 19) |
699 699 (f14 << 14) |
700 700 (f5 << 5) |
701 701 (f0 << 0);
702 702 cbuf.insts()->emit_int32(op);
703 703 }
704 704
705 705 // Standard Sparc opcode form3 field breakdown
706 706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
707 707 simm13 &= (1<<13)-1; // Mask to 13 bits
708 708 int op = (f30 << 30) |
709 709 (f25 << 25) |
710 710 (f19 << 19) |
711 711 (f14 << 14) |
712 712 (1 << 13) | // bit to indicate immediate-mode
713 713 (simm13<<0);
714 714 cbuf.insts()->emit_int32(op);
715 715 }
716 716
717 717 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
718 718 simm10 &= (1<<10)-1; // Mask to 10 bits
719 719 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
720 720 }
721 721
722 722 #ifdef ASSERT
723 723 // Helper function for VerifyOops in emit_form3_mem_reg
724 724 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
725 725 warning("VerifyOops encountered unexpected instruction:");
726 726 n->dump(2);
727 727 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
728 728 }
729 729 #endif
730 730
731 731
732 732 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
733 733 int src1_enc, int disp32, int src2_enc, int dst_enc) {
734 734
735 735 #ifdef ASSERT
736 736 // The following code implements the +VerifyOops feature.
737 737 // It verifies oop values which are loaded into or stored out of
738 738 // the current method activation. +VerifyOops complements techniques
739 739 // like ScavengeALot, because it eagerly inspects oops in transit,
740 740 // as they enter or leave the stack, as opposed to ScavengeALot,
741 741 // which inspects oops "at rest", in the stack or heap, at safepoints.
742 742 // For this reason, +VerifyOops can sometimes detect bugs very close
743 743 // to their point of creation. It can also serve as a cross-check
744 744 // on the validity of oop maps, when used toegether with ScavengeALot.
745 745
746 746 // It would be good to verify oops at other points, especially
747 747 // when an oop is used as a base pointer for a load or store.
748 748 // This is presently difficult, because it is hard to know when
749 749 // a base address is biased or not. (If we had such information,
750 750 // it would be easy and useful to make a two-argument version of
751 751 // verify_oop which unbiases the base, and performs verification.)
752 752
753 753 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
754 754 bool is_verified_oop_base = false;
755 755 bool is_verified_oop_load = false;
756 756 bool is_verified_oop_store = false;
757 757 int tmp_enc = -1;
758 758 if (VerifyOops && src1_enc != R_SP_enc) {
759 759 // classify the op, mainly for an assert check
760 760 int st_op = 0, ld_op = 0;
761 761 switch (primary) {
762 762 case Assembler::stb_op3: st_op = Op_StoreB; break;
763 763 case Assembler::sth_op3: st_op = Op_StoreC; break;
764 764 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
765 765 case Assembler::stw_op3: st_op = Op_StoreI; break;
766 766 case Assembler::std_op3: st_op = Op_StoreL; break;
767 767 case Assembler::stf_op3: st_op = Op_StoreF; break;
768 768 case Assembler::stdf_op3: st_op = Op_StoreD; break;
769 769
770 770 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
771 771 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
772 772 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
773 773 case Assembler::ldx_op3: // may become LoadP or stay LoadI
774 774 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
775 775 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
776 776 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
777 777 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
778 778 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
779 779 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
780 780 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
781 781
782 782 default: ShouldNotReachHere();
783 783 }
784 784 if (tertiary == REGP_OP) {
785 785 if (st_op == Op_StoreI) st_op = Op_StoreP;
786 786 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
787 787 else ShouldNotReachHere();
788 788 if (st_op) {
789 789 // a store
790 790 // inputs are (0:control, 1:memory, 2:address, 3:value)
791 791 Node* n2 = n->in(3);
792 792 if (n2 != NULL) {
793 793 const Type* t = n2->bottom_type();
794 794 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
795 795 }
796 796 } else {
797 797 // a load
798 798 const Type* t = n->bottom_type();
799 799 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
800 800 }
801 801 }
802 802
803 803 if (ld_op) {
804 804 // a Load
805 805 // inputs are (0:control, 1:memory, 2:address)
806 806 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
807 807 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
808 808 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
809 809 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
810 810 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
811 811 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
812 812 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
813 813 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
814 814 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
815 815 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
816 816 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
817 817 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
818 818 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
819 819 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
820 820 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
821 821 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
822 822 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
823 823 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
824 824 !(n->rule() == loadUB_rule)) {
825 825 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
826 826 }
827 827 } else if (st_op) {
828 828 // a Store
829 829 // inputs are (0:control, 1:memory, 2:address, 3:value)
830 830 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
831 831 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
832 832 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
833 833 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
834 834 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
835 835 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
836 836 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
837 837 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
838 838 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
839 839 verify_oops_warning(n, n->ideal_Opcode(), st_op);
840 840 }
841 841 }
842 842
843 843 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
844 844 Node* addr = n->in(2);
845 845 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
846 846 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
847 847 if (atype != NULL) {
848 848 intptr_t offset = get_offset_from_base(n, atype, disp32);
849 849 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
850 850 if (offset != offset_2) {
851 851 get_offset_from_base(n, atype, disp32);
852 852 get_offset_from_base_2(n, atype, disp32);
853 853 }
854 854 assert(offset == offset_2, "different offsets");
855 855 if (offset == disp32) {
856 856 // we now know that src1 is a true oop pointer
857 857 is_verified_oop_base = true;
858 858 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
859 859 if( primary == Assembler::ldd_op3 ) {
860 860 is_verified_oop_base = false; // Cannot 'ldd' into O7
861 861 } else {
862 862 tmp_enc = dst_enc;
863 863 dst_enc = R_O7_enc; // Load into O7; preserve source oop
864 864 assert(src1_enc != dst_enc, "");
865 865 }
866 866 }
867 867 }
868 868 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
869 869 || offset == oopDesc::mark_offset_in_bytes())) {
870 870 // loading the mark should not be allowed either, but
871 871 // we don't check this since it conflicts with InlineObjectHash
872 872 // usage of LoadINode to get the mark. We could keep the
873 873 // check if we create a new LoadMarkNode
874 874 // but do not verify the object before its header is initialized
875 875 ShouldNotReachHere();
876 876 }
877 877 }
878 878 }
879 879 }
880 880 }
881 881 #endif
882 882
883 883 uint instr;
884 884 instr = (Assembler::ldst_op << 30)
885 885 | (dst_enc << 25)
886 886 | (primary << 19)
887 887 | (src1_enc << 14);
888 888
889 889 uint index = src2_enc;
890 890 int disp = disp32;
891 891
892 892 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
893 893 disp += STACK_BIAS;
894 894
895 895 // We should have a compiler bailout here rather than a guarantee.
896 896 // Better yet would be some mechanism to handle variable-size matches correctly.
897 897 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
898 898
899 899 if( disp == 0 ) {
900 900 // use reg-reg form
901 901 // bit 13 is already zero
902 902 instr |= index;
903 903 } else {
904 904 // use reg-imm form
905 905 instr |= 0x00002000; // set bit 13 to one
906 906 instr |= disp & 0x1FFF;
907 907 }
908 908
909 909 cbuf.insts()->emit_int32(instr);
910 910
911 911 #ifdef ASSERT
912 912 {
913 913 MacroAssembler _masm(&cbuf);
914 914 if (is_verified_oop_base) {
915 915 __ verify_oop(reg_to_register_object(src1_enc));
916 916 }
917 917 if (is_verified_oop_store) {
918 918 __ verify_oop(reg_to_register_object(dst_enc));
919 919 }
920 920 if (tmp_enc != -1) {
921 921 __ mov(O7, reg_to_register_object(tmp_enc));
922 922 }
923 923 if (is_verified_oop_load) {
924 924 __ verify_oop(reg_to_register_object(dst_enc));
925 925 }
926 926 }
927 927 #endif
928 928 }
929 929
930 930 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
931 931 // The method which records debug information at every safepoint
932 932 // expects the call to be the first instruction in the snippet as
933 933 // it creates a PcDesc structure which tracks the offset of a call
934 934 // from the start of the codeBlob. This offset is computed as
935 935 // code_end() - code_begin() of the code which has been emitted
936 936 // so far.
937 937 // In this particular case we have skirted around the problem by
938 938 // putting the "mov" instruction in the delay slot but the problem
939 939 // may bite us again at some other point and a cleaner/generic
940 940 // solution using relocations would be needed.
941 941 MacroAssembler _masm(&cbuf);
942 942 __ set_inst_mark();
943 943
944 944 // We flush the current window just so that there is a valid stack copy
945 945 // the fact that the current window becomes active again instantly is
946 946 // not a problem there is nothing live in it.
947 947
948 948 #ifdef ASSERT
949 949 int startpos = __ offset();
950 950 #endif /* ASSERT */
951 951
952 952 #ifdef _LP64
953 953 // Calls to the runtime or native may not be reachable from compiled code,
954 954 // so we generate the far call sequence on 64 bit sparc.
955 955 // This code sequence is relocatable to any address, even on LP64.
956 956 if ( force_far_call ) {
957 957 __ relocate(rtype);
958 958 AddressLiteral dest(entry_point);
959 959 __ jumpl_to(dest, O7, O7);
960 960 }
961 961 else
962 962 #endif
963 963 {
964 964 __ call((address)entry_point, rtype);
965 965 }
966 966
967 967 if (preserve_g2) __ delayed()->mov(G2, L7);
968 968 else __ delayed()->nop();
969 969
970 970 if (preserve_g2) __ mov(L7, G2);
971 971
972 972 #ifdef ASSERT
973 973 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
974 974 #ifdef _LP64
975 975 // Trash argument dump slots.
976 976 __ set(0xb0b8ac0db0b8ac0d, G1);
977 977 __ mov(G1, G5);
978 978 __ stx(G1, SP, STACK_BIAS + 0x80);
979 979 __ stx(G1, SP, STACK_BIAS + 0x88);
980 980 __ stx(G1, SP, STACK_BIAS + 0x90);
981 981 __ stx(G1, SP, STACK_BIAS + 0x98);
982 982 __ stx(G1, SP, STACK_BIAS + 0xA0);
983 983 __ stx(G1, SP, STACK_BIAS + 0xA8);
984 984 #else // _LP64
985 985 // this is also a native call, so smash the first 7 stack locations,
986 986 // and the various registers
987 987
988 988 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
989 989 // while [SP+0x44..0x58] are the argument dump slots.
990 990 __ set((intptr_t)0xbaadf00d, G1);
991 991 __ mov(G1, G5);
992 992 __ sllx(G1, 32, G1);
993 993 __ or3(G1, G5, G1);
994 994 __ mov(G1, G5);
995 995 __ stx(G1, SP, 0x40);
996 996 __ stx(G1, SP, 0x48);
997 997 __ stx(G1, SP, 0x50);
998 998 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
999 999 #endif // _LP64
1000 1000 }
1001 1001 #endif /*ASSERT*/
1002 1002 }
1003 1003
1004 1004 //=============================================================================
1005 1005 // REQUIRED FUNCTIONALITY for encoding
1006 1006 void emit_lo(CodeBuffer &cbuf, int val) { }
1007 1007 void emit_hi(CodeBuffer &cbuf, int val) { }
1008 1008
1009 1009
1010 1010 //=============================================================================
1011 1011
1012 1012 #ifndef PRODUCT
1013 1013 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1014 1014 Compile* C = ra_->C;
1015 1015
1016 1016 for (int i = 0; i < OptoPrologueNops; i++) {
1017 1017 st->print_cr("NOP"); st->print("\t");
1018 1018 }
1019 1019
1020 1020 if( VerifyThread ) {
1021 1021 st->print_cr("Verify_Thread"); st->print("\t");
1022 1022 }
1023 1023
1024 1024 size_t framesize = C->frame_slots() << LogBytesPerInt;
1025 1025
1026 1026 // Calls to C2R adapters often do not accept exceptional returns.
1027 1027 // We require that their callers must bang for them. But be careful, because
1028 1028 // some VM calls (such as call site linkage) can use several kilobytes of
1029 1029 // stack. But the stack safety zone should account for that.
1030 1030 // See bugs 4446381, 4468289, 4497237.
1031 1031 if (C->need_stack_bang(framesize)) {
1032 1032 st->print_cr("! stack bang"); st->print("\t");
1033 1033 }
1034 1034
1035 1035 if (Assembler::is_simm13(-framesize)) {
1036 1036 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1037 1037 } else {
1038 1038 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1039 1039 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1040 1040 st->print ("SAVE R_SP,R_G3,R_SP");
1041 1041 }
1042 1042
1043 1043 }
1044 1044 #endif
1045 1045
1046 1046 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1047 1047 Compile* C = ra_->C;
1048 1048 MacroAssembler _masm(&cbuf);
1049 1049
1050 1050 for (int i = 0; i < OptoPrologueNops; i++) {
1051 1051 __ nop();
1052 1052 }
1053 1053
1054 1054 __ verify_thread();
1055 1055
1056 1056 size_t framesize = C->frame_slots() << LogBytesPerInt;
1057 1057 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1058 1058 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1059 1059
1060 1060 // Calls to C2R adapters often do not accept exceptional returns.
1061 1061 // We require that their callers must bang for them. But be careful, because
1062 1062 // some VM calls (such as call site linkage) can use several kilobytes of
1063 1063 // stack. But the stack safety zone should account for that.
1064 1064 // See bugs 4446381, 4468289, 4497237.
1065 1065 if (C->need_stack_bang(framesize)) {
1066 1066 __ generate_stack_overflow_check(framesize);
1067 1067 }
1068 1068
1069 1069 if (Assembler::is_simm13(-framesize)) {
1070 1070 __ save(SP, -framesize, SP);
1071 1071 } else {
1072 1072 __ sethi(-framesize & ~0x3ff, G3);
1073 1073 __ add(G3, -framesize & 0x3ff, G3);
1074 1074 __ save(SP, G3, SP);
1075 1075 }
1076 1076 C->set_frame_complete( __ offset() );
1077 1077 }
1078 1078
1079 1079 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1080 1080 return MachNode::size(ra_);
1081 1081 }
1082 1082
1083 1083 int MachPrologNode::reloc() const {
1084 1084 return 10; // a large enough number
1085 1085 }
1086 1086
1087 1087 //=============================================================================
1088 1088 #ifndef PRODUCT
1089 1089 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1090 1090 Compile* C = ra_->C;
1091 1091
1092 1092 if( do_polling() && ra_->C->is_method_compilation() ) {
1093 1093 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1094 1094 #ifdef _LP64
1095 1095 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1096 1096 #else
1097 1097 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1098 1098 #endif
1099 1099 }
1100 1100
1101 1101 if( do_polling() )
1102 1102 st->print("RET\n\t");
1103 1103
1104 1104 st->print("RESTORE");
1105 1105 }
1106 1106 #endif
1107 1107
1108 1108 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1109 1109 MacroAssembler _masm(&cbuf);
1110 1110 Compile* C = ra_->C;
1111 1111
1112 1112 __ verify_thread();
1113 1113
1114 1114 // If this does safepoint polling, then do it here
1115 1115 if( do_polling() && ra_->C->is_method_compilation() ) {
1116 1116 AddressLiteral polling_page(os::get_polling_page());
1117 1117 __ sethi(polling_page, L0);
1118 1118 __ relocate(relocInfo::poll_return_type);
1119 1119 __ ld_ptr( L0, 0, G0 );
1120 1120 }
1121 1121
1122 1122 // If this is a return, then stuff the restore in the delay slot
1123 1123 if( do_polling() ) {
1124 1124 __ ret();
1125 1125 __ delayed()->restore();
1126 1126 } else {
1127 1127 __ restore();
1128 1128 }
1129 1129 }
1130 1130
1131 1131 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1132 1132 return MachNode::size(ra_);
1133 1133 }
1134 1134
1135 1135 int MachEpilogNode::reloc() const {
1136 1136 return 16; // a large enough number
1137 1137 }
1138 1138
1139 1139 const Pipeline * MachEpilogNode::pipeline() const {
1140 1140 return MachNode::pipeline_class();
1141 1141 }
1142 1142
1143 1143 int MachEpilogNode::safepoint_offset() const {
1144 1144 assert( do_polling(), "no return for this epilog node");
1145 1145 return MacroAssembler::size_of_sethi(os::get_polling_page());
1146 1146 }
1147 1147
1148 1148 //=============================================================================
1149 1149
1150 1150 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1151 1151 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1152 1152 static enum RC rc_class( OptoReg::Name reg ) {
1153 1153 if( !OptoReg::is_valid(reg) ) return rc_bad;
1154 1154 if (OptoReg::is_stack(reg)) return rc_stack;
1155 1155 VMReg r = OptoReg::as_VMReg(reg);
1156 1156 if (r->is_Register()) return rc_int;
1157 1157 assert(r->is_FloatRegister(), "must be");
1158 1158 return rc_float;
1159 1159 }
1160 1160
1161 1161 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1162 1162 if( cbuf ) {
1163 1163 // Better yet would be some mechanism to handle variable-size matches correctly
1164 1164 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1165 1165 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1166 1166 } else {
1167 1167 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1168 1168 }
1169 1169 }
1170 1170 #ifndef PRODUCT
1171 1171 else if( !do_size ) {
1172 1172 if( size != 0 ) st->print("\n\t");
1173 1173 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1174 1174 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1175 1175 }
1176 1176 #endif
1177 1177 return size+4;
1178 1178 }
1179 1179
1180 1180 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1181 1181 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1182 1182 #ifndef PRODUCT
1183 1183 else if( !do_size ) {
1184 1184 if( size != 0 ) st->print("\n\t");
1185 1185 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1186 1186 }
1187 1187 #endif
1188 1188 return size+4;
1189 1189 }
1190 1190
1191 1191 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1192 1192 PhaseRegAlloc *ra_,
1193 1193 bool do_size,
1194 1194 outputStream* st ) const {
1195 1195 // Get registers to move
1196 1196 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1197 1197 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1198 1198 OptoReg::Name dst_second = ra_->get_reg_second(this );
1199 1199 OptoReg::Name dst_first = ra_->get_reg_first(this );
1200 1200
1201 1201 enum RC src_second_rc = rc_class(src_second);
1202 1202 enum RC src_first_rc = rc_class(src_first);
1203 1203 enum RC dst_second_rc = rc_class(dst_second);
1204 1204 enum RC dst_first_rc = rc_class(dst_first);
1205 1205
1206 1206 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1207 1207
1208 1208 // Generate spill code!
1209 1209 int size = 0;
1210 1210
1211 1211 if( src_first == dst_first && src_second == dst_second )
1212 1212 return size; // Self copy, no move
1213 1213
1214 1214 // --------------------------------------
1215 1215 // Check for mem-mem move. Load into unused float registers and fall into
1216 1216 // the float-store case.
1217 1217 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1218 1218 int offset = ra_->reg2offset(src_first);
1219 1219 // Further check for aligned-adjacent pair, so we can use a double load
1220 1220 if( (src_first&1)==0 && src_first+1 == src_second ) {
1221 1221 src_second = OptoReg::Name(R_F31_num);
1222 1222 src_second_rc = rc_float;
1223 1223 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1224 1224 } else {
1225 1225 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1226 1226 }
1227 1227 src_first = OptoReg::Name(R_F30_num);
1228 1228 src_first_rc = rc_float;
1229 1229 }
1230 1230
1231 1231 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1232 1232 int offset = ra_->reg2offset(src_second);
1233 1233 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1234 1234 src_second = OptoReg::Name(R_F31_num);
1235 1235 src_second_rc = rc_float;
1236 1236 }
1237 1237
1238 1238 // --------------------------------------
1239 1239 // Check for float->int copy; requires a trip through memory
1240 1240 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1241 1241 int offset = frame::register_save_words*wordSize;
1242 1242 if( cbuf ) {
1243 1243 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1244 1244 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1245 1245 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1246 1246 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1247 1247 }
1248 1248 #ifndef PRODUCT
1249 1249 else if( !do_size ) {
1250 1250 if( size != 0 ) st->print("\n\t");
1251 1251 st->print( "SUB R_SP,16,R_SP\n");
1252 1252 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1253 1253 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1254 1254 st->print("\tADD R_SP,16,R_SP\n");
1255 1255 }
1256 1256 #endif
1257 1257 size += 16;
1258 1258 }
1259 1259
1260 1260 // --------------------------------------
1261 1261 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1262 1262 // In such cases, I have to do the big-endian swap. For aligned targets, the
1263 1263 // hardware does the flop for me. Doubles are always aligned, so no problem
1264 1264 // there. Misaligned sources only come from native-long-returns (handled
1265 1265 // special below).
1266 1266 #ifndef _LP64
1267 1267 if( src_first_rc == rc_int && // source is already big-endian
1268 1268 src_second_rc != rc_bad && // 64-bit move
1269 1269 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1270 1270 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1271 1271 // Do the big-endian flop.
1272 1272 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1273 1273 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1274 1274 }
1275 1275 #endif
1276 1276
1277 1277 // --------------------------------------
1278 1278 // Check for integer reg-reg copy
1279 1279 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1280 1280 #ifndef _LP64
1281 1281 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1282 1282 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1283 1283 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1284 1284 // operand contains the least significant word of the 64-bit value and vice versa.
1285 1285 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1286 1286 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1287 1287 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1288 1288 if( cbuf ) {
1289 1289 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1290 1290 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1291 1291 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1292 1292 #ifndef PRODUCT
1293 1293 } else if( !do_size ) {
1294 1294 if( size != 0 ) st->print("\n\t");
1295 1295 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1296 1296 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1297 1297 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1298 1298 #endif
1299 1299 }
1300 1300 return size+12;
1301 1301 }
1302 1302 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1303 1303 // returning a long value in I0/I1
1304 1304 // a SpillCopy must be able to target a return instruction's reg_class
1305 1305 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1306 1306 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1307 1307 // operand contains the least significant word of the 64-bit value and vice versa.
1308 1308 OptoReg::Name tdest = dst_first;
1309 1309
1310 1310 if (src_first == dst_first) {
1311 1311 tdest = OptoReg::Name(R_O7_num);
1312 1312 size += 4;
1313 1313 }
1314 1314
1315 1315 if( cbuf ) {
1316 1316 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1317 1317 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1318 1318 // ShrL_reg_imm6
1319 1319 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1320 1320 // ShrR_reg_imm6 src, 0, dst
1321 1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1322 1322 if (tdest != dst_first) {
1323 1323 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1324 1324 }
1325 1325 }
1326 1326 #ifndef PRODUCT
1327 1327 else if( !do_size ) {
1328 1328 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1329 1329 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1330 1330 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1331 1331 if (tdest != dst_first) {
1332 1332 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1333 1333 }
1334 1334 }
1335 1335 #endif // PRODUCT
1336 1336 return size+8;
1337 1337 }
1338 1338 #endif // !_LP64
1339 1339 // Else normal reg-reg copy
1340 1340 assert( src_second != dst_first, "smashed second before evacuating it" );
1341 1341 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1342 1342 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1343 1343 // This moves an aligned adjacent pair.
1344 1344 // See if we are done.
1345 1345 if( src_first+1 == src_second && dst_first+1 == dst_second )
1346 1346 return size;
1347 1347 }
1348 1348
1349 1349 // Check for integer store
1350 1350 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1351 1351 int offset = ra_->reg2offset(dst_first);
1352 1352 // Further check for aligned-adjacent pair, so we can use a double store
1353 1353 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1354 1354 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1355 1355 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1356 1356 }
1357 1357
1358 1358 // Check for integer load
1359 1359 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1360 1360 int offset = ra_->reg2offset(src_first);
1361 1361 // Further check for aligned-adjacent pair, so we can use a double load
1362 1362 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1363 1363 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1364 1364 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1365 1365 }
1366 1366
1367 1367 // Check for float reg-reg copy
1368 1368 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1369 1369 // Further check for aligned-adjacent pair, so we can use a double move
1370 1370 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1371 1371 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1372 1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1373 1373 }
1374 1374
1375 1375 // Check for float store
1376 1376 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1377 1377 int offset = ra_->reg2offset(dst_first);
1378 1378 // Further check for aligned-adjacent pair, so we can use a double store
1379 1379 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1380 1380 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1381 1381 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1382 1382 }
1383 1383
1384 1384 // Check for float load
1385 1385 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1386 1386 int offset = ra_->reg2offset(src_first);
1387 1387 // Further check for aligned-adjacent pair, so we can use a double load
1388 1388 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1389 1389 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1390 1390 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1391 1391 }
1392 1392
1393 1393 // --------------------------------------------------------------------
1394 1394 // Check for hi bits still needing moving. Only happens for misaligned
1395 1395 // arguments to native calls.
1396 1396 if( src_second == dst_second )
1397 1397 return size; // Self copy; no move
1398 1398 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1399 1399
1400 1400 #ifndef _LP64
1401 1401 // In the LP64 build, all registers can be moved as aligned/adjacent
1402 1402 // pairs, so there's never any need to move the high bits separately.
1403 1403 // The 32-bit builds have to deal with the 32-bit ABI which can force
1404 1404 // all sorts of silly alignment problems.
1405 1405
1406 1406 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1407 1407 // 32-bits of a 64-bit register, but are needed in low bits of another
1408 1408 // register (else it's a hi-bits-to-hi-bits copy which should have
1409 1409 // happened already as part of a 64-bit move)
1410 1410 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1411 1411 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1412 1412 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1413 1413 // Shift src_second down to dst_second's low bits.
1414 1414 if( cbuf ) {
1415 1415 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1416 1416 #ifndef PRODUCT
1417 1417 } else if( !do_size ) {
1418 1418 if( size != 0 ) st->print("\n\t");
1419 1419 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1420 1420 #endif
1421 1421 }
1422 1422 return size+4;
1423 1423 }
1424 1424
1425 1425 // Check for high word integer store. Must down-shift the hi bits
1426 1426 // into a temp register, then fall into the case of storing int bits.
1427 1427 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1428 1428 // Shift src_second down to dst_second's low bits.
1429 1429 if( cbuf ) {
1430 1430 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1431 1431 #ifndef PRODUCT
1432 1432 } else if( !do_size ) {
1433 1433 if( size != 0 ) st->print("\n\t");
1434 1434 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1435 1435 #endif
1436 1436 }
1437 1437 size+=4;
1438 1438 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1439 1439 }
1440 1440
1441 1441 // Check for high word integer load
1442 1442 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1443 1443 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1444 1444
1445 1445 // Check for high word integer store
1446 1446 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1447 1447 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1448 1448
1449 1449 // Check for high word float store
1450 1450 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1451 1451 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1452 1452
1453 1453 #endif // !_LP64
1454 1454
1455 1455 Unimplemented();
1456 1456 }
1457 1457
1458 1458 #ifndef PRODUCT
1459 1459 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1460 1460 implementation( NULL, ra_, false, st );
1461 1461 }
1462 1462 #endif
1463 1463
1464 1464 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1465 1465 implementation( &cbuf, ra_, false, NULL );
1466 1466 }
1467 1467
1468 1468 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1469 1469 return implementation( NULL, ra_, true, NULL );
1470 1470 }
1471 1471
1472 1472 //=============================================================================
1473 1473 #ifndef PRODUCT
1474 1474 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1475 1475 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1476 1476 }
1477 1477 #endif
1478 1478
1479 1479 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1480 1480 MacroAssembler _masm(&cbuf);
1481 1481 for(int i = 0; i < _count; i += 1) {
1482 1482 __ nop();
1483 1483 }
1484 1484 }
1485 1485
1486 1486 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1487 1487 return 4 * _count;
1488 1488 }
1489 1489
1490 1490
1491 1491 //=============================================================================
1492 1492 #ifndef PRODUCT
1493 1493 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1494 1494 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1495 1495 int reg = ra_->get_reg_first(this);
1496 1496 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1497 1497 }
1498 1498 #endif
1499 1499
1500 1500 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 1501 MacroAssembler _masm(&cbuf);
1502 1502 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1503 1503 int reg = ra_->get_encode(this);
1504 1504
1505 1505 if (Assembler::is_simm13(offset)) {
1506 1506 __ add(SP, offset, reg_to_register_object(reg));
1507 1507 } else {
1508 1508 __ set(offset, O7);
1509 1509 __ add(SP, O7, reg_to_register_object(reg));
1510 1510 }
1511 1511 }
1512 1512
1513 1513 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1514 1514 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1515 1515 assert(ra_ == ra_->C->regalloc(), "sanity");
1516 1516 return ra_->C->scratch_emit_size(this);
1517 1517 }
1518 1518
1519 1519 //=============================================================================
1520 1520
1521 1521 // emit call stub, compiled java to interpretor
1522 1522 void emit_java_to_interp(CodeBuffer &cbuf ) {
1523 1523
1524 1524 // Stub is fixed up when the corresponding call is converted from calling
1525 1525 // compiled code to calling interpreted code.
1526 1526 // set (empty), G5
1527 1527 // jmp -1
1528 1528
1529 1529 address mark = cbuf.insts_mark(); // get mark within main instrs section
1530 1530
1531 1531 MacroAssembler _masm(&cbuf);
1532 1532
1533 1533 address base =
1534 1534 __ start_a_stub(Compile::MAX_stubs_size);
1535 1535 if (base == NULL) return; // CodeBuffer::expand failed
1536 1536
1537 1537 // static stub relocation stores the instruction address of the call
1538 1538 __ relocate(static_stub_Relocation::spec(mark));
1539 1539
1540 1540 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1541 1541
1542 1542 __ set_inst_mark();
1543 1543 AddressLiteral addrlit(-1);
1544 1544 __ JUMP(addrlit, G3, 0);
1545 1545
1546 1546 __ delayed()->nop();
1547 1547
1548 1548 // Update current stubs pointer and restore code_end.
1549 1549 __ end_a_stub();
1550 1550 }
1551 1551
1552 1552 // size of call stub, compiled java to interpretor
1553 1553 uint size_java_to_interp() {
1554 1554 // This doesn't need to be accurate but it must be larger or equal to
1555 1555 // the real size of the stub.
1556 1556 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1557 1557 NativeJump::instruction_size + // sethi; jmp; nop
1558 1558 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1559 1559 }
1560 1560 // relocation entries for call stub, compiled java to interpretor
1561 1561 uint reloc_java_to_interp() {
1562 1562 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1563 1563 }
1564 1564
1565 1565
1566 1566 //=============================================================================
1567 1567 #ifndef PRODUCT
1568 1568 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1569 1569 st->print_cr("\nUEP:");
1570 1570 #ifdef _LP64
1571 1571 if (UseCompressedOops) {
1572 1572 assert(Universe::heap() != NULL, "java heap should be initialized");
1573 1573 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1574 1574 st->print_cr("\tSLL R_G5,3,R_G5");
1575 1575 if (Universe::narrow_oop_base() != NULL)
1576 1576 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1577 1577 } else {
1578 1578 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1579 1579 }
1580 1580 st->print_cr("\tCMP R_G5,R_G3" );
1581 1581 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1582 1582 #else // _LP64
1583 1583 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1584 1584 st->print_cr("\tCMP R_G5,R_G3" );
1585 1585 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1586 1586 #endif // _LP64
1587 1587 }
1588 1588 #endif
1589 1589
1590 1590 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1591 1591 MacroAssembler _masm(&cbuf);
1592 1592 Label L;
1593 1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1594 1594 Register temp_reg = G3;
1595 1595 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1596 1596
1597 1597 // Load klass from receiver
1598 1598 __ load_klass(O0, temp_reg);
1599 1599 // Compare against expected klass
1600 1600 __ cmp(temp_reg, G5_ic_reg);
1601 1601 // Branch to miss code, checks xcc or icc depending
1602 1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1603 1603 }
1604 1604
1605 1605 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1606 1606 return MachNode::size(ra_);
1607 1607 }
1608 1608
1609 1609
1610 1610 //=============================================================================
1611 1611
1612 1612 uint size_exception_handler() {
1613 1613 if (TraceJumps) {
1614 1614 return (400); // just a guess
1615 1615 }
1616 1616 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1617 1617 }
1618 1618
1619 1619 uint size_deopt_handler() {
1620 1620 if (TraceJumps) {
1621 1621 return (400); // just a guess
1622 1622 }
1623 1623 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1624 1624 }
1625 1625
1626 1626 // Emit exception handler code.
1627 1627 int emit_exception_handler(CodeBuffer& cbuf) {
1628 1628 Register temp_reg = G3;
1629 1629 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1630 1630 MacroAssembler _masm(&cbuf);
1631 1631
1632 1632 address base =
1633 1633 __ start_a_stub(size_exception_handler());
1634 1634 if (base == NULL) return 0; // CodeBuffer::expand failed
1635 1635
1636 1636 int offset = __ offset();
1637 1637
1638 1638 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1639 1639 __ delayed()->nop();
1640 1640
1641 1641 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1642 1642
1643 1643 __ end_a_stub();
1644 1644
1645 1645 return offset;
1646 1646 }
1647 1647
1648 1648 int emit_deopt_handler(CodeBuffer& cbuf) {
1649 1649 // Can't use any of the current frame's registers as we may have deopted
1650 1650 // at a poll and everything (including G3) can be live.
1651 1651 Register temp_reg = L0;
1652 1652 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1653 1653 MacroAssembler _masm(&cbuf);
1654 1654
1655 1655 address base =
1656 1656 __ start_a_stub(size_deopt_handler());
1657 1657 if (base == NULL) return 0; // CodeBuffer::expand failed
1658 1658
1659 1659 int offset = __ offset();
1660 1660 __ save_frame(0);
1661 1661 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1662 1662 __ delayed()->restore();
1663 1663
1664 1664 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1665 1665
1666 1666 __ end_a_stub();
1667 1667 return offset;
1668 1668
1669 1669 }
1670 1670
1671 1671 // Given a register encoding, produce a Integer Register object
1672 1672 static Register reg_to_register_object(int register_encoding) {
1673 1673 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1674 1674 return as_Register(register_encoding);
1675 1675 }
1676 1676
1677 1677 // Given a register encoding, produce a single-precision Float Register object
1678 1678 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1679 1679 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1680 1680 return as_SingleFloatRegister(register_encoding);
1681 1681 }
1682 1682
1683 1683 // Given a register encoding, produce a double-precision Float Register object
1684 1684 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1685 1685 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1686 1686 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1687 1687 return as_DoubleFloatRegister(register_encoding);
1688 1688 }
1689 1689
1690 1690 const bool Matcher::match_rule_supported(int opcode) {
1691 1691 if (!has_match_rule(opcode))
1692 1692 return false;
1693 1693
1694 1694 switch (opcode) {
1695 1695 case Op_CountLeadingZerosI:
1696 1696 case Op_CountLeadingZerosL:
1697 1697 case Op_CountTrailingZerosI:
1698 1698 case Op_CountTrailingZerosL:
1699 1699 if (!UsePopCountInstruction)
1700 1700 return false;
1701 1701 break;
1702 1702 }
1703 1703
1704 1704 return true; // Per default match rules are supported.
1705 1705 }
1706 1706
1707 1707 int Matcher::regnum_to_fpu_offset(int regnum) {
1708 1708 return regnum - 32; // The FP registers are in the second chunk
1709 1709 }
1710 1710
1711 1711 #ifdef ASSERT
1712 1712 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1713 1713 #endif
1714 1714
1715 1715 // Vector width in bytes
1716 1716 const uint Matcher::vector_width_in_bytes(void) {
1717 1717 return 8;
1718 1718 }
1719 1719
1720 1720 // Vector ideal reg
1721 1721 const uint Matcher::vector_ideal_reg(void) {
1722 1722 return Op_RegD;
1723 1723 }
1724 1724
1725 1725 // USII supports fxtof through the whole range of number, USIII doesn't
1726 1726 const bool Matcher::convL2FSupported(void) {
1727 1727 return VM_Version::has_fast_fxtof();
1728 1728 }
1729 1729
1730 1730 // Is this branch offset short enough that a short branch can be used?
1731 1731 //
1732 1732 // NOTE: If the platform does not provide any short branch variants, then
1733 1733 // this method should return false for offset 0.
1734 1734 bool Matcher::is_short_branch_offset(int rule, int offset) {
1735 1735 return false;
1736 1736 }
1737 1737
1738 1738 const bool Matcher::isSimpleConstant64(jlong value) {
1739 1739 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1740 1740 // Depends on optimizations in MacroAssembler::setx.
1741 1741 int hi = (int)(value >> 32);
1742 1742 int lo = (int)(value & ~0);
1743 1743 return (hi == 0) || (hi == -1) || (lo == 0);
1744 1744 }
1745 1745
1746 1746 // No scaling for the parameter the ClearArray node.
1747 1747 const bool Matcher::init_array_count_is_in_bytes = true;
1748 1748
1749 1749 // Threshold size for cleararray.
1750 1750 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1751 1751
1752 1752 // Should the Matcher clone shifts on addressing modes, expecting them to
1753 1753 // be subsumed into complex addressing expressions or compute them into
1754 1754 // registers? True for Intel but false for most RISCs
1755 1755 const bool Matcher::clone_shift_expressions = false;
1756 1756
1757 1757 bool Matcher::narrow_oop_use_complex_address() {
1758 1758 NOT_LP64(ShouldNotCallThis());
1759 1759 assert(UseCompressedOops, "only for compressed oops code");
1760 1760 return false;
1761 1761 }
1762 1762
1763 1763 // Is it better to copy float constants, or load them directly from memory?
1764 1764 // Intel can load a float constant from a direct address, requiring no
1765 1765 // extra registers. Most RISCs will have to materialize an address into a
1766 1766 // register first, so they would do better to copy the constant from stack.
1767 1767 const bool Matcher::rematerialize_float_constants = false;
1768 1768
1769 1769 // If CPU can load and store mis-aligned doubles directly then no fixup is
1770 1770 // needed. Else we split the double into 2 integer pieces and move it
1771 1771 // piece-by-piece. Only happens when passing doubles into C code as the
1772 1772 // Java calling convention forces doubles to be aligned.
1773 1773 #ifdef _LP64
1774 1774 const bool Matcher::misaligned_doubles_ok = true;
1775 1775 #else
1776 1776 const bool Matcher::misaligned_doubles_ok = false;
1777 1777 #endif
1778 1778
1779 1779 // No-op on SPARC.
1780 1780 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1781 1781 }
1782 1782
1783 1783 // Advertise here if the CPU requires explicit rounding operations
1784 1784 // to implement the UseStrictFP mode.
1785 1785 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1786 1786
1787 1787 // Are floats conerted to double when stored to stack during deoptimization?
1788 1788 // Sparc does not handle callee-save floats.
1789 1789 bool Matcher::float_in_double() { return false; }
1790 1790
1791 1791 // Do ints take an entire long register or just half?
1792 1792 // Note that we if-def off of _LP64.
1793 1793 // The relevant question is how the int is callee-saved. In _LP64
1794 1794 // the whole long is written but de-opt'ing will have to extract
1795 1795 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1796 1796 #ifdef _LP64
1797 1797 const bool Matcher::int_in_long = true;
1798 1798 #else
1799 1799 const bool Matcher::int_in_long = false;
1800 1800 #endif
1801 1801
1802 1802 // Return whether or not this register is ever used as an argument. This
1803 1803 // function is used on startup to build the trampoline stubs in generateOptoStub.
1804 1804 // Registers not mentioned will be killed by the VM call in the trampoline, and
1805 1805 // arguments in those registers not be available to the callee.
1806 1806 bool Matcher::can_be_java_arg( int reg ) {
1807 1807 // Standard sparc 6 args in registers
1808 1808 if( reg == R_I0_num ||
1809 1809 reg == R_I1_num ||
1810 1810 reg == R_I2_num ||
1811 1811 reg == R_I3_num ||
1812 1812 reg == R_I4_num ||
1813 1813 reg == R_I5_num ) return true;
1814 1814 #ifdef _LP64
1815 1815 // 64-bit builds can pass 64-bit pointers and longs in
1816 1816 // the high I registers
1817 1817 if( reg == R_I0H_num ||
1818 1818 reg == R_I1H_num ||
1819 1819 reg == R_I2H_num ||
1820 1820 reg == R_I3H_num ||
1821 1821 reg == R_I4H_num ||
1822 1822 reg == R_I5H_num ) return true;
1823 1823
1824 1824 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1825 1825 return true;
1826 1826 }
1827 1827
1828 1828 #else
1829 1829 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1830 1830 // Longs cannot be passed in O regs, because O regs become I regs
1831 1831 // after a 'save' and I regs get their high bits chopped off on
1832 1832 // interrupt.
1833 1833 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1834 1834 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1835 1835 #endif
1836 1836 // A few float args in registers
1837 1837 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1838 1838
1839 1839 return false;
1840 1840 }
1841 1841
1842 1842 bool Matcher::is_spillable_arg( int reg ) {
1843 1843 return can_be_java_arg(reg);
1844 1844 }
1845 1845
1846 1846 // Register for DIVI projection of divmodI
1847 1847 RegMask Matcher::divI_proj_mask() {
1848 1848 ShouldNotReachHere();
1849 1849 return RegMask();
1850 1850 }
1851 1851
1852 1852 // Register for MODI projection of divmodI
1853 1853 RegMask Matcher::modI_proj_mask() {
1854 1854 ShouldNotReachHere();
1855 1855 return RegMask();
1856 1856 }
1857 1857
1858 1858 // Register for DIVL projection of divmodL
1859 1859 RegMask Matcher::divL_proj_mask() {
1860 1860 ShouldNotReachHere();
1861 1861 return RegMask();
1862 1862 }
1863 1863
1864 1864 // Register for MODL projection of divmodL
1865 1865 RegMask Matcher::modL_proj_mask() {
1866 1866 ShouldNotReachHere();
1867 1867 return RegMask();
1868 1868 }
1869 1869
1870 1870 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1871 1871 return L7_REGP_mask;
1872 1872 }
1873 1873
1874 1874 %}
1875 1875
1876 1876
1877 1877 // The intptr_t operand types, defined by textual substitution.
1878 1878 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1879 1879 #ifdef _LP64
1880 1880 #define immX immL
1881 1881 #define immX13 immL13
1882 1882 #define immX13m7 immL13m7
1883 1883 #define iRegX iRegL
1884 1884 #define g1RegX g1RegL
1885 1885 #else
1886 1886 #define immX immI
1887 1887 #define immX13 immI13
1888 1888 #define immX13m7 immI13m7
1889 1889 #define iRegX iRegI
1890 1890 #define g1RegX g1RegI
1891 1891 #endif
1892 1892
1893 1893 //----------ENCODING BLOCK-----------------------------------------------------
1894 1894 // This block specifies the encoding classes used by the compiler to output
1895 1895 // byte streams. Encoding classes are parameterized macros used by
1896 1896 // Machine Instruction Nodes in order to generate the bit encoding of the
1897 1897 // instruction. Operands specify their base encoding interface with the
1898 1898 // interface keyword. There are currently supported four interfaces,
1899 1899 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1900 1900 // operand to generate a function which returns its register number when
1901 1901 // queried. CONST_INTER causes an operand to generate a function which
1902 1902 // returns the value of the constant when queried. MEMORY_INTER causes an
1903 1903 // operand to generate four functions which return the Base Register, the
1904 1904 // Index Register, the Scale Value, and the Offset Value of the operand when
1905 1905 // queried. COND_INTER causes an operand to generate six functions which
1906 1906 // return the encoding code (ie - encoding bits for the instruction)
1907 1907 // associated with each basic boolean condition for a conditional instruction.
1908 1908 //
1909 1909 // Instructions specify two basic values for encoding. Again, a function
1910 1910 // is available to check if the constant displacement is an oop. They use the
1911 1911 // ins_encode keyword to specify their encoding classes (which must be
1912 1912 // a sequence of enc_class names, and their parameters, specified in
1913 1913 // the encoding block), and they use the
1914 1914 // opcode keyword to specify, in order, their primary, secondary, and
1915 1915 // tertiary opcode. Only the opcode sections which a particular instruction
1916 1916 // needs for encoding need to be specified.
1917 1917 encode %{
1918 1918 enc_class enc_untested %{
1919 1919 #ifdef ASSERT
1920 1920 MacroAssembler _masm(&cbuf);
1921 1921 __ untested("encoding");
1922 1922 #endif
1923 1923 %}
1924 1924
1925 1925 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1926 1926 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1927 1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1928 1928 %}
1929 1929
1930 1930 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1931 1931 emit_form3_mem_reg(cbuf, this, $primary, -1,
1932 1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1933 1933 %}
1934 1934
1935 1935 enc_class form3_mem_prefetch_read( memory mem ) %{
1936 1936 emit_form3_mem_reg(cbuf, this, $primary, -1,
1937 1937 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1938 1938 %}
1939 1939
1940 1940 enc_class form3_mem_prefetch_write( memory mem ) %{
1941 1941 emit_form3_mem_reg(cbuf, this, $primary, -1,
1942 1942 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1943 1943 %}
1944 1944
1945 1945 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1946 1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1947 1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1948 1948 guarantee($mem$$index == R_G0_enc, "double index?");
1949 1949 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1950 1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1951 1951 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1952 1952 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1953 1953 %}
1954 1954
1955 1955 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1956 1956 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1957 1957 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1958 1958 guarantee($mem$$index == R_G0_enc, "double index?");
1959 1959 // Load long with 2 instructions
1960 1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1961 1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1962 1962 %}
1963 1963
1964 1964 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1965 1965 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1966 1966 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1967 1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1968 1968 %}
1969 1969
1970 1970 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1971 1971 // Encode a reg-reg copy. If it is useless, then empty encoding.
1972 1972 if( $rs2$$reg != $rd$$reg )
1973 1973 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1974 1974 %}
1975 1975
1976 1976 // Target lo half of long
1977 1977 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1978 1978 // Encode a reg-reg copy. If it is useless, then empty encoding.
1979 1979 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1980 1980 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1981 1981 %}
1982 1982
1983 1983 // Source lo half of long
1984 1984 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1985 1985 // Encode a reg-reg copy. If it is useless, then empty encoding.
1986 1986 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1987 1987 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1988 1988 %}
1989 1989
1990 1990 // Target hi half of long
1991 1991 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1992 1992 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1993 1993 %}
1994 1994
1995 1995 // Source lo half of long, and leave it sign extended.
1996 1996 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
1997 1997 // Sign extend low half
1998 1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
1999 1999 %}
2000 2000
2001 2001 // Source hi half of long, and leave it sign extended.
2002 2002 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2003 2003 // Shift high half to low half
2004 2004 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2005 2005 %}
2006 2006
2007 2007 // Source hi half of long
2008 2008 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2009 2009 // Encode a reg-reg copy. If it is useless, then empty encoding.
2010 2010 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2011 2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2012 2012 %}
2013 2013
2014 2014 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2015 2015 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2016 2016 %}
2017 2017
2018 2018 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2019 2019 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2020 2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2021 2021 %}
2022 2022
2023 2023 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2024 2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2025 2025 // clear if nothing else is happening
2026 2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2027 2027 // blt,a,pn done
2028 2028 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2029 2029 // mov dst,-1 in delay slot
2030 2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2031 2031 %}
2032 2032
2033 2033 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2034 2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2035 2035 %}
2036 2036
2037 2037 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2038 2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2039 2039 %}
2040 2040
2041 2041 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2042 2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2043 2043 %}
2044 2044
2045 2045 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2046 2046 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2047 2047 %}
2048 2048
2049 2049 enc_class move_return_pc_to_o1() %{
2050 2050 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2051 2051 %}
2052 2052
2053 2053 #ifdef _LP64
2054 2054 /* %%% merge with enc_to_bool */
2055 2055 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2056 2056 MacroAssembler _masm(&cbuf);
2057 2057
2058 2058 Register src_reg = reg_to_register_object($src$$reg);
2059 2059 Register dst_reg = reg_to_register_object($dst$$reg);
2060 2060 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2061 2061 %}
2062 2062 #endif
2063 2063
2064 2064 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2065 2065 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2066 2066 MacroAssembler _masm(&cbuf);
2067 2067
2068 2068 Register p_reg = reg_to_register_object($p$$reg);
2069 2069 Register q_reg = reg_to_register_object($q$$reg);
2070 2070 Register y_reg = reg_to_register_object($y$$reg);
2071 2071 Register tmp_reg = reg_to_register_object($tmp$$reg);
2072 2072
2073 2073 __ subcc( p_reg, q_reg, p_reg );
2074 2074 __ add ( p_reg, y_reg, tmp_reg );
2075 2075 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2076 2076 %}
2077 2077
2078 2078 enc_class form_d2i_helper(regD src, regF dst) %{
2079 2079 // fcmp %fcc0,$src,$src
2080 2080 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2081 2081 // branch %fcc0 not-nan, predict taken
2082 2082 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2083 2083 // fdtoi $src,$dst
2084 2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2085 2085 // fitos $dst,$dst (if nan)
2086 2086 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2087 2087 // clear $dst (if nan)
2088 2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2089 2089 // carry on here...
2090 2090 %}
2091 2091
2092 2092 enc_class form_d2l_helper(regD src, regD dst) %{
2093 2093 // fcmp %fcc0,$src,$src check for NAN
2094 2094 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2095 2095 // branch %fcc0 not-nan, predict taken
2096 2096 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2097 2097 // fdtox $src,$dst convert in delay slot
2098 2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2099 2099 // fxtod $dst,$dst (if nan)
2100 2100 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2101 2101 // clear $dst (if nan)
2102 2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2103 2103 // carry on here...
2104 2104 %}
2105 2105
2106 2106 enc_class form_f2i_helper(regF src, regF dst) %{
2107 2107 // fcmps %fcc0,$src,$src
2108 2108 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2109 2109 // branch %fcc0 not-nan, predict taken
2110 2110 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2111 2111 // fstoi $src,$dst
2112 2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2113 2113 // fitos $dst,$dst (if nan)
2114 2114 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2115 2115 // clear $dst (if nan)
2116 2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2117 2117 // carry on here...
2118 2118 %}
2119 2119
2120 2120 enc_class form_f2l_helper(regF src, regD dst) %{
2121 2121 // fcmps %fcc0,$src,$src
2122 2122 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2123 2123 // branch %fcc0 not-nan, predict taken
2124 2124 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2125 2125 // fstox $src,$dst
2126 2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2127 2127 // fxtod $dst,$dst (if nan)
2128 2128 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2129 2129 // clear $dst (if nan)
2130 2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2131 2131 // carry on here...
2132 2132 %}
2133 2133
2134 2134 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2135 2135 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2136 2136 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2137 2137 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2138 2138
2139 2139 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2140 2140
2141 2141 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2142 2142 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2143 2143
2144 2144 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2145 2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2146 2146 %}
2147 2147
2148 2148 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2149 2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2150 2150 %}
2151 2151
2152 2152 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2153 2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2154 2154 %}
2155 2155
2156 2156 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2157 2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2158 2158 %}
2159 2159
2160 2160 enc_class form3_convI2F(regF rs2, regF rd) %{
2161 2161 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2162 2162 %}
2163 2163
2164 2164 // Encloding class for traceable jumps
2165 2165 enc_class form_jmpl(g3RegP dest) %{
2166 2166 emit_jmpl(cbuf, $dest$$reg);
2167 2167 %}
2168 2168
2169 2169 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2170 2170 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2171 2171 %}
2172 2172
2173 2173 enc_class form2_nop() %{
2174 2174 emit_nop(cbuf);
2175 2175 %}
2176 2176
2177 2177 enc_class form2_illtrap() %{
2178 2178 emit_illtrap(cbuf);
2179 2179 %}
2180 2180
2181 2181
2182 2182 // Compare longs and convert into -1, 0, 1.
2183 2183 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2184 2184 // CMP $src1,$src2
2185 2185 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2186 2186 // blt,a,pn done
2187 2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2188 2188 // mov dst,-1 in delay slot
2189 2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2190 2190 // bgt,a,pn done
2191 2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2192 2192 // mov dst,1 in delay slot
2193 2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2194 2194 // CLR $dst
2195 2195 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2196 2196 %}
2197 2197
2198 2198 enc_class enc_PartialSubtypeCheck() %{
2199 2199 MacroAssembler _masm(&cbuf);
2200 2200 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2201 2201 __ delayed()->nop();
2202 2202 %}
2203 2203
2204 2204 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2205 2205 MacroAssembler _masm(&cbuf);
2206 2206 Label &L = *($labl$$label);
2207 2207 Assembler::Predict predict_taken =
2208 2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2209 2209
2210 2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2211 2211 __ delayed()->nop();
2212 2212 %}
2213 2213
2214 2214 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2215 2215 MacroAssembler _masm(&cbuf);
2216 2216 Label &L = *($labl$$label);
2217 2217 Assembler::Predict predict_taken =
2218 2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2219 2219
2220 2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2221 2221 __ delayed()->nop();
2222 2222 %}
2223 2223
2224 2224 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2225 2225 MacroAssembler _masm(&cbuf);
2226 2226 Label &L = *($labl$$label);
2227 2227 Assembler::Predict predict_taken =
2228 2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2229 2229
2230 2230 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2231 2231 __ delayed()->nop();
2232 2232 %}
2233 2233
2234 2234 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2235 2235 MacroAssembler _masm(&cbuf);
2236 2236 Label &L = *($labl$$label);
2237 2237 Assembler::Predict predict_taken =
2238 2238 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2239 2239
2240 2240 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2241 2241 __ delayed()->nop();
2242 2242 %}
2243 2243
2244 2244 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2245 2245 MacroAssembler _masm(&cbuf);
2246 2246
2247 2247 Register switch_reg = as_Register($switch_val$$reg);
2248 2248 Register table_reg = O7;
2249 2249
2250 2250 address table_base = __ address_table_constant(_index2label);
2251 2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2252 2252
2253 2253 // Move table address into a register.
2254 2254 __ set(table_base, table_reg, rspec);
2255 2255
2256 2256 // Jump to base address + switch value
2257 2257 __ ld_ptr(table_reg, switch_reg, table_reg);
2258 2258 __ jmp(table_reg, G0);
2259 2259 __ delayed()->nop();
2260 2260
2261 2261 %}
2262 2262
2263 2263 enc_class enc_ba( Label labl ) %{
2264 2264 MacroAssembler _masm(&cbuf);
2265 2265 Label &L = *($labl$$label);
2266 2266 __ ba(false, L);
2267 2267 __ delayed()->nop();
2268 2268 %}
2269 2269
2270 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2271 2271 MacroAssembler _masm(&cbuf);
2272 2272 Label &L = *$labl$$label;
2273 2273 Assembler::Predict predict_taken =
2274 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2275 2275
2276 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2277 2277 __ delayed()->nop();
2278 2278 %}
2279 2279
2280 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2281 2281 int op = (Assembler::arith_op << 30) |
2282 2282 ($dst$$reg << 25) |
2283 2283 (Assembler::movcc_op3 << 19) |
2284 2284 (1 << 18) | // cc2 bit for 'icc'
2285 2285 ($cmp$$cmpcode << 14) |
2286 2286 (0 << 13) | // select register move
2287 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2288 2288 ($src$$reg << 0);
2289 2289 cbuf.insts()->emit_int32(op);
2290 2290 %}
2291 2291
2292 2292 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2293 2293 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2294 2294 int op = (Assembler::arith_op << 30) |
2295 2295 ($dst$$reg << 25) |
2296 2296 (Assembler::movcc_op3 << 19) |
2297 2297 (1 << 18) | // cc2 bit for 'icc'
2298 2298 ($cmp$$cmpcode << 14) |
2299 2299 (1 << 13) | // select immediate move
2300 2300 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2301 2301 (simm11 << 0);
2302 2302 cbuf.insts()->emit_int32(op);
2303 2303 %}
2304 2304
2305 2305 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2306 2306 int op = (Assembler::arith_op << 30) |
2307 2307 ($dst$$reg << 25) |
2308 2308 (Assembler::movcc_op3 << 19) |
2309 2309 (0 << 18) | // cc2 bit for 'fccX'
2310 2310 ($cmp$$cmpcode << 14) |
2311 2311 (0 << 13) | // select register move
2312 2312 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2313 2313 ($src$$reg << 0);
2314 2314 cbuf.insts()->emit_int32(op);
2315 2315 %}
2316 2316
2317 2317 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2318 2318 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2319 2319 int op = (Assembler::arith_op << 30) |
2320 2320 ($dst$$reg << 25) |
2321 2321 (Assembler::movcc_op3 << 19) |
2322 2322 (0 << 18) | // cc2 bit for 'fccX'
2323 2323 ($cmp$$cmpcode << 14) |
2324 2324 (1 << 13) | // select immediate move
2325 2325 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2326 2326 (simm11 << 0);
2327 2327 cbuf.insts()->emit_int32(op);
2328 2328 %}
2329 2329
2330 2330 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2331 2331 int op = (Assembler::arith_op << 30) |
2332 2332 ($dst$$reg << 25) |
2333 2333 (Assembler::fpop2_op3 << 19) |
2334 2334 (0 << 18) |
2335 2335 ($cmp$$cmpcode << 14) |
2336 2336 (1 << 13) | // select register move
2337 2337 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2338 2338 ($primary << 5) | // select single, double or quad
2339 2339 ($src$$reg << 0);
2340 2340 cbuf.insts()->emit_int32(op);
2341 2341 %}
2342 2342
2343 2343 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2344 2344 int op = (Assembler::arith_op << 30) |
2345 2345 ($dst$$reg << 25) |
2346 2346 (Assembler::fpop2_op3 << 19) |
2347 2347 (0 << 18) |
2348 2348 ($cmp$$cmpcode << 14) |
2349 2349 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2350 2350 ($primary << 5) | // select single, double or quad
2351 2351 ($src$$reg << 0);
2352 2352 cbuf.insts()->emit_int32(op);
2353 2353 %}
2354 2354
2355 2355 // Used by the MIN/MAX encodings. Same as a CMOV, but
2356 2356 // the condition comes from opcode-field instead of an argument.
2357 2357 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2358 2358 int op = (Assembler::arith_op << 30) |
2359 2359 ($dst$$reg << 25) |
2360 2360 (Assembler::movcc_op3 << 19) |
2361 2361 (1 << 18) | // cc2 bit for 'icc'
2362 2362 ($primary << 14) |
2363 2363 (0 << 13) | // select register move
2364 2364 (0 << 11) | // cc1, cc0 bits for 'icc'
2365 2365 ($src$$reg << 0);
2366 2366 cbuf.insts()->emit_int32(op);
2367 2367 %}
2368 2368
2369 2369 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2370 2370 int op = (Assembler::arith_op << 30) |
2371 2371 ($dst$$reg << 25) |
2372 2372 (Assembler::movcc_op3 << 19) |
2373 2373 (6 << 16) | // cc2 bit for 'xcc'
2374 2374 ($primary << 14) |
2375 2375 (0 << 13) | // select register move
2376 2376 (0 << 11) | // cc1, cc0 bits for 'icc'
2377 2377 ($src$$reg << 0);
2378 2378 cbuf.insts()->emit_int32(op);
2379 2379 %}
2380 2380
2381 2381 // Utility encoding for loading a 64 bit Pointer into a register
2382 2382 // The 64 bit pointer is stored in the generated code stream
2383 2383 enc_class SetPtr( immP src, iRegP rd ) %{
2384 2384 Register dest = reg_to_register_object($rd$$reg);
2385 2385 MacroAssembler _masm(&cbuf);
2386 2386 // [RGV] This next line should be generated from ADLC
2387 2387 if ( _opnds[1]->constant_is_oop() ) {
2388 2388 intptr_t val = $src$$constant;
2389 2389 __ set_oop_constant((jobject)val, dest);
2390 2390 } else { // non-oop pointers, e.g. card mark base, heap top
2391 2391 __ set($src$$constant, dest);
2392 2392 }
2393 2393 %}
2394 2394
2395 2395 enc_class Set13( immI13 src, iRegI rd ) %{
2396 2396 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2397 2397 %}
2398 2398
2399 2399 enc_class SetHi22( immI src, iRegI rd ) %{
2400 2400 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2401 2401 %}
2402 2402
2403 2403 enc_class Set32( immI src, iRegI rd ) %{
2404 2404 MacroAssembler _masm(&cbuf);
2405 2405 __ set($src$$constant, reg_to_register_object($rd$$reg));
2406 2406 %}
2407 2407
2408 2408 enc_class SetNull( iRegI rd ) %{
2409 2409 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2410 2410 %}
2411 2411
2412 2412 enc_class call_epilog %{
2413 2413 if( VerifyStackAtCalls ) {
2414 2414 MacroAssembler _masm(&cbuf);
2415 2415 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2416 2416 Register temp_reg = G3;
2417 2417 __ add(SP, framesize, temp_reg);
2418 2418 __ cmp(temp_reg, FP);
2419 2419 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2420 2420 }
2421 2421 %}
2422 2422
2423 2423 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2424 2424 // to G1 so the register allocator will not have to deal with the misaligned register
2425 2425 // pair.
2426 2426 enc_class adjust_long_from_native_call %{
2427 2427 #ifndef _LP64
2428 2428 if (returns_long()) {
2429 2429 // sllx O0,32,O0
2430 2430 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2431 2431 // srl O1,0,O1
2432 2432 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2433 2433 // or O0,O1,G1
2434 2434 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2435 2435 }
2436 2436 #endif
2437 2437 %}
2438 2438
2439 2439 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2440 2440 // CALL directly to the runtime
2441 2441 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2442 2442 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2443 2443 /*preserve_g2=*/true, /*force far call*/true);
2444 2444 %}
2445 2445
2446 2446 enc_class preserve_SP %{
2447 2447 MacroAssembler _masm(&cbuf);
2448 2448 __ mov(SP, L7_mh_SP_save);
2449 2449 %}
2450 2450
2451 2451 enc_class restore_SP %{
2452 2452 MacroAssembler _masm(&cbuf);
2453 2453 __ mov(L7_mh_SP_save, SP);
2454 2454 %}
2455 2455
2456 2456 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2457 2457 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2458 2458 // who we intended to call.
2459 2459 if ( !_method ) {
2460 2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2461 2461 } else if (_optimized_virtual) {
2462 2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2463 2463 } else {
2464 2464 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2465 2465 }
2466 2466 if( _method ) { // Emit stub for static call
2467 2467 emit_java_to_interp(cbuf);
2468 2468 }
2469 2469 %}
2470 2470
2471 2471 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2472 2472 MacroAssembler _masm(&cbuf);
2473 2473 __ set_inst_mark();
2474 2474 int vtable_index = this->_vtable_index;
2475 2475 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2476 2476 if (vtable_index < 0) {
2477 2477 // must be invalid_vtable_index, not nonvirtual_vtable_index
2478 2478 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2479 2479 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2480 2480 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2481 2481 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2482 2482 // !!!!!
2483 2483 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2484 2484 // emit_call_dynamic_prologue( cbuf );
2485 2485 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2486 2486
2487 2487 address virtual_call_oop_addr = __ inst_mark();
2488 2488 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2489 2489 // who we intended to call.
2490 2490 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2491 2491 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2492 2492 } else {
2493 2493 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2494 2494 // Just go thru the vtable
2495 2495 // get receiver klass (receiver already checked for non-null)
2496 2496 // If we end up going thru a c2i adapter interpreter expects method in G5
2497 2497 int off = __ offset();
2498 2498 __ load_klass(O0, G3_scratch);
2499 2499 int klass_load_size;
2500 2500 if (UseCompressedOops) {
2501 2501 assert(Universe::heap() != NULL, "java heap should be initialized");
2502 2502 if (Universe::narrow_oop_base() == NULL)
2503 2503 klass_load_size = 2*BytesPerInstWord;
2504 2504 else
2505 2505 klass_load_size = 3*BytesPerInstWord;
2506 2506 } else {
2507 2507 klass_load_size = 1*BytesPerInstWord;
2508 2508 }
2509 2509 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2510 2510 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2511 2511 if( __ is_simm13(v_off) ) {
2512 2512 __ ld_ptr(G3, v_off, G5_method);
2513 2513 } else {
2514 2514 // Generate 2 instructions
2515 2515 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2516 2516 __ or3(G5_method, v_off & 0x3ff, G5_method);
2517 2517 // ld_ptr, set_hi, set
2518 2518 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2519 2519 "Unexpected instruction size(s)");
2520 2520 __ ld_ptr(G3, G5_method, G5_method);
2521 2521 }
2522 2522 // NOTE: for vtable dispatches, the vtable entry will never be null.
2523 2523 // However it may very well end up in handle_wrong_method if the
2524 2524 // method is abstract for the particular class.
2525 2525 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2526 2526 // jump to target (either compiled code or c2iadapter)
2527 2527 __ jmpl(G3_scratch, G0, O7);
2528 2528 __ delayed()->nop();
2529 2529 }
2530 2530 %}
2531 2531
2532 2532 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2533 2533 MacroAssembler _masm(&cbuf);
2534 2534
2535 2535 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2536 2536 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2537 2537 // we might be calling a C2I adapter which needs it.
2538 2538
2539 2539 assert(temp_reg != G5_ic_reg, "conflicting registers");
2540 2540 // Load nmethod
2541 2541 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2542 2542
2543 2543 // CALL to compiled java, indirect the contents of G3
2544 2544 __ set_inst_mark();
2545 2545 __ callr(temp_reg, G0);
2546 2546 __ delayed()->nop();
2547 2547 %}
2548 2548
2549 2549 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2550 2550 MacroAssembler _masm(&cbuf);
2551 2551 Register Rdividend = reg_to_register_object($src1$$reg);
2552 2552 Register Rdivisor = reg_to_register_object($src2$$reg);
2553 2553 Register Rresult = reg_to_register_object($dst$$reg);
2554 2554
2555 2555 __ sra(Rdivisor, 0, Rdivisor);
2556 2556 __ sra(Rdividend, 0, Rdividend);
2557 2557 __ sdivx(Rdividend, Rdivisor, Rresult);
2558 2558 %}
2559 2559
2560 2560 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2561 2561 MacroAssembler _masm(&cbuf);
2562 2562
2563 2563 Register Rdividend = reg_to_register_object($src1$$reg);
2564 2564 int divisor = $imm$$constant;
2565 2565 Register Rresult = reg_to_register_object($dst$$reg);
2566 2566
2567 2567 __ sra(Rdividend, 0, Rdividend);
2568 2568 __ sdivx(Rdividend, divisor, Rresult);
2569 2569 %}
2570 2570
2571 2571 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2572 2572 MacroAssembler _masm(&cbuf);
2573 2573 Register Rsrc1 = reg_to_register_object($src1$$reg);
2574 2574 Register Rsrc2 = reg_to_register_object($src2$$reg);
2575 2575 Register Rdst = reg_to_register_object($dst$$reg);
2576 2576
2577 2577 __ sra( Rsrc1, 0, Rsrc1 );
2578 2578 __ sra( Rsrc2, 0, Rsrc2 );
2579 2579 __ mulx( Rsrc1, Rsrc2, Rdst );
2580 2580 __ srlx( Rdst, 32, Rdst );
2581 2581 %}
2582 2582
2583 2583 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2584 2584 MacroAssembler _masm(&cbuf);
2585 2585 Register Rdividend = reg_to_register_object($src1$$reg);
2586 2586 Register Rdivisor = reg_to_register_object($src2$$reg);
2587 2587 Register Rresult = reg_to_register_object($dst$$reg);
2588 2588 Register Rscratch = reg_to_register_object($scratch$$reg);
2589 2589
2590 2590 assert(Rdividend != Rscratch, "");
2591 2591 assert(Rdivisor != Rscratch, "");
2592 2592
2593 2593 __ sra(Rdividend, 0, Rdividend);
2594 2594 __ sra(Rdivisor, 0, Rdivisor);
2595 2595 __ sdivx(Rdividend, Rdivisor, Rscratch);
2596 2596 __ mulx(Rscratch, Rdivisor, Rscratch);
2597 2597 __ sub(Rdividend, Rscratch, Rresult);
2598 2598 %}
2599 2599
2600 2600 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2601 2601 MacroAssembler _masm(&cbuf);
2602 2602
2603 2603 Register Rdividend = reg_to_register_object($src1$$reg);
2604 2604 int divisor = $imm$$constant;
2605 2605 Register Rresult = reg_to_register_object($dst$$reg);
2606 2606 Register Rscratch = reg_to_register_object($scratch$$reg);
2607 2607
2608 2608 assert(Rdividend != Rscratch, "");
2609 2609
2610 2610 __ sra(Rdividend, 0, Rdividend);
2611 2611 __ sdivx(Rdividend, divisor, Rscratch);
2612 2612 __ mulx(Rscratch, divisor, Rscratch);
2613 2613 __ sub(Rdividend, Rscratch, Rresult);
2614 2614 %}
2615 2615
2616 2616 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2617 2617 MacroAssembler _masm(&cbuf);
2618 2618
2619 2619 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2620 2620 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2621 2621
2622 2622 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2623 2623 %}
2624 2624
2625 2625 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2626 2626 MacroAssembler _masm(&cbuf);
2627 2627
2628 2628 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2629 2629 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2630 2630
2631 2631 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2632 2632 %}
2633 2633
2634 2634 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2635 2635 MacroAssembler _masm(&cbuf);
2636 2636
2637 2637 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2638 2638 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2639 2639
2640 2640 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2641 2641 %}
2642 2642
2643 2643 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2644 2644 MacroAssembler _masm(&cbuf);
2645 2645
2646 2646 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2647 2647 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2648 2648
2649 2649 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2650 2650 %}
2651 2651
2652 2652 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2653 2653 MacroAssembler _masm(&cbuf);
2654 2654
2655 2655 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2656 2656 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2657 2657
2658 2658 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2659 2659 %}
2660 2660
2661 2661 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2662 2662 MacroAssembler _masm(&cbuf);
2663 2663
2664 2664 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2665 2665 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2666 2666
2667 2667 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2668 2668 %}
2669 2669
2670 2670 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2671 2671 MacroAssembler _masm(&cbuf);
2672 2672
2673 2673 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2674 2674 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2675 2675
2676 2676 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2677 2677 %}
2678 2678
2679 2679 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2680 2680 MacroAssembler _masm(&cbuf);
2681 2681
2682 2682 Register Roop = reg_to_register_object($oop$$reg);
2683 2683 Register Rbox = reg_to_register_object($box$$reg);
2684 2684 Register Rscratch = reg_to_register_object($scratch$$reg);
2685 2685 Register Rmark = reg_to_register_object($scratch2$$reg);
2686 2686
2687 2687 assert(Roop != Rscratch, "");
2688 2688 assert(Roop != Rmark, "");
2689 2689 assert(Rbox != Rscratch, "");
2690 2690 assert(Rbox != Rmark, "");
2691 2691
2692 2692 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2693 2693 %}
2694 2694
2695 2695 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2696 2696 MacroAssembler _masm(&cbuf);
2697 2697
2698 2698 Register Roop = reg_to_register_object($oop$$reg);
2699 2699 Register Rbox = reg_to_register_object($box$$reg);
2700 2700 Register Rscratch = reg_to_register_object($scratch$$reg);
2701 2701 Register Rmark = reg_to_register_object($scratch2$$reg);
2702 2702
2703 2703 assert(Roop != Rscratch, "");
2704 2704 assert(Roop != Rmark, "");
2705 2705 assert(Rbox != Rscratch, "");
2706 2706 assert(Rbox != Rmark, "");
2707 2707
2708 2708 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2709 2709 %}
2710 2710
2711 2711 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2712 2712 MacroAssembler _masm(&cbuf);
2713 2713 Register Rmem = reg_to_register_object($mem$$reg);
2714 2714 Register Rold = reg_to_register_object($old$$reg);
2715 2715 Register Rnew = reg_to_register_object($new$$reg);
2716 2716
2717 2717 // casx_under_lock picks 1 of 3 encodings:
2718 2718 // For 32-bit pointers you get a 32-bit CAS
2719 2719 // For 64-bit pointers you get a 64-bit CASX
2720 2720 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2721 2721 __ cmp( Rold, Rnew );
2722 2722 %}
2723 2723
2724 2724 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2725 2725 Register Rmem = reg_to_register_object($mem$$reg);
2726 2726 Register Rold = reg_to_register_object($old$$reg);
2727 2727 Register Rnew = reg_to_register_object($new$$reg);
2728 2728
2729 2729 MacroAssembler _masm(&cbuf);
2730 2730 __ mov(Rnew, O7);
2731 2731 __ casx(Rmem, Rold, O7);
2732 2732 __ cmp( Rold, O7 );
2733 2733 %}
2734 2734
2735 2735 // raw int cas, used for compareAndSwap
2736 2736 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2737 2737 Register Rmem = reg_to_register_object($mem$$reg);
2738 2738 Register Rold = reg_to_register_object($old$$reg);
2739 2739 Register Rnew = reg_to_register_object($new$$reg);
2740 2740
2741 2741 MacroAssembler _masm(&cbuf);
2742 2742 __ mov(Rnew, O7);
2743 2743 __ cas(Rmem, Rold, O7);
2744 2744 __ cmp( Rold, O7 );
2745 2745 %}
2746 2746
2747 2747 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2748 2748 Register Rres = reg_to_register_object($res$$reg);
2749 2749
2750 2750 MacroAssembler _masm(&cbuf);
2751 2751 __ mov(1, Rres);
2752 2752 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2753 2753 %}
2754 2754
2755 2755 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2756 2756 Register Rres = reg_to_register_object($res$$reg);
2757 2757
2758 2758 MacroAssembler _masm(&cbuf);
2759 2759 __ mov(1, Rres);
2760 2760 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2761 2761 %}
2762 2762
2763 2763 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2764 2764 MacroAssembler _masm(&cbuf);
2765 2765 Register Rdst = reg_to_register_object($dst$$reg);
2766 2766 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2767 2767 : reg_to_DoubleFloatRegister_object($src1$$reg);
2768 2768 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2769 2769 : reg_to_DoubleFloatRegister_object($src2$$reg);
2770 2770
2771 2771 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2772 2772 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2773 2773 %}
2774 2774
2775 2775 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2776 2776 MacroAssembler _masm(&cbuf);
2777 2777 Register dest = reg_to_register_object($dst$$reg);
2778 2778 Register temp = reg_to_register_object($tmp$$reg);
2779 2779 __ set64( $src$$constant, dest, temp );
2780 2780 %}
2781 2781
2782 2782 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2783 2783 // Load a constant replicated "count" times with width "width"
2784 2784 int bit_width = $width$$constant * 8;
2785 2785 jlong elt_val = $src$$constant;
2786 2786 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2787 2787 jlong val = elt_val;
2788 2788 for (int i = 0; i < $count$$constant - 1; i++) {
2789 2789 val <<= bit_width;
2790 2790 val |= elt_val;
2791 2791 }
2792 2792 jdouble dval = *(jdouble*)&val; // coerce to double type
2793 2793 MacroAssembler _masm(&cbuf);
2794 2794 address double_address = __ double_constant(dval);
2795 2795 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2796 2796 AddressLiteral addrlit(double_address, rspec);
2797 2797
2798 2798 __ sethi(addrlit, $tmp$$Register);
2799 2799 // XXX This is a quick fix for 6833573.
2800 2800 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2801 2801 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2802 2802 %}
2803 2803
2804 2804 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2805 2805 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2806 2806 MacroAssembler _masm(&cbuf);
2807 2807 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2808 2808 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2809 2809 Register base_pointer_arg = reg_to_register_object($base$$reg);
2810 2810
2811 2811 Label loop;
2812 2812 __ mov(nof_bytes_arg, nof_bytes_tmp);
2813 2813
2814 2814 // Loop and clear, walking backwards through the array.
2815 2815 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2816 2816 __ bind(loop);
2817 2817 __ deccc(nof_bytes_tmp, 8);
2818 2818 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2819 2819 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2820 2820 // %%%% this mini-loop must not cross a cache boundary!
2821 2821 %}
2822 2822
2823 2823
2824 2824 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2825 2825 Label Ldone, Lloop;
2826 2826 MacroAssembler _masm(&cbuf);
2827 2827
2828 2828 Register str1_reg = reg_to_register_object($str1$$reg);
2829 2829 Register str2_reg = reg_to_register_object($str2$$reg);
2830 2830 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2831 2831 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2832 2832 Register result_reg = reg_to_register_object($result$$reg);
2833 2833
2834 2834 assert(result_reg != str1_reg &&
2835 2835 result_reg != str2_reg &&
2836 2836 result_reg != cnt1_reg &&
2837 2837 result_reg != cnt2_reg ,
2838 2838 "need different registers");
2839 2839
2840 2840 // Compute the minimum of the string lengths(str1_reg) and the
2841 2841 // difference of the string lengths (stack)
2842 2842
2843 2843 // See if the lengths are different, and calculate min in str1_reg.
2844 2844 // Stash diff in O7 in case we need it for a tie-breaker.
2845 2845 Label Lskip;
2846 2846 __ subcc(cnt1_reg, cnt2_reg, O7);
2847 2847 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2848 2848 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2849 2849 // cnt2 is shorter, so use its count:
2850 2850 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2851 2851 __ bind(Lskip);
2852 2852
2853 2853 // reallocate cnt1_reg, cnt2_reg, result_reg
2854 2854 // Note: limit_reg holds the string length pre-scaled by 2
2855 2855 Register limit_reg = cnt1_reg;
2856 2856 Register chr2_reg = cnt2_reg;
2857 2857 Register chr1_reg = result_reg;
2858 2858 // str{12} are the base pointers
2859 2859
2860 2860 // Is the minimum length zero?
2861 2861 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2862 2862 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2863 2863 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2864 2864
2865 2865 // Load first characters
2866 2866 __ lduh(str1_reg, 0, chr1_reg);
2867 2867 __ lduh(str2_reg, 0, chr2_reg);
2868 2868
2869 2869 // Compare first characters
2870 2870 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2871 2871 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2872 2872 assert(chr1_reg == result_reg, "result must be pre-placed");
2873 2873 __ delayed()->nop();
2874 2874
2875 2875 {
2876 2876 // Check after comparing first character to see if strings are equivalent
2877 2877 Label LSkip2;
2878 2878 // Check if the strings start at same location
2879 2879 __ cmp(str1_reg, str2_reg);
2880 2880 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2881 2881 __ delayed()->nop();
2882 2882
2883 2883 // Check if the length difference is zero (in O7)
2884 2884 __ cmp(G0, O7);
2885 2885 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2886 2886 __ delayed()->mov(G0, result_reg); // result is zero
2887 2887
2888 2888 // Strings might not be equal
2889 2889 __ bind(LSkip2);
2890 2890 }
2891 2891
2892 2892 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2893 2893 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2894 2894 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2895 2895
2896 2896 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2897 2897 __ add(str1_reg, limit_reg, str1_reg);
2898 2898 __ add(str2_reg, limit_reg, str2_reg);
2899 2899 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2900 2900
2901 2901 // Compare the rest of the characters
2902 2902 __ lduh(str1_reg, limit_reg, chr1_reg);
2903 2903 __ bind(Lloop);
2904 2904 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2905 2905 __ lduh(str2_reg, limit_reg, chr2_reg);
2906 2906 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2907 2907 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2908 2908 assert(chr1_reg == result_reg, "result must be pre-placed");
2909 2909 __ delayed()->inccc(limit_reg, sizeof(jchar));
2910 2910 // annul LDUH if branch is not taken to prevent access past end of string
2911 2911 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2912 2912 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2913 2913
2914 2914 // If strings are equal up to min length, return the length difference.
2915 2915 __ mov(O7, result_reg);
2916 2916
2917 2917 // Otherwise, return the difference between the first mismatched chars.
2918 2918 __ bind(Ldone);
2919 2919 %}
2920 2920
2921 2921 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2922 2922 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2923 2923 MacroAssembler _masm(&cbuf);
2924 2924
2925 2925 Register str1_reg = reg_to_register_object($str1$$reg);
2926 2926 Register str2_reg = reg_to_register_object($str2$$reg);
2927 2927 Register cnt_reg = reg_to_register_object($cnt$$reg);
2928 2928 Register tmp1_reg = O7;
2929 2929 Register result_reg = reg_to_register_object($result$$reg);
2930 2930
2931 2931 assert(result_reg != str1_reg &&
2932 2932 result_reg != str2_reg &&
2933 2933 result_reg != cnt_reg &&
2934 2934 result_reg != tmp1_reg ,
2935 2935 "need different registers");
2936 2936
2937 2937 __ cmp(str1_reg, str2_reg); //same char[] ?
2938 2938 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2939 2939 __ delayed()->add(G0, 1, result_reg);
2940 2940
2941 2941 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2942 2942 __ delayed()->add(G0, 1, result_reg); // count == 0
2943 2943
2944 2944 //rename registers
2945 2945 Register limit_reg = cnt_reg;
2946 2946 Register chr1_reg = result_reg;
2947 2947 Register chr2_reg = tmp1_reg;
2948 2948
2949 2949 //check for alignment and position the pointers to the ends
2950 2950 __ or3(str1_reg, str2_reg, chr1_reg);
2951 2951 __ andcc(chr1_reg, 0x3, chr1_reg);
2952 2952 // notZero means at least one not 4-byte aligned.
2953 2953 // We could optimize the case when both arrays are not aligned
2954 2954 // but it is not frequent case and it requires additional checks.
2955 2955 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2956 2956 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2957 2957
2958 2958 // Compare char[] arrays aligned to 4 bytes.
2959 2959 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2960 2960 chr1_reg, chr2_reg, Ldone);
2961 2961 __ ba(false,Ldone);
2962 2962 __ delayed()->add(G0, 1, result_reg);
2963 2963
2964 2964 // char by char compare
2965 2965 __ bind(Lchar);
2966 2966 __ add(str1_reg, limit_reg, str1_reg);
2967 2967 __ add(str2_reg, limit_reg, str2_reg);
2968 2968 __ neg(limit_reg); //negate count
2969 2969
2970 2970 __ lduh(str1_reg, limit_reg, chr1_reg);
2971 2971 // Lchar_loop
2972 2972 __ bind(Lchar_loop);
2973 2973 __ lduh(str2_reg, limit_reg, chr2_reg);
2974 2974 __ cmp(chr1_reg, chr2_reg);
2975 2975 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2976 2976 __ delayed()->mov(G0, result_reg); //not equal
2977 2977 __ inccc(limit_reg, sizeof(jchar));
2978 2978 // annul LDUH if branch is not taken to prevent access past end of string
2979 2979 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2980 2980 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2981 2981
2982 2982 __ add(G0, 1, result_reg); //equal
2983 2983
2984 2984 __ bind(Ldone);
2985 2985 %}
2986 2986
2987 2987 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2988 2988 Label Lvector, Ldone, Lloop;
2989 2989 MacroAssembler _masm(&cbuf);
2990 2990
2991 2991 Register ary1_reg = reg_to_register_object($ary1$$reg);
2992 2992 Register ary2_reg = reg_to_register_object($ary2$$reg);
2993 2993 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2994 2994 Register tmp2_reg = O7;
2995 2995 Register result_reg = reg_to_register_object($result$$reg);
2996 2996
2997 2997 int length_offset = arrayOopDesc::length_offset_in_bytes();
2998 2998 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
2999 2999
3000 3000 // return true if the same array
3001 3001 __ cmp(ary1_reg, ary2_reg);
3002 3002 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3003 3003 __ delayed()->add(G0, 1, result_reg); // equal
3004 3004
3005 3005 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3006 3006 __ delayed()->mov(G0, result_reg); // not equal
3007 3007
3008 3008 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3009 3009 __ delayed()->mov(G0, result_reg); // not equal
3010 3010
3011 3011 //load the lengths of arrays
3012 3012 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3013 3013 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3014 3014
3015 3015 // return false if the two arrays are not equal length
3016 3016 __ cmp(tmp1_reg, tmp2_reg);
3017 3017 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3018 3018 __ delayed()->mov(G0, result_reg); // not equal
3019 3019
3020 3020 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3021 3021 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3022 3022
3023 3023 // load array addresses
3024 3024 __ add(ary1_reg, base_offset, ary1_reg);
3025 3025 __ add(ary2_reg, base_offset, ary2_reg);
3026 3026
3027 3027 // renaming registers
3028 3028 Register chr1_reg = result_reg; // for characters in ary1
3029 3029 Register chr2_reg = tmp2_reg; // for characters in ary2
3030 3030 Register limit_reg = tmp1_reg; // length
3031 3031
3032 3032 // set byte count
3033 3033 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3034 3034
3035 3035 // Compare char[] arrays aligned to 4 bytes.
3036 3036 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3037 3037 chr1_reg, chr2_reg, Ldone);
3038 3038 __ add(G0, 1, result_reg); // equals
3039 3039
3040 3040 __ bind(Ldone);
3041 3041 %}
3042 3042
3043 3043 enc_class enc_rethrow() %{
3044 3044 cbuf.set_insts_mark();
3045 3045 Register temp_reg = G3;
3046 3046 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3047 3047 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3048 3048 MacroAssembler _masm(&cbuf);
3049 3049 #ifdef ASSERT
3050 3050 __ save_frame(0);
3051 3051 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3052 3052 __ sethi(last_rethrow_addrlit, L1);
3053 3053 Address addr(L1, last_rethrow_addrlit.low10());
3054 3054 __ get_pc(L2);
3055 3055 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3056 3056 __ st_ptr(L2, addr);
3057 3057 __ restore();
3058 3058 #endif
3059 3059 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3060 3060 __ delayed()->nop();
3061 3061 %}
3062 3062
3063 3063 enc_class emit_mem_nop() %{
3064 3064 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3065 3065 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3066 3066 %}
3067 3067
3068 3068 enc_class emit_fadd_nop() %{
3069 3069 // Generates the instruction FMOVS f31,f31
3070 3070 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3071 3071 %}
3072 3072
3073 3073 enc_class emit_br_nop() %{
3074 3074 // Generates the instruction BPN,PN .
3075 3075 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3076 3076 %}
3077 3077
3078 3078 enc_class enc_membar_acquire %{
3079 3079 MacroAssembler _masm(&cbuf);
3080 3080 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3081 3081 %}
3082 3082
3083 3083 enc_class enc_membar_release %{
3084 3084 MacroAssembler _masm(&cbuf);
3085 3085 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3086 3086 %}
3087 3087
3088 3088 enc_class enc_membar_volatile %{
3089 3089 MacroAssembler _masm(&cbuf);
3090 3090 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3091 3091 %}
3092 3092
3093 3093 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3094 3094 MacroAssembler _masm(&cbuf);
3095 3095 Register src_reg = reg_to_register_object($src$$reg);
3096 3096 Register dst_reg = reg_to_register_object($dst$$reg);
3097 3097 __ sllx(src_reg, 56, dst_reg);
3098 3098 __ srlx(dst_reg, 8, O7);
3099 3099 __ or3 (dst_reg, O7, dst_reg);
3100 3100 __ srlx(dst_reg, 16, O7);
3101 3101 __ or3 (dst_reg, O7, dst_reg);
3102 3102 __ srlx(dst_reg, 32, O7);
3103 3103 __ or3 (dst_reg, O7, dst_reg);
3104 3104 %}
3105 3105
3106 3106 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3107 3107 MacroAssembler _masm(&cbuf);
3108 3108 Register src_reg = reg_to_register_object($src$$reg);
3109 3109 Register dst_reg = reg_to_register_object($dst$$reg);
3110 3110 __ sll(src_reg, 24, dst_reg);
3111 3111 __ srl(dst_reg, 8, O7);
3112 3112 __ or3(dst_reg, O7, dst_reg);
3113 3113 __ srl(dst_reg, 16, O7);
3114 3114 __ or3(dst_reg, O7, dst_reg);
3115 3115 %}
3116 3116
3117 3117 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3118 3118 MacroAssembler _masm(&cbuf);
3119 3119 Register src_reg = reg_to_register_object($src$$reg);
3120 3120 Register dst_reg = reg_to_register_object($dst$$reg);
3121 3121 __ sllx(src_reg, 48, dst_reg);
3122 3122 __ srlx(dst_reg, 16, O7);
3123 3123 __ or3 (dst_reg, O7, dst_reg);
3124 3124 __ srlx(dst_reg, 32, O7);
3125 3125 __ or3 (dst_reg, O7, dst_reg);
3126 3126 %}
3127 3127
3128 3128 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3129 3129 MacroAssembler _masm(&cbuf);
3130 3130 Register src_reg = reg_to_register_object($src$$reg);
3131 3131 Register dst_reg = reg_to_register_object($dst$$reg);
3132 3132 __ sllx(src_reg, 32, dst_reg);
3133 3133 __ srlx(dst_reg, 32, O7);
3134 3134 __ or3 (dst_reg, O7, dst_reg);
3135 3135 %}
3136 3136
3137 3137 %}
3138 3138
3139 3139 //----------FRAME--------------------------------------------------------------
3140 3140 // Definition of frame structure and management information.
3141 3141 //
3142 3142 // S T A C K L A Y O U T Allocators stack-slot number
3143 3143 // | (to get allocators register number
3144 3144 // G Owned by | | v add VMRegImpl::stack0)
3145 3145 // r CALLER | |
3146 3146 // o | +--------+ pad to even-align allocators stack-slot
3147 3147 // w V | pad0 | numbers; owned by CALLER
3148 3148 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3149 3149 // h ^ | in | 5
3150 3150 // | | args | 4 Holes in incoming args owned by SELF
3151 3151 // | | | | 3
3152 3152 // | | +--------+
3153 3153 // V | | old out| Empty on Intel, window on Sparc
3154 3154 // | old |preserve| Must be even aligned.
3155 3155 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3156 3156 // | | in | 3 area for Intel ret address
3157 3157 // Owned by |preserve| Empty on Sparc.
3158 3158 // SELF +--------+
3159 3159 // | | pad2 | 2 pad to align old SP
3160 3160 // | +--------+ 1
3161 3161 // | | locks | 0
3162 3162 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3163 3163 // | | pad1 | 11 pad to align new SP
3164 3164 // | +--------+
3165 3165 // | | | 10
3166 3166 // | | spills | 9 spills
3167 3167 // V | | 8 (pad0 slot for callee)
3168 3168 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3169 3169 // ^ | out | 7
3170 3170 // | | args | 6 Holes in outgoing args owned by CALLEE
3171 3171 // Owned by +--------+
3172 3172 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3173 3173 // | new |preserve| Must be even-aligned.
3174 3174 // | SP-+--------+----> Matcher::_new_SP, even aligned
3175 3175 // | | |
3176 3176 //
3177 3177 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3178 3178 // known from SELF's arguments and the Java calling convention.
3179 3179 // Region 6-7 is determined per call site.
3180 3180 // Note 2: If the calling convention leaves holes in the incoming argument
3181 3181 // area, those holes are owned by SELF. Holes in the outgoing area
3182 3182 // are owned by the CALLEE. Holes should not be nessecary in the
3183 3183 // incoming area, as the Java calling convention is completely under
3184 3184 // the control of the AD file. Doubles can be sorted and packed to
3185 3185 // avoid holes. Holes in the outgoing arguments may be nessecary for
3186 3186 // varargs C calling conventions.
3187 3187 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3188 3188 // even aligned with pad0 as needed.
3189 3189 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3190 3190 // region 6-11 is even aligned; it may be padded out more so that
3191 3191 // the region from SP to FP meets the minimum stack alignment.
3192 3192
3193 3193 frame %{
3194 3194 // What direction does stack grow in (assumed to be same for native & Java)
3195 3195 stack_direction(TOWARDS_LOW);
3196 3196
3197 3197 // These two registers define part of the calling convention
3198 3198 // between compiled code and the interpreter.
3199 3199 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3200 3200 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3201 3201
3202 3202 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3203 3203 cisc_spilling_operand_name(indOffset);
3204 3204
3205 3205 // Number of stack slots consumed by a Monitor enter
3206 3206 #ifdef _LP64
3207 3207 sync_stack_slots(2);
3208 3208 #else
3209 3209 sync_stack_slots(1);
3210 3210 #endif
3211 3211
3212 3212 // Compiled code's Frame Pointer
3213 3213 frame_pointer(R_SP);
3214 3214
3215 3215 // Stack alignment requirement
3216 3216 stack_alignment(StackAlignmentInBytes);
3217 3217 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3218 3218 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3219 3219
3220 3220 // Number of stack slots between incoming argument block and the start of
3221 3221 // a new frame. The PROLOG must add this many slots to the stack. The
3222 3222 // EPILOG must remove this many slots.
3223 3223 in_preserve_stack_slots(0);
3224 3224
3225 3225 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3226 3226 // for calls to C. Supports the var-args backing area for register parms.
3227 3227 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3228 3228 #ifdef _LP64
3229 3229 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3230 3230 varargs_C_out_slots_killed(12);
3231 3231 #else
3232 3232 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3233 3233 varargs_C_out_slots_killed( 7);
3234 3234 #endif
3235 3235
3236 3236 // The after-PROLOG location of the return address. Location of
3237 3237 // return address specifies a type (REG or STACK) and a number
3238 3238 // representing the register number (i.e. - use a register name) or
3239 3239 // stack slot.
3240 3240 return_addr(REG R_I7); // Ret Addr is in register I7
3241 3241
3242 3242 // Body of function which returns an OptoRegs array locating
3243 3243 // arguments either in registers or in stack slots for calling
3244 3244 // java
3245 3245 calling_convention %{
3246 3246 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3247 3247
3248 3248 %}
3249 3249
3250 3250 // Body of function which returns an OptoRegs array locating
3251 3251 // arguments either in registers or in stack slots for callin
3252 3252 // C.
3253 3253 c_calling_convention %{
3254 3254 // This is obviously always outgoing
3255 3255 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3256 3256 %}
3257 3257
3258 3258 // Location of native (C/C++) and interpreter return values. This is specified to
3259 3259 // be the same as Java. In the 32-bit VM, long values are actually returned from
3260 3260 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3261 3261 // to and from the register pairs is done by the appropriate call and epilog
3262 3262 // opcodes. This simplifies the register allocator.
3263 3263 c_return_value %{
3264 3264 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3265 3265 #ifdef _LP64
3266 3266 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3267 3267 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3268 3268 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3269 3269 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3270 3270 #else // !_LP64
3271 3271 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3272 3272 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3273 3273 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3274 3274 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3275 3275 #endif
3276 3276 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3277 3277 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3278 3278 %}
3279 3279
3280 3280 // Location of compiled Java return values. Same as C
3281 3281 return_value %{
3282 3282 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3283 3283 #ifdef _LP64
3284 3284 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3285 3285 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3286 3286 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3287 3287 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3288 3288 #else // !_LP64
3289 3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3290 3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3291 3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3292 3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3293 3293 #endif
3294 3294 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3295 3295 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3296 3296 %}
3297 3297
3298 3298 %}
3299 3299
3300 3300
3301 3301 //----------ATTRIBUTES---------------------------------------------------------
3302 3302 //----------Operand Attributes-------------------------------------------------
3303 3303 op_attrib op_cost(1); // Required cost attribute
3304 3304
3305 3305 //----------Instruction Attributes---------------------------------------------
3306 3306 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3307 3307 ins_attrib ins_size(32); // Required size attribute (in bits)
3308 3308 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3309 3309 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3310 3310 // non-matching short branch variant of some
3311 3311 // long branch?
3312 3312
3313 3313 //----------OPERANDS-----------------------------------------------------------
3314 3314 // Operand definitions must precede instruction definitions for correct parsing
3315 3315 // in the ADLC because operands constitute user defined types which are used in
3316 3316 // instruction definitions.
3317 3317
3318 3318 //----------Simple Operands----------------------------------------------------
3319 3319 // Immediate Operands
3320 3320 // Integer Immediate: 32-bit
3321 3321 operand immI() %{
3322 3322 match(ConI);
3323 3323
3324 3324 op_cost(0);
3325 3325 // formats are generated automatically for constants and base registers
3326 3326 format %{ %}
3327 3327 interface(CONST_INTER);
3328 3328 %}
3329 3329
3330 3330 // Integer Immediate: 8-bit
3331 3331 operand immI8() %{
3332 3332 predicate(Assembler::is_simm(n->get_int(), 8));
3333 3333 match(ConI);
3334 3334 op_cost(0);
3335 3335 format %{ %}
3336 3336 interface(CONST_INTER);
3337 3337 %}
3338 3338
3339 3339 // Integer Immediate: 13-bit
3340 3340 operand immI13() %{
3341 3341 predicate(Assembler::is_simm13(n->get_int()));
3342 3342 match(ConI);
3343 3343 op_cost(0);
3344 3344
3345 3345 format %{ %}
3346 3346 interface(CONST_INTER);
3347 3347 %}
3348 3348
3349 3349 // Integer Immediate: 13-bit minus 7
3350 3350 operand immI13m7() %{
3351 3351 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3352 3352 match(ConI);
3353 3353 op_cost(0);
3354 3354
3355 3355 format %{ %}
3356 3356 interface(CONST_INTER);
3357 3357 %}
3358 3358
3359 3359 // Integer Immediate: 16-bit
3360 3360 operand immI16() %{
3361 3361 predicate(Assembler::is_simm(n->get_int(), 16));
3362 3362 match(ConI);
3363 3363 op_cost(0);
3364 3364 format %{ %}
3365 3365 interface(CONST_INTER);
3366 3366 %}
3367 3367
3368 3368 // Unsigned (positive) Integer Immediate: 13-bit
3369 3369 operand immU13() %{
3370 3370 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3371 3371 match(ConI);
3372 3372 op_cost(0);
3373 3373
3374 3374 format %{ %}
3375 3375 interface(CONST_INTER);
3376 3376 %}
3377 3377
3378 3378 // Integer Immediate: 6-bit
3379 3379 operand immU6() %{
3380 3380 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3381 3381 match(ConI);
3382 3382 op_cost(0);
3383 3383 format %{ %}
3384 3384 interface(CONST_INTER);
3385 3385 %}
3386 3386
3387 3387 // Integer Immediate: 11-bit
3388 3388 operand immI11() %{
3389 3389 predicate(Assembler::is_simm(n->get_int(),11));
3390 3390 match(ConI);
3391 3391 op_cost(0);
3392 3392 format %{ %}
3393 3393 interface(CONST_INTER);
3394 3394 %}
3395 3395
3396 3396 // Integer Immediate: 0-bit
3397 3397 operand immI0() %{
3398 3398 predicate(n->get_int() == 0);
3399 3399 match(ConI);
3400 3400 op_cost(0);
3401 3401
3402 3402 format %{ %}
3403 3403 interface(CONST_INTER);
3404 3404 %}
3405 3405
3406 3406 // Integer Immediate: the value 10
3407 3407 operand immI10() %{
3408 3408 predicate(n->get_int() == 10);
3409 3409 match(ConI);
3410 3410 op_cost(0);
3411 3411
3412 3412 format %{ %}
3413 3413 interface(CONST_INTER);
3414 3414 %}
3415 3415
3416 3416 // Integer Immediate: the values 0-31
3417 3417 operand immU5() %{
3418 3418 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3419 3419 match(ConI);
3420 3420 op_cost(0);
3421 3421
3422 3422 format %{ %}
3423 3423 interface(CONST_INTER);
3424 3424 %}
3425 3425
3426 3426 // Integer Immediate: the values 1-31
3427 3427 operand immI_1_31() %{
3428 3428 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3429 3429 match(ConI);
3430 3430 op_cost(0);
3431 3431
3432 3432 format %{ %}
3433 3433 interface(CONST_INTER);
3434 3434 %}
3435 3435
3436 3436 // Integer Immediate: the values 32-63
3437 3437 operand immI_32_63() %{
3438 3438 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3439 3439 match(ConI);
3440 3440 op_cost(0);
3441 3441
3442 3442 format %{ %}
3443 3443 interface(CONST_INTER);
3444 3444 %}
3445 3445
3446 3446 // Immediates for special shifts (sign extend)
3447 3447
3448 3448 // Integer Immediate: the value 16
3449 3449 operand immI_16() %{
3450 3450 predicate(n->get_int() == 16);
3451 3451 match(ConI);
3452 3452 op_cost(0);
3453 3453
3454 3454 format %{ %}
3455 3455 interface(CONST_INTER);
3456 3456 %}
3457 3457
3458 3458 // Integer Immediate: the value 24
3459 3459 operand immI_24() %{
3460 3460 predicate(n->get_int() == 24);
3461 3461 match(ConI);
3462 3462 op_cost(0);
3463 3463
3464 3464 format %{ %}
3465 3465 interface(CONST_INTER);
3466 3466 %}
3467 3467
3468 3468 // Integer Immediate: the value 255
3469 3469 operand immI_255() %{
3470 3470 predicate( n->get_int() == 255 );
3471 3471 match(ConI);
3472 3472 op_cost(0);
3473 3473
3474 3474 format %{ %}
3475 3475 interface(CONST_INTER);
3476 3476 %}
3477 3477
3478 3478 // Integer Immediate: the value 65535
3479 3479 operand immI_65535() %{
3480 3480 predicate(n->get_int() == 65535);
3481 3481 match(ConI);
3482 3482 op_cost(0);
3483 3483
3484 3484 format %{ %}
3485 3485 interface(CONST_INTER);
3486 3486 %}
3487 3487
3488 3488 // Long Immediate: the value FF
3489 3489 operand immL_FF() %{
3490 3490 predicate( n->get_long() == 0xFFL );
3491 3491 match(ConL);
3492 3492 op_cost(0);
3493 3493
3494 3494 format %{ %}
3495 3495 interface(CONST_INTER);
3496 3496 %}
3497 3497
3498 3498 // Long Immediate: the value FFFF
3499 3499 operand immL_FFFF() %{
3500 3500 predicate( n->get_long() == 0xFFFFL );
3501 3501 match(ConL);
3502 3502 op_cost(0);
3503 3503
3504 3504 format %{ %}
3505 3505 interface(CONST_INTER);
3506 3506 %}
3507 3507
3508 3508 // Pointer Immediate: 32 or 64-bit
3509 3509 operand immP() %{
3510 3510 match(ConP);
3511 3511
3512 3512 op_cost(5);
3513 3513 // formats are generated automatically for constants and base registers
3514 3514 format %{ %}
3515 3515 interface(CONST_INTER);
3516 3516 %}
3517 3517
3518 3518 operand immP13() %{
3519 3519 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3520 3520 match(ConP);
3521 3521 op_cost(0);
3522 3522
3523 3523 format %{ %}
3524 3524 interface(CONST_INTER);
3525 3525 %}
3526 3526
3527 3527 operand immP0() %{
3528 3528 predicate(n->get_ptr() == 0);
3529 3529 match(ConP);
3530 3530 op_cost(0);
3531 3531
3532 3532 format %{ %}
3533 3533 interface(CONST_INTER);
3534 3534 %}
3535 3535
3536 3536 operand immP_poll() %{
3537 3537 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3538 3538 match(ConP);
3539 3539
3540 3540 // formats are generated automatically for constants and base registers
3541 3541 format %{ %}
3542 3542 interface(CONST_INTER);
3543 3543 %}
3544 3544
3545 3545 // Pointer Immediate
3546 3546 operand immN()
3547 3547 %{
3548 3548 match(ConN);
3549 3549
3550 3550 op_cost(10);
3551 3551 format %{ %}
3552 3552 interface(CONST_INTER);
3553 3553 %}
3554 3554
3555 3555 // NULL Pointer Immediate
3556 3556 operand immN0()
3557 3557 %{
3558 3558 predicate(n->get_narrowcon() == 0);
3559 3559 match(ConN);
3560 3560
3561 3561 op_cost(0);
3562 3562 format %{ %}
3563 3563 interface(CONST_INTER);
3564 3564 %}
3565 3565
3566 3566 operand immL() %{
3567 3567 match(ConL);
3568 3568 op_cost(40);
3569 3569 // formats are generated automatically for constants and base registers
3570 3570 format %{ %}
3571 3571 interface(CONST_INTER);
3572 3572 %}
3573 3573
3574 3574 operand immL0() %{
3575 3575 predicate(n->get_long() == 0L);
3576 3576 match(ConL);
3577 3577 op_cost(0);
3578 3578 // formats are generated automatically for constants and base registers
3579 3579 format %{ %}
3580 3580 interface(CONST_INTER);
3581 3581 %}
3582 3582
3583 3583 // Long Immediate: 13-bit
3584 3584 operand immL13() %{
3585 3585 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3586 3586 match(ConL);
3587 3587 op_cost(0);
3588 3588
3589 3589 format %{ %}
3590 3590 interface(CONST_INTER);
3591 3591 %}
3592 3592
3593 3593 // Long Immediate: 13-bit minus 7
3594 3594 operand immL13m7() %{
3595 3595 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3596 3596 match(ConL);
3597 3597 op_cost(0);
3598 3598
3599 3599 format %{ %}
3600 3600 interface(CONST_INTER);
3601 3601 %}
3602 3602
3603 3603 // Long Immediate: low 32-bit mask
3604 3604 operand immL_32bits() %{
3605 3605 predicate(n->get_long() == 0xFFFFFFFFL);
3606 3606 match(ConL);
3607 3607 op_cost(0);
3608 3608
3609 3609 format %{ %}
3610 3610 interface(CONST_INTER);
3611 3611 %}
3612 3612
3613 3613 // Double Immediate
3614 3614 operand immD() %{
3615 3615 match(ConD);
3616 3616
3617 3617 op_cost(40);
3618 3618 format %{ %}
3619 3619 interface(CONST_INTER);
3620 3620 %}
3621 3621
3622 3622 operand immD0() %{
3623 3623 #ifdef _LP64
3624 3624 // on 64-bit architectures this comparision is faster
3625 3625 predicate(jlong_cast(n->getd()) == 0);
3626 3626 #else
3627 3627 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3628 3628 #endif
3629 3629 match(ConD);
3630 3630
3631 3631 op_cost(0);
3632 3632 format %{ %}
3633 3633 interface(CONST_INTER);
3634 3634 %}
3635 3635
3636 3636 // Float Immediate
3637 3637 operand immF() %{
3638 3638 match(ConF);
3639 3639
3640 3640 op_cost(20);
3641 3641 format %{ %}
3642 3642 interface(CONST_INTER);
3643 3643 %}
3644 3644
3645 3645 // Float Immediate: 0
3646 3646 operand immF0() %{
3647 3647 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3648 3648 match(ConF);
3649 3649
3650 3650 op_cost(0);
3651 3651 format %{ %}
3652 3652 interface(CONST_INTER);
3653 3653 %}
3654 3654
3655 3655 // Integer Register Operands
3656 3656 // Integer Register
3657 3657 operand iRegI() %{
3658 3658 constraint(ALLOC_IN_RC(int_reg));
3659 3659 match(RegI);
3660 3660
3661 3661 match(notemp_iRegI);
3662 3662 match(g1RegI);
3663 3663 match(o0RegI);
3664 3664 match(iRegIsafe);
3665 3665
3666 3666 format %{ %}
3667 3667 interface(REG_INTER);
3668 3668 %}
3669 3669
3670 3670 operand notemp_iRegI() %{
3671 3671 constraint(ALLOC_IN_RC(notemp_int_reg));
3672 3672 match(RegI);
3673 3673
3674 3674 match(o0RegI);
3675 3675
3676 3676 format %{ %}
3677 3677 interface(REG_INTER);
3678 3678 %}
3679 3679
3680 3680 operand o0RegI() %{
3681 3681 constraint(ALLOC_IN_RC(o0_regI));
3682 3682 match(iRegI);
3683 3683
3684 3684 format %{ %}
3685 3685 interface(REG_INTER);
3686 3686 %}
3687 3687
3688 3688 // Pointer Register
3689 3689 operand iRegP() %{
3690 3690 constraint(ALLOC_IN_RC(ptr_reg));
3691 3691 match(RegP);
3692 3692
3693 3693 match(lock_ptr_RegP);
3694 3694 match(g1RegP);
3695 3695 match(g2RegP);
3696 3696 match(g3RegP);
3697 3697 match(g4RegP);
3698 3698 match(i0RegP);
3699 3699 match(o0RegP);
3700 3700 match(o1RegP);
3701 3701 match(l7RegP);
3702 3702
3703 3703 format %{ %}
3704 3704 interface(REG_INTER);
3705 3705 %}
3706 3706
3707 3707 operand sp_ptr_RegP() %{
3708 3708 constraint(ALLOC_IN_RC(sp_ptr_reg));
3709 3709 match(RegP);
3710 3710 match(iRegP);
3711 3711
3712 3712 format %{ %}
3713 3713 interface(REG_INTER);
3714 3714 %}
3715 3715
3716 3716 operand lock_ptr_RegP() %{
3717 3717 constraint(ALLOC_IN_RC(lock_ptr_reg));
3718 3718 match(RegP);
3719 3719 match(i0RegP);
3720 3720 match(o0RegP);
3721 3721 match(o1RegP);
3722 3722 match(l7RegP);
3723 3723
3724 3724 format %{ %}
3725 3725 interface(REG_INTER);
3726 3726 %}
3727 3727
3728 3728 operand g1RegP() %{
3729 3729 constraint(ALLOC_IN_RC(g1_regP));
3730 3730 match(iRegP);
3731 3731
3732 3732 format %{ %}
3733 3733 interface(REG_INTER);
3734 3734 %}
3735 3735
3736 3736 operand g2RegP() %{
3737 3737 constraint(ALLOC_IN_RC(g2_regP));
3738 3738 match(iRegP);
3739 3739
3740 3740 format %{ %}
3741 3741 interface(REG_INTER);
3742 3742 %}
3743 3743
3744 3744 operand g3RegP() %{
3745 3745 constraint(ALLOC_IN_RC(g3_regP));
3746 3746 match(iRegP);
3747 3747
3748 3748 format %{ %}
3749 3749 interface(REG_INTER);
3750 3750 %}
3751 3751
3752 3752 operand g1RegI() %{
3753 3753 constraint(ALLOC_IN_RC(g1_regI));
3754 3754 match(iRegI);
3755 3755
3756 3756 format %{ %}
3757 3757 interface(REG_INTER);
3758 3758 %}
3759 3759
3760 3760 operand g3RegI() %{
3761 3761 constraint(ALLOC_IN_RC(g3_regI));
3762 3762 match(iRegI);
3763 3763
3764 3764 format %{ %}
3765 3765 interface(REG_INTER);
3766 3766 %}
3767 3767
3768 3768 operand g4RegI() %{
3769 3769 constraint(ALLOC_IN_RC(g4_regI));
3770 3770 match(iRegI);
3771 3771
3772 3772 format %{ %}
3773 3773 interface(REG_INTER);
3774 3774 %}
3775 3775
3776 3776 operand g4RegP() %{
3777 3777 constraint(ALLOC_IN_RC(g4_regP));
3778 3778 match(iRegP);
3779 3779
3780 3780 format %{ %}
3781 3781 interface(REG_INTER);
3782 3782 %}
3783 3783
3784 3784 operand i0RegP() %{
3785 3785 constraint(ALLOC_IN_RC(i0_regP));
3786 3786 match(iRegP);
3787 3787
3788 3788 format %{ %}
3789 3789 interface(REG_INTER);
3790 3790 %}
3791 3791
3792 3792 operand o0RegP() %{
3793 3793 constraint(ALLOC_IN_RC(o0_regP));
3794 3794 match(iRegP);
3795 3795
3796 3796 format %{ %}
3797 3797 interface(REG_INTER);
3798 3798 %}
3799 3799
3800 3800 operand o1RegP() %{
3801 3801 constraint(ALLOC_IN_RC(o1_regP));
3802 3802 match(iRegP);
3803 3803
3804 3804 format %{ %}
3805 3805 interface(REG_INTER);
3806 3806 %}
3807 3807
3808 3808 operand o2RegP() %{
3809 3809 constraint(ALLOC_IN_RC(o2_regP));
3810 3810 match(iRegP);
3811 3811
3812 3812 format %{ %}
3813 3813 interface(REG_INTER);
3814 3814 %}
3815 3815
3816 3816 operand o7RegP() %{
3817 3817 constraint(ALLOC_IN_RC(o7_regP));
3818 3818 match(iRegP);
3819 3819
3820 3820 format %{ %}
3821 3821 interface(REG_INTER);
3822 3822 %}
3823 3823
3824 3824 operand l7RegP() %{
3825 3825 constraint(ALLOC_IN_RC(l7_regP));
3826 3826 match(iRegP);
3827 3827
3828 3828 format %{ %}
3829 3829 interface(REG_INTER);
3830 3830 %}
3831 3831
3832 3832 operand o7RegI() %{
3833 3833 constraint(ALLOC_IN_RC(o7_regI));
3834 3834 match(iRegI);
3835 3835
3836 3836 format %{ %}
3837 3837 interface(REG_INTER);
3838 3838 %}
3839 3839
3840 3840 operand iRegN() %{
3841 3841 constraint(ALLOC_IN_RC(int_reg));
3842 3842 match(RegN);
3843 3843
3844 3844 format %{ %}
3845 3845 interface(REG_INTER);
3846 3846 %}
3847 3847
3848 3848 // Long Register
3849 3849 operand iRegL() %{
3850 3850 constraint(ALLOC_IN_RC(long_reg));
3851 3851 match(RegL);
3852 3852
3853 3853 format %{ %}
3854 3854 interface(REG_INTER);
3855 3855 %}
3856 3856
3857 3857 operand o2RegL() %{
3858 3858 constraint(ALLOC_IN_RC(o2_regL));
3859 3859 match(iRegL);
3860 3860
3861 3861 format %{ %}
3862 3862 interface(REG_INTER);
3863 3863 %}
3864 3864
3865 3865 operand o7RegL() %{
3866 3866 constraint(ALLOC_IN_RC(o7_regL));
3867 3867 match(iRegL);
3868 3868
3869 3869 format %{ %}
3870 3870 interface(REG_INTER);
3871 3871 %}
3872 3872
3873 3873 operand g1RegL() %{
3874 3874 constraint(ALLOC_IN_RC(g1_regL));
3875 3875 match(iRegL);
3876 3876
3877 3877 format %{ %}
3878 3878 interface(REG_INTER);
3879 3879 %}
3880 3880
3881 3881 operand g3RegL() %{
3882 3882 constraint(ALLOC_IN_RC(g3_regL));
3883 3883 match(iRegL);
3884 3884
3885 3885 format %{ %}
3886 3886 interface(REG_INTER);
3887 3887 %}
3888 3888
3889 3889 // Int Register safe
3890 3890 // This is 64bit safe
3891 3891 operand iRegIsafe() %{
3892 3892 constraint(ALLOC_IN_RC(long_reg));
3893 3893
3894 3894 match(iRegI);
3895 3895
3896 3896 format %{ %}
3897 3897 interface(REG_INTER);
3898 3898 %}
3899 3899
3900 3900 // Condition Code Flag Register
3901 3901 operand flagsReg() %{
3902 3902 constraint(ALLOC_IN_RC(int_flags));
3903 3903 match(RegFlags);
3904 3904
3905 3905 format %{ "ccr" %} // both ICC and XCC
3906 3906 interface(REG_INTER);
3907 3907 %}
3908 3908
3909 3909 // Condition Code Register, unsigned comparisons.
3910 3910 operand flagsRegU() %{
3911 3911 constraint(ALLOC_IN_RC(int_flags));
3912 3912 match(RegFlags);
3913 3913
3914 3914 format %{ "icc_U" %}
3915 3915 interface(REG_INTER);
3916 3916 %}
3917 3917
3918 3918 // Condition Code Register, pointer comparisons.
3919 3919 operand flagsRegP() %{
3920 3920 constraint(ALLOC_IN_RC(int_flags));
3921 3921 match(RegFlags);
3922 3922
3923 3923 #ifdef _LP64
3924 3924 format %{ "xcc_P" %}
3925 3925 #else
3926 3926 format %{ "icc_P" %}
3927 3927 #endif
3928 3928 interface(REG_INTER);
3929 3929 %}
3930 3930
3931 3931 // Condition Code Register, long comparisons.
3932 3932 operand flagsRegL() %{
3933 3933 constraint(ALLOC_IN_RC(int_flags));
3934 3934 match(RegFlags);
3935 3935
3936 3936 format %{ "xcc_L" %}
3937 3937 interface(REG_INTER);
3938 3938 %}
3939 3939
3940 3940 // Condition Code Register, floating comparisons, unordered same as "less".
3941 3941 operand flagsRegF() %{
3942 3942 constraint(ALLOC_IN_RC(float_flags));
3943 3943 match(RegFlags);
3944 3944 match(flagsRegF0);
3945 3945
3946 3946 format %{ %}
3947 3947 interface(REG_INTER);
3948 3948 %}
3949 3949
3950 3950 operand flagsRegF0() %{
3951 3951 constraint(ALLOC_IN_RC(float_flag0));
3952 3952 match(RegFlags);
3953 3953
3954 3954 format %{ %}
3955 3955 interface(REG_INTER);
3956 3956 %}
3957 3957
3958 3958
3959 3959 // Condition Code Flag Register used by long compare
3960 3960 operand flagsReg_long_LTGE() %{
3961 3961 constraint(ALLOC_IN_RC(int_flags));
3962 3962 match(RegFlags);
3963 3963 format %{ "icc_LTGE" %}
3964 3964 interface(REG_INTER);
3965 3965 %}
3966 3966 operand flagsReg_long_EQNE() %{
3967 3967 constraint(ALLOC_IN_RC(int_flags));
3968 3968 match(RegFlags);
3969 3969 format %{ "icc_EQNE" %}
3970 3970 interface(REG_INTER);
3971 3971 %}
3972 3972 operand flagsReg_long_LEGT() %{
3973 3973 constraint(ALLOC_IN_RC(int_flags));
3974 3974 match(RegFlags);
3975 3975 format %{ "icc_LEGT" %}
3976 3976 interface(REG_INTER);
3977 3977 %}
3978 3978
3979 3979
3980 3980 operand regD() %{
3981 3981 constraint(ALLOC_IN_RC(dflt_reg));
3982 3982 match(RegD);
3983 3983
3984 3984 match(regD_low);
3985 3985
3986 3986 format %{ %}
3987 3987 interface(REG_INTER);
3988 3988 %}
3989 3989
3990 3990 operand regF() %{
3991 3991 constraint(ALLOC_IN_RC(sflt_reg));
3992 3992 match(RegF);
3993 3993
3994 3994 format %{ %}
3995 3995 interface(REG_INTER);
3996 3996 %}
3997 3997
3998 3998 operand regD_low() %{
3999 3999 constraint(ALLOC_IN_RC(dflt_low_reg));
4000 4000 match(regD);
4001 4001
4002 4002 format %{ %}
4003 4003 interface(REG_INTER);
4004 4004 %}
4005 4005
4006 4006 // Special Registers
4007 4007
4008 4008 // Method Register
4009 4009 operand inline_cache_regP(iRegP reg) %{
4010 4010 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4011 4011 match(reg);
4012 4012 format %{ %}
4013 4013 interface(REG_INTER);
4014 4014 %}
4015 4015
4016 4016 operand interpreter_method_oop_regP(iRegP reg) %{
4017 4017 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4018 4018 match(reg);
4019 4019 format %{ %}
4020 4020 interface(REG_INTER);
4021 4021 %}
4022 4022
4023 4023
4024 4024 //----------Complex Operands---------------------------------------------------
4025 4025 // Indirect Memory Reference
4026 4026 operand indirect(sp_ptr_RegP reg) %{
4027 4027 constraint(ALLOC_IN_RC(sp_ptr_reg));
4028 4028 match(reg);
4029 4029
4030 4030 op_cost(100);
4031 4031 format %{ "[$reg]" %}
4032 4032 interface(MEMORY_INTER) %{
4033 4033 base($reg);
4034 4034 index(0x0);
4035 4035 scale(0x0);
4036 4036 disp(0x0);
4037 4037 %}
4038 4038 %}
4039 4039
4040 4040 // Indirect with simm13 Offset
4041 4041 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4042 4042 constraint(ALLOC_IN_RC(sp_ptr_reg));
4043 4043 match(AddP reg offset);
4044 4044
4045 4045 op_cost(100);
4046 4046 format %{ "[$reg + $offset]" %}
4047 4047 interface(MEMORY_INTER) %{
4048 4048 base($reg);
4049 4049 index(0x0);
4050 4050 scale(0x0);
4051 4051 disp($offset);
4052 4052 %}
4053 4053 %}
4054 4054
4055 4055 // Indirect with simm13 Offset minus 7
4056 4056 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4057 4057 constraint(ALLOC_IN_RC(sp_ptr_reg));
4058 4058 match(AddP reg offset);
4059 4059
4060 4060 op_cost(100);
4061 4061 format %{ "[$reg + $offset]" %}
4062 4062 interface(MEMORY_INTER) %{
4063 4063 base($reg);
4064 4064 index(0x0);
4065 4065 scale(0x0);
4066 4066 disp($offset);
4067 4067 %}
4068 4068 %}
4069 4069
4070 4070 // Note: Intel has a swapped version also, like this:
4071 4071 //operand indOffsetX(iRegI reg, immP offset) %{
4072 4072 // constraint(ALLOC_IN_RC(int_reg));
4073 4073 // match(AddP offset reg);
4074 4074 //
4075 4075 // op_cost(100);
4076 4076 // format %{ "[$reg + $offset]" %}
4077 4077 // interface(MEMORY_INTER) %{
4078 4078 // base($reg);
4079 4079 // index(0x0);
4080 4080 // scale(0x0);
4081 4081 // disp($offset);
4082 4082 // %}
4083 4083 //%}
4084 4084 //// However, it doesn't make sense for SPARC, since
4085 4085 // we have no particularly good way to embed oops in
4086 4086 // single instructions.
4087 4087
4088 4088 // Indirect with Register Index
4089 4089 operand indIndex(iRegP addr, iRegX index) %{
4090 4090 constraint(ALLOC_IN_RC(ptr_reg));
4091 4091 match(AddP addr index);
4092 4092
4093 4093 op_cost(100);
4094 4094 format %{ "[$addr + $index]" %}
4095 4095 interface(MEMORY_INTER) %{
4096 4096 base($addr);
4097 4097 index($index);
4098 4098 scale(0x0);
4099 4099 disp(0x0);
4100 4100 %}
4101 4101 %}
4102 4102
4103 4103 //----------Special Memory Operands--------------------------------------------
4104 4104 // Stack Slot Operand - This operand is used for loading and storing temporary
4105 4105 // values on the stack where a match requires a value to
4106 4106 // flow through memory.
4107 4107 operand stackSlotI(sRegI reg) %{
4108 4108 constraint(ALLOC_IN_RC(stack_slots));
4109 4109 op_cost(100);
4110 4110 //match(RegI);
4111 4111 format %{ "[$reg]" %}
4112 4112 interface(MEMORY_INTER) %{
4113 4113 base(0xE); // R_SP
4114 4114 index(0x0);
4115 4115 scale(0x0);
4116 4116 disp($reg); // Stack Offset
4117 4117 %}
4118 4118 %}
4119 4119
4120 4120 operand stackSlotP(sRegP reg) %{
4121 4121 constraint(ALLOC_IN_RC(stack_slots));
4122 4122 op_cost(100);
4123 4123 //match(RegP);
4124 4124 format %{ "[$reg]" %}
4125 4125 interface(MEMORY_INTER) %{
4126 4126 base(0xE); // R_SP
4127 4127 index(0x0);
4128 4128 scale(0x0);
4129 4129 disp($reg); // Stack Offset
4130 4130 %}
4131 4131 %}
4132 4132
4133 4133 operand stackSlotF(sRegF reg) %{
4134 4134 constraint(ALLOC_IN_RC(stack_slots));
4135 4135 op_cost(100);
4136 4136 //match(RegF);
4137 4137 format %{ "[$reg]" %}
4138 4138 interface(MEMORY_INTER) %{
4139 4139 base(0xE); // R_SP
4140 4140 index(0x0);
4141 4141 scale(0x0);
4142 4142 disp($reg); // Stack Offset
4143 4143 %}
4144 4144 %}
4145 4145 operand stackSlotD(sRegD reg) %{
4146 4146 constraint(ALLOC_IN_RC(stack_slots));
4147 4147 op_cost(100);
4148 4148 //match(RegD);
4149 4149 format %{ "[$reg]" %}
4150 4150 interface(MEMORY_INTER) %{
4151 4151 base(0xE); // R_SP
4152 4152 index(0x0);
4153 4153 scale(0x0);
4154 4154 disp($reg); // Stack Offset
4155 4155 %}
4156 4156 %}
4157 4157 operand stackSlotL(sRegL reg) %{
4158 4158 constraint(ALLOC_IN_RC(stack_slots));
4159 4159 op_cost(100);
4160 4160 //match(RegL);
4161 4161 format %{ "[$reg]" %}
4162 4162 interface(MEMORY_INTER) %{
4163 4163 base(0xE); // R_SP
4164 4164 index(0x0);
4165 4165 scale(0x0);
4166 4166 disp($reg); // Stack Offset
4167 4167 %}
4168 4168 %}
4169 4169
4170 4170 // Operands for expressing Control Flow
4171 4171 // NOTE: Label is a predefined operand which should not be redefined in
4172 4172 // the AD file. It is generically handled within the ADLC.
4173 4173
4174 4174 //----------Conditional Branch Operands----------------------------------------
4175 4175 // Comparison Op - This is the operation of the comparison, and is limited to
4176 4176 // the following set of codes:
4177 4177 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4178 4178 //
4179 4179 // Other attributes of the comparison, such as unsignedness, are specified
4180 4180 // by the comparison instruction that sets a condition code flags register.
4181 4181 // That result is represented by a flags operand whose subtype is appropriate
4182 4182 // to the unsignedness (etc.) of the comparison.
4183 4183 //
4184 4184 // Later, the instruction which matches both the Comparison Op (a Bool) and
4185 4185 // the flags (produced by the Cmp) specifies the coding of the comparison op
4186 4186 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4187 4187
4188 4188 operand cmpOp() %{
4189 4189 match(Bool);
4190 4190
4191 4191 format %{ "" %}
4192 4192 interface(COND_INTER) %{
4193 4193 equal(0x1);
4194 4194 not_equal(0x9);
4195 4195 less(0x3);
4196 4196 greater_equal(0xB);
4197 4197 less_equal(0x2);
4198 4198 greater(0xA);
4199 4199 %}
4200 4200 %}
4201 4201
4202 4202 // Comparison Op, unsigned
4203 4203 operand cmpOpU() %{
4204 4204 match(Bool);
4205 4205
4206 4206 format %{ "u" %}
4207 4207 interface(COND_INTER) %{
4208 4208 equal(0x1);
4209 4209 not_equal(0x9);
4210 4210 less(0x5);
4211 4211 greater_equal(0xD);
4212 4212 less_equal(0x4);
4213 4213 greater(0xC);
4214 4214 %}
4215 4215 %}
4216 4216
4217 4217 // Comparison Op, pointer (same as unsigned)
4218 4218 operand cmpOpP() %{
4219 4219 match(Bool);
4220 4220
4221 4221 format %{ "p" %}
4222 4222 interface(COND_INTER) %{
4223 4223 equal(0x1);
4224 4224 not_equal(0x9);
4225 4225 less(0x5);
4226 4226 greater_equal(0xD);
4227 4227 less_equal(0x4);
4228 4228 greater(0xC);
4229 4229 %}
4230 4230 %}
4231 4231
4232 4232 // Comparison Op, branch-register encoding
4233 4233 operand cmpOp_reg() %{
4234 4234 match(Bool);
4235 4235
4236 4236 format %{ "" %}
4237 4237 interface(COND_INTER) %{
4238 4238 equal (0x1);
4239 4239 not_equal (0x5);
4240 4240 less (0x3);
4241 4241 greater_equal(0x7);
4242 4242 less_equal (0x2);
4243 4243 greater (0x6);
4244 4244 %}
4245 4245 %}
4246 4246
4247 4247 // Comparison Code, floating, unordered same as less
4248 4248 operand cmpOpF() %{
4249 4249 match(Bool);
4250 4250
4251 4251 format %{ "fl" %}
4252 4252 interface(COND_INTER) %{
4253 4253 equal(0x9);
4254 4254 not_equal(0x1);
4255 4255 less(0x3);
4256 4256 greater_equal(0xB);
4257 4257 less_equal(0xE);
4258 4258 greater(0x6);
4259 4259 %}
4260 4260 %}
4261 4261
4262 4262 // Used by long compare
4263 4263 operand cmpOp_commute() %{
4264 4264 match(Bool);
4265 4265
4266 4266 format %{ "" %}
4267 4267 interface(COND_INTER) %{
4268 4268 equal(0x1);
4269 4269 not_equal(0x9);
4270 4270 less(0xA);
4271 4271 greater_equal(0x2);
4272 4272 less_equal(0xB);
4273 4273 greater(0x3);
4274 4274 %}
4275 4275 %}
4276 4276
4277 4277 //----------OPERAND CLASSES----------------------------------------------------
4278 4278 // Operand Classes are groups of operands that are used to simplify
4279 4279 // instruction definitions by not requiring the AD writer to specify separate
4280 4280 // instructions for every form of operand when the instruction accepts
4281 4281 // multiple operand types with the same basic encoding and format. The classic
4282 4282 // case of this is memory operands.
4283 4283 opclass memory( indirect, indOffset13, indIndex );
4284 4284 opclass indIndexMemory( indIndex );
4285 4285
4286 4286 //----------PIPELINE-----------------------------------------------------------
4287 4287 pipeline %{
4288 4288
4289 4289 //----------ATTRIBUTES---------------------------------------------------------
4290 4290 attributes %{
4291 4291 fixed_size_instructions; // Fixed size instructions
4292 4292 branch_has_delay_slot; // Branch has delay slot following
4293 4293 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4294 4294 instruction_unit_size = 4; // An instruction is 4 bytes long
4295 4295 instruction_fetch_unit_size = 16; // The processor fetches one line
4296 4296 instruction_fetch_units = 1; // of 16 bytes
4297 4297
4298 4298 // List of nop instructions
4299 4299 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4300 4300 %}
4301 4301
4302 4302 //----------RESOURCES----------------------------------------------------------
4303 4303 // Resources are the functional units available to the machine
4304 4304 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4305 4305
4306 4306 //----------PIPELINE DESCRIPTION-----------------------------------------------
4307 4307 // Pipeline Description specifies the stages in the machine's pipeline
4308 4308
4309 4309 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4310 4310
4311 4311 //----------PIPELINE CLASSES---------------------------------------------------
4312 4312 // Pipeline Classes describe the stages in which input and output are
4313 4313 // referenced by the hardware pipeline.
4314 4314
4315 4315 // Integer ALU reg-reg operation
4316 4316 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4317 4317 single_instruction;
4318 4318 dst : E(write);
4319 4319 src1 : R(read);
4320 4320 src2 : R(read);
4321 4321 IALU : R;
4322 4322 %}
4323 4323
4324 4324 // Integer ALU reg-reg long operation
4325 4325 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4326 4326 instruction_count(2);
4327 4327 dst : E(write);
4328 4328 src1 : R(read);
4329 4329 src2 : R(read);
4330 4330 IALU : R;
4331 4331 IALU : R;
4332 4332 %}
4333 4333
4334 4334 // Integer ALU reg-reg long dependent operation
4335 4335 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4336 4336 instruction_count(1); multiple_bundles;
4337 4337 dst : E(write);
4338 4338 src1 : R(read);
4339 4339 src2 : R(read);
4340 4340 cr : E(write);
4341 4341 IALU : R(2);
4342 4342 %}
4343 4343
4344 4344 // Integer ALU reg-imm operaion
4345 4345 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4346 4346 single_instruction;
4347 4347 dst : E(write);
4348 4348 src1 : R(read);
4349 4349 IALU : R;
4350 4350 %}
4351 4351
4352 4352 // Integer ALU reg-reg operation with condition code
4353 4353 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4354 4354 single_instruction;
4355 4355 dst : E(write);
4356 4356 cr : E(write);
4357 4357 src1 : R(read);
4358 4358 src2 : R(read);
4359 4359 IALU : R;
4360 4360 %}
4361 4361
4362 4362 // Integer ALU reg-imm operation with condition code
4363 4363 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4364 4364 single_instruction;
4365 4365 dst : E(write);
4366 4366 cr : E(write);
4367 4367 src1 : R(read);
4368 4368 IALU : R;
4369 4369 %}
4370 4370
4371 4371 // Integer ALU zero-reg operation
4372 4372 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4373 4373 single_instruction;
4374 4374 dst : E(write);
4375 4375 src2 : R(read);
4376 4376 IALU : R;
4377 4377 %}
4378 4378
4379 4379 // Integer ALU zero-reg operation with condition code only
4380 4380 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4381 4381 single_instruction;
4382 4382 cr : E(write);
4383 4383 src : R(read);
4384 4384 IALU : R;
4385 4385 %}
4386 4386
4387 4387 // Integer ALU reg-reg operation with condition code only
4388 4388 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4389 4389 single_instruction;
4390 4390 cr : E(write);
4391 4391 src1 : R(read);
4392 4392 src2 : R(read);
4393 4393 IALU : R;
4394 4394 %}
4395 4395
4396 4396 // Integer ALU reg-imm operation with condition code only
4397 4397 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4398 4398 single_instruction;
4399 4399 cr : E(write);
4400 4400 src1 : R(read);
4401 4401 IALU : R;
4402 4402 %}
4403 4403
4404 4404 // Integer ALU reg-reg-zero operation with condition code only
4405 4405 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4406 4406 single_instruction;
4407 4407 cr : E(write);
4408 4408 src1 : R(read);
4409 4409 src2 : R(read);
4410 4410 IALU : R;
4411 4411 %}
4412 4412
4413 4413 // Integer ALU reg-imm-zero operation with condition code only
4414 4414 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4415 4415 single_instruction;
4416 4416 cr : E(write);
4417 4417 src1 : R(read);
4418 4418 IALU : R;
4419 4419 %}
4420 4420
4421 4421 // Integer ALU reg-reg operation with condition code, src1 modified
4422 4422 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4423 4423 single_instruction;
4424 4424 cr : E(write);
4425 4425 src1 : E(write);
4426 4426 src1 : R(read);
4427 4427 src2 : R(read);
4428 4428 IALU : R;
4429 4429 %}
4430 4430
4431 4431 // Integer ALU reg-imm operation with condition code, src1 modified
4432 4432 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4433 4433 single_instruction;
4434 4434 cr : E(write);
4435 4435 src1 : E(write);
4436 4436 src1 : R(read);
4437 4437 IALU : R;
4438 4438 %}
4439 4439
4440 4440 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4441 4441 multiple_bundles;
4442 4442 dst : E(write)+4;
4443 4443 cr : E(write);
4444 4444 src1 : R(read);
4445 4445 src2 : R(read);
4446 4446 IALU : R(3);
4447 4447 BR : R(2);
4448 4448 %}
4449 4449
4450 4450 // Integer ALU operation
4451 4451 pipe_class ialu_none(iRegI dst) %{
4452 4452 single_instruction;
4453 4453 dst : E(write);
4454 4454 IALU : R;
4455 4455 %}
4456 4456
4457 4457 // Integer ALU reg operation
4458 4458 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4459 4459 single_instruction; may_have_no_code;
4460 4460 dst : E(write);
4461 4461 src : R(read);
4462 4462 IALU : R;
4463 4463 %}
4464 4464
4465 4465 // Integer ALU reg conditional operation
4466 4466 // This instruction has a 1 cycle stall, and cannot execute
4467 4467 // in the same cycle as the instruction setting the condition
4468 4468 // code. We kludge this by pretending to read the condition code
4469 4469 // 1 cycle earlier, and by marking the functional units as busy
4470 4470 // for 2 cycles with the result available 1 cycle later than
4471 4471 // is really the case.
4472 4472 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4473 4473 single_instruction;
4474 4474 op2_out : C(write);
4475 4475 op1 : R(read);
4476 4476 cr : R(read); // This is really E, with a 1 cycle stall
4477 4477 BR : R(2);
4478 4478 MS : R(2);
4479 4479 %}
4480 4480
4481 4481 #ifdef _LP64
4482 4482 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4483 4483 instruction_count(1); multiple_bundles;
4484 4484 dst : C(write)+1;
4485 4485 src : R(read)+1;
4486 4486 IALU : R(1);
4487 4487 BR : E(2);
4488 4488 MS : E(2);
4489 4489 %}
4490 4490 #endif
4491 4491
4492 4492 // Integer ALU reg operation
4493 4493 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4494 4494 single_instruction; may_have_no_code;
4495 4495 dst : E(write);
4496 4496 src : R(read);
4497 4497 IALU : R;
4498 4498 %}
4499 4499 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4500 4500 single_instruction; may_have_no_code;
4501 4501 dst : E(write);
4502 4502 src : R(read);
4503 4503 IALU : R;
4504 4504 %}
4505 4505
4506 4506 // Two integer ALU reg operations
4507 4507 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4508 4508 instruction_count(2);
4509 4509 dst : E(write);
4510 4510 src : R(read);
4511 4511 A0 : R;
4512 4512 A1 : R;
4513 4513 %}
4514 4514
4515 4515 // Two integer ALU reg operations
4516 4516 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4517 4517 instruction_count(2); may_have_no_code;
4518 4518 dst : E(write);
4519 4519 src : R(read);
4520 4520 A0 : R;
4521 4521 A1 : R;
4522 4522 %}
4523 4523
4524 4524 // Integer ALU imm operation
4525 4525 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4526 4526 single_instruction;
4527 4527 dst : E(write);
4528 4528 IALU : R;
4529 4529 %}
4530 4530
4531 4531 // Integer ALU reg-reg with carry operation
4532 4532 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4533 4533 single_instruction;
4534 4534 dst : E(write);
4535 4535 src1 : R(read);
4536 4536 src2 : R(read);
4537 4537 IALU : R;
4538 4538 %}
4539 4539
4540 4540 // Integer ALU cc operation
4541 4541 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4542 4542 single_instruction;
4543 4543 dst : E(write);
4544 4544 cc : R(read);
4545 4545 IALU : R;
4546 4546 %}
4547 4547
4548 4548 // Integer ALU cc / second IALU operation
4549 4549 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4550 4550 instruction_count(1); multiple_bundles;
4551 4551 dst : E(write)+1;
4552 4552 src : R(read);
4553 4553 IALU : R;
4554 4554 %}
4555 4555
4556 4556 // Integer ALU cc / second IALU operation
4557 4557 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4558 4558 instruction_count(1); multiple_bundles;
4559 4559 dst : E(write)+1;
4560 4560 p : R(read);
4561 4561 q : R(read);
4562 4562 IALU : R;
4563 4563 %}
4564 4564
4565 4565 // Integer ALU hi-lo-reg operation
4566 4566 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4567 4567 instruction_count(1); multiple_bundles;
4568 4568 dst : E(write)+1;
4569 4569 IALU : R(2);
4570 4570 %}
4571 4571
4572 4572 // Float ALU hi-lo-reg operation (with temp)
4573 4573 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4574 4574 instruction_count(1); multiple_bundles;
4575 4575 dst : E(write)+1;
4576 4576 IALU : R(2);
4577 4577 %}
4578 4578
4579 4579 // Long Constant
4580 4580 pipe_class loadConL( iRegL dst, immL src ) %{
4581 4581 instruction_count(2); multiple_bundles;
4582 4582 dst : E(write)+1;
4583 4583 IALU : R(2);
4584 4584 IALU : R(2);
4585 4585 %}
4586 4586
4587 4587 // Pointer Constant
4588 4588 pipe_class loadConP( iRegP dst, immP src ) %{
4589 4589 instruction_count(0); multiple_bundles;
4590 4590 fixed_latency(6);
4591 4591 %}
4592 4592
4593 4593 // Polling Address
4594 4594 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4595 4595 #ifdef _LP64
4596 4596 instruction_count(0); multiple_bundles;
4597 4597 fixed_latency(6);
4598 4598 #else
4599 4599 dst : E(write);
4600 4600 IALU : R;
4601 4601 #endif
4602 4602 %}
4603 4603
4604 4604 // Long Constant small
4605 4605 pipe_class loadConLlo( iRegL dst, immL src ) %{
4606 4606 instruction_count(2);
4607 4607 dst : E(write);
4608 4608 IALU : R;
4609 4609 IALU : R;
4610 4610 %}
4611 4611
4612 4612 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4613 4613 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4614 4614 instruction_count(1); multiple_bundles;
4615 4615 src : R(read);
4616 4616 dst : M(write)+1;
4617 4617 IALU : R;
4618 4618 MS : E;
4619 4619 %}
4620 4620
4621 4621 // Integer ALU nop operation
4622 4622 pipe_class ialu_nop() %{
4623 4623 single_instruction;
4624 4624 IALU : R;
4625 4625 %}
4626 4626
4627 4627 // Integer ALU nop operation
4628 4628 pipe_class ialu_nop_A0() %{
4629 4629 single_instruction;
4630 4630 A0 : R;
4631 4631 %}
4632 4632
4633 4633 // Integer ALU nop operation
4634 4634 pipe_class ialu_nop_A1() %{
4635 4635 single_instruction;
4636 4636 A1 : R;
4637 4637 %}
4638 4638
4639 4639 // Integer Multiply reg-reg operation
4640 4640 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4641 4641 single_instruction;
4642 4642 dst : E(write);
4643 4643 src1 : R(read);
4644 4644 src2 : R(read);
4645 4645 MS : R(5);
4646 4646 %}
4647 4647
4648 4648 // Integer Multiply reg-imm operation
4649 4649 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4650 4650 single_instruction;
4651 4651 dst : E(write);
4652 4652 src1 : R(read);
4653 4653 MS : R(5);
4654 4654 %}
4655 4655
4656 4656 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4657 4657 single_instruction;
4658 4658 dst : E(write)+4;
4659 4659 src1 : R(read);
4660 4660 src2 : R(read);
4661 4661 MS : R(6);
4662 4662 %}
4663 4663
4664 4664 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4665 4665 single_instruction;
4666 4666 dst : E(write)+4;
4667 4667 src1 : R(read);
4668 4668 MS : R(6);
4669 4669 %}
4670 4670
4671 4671 // Integer Divide reg-reg
4672 4672 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4673 4673 instruction_count(1); multiple_bundles;
4674 4674 dst : E(write);
4675 4675 temp : E(write);
4676 4676 src1 : R(read);
4677 4677 src2 : R(read);
4678 4678 temp : R(read);
4679 4679 MS : R(38);
4680 4680 %}
4681 4681
4682 4682 // Integer Divide reg-imm
4683 4683 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4684 4684 instruction_count(1); multiple_bundles;
4685 4685 dst : E(write);
4686 4686 temp : E(write);
4687 4687 src1 : R(read);
4688 4688 temp : R(read);
4689 4689 MS : R(38);
4690 4690 %}
4691 4691
4692 4692 // Long Divide
4693 4693 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4694 4694 dst : E(write)+71;
4695 4695 src1 : R(read);
4696 4696 src2 : R(read)+1;
4697 4697 MS : R(70);
4698 4698 %}
4699 4699
4700 4700 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4701 4701 dst : E(write)+71;
4702 4702 src1 : R(read);
4703 4703 MS : R(70);
4704 4704 %}
4705 4705
4706 4706 // Floating Point Add Float
4707 4707 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4708 4708 single_instruction;
4709 4709 dst : X(write);
4710 4710 src1 : E(read);
4711 4711 src2 : E(read);
4712 4712 FA : R;
4713 4713 %}
4714 4714
4715 4715 // Floating Point Add Double
4716 4716 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4717 4717 single_instruction;
4718 4718 dst : X(write);
4719 4719 src1 : E(read);
4720 4720 src2 : E(read);
4721 4721 FA : R;
4722 4722 %}
4723 4723
4724 4724 // Floating Point Conditional Move based on integer flags
4725 4725 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4726 4726 single_instruction;
4727 4727 dst : X(write);
4728 4728 src : E(read);
4729 4729 cr : R(read);
4730 4730 FA : R(2);
4731 4731 BR : R(2);
4732 4732 %}
4733 4733
4734 4734 // Floating Point Conditional Move based on integer flags
4735 4735 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4736 4736 single_instruction;
4737 4737 dst : X(write);
4738 4738 src : E(read);
4739 4739 cr : R(read);
4740 4740 FA : R(2);
4741 4741 BR : R(2);
4742 4742 %}
4743 4743
4744 4744 // Floating Point Multiply Float
4745 4745 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4746 4746 single_instruction;
4747 4747 dst : X(write);
4748 4748 src1 : E(read);
4749 4749 src2 : E(read);
4750 4750 FM : R;
4751 4751 %}
4752 4752
4753 4753 // Floating Point Multiply Double
4754 4754 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4755 4755 single_instruction;
4756 4756 dst : X(write);
4757 4757 src1 : E(read);
4758 4758 src2 : E(read);
4759 4759 FM : R;
4760 4760 %}
4761 4761
4762 4762 // Floating Point Divide Float
4763 4763 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4764 4764 single_instruction;
4765 4765 dst : X(write);
4766 4766 src1 : E(read);
4767 4767 src2 : E(read);
4768 4768 FM : R;
4769 4769 FDIV : C(14);
4770 4770 %}
4771 4771
4772 4772 // Floating Point Divide Double
4773 4773 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4774 4774 single_instruction;
4775 4775 dst : X(write);
4776 4776 src1 : E(read);
4777 4777 src2 : E(read);
4778 4778 FM : R;
4779 4779 FDIV : C(17);
4780 4780 %}
4781 4781
4782 4782 // Floating Point Move/Negate/Abs Float
4783 4783 pipe_class faddF_reg(regF dst, regF src) %{
4784 4784 single_instruction;
4785 4785 dst : W(write);
4786 4786 src : E(read);
4787 4787 FA : R(1);
4788 4788 %}
4789 4789
4790 4790 // Floating Point Move/Negate/Abs Double
4791 4791 pipe_class faddD_reg(regD dst, regD src) %{
4792 4792 single_instruction;
4793 4793 dst : W(write);
4794 4794 src : E(read);
4795 4795 FA : R;
4796 4796 %}
4797 4797
4798 4798 // Floating Point Convert F->D
4799 4799 pipe_class fcvtF2D(regD dst, regF src) %{
4800 4800 single_instruction;
4801 4801 dst : X(write);
4802 4802 src : E(read);
4803 4803 FA : R;
4804 4804 %}
4805 4805
4806 4806 // Floating Point Convert I->D
4807 4807 pipe_class fcvtI2D(regD dst, regF src) %{
4808 4808 single_instruction;
4809 4809 dst : X(write);
4810 4810 src : E(read);
4811 4811 FA : R;
4812 4812 %}
4813 4813
4814 4814 // Floating Point Convert LHi->D
4815 4815 pipe_class fcvtLHi2D(regD dst, regD src) %{
4816 4816 single_instruction;
4817 4817 dst : X(write);
4818 4818 src : E(read);
4819 4819 FA : R;
4820 4820 %}
4821 4821
4822 4822 // Floating Point Convert L->D
4823 4823 pipe_class fcvtL2D(regD dst, regF src) %{
4824 4824 single_instruction;
4825 4825 dst : X(write);
4826 4826 src : E(read);
4827 4827 FA : R;
4828 4828 %}
4829 4829
4830 4830 // Floating Point Convert L->F
4831 4831 pipe_class fcvtL2F(regD dst, regF src) %{
4832 4832 single_instruction;
4833 4833 dst : X(write);
4834 4834 src : E(read);
4835 4835 FA : R;
4836 4836 %}
4837 4837
4838 4838 // Floating Point Convert D->F
4839 4839 pipe_class fcvtD2F(regD dst, regF src) %{
4840 4840 single_instruction;
4841 4841 dst : X(write);
4842 4842 src : E(read);
4843 4843 FA : R;
4844 4844 %}
4845 4845
4846 4846 // Floating Point Convert I->L
4847 4847 pipe_class fcvtI2L(regD dst, regF src) %{
4848 4848 single_instruction;
4849 4849 dst : X(write);
4850 4850 src : E(read);
4851 4851 FA : R;
4852 4852 %}
4853 4853
4854 4854 // Floating Point Convert D->F
4855 4855 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4856 4856 instruction_count(1); multiple_bundles;
4857 4857 dst : X(write)+6;
4858 4858 src : E(read);
4859 4859 FA : R;
4860 4860 %}
4861 4861
4862 4862 // Floating Point Convert D->L
4863 4863 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4864 4864 instruction_count(1); multiple_bundles;
4865 4865 dst : X(write)+6;
4866 4866 src : E(read);
4867 4867 FA : R;
4868 4868 %}
4869 4869
4870 4870 // Floating Point Convert F->I
4871 4871 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4872 4872 instruction_count(1); multiple_bundles;
4873 4873 dst : X(write)+6;
4874 4874 src : E(read);
4875 4875 FA : R;
4876 4876 %}
4877 4877
4878 4878 // Floating Point Convert F->L
4879 4879 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4880 4880 instruction_count(1); multiple_bundles;
4881 4881 dst : X(write)+6;
4882 4882 src : E(read);
4883 4883 FA : R;
4884 4884 %}
4885 4885
4886 4886 // Floating Point Convert I->F
4887 4887 pipe_class fcvtI2F(regF dst, regF src) %{
4888 4888 single_instruction;
4889 4889 dst : X(write);
4890 4890 src : E(read);
4891 4891 FA : R;
4892 4892 %}
4893 4893
4894 4894 // Floating Point Compare
4895 4895 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4896 4896 single_instruction;
4897 4897 cr : X(write);
4898 4898 src1 : E(read);
4899 4899 src2 : E(read);
4900 4900 FA : R;
4901 4901 %}
4902 4902
4903 4903 // Floating Point Compare
4904 4904 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4905 4905 single_instruction;
4906 4906 cr : X(write);
4907 4907 src1 : E(read);
4908 4908 src2 : E(read);
4909 4909 FA : R;
4910 4910 %}
4911 4911
4912 4912 // Floating Add Nop
4913 4913 pipe_class fadd_nop() %{
4914 4914 single_instruction;
4915 4915 FA : R;
4916 4916 %}
4917 4917
4918 4918 // Integer Store to Memory
4919 4919 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4920 4920 single_instruction;
4921 4921 mem : R(read);
4922 4922 src : C(read);
4923 4923 MS : R;
4924 4924 %}
4925 4925
4926 4926 // Integer Store to Memory
4927 4927 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4928 4928 single_instruction;
4929 4929 mem : R(read);
4930 4930 src : C(read);
4931 4931 MS : R;
4932 4932 %}
4933 4933
4934 4934 // Integer Store Zero to Memory
4935 4935 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4936 4936 single_instruction;
4937 4937 mem : R(read);
4938 4938 MS : R;
4939 4939 %}
4940 4940
4941 4941 // Special Stack Slot Store
4942 4942 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4943 4943 single_instruction;
4944 4944 stkSlot : R(read);
4945 4945 src : C(read);
4946 4946 MS : R;
4947 4947 %}
4948 4948
4949 4949 // Special Stack Slot Store
4950 4950 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4951 4951 instruction_count(2); multiple_bundles;
4952 4952 stkSlot : R(read);
4953 4953 src : C(read);
4954 4954 MS : R(2);
4955 4955 %}
4956 4956
4957 4957 // Float Store
4958 4958 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4959 4959 single_instruction;
4960 4960 mem : R(read);
4961 4961 src : C(read);
4962 4962 MS : R;
4963 4963 %}
4964 4964
4965 4965 // Float Store
4966 4966 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4967 4967 single_instruction;
4968 4968 mem : R(read);
4969 4969 MS : R;
4970 4970 %}
4971 4971
4972 4972 // Double Store
4973 4973 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4974 4974 instruction_count(1);
4975 4975 mem : R(read);
4976 4976 src : C(read);
4977 4977 MS : R;
4978 4978 %}
4979 4979
4980 4980 // Double Store
4981 4981 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4982 4982 single_instruction;
4983 4983 mem : R(read);
4984 4984 MS : R;
4985 4985 %}
4986 4986
4987 4987 // Special Stack Slot Float Store
4988 4988 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4989 4989 single_instruction;
4990 4990 stkSlot : R(read);
4991 4991 src : C(read);
4992 4992 MS : R;
4993 4993 %}
4994 4994
4995 4995 // Special Stack Slot Double Store
4996 4996 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4997 4997 single_instruction;
4998 4998 stkSlot : R(read);
4999 4999 src : C(read);
5000 5000 MS : R;
5001 5001 %}
5002 5002
5003 5003 // Integer Load (when sign bit propagation not needed)
5004 5004 pipe_class iload_mem(iRegI dst, memory mem) %{
5005 5005 single_instruction;
5006 5006 mem : R(read);
5007 5007 dst : C(write);
5008 5008 MS : R;
5009 5009 %}
5010 5010
5011 5011 // Integer Load from stack operand
5012 5012 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5013 5013 single_instruction;
5014 5014 mem : R(read);
5015 5015 dst : C(write);
5016 5016 MS : R;
5017 5017 %}
5018 5018
5019 5019 // Integer Load (when sign bit propagation or masking is needed)
5020 5020 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5021 5021 single_instruction;
5022 5022 mem : R(read);
5023 5023 dst : M(write);
5024 5024 MS : R;
5025 5025 %}
5026 5026
5027 5027 // Float Load
5028 5028 pipe_class floadF_mem(regF dst, memory mem) %{
5029 5029 single_instruction;
5030 5030 mem : R(read);
5031 5031 dst : M(write);
5032 5032 MS : R;
5033 5033 %}
5034 5034
5035 5035 // Float Load
5036 5036 pipe_class floadD_mem(regD dst, memory mem) %{
5037 5037 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5038 5038 mem : R(read);
5039 5039 dst : M(write);
5040 5040 MS : R;
5041 5041 %}
5042 5042
5043 5043 // Float Load
5044 5044 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5045 5045 single_instruction;
5046 5046 stkSlot : R(read);
5047 5047 dst : M(write);
5048 5048 MS : R;
5049 5049 %}
5050 5050
5051 5051 // Float Load
5052 5052 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5053 5053 single_instruction;
5054 5054 stkSlot : R(read);
5055 5055 dst : M(write);
5056 5056 MS : R;
5057 5057 %}
5058 5058
5059 5059 // Memory Nop
5060 5060 pipe_class mem_nop() %{
5061 5061 single_instruction;
5062 5062 MS : R;
5063 5063 %}
5064 5064
5065 5065 pipe_class sethi(iRegP dst, immI src) %{
5066 5066 single_instruction;
5067 5067 dst : E(write);
5068 5068 IALU : R;
5069 5069 %}
5070 5070
5071 5071 pipe_class loadPollP(iRegP poll) %{
5072 5072 single_instruction;
5073 5073 poll : R(read);
5074 5074 MS : R;
5075 5075 %}
5076 5076
5077 5077 pipe_class br(Universe br, label labl) %{
5078 5078 single_instruction_with_delay_slot;
5079 5079 BR : R;
5080 5080 %}
5081 5081
5082 5082 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5083 5083 single_instruction_with_delay_slot;
5084 5084 cr : E(read);
5085 5085 BR : R;
5086 5086 %}
5087 5087
5088 5088 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5089 5089 single_instruction_with_delay_slot;
5090 5090 op1 : E(read);
5091 5091 BR : R;
5092 5092 MS : R;
5093 5093 %}
5094 5094
5095 5095 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5096 5096 single_instruction_with_delay_slot;
5097 5097 cr : E(read);
5098 5098 BR : R;
5099 5099 %}
5100 5100
5101 5101 pipe_class br_nop() %{
5102 5102 single_instruction;
5103 5103 BR : R;
5104 5104 %}
5105 5105
5106 5106 pipe_class simple_call(method meth) %{
5107 5107 instruction_count(2); multiple_bundles; force_serialization;
5108 5108 fixed_latency(100);
5109 5109 BR : R(1);
5110 5110 MS : R(1);
5111 5111 A0 : R(1);
5112 5112 %}
5113 5113
5114 5114 pipe_class compiled_call(method meth) %{
5115 5115 instruction_count(1); multiple_bundles; force_serialization;
5116 5116 fixed_latency(100);
5117 5117 MS : R(1);
5118 5118 %}
5119 5119
5120 5120 pipe_class call(method meth) %{
5121 5121 instruction_count(0); multiple_bundles; force_serialization;
5122 5122 fixed_latency(100);
5123 5123 %}
5124 5124
5125 5125 pipe_class tail_call(Universe ignore, label labl) %{
5126 5126 single_instruction; has_delay_slot;
5127 5127 fixed_latency(100);
5128 5128 BR : R(1);
5129 5129 MS : R(1);
5130 5130 %}
5131 5131
5132 5132 pipe_class ret(Universe ignore) %{
5133 5133 single_instruction; has_delay_slot;
5134 5134 BR : R(1);
5135 5135 MS : R(1);
5136 5136 %}
5137 5137
5138 5138 pipe_class ret_poll(g3RegP poll) %{
5139 5139 instruction_count(3); has_delay_slot;
5140 5140 poll : E(read);
5141 5141 MS : R;
5142 5142 %}
5143 5143
5144 5144 // The real do-nothing guy
5145 5145 pipe_class empty( ) %{
5146 5146 instruction_count(0);
5147 5147 %}
5148 5148
5149 5149 pipe_class long_memory_op() %{
5150 5150 instruction_count(0); multiple_bundles; force_serialization;
5151 5151 fixed_latency(25);
5152 5152 MS : R(1);
5153 5153 %}
5154 5154
5155 5155 // Check-cast
5156 5156 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5157 5157 array : R(read);
5158 5158 match : R(read);
5159 5159 IALU : R(2);
5160 5160 BR : R(2);
5161 5161 MS : R;
5162 5162 %}
5163 5163
5164 5164 // Convert FPU flags into +1,0,-1
5165 5165 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5166 5166 src1 : E(read);
5167 5167 src2 : E(read);
5168 5168 dst : E(write);
5169 5169 FA : R;
5170 5170 MS : R(2);
5171 5171 BR : R(2);
5172 5172 %}
5173 5173
5174 5174 // Compare for p < q, and conditionally add y
5175 5175 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5176 5176 p : E(read);
5177 5177 q : E(read);
5178 5178 y : E(read);
5179 5179 IALU : R(3)
5180 5180 %}
5181 5181
5182 5182 // Perform a compare, then move conditionally in a branch delay slot.
5183 5183 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5184 5184 src2 : E(read);
5185 5185 srcdst : E(read);
5186 5186 IALU : R;
5187 5187 BR : R;
5188 5188 %}
5189 5189
5190 5190 // Define the class for the Nop node
5191 5191 define %{
5192 5192 MachNop = ialu_nop;
5193 5193 %}
5194 5194
5195 5195 %}
5196 5196
5197 5197 //----------INSTRUCTIONS-------------------------------------------------------
5198 5198
5199 5199 //------------Special Stack Slot instructions - no match rules-----------------
5200 5200 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5201 5201 // No match rule to avoid chain rule match.
5202 5202 effect(DEF dst, USE src);
5203 5203 ins_cost(MEMORY_REF_COST);
5204 5204 size(4);
5205 5205 format %{ "LDF $src,$dst\t! stkI to regF" %}
5206 5206 opcode(Assembler::ldf_op3);
5207 5207 ins_encode(simple_form3_mem_reg(src, dst));
5208 5208 ins_pipe(floadF_stk);
5209 5209 %}
5210 5210
5211 5211 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5212 5212 // No match rule to avoid chain rule match.
5213 5213 effect(DEF dst, USE src);
5214 5214 ins_cost(MEMORY_REF_COST);
5215 5215 size(4);
5216 5216 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5217 5217 opcode(Assembler::lddf_op3);
5218 5218 ins_encode(simple_form3_mem_reg(src, dst));
5219 5219 ins_pipe(floadD_stk);
5220 5220 %}
5221 5221
5222 5222 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5223 5223 // No match rule to avoid chain rule match.
5224 5224 effect(DEF dst, USE src);
5225 5225 ins_cost(MEMORY_REF_COST);
5226 5226 size(4);
5227 5227 format %{ "STF $src,$dst\t! regF to stkI" %}
5228 5228 opcode(Assembler::stf_op3);
5229 5229 ins_encode(simple_form3_mem_reg(dst, src));
5230 5230 ins_pipe(fstoreF_stk_reg);
5231 5231 %}
5232 5232
5233 5233 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5234 5234 // No match rule to avoid chain rule match.
5235 5235 effect(DEF dst, USE src);
5236 5236 ins_cost(MEMORY_REF_COST);
5237 5237 size(4);
5238 5238 format %{ "STDF $src,$dst\t! regD to stkL" %}
5239 5239 opcode(Assembler::stdf_op3);
5240 5240 ins_encode(simple_form3_mem_reg(dst, src));
5241 5241 ins_pipe(fstoreD_stk_reg);
5242 5242 %}
5243 5243
5244 5244 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5245 5245 effect(DEF dst, USE src);
5246 5246 ins_cost(MEMORY_REF_COST*2);
5247 5247 size(8);
5248 5248 format %{ "STW $src,$dst.hi\t! long\n\t"
5249 5249 "STW R_G0,$dst.lo" %}
5250 5250 opcode(Assembler::stw_op3);
5251 5251 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5252 5252 ins_pipe(lstoreI_stk_reg);
5253 5253 %}
5254 5254
5255 5255 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5256 5256 // No match rule to avoid chain rule match.
5257 5257 effect(DEF dst, USE src);
5258 5258 ins_cost(MEMORY_REF_COST);
5259 5259 size(4);
5260 5260 format %{ "STX $src,$dst\t! regL to stkD" %}
5261 5261 opcode(Assembler::stx_op3);
5262 5262 ins_encode(simple_form3_mem_reg( dst, src ) );
5263 5263 ins_pipe(istore_stk_reg);
5264 5264 %}
5265 5265
5266 5266 //---------- Chain stack slots between similar types --------
5267 5267
5268 5268 // Load integer from stack slot
5269 5269 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5270 5270 match(Set dst src);
5271 5271 ins_cost(MEMORY_REF_COST);
5272 5272
5273 5273 size(4);
5274 5274 format %{ "LDUW $src,$dst\t!stk" %}
5275 5275 opcode(Assembler::lduw_op3);
5276 5276 ins_encode(simple_form3_mem_reg( src, dst ) );
5277 5277 ins_pipe(iload_mem);
5278 5278 %}
5279 5279
5280 5280 // Store integer to stack slot
5281 5281 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5282 5282 match(Set dst src);
5283 5283 ins_cost(MEMORY_REF_COST);
5284 5284
5285 5285 size(4);
5286 5286 format %{ "STW $src,$dst\t!stk" %}
5287 5287 opcode(Assembler::stw_op3);
5288 5288 ins_encode(simple_form3_mem_reg( dst, src ) );
5289 5289 ins_pipe(istore_mem_reg);
5290 5290 %}
5291 5291
5292 5292 // Load long from stack slot
5293 5293 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5294 5294 match(Set dst src);
5295 5295
5296 5296 ins_cost(MEMORY_REF_COST);
5297 5297 size(4);
5298 5298 format %{ "LDX $src,$dst\t! long" %}
5299 5299 opcode(Assembler::ldx_op3);
5300 5300 ins_encode(simple_form3_mem_reg( src, dst ) );
5301 5301 ins_pipe(iload_mem);
5302 5302 %}
5303 5303
5304 5304 // Store long to stack slot
5305 5305 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5306 5306 match(Set dst src);
5307 5307
5308 5308 ins_cost(MEMORY_REF_COST);
5309 5309 size(4);
5310 5310 format %{ "STX $src,$dst\t! long" %}
5311 5311 opcode(Assembler::stx_op3);
5312 5312 ins_encode(simple_form3_mem_reg( dst, src ) );
5313 5313 ins_pipe(istore_mem_reg);
5314 5314 %}
5315 5315
5316 5316 #ifdef _LP64
5317 5317 // Load pointer from stack slot, 64-bit encoding
5318 5318 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5319 5319 match(Set dst src);
5320 5320 ins_cost(MEMORY_REF_COST);
5321 5321 size(4);
5322 5322 format %{ "LDX $src,$dst\t!ptr" %}
5323 5323 opcode(Assembler::ldx_op3);
5324 5324 ins_encode(simple_form3_mem_reg( src, dst ) );
5325 5325 ins_pipe(iload_mem);
5326 5326 %}
5327 5327
5328 5328 // Store pointer to stack slot
5329 5329 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5330 5330 match(Set dst src);
5331 5331 ins_cost(MEMORY_REF_COST);
5332 5332 size(4);
5333 5333 format %{ "STX $src,$dst\t!ptr" %}
5334 5334 opcode(Assembler::stx_op3);
5335 5335 ins_encode(simple_form3_mem_reg( dst, src ) );
5336 5336 ins_pipe(istore_mem_reg);
5337 5337 %}
5338 5338 #else // _LP64
5339 5339 // Load pointer from stack slot, 32-bit encoding
5340 5340 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5341 5341 match(Set dst src);
5342 5342 ins_cost(MEMORY_REF_COST);
5343 5343 format %{ "LDUW $src,$dst\t!ptr" %}
5344 5344 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5345 5345 ins_encode(simple_form3_mem_reg( src, dst ) );
5346 5346 ins_pipe(iload_mem);
5347 5347 %}
5348 5348
5349 5349 // Store pointer to stack slot
5350 5350 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5351 5351 match(Set dst src);
5352 5352 ins_cost(MEMORY_REF_COST);
5353 5353 format %{ "STW $src,$dst\t!ptr" %}
5354 5354 opcode(Assembler::stw_op3, Assembler::ldst_op);
5355 5355 ins_encode(simple_form3_mem_reg( dst, src ) );
5356 5356 ins_pipe(istore_mem_reg);
5357 5357 %}
5358 5358 #endif // _LP64
5359 5359
5360 5360 //------------Special Nop instructions for bundling - no match rules-----------
5361 5361 // Nop using the A0 functional unit
5362 5362 instruct Nop_A0() %{
5363 5363 ins_cost(0);
5364 5364
5365 5365 format %{ "NOP ! Alu Pipeline" %}
5366 5366 opcode(Assembler::or_op3, Assembler::arith_op);
5367 5367 ins_encode( form2_nop() );
5368 5368 ins_pipe(ialu_nop_A0);
5369 5369 %}
5370 5370
5371 5371 // Nop using the A1 functional unit
5372 5372 instruct Nop_A1( ) %{
5373 5373 ins_cost(0);
5374 5374
5375 5375 format %{ "NOP ! Alu Pipeline" %}
5376 5376 opcode(Assembler::or_op3, Assembler::arith_op);
5377 5377 ins_encode( form2_nop() );
5378 5378 ins_pipe(ialu_nop_A1);
5379 5379 %}
5380 5380
5381 5381 // Nop using the memory functional unit
5382 5382 instruct Nop_MS( ) %{
5383 5383 ins_cost(0);
5384 5384
5385 5385 format %{ "NOP ! Memory Pipeline" %}
5386 5386 ins_encode( emit_mem_nop );
5387 5387 ins_pipe(mem_nop);
5388 5388 %}
5389 5389
5390 5390 // Nop using the floating add functional unit
5391 5391 instruct Nop_FA( ) %{
5392 5392 ins_cost(0);
5393 5393
5394 5394 format %{ "NOP ! Floating Add Pipeline" %}
5395 5395 ins_encode( emit_fadd_nop );
5396 5396 ins_pipe(fadd_nop);
5397 5397 %}
5398 5398
5399 5399 // Nop using the branch functional unit
5400 5400 instruct Nop_BR( ) %{
5401 5401 ins_cost(0);
5402 5402
5403 5403 format %{ "NOP ! Branch Pipeline" %}
5404 5404 ins_encode( emit_br_nop );
5405 5405 ins_pipe(br_nop);
5406 5406 %}
5407 5407
5408 5408 //----------Load/Store/Move Instructions---------------------------------------
5409 5409 //----------Load Instructions--------------------------------------------------
5410 5410 // Load Byte (8bit signed)
5411 5411 instruct loadB(iRegI dst, memory mem) %{
5412 5412 match(Set dst (LoadB mem));
5413 5413 ins_cost(MEMORY_REF_COST);
5414 5414
5415 5415 size(4);
5416 5416 format %{ "LDSB $mem,$dst\t! byte" %}
5417 5417 ins_encode %{
5418 5418 __ ldsb($mem$$Address, $dst$$Register);
5419 5419 %}
5420 5420 ins_pipe(iload_mask_mem);
5421 5421 %}
5422 5422
5423 5423 // Load Byte (8bit signed) into a Long Register
5424 5424 instruct loadB2L(iRegL dst, memory mem) %{
5425 5425 match(Set dst (ConvI2L (LoadB mem)));
5426 5426 ins_cost(MEMORY_REF_COST);
5427 5427
5428 5428 size(4);
5429 5429 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5430 5430 ins_encode %{
5431 5431 __ ldsb($mem$$Address, $dst$$Register);
5432 5432 %}
5433 5433 ins_pipe(iload_mask_mem);
5434 5434 %}
5435 5435
5436 5436 // Load Unsigned Byte (8bit UNsigned) into an int reg
5437 5437 instruct loadUB(iRegI dst, memory mem) %{
5438 5438 match(Set dst (LoadUB mem));
5439 5439 ins_cost(MEMORY_REF_COST);
5440 5440
5441 5441 size(4);
5442 5442 format %{ "LDUB $mem,$dst\t! ubyte" %}
5443 5443 ins_encode %{
5444 5444 __ ldub($mem$$Address, $dst$$Register);
5445 5445 %}
5446 5446 ins_pipe(iload_mem);
5447 5447 %}
5448 5448
5449 5449 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5450 5450 instruct loadUB2L(iRegL dst, memory mem) %{
5451 5451 match(Set dst (ConvI2L (LoadUB mem)));
5452 5452 ins_cost(MEMORY_REF_COST);
5453 5453
5454 5454 size(4);
5455 5455 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5456 5456 ins_encode %{
5457 5457 __ ldub($mem$$Address, $dst$$Register);
5458 5458 %}
5459 5459 ins_pipe(iload_mem);
5460 5460 %}
5461 5461
5462 5462 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5463 5463 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5464 5464 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5465 5465 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5466 5466
5467 5467 size(2*4);
5468 5468 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5469 5469 "AND $dst,$mask,$dst" %}
5470 5470 ins_encode %{
5471 5471 __ ldub($mem$$Address, $dst$$Register);
5472 5472 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5473 5473 %}
5474 5474 ins_pipe(iload_mem);
5475 5475 %}
5476 5476
5477 5477 // Load Short (16bit signed)
5478 5478 instruct loadS(iRegI dst, memory mem) %{
5479 5479 match(Set dst (LoadS mem));
5480 5480 ins_cost(MEMORY_REF_COST);
5481 5481
5482 5482 size(4);
5483 5483 format %{ "LDSH $mem,$dst\t! short" %}
5484 5484 ins_encode %{
5485 5485 __ ldsh($mem$$Address, $dst$$Register);
5486 5486 %}
5487 5487 ins_pipe(iload_mask_mem);
5488 5488 %}
5489 5489
5490 5490 // Load Short (16 bit signed) to Byte (8 bit signed)
5491 5491 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5492 5492 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5493 5493 ins_cost(MEMORY_REF_COST);
5494 5494
5495 5495 size(4);
5496 5496
5497 5497 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5498 5498 ins_encode %{
5499 5499 __ ldsb($mem$$Address, $dst$$Register, 1);
5500 5500 %}
5501 5501 ins_pipe(iload_mask_mem);
5502 5502 %}
5503 5503
5504 5504 // Load Short (16bit signed) into a Long Register
5505 5505 instruct loadS2L(iRegL dst, memory mem) %{
5506 5506 match(Set dst (ConvI2L (LoadS mem)));
5507 5507 ins_cost(MEMORY_REF_COST);
5508 5508
5509 5509 size(4);
5510 5510 format %{ "LDSH $mem,$dst\t! short -> long" %}
5511 5511 ins_encode %{
5512 5512 __ ldsh($mem$$Address, $dst$$Register);
5513 5513 %}
5514 5514 ins_pipe(iload_mask_mem);
5515 5515 %}
5516 5516
5517 5517 // Load Unsigned Short/Char (16bit UNsigned)
5518 5518 instruct loadUS(iRegI dst, memory mem) %{
5519 5519 match(Set dst (LoadUS mem));
5520 5520 ins_cost(MEMORY_REF_COST);
5521 5521
5522 5522 size(4);
5523 5523 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5524 5524 ins_encode %{
5525 5525 __ lduh($mem$$Address, $dst$$Register);
5526 5526 %}
5527 5527 ins_pipe(iload_mem);
5528 5528 %}
5529 5529
5530 5530 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5531 5531 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5532 5532 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5533 5533 ins_cost(MEMORY_REF_COST);
5534 5534
5535 5535 size(4);
5536 5536 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5537 5537 ins_encode %{
5538 5538 __ ldsb($mem$$Address, $dst$$Register, 1);
5539 5539 %}
5540 5540 ins_pipe(iload_mask_mem);
5541 5541 %}
5542 5542
5543 5543 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5544 5544 instruct loadUS2L(iRegL dst, memory mem) %{
5545 5545 match(Set dst (ConvI2L (LoadUS mem)));
5546 5546 ins_cost(MEMORY_REF_COST);
5547 5547
5548 5548 size(4);
5549 5549 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5550 5550 ins_encode %{
5551 5551 __ lduh($mem$$Address, $dst$$Register);
5552 5552 %}
5553 5553 ins_pipe(iload_mem);
5554 5554 %}
5555 5555
5556 5556 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5557 5557 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5558 5558 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5559 5559 ins_cost(MEMORY_REF_COST);
5560 5560
5561 5561 size(4);
5562 5562 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5563 5563 ins_encode %{
5564 5564 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5565 5565 %}
5566 5566 ins_pipe(iload_mem);
5567 5567 %}
5568 5568
5569 5569 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5570 5570 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5571 5571 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5572 5572 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5573 5573
5574 5574 size(2*4);
5575 5575 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5576 5576 "AND $dst,$mask,$dst" %}
5577 5577 ins_encode %{
5578 5578 Register Rdst = $dst$$Register;
5579 5579 __ lduh($mem$$Address, Rdst);
5580 5580 __ and3(Rdst, $mask$$constant, Rdst);
5581 5581 %}
5582 5582 ins_pipe(iload_mem);
5583 5583 %}
5584 5584
5585 5585 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5586 5586 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5587 5587 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5588 5588 effect(TEMP dst, TEMP tmp);
5589 5589 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5590 5590
5591 5591 size((3+1)*4); // set may use two instructions.
5592 5592 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5593 5593 "SET $mask,$tmp\n\t"
5594 5594 "AND $dst,$tmp,$dst" %}
5595 5595 ins_encode %{
5596 5596 Register Rdst = $dst$$Register;
5597 5597 Register Rtmp = $tmp$$Register;
5598 5598 __ lduh($mem$$Address, Rdst);
5599 5599 __ set($mask$$constant, Rtmp);
5600 5600 __ and3(Rdst, Rtmp, Rdst);
5601 5601 %}
5602 5602 ins_pipe(iload_mem);
5603 5603 %}
5604 5604
5605 5605 // Load Integer
5606 5606 instruct loadI(iRegI dst, memory mem) %{
5607 5607 match(Set dst (LoadI mem));
5608 5608 ins_cost(MEMORY_REF_COST);
5609 5609
5610 5610 size(4);
5611 5611 format %{ "LDUW $mem,$dst\t! int" %}
5612 5612 ins_encode %{
5613 5613 __ lduw($mem$$Address, $dst$$Register);
5614 5614 %}
5615 5615 ins_pipe(iload_mem);
5616 5616 %}
5617 5617
5618 5618 // Load Integer to Byte (8 bit signed)
5619 5619 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5620 5620 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5621 5621 ins_cost(MEMORY_REF_COST);
5622 5622
5623 5623 size(4);
5624 5624
5625 5625 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5626 5626 ins_encode %{
5627 5627 __ ldsb($mem$$Address, $dst$$Register, 3);
5628 5628 %}
5629 5629 ins_pipe(iload_mask_mem);
5630 5630 %}
5631 5631
5632 5632 // Load Integer to Unsigned Byte (8 bit UNsigned)
5633 5633 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5634 5634 match(Set dst (AndI (LoadI mem) mask));
5635 5635 ins_cost(MEMORY_REF_COST);
5636 5636
5637 5637 size(4);
5638 5638
5639 5639 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5640 5640 ins_encode %{
5641 5641 __ ldub($mem$$Address, $dst$$Register, 3);
5642 5642 %}
5643 5643 ins_pipe(iload_mask_mem);
5644 5644 %}
5645 5645
5646 5646 // Load Integer to Short (16 bit signed)
5647 5647 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5648 5648 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5649 5649 ins_cost(MEMORY_REF_COST);
5650 5650
5651 5651 size(4);
5652 5652
5653 5653 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5654 5654 ins_encode %{
5655 5655 __ ldsh($mem$$Address, $dst$$Register, 2);
5656 5656 %}
5657 5657 ins_pipe(iload_mask_mem);
5658 5658 %}
5659 5659
5660 5660 // Load Integer to Unsigned Short (16 bit UNsigned)
5661 5661 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5662 5662 match(Set dst (AndI (LoadI mem) mask));
5663 5663 ins_cost(MEMORY_REF_COST);
5664 5664
5665 5665 size(4);
5666 5666
5667 5667 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5668 5668 ins_encode %{
5669 5669 __ lduh($mem$$Address, $dst$$Register, 2);
5670 5670 %}
5671 5671 ins_pipe(iload_mask_mem);
5672 5672 %}
5673 5673
5674 5674 // Load Integer into a Long Register
5675 5675 instruct loadI2L(iRegL dst, memory mem) %{
5676 5676 match(Set dst (ConvI2L (LoadI mem)));
5677 5677 ins_cost(MEMORY_REF_COST);
5678 5678
5679 5679 size(4);
5680 5680 format %{ "LDSW $mem,$dst\t! int -> long" %}
5681 5681 ins_encode %{
5682 5682 __ ldsw($mem$$Address, $dst$$Register);
5683 5683 %}
5684 5684 ins_pipe(iload_mask_mem);
5685 5685 %}
5686 5686
5687 5687 // Load Integer with mask 0xFF into a Long Register
5688 5688 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5689 5689 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5690 5690 ins_cost(MEMORY_REF_COST);
5691 5691
5692 5692 size(4);
5693 5693 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5694 5694 ins_encode %{
5695 5695 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5696 5696 %}
5697 5697 ins_pipe(iload_mem);
5698 5698 %}
5699 5699
5700 5700 // Load Integer with mask 0xFFFF into a Long Register
5701 5701 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5702 5702 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5703 5703 ins_cost(MEMORY_REF_COST);
5704 5704
5705 5705 size(4);
5706 5706 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5707 5707 ins_encode %{
5708 5708 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5709 5709 %}
5710 5710 ins_pipe(iload_mem);
5711 5711 %}
5712 5712
5713 5713 // Load Integer with a 13-bit mask into a Long Register
5714 5714 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5715 5715 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5716 5716 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5717 5717
5718 5718 size(2*4);
5719 5719 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5720 5720 "AND $dst,$mask,$dst" %}
5721 5721 ins_encode %{
5722 5722 Register Rdst = $dst$$Register;
5723 5723 __ lduw($mem$$Address, Rdst);
5724 5724 __ and3(Rdst, $mask$$constant, Rdst);
5725 5725 %}
5726 5726 ins_pipe(iload_mem);
5727 5727 %}
5728 5728
5729 5729 // Load Integer with a 32-bit mask into a Long Register
5730 5730 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5731 5731 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5732 5732 effect(TEMP dst, TEMP tmp);
5733 5733 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5734 5734
5735 5735 size((3+1)*4); // set may use two instructions.
5736 5736 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5737 5737 "SET $mask,$tmp\n\t"
5738 5738 "AND $dst,$tmp,$dst" %}
5739 5739 ins_encode %{
5740 5740 Register Rdst = $dst$$Register;
5741 5741 Register Rtmp = $tmp$$Register;
5742 5742 __ lduw($mem$$Address, Rdst);
5743 5743 __ set($mask$$constant, Rtmp);
5744 5744 __ and3(Rdst, Rtmp, Rdst);
5745 5745 %}
5746 5746 ins_pipe(iload_mem);
5747 5747 %}
5748 5748
5749 5749 // Load Unsigned Integer into a Long Register
5750 5750 instruct loadUI2L(iRegL dst, memory mem) %{
5751 5751 match(Set dst (LoadUI2L mem));
5752 5752 ins_cost(MEMORY_REF_COST);
5753 5753
5754 5754 size(4);
5755 5755 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5756 5756 ins_encode %{
5757 5757 __ lduw($mem$$Address, $dst$$Register);
5758 5758 %}
5759 5759 ins_pipe(iload_mem);
5760 5760 %}
5761 5761
5762 5762 // Load Long - aligned
5763 5763 instruct loadL(iRegL dst, memory mem ) %{
5764 5764 match(Set dst (LoadL mem));
5765 5765 ins_cost(MEMORY_REF_COST);
5766 5766
5767 5767 size(4);
5768 5768 format %{ "LDX $mem,$dst\t! long" %}
5769 5769 ins_encode %{
5770 5770 __ ldx($mem$$Address, $dst$$Register);
5771 5771 %}
5772 5772 ins_pipe(iload_mem);
5773 5773 %}
5774 5774
5775 5775 // Load Long - UNaligned
5776 5776 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5777 5777 match(Set dst (LoadL_unaligned mem));
5778 5778 effect(KILL tmp);
5779 5779 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5780 5780 size(16);
5781 5781 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5782 5782 "\tLDUW $mem ,$dst\n"
5783 5783 "\tSLLX #32, $dst, $dst\n"
5784 5784 "\tOR $dst, R_O7, $dst" %}
5785 5785 opcode(Assembler::lduw_op3);
5786 5786 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5787 5787 ins_pipe(iload_mem);
5788 5788 %}
5789 5789
5790 5790 // Load Aligned Packed Byte into a Double Register
5791 5791 instruct loadA8B(regD dst, memory mem) %{
5792 5792 match(Set dst (Load8B mem));
5793 5793 ins_cost(MEMORY_REF_COST);
5794 5794 size(4);
5795 5795 format %{ "LDDF $mem,$dst\t! packed8B" %}
5796 5796 opcode(Assembler::lddf_op3);
5797 5797 ins_encode(simple_form3_mem_reg( mem, dst ) );
5798 5798 ins_pipe(floadD_mem);
5799 5799 %}
5800 5800
5801 5801 // Load Aligned Packed Char into a Double Register
5802 5802 instruct loadA4C(regD dst, memory mem) %{
5803 5803 match(Set dst (Load4C mem));
5804 5804 ins_cost(MEMORY_REF_COST);
5805 5805 size(4);
5806 5806 format %{ "LDDF $mem,$dst\t! packed4C" %}
5807 5807 opcode(Assembler::lddf_op3);
5808 5808 ins_encode(simple_form3_mem_reg( mem, dst ) );
5809 5809 ins_pipe(floadD_mem);
5810 5810 %}
5811 5811
5812 5812 // Load Aligned Packed Short into a Double Register
5813 5813 instruct loadA4S(regD dst, memory mem) %{
5814 5814 match(Set dst (Load4S mem));
5815 5815 ins_cost(MEMORY_REF_COST);
5816 5816 size(4);
5817 5817 format %{ "LDDF $mem,$dst\t! packed4S" %}
5818 5818 opcode(Assembler::lddf_op3);
5819 5819 ins_encode(simple_form3_mem_reg( mem, dst ) );
5820 5820 ins_pipe(floadD_mem);
5821 5821 %}
5822 5822
5823 5823 // Load Aligned Packed Int into a Double Register
5824 5824 instruct loadA2I(regD dst, memory mem) %{
5825 5825 match(Set dst (Load2I mem));
5826 5826 ins_cost(MEMORY_REF_COST);
5827 5827 size(4);
5828 5828 format %{ "LDDF $mem,$dst\t! packed2I" %}
5829 5829 opcode(Assembler::lddf_op3);
5830 5830 ins_encode(simple_form3_mem_reg( mem, dst ) );
5831 5831 ins_pipe(floadD_mem);
5832 5832 %}
5833 5833
5834 5834 // Load Range
5835 5835 instruct loadRange(iRegI dst, memory mem) %{
5836 5836 match(Set dst (LoadRange mem));
5837 5837 ins_cost(MEMORY_REF_COST);
5838 5838
5839 5839 size(4);
5840 5840 format %{ "LDUW $mem,$dst\t! range" %}
5841 5841 opcode(Assembler::lduw_op3);
5842 5842 ins_encode(simple_form3_mem_reg( mem, dst ) );
5843 5843 ins_pipe(iload_mem);
5844 5844 %}
5845 5845
5846 5846 // Load Integer into %f register (for fitos/fitod)
5847 5847 instruct loadI_freg(regF dst, memory mem) %{
5848 5848 match(Set dst (LoadI mem));
5849 5849 ins_cost(MEMORY_REF_COST);
5850 5850 size(4);
5851 5851
5852 5852 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5853 5853 opcode(Assembler::ldf_op3);
5854 5854 ins_encode(simple_form3_mem_reg( mem, dst ) );
5855 5855 ins_pipe(floadF_mem);
5856 5856 %}
5857 5857
5858 5858 // Load Pointer
5859 5859 instruct loadP(iRegP dst, memory mem) %{
5860 5860 match(Set dst (LoadP mem));
5861 5861 ins_cost(MEMORY_REF_COST);
5862 5862 size(4);
5863 5863
5864 5864 #ifndef _LP64
5865 5865 format %{ "LDUW $mem,$dst\t! ptr" %}
5866 5866 ins_encode %{
5867 5867 __ lduw($mem$$Address, $dst$$Register);
5868 5868 %}
5869 5869 #else
5870 5870 format %{ "LDX $mem,$dst\t! ptr" %}
5871 5871 ins_encode %{
5872 5872 __ ldx($mem$$Address, $dst$$Register);
5873 5873 %}
5874 5874 #endif
5875 5875 ins_pipe(iload_mem);
5876 5876 %}
5877 5877
5878 5878 // Load Compressed Pointer
5879 5879 instruct loadN(iRegN dst, memory mem) %{
5880 5880 match(Set dst (LoadN mem));
5881 5881 ins_cost(MEMORY_REF_COST);
5882 5882 size(4);
5883 5883
5884 5884 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5885 5885 ins_encode %{
5886 5886 __ lduw($mem$$Address, $dst$$Register);
5887 5887 %}
5888 5888 ins_pipe(iload_mem);
5889 5889 %}
5890 5890
5891 5891 // Load Klass Pointer
5892 5892 instruct loadKlass(iRegP dst, memory mem) %{
5893 5893 match(Set dst (LoadKlass mem));
5894 5894 ins_cost(MEMORY_REF_COST);
5895 5895 size(4);
5896 5896
5897 5897 #ifndef _LP64
5898 5898 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5899 5899 ins_encode %{
5900 5900 __ lduw($mem$$Address, $dst$$Register);
5901 5901 %}
5902 5902 #else
5903 5903 format %{ "LDX $mem,$dst\t! klass ptr" %}
5904 5904 ins_encode %{
5905 5905 __ ldx($mem$$Address, $dst$$Register);
5906 5906 %}
5907 5907 #endif
5908 5908 ins_pipe(iload_mem);
5909 5909 %}
5910 5910
5911 5911 // Load narrow Klass Pointer
5912 5912 instruct loadNKlass(iRegN dst, memory mem) %{
5913 5913 match(Set dst (LoadNKlass mem));
5914 5914 ins_cost(MEMORY_REF_COST);
5915 5915 size(4);
5916 5916
5917 5917 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5918 5918 ins_encode %{
5919 5919 __ lduw($mem$$Address, $dst$$Register);
5920 5920 %}
5921 5921 ins_pipe(iload_mem);
5922 5922 %}
5923 5923
5924 5924 // Load Double
5925 5925 instruct loadD(regD dst, memory mem) %{
5926 5926 match(Set dst (LoadD mem));
5927 5927 ins_cost(MEMORY_REF_COST);
5928 5928
5929 5929 size(4);
5930 5930 format %{ "LDDF $mem,$dst" %}
5931 5931 opcode(Assembler::lddf_op3);
5932 5932 ins_encode(simple_form3_mem_reg( mem, dst ) );
5933 5933 ins_pipe(floadD_mem);
5934 5934 %}
5935 5935
5936 5936 // Load Double - UNaligned
5937 5937 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5938 5938 match(Set dst (LoadD_unaligned mem));
5939 5939 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5940 5940 size(8);
5941 5941 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5942 5942 "\tLDF $mem+4,$dst.lo\t!" %}
5943 5943 opcode(Assembler::ldf_op3);
5944 5944 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5945 5945 ins_pipe(iload_mem);
5946 5946 %}
5947 5947
5948 5948 // Load Float
5949 5949 instruct loadF(regF dst, memory mem) %{
5950 5950 match(Set dst (LoadF mem));
5951 5951 ins_cost(MEMORY_REF_COST);
5952 5952
5953 5953 size(4);
5954 5954 format %{ "LDF $mem,$dst" %}
5955 5955 opcode(Assembler::ldf_op3);
5956 5956 ins_encode(simple_form3_mem_reg( mem, dst ) );
5957 5957 ins_pipe(floadF_mem);
5958 5958 %}
5959 5959
5960 5960 // Load Constant
5961 5961 instruct loadConI( iRegI dst, immI src ) %{
5962 5962 match(Set dst src);
5963 5963 ins_cost(DEFAULT_COST * 3/2);
5964 5964 format %{ "SET $src,$dst" %}
5965 5965 ins_encode( Set32(src, dst) );
5966 5966 ins_pipe(ialu_hi_lo_reg);
5967 5967 %}
5968 5968
5969 5969 instruct loadConI13( iRegI dst, immI13 src ) %{
5970 5970 match(Set dst src);
5971 5971
5972 5972 size(4);
5973 5973 format %{ "MOV $src,$dst" %}
5974 5974 ins_encode( Set13( src, dst ) );
5975 5975 ins_pipe(ialu_imm);
5976 5976 %}
5977 5977
5978 5978 instruct loadConP(iRegP dst, immP src) %{
5979 5979 match(Set dst src);
5980 5980 ins_cost(DEFAULT_COST * 3/2);
5981 5981 format %{ "SET $src,$dst\t!ptr" %}
5982 5982 // This rule does not use "expand" unlike loadConI because then
5983 5983 // the result type is not known to be an Oop. An ADLC
5984 5984 // enhancement will be needed to make that work - not worth it!
5985 5985
5986 5986 ins_encode( SetPtr( src, dst ) );
5987 5987 ins_pipe(loadConP);
5988 5988
5989 5989 %}
5990 5990
5991 5991 instruct loadConP0(iRegP dst, immP0 src) %{
5992 5992 match(Set dst src);
5993 5993
5994 5994 size(4);
5995 5995 format %{ "CLR $dst\t!ptr" %}
5996 5996 ins_encode( SetNull( dst ) );
5997 5997 ins_pipe(ialu_imm);
5998 5998 %}
5999 5999
6000 6000 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6001 6001 match(Set dst src);
6002 6002 ins_cost(DEFAULT_COST);
6003 6003 format %{ "SET $src,$dst\t!ptr" %}
6004 6004 ins_encode %{
6005 6005 AddressLiteral polling_page(os::get_polling_page());
6006 6006 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6007 6007 %}
6008 6008 ins_pipe(loadConP_poll);
6009 6009 %}
6010 6010
6011 6011 instruct loadConN0(iRegN dst, immN0 src) %{
6012 6012 match(Set dst src);
6013 6013
6014 6014 size(4);
6015 6015 format %{ "CLR $dst\t! compressed NULL ptr" %}
6016 6016 ins_encode( SetNull( dst ) );
6017 6017 ins_pipe(ialu_imm);
6018 6018 %}
6019 6019
6020 6020 instruct loadConN(iRegN dst, immN src) %{
6021 6021 match(Set dst src);
6022 6022 ins_cost(DEFAULT_COST * 3/2);
6023 6023 format %{ "SET $src,$dst\t! compressed ptr" %}
6024 6024 ins_encode %{
6025 6025 Register dst = $dst$$Register;
6026 6026 __ set_narrow_oop((jobject)$src$$constant, dst);
6027 6027 %}
6028 6028 ins_pipe(ialu_hi_lo_reg);
6029 6029 %}
6030 6030
6031 6031 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6032 6032 // %%% maybe this should work like loadConD
6033 6033 match(Set dst src);
6034 6034 effect(KILL tmp);
6035 6035 ins_cost(DEFAULT_COST * 4);
6036 6036 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6037 6037 ins_encode( LdImmL(src, dst, tmp) );
6038 6038 ins_pipe(loadConL);
6039 6039 %}
6040 6040
6041 6041 instruct loadConL0( iRegL dst, immL0 src ) %{
6042 6042 match(Set dst src);
6043 6043 ins_cost(DEFAULT_COST);
6044 6044 size(4);
6045 6045 format %{ "CLR $dst\t! long" %}
6046 6046 ins_encode( Set13( src, dst ) );
6047 6047 ins_pipe(ialu_imm);
6048 6048 %}
6049 6049
6050 6050 instruct loadConL13( iRegL dst, immL13 src ) %{
6051 6051 match(Set dst src);
6052 6052 ins_cost(DEFAULT_COST * 2);
6053 6053
6054 6054 size(4);
6055 6055 format %{ "MOV $src,$dst\t! long" %}
6056 6056 ins_encode( Set13( src, dst ) );
6057 6057 ins_pipe(ialu_imm);
6058 6058 %}
6059 6059
6060 6060 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6061 6061 match(Set dst src);
6062 6062 effect(KILL tmp);
6063 6063
6064 6064 #ifdef _LP64
6065 6065 size(8*4);
6066 6066 #else
6067 6067 size(2*4);
6068 6068 #endif
6069 6069
6070 6070 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6071 6071 "LDF [$tmp+lo(&$src)],$dst" %}
6072 6072 ins_encode %{
6073 6073 address float_address = __ float_constant($src$$constant);
6074 6074 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6075 6075 AddressLiteral addrlit(float_address, rspec);
6076 6076
6077 6077 __ sethi(addrlit, $tmp$$Register);
6078 6078 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6079 6079 %}
6080 6080 ins_pipe(loadConFD);
6081 6081 %}
6082 6082
6083 6083 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6084 6084 match(Set dst src);
6085 6085 effect(KILL tmp);
6086 6086
6087 6087 #ifdef _LP64
6088 6088 size(8*4);
6089 6089 #else
6090 6090 size(2*4);
6091 6091 #endif
6092 6092
6093 6093 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6094 6094 "LDDF [$tmp+lo(&$src)],$dst" %}
6095 6095 ins_encode %{
6096 6096 address double_address = __ double_constant($src$$constant);
6097 6097 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6098 6098 AddressLiteral addrlit(double_address, rspec);
6099 6099
6100 6100 __ sethi(addrlit, $tmp$$Register);
6101 6101 // XXX This is a quick fix for 6833573.
6102 6102 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6103 6103 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6104 6104 %}
6105 6105 ins_pipe(loadConFD);
6106 6106 %}
6107 6107
6108 6108 // Prefetch instructions.
6109 6109 // Must be safe to execute with invalid address (cannot fault).
6110 6110
6111 6111 instruct prefetchr( memory mem ) %{
6112 6112 match( PrefetchRead mem );
6113 6113 ins_cost(MEMORY_REF_COST);
6114 6114
6115 6115 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6116 6116 opcode(Assembler::prefetch_op3);
6117 6117 ins_encode( form3_mem_prefetch_read( mem ) );
6118 6118 ins_pipe(iload_mem);
6119 6119 %}
6120 6120
6121 6121 instruct prefetchw( memory mem ) %{
6122 6122 predicate(AllocatePrefetchStyle != 3 );
6123 6123 match( PrefetchWrite mem );
6124 6124 ins_cost(MEMORY_REF_COST);
6125 6125
6126 6126 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6127 6127 opcode(Assembler::prefetch_op3);
6128 6128 ins_encode( form3_mem_prefetch_write( mem ) );
6129 6129 ins_pipe(iload_mem);
6130 6130 %}
6131 6131
6132 6132 // Use BIS instruction to prefetch.
6133 6133 instruct prefetchw_bis( memory mem ) %{
6134 6134 predicate(AllocatePrefetchStyle == 3);
6135 6135 match( PrefetchWrite mem );
6136 6136 ins_cost(MEMORY_REF_COST);
6137 6137
6138 6138 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6139 6139 ins_encode %{
6140 6140 Register base = as_Register($mem$$base);
6141 6141 int disp = $mem$$disp;
6142 6142 if (disp != 0) {
6143 6143 __ add(base, AllocatePrefetchStepSize, base);
6144 6144 }
6145 6145 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6146 6146 %}
6147 6147 ins_pipe(istore_mem_reg);
6148 6148 %}
6149 6149
6150 6150 //----------Store Instructions-------------------------------------------------
6151 6151 // Store Byte
6152 6152 instruct storeB(memory mem, iRegI src) %{
6153 6153 match(Set mem (StoreB mem src));
6154 6154 ins_cost(MEMORY_REF_COST);
6155 6155
6156 6156 size(4);
6157 6157 format %{ "STB $src,$mem\t! byte" %}
6158 6158 opcode(Assembler::stb_op3);
6159 6159 ins_encode(simple_form3_mem_reg( mem, src ) );
6160 6160 ins_pipe(istore_mem_reg);
6161 6161 %}
6162 6162
6163 6163 instruct storeB0(memory mem, immI0 src) %{
6164 6164 match(Set mem (StoreB mem src));
6165 6165 ins_cost(MEMORY_REF_COST);
6166 6166
6167 6167 size(4);
6168 6168 format %{ "STB $src,$mem\t! byte" %}
6169 6169 opcode(Assembler::stb_op3);
6170 6170 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6171 6171 ins_pipe(istore_mem_zero);
6172 6172 %}
6173 6173
6174 6174 instruct storeCM0(memory mem, immI0 src) %{
6175 6175 match(Set mem (StoreCM mem src));
6176 6176 ins_cost(MEMORY_REF_COST);
6177 6177
6178 6178 size(4);
6179 6179 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6180 6180 opcode(Assembler::stb_op3);
6181 6181 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6182 6182 ins_pipe(istore_mem_zero);
6183 6183 %}
6184 6184
6185 6185 // Store Char/Short
6186 6186 instruct storeC(memory mem, iRegI src) %{
6187 6187 match(Set mem (StoreC mem src));
6188 6188 ins_cost(MEMORY_REF_COST);
6189 6189
6190 6190 size(4);
6191 6191 format %{ "STH $src,$mem\t! short" %}
6192 6192 opcode(Assembler::sth_op3);
6193 6193 ins_encode(simple_form3_mem_reg( mem, src ) );
6194 6194 ins_pipe(istore_mem_reg);
6195 6195 %}
6196 6196
6197 6197 instruct storeC0(memory mem, immI0 src) %{
6198 6198 match(Set mem (StoreC mem src));
6199 6199 ins_cost(MEMORY_REF_COST);
6200 6200
6201 6201 size(4);
6202 6202 format %{ "STH $src,$mem\t! short" %}
6203 6203 opcode(Assembler::sth_op3);
6204 6204 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6205 6205 ins_pipe(istore_mem_zero);
6206 6206 %}
6207 6207
6208 6208 // Store Integer
6209 6209 instruct storeI(memory mem, iRegI src) %{
6210 6210 match(Set mem (StoreI mem src));
6211 6211 ins_cost(MEMORY_REF_COST);
6212 6212
6213 6213 size(4);
6214 6214 format %{ "STW $src,$mem" %}
6215 6215 opcode(Assembler::stw_op3);
6216 6216 ins_encode(simple_form3_mem_reg( mem, src ) );
6217 6217 ins_pipe(istore_mem_reg);
6218 6218 %}
6219 6219
6220 6220 // Store Long
6221 6221 instruct storeL(memory mem, iRegL src) %{
6222 6222 match(Set mem (StoreL mem src));
6223 6223 ins_cost(MEMORY_REF_COST);
6224 6224 size(4);
6225 6225 format %{ "STX $src,$mem\t! long" %}
6226 6226 opcode(Assembler::stx_op3);
6227 6227 ins_encode(simple_form3_mem_reg( mem, src ) );
6228 6228 ins_pipe(istore_mem_reg);
6229 6229 %}
6230 6230
6231 6231 instruct storeI0(memory mem, immI0 src) %{
6232 6232 match(Set mem (StoreI mem src));
6233 6233 ins_cost(MEMORY_REF_COST);
6234 6234
6235 6235 size(4);
6236 6236 format %{ "STW $src,$mem" %}
6237 6237 opcode(Assembler::stw_op3);
6238 6238 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6239 6239 ins_pipe(istore_mem_zero);
6240 6240 %}
6241 6241
6242 6242 instruct storeL0(memory mem, immL0 src) %{
6243 6243 match(Set mem (StoreL mem src));
6244 6244 ins_cost(MEMORY_REF_COST);
6245 6245
6246 6246 size(4);
6247 6247 format %{ "STX $src,$mem" %}
6248 6248 opcode(Assembler::stx_op3);
6249 6249 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6250 6250 ins_pipe(istore_mem_zero);
6251 6251 %}
6252 6252
6253 6253 // Store Integer from float register (used after fstoi)
6254 6254 instruct storeI_Freg(memory mem, regF src) %{
6255 6255 match(Set mem (StoreI mem src));
6256 6256 ins_cost(MEMORY_REF_COST);
6257 6257
6258 6258 size(4);
6259 6259 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6260 6260 opcode(Assembler::stf_op3);
6261 6261 ins_encode(simple_form3_mem_reg( mem, src ) );
6262 6262 ins_pipe(fstoreF_mem_reg);
6263 6263 %}
6264 6264
6265 6265 // Store Pointer
6266 6266 instruct storeP(memory dst, sp_ptr_RegP src) %{
6267 6267 match(Set dst (StoreP dst src));
6268 6268 ins_cost(MEMORY_REF_COST);
6269 6269 size(4);
6270 6270
6271 6271 #ifndef _LP64
6272 6272 format %{ "STW $src,$dst\t! ptr" %}
6273 6273 opcode(Assembler::stw_op3, 0, REGP_OP);
6274 6274 #else
6275 6275 format %{ "STX $src,$dst\t! ptr" %}
6276 6276 opcode(Assembler::stx_op3, 0, REGP_OP);
6277 6277 #endif
6278 6278 ins_encode( form3_mem_reg( dst, src ) );
6279 6279 ins_pipe(istore_mem_spORreg);
6280 6280 %}
6281 6281
6282 6282 instruct storeP0(memory dst, immP0 src) %{
6283 6283 match(Set dst (StoreP dst src));
6284 6284 ins_cost(MEMORY_REF_COST);
6285 6285 size(4);
6286 6286
6287 6287 #ifndef _LP64
6288 6288 format %{ "STW $src,$dst\t! ptr" %}
6289 6289 opcode(Assembler::stw_op3, 0, REGP_OP);
6290 6290 #else
6291 6291 format %{ "STX $src,$dst\t! ptr" %}
6292 6292 opcode(Assembler::stx_op3, 0, REGP_OP);
6293 6293 #endif
6294 6294 ins_encode( form3_mem_reg( dst, R_G0 ) );
6295 6295 ins_pipe(istore_mem_zero);
6296 6296 %}
6297 6297
6298 6298 // Store Compressed Pointer
6299 6299 instruct storeN(memory dst, iRegN src) %{
6300 6300 match(Set dst (StoreN dst src));
6301 6301 ins_cost(MEMORY_REF_COST);
6302 6302 size(4);
6303 6303
6304 6304 format %{ "STW $src,$dst\t! compressed ptr" %}
6305 6305 ins_encode %{
6306 6306 Register base = as_Register($dst$$base);
6307 6307 Register index = as_Register($dst$$index);
6308 6308 Register src = $src$$Register;
6309 6309 if (index != G0) {
6310 6310 __ stw(src, base, index);
6311 6311 } else {
6312 6312 __ stw(src, base, $dst$$disp);
6313 6313 }
6314 6314 %}
6315 6315 ins_pipe(istore_mem_spORreg);
6316 6316 %}
6317 6317
6318 6318 instruct storeN0(memory dst, immN0 src) %{
6319 6319 match(Set dst (StoreN dst src));
6320 6320 ins_cost(MEMORY_REF_COST);
6321 6321 size(4);
6322 6322
6323 6323 format %{ "STW $src,$dst\t! compressed ptr" %}
6324 6324 ins_encode %{
6325 6325 Register base = as_Register($dst$$base);
6326 6326 Register index = as_Register($dst$$index);
6327 6327 if (index != G0) {
6328 6328 __ stw(0, base, index);
6329 6329 } else {
6330 6330 __ stw(0, base, $dst$$disp);
6331 6331 }
6332 6332 %}
6333 6333 ins_pipe(istore_mem_zero);
6334 6334 %}
6335 6335
6336 6336 // Store Double
6337 6337 instruct storeD( memory mem, regD src) %{
6338 6338 match(Set mem (StoreD mem src));
6339 6339 ins_cost(MEMORY_REF_COST);
6340 6340
6341 6341 size(4);
6342 6342 format %{ "STDF $src,$mem" %}
6343 6343 opcode(Assembler::stdf_op3);
6344 6344 ins_encode(simple_form3_mem_reg( mem, src ) );
6345 6345 ins_pipe(fstoreD_mem_reg);
6346 6346 %}
6347 6347
6348 6348 instruct storeD0( memory mem, immD0 src) %{
6349 6349 match(Set mem (StoreD mem src));
6350 6350 ins_cost(MEMORY_REF_COST);
6351 6351
6352 6352 size(4);
6353 6353 format %{ "STX $src,$mem" %}
6354 6354 opcode(Assembler::stx_op3);
6355 6355 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6356 6356 ins_pipe(fstoreD_mem_zero);
6357 6357 %}
6358 6358
6359 6359 // Store Float
6360 6360 instruct storeF( memory mem, regF src) %{
6361 6361 match(Set mem (StoreF mem src));
6362 6362 ins_cost(MEMORY_REF_COST);
6363 6363
6364 6364 size(4);
6365 6365 format %{ "STF $src,$mem" %}
6366 6366 opcode(Assembler::stf_op3);
6367 6367 ins_encode(simple_form3_mem_reg( mem, src ) );
6368 6368 ins_pipe(fstoreF_mem_reg);
6369 6369 %}
6370 6370
6371 6371 instruct storeF0( memory mem, immF0 src) %{
6372 6372 match(Set mem (StoreF mem src));
6373 6373 ins_cost(MEMORY_REF_COST);
6374 6374
6375 6375 size(4);
6376 6376 format %{ "STW $src,$mem\t! storeF0" %}
6377 6377 opcode(Assembler::stw_op3);
6378 6378 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6379 6379 ins_pipe(fstoreF_mem_zero);
6380 6380 %}
6381 6381
6382 6382 // Store Aligned Packed Bytes in Double register to memory
6383 6383 instruct storeA8B(memory mem, regD src) %{
6384 6384 match(Set mem (Store8B mem src));
6385 6385 ins_cost(MEMORY_REF_COST);
6386 6386 size(4);
6387 6387 format %{ "STDF $src,$mem\t! packed8B" %}
6388 6388 opcode(Assembler::stdf_op3);
6389 6389 ins_encode(simple_form3_mem_reg( mem, src ) );
6390 6390 ins_pipe(fstoreD_mem_reg);
6391 6391 %}
6392 6392
6393 6393 // Convert oop pointer into compressed form
6394 6394 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6395 6395 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6396 6396 match(Set dst (EncodeP src));
6397 6397 format %{ "encode_heap_oop $src, $dst" %}
6398 6398 ins_encode %{
6399 6399 __ encode_heap_oop($src$$Register, $dst$$Register);
6400 6400 %}
6401 6401 ins_pipe(ialu_reg);
6402 6402 %}
6403 6403
6404 6404 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6405 6405 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6406 6406 match(Set dst (EncodeP src));
6407 6407 format %{ "encode_heap_oop_not_null $src, $dst" %}
6408 6408 ins_encode %{
6409 6409 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6410 6410 %}
6411 6411 ins_pipe(ialu_reg);
6412 6412 %}
6413 6413
6414 6414 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6415 6415 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6416 6416 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6417 6417 match(Set dst (DecodeN src));
6418 6418 format %{ "decode_heap_oop $src, $dst" %}
6419 6419 ins_encode %{
6420 6420 __ decode_heap_oop($src$$Register, $dst$$Register);
6421 6421 %}
6422 6422 ins_pipe(ialu_reg);
6423 6423 %}
6424 6424
6425 6425 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6426 6426 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6427 6427 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6428 6428 match(Set dst (DecodeN src));
6429 6429 format %{ "decode_heap_oop_not_null $src, $dst" %}
6430 6430 ins_encode %{
6431 6431 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6432 6432 %}
6433 6433 ins_pipe(ialu_reg);
6434 6434 %}
6435 6435
6436 6436
6437 6437 // Store Zero into Aligned Packed Bytes
6438 6438 instruct storeA8B0(memory mem, immI0 zero) %{
6439 6439 match(Set mem (Store8B mem zero));
6440 6440 ins_cost(MEMORY_REF_COST);
6441 6441 size(4);
6442 6442 format %{ "STX $zero,$mem\t! packed8B" %}
6443 6443 opcode(Assembler::stx_op3);
6444 6444 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6445 6445 ins_pipe(fstoreD_mem_zero);
6446 6446 %}
6447 6447
6448 6448 // Store Aligned Packed Chars/Shorts in Double register to memory
6449 6449 instruct storeA4C(memory mem, regD src) %{
6450 6450 match(Set mem (Store4C mem src));
6451 6451 ins_cost(MEMORY_REF_COST);
6452 6452 size(4);
6453 6453 format %{ "STDF $src,$mem\t! packed4C" %}
6454 6454 opcode(Assembler::stdf_op3);
6455 6455 ins_encode(simple_form3_mem_reg( mem, src ) );
6456 6456 ins_pipe(fstoreD_mem_reg);
6457 6457 %}
6458 6458
6459 6459 // Store Zero into Aligned Packed Chars/Shorts
6460 6460 instruct storeA4C0(memory mem, immI0 zero) %{
6461 6461 match(Set mem (Store4C mem (Replicate4C zero)));
6462 6462 ins_cost(MEMORY_REF_COST);
6463 6463 size(4);
6464 6464 format %{ "STX $zero,$mem\t! packed4C" %}
6465 6465 opcode(Assembler::stx_op3);
6466 6466 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6467 6467 ins_pipe(fstoreD_mem_zero);
6468 6468 %}
6469 6469
6470 6470 // Store Aligned Packed Ints in Double register to memory
6471 6471 instruct storeA2I(memory mem, regD src) %{
6472 6472 match(Set mem (Store2I mem src));
6473 6473 ins_cost(MEMORY_REF_COST);
6474 6474 size(4);
6475 6475 format %{ "STDF $src,$mem\t! packed2I" %}
6476 6476 opcode(Assembler::stdf_op3);
6477 6477 ins_encode(simple_form3_mem_reg( mem, src ) );
6478 6478 ins_pipe(fstoreD_mem_reg);
6479 6479 %}
6480 6480
6481 6481 // Store Zero into Aligned Packed Ints
6482 6482 instruct storeA2I0(memory mem, immI0 zero) %{
6483 6483 match(Set mem (Store2I mem zero));
6484 6484 ins_cost(MEMORY_REF_COST);
6485 6485 size(4);
6486 6486 format %{ "STX $zero,$mem\t! packed2I" %}
6487 6487 opcode(Assembler::stx_op3);
6488 6488 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6489 6489 ins_pipe(fstoreD_mem_zero);
6490 6490 %}
6491 6491
6492 6492
6493 6493 //----------MemBar Instructions-----------------------------------------------
6494 6494 // Memory barrier flavors
6495 6495
6496 6496 instruct membar_acquire() %{
6497 6497 match(MemBarAcquire);
6498 6498 ins_cost(4*MEMORY_REF_COST);
6499 6499
6500 6500 size(0);
6501 6501 format %{ "MEMBAR-acquire" %}
6502 6502 ins_encode( enc_membar_acquire );
6503 6503 ins_pipe(long_memory_op);
6504 6504 %}
6505 6505
6506 6506 instruct membar_acquire_lock() %{
6507 6507 match(MemBarAcquire);
6508 6508 predicate(Matcher::prior_fast_lock(n));
6509 6509 ins_cost(0);
6510 6510
6511 6511 size(0);
6512 6512 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6513 6513 ins_encode( );
6514 6514 ins_pipe(empty);
6515 6515 %}
6516 6516
6517 6517 instruct membar_release() %{
6518 6518 match(MemBarRelease);
6519 6519 ins_cost(4*MEMORY_REF_COST);
6520 6520
6521 6521 size(0);
6522 6522 format %{ "MEMBAR-release" %}
6523 6523 ins_encode( enc_membar_release );
6524 6524 ins_pipe(long_memory_op);
6525 6525 %}
6526 6526
6527 6527 instruct membar_release_lock() %{
6528 6528 match(MemBarRelease);
6529 6529 predicate(Matcher::post_fast_unlock(n));
6530 6530 ins_cost(0);
6531 6531
6532 6532 size(0);
6533 6533 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6534 6534 ins_encode( );
6535 6535 ins_pipe(empty);
6536 6536 %}
6537 6537
6538 6538 instruct membar_volatile() %{
6539 6539 match(MemBarVolatile);
6540 6540 ins_cost(4*MEMORY_REF_COST);
6541 6541
6542 6542 size(4);
6543 6543 format %{ "MEMBAR-volatile" %}
6544 6544 ins_encode( enc_membar_volatile );
6545 6545 ins_pipe(long_memory_op);
6546 6546 %}
6547 6547
6548 6548 instruct unnecessary_membar_volatile() %{
6549 6549 match(MemBarVolatile);
6550 6550 predicate(Matcher::post_store_load_barrier(n));
6551 6551 ins_cost(0);
6552 6552
6553 6553 size(0);
6554 6554 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6555 6555 ins_encode( );
6556 6556 ins_pipe(empty);
6557 6557 %}
6558 6558
6559 6559 //----------Register Move Instructions-----------------------------------------
6560 6560 instruct roundDouble_nop(regD dst) %{
6561 6561 match(Set dst (RoundDouble dst));
6562 6562 ins_cost(0);
6563 6563 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6564 6564 ins_encode( );
6565 6565 ins_pipe(empty);
6566 6566 %}
6567 6567
6568 6568
6569 6569 instruct roundFloat_nop(regF dst) %{
6570 6570 match(Set dst (RoundFloat dst));
6571 6571 ins_cost(0);
6572 6572 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6573 6573 ins_encode( );
6574 6574 ins_pipe(empty);
6575 6575 %}
6576 6576
6577 6577
6578 6578 // Cast Index to Pointer for unsafe natives
6579 6579 instruct castX2P(iRegX src, iRegP dst) %{
6580 6580 match(Set dst (CastX2P src));
6581 6581
6582 6582 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6583 6583 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6584 6584 ins_pipe(ialu_reg);
6585 6585 %}
6586 6586
6587 6587 // Cast Pointer to Index for unsafe natives
6588 6588 instruct castP2X(iRegP src, iRegX dst) %{
6589 6589 match(Set dst (CastP2X src));
6590 6590
6591 6591 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6592 6592 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6593 6593 ins_pipe(ialu_reg);
6594 6594 %}
6595 6595
6596 6596 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6597 6597 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6598 6598 match(Set stkSlot src); // chain rule
6599 6599 ins_cost(MEMORY_REF_COST);
6600 6600 format %{ "STDF $src,$stkSlot\t!stk" %}
6601 6601 opcode(Assembler::stdf_op3);
6602 6602 ins_encode(simple_form3_mem_reg(stkSlot, src));
6603 6603 ins_pipe(fstoreD_stk_reg);
6604 6604 %}
6605 6605
6606 6606 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6607 6607 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6608 6608 match(Set dst stkSlot); // chain rule
6609 6609 ins_cost(MEMORY_REF_COST);
6610 6610 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6611 6611 opcode(Assembler::lddf_op3);
6612 6612 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6613 6613 ins_pipe(floadD_stk);
6614 6614 %}
6615 6615
6616 6616 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6617 6617 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6618 6618 match(Set stkSlot src); // chain rule
6619 6619 ins_cost(MEMORY_REF_COST);
6620 6620 format %{ "STF $src,$stkSlot\t!stk" %}
6621 6621 opcode(Assembler::stf_op3);
6622 6622 ins_encode(simple_form3_mem_reg(stkSlot, src));
6623 6623 ins_pipe(fstoreF_stk_reg);
6624 6624 %}
6625 6625
6626 6626 //----------Conditional Move---------------------------------------------------
6627 6627 // Conditional move
6628 6628 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6629 6629 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6630 6630 ins_cost(150);
6631 6631 format %{ "MOV$cmp $pcc,$src,$dst" %}
6632 6632 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6633 6633 ins_pipe(ialu_reg);
6634 6634 %}
6635 6635
6636 6636 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6637 6637 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6638 6638 ins_cost(140);
6639 6639 format %{ "MOV$cmp $pcc,$src,$dst" %}
6640 6640 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6641 6641 ins_pipe(ialu_imm);
6642 6642 %}
6643 6643
6644 6644 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6645 6645 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6646 6646 ins_cost(150);
6647 6647 size(4);
6648 6648 format %{ "MOV$cmp $icc,$src,$dst" %}
6649 6649 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6650 6650 ins_pipe(ialu_reg);
6651 6651 %}
6652 6652
6653 6653 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6654 6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6655 6655 ins_cost(140);
6656 6656 size(4);
6657 6657 format %{ "MOV$cmp $icc,$src,$dst" %}
6658 6658 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6659 6659 ins_pipe(ialu_imm);
6660 6660 %}
6661 6661
6662 6662 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6663 6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6664 6664 ins_cost(150);
6665 6665 size(4);
6666 6666 format %{ "MOV$cmp $icc,$src,$dst" %}
6667 6667 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6668 6668 ins_pipe(ialu_reg);
6669 6669 %}
6670 6670
6671 6671 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6672 6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6673 6673 ins_cost(140);
6674 6674 size(4);
6675 6675 format %{ "MOV$cmp $icc,$src,$dst" %}
6676 6676 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6677 6677 ins_pipe(ialu_imm);
6678 6678 %}
6679 6679
6680 6680 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6681 6681 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6682 6682 ins_cost(150);
6683 6683 size(4);
6684 6684 format %{ "MOV$cmp $fcc,$src,$dst" %}
6685 6685 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6686 6686 ins_pipe(ialu_reg);
6687 6687 %}
6688 6688
6689 6689 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6690 6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6691 6691 ins_cost(140);
6692 6692 size(4);
6693 6693 format %{ "MOV$cmp $fcc,$src,$dst" %}
6694 6694 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6695 6695 ins_pipe(ialu_imm);
6696 6696 %}
6697 6697
6698 6698 // Conditional move for RegN. Only cmov(reg,reg).
6699 6699 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6700 6700 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6701 6701 ins_cost(150);
6702 6702 format %{ "MOV$cmp $pcc,$src,$dst" %}
6703 6703 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6704 6704 ins_pipe(ialu_reg);
6705 6705 %}
6706 6706
6707 6707 // This instruction also works with CmpN so we don't need cmovNN_reg.
6708 6708 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6709 6709 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6710 6710 ins_cost(150);
6711 6711 size(4);
6712 6712 format %{ "MOV$cmp $icc,$src,$dst" %}
6713 6713 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6714 6714 ins_pipe(ialu_reg);
6715 6715 %}
6716 6716
6717 6717 // This instruction also works with CmpN so we don't need cmovNN_reg.
6718 6718 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6719 6719 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6720 6720 ins_cost(150);
6721 6721 size(4);
6722 6722 format %{ "MOV$cmp $icc,$src,$dst" %}
6723 6723 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6724 6724 ins_pipe(ialu_reg);
6725 6725 %}
6726 6726
6727 6727 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6728 6728 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6729 6729 ins_cost(150);
6730 6730 size(4);
6731 6731 format %{ "MOV$cmp $fcc,$src,$dst" %}
6732 6732 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6733 6733 ins_pipe(ialu_reg);
6734 6734 %}
6735 6735
6736 6736 // Conditional move
6737 6737 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6738 6738 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6739 6739 ins_cost(150);
6740 6740 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6741 6741 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6742 6742 ins_pipe(ialu_reg);
6743 6743 %}
6744 6744
6745 6745 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6746 6746 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6747 6747 ins_cost(140);
6748 6748 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6749 6749 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6750 6750 ins_pipe(ialu_imm);
6751 6751 %}
6752 6752
6753 6753 // This instruction also works with CmpN so we don't need cmovPN_reg.
6754 6754 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6755 6755 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6756 6756 ins_cost(150);
6757 6757
6758 6758 size(4);
6759 6759 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6760 6760 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6761 6761 ins_pipe(ialu_reg);
6762 6762 %}
6763 6763
6764 6764 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6765 6765 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6766 6766 ins_cost(150);
6767 6767
6768 6768 size(4);
6769 6769 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6770 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6771 6771 ins_pipe(ialu_reg);
6772 6772 %}
6773 6773
6774 6774 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6775 6775 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6776 6776 ins_cost(140);
6777 6777
6778 6778 size(4);
6779 6779 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6780 6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6781 6781 ins_pipe(ialu_imm);
6782 6782 %}
6783 6783
6784 6784 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6785 6785 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6786 6786 ins_cost(140);
6787 6787
6788 6788 size(4);
6789 6789 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6790 6790 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6791 6791 ins_pipe(ialu_imm);
6792 6792 %}
6793 6793
6794 6794 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6795 6795 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6796 6796 ins_cost(150);
6797 6797 size(4);
6798 6798 format %{ "MOV$cmp $fcc,$src,$dst" %}
6799 6799 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6800 6800 ins_pipe(ialu_imm);
6801 6801 %}
6802 6802
6803 6803 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6804 6804 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6805 6805 ins_cost(140);
6806 6806 size(4);
6807 6807 format %{ "MOV$cmp $fcc,$src,$dst" %}
6808 6808 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6809 6809 ins_pipe(ialu_imm);
6810 6810 %}
6811 6811
6812 6812 // Conditional move
6813 6813 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6814 6814 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6815 6815 ins_cost(150);
6816 6816 opcode(0x101);
6817 6817 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6818 6818 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6819 6819 ins_pipe(int_conditional_float_move);
6820 6820 %}
6821 6821
6822 6822 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6823 6823 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6824 6824 ins_cost(150);
6825 6825
6826 6826 size(4);
6827 6827 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6828 6828 opcode(0x101);
6829 6829 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6830 6830 ins_pipe(int_conditional_float_move);
6831 6831 %}
6832 6832
6833 6833 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6834 6834 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6835 6835 ins_cost(150);
6836 6836
6837 6837 size(4);
6838 6838 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6839 6839 opcode(0x101);
6840 6840 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6841 6841 ins_pipe(int_conditional_float_move);
6842 6842 %}
6843 6843
6844 6844 // Conditional move,
6845 6845 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6846 6846 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6847 6847 ins_cost(150);
6848 6848 size(4);
6849 6849 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6850 6850 opcode(0x1);
6851 6851 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6852 6852 ins_pipe(int_conditional_double_move);
6853 6853 %}
6854 6854
6855 6855 // Conditional move
6856 6856 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6857 6857 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6858 6858 ins_cost(150);
6859 6859 size(4);
6860 6860 opcode(0x102);
6861 6861 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6862 6862 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6863 6863 ins_pipe(int_conditional_double_move);
6864 6864 %}
6865 6865
6866 6866 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6867 6867 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6868 6868 ins_cost(150);
6869 6869
6870 6870 size(4);
6871 6871 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6872 6872 opcode(0x102);
6873 6873 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6874 6874 ins_pipe(int_conditional_double_move);
6875 6875 %}
6876 6876
6877 6877 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6878 6878 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6879 6879 ins_cost(150);
6880 6880
6881 6881 size(4);
6882 6882 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6883 6883 opcode(0x102);
6884 6884 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6885 6885 ins_pipe(int_conditional_double_move);
6886 6886 %}
6887 6887
6888 6888 // Conditional move,
6889 6889 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6890 6890 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6891 6891 ins_cost(150);
6892 6892 size(4);
6893 6893 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6894 6894 opcode(0x2);
6895 6895 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6896 6896 ins_pipe(int_conditional_double_move);
6897 6897 %}
6898 6898
6899 6899 // Conditional move
6900 6900 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6901 6901 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6902 6902 ins_cost(150);
6903 6903 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6904 6904 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6905 6905 ins_pipe(ialu_reg);
6906 6906 %}
6907 6907
6908 6908 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6909 6909 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6910 6910 ins_cost(140);
6911 6911 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6912 6912 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6913 6913 ins_pipe(ialu_imm);
6914 6914 %}
6915 6915
6916 6916 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6917 6917 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6918 6918 ins_cost(150);
6919 6919
6920 6920 size(4);
6921 6921 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6922 6922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6923 6923 ins_pipe(ialu_reg);
6924 6924 %}
6925 6925
6926 6926
6927 6927 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6928 6928 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6929 6929 ins_cost(150);
6930 6930
6931 6931 size(4);
6932 6932 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6933 6933 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6934 6934 ins_pipe(ialu_reg);
6935 6935 %}
6936 6936
6937 6937
6938 6938 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6939 6939 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6940 6940 ins_cost(150);
6941 6941
6942 6942 size(4);
6943 6943 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6944 6944 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6945 6945 ins_pipe(ialu_reg);
6946 6946 %}
6947 6947
6948 6948
6949 6949
6950 6950 //----------OS and Locking Instructions----------------------------------------
6951 6951
6952 6952 // This name is KNOWN by the ADLC and cannot be changed.
6953 6953 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6954 6954 // for this guy.
6955 6955 instruct tlsLoadP(g2RegP dst) %{
6956 6956 match(Set dst (ThreadLocal));
6957 6957
6958 6958 size(0);
6959 6959 ins_cost(0);
6960 6960 format %{ "# TLS is in G2" %}
6961 6961 ins_encode( /*empty encoding*/ );
6962 6962 ins_pipe(ialu_none);
6963 6963 %}
6964 6964
6965 6965 instruct checkCastPP( iRegP dst ) %{
6966 6966 match(Set dst (CheckCastPP dst));
6967 6967
6968 6968 size(0);
6969 6969 format %{ "# checkcastPP of $dst" %}
6970 6970 ins_encode( /*empty encoding*/ );
6971 6971 ins_pipe(empty);
6972 6972 %}
6973 6973
6974 6974
6975 6975 instruct castPP( iRegP dst ) %{
6976 6976 match(Set dst (CastPP dst));
6977 6977 format %{ "# castPP of $dst" %}
6978 6978 ins_encode( /*empty encoding*/ );
6979 6979 ins_pipe(empty);
6980 6980 %}
6981 6981
6982 6982 instruct castII( iRegI dst ) %{
6983 6983 match(Set dst (CastII dst));
6984 6984 format %{ "# castII of $dst" %}
6985 6985 ins_encode( /*empty encoding*/ );
6986 6986 ins_cost(0);
6987 6987 ins_pipe(empty);
6988 6988 %}
6989 6989
6990 6990 //----------Arithmetic Instructions--------------------------------------------
6991 6991 // Addition Instructions
6992 6992 // Register Addition
6993 6993 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6994 6994 match(Set dst (AddI src1 src2));
6995 6995
6996 6996 size(4);
6997 6997 format %{ "ADD $src1,$src2,$dst" %}
6998 6998 ins_encode %{
6999 6999 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7000 7000 %}
7001 7001 ins_pipe(ialu_reg_reg);
7002 7002 %}
7003 7003
7004 7004 // Immediate Addition
7005 7005 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7006 7006 match(Set dst (AddI src1 src2));
7007 7007
7008 7008 size(4);
7009 7009 format %{ "ADD $src1,$src2,$dst" %}
7010 7010 opcode(Assembler::add_op3, Assembler::arith_op);
7011 7011 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7012 7012 ins_pipe(ialu_reg_imm);
7013 7013 %}
7014 7014
7015 7015 // Pointer Register Addition
7016 7016 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7017 7017 match(Set dst (AddP src1 src2));
7018 7018
7019 7019 size(4);
7020 7020 format %{ "ADD $src1,$src2,$dst" %}
7021 7021 opcode(Assembler::add_op3, Assembler::arith_op);
7022 7022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7023 7023 ins_pipe(ialu_reg_reg);
7024 7024 %}
7025 7025
7026 7026 // Pointer Immediate Addition
7027 7027 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7028 7028 match(Set dst (AddP src1 src2));
7029 7029
7030 7030 size(4);
7031 7031 format %{ "ADD $src1,$src2,$dst" %}
7032 7032 opcode(Assembler::add_op3, Assembler::arith_op);
7033 7033 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7034 7034 ins_pipe(ialu_reg_imm);
7035 7035 %}
7036 7036
7037 7037 // Long Addition
7038 7038 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7039 7039 match(Set dst (AddL src1 src2));
7040 7040
7041 7041 size(4);
7042 7042 format %{ "ADD $src1,$src2,$dst\t! long" %}
7043 7043 opcode(Assembler::add_op3, Assembler::arith_op);
7044 7044 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7045 7045 ins_pipe(ialu_reg_reg);
7046 7046 %}
7047 7047
7048 7048 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7049 7049 match(Set dst (AddL src1 con));
7050 7050
7051 7051 size(4);
7052 7052 format %{ "ADD $src1,$con,$dst" %}
7053 7053 opcode(Assembler::add_op3, Assembler::arith_op);
7054 7054 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7055 7055 ins_pipe(ialu_reg_imm);
7056 7056 %}
7057 7057
7058 7058 //----------Conditional_store--------------------------------------------------
7059 7059 // Conditional-store of the updated heap-top.
7060 7060 // Used during allocation of the shared heap.
7061 7061 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7062 7062
7063 7063 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7064 7064 instruct loadPLocked(iRegP dst, memory mem) %{
7065 7065 match(Set dst (LoadPLocked mem));
7066 7066 ins_cost(MEMORY_REF_COST);
7067 7067
7068 7068 #ifndef _LP64
7069 7069 size(4);
7070 7070 format %{ "LDUW $mem,$dst\t! ptr" %}
7071 7071 opcode(Assembler::lduw_op3, 0, REGP_OP);
7072 7072 #else
7073 7073 format %{ "LDX $mem,$dst\t! ptr" %}
7074 7074 opcode(Assembler::ldx_op3, 0, REGP_OP);
7075 7075 #endif
7076 7076 ins_encode( form3_mem_reg( mem, dst ) );
7077 7077 ins_pipe(iload_mem);
7078 7078 %}
7079 7079
7080 7080 // LoadL-locked. Same as a regular long load when used with a compare-swap
7081 7081 instruct loadLLocked(iRegL dst, memory mem) %{
7082 7082 match(Set dst (LoadLLocked mem));
7083 7083 ins_cost(MEMORY_REF_COST);
7084 7084 size(4);
7085 7085 format %{ "LDX $mem,$dst\t! long" %}
7086 7086 opcode(Assembler::ldx_op3);
7087 7087 ins_encode(simple_form3_mem_reg( mem, dst ) );
7088 7088 ins_pipe(iload_mem);
7089 7089 %}
7090 7090
7091 7091 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7092 7092 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7093 7093 effect( KILL newval );
7094 7094 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7095 7095 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7096 7096 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7097 7097 ins_pipe( long_memory_op );
7098 7098 %}
7099 7099
7100 7100 // Conditional-store of an int value.
7101 7101 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7102 7102 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7103 7103 effect( KILL newval );
7104 7104 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7105 7105 "CMP $oldval,$newval\t\t! See if we made progress" %}
7106 7106 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7107 7107 ins_pipe( long_memory_op );
7108 7108 %}
7109 7109
7110 7110 // Conditional-store of a long value.
7111 7111 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7112 7112 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7113 7113 effect( KILL newval );
7114 7114 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7115 7115 "CMP $oldval,$newval\t\t! See if we made progress" %}
7116 7116 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7117 7117 ins_pipe( long_memory_op );
7118 7118 %}
7119 7119
7120 7120 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7121 7121
7122 7122 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7123 7123 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7124 7124 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7125 7125 format %{
7126 7126 "MOV $newval,O7\n\t"
7127 7127 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7128 7128 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7129 7129 "MOV 1,$res\n\t"
7130 7130 "MOVne xcc,R_G0,$res"
7131 7131 %}
7132 7132 ins_encode( enc_casx(mem_ptr, oldval, newval),
7133 7133 enc_lflags_ne_to_boolean(res) );
7134 7134 ins_pipe( long_memory_op );
7135 7135 %}
7136 7136
7137 7137
7138 7138 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7139 7139 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7140 7140 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7141 7141 format %{
7142 7142 "MOV $newval,O7\n\t"
7143 7143 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7144 7144 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7145 7145 "MOV 1,$res\n\t"
7146 7146 "MOVne icc,R_G0,$res"
7147 7147 %}
7148 7148 ins_encode( enc_casi(mem_ptr, oldval, newval),
7149 7149 enc_iflags_ne_to_boolean(res) );
7150 7150 ins_pipe( long_memory_op );
7151 7151 %}
7152 7152
7153 7153 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7154 7154 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7155 7155 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7156 7156 format %{
7157 7157 "MOV $newval,O7\n\t"
7158 7158 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7159 7159 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7160 7160 "MOV 1,$res\n\t"
7161 7161 "MOVne xcc,R_G0,$res"
7162 7162 %}
7163 7163 #ifdef _LP64
7164 7164 ins_encode( enc_casx(mem_ptr, oldval, newval),
7165 7165 enc_lflags_ne_to_boolean(res) );
7166 7166 #else
7167 7167 ins_encode( enc_casi(mem_ptr, oldval, newval),
7168 7168 enc_iflags_ne_to_boolean(res) );
7169 7169 #endif
7170 7170 ins_pipe( long_memory_op );
7171 7171 %}
7172 7172
7173 7173 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7174 7174 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7175 7175 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7176 7176 format %{
7177 7177 "MOV $newval,O7\n\t"
7178 7178 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7179 7179 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7180 7180 "MOV 1,$res\n\t"
7181 7181 "MOVne icc,R_G0,$res"
7182 7182 %}
7183 7183 ins_encode( enc_casi(mem_ptr, oldval, newval),
7184 7184 enc_iflags_ne_to_boolean(res) );
7185 7185 ins_pipe( long_memory_op );
7186 7186 %}
7187 7187
7188 7188 //---------------------
7189 7189 // Subtraction Instructions
7190 7190 // Register Subtraction
7191 7191 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7192 7192 match(Set dst (SubI src1 src2));
7193 7193
7194 7194 size(4);
7195 7195 format %{ "SUB $src1,$src2,$dst" %}
7196 7196 opcode(Assembler::sub_op3, Assembler::arith_op);
7197 7197 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7198 7198 ins_pipe(ialu_reg_reg);
7199 7199 %}
7200 7200
7201 7201 // Immediate Subtraction
7202 7202 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7203 7203 match(Set dst (SubI src1 src2));
7204 7204
7205 7205 size(4);
7206 7206 format %{ "SUB $src1,$src2,$dst" %}
7207 7207 opcode(Assembler::sub_op3, Assembler::arith_op);
7208 7208 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7209 7209 ins_pipe(ialu_reg_imm);
7210 7210 %}
7211 7211
7212 7212 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7213 7213 match(Set dst (SubI zero src2));
7214 7214
7215 7215 size(4);
7216 7216 format %{ "NEG $src2,$dst" %}
7217 7217 opcode(Assembler::sub_op3, Assembler::arith_op);
7218 7218 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7219 7219 ins_pipe(ialu_zero_reg);
7220 7220 %}
7221 7221
7222 7222 // Long subtraction
7223 7223 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7224 7224 match(Set dst (SubL src1 src2));
7225 7225
7226 7226 size(4);
7227 7227 format %{ "SUB $src1,$src2,$dst\t! long" %}
7228 7228 opcode(Assembler::sub_op3, Assembler::arith_op);
7229 7229 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7230 7230 ins_pipe(ialu_reg_reg);
7231 7231 %}
7232 7232
7233 7233 // Immediate Subtraction
7234 7234 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7235 7235 match(Set dst (SubL src1 con));
7236 7236
7237 7237 size(4);
7238 7238 format %{ "SUB $src1,$con,$dst\t! long" %}
7239 7239 opcode(Assembler::sub_op3, Assembler::arith_op);
7240 7240 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7241 7241 ins_pipe(ialu_reg_imm);
7242 7242 %}
7243 7243
7244 7244 // Long negation
7245 7245 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7246 7246 match(Set dst (SubL zero src2));
7247 7247
7248 7248 size(4);
7249 7249 format %{ "NEG $src2,$dst\t! long" %}
7250 7250 opcode(Assembler::sub_op3, Assembler::arith_op);
7251 7251 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7252 7252 ins_pipe(ialu_zero_reg);
7253 7253 %}
7254 7254
7255 7255 // Multiplication Instructions
7256 7256 // Integer Multiplication
7257 7257 // Register Multiplication
7258 7258 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7259 7259 match(Set dst (MulI src1 src2));
7260 7260
7261 7261 size(4);
7262 7262 format %{ "MULX $src1,$src2,$dst" %}
7263 7263 opcode(Assembler::mulx_op3, Assembler::arith_op);
7264 7264 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7265 7265 ins_pipe(imul_reg_reg);
7266 7266 %}
7267 7267
7268 7268 // Immediate Multiplication
7269 7269 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7270 7270 match(Set dst (MulI src1 src2));
7271 7271
7272 7272 size(4);
7273 7273 format %{ "MULX $src1,$src2,$dst" %}
7274 7274 opcode(Assembler::mulx_op3, Assembler::arith_op);
7275 7275 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7276 7276 ins_pipe(imul_reg_imm);
7277 7277 %}
7278 7278
7279 7279 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7280 7280 match(Set dst (MulL src1 src2));
7281 7281 ins_cost(DEFAULT_COST * 5);
7282 7282 size(4);
7283 7283 format %{ "MULX $src1,$src2,$dst\t! long" %}
7284 7284 opcode(Assembler::mulx_op3, Assembler::arith_op);
7285 7285 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7286 7286 ins_pipe(mulL_reg_reg);
7287 7287 %}
7288 7288
7289 7289 // Immediate Multiplication
7290 7290 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7291 7291 match(Set dst (MulL src1 src2));
7292 7292 ins_cost(DEFAULT_COST * 5);
7293 7293 size(4);
7294 7294 format %{ "MULX $src1,$src2,$dst" %}
7295 7295 opcode(Assembler::mulx_op3, Assembler::arith_op);
7296 7296 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7297 7297 ins_pipe(mulL_reg_imm);
7298 7298 %}
7299 7299
7300 7300 // Integer Division
7301 7301 // Register Division
7302 7302 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7303 7303 match(Set dst (DivI src1 src2));
7304 7304 ins_cost((2+71)*DEFAULT_COST);
7305 7305
7306 7306 format %{ "SRA $src2,0,$src2\n\t"
7307 7307 "SRA $src1,0,$src1\n\t"
7308 7308 "SDIVX $src1,$src2,$dst" %}
7309 7309 ins_encode( idiv_reg( src1, src2, dst ) );
7310 7310 ins_pipe(sdiv_reg_reg);
7311 7311 %}
7312 7312
7313 7313 // Immediate Division
7314 7314 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7315 7315 match(Set dst (DivI src1 src2));
7316 7316 ins_cost((2+71)*DEFAULT_COST);
7317 7317
7318 7318 format %{ "SRA $src1,0,$src1\n\t"
7319 7319 "SDIVX $src1,$src2,$dst" %}
7320 7320 ins_encode( idiv_imm( src1, src2, dst ) );
7321 7321 ins_pipe(sdiv_reg_imm);
7322 7322 %}
7323 7323
7324 7324 //----------Div-By-10-Expansion------------------------------------------------
7325 7325 // Extract hi bits of a 32x32->64 bit multiply.
7326 7326 // Expand rule only, not matched
7327 7327 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7328 7328 effect( DEF dst, USE src1, USE src2 );
7329 7329 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7330 7330 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7331 7331 ins_encode( enc_mul_hi(dst,src1,src2));
7332 7332 ins_pipe(sdiv_reg_reg);
7333 7333 %}
7334 7334
7335 7335 // Magic constant, reciprocal of 10
7336 7336 instruct loadConI_x66666667(iRegIsafe dst) %{
7337 7337 effect( DEF dst );
7338 7338
7339 7339 size(8);
7340 7340 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7341 7341 ins_encode( Set32(0x66666667, dst) );
7342 7342 ins_pipe(ialu_hi_lo_reg);
7343 7343 %}
7344 7344
7345 7345 // Register Shift Right Arithmetic Long by 32-63
7346 7346 instruct sra_31( iRegI dst, iRegI src ) %{
7347 7347 effect( DEF dst, USE src );
7348 7348 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7349 7349 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7350 7350 ins_pipe(ialu_reg_reg);
7351 7351 %}
7352 7352
7353 7353 // Arithmetic Shift Right by 8-bit immediate
7354 7354 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7355 7355 effect( DEF dst, USE src );
7356 7356 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7357 7357 opcode(Assembler::sra_op3, Assembler::arith_op);
7358 7358 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7359 7359 ins_pipe(ialu_reg_imm);
7360 7360 %}
7361 7361
7362 7362 // Integer DIV with 10
7363 7363 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7364 7364 match(Set dst (DivI src div));
7365 7365 ins_cost((6+6)*DEFAULT_COST);
7366 7366 expand %{
7367 7367 iRegIsafe tmp1; // Killed temps;
7368 7368 iRegIsafe tmp2; // Killed temps;
7369 7369 iRegI tmp3; // Killed temps;
7370 7370 iRegI tmp4; // Killed temps;
7371 7371 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7372 7372 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7373 7373 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7374 7374 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7375 7375 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7376 7376 %}
7377 7377 %}
7378 7378
7379 7379 // Register Long Division
7380 7380 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7381 7381 match(Set dst (DivL src1 src2));
7382 7382 ins_cost(DEFAULT_COST*71);
7383 7383 size(4);
7384 7384 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7385 7385 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7386 7386 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7387 7387 ins_pipe(divL_reg_reg);
7388 7388 %}
7389 7389
7390 7390 // Register Long Division
7391 7391 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7392 7392 match(Set dst (DivL src1 src2));
7393 7393 ins_cost(DEFAULT_COST*71);
7394 7394 size(4);
7395 7395 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7396 7396 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7397 7397 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7398 7398 ins_pipe(divL_reg_imm);
7399 7399 %}
7400 7400
7401 7401 // Integer Remainder
7402 7402 // Register Remainder
7403 7403 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7404 7404 match(Set dst (ModI src1 src2));
7405 7405 effect( KILL ccr, KILL temp);
7406 7406
7407 7407 format %{ "SREM $src1,$src2,$dst" %}
7408 7408 ins_encode( irem_reg(src1, src2, dst, temp) );
7409 7409 ins_pipe(sdiv_reg_reg);
7410 7410 %}
7411 7411
7412 7412 // Immediate Remainder
7413 7413 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7414 7414 match(Set dst (ModI src1 src2));
7415 7415 effect( KILL ccr, KILL temp);
7416 7416
7417 7417 format %{ "SREM $src1,$src2,$dst" %}
7418 7418 ins_encode( irem_imm(src1, src2, dst, temp) );
7419 7419 ins_pipe(sdiv_reg_imm);
7420 7420 %}
7421 7421
7422 7422 // Register Long Remainder
7423 7423 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7424 7424 effect(DEF dst, USE src1, USE src2);
7425 7425 size(4);
7426 7426 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7427 7427 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7428 7428 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7429 7429 ins_pipe(divL_reg_reg);
7430 7430 %}
7431 7431
7432 7432 // Register Long Division
7433 7433 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7434 7434 effect(DEF dst, USE src1, USE src2);
7435 7435 size(4);
7436 7436 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7437 7437 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7438 7438 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7439 7439 ins_pipe(divL_reg_imm);
7440 7440 %}
7441 7441
7442 7442 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7443 7443 effect(DEF dst, USE src1, USE src2);
7444 7444 size(4);
7445 7445 format %{ "MULX $src1,$src2,$dst\t! long" %}
7446 7446 opcode(Assembler::mulx_op3, Assembler::arith_op);
7447 7447 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7448 7448 ins_pipe(mulL_reg_reg);
7449 7449 %}
7450 7450
7451 7451 // Immediate Multiplication
7452 7452 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7453 7453 effect(DEF dst, USE src1, USE src2);
7454 7454 size(4);
7455 7455 format %{ "MULX $src1,$src2,$dst" %}
7456 7456 opcode(Assembler::mulx_op3, Assembler::arith_op);
7457 7457 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7458 7458 ins_pipe(mulL_reg_imm);
7459 7459 %}
7460 7460
7461 7461 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7462 7462 effect(DEF dst, USE src1, USE src2);
7463 7463 size(4);
7464 7464 format %{ "SUB $src1,$src2,$dst\t! long" %}
7465 7465 opcode(Assembler::sub_op3, Assembler::arith_op);
7466 7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7467 7467 ins_pipe(ialu_reg_reg);
7468 7468 %}
7469 7469
7470 7470 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7471 7471 effect(DEF dst, USE src1, USE src2);
7472 7472 size(4);
7473 7473 format %{ "SUB $src1,$src2,$dst\t! long" %}
7474 7474 opcode(Assembler::sub_op3, Assembler::arith_op);
7475 7475 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7476 7476 ins_pipe(ialu_reg_reg);
7477 7477 %}
7478 7478
7479 7479 // Register Long Remainder
7480 7480 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7481 7481 match(Set dst (ModL src1 src2));
7482 7482 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7483 7483 expand %{
7484 7484 iRegL tmp1;
7485 7485 iRegL tmp2;
7486 7486 divL_reg_reg_1(tmp1, src1, src2);
7487 7487 mulL_reg_reg_1(tmp2, tmp1, src2);
7488 7488 subL_reg_reg_1(dst, src1, tmp2);
7489 7489 %}
7490 7490 %}
7491 7491
7492 7492 // Register Long Remainder
7493 7493 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7494 7494 match(Set dst (ModL src1 src2));
7495 7495 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7496 7496 expand %{
7497 7497 iRegL tmp1;
7498 7498 iRegL tmp2;
7499 7499 divL_reg_imm13_1(tmp1, src1, src2);
7500 7500 mulL_reg_imm13_1(tmp2, tmp1, src2);
7501 7501 subL_reg_reg_2 (dst, src1, tmp2);
7502 7502 %}
7503 7503 %}
7504 7504
7505 7505 // Integer Shift Instructions
7506 7506 // Register Shift Left
7507 7507 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7508 7508 match(Set dst (LShiftI src1 src2));
7509 7509
7510 7510 size(4);
7511 7511 format %{ "SLL $src1,$src2,$dst" %}
7512 7512 opcode(Assembler::sll_op3, Assembler::arith_op);
7513 7513 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7514 7514 ins_pipe(ialu_reg_reg);
7515 7515 %}
7516 7516
7517 7517 // Register Shift Left Immediate
7518 7518 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7519 7519 match(Set dst (LShiftI src1 src2));
7520 7520
7521 7521 size(4);
7522 7522 format %{ "SLL $src1,$src2,$dst" %}
7523 7523 opcode(Assembler::sll_op3, Assembler::arith_op);
7524 7524 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7525 7525 ins_pipe(ialu_reg_imm);
7526 7526 %}
7527 7527
7528 7528 // Register Shift Left
7529 7529 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7530 7530 match(Set dst (LShiftL src1 src2));
7531 7531
7532 7532 size(4);
7533 7533 format %{ "SLLX $src1,$src2,$dst" %}
7534 7534 opcode(Assembler::sllx_op3, Assembler::arith_op);
7535 7535 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7536 7536 ins_pipe(ialu_reg_reg);
7537 7537 %}
7538 7538
7539 7539 // Register Shift Left Immediate
7540 7540 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7541 7541 match(Set dst (LShiftL src1 src2));
7542 7542
7543 7543 size(4);
7544 7544 format %{ "SLLX $src1,$src2,$dst" %}
7545 7545 opcode(Assembler::sllx_op3, Assembler::arith_op);
7546 7546 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7547 7547 ins_pipe(ialu_reg_imm);
7548 7548 %}
7549 7549
7550 7550 // Register Arithmetic Shift Right
7551 7551 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7552 7552 match(Set dst (RShiftI src1 src2));
7553 7553 size(4);
7554 7554 format %{ "SRA $src1,$src2,$dst" %}
7555 7555 opcode(Assembler::sra_op3, Assembler::arith_op);
7556 7556 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7557 7557 ins_pipe(ialu_reg_reg);
7558 7558 %}
7559 7559
7560 7560 // Register Arithmetic Shift Right Immediate
7561 7561 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7562 7562 match(Set dst (RShiftI src1 src2));
7563 7563
7564 7564 size(4);
7565 7565 format %{ "SRA $src1,$src2,$dst" %}
7566 7566 opcode(Assembler::sra_op3, Assembler::arith_op);
7567 7567 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7568 7568 ins_pipe(ialu_reg_imm);
7569 7569 %}
7570 7570
7571 7571 // Register Shift Right Arithmatic Long
7572 7572 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7573 7573 match(Set dst (RShiftL src1 src2));
7574 7574
7575 7575 size(4);
7576 7576 format %{ "SRAX $src1,$src2,$dst" %}
7577 7577 opcode(Assembler::srax_op3, Assembler::arith_op);
7578 7578 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7579 7579 ins_pipe(ialu_reg_reg);
7580 7580 %}
7581 7581
7582 7582 // Register Shift Left Immediate
7583 7583 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7584 7584 match(Set dst (RShiftL src1 src2));
7585 7585
7586 7586 size(4);
7587 7587 format %{ "SRAX $src1,$src2,$dst" %}
7588 7588 opcode(Assembler::srax_op3, Assembler::arith_op);
7589 7589 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7590 7590 ins_pipe(ialu_reg_imm);
7591 7591 %}
7592 7592
7593 7593 // Register Shift Right
7594 7594 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7595 7595 match(Set dst (URShiftI src1 src2));
7596 7596
7597 7597 size(4);
7598 7598 format %{ "SRL $src1,$src2,$dst" %}
7599 7599 opcode(Assembler::srl_op3, Assembler::arith_op);
7600 7600 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7601 7601 ins_pipe(ialu_reg_reg);
7602 7602 %}
7603 7603
7604 7604 // Register Shift Right Immediate
7605 7605 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7606 7606 match(Set dst (URShiftI src1 src2));
7607 7607
7608 7608 size(4);
7609 7609 format %{ "SRL $src1,$src2,$dst" %}
7610 7610 opcode(Assembler::srl_op3, Assembler::arith_op);
7611 7611 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7612 7612 ins_pipe(ialu_reg_imm);
7613 7613 %}
7614 7614
7615 7615 // Register Shift Right
7616 7616 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7617 7617 match(Set dst (URShiftL src1 src2));
7618 7618
7619 7619 size(4);
7620 7620 format %{ "SRLX $src1,$src2,$dst" %}
7621 7621 opcode(Assembler::srlx_op3, Assembler::arith_op);
7622 7622 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7623 7623 ins_pipe(ialu_reg_reg);
7624 7624 %}
7625 7625
7626 7626 // Register Shift Right Immediate
7627 7627 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7628 7628 match(Set dst (URShiftL src1 src2));
7629 7629
7630 7630 size(4);
7631 7631 format %{ "SRLX $src1,$src2,$dst" %}
7632 7632 opcode(Assembler::srlx_op3, Assembler::arith_op);
7633 7633 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7634 7634 ins_pipe(ialu_reg_imm);
7635 7635 %}
7636 7636
7637 7637 // Register Shift Right Immediate with a CastP2X
7638 7638 #ifdef _LP64
7639 7639 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7640 7640 match(Set dst (URShiftL (CastP2X src1) src2));
7641 7641 size(4);
7642 7642 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7643 7643 opcode(Assembler::srlx_op3, Assembler::arith_op);
7644 7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7645 7645 ins_pipe(ialu_reg_imm);
7646 7646 %}
7647 7647 #else
7648 7648 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7649 7649 match(Set dst (URShiftI (CastP2X src1) src2));
7650 7650 size(4);
7651 7651 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7652 7652 opcode(Assembler::srl_op3, Assembler::arith_op);
7653 7653 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7654 7654 ins_pipe(ialu_reg_imm);
7655 7655 %}
7656 7656 #endif
7657 7657
7658 7658
7659 7659 //----------Floating Point Arithmetic Instructions-----------------------------
7660 7660
7661 7661 // Add float single precision
7662 7662 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7663 7663 match(Set dst (AddF src1 src2));
7664 7664
7665 7665 size(4);
7666 7666 format %{ "FADDS $src1,$src2,$dst" %}
7667 7667 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7668 7668 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7669 7669 ins_pipe(faddF_reg_reg);
7670 7670 %}
7671 7671
7672 7672 // Add float double precision
7673 7673 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7674 7674 match(Set dst (AddD src1 src2));
7675 7675
7676 7676 size(4);
7677 7677 format %{ "FADDD $src1,$src2,$dst" %}
7678 7678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7679 7679 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7680 7680 ins_pipe(faddD_reg_reg);
7681 7681 %}
7682 7682
7683 7683 // Sub float single precision
7684 7684 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7685 7685 match(Set dst (SubF src1 src2));
7686 7686
7687 7687 size(4);
7688 7688 format %{ "FSUBS $src1,$src2,$dst" %}
7689 7689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7690 7690 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7691 7691 ins_pipe(faddF_reg_reg);
7692 7692 %}
7693 7693
7694 7694 // Sub float double precision
7695 7695 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7696 7696 match(Set dst (SubD src1 src2));
7697 7697
7698 7698 size(4);
7699 7699 format %{ "FSUBD $src1,$src2,$dst" %}
7700 7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7701 7701 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7702 7702 ins_pipe(faddD_reg_reg);
7703 7703 %}
7704 7704
7705 7705 // Mul float single precision
7706 7706 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7707 7707 match(Set dst (MulF src1 src2));
7708 7708
7709 7709 size(4);
7710 7710 format %{ "FMULS $src1,$src2,$dst" %}
7711 7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7712 7712 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7713 7713 ins_pipe(fmulF_reg_reg);
7714 7714 %}
7715 7715
7716 7716 // Mul float double precision
7717 7717 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7718 7718 match(Set dst (MulD src1 src2));
7719 7719
7720 7720 size(4);
7721 7721 format %{ "FMULD $src1,$src2,$dst" %}
7722 7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7723 7723 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7724 7724 ins_pipe(fmulD_reg_reg);
7725 7725 %}
7726 7726
7727 7727 // Div float single precision
7728 7728 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7729 7729 match(Set dst (DivF src1 src2));
7730 7730
7731 7731 size(4);
7732 7732 format %{ "FDIVS $src1,$src2,$dst" %}
7733 7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7734 7734 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7735 7735 ins_pipe(fdivF_reg_reg);
7736 7736 %}
7737 7737
7738 7738 // Div float double precision
7739 7739 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7740 7740 match(Set dst (DivD src1 src2));
7741 7741
7742 7742 size(4);
7743 7743 format %{ "FDIVD $src1,$src2,$dst" %}
7744 7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7745 7745 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7746 7746 ins_pipe(fdivD_reg_reg);
7747 7747 %}
7748 7748
7749 7749 // Absolute float double precision
7750 7750 instruct absD_reg(regD dst, regD src) %{
7751 7751 match(Set dst (AbsD src));
7752 7752
7753 7753 format %{ "FABSd $src,$dst" %}
7754 7754 ins_encode(fabsd(dst, src));
7755 7755 ins_pipe(faddD_reg);
7756 7756 %}
7757 7757
7758 7758 // Absolute float single precision
7759 7759 instruct absF_reg(regF dst, regF src) %{
7760 7760 match(Set dst (AbsF src));
7761 7761
7762 7762 format %{ "FABSs $src,$dst" %}
7763 7763 ins_encode(fabss(dst, src));
7764 7764 ins_pipe(faddF_reg);
7765 7765 %}
7766 7766
7767 7767 instruct negF_reg(regF dst, regF src) %{
7768 7768 match(Set dst (NegF src));
7769 7769
7770 7770 size(4);
7771 7771 format %{ "FNEGs $src,$dst" %}
7772 7772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7773 7773 ins_encode(form3_opf_rs2F_rdF(src, dst));
7774 7774 ins_pipe(faddF_reg);
7775 7775 %}
7776 7776
7777 7777 instruct negD_reg(regD dst, regD src) %{
7778 7778 match(Set dst (NegD src));
7779 7779
7780 7780 format %{ "FNEGd $src,$dst" %}
7781 7781 ins_encode(fnegd(dst, src));
7782 7782 ins_pipe(faddD_reg);
7783 7783 %}
7784 7784
7785 7785 // Sqrt float double precision
7786 7786 instruct sqrtF_reg_reg(regF dst, regF src) %{
7787 7787 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7788 7788
7789 7789 size(4);
7790 7790 format %{ "FSQRTS $src,$dst" %}
7791 7791 ins_encode(fsqrts(dst, src));
7792 7792 ins_pipe(fdivF_reg_reg);
7793 7793 %}
7794 7794
7795 7795 // Sqrt float double precision
7796 7796 instruct sqrtD_reg_reg(regD dst, regD src) %{
7797 7797 match(Set dst (SqrtD src));
7798 7798
7799 7799 size(4);
7800 7800 format %{ "FSQRTD $src,$dst" %}
7801 7801 ins_encode(fsqrtd(dst, src));
7802 7802 ins_pipe(fdivD_reg_reg);
7803 7803 %}
7804 7804
7805 7805 //----------Logical Instructions-----------------------------------------------
7806 7806 // And Instructions
7807 7807 // Register And
7808 7808 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7809 7809 match(Set dst (AndI src1 src2));
7810 7810
7811 7811 size(4);
7812 7812 format %{ "AND $src1,$src2,$dst" %}
7813 7813 opcode(Assembler::and_op3, Assembler::arith_op);
7814 7814 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7815 7815 ins_pipe(ialu_reg_reg);
7816 7816 %}
7817 7817
7818 7818 // Immediate And
7819 7819 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7820 7820 match(Set dst (AndI src1 src2));
7821 7821
7822 7822 size(4);
7823 7823 format %{ "AND $src1,$src2,$dst" %}
7824 7824 opcode(Assembler::and_op3, Assembler::arith_op);
7825 7825 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7826 7826 ins_pipe(ialu_reg_imm);
7827 7827 %}
7828 7828
7829 7829 // Register And Long
7830 7830 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7831 7831 match(Set dst (AndL src1 src2));
7832 7832
7833 7833 ins_cost(DEFAULT_COST);
7834 7834 size(4);
7835 7835 format %{ "AND $src1,$src2,$dst\t! long" %}
7836 7836 opcode(Assembler::and_op3, Assembler::arith_op);
7837 7837 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7838 7838 ins_pipe(ialu_reg_reg);
7839 7839 %}
7840 7840
7841 7841 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7842 7842 match(Set dst (AndL src1 con));
7843 7843
7844 7844 ins_cost(DEFAULT_COST);
7845 7845 size(4);
7846 7846 format %{ "AND $src1,$con,$dst\t! long" %}
7847 7847 opcode(Assembler::and_op3, Assembler::arith_op);
7848 7848 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7849 7849 ins_pipe(ialu_reg_imm);
7850 7850 %}
7851 7851
7852 7852 // Or Instructions
7853 7853 // Register Or
7854 7854 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7855 7855 match(Set dst (OrI src1 src2));
7856 7856
7857 7857 size(4);
7858 7858 format %{ "OR $src1,$src2,$dst" %}
7859 7859 opcode(Assembler::or_op3, Assembler::arith_op);
7860 7860 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7861 7861 ins_pipe(ialu_reg_reg);
7862 7862 %}
7863 7863
7864 7864 // Immediate Or
7865 7865 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7866 7866 match(Set dst (OrI src1 src2));
7867 7867
7868 7868 size(4);
7869 7869 format %{ "OR $src1,$src2,$dst" %}
7870 7870 opcode(Assembler::or_op3, Assembler::arith_op);
7871 7871 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7872 7872 ins_pipe(ialu_reg_imm);
7873 7873 %}
7874 7874
7875 7875 // Register Or Long
7876 7876 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7877 7877 match(Set dst (OrL src1 src2));
7878 7878
7879 7879 ins_cost(DEFAULT_COST);
7880 7880 size(4);
7881 7881 format %{ "OR $src1,$src2,$dst\t! long" %}
7882 7882 opcode(Assembler::or_op3, Assembler::arith_op);
7883 7883 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7884 7884 ins_pipe(ialu_reg_reg);
7885 7885 %}
7886 7886
7887 7887 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7888 7888 match(Set dst (OrL src1 con));
7889 7889 ins_cost(DEFAULT_COST*2);
7890 7890
7891 7891 ins_cost(DEFAULT_COST);
7892 7892 size(4);
7893 7893 format %{ "OR $src1,$con,$dst\t! long" %}
7894 7894 opcode(Assembler::or_op3, Assembler::arith_op);
7895 7895 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7896 7896 ins_pipe(ialu_reg_imm);
7897 7897 %}
7898 7898
7899 7899 #ifndef _LP64
7900 7900
7901 7901 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7902 7902 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7903 7903 match(Set dst (OrI src1 (CastP2X src2)));
7904 7904
7905 7905 size(4);
7906 7906 format %{ "OR $src1,$src2,$dst" %}
7907 7907 opcode(Assembler::or_op3, Assembler::arith_op);
7908 7908 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7909 7909 ins_pipe(ialu_reg_reg);
7910 7910 %}
7911 7911
7912 7912 #else
7913 7913
7914 7914 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7915 7915 match(Set dst (OrL src1 (CastP2X src2)));
7916 7916
7917 7917 ins_cost(DEFAULT_COST);
7918 7918 size(4);
7919 7919 format %{ "OR $src1,$src2,$dst\t! long" %}
7920 7920 opcode(Assembler::or_op3, Assembler::arith_op);
7921 7921 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7922 7922 ins_pipe(ialu_reg_reg);
7923 7923 %}
7924 7924
7925 7925 #endif
7926 7926
7927 7927 // Xor Instructions
7928 7928 // Register Xor
7929 7929 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7930 7930 match(Set dst (XorI src1 src2));
7931 7931
7932 7932 size(4);
7933 7933 format %{ "XOR $src1,$src2,$dst" %}
7934 7934 opcode(Assembler::xor_op3, Assembler::arith_op);
7935 7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7936 7936 ins_pipe(ialu_reg_reg);
7937 7937 %}
7938 7938
7939 7939 // Immediate Xor
7940 7940 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7941 7941 match(Set dst (XorI src1 src2));
7942 7942
7943 7943 size(4);
7944 7944 format %{ "XOR $src1,$src2,$dst" %}
7945 7945 opcode(Assembler::xor_op3, Assembler::arith_op);
7946 7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7947 7947 ins_pipe(ialu_reg_imm);
7948 7948 %}
7949 7949
7950 7950 // Register Xor Long
7951 7951 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7952 7952 match(Set dst (XorL src1 src2));
7953 7953
7954 7954 ins_cost(DEFAULT_COST);
7955 7955 size(4);
7956 7956 format %{ "XOR $src1,$src2,$dst\t! long" %}
7957 7957 opcode(Assembler::xor_op3, Assembler::arith_op);
7958 7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7959 7959 ins_pipe(ialu_reg_reg);
7960 7960 %}
7961 7961
7962 7962 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7963 7963 match(Set dst (XorL src1 con));
7964 7964
7965 7965 ins_cost(DEFAULT_COST);
7966 7966 size(4);
7967 7967 format %{ "XOR $src1,$con,$dst\t! long" %}
7968 7968 opcode(Assembler::xor_op3, Assembler::arith_op);
7969 7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7970 7970 ins_pipe(ialu_reg_imm);
7971 7971 %}
7972 7972
7973 7973 //----------Convert to Boolean-------------------------------------------------
7974 7974 // Nice hack for 32-bit tests but doesn't work for
7975 7975 // 64-bit pointers.
7976 7976 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7977 7977 match(Set dst (Conv2B src));
7978 7978 effect( KILL ccr );
7979 7979 ins_cost(DEFAULT_COST*2);
7980 7980 format %{ "CMP R_G0,$src\n\t"
7981 7981 "ADDX R_G0,0,$dst" %}
7982 7982 ins_encode( enc_to_bool( src, dst ) );
7983 7983 ins_pipe(ialu_reg_ialu);
7984 7984 %}
7985 7985
7986 7986 #ifndef _LP64
7987 7987 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7988 7988 match(Set dst (Conv2B src));
7989 7989 effect( KILL ccr );
7990 7990 ins_cost(DEFAULT_COST*2);
7991 7991 format %{ "CMP R_G0,$src\n\t"
7992 7992 "ADDX R_G0,0,$dst" %}
7993 7993 ins_encode( enc_to_bool( src, dst ) );
7994 7994 ins_pipe(ialu_reg_ialu);
7995 7995 %}
7996 7996 #else
7997 7997 instruct convP2B( iRegI dst, iRegP src ) %{
7998 7998 match(Set dst (Conv2B src));
7999 7999 ins_cost(DEFAULT_COST*2);
8000 8000 format %{ "MOV $src,$dst\n\t"
8001 8001 "MOVRNZ $src,1,$dst" %}
8002 8002 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8003 8003 ins_pipe(ialu_clr_and_mover);
8004 8004 %}
8005 8005 #endif
8006 8006
8007 8007 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8008 8008 match(Set dst (CmpLTMask p q));
8009 8009 effect( KILL ccr );
8010 8010 ins_cost(DEFAULT_COST*4);
8011 8011 format %{ "CMP $p,$q\n\t"
8012 8012 "MOV #0,$dst\n\t"
8013 8013 "BLT,a .+8\n\t"
8014 8014 "MOV #-1,$dst" %}
8015 8015 ins_encode( enc_ltmask(p,q,dst) );
8016 8016 ins_pipe(ialu_reg_reg_ialu);
8017 8017 %}
8018 8018
8019 8019 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8020 8020 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8021 8021 effect(KILL ccr, TEMP tmp);
8022 8022 ins_cost(DEFAULT_COST*3);
8023 8023
8024 8024 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8025 8025 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8026 8026 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8027 8027 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8028 8028 ins_pipe( cadd_cmpltmask );
8029 8029 %}
8030 8030
8031 8031 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8032 8032 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
8033 8033 effect( KILL ccr, TEMP tmp);
8034 8034 ins_cost(DEFAULT_COST*3);
8035 8035
8036 8036 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8037 8037 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8038 8038 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8039 8039 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8040 8040 ins_pipe( cadd_cmpltmask );
8041 8041 %}
8042 8042
8043 8043 //----------Arithmetic Conversion Instructions---------------------------------
8044 8044 // The conversions operations are all Alpha sorted. Please keep it that way!
8045 8045
8046 8046 instruct convD2F_reg(regF dst, regD src) %{
8047 8047 match(Set dst (ConvD2F src));
8048 8048 size(4);
8049 8049 format %{ "FDTOS $src,$dst" %}
8050 8050 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8051 8051 ins_encode(form3_opf_rs2D_rdF(src, dst));
8052 8052 ins_pipe(fcvtD2F);
8053 8053 %}
8054 8054
8055 8055
8056 8056 // Convert a double to an int in a float register.
8057 8057 // If the double is a NAN, stuff a zero in instead.
8058 8058 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8059 8059 effect(DEF dst, USE src, KILL fcc0);
8060 8060 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8061 8061 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8062 8062 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8063 8063 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8064 8064 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8065 8065 "skip:" %}
8066 8066 ins_encode(form_d2i_helper(src,dst));
8067 8067 ins_pipe(fcvtD2I);
8068 8068 %}
8069 8069
8070 8070 instruct convD2I_reg(stackSlotI dst, regD src) %{
8071 8071 match(Set dst (ConvD2I src));
8072 8072 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8073 8073 expand %{
8074 8074 regF tmp;
8075 8075 convD2I_helper(tmp, src);
8076 8076 regF_to_stkI(dst, tmp);
8077 8077 %}
8078 8078 %}
8079 8079
8080 8080 // Convert a double to a long in a double register.
8081 8081 // If the double is a NAN, stuff a zero in instead.
8082 8082 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8083 8083 effect(DEF dst, USE src, KILL fcc0);
8084 8084 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8085 8085 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8086 8086 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8087 8087 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8088 8088 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8089 8089 "skip:" %}
8090 8090 ins_encode(form_d2l_helper(src,dst));
8091 8091 ins_pipe(fcvtD2L);
8092 8092 %}
8093 8093
8094 8094
8095 8095 // Double to Long conversion
8096 8096 instruct convD2L_reg(stackSlotL dst, regD src) %{
8097 8097 match(Set dst (ConvD2L src));
8098 8098 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8099 8099 expand %{
8100 8100 regD tmp;
8101 8101 convD2L_helper(tmp, src);
8102 8102 regD_to_stkL(dst, tmp);
8103 8103 %}
8104 8104 %}
8105 8105
8106 8106
8107 8107 instruct convF2D_reg(regD dst, regF src) %{
8108 8108 match(Set dst (ConvF2D src));
8109 8109 format %{ "FSTOD $src,$dst" %}
8110 8110 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8111 8111 ins_encode(form3_opf_rs2F_rdD(src, dst));
8112 8112 ins_pipe(fcvtF2D);
8113 8113 %}
8114 8114
8115 8115
8116 8116 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8117 8117 effect(DEF dst, USE src, KILL fcc0);
8118 8118 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8119 8119 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8120 8120 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8121 8121 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8122 8122 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8123 8123 "skip:" %}
8124 8124 ins_encode(form_f2i_helper(src,dst));
8125 8125 ins_pipe(fcvtF2I);
8126 8126 %}
8127 8127
8128 8128 instruct convF2I_reg(stackSlotI dst, regF src) %{
8129 8129 match(Set dst (ConvF2I src));
8130 8130 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8131 8131 expand %{
8132 8132 regF tmp;
8133 8133 convF2I_helper(tmp, src);
8134 8134 regF_to_stkI(dst, tmp);
8135 8135 %}
8136 8136 %}
8137 8137
8138 8138
8139 8139 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8140 8140 effect(DEF dst, USE src, KILL fcc0);
8141 8141 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8142 8142 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8143 8143 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8144 8144 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8145 8145 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8146 8146 "skip:" %}
8147 8147 ins_encode(form_f2l_helper(src,dst));
8148 8148 ins_pipe(fcvtF2L);
8149 8149 %}
8150 8150
8151 8151 // Float to Long conversion
8152 8152 instruct convF2L_reg(stackSlotL dst, regF src) %{
8153 8153 match(Set dst (ConvF2L src));
8154 8154 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8155 8155 expand %{
8156 8156 regD tmp;
8157 8157 convF2L_helper(tmp, src);
8158 8158 regD_to_stkL(dst, tmp);
8159 8159 %}
8160 8160 %}
8161 8161
8162 8162
8163 8163 instruct convI2D_helper(regD dst, regF tmp) %{
8164 8164 effect(USE tmp, DEF dst);
8165 8165 format %{ "FITOD $tmp,$dst" %}
8166 8166 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8167 8167 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8168 8168 ins_pipe(fcvtI2D);
8169 8169 %}
8170 8170
8171 8171 instruct convI2D_reg(stackSlotI src, regD dst) %{
8172 8172 match(Set dst (ConvI2D src));
8173 8173 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8174 8174 expand %{
8175 8175 regF tmp;
8176 8176 stkI_to_regF( tmp, src);
8177 8177 convI2D_helper( dst, tmp);
8178 8178 %}
8179 8179 %}
8180 8180
8181 8181 instruct convI2D_mem( regD_low dst, memory mem ) %{
8182 8182 match(Set dst (ConvI2D (LoadI mem)));
8183 8183 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8184 8184 size(8);
8185 8185 format %{ "LDF $mem,$dst\n\t"
8186 8186 "FITOD $dst,$dst" %}
8187 8187 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8188 8188 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8189 8189 ins_pipe(floadF_mem);
8190 8190 %}
8191 8191
8192 8192
8193 8193 instruct convI2F_helper(regF dst, regF tmp) %{
8194 8194 effect(DEF dst, USE tmp);
8195 8195 format %{ "FITOS $tmp,$dst" %}
8196 8196 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8197 8197 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8198 8198 ins_pipe(fcvtI2F);
8199 8199 %}
8200 8200
8201 8201 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8202 8202 match(Set dst (ConvI2F src));
8203 8203 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8204 8204 expand %{
8205 8205 regF tmp;
8206 8206 stkI_to_regF(tmp,src);
8207 8207 convI2F_helper(dst, tmp);
8208 8208 %}
8209 8209 %}
8210 8210
8211 8211 instruct convI2F_mem( regF dst, memory mem ) %{
8212 8212 match(Set dst (ConvI2F (LoadI mem)));
8213 8213 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8214 8214 size(8);
8215 8215 format %{ "LDF $mem,$dst\n\t"
8216 8216 "FITOS $dst,$dst" %}
8217 8217 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8218 8218 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8219 8219 ins_pipe(floadF_mem);
8220 8220 %}
8221 8221
8222 8222
8223 8223 instruct convI2L_reg(iRegL dst, iRegI src) %{
8224 8224 match(Set dst (ConvI2L src));
8225 8225 size(4);
8226 8226 format %{ "SRA $src,0,$dst\t! int->long" %}
8227 8227 opcode(Assembler::sra_op3, Assembler::arith_op);
8228 8228 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8229 8229 ins_pipe(ialu_reg_reg);
8230 8230 %}
8231 8231
8232 8232 // Zero-extend convert int to long
8233 8233 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8234 8234 match(Set dst (AndL (ConvI2L src) mask) );
8235 8235 size(4);
8236 8236 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8237 8237 opcode(Assembler::srl_op3, Assembler::arith_op);
8238 8238 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8239 8239 ins_pipe(ialu_reg_reg);
8240 8240 %}
8241 8241
8242 8242 // Zero-extend long
8243 8243 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8244 8244 match(Set dst (AndL src mask) );
8245 8245 size(4);
8246 8246 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8247 8247 opcode(Assembler::srl_op3, Assembler::arith_op);
8248 8248 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8249 8249 ins_pipe(ialu_reg_reg);
8250 8250 %}
8251 8251
8252 8252 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8253 8253 match(Set dst (MoveF2I src));
8254 8254 effect(DEF dst, USE src);
8255 8255 ins_cost(MEMORY_REF_COST);
8256 8256
8257 8257 size(4);
8258 8258 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8259 8259 opcode(Assembler::lduw_op3);
8260 8260 ins_encode(simple_form3_mem_reg( src, dst ) );
8261 8261 ins_pipe(iload_mem);
8262 8262 %}
8263 8263
8264 8264 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8265 8265 match(Set dst (MoveI2F src));
8266 8266 effect(DEF dst, USE src);
8267 8267 ins_cost(MEMORY_REF_COST);
8268 8268
8269 8269 size(4);
8270 8270 format %{ "LDF $src,$dst\t! MoveI2F" %}
8271 8271 opcode(Assembler::ldf_op3);
8272 8272 ins_encode(simple_form3_mem_reg(src, dst));
8273 8273 ins_pipe(floadF_stk);
8274 8274 %}
8275 8275
8276 8276 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8277 8277 match(Set dst (MoveD2L src));
8278 8278 effect(DEF dst, USE src);
8279 8279 ins_cost(MEMORY_REF_COST);
8280 8280
8281 8281 size(4);
8282 8282 format %{ "LDX $src,$dst\t! MoveD2L" %}
8283 8283 opcode(Assembler::ldx_op3);
8284 8284 ins_encode(simple_form3_mem_reg( src, dst ) );
8285 8285 ins_pipe(iload_mem);
8286 8286 %}
8287 8287
8288 8288 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8289 8289 match(Set dst (MoveL2D src));
8290 8290 effect(DEF dst, USE src);
8291 8291 ins_cost(MEMORY_REF_COST);
8292 8292
8293 8293 size(4);
8294 8294 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8295 8295 opcode(Assembler::lddf_op3);
8296 8296 ins_encode(simple_form3_mem_reg(src, dst));
8297 8297 ins_pipe(floadD_stk);
8298 8298 %}
8299 8299
8300 8300 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8301 8301 match(Set dst (MoveF2I src));
8302 8302 effect(DEF dst, USE src);
8303 8303 ins_cost(MEMORY_REF_COST);
8304 8304
8305 8305 size(4);
8306 8306 format %{ "STF $src,$dst\t!MoveF2I" %}
8307 8307 opcode(Assembler::stf_op3);
8308 8308 ins_encode(simple_form3_mem_reg(dst, src));
8309 8309 ins_pipe(fstoreF_stk_reg);
8310 8310 %}
8311 8311
8312 8312 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8313 8313 match(Set dst (MoveI2F src));
8314 8314 effect(DEF dst, USE src);
8315 8315 ins_cost(MEMORY_REF_COST);
8316 8316
8317 8317 size(4);
8318 8318 format %{ "STW $src,$dst\t!MoveI2F" %}
8319 8319 opcode(Assembler::stw_op3);
8320 8320 ins_encode(simple_form3_mem_reg( dst, src ) );
8321 8321 ins_pipe(istore_mem_reg);
8322 8322 %}
8323 8323
8324 8324 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8325 8325 match(Set dst (MoveD2L src));
8326 8326 effect(DEF dst, USE src);
8327 8327 ins_cost(MEMORY_REF_COST);
8328 8328
8329 8329 size(4);
8330 8330 format %{ "STDF $src,$dst\t!MoveD2L" %}
8331 8331 opcode(Assembler::stdf_op3);
8332 8332 ins_encode(simple_form3_mem_reg(dst, src));
8333 8333 ins_pipe(fstoreD_stk_reg);
8334 8334 %}
8335 8335
8336 8336 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8337 8337 match(Set dst (MoveL2D src));
8338 8338 effect(DEF dst, USE src);
8339 8339 ins_cost(MEMORY_REF_COST);
8340 8340
8341 8341 size(4);
8342 8342 format %{ "STX $src,$dst\t!MoveL2D" %}
8343 8343 opcode(Assembler::stx_op3);
8344 8344 ins_encode(simple_form3_mem_reg( dst, src ) );
8345 8345 ins_pipe(istore_mem_reg);
8346 8346 %}
8347 8347
8348 8348
8349 8349 //-----------
8350 8350 // Long to Double conversion using V8 opcodes.
8351 8351 // Still useful because cheetah traps and becomes
8352 8352 // amazingly slow for some common numbers.
8353 8353
8354 8354 // Magic constant, 0x43300000
8355 8355 instruct loadConI_x43300000(iRegI dst) %{
8356 8356 effect(DEF dst);
8357 8357 size(4);
8358 8358 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8359 8359 ins_encode(SetHi22(0x43300000, dst));
8360 8360 ins_pipe(ialu_none);
8361 8361 %}
8362 8362
8363 8363 // Magic constant, 0x41f00000
8364 8364 instruct loadConI_x41f00000(iRegI dst) %{
8365 8365 effect(DEF dst);
8366 8366 size(4);
8367 8367 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8368 8368 ins_encode(SetHi22(0x41f00000, dst));
8369 8369 ins_pipe(ialu_none);
8370 8370 %}
8371 8371
8372 8372 // Construct a double from two float halves
8373 8373 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8374 8374 effect(DEF dst, USE src1, USE src2);
8375 8375 size(8);
8376 8376 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8377 8377 "FMOVS $src2.lo,$dst.lo" %}
8378 8378 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8379 8379 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8380 8380 ins_pipe(faddD_reg_reg);
8381 8381 %}
8382 8382
8383 8383 // Convert integer in high half of a double register (in the lower half of
8384 8384 // the double register file) to double
8385 8385 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8386 8386 effect(DEF dst, USE src);
8387 8387 size(4);
8388 8388 format %{ "FITOD $src,$dst" %}
8389 8389 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8390 8390 ins_encode(form3_opf_rs2D_rdD(src, dst));
8391 8391 ins_pipe(fcvtLHi2D);
8392 8392 %}
8393 8393
8394 8394 // Add float double precision
8395 8395 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8396 8396 effect(DEF dst, USE src1, USE src2);
8397 8397 size(4);
8398 8398 format %{ "FADDD $src1,$src2,$dst" %}
8399 8399 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8400 8400 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8401 8401 ins_pipe(faddD_reg_reg);
8402 8402 %}
8403 8403
8404 8404 // Sub float double precision
8405 8405 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8406 8406 effect(DEF dst, USE src1, USE src2);
8407 8407 size(4);
8408 8408 format %{ "FSUBD $src1,$src2,$dst" %}
8409 8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8410 8410 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8411 8411 ins_pipe(faddD_reg_reg);
8412 8412 %}
8413 8413
8414 8414 // Mul float double precision
8415 8415 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8416 8416 effect(DEF dst, USE src1, USE src2);
8417 8417 size(4);
8418 8418 format %{ "FMULD $src1,$src2,$dst" %}
8419 8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8420 8420 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8421 8421 ins_pipe(fmulD_reg_reg);
8422 8422 %}
8423 8423
8424 8424 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8425 8425 match(Set dst (ConvL2D src));
8426 8426 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8427 8427
8428 8428 expand %{
8429 8429 regD_low tmpsrc;
8430 8430 iRegI ix43300000;
8431 8431 iRegI ix41f00000;
8432 8432 stackSlotL lx43300000;
8433 8433 stackSlotL lx41f00000;
8434 8434 regD_low dx43300000;
8435 8435 regD dx41f00000;
8436 8436 regD tmp1;
8437 8437 regD_low tmp2;
8438 8438 regD tmp3;
8439 8439 regD tmp4;
8440 8440
8441 8441 stkL_to_regD(tmpsrc, src);
8442 8442
8443 8443 loadConI_x43300000(ix43300000);
8444 8444 loadConI_x41f00000(ix41f00000);
8445 8445 regI_to_stkLHi(lx43300000, ix43300000);
8446 8446 regI_to_stkLHi(lx41f00000, ix41f00000);
8447 8447 stkL_to_regD(dx43300000, lx43300000);
8448 8448 stkL_to_regD(dx41f00000, lx41f00000);
8449 8449
8450 8450 convI2D_regDHi_regD(tmp1, tmpsrc);
8451 8451 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8452 8452 subD_regD_regD(tmp3, tmp2, dx43300000);
8453 8453 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8454 8454 addD_regD_regD(dst, tmp3, tmp4);
8455 8455 %}
8456 8456 %}
8457 8457
8458 8458 // Long to Double conversion using fast fxtof
8459 8459 instruct convL2D_helper(regD dst, regD tmp) %{
8460 8460 effect(DEF dst, USE tmp);
8461 8461 size(4);
8462 8462 format %{ "FXTOD $tmp,$dst" %}
8463 8463 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8464 8464 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8465 8465 ins_pipe(fcvtL2D);
8466 8466 %}
8467 8467
8468 8468 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8469 8469 predicate(VM_Version::has_fast_fxtof());
8470 8470 match(Set dst (ConvL2D src));
8471 8471 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8472 8472 expand %{
8473 8473 regD tmp;
8474 8474 stkL_to_regD(tmp, src);
8475 8475 convL2D_helper(dst, tmp);
8476 8476 %}
8477 8477 %}
8478 8478
8479 8479 //-----------
8480 8480 // Long to Float conversion using V8 opcodes.
8481 8481 // Still useful because cheetah traps and becomes
8482 8482 // amazingly slow for some common numbers.
8483 8483
8484 8484 // Long to Float conversion using fast fxtof
8485 8485 instruct convL2F_helper(regF dst, regD tmp) %{
8486 8486 effect(DEF dst, USE tmp);
8487 8487 size(4);
8488 8488 format %{ "FXTOS $tmp,$dst" %}
8489 8489 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8490 8490 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8491 8491 ins_pipe(fcvtL2F);
8492 8492 %}
8493 8493
8494 8494 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8495 8495 match(Set dst (ConvL2F src));
8496 8496 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8497 8497 expand %{
8498 8498 regD tmp;
8499 8499 stkL_to_regD(tmp, src);
8500 8500 convL2F_helper(dst, tmp);
8501 8501 %}
8502 8502 %}
8503 8503 //-----------
8504 8504
8505 8505 instruct convL2I_reg(iRegI dst, iRegL src) %{
8506 8506 match(Set dst (ConvL2I src));
8507 8507 #ifndef _LP64
8508 8508 format %{ "MOV $src.lo,$dst\t! long->int" %}
8509 8509 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8510 8510 ins_pipe(ialu_move_reg_I_to_L);
8511 8511 #else
8512 8512 size(4);
8513 8513 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8514 8514 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8515 8515 ins_pipe(ialu_reg);
8516 8516 #endif
8517 8517 %}
8518 8518
8519 8519 // Register Shift Right Immediate
8520 8520 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8521 8521 match(Set dst (ConvL2I (RShiftL src cnt)));
8522 8522
8523 8523 size(4);
8524 8524 format %{ "SRAX $src,$cnt,$dst" %}
8525 8525 opcode(Assembler::srax_op3, Assembler::arith_op);
8526 8526 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8527 8527 ins_pipe(ialu_reg_imm);
8528 8528 %}
8529 8529
8530 8530 // Replicate scalar to packed byte values in Double register
8531 8531 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8532 8532 effect(DEF dst, USE src);
8533 8533 format %{ "SLLX $src,56,$dst\n\t"
8534 8534 "SRLX $dst, 8,O7\n\t"
8535 8535 "OR $dst,O7,$dst\n\t"
8536 8536 "SRLX $dst,16,O7\n\t"
8537 8537 "OR $dst,O7,$dst\n\t"
8538 8538 "SRLX $dst,32,O7\n\t"
8539 8539 "OR $dst,O7,$dst\t! replicate8B" %}
8540 8540 ins_encode( enc_repl8b(src, dst));
8541 8541 ins_pipe(ialu_reg);
8542 8542 %}
8543 8543
8544 8544 // Replicate scalar to packed byte values in Double register
8545 8545 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8546 8546 match(Set dst (Replicate8B src));
8547 8547 expand %{
8548 8548 iRegL tmp;
8549 8549 Repl8B_reg_helper(tmp, src);
8550 8550 regL_to_stkD(dst, tmp);
8551 8551 %}
8552 8552 %}
8553 8553
8554 8554 // Replicate scalar constant to packed byte values in Double register
8555 8555 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8556 8556 match(Set dst (Replicate8B src));
8557 8557 #ifdef _LP64
8558 8558 size(36);
8559 8559 #else
8560 8560 size(8);
8561 8561 #endif
8562 8562 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8563 8563 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8564 8564 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8565 8565 ins_pipe(loadConFD);
8566 8566 %}
8567 8567
8568 8568 // Replicate scalar to packed char values into stack slot
8569 8569 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8570 8570 effect(DEF dst, USE src);
8571 8571 format %{ "SLLX $src,48,$dst\n\t"
8572 8572 "SRLX $dst,16,O7\n\t"
8573 8573 "OR $dst,O7,$dst\n\t"
8574 8574 "SRLX $dst,32,O7\n\t"
8575 8575 "OR $dst,O7,$dst\t! replicate4C" %}
8576 8576 ins_encode( enc_repl4s(src, dst) );
8577 8577 ins_pipe(ialu_reg);
8578 8578 %}
8579 8579
8580 8580 // Replicate scalar to packed char values into stack slot
8581 8581 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8582 8582 match(Set dst (Replicate4C src));
8583 8583 expand %{
8584 8584 iRegL tmp;
8585 8585 Repl4C_reg_helper(tmp, src);
8586 8586 regL_to_stkD(dst, tmp);
8587 8587 %}
8588 8588 %}
8589 8589
8590 8590 // Replicate scalar constant to packed char values in Double register
8591 8591 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8592 8592 match(Set dst (Replicate4C src));
8593 8593 #ifdef _LP64
8594 8594 size(36);
8595 8595 #else
8596 8596 size(8);
8597 8597 #endif
8598 8598 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8599 8599 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8600 8600 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8601 8601 ins_pipe(loadConFD);
8602 8602 %}
8603 8603
8604 8604 // Replicate scalar to packed short values into stack slot
8605 8605 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8606 8606 effect(DEF dst, USE src);
8607 8607 format %{ "SLLX $src,48,$dst\n\t"
8608 8608 "SRLX $dst,16,O7\n\t"
8609 8609 "OR $dst,O7,$dst\n\t"
8610 8610 "SRLX $dst,32,O7\n\t"
8611 8611 "OR $dst,O7,$dst\t! replicate4S" %}
8612 8612 ins_encode( enc_repl4s(src, dst) );
8613 8613 ins_pipe(ialu_reg);
8614 8614 %}
8615 8615
8616 8616 // Replicate scalar to packed short values into stack slot
8617 8617 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8618 8618 match(Set dst (Replicate4S src));
8619 8619 expand %{
8620 8620 iRegL tmp;
8621 8621 Repl4S_reg_helper(tmp, src);
8622 8622 regL_to_stkD(dst, tmp);
8623 8623 %}
8624 8624 %}
8625 8625
8626 8626 // Replicate scalar constant to packed short values in Double register
8627 8627 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8628 8628 match(Set dst (Replicate4S src));
8629 8629 #ifdef _LP64
8630 8630 size(36);
8631 8631 #else
8632 8632 size(8);
8633 8633 #endif
8634 8634 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8635 8635 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8636 8636 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8637 8637 ins_pipe(loadConFD);
8638 8638 %}
8639 8639
8640 8640 // Replicate scalar to packed int values in Double register
8641 8641 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8642 8642 effect(DEF dst, USE src);
8643 8643 format %{ "SLLX $src,32,$dst\n\t"
8644 8644 "SRLX $dst,32,O7\n\t"
8645 8645 "OR $dst,O7,$dst\t! replicate2I" %}
8646 8646 ins_encode( enc_repl2i(src, dst));
8647 8647 ins_pipe(ialu_reg);
8648 8648 %}
8649 8649
8650 8650 // Replicate scalar to packed int values in Double register
8651 8651 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8652 8652 match(Set dst (Replicate2I src));
8653 8653 expand %{
8654 8654 iRegL tmp;
8655 8655 Repl2I_reg_helper(tmp, src);
8656 8656 regL_to_stkD(dst, tmp);
8657 8657 %}
8658 8658 %}
8659 8659
8660 8660 // Replicate scalar zero constant to packed int values in Double register
8661 8661 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8662 8662 match(Set dst (Replicate2I src));
8663 8663 #ifdef _LP64
8664 8664 size(36);
8665 8665 #else
8666 8666 size(8);
8667 8667 #endif
8668 8668 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8669 8669 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8670 8670 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8671 8671 ins_pipe(loadConFD);
8672 8672 %}
8673 8673
8674 8674 //----------Control Flow Instructions------------------------------------------
8675 8675 // Compare Instructions
8676 8676 // Compare Integers
8677 8677 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8678 8678 match(Set icc (CmpI op1 op2));
8679 8679 effect( DEF icc, USE op1, USE op2 );
8680 8680
8681 8681 size(4);
8682 8682 format %{ "CMP $op1,$op2" %}
8683 8683 opcode(Assembler::subcc_op3, Assembler::arith_op);
8684 8684 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8685 8685 ins_pipe(ialu_cconly_reg_reg);
8686 8686 %}
8687 8687
8688 8688 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8689 8689 match(Set icc (CmpU op1 op2));
8690 8690
8691 8691 size(4);
8692 8692 format %{ "CMP $op1,$op2\t! unsigned" %}
8693 8693 opcode(Assembler::subcc_op3, Assembler::arith_op);
8694 8694 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8695 8695 ins_pipe(ialu_cconly_reg_reg);
8696 8696 %}
8697 8697
8698 8698 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8699 8699 match(Set icc (CmpI op1 op2));
8700 8700 effect( DEF icc, USE op1 );
8701 8701
8702 8702 size(4);
8703 8703 format %{ "CMP $op1,$op2" %}
8704 8704 opcode(Assembler::subcc_op3, Assembler::arith_op);
8705 8705 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8706 8706 ins_pipe(ialu_cconly_reg_imm);
8707 8707 %}
8708 8708
8709 8709 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8710 8710 match(Set icc (CmpI (AndI op1 op2) zero));
8711 8711
8712 8712 size(4);
8713 8713 format %{ "BTST $op2,$op1" %}
8714 8714 opcode(Assembler::andcc_op3, Assembler::arith_op);
8715 8715 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8716 8716 ins_pipe(ialu_cconly_reg_reg_zero);
8717 8717 %}
8718 8718
8719 8719 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8720 8720 match(Set icc (CmpI (AndI op1 op2) zero));
8721 8721
8722 8722 size(4);
8723 8723 format %{ "BTST $op2,$op1" %}
8724 8724 opcode(Assembler::andcc_op3, Assembler::arith_op);
8725 8725 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8726 8726 ins_pipe(ialu_cconly_reg_imm_zero);
8727 8727 %}
8728 8728
8729 8729 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8730 8730 match(Set xcc (CmpL op1 op2));
8731 8731 effect( DEF xcc, USE op1, USE op2 );
8732 8732
8733 8733 size(4);
8734 8734 format %{ "CMP $op1,$op2\t\t! long" %}
8735 8735 opcode(Assembler::subcc_op3, Assembler::arith_op);
8736 8736 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8737 8737 ins_pipe(ialu_cconly_reg_reg);
8738 8738 %}
8739 8739
8740 8740 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8741 8741 match(Set xcc (CmpL op1 con));
8742 8742 effect( DEF xcc, USE op1, USE con );
8743 8743
8744 8744 size(4);
8745 8745 format %{ "CMP $op1,$con\t\t! long" %}
8746 8746 opcode(Assembler::subcc_op3, Assembler::arith_op);
8747 8747 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8748 8748 ins_pipe(ialu_cconly_reg_reg);
8749 8749 %}
8750 8750
8751 8751 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8752 8752 match(Set xcc (CmpL (AndL op1 op2) zero));
8753 8753 effect( DEF xcc, USE op1, USE op2 );
8754 8754
8755 8755 size(4);
8756 8756 format %{ "BTST $op1,$op2\t\t! long" %}
8757 8757 opcode(Assembler::andcc_op3, Assembler::arith_op);
8758 8758 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8759 8759 ins_pipe(ialu_cconly_reg_reg);
8760 8760 %}
8761 8761
8762 8762 // useful for checking the alignment of a pointer:
8763 8763 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8764 8764 match(Set xcc (CmpL (AndL op1 con) zero));
8765 8765 effect( DEF xcc, USE op1, USE con );
8766 8766
8767 8767 size(4);
8768 8768 format %{ "BTST $op1,$con\t\t! long" %}
8769 8769 opcode(Assembler::andcc_op3, Assembler::arith_op);
8770 8770 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8771 8771 ins_pipe(ialu_cconly_reg_reg);
8772 8772 %}
8773 8773
8774 8774 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8775 8775 match(Set icc (CmpU op1 op2));
8776 8776
8777 8777 size(4);
8778 8778 format %{ "CMP $op1,$op2\t! unsigned" %}
8779 8779 opcode(Assembler::subcc_op3, Assembler::arith_op);
8780 8780 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8781 8781 ins_pipe(ialu_cconly_reg_imm);
8782 8782 %}
8783 8783
8784 8784 // Compare Pointers
8785 8785 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8786 8786 match(Set pcc (CmpP op1 op2));
8787 8787
8788 8788 size(4);
8789 8789 format %{ "CMP $op1,$op2\t! ptr" %}
8790 8790 opcode(Assembler::subcc_op3, Assembler::arith_op);
8791 8791 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8792 8792 ins_pipe(ialu_cconly_reg_reg);
8793 8793 %}
8794 8794
8795 8795 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8796 8796 match(Set pcc (CmpP op1 op2));
8797 8797
8798 8798 size(4);
8799 8799 format %{ "CMP $op1,$op2\t! ptr" %}
8800 8800 opcode(Assembler::subcc_op3, Assembler::arith_op);
8801 8801 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8802 8802 ins_pipe(ialu_cconly_reg_imm);
8803 8803 %}
8804 8804
8805 8805 // Compare Narrow oops
8806 8806 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8807 8807 match(Set icc (CmpN op1 op2));
8808 8808
8809 8809 size(4);
8810 8810 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8811 8811 opcode(Assembler::subcc_op3, Assembler::arith_op);
8812 8812 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8813 8813 ins_pipe(ialu_cconly_reg_reg);
8814 8814 %}
8815 8815
8816 8816 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8817 8817 match(Set icc (CmpN op1 op2));
8818 8818
8819 8819 size(4);
8820 8820 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8821 8821 opcode(Assembler::subcc_op3, Assembler::arith_op);
8822 8822 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8823 8823 ins_pipe(ialu_cconly_reg_imm);
8824 8824 %}
8825 8825
8826 8826 //----------Max and Min--------------------------------------------------------
8827 8827 // Min Instructions
8828 8828 // Conditional move for min
8829 8829 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8830 8830 effect( USE_DEF op2, USE op1, USE icc );
8831 8831
8832 8832 size(4);
8833 8833 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8834 8834 opcode(Assembler::less);
8835 8835 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8836 8836 ins_pipe(ialu_reg_flags);
8837 8837 %}
8838 8838
8839 8839 // Min Register with Register.
8840 8840 instruct minI_eReg(iRegI op1, iRegI op2) %{
8841 8841 match(Set op2 (MinI op1 op2));
8842 8842 ins_cost(DEFAULT_COST*2);
8843 8843 expand %{
8844 8844 flagsReg icc;
8845 8845 compI_iReg(icc,op1,op2);
8846 8846 cmovI_reg_lt(op2,op1,icc);
8847 8847 %}
8848 8848 %}
8849 8849
8850 8850 // Max Instructions
8851 8851 // Conditional move for max
8852 8852 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8853 8853 effect( USE_DEF op2, USE op1, USE icc );
8854 8854 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8855 8855 opcode(Assembler::greater);
8856 8856 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8857 8857 ins_pipe(ialu_reg_flags);
8858 8858 %}
8859 8859
8860 8860 // Max Register with Register
8861 8861 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8862 8862 match(Set op2 (MaxI op1 op2));
8863 8863 ins_cost(DEFAULT_COST*2);
8864 8864 expand %{
8865 8865 flagsReg icc;
8866 8866 compI_iReg(icc,op1,op2);
8867 8867 cmovI_reg_gt(op2,op1,icc);
8868 8868 %}
8869 8869 %}
8870 8870
8871 8871
8872 8872 //----------Float Compares----------------------------------------------------
8873 8873 // Compare floating, generate condition code
8874 8874 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8875 8875 match(Set fcc (CmpF src1 src2));
8876 8876
8877 8877 size(4);
8878 8878 format %{ "FCMPs $fcc,$src1,$src2" %}
8879 8879 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8880 8880 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8881 8881 ins_pipe(faddF_fcc_reg_reg_zero);
8882 8882 %}
8883 8883
8884 8884 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8885 8885 match(Set fcc (CmpD src1 src2));
8886 8886
8887 8887 size(4);
8888 8888 format %{ "FCMPd $fcc,$src1,$src2" %}
8889 8889 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8890 8890 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8891 8891 ins_pipe(faddD_fcc_reg_reg_zero);
8892 8892 %}
8893 8893
8894 8894
8895 8895 // Compare floating, generate -1,0,1
8896 8896 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8897 8897 match(Set dst (CmpF3 src1 src2));
8898 8898 effect(KILL fcc0);
8899 8899 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8900 8900 format %{ "fcmpl $dst,$src1,$src2" %}
8901 8901 // Primary = float
8902 8902 opcode( true );
8903 8903 ins_encode( floating_cmp( dst, src1, src2 ) );
8904 8904 ins_pipe( floating_cmp );
8905 8905 %}
8906 8906
8907 8907 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8908 8908 match(Set dst (CmpD3 src1 src2));
8909 8909 effect(KILL fcc0);
8910 8910 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8911 8911 format %{ "dcmpl $dst,$src1,$src2" %}
8912 8912 // Primary = double (not float)
8913 8913 opcode( false );
8914 8914 ins_encode( floating_cmp( dst, src1, src2 ) );
8915 8915 ins_pipe( floating_cmp );
8916 8916 %}
8917 8917
8918 8918 //----------Branches---------------------------------------------------------
8919 8919 // Jump
8920 8920 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8921 8921 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8922 8922 match(Jump switch_val);
8923 8923
8924 8924 ins_cost(350);
8925 8925
8926 8926 format %{ "SETHI [hi(table_base)],O7\n\t"
8927 8927 "ADD O7, lo(table_base), O7\n\t"
8928 8928 "LD [O7+$switch_val], O7\n\t"
8929 8929 "JUMP O7"
8930 8930 %}
8931 8931 ins_encode( jump_enc( switch_val, table) );
8932 8932 ins_pc_relative(1);
8933 8933 ins_pipe(ialu_reg_reg);
8934 8934 %}
8935 8935
8936 8936 // Direct Branch. Use V8 version with longer range.
8937 8937 instruct branch(label labl) %{
8938 8938 match(Goto);
8939 8939 effect(USE labl);
8940 8940
8941 8941 size(8);
8942 8942 ins_cost(BRANCH_COST);
8943 8943 format %{ "BA $labl" %}
8944 8944 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8945 8945 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8946 8946 ins_encode( enc_ba( labl ) );
8947 8947 ins_pc_relative(1);
8948 8948 ins_pipe(br);
8949 8949 %}
8950 8950
8951 8951 // Conditional Direct Branch
8952 8952 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8953 8953 match(If cmp icc);
8954 8954 effect(USE labl);
8955 8955
8956 8956 size(8);
8957 8957 ins_cost(BRANCH_COST);
8958 8958 format %{ "BP$cmp $icc,$labl" %}
8959 8959 // Prim = bits 24-22, Secnd = bits 31-30
8960 8960 ins_encode( enc_bp( labl, cmp, icc ) );
8961 8961 ins_pc_relative(1);
8962 8962 ins_pipe(br_cc);
8963 8963 %}
8964 8964
8965 8965 // Branch-on-register tests all 64 bits. We assume that values
8966 8966 // in 64-bit registers always remains zero or sign extended
8967 8967 // unless our code munges the high bits. Interrupts can chop
8968 8968 // the high order bits to zero or sign at any time.
8969 8969 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8970 8970 match(If cmp (CmpI op1 zero));
8971 8971 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8972 8972 effect(USE labl);
8973 8973
8974 8974 size(8);
8975 8975 ins_cost(BRANCH_COST);
8976 8976 format %{ "BR$cmp $op1,$labl" %}
8977 8977 ins_encode( enc_bpr( labl, cmp, op1 ) );
8978 8978 ins_pc_relative(1);
8979 8979 ins_pipe(br_reg);
8980 8980 %}
8981 8981
8982 8982 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8983 8983 match(If cmp (CmpP op1 null));
8984 8984 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8985 8985 effect(USE labl);
8986 8986
8987 8987 size(8);
8988 8988 ins_cost(BRANCH_COST);
8989 8989 format %{ "BR$cmp $op1,$labl" %}
8990 8990 ins_encode( enc_bpr( labl, cmp, op1 ) );
8991 8991 ins_pc_relative(1);
8992 8992 ins_pipe(br_reg);
8993 8993 %}
8994 8994
8995 8995 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8996 8996 match(If cmp (CmpL op1 zero));
8997 8997 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8998 8998 effect(USE labl);
8999 8999
9000 9000 size(8);
9001 9001 ins_cost(BRANCH_COST);
9002 9002 format %{ "BR$cmp $op1,$labl" %}
9003 9003 ins_encode( enc_bpr( labl, cmp, op1 ) );
9004 9004 ins_pc_relative(1);
9005 9005 ins_pipe(br_reg);
9006 9006 %}
9007 9007
9008 9008 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9009 9009 match(If cmp icc);
9010 9010 effect(USE labl);
9011 9011
9012 9012 format %{ "BP$cmp $icc,$labl" %}
9013 9013 // Prim = bits 24-22, Secnd = bits 31-30
9014 9014 ins_encode( enc_bp( labl, cmp, icc ) );
9015 9015 ins_pc_relative(1);
9016 9016 ins_pipe(br_cc);
9017 9017 %}
9018 9018
9019 9019 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9020 9020 match(If cmp pcc);
9021 9021 effect(USE labl);
9022 9022
9023 9023 size(8);
9024 9024 ins_cost(BRANCH_COST);
9025 9025 format %{ "BP$cmp $pcc,$labl" %}
9026 9026 // Prim = bits 24-22, Secnd = bits 31-30
9027 9027 ins_encode( enc_bpx( labl, cmp, pcc ) );
9028 9028 ins_pc_relative(1);
9029 9029 ins_pipe(br_cc);
9030 9030 %}
9031 9031
9032 9032 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9033 9033 match(If cmp fcc);
9034 9034 effect(USE labl);
9035 9035
9036 9036 size(8);
9037 9037 ins_cost(BRANCH_COST);
9038 9038 format %{ "FBP$cmp $fcc,$labl" %}
9039 9039 // Prim = bits 24-22, Secnd = bits 31-30
9040 9040 ins_encode( enc_fbp( labl, cmp, fcc ) );
9041 9041 ins_pc_relative(1);
9042 9042 ins_pipe(br_fcc);
9043 9043 %}
9044 9044
9045 9045 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9046 9046 match(CountedLoopEnd cmp icc);
9047 9047 effect(USE labl);
9048 9048
9049 9049 size(8);
9050 9050 ins_cost(BRANCH_COST);
9051 9051 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9052 9052 // Prim = bits 24-22, Secnd = bits 31-30
9053 9053 ins_encode( enc_bp( labl, cmp, icc ) );
9054 9054 ins_pc_relative(1);
9055 9055 ins_pipe(br_cc);
9056 9056 %}
9057 9057
9058 9058 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9059 9059 match(CountedLoopEnd cmp icc);
9060 9060 effect(USE labl);
9061 9061
9062 9062 size(8);
9063 9063 ins_cost(BRANCH_COST);
9064 9064 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9065 9065 // Prim = bits 24-22, Secnd = bits 31-30
9066 9066 ins_encode( enc_bp( labl, cmp, icc ) );
9067 9067 ins_pc_relative(1);
9068 9068 ins_pipe(br_cc);
9069 9069 %}
9070 9070
9071 9071 // ============================================================================
9072 9072 // Long Compare
9073 9073 //
9074 9074 // Currently we hold longs in 2 registers. Comparing such values efficiently
9075 9075 // is tricky. The flavor of compare used depends on whether we are testing
9076 9076 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9077 9077 // The GE test is the negated LT test. The LE test can be had by commuting
9078 9078 // the operands (yielding a GE test) and then negating; negate again for the
9079 9079 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9080 9080 // NE test is negated from that.
9081 9081
9082 9082 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9083 9083 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9084 9084 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9085 9085 // are collapsed internally in the ADLC's dfa-gen code. The match for
9086 9086 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9087 9087 // foo match ends up with the wrong leaf. One fix is to not match both
9088 9088 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9089 9089 // both forms beat the trinary form of long-compare and both are very useful
9090 9090 // on Intel which has so few registers.
9091 9091
9092 9092 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9093 9093 match(If cmp xcc);
9094 9094 effect(USE labl);
9095 9095
9096 9096 size(8);
9097 9097 ins_cost(BRANCH_COST);
9098 9098 format %{ "BP$cmp $xcc,$labl" %}
9099 9099 // Prim = bits 24-22, Secnd = bits 31-30
9100 9100 ins_encode( enc_bpl( labl, cmp, xcc ) );
9101 9101 ins_pc_relative(1);
9102 9102 ins_pipe(br_cc);
9103 9103 %}
9104 9104
9105 9105 // Manifest a CmpL3 result in an integer register. Very painful.
9106 9106 // This is the test to avoid.
9107 9107 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9108 9108 match(Set dst (CmpL3 src1 src2) );
9109 9109 effect( KILL ccr );
9110 9110 ins_cost(6*DEFAULT_COST);
9111 9111 size(24);
9112 9112 format %{ "CMP $src1,$src2\t\t! long\n"
9113 9113 "\tBLT,a,pn done\n"
9114 9114 "\tMOV -1,$dst\t! delay slot\n"
9115 9115 "\tBGT,a,pn done\n"
9116 9116 "\tMOV 1,$dst\t! delay slot\n"
9117 9117 "\tCLR $dst\n"
9118 9118 "done:" %}
9119 9119 ins_encode( cmpl_flag(src1,src2,dst) );
9120 9120 ins_pipe(cmpL_reg);
9121 9121 %}
9122 9122
9123 9123 // Conditional move
9124 9124 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9125 9125 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9126 9126 ins_cost(150);
9127 9127 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9128 9128 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9129 9129 ins_pipe(ialu_reg);
9130 9130 %}
9131 9131
9132 9132 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9133 9133 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9134 9134 ins_cost(140);
9135 9135 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9136 9136 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9137 9137 ins_pipe(ialu_imm);
9138 9138 %}
9139 9139
9140 9140 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9141 9141 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9142 9142 ins_cost(150);
9143 9143 format %{ "MOV$cmp $xcc,$src,$dst" %}
9144 9144 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9145 9145 ins_pipe(ialu_reg);
9146 9146 %}
9147 9147
9148 9148 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9149 9149 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9150 9150 ins_cost(140);
9151 9151 format %{ "MOV$cmp $xcc,$src,$dst" %}
9152 9152 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9153 9153 ins_pipe(ialu_imm);
9154 9154 %}
9155 9155
9156 9156 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9157 9157 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9158 9158 ins_cost(150);
9159 9159 format %{ "MOV$cmp $xcc,$src,$dst" %}
9160 9160 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9161 9161 ins_pipe(ialu_reg);
9162 9162 %}
9163 9163
9164 9164 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9165 9165 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9166 9166 ins_cost(150);
9167 9167 format %{ "MOV$cmp $xcc,$src,$dst" %}
9168 9168 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9169 9169 ins_pipe(ialu_reg);
9170 9170 %}
9171 9171
9172 9172 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9173 9173 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9174 9174 ins_cost(140);
9175 9175 format %{ "MOV$cmp $xcc,$src,$dst" %}
9176 9176 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9177 9177 ins_pipe(ialu_imm);
9178 9178 %}
9179 9179
9180 9180 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9181 9181 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9182 9182 ins_cost(150);
9183 9183 opcode(0x101);
9184 9184 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9185 9185 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9186 9186 ins_pipe(int_conditional_float_move);
9187 9187 %}
9188 9188
9189 9189 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9190 9190 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9191 9191 ins_cost(150);
9192 9192 opcode(0x102);
9193 9193 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9194 9194 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9195 9195 ins_pipe(int_conditional_float_move);
9196 9196 %}
9197 9197
9198 9198 // ============================================================================
9199 9199 // Safepoint Instruction
9200 9200 instruct safePoint_poll(iRegP poll) %{
9201 9201 match(SafePoint poll);
9202 9202 effect(USE poll);
9203 9203
9204 9204 size(4);
9205 9205 #ifdef _LP64
9206 9206 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9207 9207 #else
9208 9208 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9209 9209 #endif
9210 9210 ins_encode %{
9211 9211 __ relocate(relocInfo::poll_type);
9212 9212 __ ld_ptr($poll$$Register, 0, G0);
9213 9213 %}
9214 9214 ins_pipe(loadPollP);
9215 9215 %}
9216 9216
9217 9217 // ============================================================================
9218 9218 // Call Instructions
9219 9219 // Call Java Static Instruction
9220 9220 instruct CallStaticJavaDirect( method meth ) %{
9221 9221 match(CallStaticJava);
9222 9222 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9223 9223 effect(USE meth);
9224 9224
9225 9225 size(8);
9226 9226 ins_cost(CALL_COST);
9227 9227 format %{ "CALL,static ; NOP ==> " %}
9228 9228 ins_encode( Java_Static_Call( meth ), call_epilog );
9229 9229 ins_pc_relative(1);
9230 9230 ins_pipe(simple_call);
9231 9231 %}
9232 9232
9233 9233 // Call Java Static Instruction (method handle version)
9234 9234 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9235 9235 match(CallStaticJava);
9236 9236 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9237 9237 effect(USE meth, KILL l7_mh_SP_save);
9238 9238
9239 9239 size(8);
9240 9240 ins_cost(CALL_COST);
9241 9241 format %{ "CALL,static/MethodHandle" %}
9242 9242 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9243 9243 ins_pc_relative(1);
9244 9244 ins_pipe(simple_call);
9245 9245 %}
9246 9246
9247 9247 // Call Java Dynamic Instruction
9248 9248 instruct CallDynamicJavaDirect( method meth ) %{
9249 9249 match(CallDynamicJava);
9250 9250 effect(USE meth);
9251 9251
9252 9252 ins_cost(CALL_COST);
9253 9253 format %{ "SET (empty),R_G5\n\t"
9254 9254 "CALL,dynamic ; NOP ==> " %}
9255 9255 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9256 9256 ins_pc_relative(1);
9257 9257 ins_pipe(call);
9258 9258 %}
9259 9259
9260 9260 // Call Runtime Instruction
9261 9261 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9262 9262 match(CallRuntime);
9263 9263 effect(USE meth, KILL l7);
9264 9264 ins_cost(CALL_COST);
9265 9265 format %{ "CALL,runtime" %}
9266 9266 ins_encode( Java_To_Runtime( meth ),
9267 9267 call_epilog, adjust_long_from_native_call );
9268 9268 ins_pc_relative(1);
9269 9269 ins_pipe(simple_call);
9270 9270 %}
9271 9271
9272 9272 // Call runtime without safepoint - same as CallRuntime
9273 9273 instruct CallLeafDirect(method meth, l7RegP l7) %{
9274 9274 match(CallLeaf);
9275 9275 effect(USE meth, KILL l7);
9276 9276 ins_cost(CALL_COST);
9277 9277 format %{ "CALL,runtime leaf" %}
9278 9278 ins_encode( Java_To_Runtime( meth ),
9279 9279 call_epilog,
9280 9280 adjust_long_from_native_call );
9281 9281 ins_pc_relative(1);
9282 9282 ins_pipe(simple_call);
9283 9283 %}
9284 9284
9285 9285 // Call runtime without safepoint - same as CallLeaf
9286 9286 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9287 9287 match(CallLeafNoFP);
9288 9288 effect(USE meth, KILL l7);
9289 9289 ins_cost(CALL_COST);
9290 9290 format %{ "CALL,runtime leaf nofp" %}
9291 9291 ins_encode( Java_To_Runtime( meth ),
9292 9292 call_epilog,
9293 9293 adjust_long_from_native_call );
9294 9294 ins_pc_relative(1);
9295 9295 ins_pipe(simple_call);
9296 9296 %}
9297 9297
9298 9298 // Tail Call; Jump from runtime stub to Java code.
9299 9299 // Also known as an 'interprocedural jump'.
9300 9300 // Target of jump will eventually return to caller.
9301 9301 // TailJump below removes the return address.
9302 9302 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9303 9303 match(TailCall jump_target method_oop );
9304 9304
9305 9305 ins_cost(CALL_COST);
9306 9306 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9307 9307 ins_encode(form_jmpl(jump_target));
9308 9308 ins_pipe(tail_call);
9309 9309 %}
9310 9310
9311 9311
9312 9312 // Return Instruction
9313 9313 instruct Ret() %{
9314 9314 match(Return);
9315 9315
9316 9316 // The epilogue node did the ret already.
9317 9317 size(0);
9318 9318 format %{ "! return" %}
9319 9319 ins_encode();
9320 9320 ins_pipe(empty);
9321 9321 %}
9322 9322
9323 9323
9324 9324 // Tail Jump; remove the return address; jump to target.
9325 9325 // TailCall above leaves the return address around.
9326 9326 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9327 9327 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9328 9328 // "restore" before this instruction (in Epilogue), we need to materialize it
9329 9329 // in %i0.
9330 9330 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9331 9331 match( TailJump jump_target ex_oop );
9332 9332 ins_cost(CALL_COST);
9333 9333 format %{ "! discard R_O7\n\t"
9334 9334 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9335 9335 ins_encode(form_jmpl_set_exception_pc(jump_target));
9336 9336 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9337 9337 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9338 9338 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9339 9339 ins_pipe(tail_call);
9340 9340 %}
9341 9341
9342 9342 // Create exception oop: created by stack-crawling runtime code.
9343 9343 // Created exception is now available to this handler, and is setup
9344 9344 // just prior to jumping to this handler. No code emitted.
9345 9345 instruct CreateException( o0RegP ex_oop )
9346 9346 %{
9347 9347 match(Set ex_oop (CreateEx));
9348 9348 ins_cost(0);
9349 9349
9350 9350 size(0);
9351 9351 // use the following format syntax
9352 9352 format %{ "! exception oop is in R_O0; no code emitted" %}
9353 9353 ins_encode();
9354 9354 ins_pipe(empty);
9355 9355 %}
9356 9356
9357 9357
9358 9358 // Rethrow exception:
9359 9359 // The exception oop will come in the first argument position.
9360 9360 // Then JUMP (not call) to the rethrow stub code.
9361 9361 instruct RethrowException()
9362 9362 %{
9363 9363 match(Rethrow);
9364 9364 ins_cost(CALL_COST);
9365 9365
9366 9366 // use the following format syntax
9367 9367 format %{ "Jmp rethrow_stub" %}
9368 9368 ins_encode(enc_rethrow);
9369 9369 ins_pipe(tail_call);
9370 9370 %}
9371 9371
9372 9372
9373 9373 // Die now
9374 9374 instruct ShouldNotReachHere( )
9375 9375 %{
9376 9376 match(Halt);
9377 9377 ins_cost(CALL_COST);
9378 9378
9379 9379 size(4);
9380 9380 // Use the following format syntax
9381 9381 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9382 9382 ins_encode( form2_illtrap() );
9383 9383 ins_pipe(tail_call);
9384 9384 %}
9385 9385
9386 9386 // ============================================================================
9387 9387 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9388 9388 // array for an instance of the superklass. Set a hidden internal cache on a
9389 9389 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9390 9390 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9391 9391 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9392 9392 match(Set index (PartialSubtypeCheck sub super));
9393 9393 effect( KILL pcc, KILL o7 );
9394 9394 ins_cost(DEFAULT_COST*10);
9395 9395 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9396 9396 ins_encode( enc_PartialSubtypeCheck() );
9397 9397 ins_pipe(partial_subtype_check_pipe);
9398 9398 %}
9399 9399
9400 9400 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9401 9401 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9402 9402 effect( KILL idx, KILL o7 );
9403 9403 ins_cost(DEFAULT_COST*10);
9404 9404 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9405 9405 ins_encode( enc_PartialSubtypeCheck() );
9406 9406 ins_pipe(partial_subtype_check_pipe);
9407 9407 %}
9408 9408
9409 9409
9410 9410 // ============================================================================
9411 9411 // inlined locking and unlocking
9412 9412
9413 9413 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9414 9414 match(Set pcc (FastLock object box));
9415 9415
9416 9416 effect(KILL scratch, TEMP scratch2);
9417 9417 ins_cost(100);
9418 9418
9419 9419 size(4*112); // conservative overestimation ...
9420 9420 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9421 9421 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9422 9422 ins_pipe(long_memory_op);
9423 9423 %}
9424 9424
9425 9425
9426 9426 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9427 9427 match(Set pcc (FastUnlock object box));
9428 9428 effect(KILL scratch, TEMP scratch2);
9429 9429 ins_cost(100);
9430 9430
9431 9431 size(4*120); // conservative overestimation ...
9432 9432 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9433 9433 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9434 9434 ins_pipe(long_memory_op);
9435 9435 %}
9436 9436
9437 9437 // Count and Base registers are fixed because the allocator cannot
9438 9438 // kill unknown registers. The encodings are generic.
9439 9439 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9440 9440 match(Set dummy (ClearArray cnt base));
9441 9441 effect(TEMP temp, KILL ccr);
9442 9442 ins_cost(300);
9443 9443 format %{ "MOV $cnt,$temp\n"
9444 9444 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9445 9445 " BRge loop\t\t! Clearing loop\n"
9446 9446 " STX G0,[$base+$temp]\t! delay slot" %}
9447 9447 ins_encode( enc_Clear_Array(cnt, base, temp) );
9448 9448 ins_pipe(long_memory_op);
9449 9449 %}
9450 9450
9451 9451 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9452 9452 o7RegI tmp, flagsReg ccr) %{
9453 9453 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9454 9454 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9455 9455 ins_cost(300);
9456 9456 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9457 9457 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9458 9458 ins_pipe(long_memory_op);
9459 9459 %}
9460 9460
9461 9461 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9462 9462 o7RegI tmp, flagsReg ccr) %{
9463 9463 match(Set result (StrEquals (Binary str1 str2) cnt));
9464 9464 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9465 9465 ins_cost(300);
9466 9466 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9467 9467 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9468 9468 ins_pipe(long_memory_op);
9469 9469 %}
9470 9470
9471 9471 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9472 9472 o7RegI tmp2, flagsReg ccr) %{
9473 9473 match(Set result (AryEq ary1 ary2));
9474 9474 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9475 9475 ins_cost(300);
9476 9476 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9477 9477 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9478 9478 ins_pipe(long_memory_op);
9479 9479 %}
9480 9480
9481 9481
9482 9482 //---------- Zeros Count Instructions ------------------------------------------
9483 9483
9484 9484 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9485 9485 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9486 9486 match(Set dst (CountLeadingZerosI src));
9487 9487 effect(TEMP dst, TEMP tmp, KILL cr);
9488 9488
9489 9489 // x |= (x >> 1);
9490 9490 // x |= (x >> 2);
9491 9491 // x |= (x >> 4);
9492 9492 // x |= (x >> 8);
9493 9493 // x |= (x >> 16);
9494 9494 // return (WORDBITS - popc(x));
9495 9495 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9496 9496 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9497 9497 "OR $dst,$tmp,$dst\n\t"
9498 9498 "SRL $dst,2,$tmp\n\t"
9499 9499 "OR $dst,$tmp,$dst\n\t"
9500 9500 "SRL $dst,4,$tmp\n\t"
9501 9501 "OR $dst,$tmp,$dst\n\t"
9502 9502 "SRL $dst,8,$tmp\n\t"
9503 9503 "OR $dst,$tmp,$dst\n\t"
9504 9504 "SRL $dst,16,$tmp\n\t"
9505 9505 "OR $dst,$tmp,$dst\n\t"
9506 9506 "POPC $dst,$dst\n\t"
9507 9507 "MOV 32,$tmp\n\t"
9508 9508 "SUB $tmp,$dst,$dst" %}
9509 9509 ins_encode %{
9510 9510 Register Rdst = $dst$$Register;
9511 9511 Register Rsrc = $src$$Register;
9512 9512 Register Rtmp = $tmp$$Register;
9513 9513 __ srl(Rsrc, 1, Rtmp);
9514 9514 __ srl(Rsrc, 0, Rdst);
9515 9515 __ or3(Rdst, Rtmp, Rdst);
9516 9516 __ srl(Rdst, 2, Rtmp);
9517 9517 __ or3(Rdst, Rtmp, Rdst);
9518 9518 __ srl(Rdst, 4, Rtmp);
9519 9519 __ or3(Rdst, Rtmp, Rdst);
9520 9520 __ srl(Rdst, 8, Rtmp);
|
↓ open down ↓ |
9520 lines elided |
↑ open up ↑ |
9521 9521 __ or3(Rdst, Rtmp, Rdst);
9522 9522 __ srl(Rdst, 16, Rtmp);
9523 9523 __ or3(Rdst, Rtmp, Rdst);
9524 9524 __ popc(Rdst, Rdst);
9525 9525 __ mov(BitsPerInt, Rtmp);
9526 9526 __ sub(Rtmp, Rdst, Rdst);
9527 9527 %}
9528 9528 ins_pipe(ialu_reg);
9529 9529 %}
9530 9530
9531 -instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9531 +instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, iRegL tmp2, flagsReg cr) %{
9532 9532 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9533 9533 match(Set dst (CountLeadingZerosL src));
9534 - effect(TEMP dst, TEMP tmp, KILL cr);
9534 + effect(TEMP dst, TEMP tmp, TEMP tmp2, KILL cr);
9535 9535
9536 9536 // x |= (x >> 1);
9537 9537 // x |= (x >> 2);
9538 9538 // x |= (x >> 4);
9539 9539 // x |= (x >> 8);
9540 9540 // x |= (x >> 16);
9541 9541 // x |= (x >> 32);
9542 9542 // return (WORDBITS - popc(x));
9543 9543 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9544 - "OR $src,$tmp,$dst\n\t"
9545 - "SRLX $dst,2,$tmp\n\t"
9546 - "OR $dst,$tmp,$dst\n\t"
9547 - "SRLX $dst,4,$tmp\n\t"
9548 - "OR $dst,$tmp,$dst\n\t"
9549 - "SRLX $dst,8,$tmp\n\t"
9550 - "OR $dst,$tmp,$dst\n\t"
9551 - "SRLX $dst,16,$tmp\n\t"
9552 - "OR $dst,$tmp,$dst\n\t"
9553 - "SRLX $dst,32,$tmp\n\t"
9554 - "OR $dst,$tmp,$dst\n\t"
9555 - "POPC $dst,$dst\n\t"
9544 + "OR $src,$tmp,$tmp2\n\t"
9545 + "SRLX $tmp2,2,$tmp\n\t"
9546 + "OR $tmp2,$tmp,$tmp2\n\t"
9547 + "SRLX $tmp2,4,$tmp\n\t"
9548 + "OR $tmp2,$tmp,$tmp2\n\t"
9549 + "SRLX $tmp2,8,$tmp\n\t"
9550 + "OR $tmp2,$tmp,$tmp2\n\t"
9551 + "SRLX $tmp2,16,$tmp\n\t"
9552 + "OR $tmp2,$tmp,$tmp2\n\t"
9553 + "SRLX $tmp2,32,$tmp\n\t"
9554 + "OR $tmp2,$tmp,$tmp2\n\t"
9555 + "POPC $tmp2,$dst\n\t"
9556 9556 "MOV 64,$tmp\n\t"
9557 9557 "SUB $tmp,$dst,$dst" %}
9558 9558 ins_encode %{
9559 - Register Rdst = $dst$$Register;
9560 - Register Rsrc = $src$$Register;
9561 - Register Rtmp = $tmp$$Register;
9562 - __ srlx(Rsrc, 1, Rtmp);
9563 - __ or3(Rsrc, Rtmp, Rdst);
9564 - __ srlx(Rdst, 2, Rtmp);
9565 - __ or3(Rdst, Rtmp, Rdst);
9566 - __ srlx(Rdst, 4, Rtmp);
9567 - __ or3(Rdst, Rtmp, Rdst);
9568 - __ srlx(Rdst, 8, Rtmp);
9569 - __ or3(Rdst, Rtmp, Rdst);
9570 - __ srlx(Rdst, 16, Rtmp);
9571 - __ or3(Rdst, Rtmp, Rdst);
9572 - __ srlx(Rdst, 32, Rtmp);
9573 - __ or3(Rdst, Rtmp, Rdst);
9574 - __ popc(Rdst, Rdst);
9559 + Register Rdst = $dst$$Register;
9560 + Register Rsrc = $src$$Register;
9561 + Register Rtmp = $tmp$$Register;
9562 + Register Rtmp2 = $tmp2$$Register;
9563 + __ srlx(Rsrc, 1, Rtmp);
9564 + __ or3( Rsrc, Rtmp, Rtmp2);
9565 + __ srlx(Rtmp2, 2, Rtmp);
9566 + __ or3( Rtmp2, Rtmp, Rtmp2);
9567 + __ srlx(Rtmp2, 4, Rtmp);
9568 + __ or3( Rtmp2, Rtmp, Rtmp2);
9569 + __ srlx(Rtmp2, 8, Rtmp);
9570 + __ or3( Rtmp2, Rtmp, Rtmp2);
9571 + __ srlx(Rtmp2, 16, Rtmp);
9572 + __ or3( Rtmp2, Rtmp, Rtmp2);
9573 + __ srlx(Rtmp2, 32, Rtmp);
9574 + __ or3( Rtmp2, Rtmp, Rtmp2);
9575 + __ popc(Rtmp2, Rdst);
9575 9576 __ mov(BitsPerLong, Rtmp);
9576 9577 __ sub(Rtmp, Rdst, Rdst);
9577 9578 %}
9578 9579 ins_pipe(ialu_reg);
9579 9580 %}
9580 9581
9581 9582 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9582 9583 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9583 9584 match(Set dst (CountTrailingZerosI src));
9584 9585 effect(TEMP dst, KILL cr);
9585 9586
9586 9587 // return popc(~x & (x - 1));
9587 9588 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9588 9589 "ANDN $dst,$src,$dst\n\t"
9589 9590 "SRL $dst,R_G0,$dst\n\t"
9590 9591 "POPC $dst,$dst" %}
9591 9592 ins_encode %{
9592 9593 Register Rdst = $dst$$Register;
9593 9594 Register Rsrc = $src$$Register;
9594 9595 __ sub(Rsrc, 1, Rdst);
9595 9596 __ andn(Rdst, Rsrc, Rdst);
9596 9597 __ srl(Rdst, G0, Rdst);
9597 9598 __ popc(Rdst, Rdst);
9598 9599 %}
9599 9600 ins_pipe(ialu_reg);
9600 9601 %}
9601 9602
9602 9603 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9603 9604 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9604 9605 match(Set dst (CountTrailingZerosL src));
9605 9606 effect(TEMP dst, KILL cr);
9606 9607
9607 9608 // return popc(~x & (x - 1));
9608 9609 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9609 9610 "ANDN $dst,$src,$dst\n\t"
9610 9611 "POPC $dst,$dst" %}
9611 9612 ins_encode %{
9612 9613 Register Rdst = $dst$$Register;
9613 9614 Register Rsrc = $src$$Register;
9614 9615 __ sub(Rsrc, 1, Rdst);
9615 9616 __ andn(Rdst, Rsrc, Rdst);
9616 9617 __ popc(Rdst, Rdst);
9617 9618 %}
9618 9619 ins_pipe(ialu_reg);
9619 9620 %}
9620 9621
9621 9622
9622 9623 //---------- Population Count Instructions -------------------------------------
9623 9624
9624 9625 instruct popCountI(iRegI dst, iRegI src) %{
9625 9626 predicate(UsePopCountInstruction);
9626 9627 match(Set dst (PopCountI src));
9627 9628
9628 9629 format %{ "POPC $src, $dst" %}
9629 9630 ins_encode %{
9630 9631 __ popc($src$$Register, $dst$$Register);
9631 9632 %}
9632 9633 ins_pipe(ialu_reg);
9633 9634 %}
9634 9635
9635 9636 // Note: Long.bitCount(long) returns an int.
9636 9637 instruct popCountL(iRegI dst, iRegL src) %{
9637 9638 predicate(UsePopCountInstruction);
9638 9639 match(Set dst (PopCountL src));
9639 9640
9640 9641 format %{ "POPC $src, $dst" %}
9641 9642 ins_encode %{
9642 9643 __ popc($src$$Register, $dst$$Register);
9643 9644 %}
9644 9645 ins_pipe(ialu_reg);
9645 9646 %}
9646 9647
9647 9648
9648 9649 // ============================================================================
9649 9650 //------------Bytes reverse--------------------------------------------------
9650 9651
9651 9652 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9652 9653 match(Set dst (ReverseBytesI src));
9653 9654
9654 9655 // Op cost is artificially doubled to make sure that load or store
9655 9656 // instructions are preferred over this one which requires a spill
9656 9657 // onto a stack slot.
9657 9658 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9658 9659 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9659 9660
9660 9661 ins_encode %{
9661 9662 __ set($src$$disp + STACK_BIAS, O7);
9662 9663 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9663 9664 %}
9664 9665 ins_pipe( iload_mem );
9665 9666 %}
9666 9667
9667 9668 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9668 9669 match(Set dst (ReverseBytesL src));
9669 9670
9670 9671 // Op cost is artificially doubled to make sure that load or store
9671 9672 // instructions are preferred over this one which requires a spill
9672 9673 // onto a stack slot.
9673 9674 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9674 9675 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9675 9676
9676 9677 ins_encode %{
9677 9678 __ set($src$$disp + STACK_BIAS, O7);
9678 9679 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9679 9680 %}
9680 9681 ins_pipe( iload_mem );
9681 9682 %}
9682 9683
9683 9684 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9684 9685 match(Set dst (ReverseBytesUS src));
9685 9686
9686 9687 // Op cost is artificially doubled to make sure that load or store
9687 9688 // instructions are preferred over this one which requires a spill
9688 9689 // onto a stack slot.
9689 9690 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9690 9691 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9691 9692
9692 9693 ins_encode %{
9693 9694 // the value was spilled as an int so bias the load
9694 9695 __ set($src$$disp + STACK_BIAS + 2, O7);
9695 9696 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9696 9697 %}
9697 9698 ins_pipe( iload_mem );
9698 9699 %}
9699 9700
9700 9701 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9701 9702 match(Set dst (ReverseBytesS src));
9702 9703
9703 9704 // Op cost is artificially doubled to make sure that load or store
9704 9705 // instructions are preferred over this one which requires a spill
9705 9706 // onto a stack slot.
9706 9707 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9707 9708 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9708 9709
9709 9710 ins_encode %{
9710 9711 // the value was spilled as an int so bias the load
9711 9712 __ set($src$$disp + STACK_BIAS + 2, O7);
9712 9713 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9713 9714 %}
9714 9715 ins_pipe( iload_mem );
9715 9716 %}
9716 9717
9717 9718 // Load Integer reversed byte order
9718 9719 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9719 9720 match(Set dst (ReverseBytesI (LoadI src)));
9720 9721
9721 9722 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9722 9723 size(4);
9723 9724 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9724 9725
9725 9726 ins_encode %{
9726 9727 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9727 9728 %}
9728 9729 ins_pipe(iload_mem);
9729 9730 %}
9730 9731
9731 9732 // Load Long - aligned and reversed
9732 9733 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9733 9734 match(Set dst (ReverseBytesL (LoadL src)));
9734 9735
9735 9736 ins_cost(MEMORY_REF_COST);
9736 9737 size(4);
9737 9738 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9738 9739
9739 9740 ins_encode %{
9740 9741 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9741 9742 %}
9742 9743 ins_pipe(iload_mem);
9743 9744 %}
9744 9745
9745 9746 // Load unsigned short / char reversed byte order
9746 9747 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9747 9748 match(Set dst (ReverseBytesUS (LoadUS src)));
9748 9749
9749 9750 ins_cost(MEMORY_REF_COST);
9750 9751 size(4);
9751 9752 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9752 9753
9753 9754 ins_encode %{
9754 9755 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9755 9756 %}
9756 9757 ins_pipe(iload_mem);
9757 9758 %}
9758 9759
9759 9760 // Load short reversed byte order
9760 9761 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
9761 9762 match(Set dst (ReverseBytesS (LoadS src)));
9762 9763
9763 9764 ins_cost(MEMORY_REF_COST);
9764 9765 size(4);
9765 9766 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9766 9767
9767 9768 ins_encode %{
9768 9769 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9769 9770 %}
9770 9771 ins_pipe(iload_mem);
9771 9772 %}
9772 9773
9773 9774 // Store Integer reversed byte order
9774 9775 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
9775 9776 match(Set dst (StoreI dst (ReverseBytesI src)));
9776 9777
9777 9778 ins_cost(MEMORY_REF_COST);
9778 9779 size(4);
9779 9780 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9780 9781
9781 9782 ins_encode %{
9782 9783 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9783 9784 %}
9784 9785 ins_pipe(istore_mem_reg);
9785 9786 %}
9786 9787
9787 9788 // Store Long reversed byte order
9788 9789 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
9789 9790 match(Set dst (StoreL dst (ReverseBytesL src)));
9790 9791
9791 9792 ins_cost(MEMORY_REF_COST);
9792 9793 size(4);
9793 9794 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9794 9795
9795 9796 ins_encode %{
9796 9797 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9797 9798 %}
9798 9799 ins_pipe(istore_mem_reg);
9799 9800 %}
9800 9801
9801 9802 // Store unsighed short/char reversed byte order
9802 9803 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
9803 9804 match(Set dst (StoreC dst (ReverseBytesUS src)));
9804 9805
9805 9806 ins_cost(MEMORY_REF_COST);
9806 9807 size(4);
9807 9808 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9808 9809
9809 9810 ins_encode %{
9810 9811 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9811 9812 %}
9812 9813 ins_pipe(istore_mem_reg);
9813 9814 %}
9814 9815
9815 9816 // Store short reversed byte order
9816 9817 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
9817 9818 match(Set dst (StoreC dst (ReverseBytesS src)));
9818 9819
9819 9820 ins_cost(MEMORY_REF_COST);
9820 9821 size(4);
9821 9822 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9822 9823
9823 9824 ins_encode %{
9824 9825 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9825 9826 %}
9826 9827 ins_pipe(istore_mem_reg);
9827 9828 %}
9828 9829
9829 9830 //----------PEEPHOLE RULES-----------------------------------------------------
9830 9831 // These must follow all instruction definitions as they use the names
9831 9832 // defined in the instructions definitions.
9832 9833 //
9833 9834 // peepmatch ( root_instr_name [preceding_instruction]* );
9834 9835 //
9835 9836 // peepconstraint %{
9836 9837 // (instruction_number.operand_name relational_op instruction_number.operand_name
9837 9838 // [, ...] );
9838 9839 // // instruction numbers are zero-based using left to right order in peepmatch
9839 9840 //
9840 9841 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9841 9842 // // provide an instruction_number.operand_name for each operand that appears
9842 9843 // // in the replacement instruction's match rule
9843 9844 //
9844 9845 // ---------VM FLAGS---------------------------------------------------------
9845 9846 //
9846 9847 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9847 9848 //
9848 9849 // Each peephole rule is given an identifying number starting with zero and
9849 9850 // increasing by one in the order seen by the parser. An individual peephole
9850 9851 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9851 9852 // on the command-line.
9852 9853 //
9853 9854 // ---------CURRENT LIMITATIONS----------------------------------------------
9854 9855 //
9855 9856 // Only match adjacent instructions in same basic block
9856 9857 // Only equality constraints
9857 9858 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9858 9859 // Only one replacement instruction
9859 9860 //
9860 9861 // ---------EXAMPLE----------------------------------------------------------
9861 9862 //
9862 9863 // // pertinent parts of existing instructions in architecture description
9863 9864 // instruct movI(eRegI dst, eRegI src) %{
9864 9865 // match(Set dst (CopyI src));
9865 9866 // %}
9866 9867 //
9867 9868 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9868 9869 // match(Set dst (AddI dst src));
9869 9870 // effect(KILL cr);
9870 9871 // %}
9871 9872 //
9872 9873 // // Change (inc mov) to lea
9873 9874 // peephole %{
9874 9875 // // increment preceeded by register-register move
9875 9876 // peepmatch ( incI_eReg movI );
9876 9877 // // require that the destination register of the increment
9877 9878 // // match the destination register of the move
9878 9879 // peepconstraint ( 0.dst == 1.dst );
9879 9880 // // construct a replacement instruction that sets
9880 9881 // // the destination to ( move's source register + one )
9881 9882 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9882 9883 // %}
9883 9884 //
9884 9885
9885 9886 // // Change load of spilled value to only a spill
9886 9887 // instruct storeI(memory mem, eRegI src) %{
9887 9888 // match(Set mem (StoreI mem src));
9888 9889 // %}
9889 9890 //
9890 9891 // instruct loadI(eRegI dst, memory mem) %{
9891 9892 // match(Set dst (LoadI mem));
9892 9893 // %}
9893 9894 //
9894 9895 // peephole %{
9895 9896 // peepmatch ( loadI storeI );
9896 9897 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9897 9898 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9898 9899 // %}
9899 9900
9900 9901 //----------SMARTSPILL RULES---------------------------------------------------
9901 9902 // These must follow all instruction definitions as they use the names
9902 9903 // defined in the instructions definitions.
9903 9904 //
9904 9905 // SPARC will probably not have any of these rules due to RISC instruction set.
9905 9906
9906 9907 //----------PIPELINE-----------------------------------------------------------
9907 9908 // Rules which define the behavior of the target architectures pipeline.
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