1 //
2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
143
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
146
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
149
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
152
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
155
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
158
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
161
162 #ifdef _WIN64
163
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
166
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
169
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
172
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
175
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
178
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
181
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
184
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
187
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
190
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
193
194 #else
195
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
198
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
201
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
204
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
207
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
210
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
213
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
216
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
219
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
222
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
225
226 #endif // _WIN64
227
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
229
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
237
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
254
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
272
273 alloc_class chunk2(RFLAGS);
274
275
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
302
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
317
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R13, R13_H,
330 R14, R14_H);
331
332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
333 RAX, RAX_H,
334 RDI, RDI_H,
335 RSI, RSI_H,
336 RCX, RCX_H,
337 RBX, RBX_H,
338 R8, R8_H,
339 R9, R9_H,
340 R10, R10_H,
341 R11, R11_H,
342 R13, R13_H,
343 R14, R14_H);
344
345 // Class for all pointer registers except RAX, RBX and RSP
346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
347 RBP, RBP_H,
348 RDI, RDI_H,
349 RSI, RSI_H,
350 RCX, RCX_H,
351 R8, R8_H,
352 R9, R9_H,
353 R10, R10_H,
354 R11, R11_H,
355 R13, R13_H,
356 R14, R14_H);
357
358 // Singleton class for RAX pointer register
359 reg_class ptr_rax_reg(RAX, RAX_H);
360
361 // Singleton class for RBX pointer register
362 reg_class ptr_rbx_reg(RBX, RBX_H);
363
364 // Singleton class for RSI pointer register
365 reg_class ptr_rsi_reg(RSI, RSI_H);
366
367 // Singleton class for RDI pointer register
368 reg_class ptr_rdi_reg(RDI, RDI_H);
369
370 // Singleton class for RBP pointer register
371 reg_class ptr_rbp_reg(RBP, RBP_H);
372
373 // Singleton class for stack pointer
374 reg_class ptr_rsp_reg(RSP, RSP_H);
375
376 // Singleton class for TLS pointer
377 reg_class ptr_r15_reg(R15, R15_H);
378
379 // Class for all long registers (except RSP)
380 reg_class long_reg(RAX, RAX_H,
381 RDX, RDX_H,
382 RBP, RBP_H,
383 RDI, RDI_H,
384 RSI, RSI_H,
385 RCX, RCX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers except RAX, RDX (and RSP)
395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
396 RDI, RDI_H,
397 RSI, RSI_H,
398 RCX, RCX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Class for all long registers except RCX (and RSP)
408 reg_class long_no_rcx_reg(RBP, RBP_H,
409 RDI, RDI_H,
410 RSI, RSI_H,
411 RAX, RAX_H,
412 RDX, RDX_H,
413 RBX, RBX_H,
414 R8, R8_H,
415 R9, R9_H,
416 R10, R10_H,
417 R11, R11_H,
418 R13, R13_H,
419 R14, R14_H);
420
421 // Class for all long registers except RAX (and RSP)
422 reg_class long_no_rax_reg(RBP, RBP_H,
423 RDX, RDX_H,
424 RDI, RDI_H,
425 RSI, RSI_H,
426 RCX, RCX_H,
427 RBX, RBX_H,
428 R8, R8_H,
429 R9, R9_H,
430 R10, R10_H,
431 R11, R11_H,
432 R13, R13_H,
433 R14, R14_H);
434
435 // Singleton class for RAX long register
436 reg_class long_rax_reg(RAX, RAX_H);
437
438 // Singleton class for RCX long register
439 reg_class long_rcx_reg(RCX, RCX_H);
440
441 // Singleton class for RDX long register
442 reg_class long_rdx_reg(RDX, RDX_H);
443
444 // Class for all int registers (except RSP)
445 reg_class int_reg(RAX,
446 RDX,
447 RBP,
448 RDI,
449 RSI,
450 RCX,
451 RBX,
452 R8,
453 R9,
454 R10,
455 R11,
456 R13,
457 R14);
458
459 // Class for all int registers except RCX (and RSP)
460 reg_class int_no_rcx_reg(RAX,
461 RDX,
462 RBP,
463 RDI,
464 RSI,
465 RBX,
466 R8,
467 R9,
468 R10,
469 R11,
470 R13,
471 R14);
472
473 // Class for all int registers except RAX, RDX (and RSP)
474 reg_class int_no_rax_rdx_reg(RBP,
475 RDI,
476 RSI,
477 RCX,
478 RBX,
479 R8,
480 R9,
481 R10,
482 R11,
483 R13,
484 R14);
485
486 // Singleton class for RAX int register
487 reg_class int_rax_reg(RAX);
488
489 // Singleton class for RBX int register
490 reg_class int_rbx_reg(RBX);
491
492 // Singleton class for RCX int register
493 reg_class int_rcx_reg(RCX);
494
495 // Singleton class for RCX int register
496 reg_class int_rdx_reg(RDX);
497
498 // Singleton class for RCX int register
499 reg_class int_rdi_reg(RDI);
500
501 // Singleton class for instruction pointer
502 // reg_class ip_reg(RIP);
503
504 // Singleton class for condition codes
505 reg_class int_flags(RFLAGS);
506
507 // Class for all float registers
508 reg_class float_reg(XMM0,
509 XMM1,
510 XMM2,
511 XMM3,
512 XMM4,
513 XMM5,
514 XMM6,
515 XMM7,
516 XMM8,
517 XMM9,
518 XMM10,
519 XMM11,
520 XMM12,
521 XMM13,
522 XMM14,
523 XMM15);
524
525 // Class for all double registers
526 reg_class double_reg(XMM0, XMM0_H,
527 XMM1, XMM1_H,
528 XMM2, XMM2_H,
529 XMM3, XMM3_H,
530 XMM4, XMM4_H,
531 XMM5, XMM5_H,
532 XMM6, XMM6_H,
533 XMM7, XMM7_H,
534 XMM8, XMM8_H,
535 XMM9, XMM9_H,
536 XMM10, XMM10_H,
537 XMM11, XMM11_H,
538 XMM12, XMM12_H,
539 XMM13, XMM13_H,
540 XMM14, XMM14_H,
541 XMM15, XMM15_H);
542 %}
543
544
545 //----------SOURCE BLOCK-------------------------------------------------------
546 // This is a block of C++ code which provides values, functions, and
547 // definitions necessary in the rest of the architecture description
548 source %{
549 #define RELOC_IMM64 Assembler::imm_operand
550 #define RELOC_DISP32 Assembler::disp32_operand
551
552 #define __ _masm.
553
554 static int preserve_SP_size() {
555 return 3; // rex.w, op, rm(reg/reg)
556 }
557
558 // !!!!! Special hack to get all types of calls to specify the byte offset
559 // from the start of the call to the point where the return address
560 // will point.
561 int MachCallStaticJavaNode::ret_addr_offset()
562 {
563 int offset = 5; // 5 bytes from start of call to where return address points
564 if (_method_handle_invoke)
565 offset += preserve_SP_size();
566 return offset;
567 }
568
569 int MachCallDynamicJavaNode::ret_addr_offset()
570 {
571 return 15; // 15 bytes from start of call to where return address points
572 }
573
574 // In os_cpu .ad file
575 // int MachCallRuntimeNode::ret_addr_offset()
576
577 // Indicate if the safepoint node needs the polling page as an input,
578 // it does if the polling page is more than disp32 away.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return Assembler::is_polling_page_far();
582 }
583
584 //
585 // Compute padding required for nodes which need alignment
586 //
587
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += 1; // skip call opcode byte
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
599 {
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
601 current_offset += 1; // skip call opcode byte
602 return round_to(current_offset, alignment_required()) - current_offset;
603 }
604
605 // The address of the call instruction needs to be 4-byte aligned to
606 // ensure that it does not span a cache line so that it can be patched.
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
608 {
609 current_offset += 11; // skip movq instruction + call opcode byte
610 return round_to(current_offset, alignment_required()) - current_offset;
611 }
612
613 // EMIT_RM()
614 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
615 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
616 cbuf.insts()->emit_int8(c);
617 }
618
619 // EMIT_CC()
620 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
621 unsigned char c = (unsigned char) (f1 | f2);
622 cbuf.insts()->emit_int8(c);
623 }
624
625 // EMIT_OPCODE()
626 void emit_opcode(CodeBuffer &cbuf, int code) {
627 cbuf.insts()->emit_int8((unsigned char) code);
628 }
629
630 // EMIT_OPCODE() w/ relocation information
631 void emit_opcode(CodeBuffer &cbuf,
632 int code, relocInfo::relocType reloc, int offset, int format)
633 {
634 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
635 emit_opcode(cbuf, code);
636 }
637
638 // EMIT_D8()
639 void emit_d8(CodeBuffer &cbuf, int d8) {
640 cbuf.insts()->emit_int8((unsigned char) d8);
641 }
642
643 // EMIT_D16()
644 void emit_d16(CodeBuffer &cbuf, int d16) {
645 cbuf.insts()->emit_int16(d16);
646 }
647
648 // EMIT_D32()
649 void emit_d32(CodeBuffer &cbuf, int d32) {
650 cbuf.insts()->emit_int32(d32);
651 }
652
653 // EMIT_D64()
654 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
655 cbuf.insts()->emit_int64(d64);
656 }
657
658 // emit 32 bit value and construct relocation entry from relocInfo::relocType
659 void emit_d32_reloc(CodeBuffer& cbuf,
660 int d32,
661 relocInfo::relocType reloc,
662 int format)
663 {
664 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
665 cbuf.relocate(cbuf.insts_mark(), reloc, format);
666 cbuf.insts()->emit_int32(d32);
667 }
668
669 // emit 32 bit value and construct relocation entry from RelocationHolder
670 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
671 #ifdef ASSERT
672 if (rspec.reloc()->type() == relocInfo::oop_type &&
673 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
674 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
675 }
676 #endif
677 cbuf.relocate(cbuf.insts_mark(), rspec, format);
678 cbuf.insts()->emit_int32(d32);
679 }
680
681 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
682 address next_ip = cbuf.insts_end() + 4;
683 emit_d32_reloc(cbuf, (int) (addr - next_ip),
684 external_word_Relocation::spec(addr),
685 RELOC_DISP32);
686 }
687
688
689 // emit 64 bit value and construct relocation entry from relocInfo::relocType
690 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
691 cbuf.relocate(cbuf.insts_mark(), reloc, format);
692 cbuf.insts()->emit_int64(d64);
693 }
694
695 // emit 64 bit value and construct relocation entry from RelocationHolder
696 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
697 #ifdef ASSERT
698 if (rspec.reloc()->type() == relocInfo::oop_type &&
699 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
700 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
701 "cannot embed scavengable oops in code");
702 }
703 #endif
704 cbuf.relocate(cbuf.insts_mark(), rspec, format);
705 cbuf.insts()->emit_int64(d64);
706 }
707
708 // Access stack slot for load or store
709 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
710 {
711 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
712 if (-0x80 <= disp && disp < 0x80) {
713 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
714 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
715 emit_d8(cbuf, disp); // Displacement // R/M byte
716 } else {
717 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
718 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
719 emit_d32(cbuf, disp); // Displacement // R/M byte
720 }
721 }
722
723 // rRegI ereg, memory mem) %{ // emit_reg_mem
724 void encode_RegMem(CodeBuffer &cbuf,
725 int reg,
726 int base, int index, int scale, int disp, bool disp_is_oop)
727 {
728 assert(!disp_is_oop, "cannot have disp");
729 int regenc = reg & 7;
730 int baseenc = base & 7;
731 int indexenc = index & 7;
732
733 // There is no index & no scale, use form without SIB byte
734 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
735 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
736 if (disp == 0 && base != RBP_enc && base != R13_enc) {
737 emit_rm(cbuf, 0x0, regenc, baseenc); // *
738 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
739 // If 8-bit displacement, mode 0x1
740 emit_rm(cbuf, 0x1, regenc, baseenc); // *
741 emit_d8(cbuf, disp);
742 } else {
743 // If 32-bit displacement
744 if (base == -1) { // Special flag for absolute address
745 emit_rm(cbuf, 0x0, regenc, 0x5); // *
746 if (disp_is_oop) {
747 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
748 } else {
749 emit_d32(cbuf, disp);
750 }
751 } else {
752 // Normal base + offset
753 emit_rm(cbuf, 0x2, regenc, baseenc); // *
754 if (disp_is_oop) {
755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
756 } else {
757 emit_d32(cbuf, disp);
758 }
759 }
760 }
761 } else {
762 // Else, encode with the SIB byte
763 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
764 if (disp == 0 && base != RBP_enc && base != R13_enc) {
765 // If no displacement
766 emit_rm(cbuf, 0x0, regenc, 0x4); // *
767 emit_rm(cbuf, scale, indexenc, baseenc);
768 } else {
769 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
770 // If 8-bit displacement, mode 0x1
771 emit_rm(cbuf, 0x1, regenc, 0x4); // *
772 emit_rm(cbuf, scale, indexenc, baseenc);
773 emit_d8(cbuf, disp);
774 } else {
775 // If 32-bit displacement
776 if (base == 0x04 ) {
777 emit_rm(cbuf, 0x2, regenc, 0x4);
778 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
779 } else {
780 emit_rm(cbuf, 0x2, regenc, 0x4);
781 emit_rm(cbuf, scale, indexenc, baseenc); // *
782 }
783 if (disp_is_oop) {
784 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
785 } else {
786 emit_d32(cbuf, disp);
787 }
788 }
789 }
790 }
791 }
792
793 // This could be in MacroAssembler but it's fairly C2 specific
794 void emit_cmpfp_fixup(MacroAssembler& _masm) {
795 Label exit;
796 __ jccb(Assembler::noParity, exit);
797 __ pushf();
798 //
799 // comiss/ucomiss instructions set ZF,PF,CF flags and
800 // zero OF,AF,SF for NaN values.
801 // Fixup flags by zeroing ZF,PF so that compare of NaN
802 // values returns 'less than' result (CF is set).
803 // Leave the rest of flags unchanged.
804 //
805 // 7 6 5 4 3 2 1 0
806 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
807 // 0 0 1 0 1 0 1 1 (0x2B)
808 //
809 __ andq(Address(rsp, 0), 0xffffff2b);
810 __ popf();
811 __ bind(exit);
812 }
813
814 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
815 Label done;
816 __ movl(dst, -1);
817 __ jcc(Assembler::parity, done);
818 __ jcc(Assembler::below, done);
819 __ setb(Assembler::notEqual, dst);
820 __ movzbl(dst, dst);
821 __ bind(done);
822 }
823
824
825 //=============================================================================
826 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
827
828 int Compile::ConstantTable::calculate_table_base_offset() const {
829 return 0; // absolute addressing, no offset
830 }
831
832 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
833 // Empty encoding
834 }
835
836 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
837 return 0;
838 }
839
840 #ifndef PRODUCT
841 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
842 st->print("# MachConstantBaseNode (empty encoding)");
843 }
844 #endif
845
846
847 //=============================================================================
848 #ifndef PRODUCT
849 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
850 Compile* C = ra_->C;
851
852 int framesize = C->frame_slots() << LogBytesPerInt;
853 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
854 // Remove wordSize for return addr which is already pushed.
855 framesize -= wordSize;
856
857 if (C->need_stack_bang(framesize)) {
858 framesize -= wordSize;
859 st->print("# stack bang");
860 st->print("\n\t");
861 st->print("pushq rbp\t# Save rbp");
862 if (framesize) {
863 st->print("\n\t");
864 st->print("subq rsp, #%d\t# Create frame",framesize);
865 }
866 } else {
867 st->print("subq rsp, #%d\t# Create frame",framesize);
868 st->print("\n\t");
869 framesize -= wordSize;
870 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
871 }
872
873 if (VerifyStackAtCalls) {
874 st->print("\n\t");
875 framesize -= wordSize;
876 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
877 #ifdef ASSERT
878 st->print("\n\t");
879 st->print("# stack alignment check");
880 #endif
881 }
882 st->cr();
883 }
884 #endif
885
886 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
887 Compile* C = ra_->C;
888 MacroAssembler _masm(&cbuf);
889
890 int framesize = C->frame_slots() << LogBytesPerInt;
891
892 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
893
894 C->set_frame_complete(cbuf.insts_size());
895
896 if (C->has_mach_constant_base_node()) {
897 // NOTE: We set the table base offset here because users might be
898 // emitted before MachConstantBaseNode.
899 Compile::ConstantTable& constant_table = C->constant_table();
900 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
901 }
902 }
903
904 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
905 {
906 return MachNode::size(ra_); // too many variables; just compute it
907 // the hard way
908 }
909
910 int MachPrologNode::reloc() const
911 {
912 return 0; // a large enough number
913 }
914
915 //=============================================================================
916 #ifndef PRODUCT
917 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
918 {
919 Compile* C = ra_->C;
920 int framesize = C->frame_slots() << LogBytesPerInt;
921 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
922 // Remove word for return adr already pushed
923 // and RBP
924 framesize -= 2*wordSize;
925
926 if (framesize) {
927 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
928 st->print("\t");
929 }
930
931 st->print_cr("popq rbp");
932 if (do_polling() && C->is_method_compilation()) {
933 st->print("\t");
934 if (Assembler::is_polling_page_far()) {
935 st->print_cr("movq rscratch1, #polling_page_address\n\t"
936 "testl rax, [rscratch1]\t"
937 "# Safepoint: poll for GC");
938 } else {
939 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
940 "# Safepoint: poll for GC");
941 }
942 }
943 }
944 #endif
945
946 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
947 {
948 Compile* C = ra_->C;
949 int framesize = C->frame_slots() << LogBytesPerInt;
950 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
951 // Remove word for return adr already pushed
952 // and RBP
953 framesize -= 2*wordSize;
954
955 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
956
957 if (framesize) {
958 emit_opcode(cbuf, Assembler::REX_W);
959 if (framesize < 0x80) {
960 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
961 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
962 emit_d8(cbuf, framesize);
963 } else {
964 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
965 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
966 emit_d32(cbuf, framesize);
967 }
968 }
969
970 // popq rbp
971 emit_opcode(cbuf, 0x58 | RBP_enc);
972
973 if (do_polling() && C->is_method_compilation()) {
974 MacroAssembler _masm(&cbuf);
975 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
976 if (Assembler::is_polling_page_far()) {
977 __ lea(rscratch1, polling_page);
978 __ relocate(relocInfo::poll_return_type);
979 __ testl(rax, Address(rscratch1, 0));
980 } else {
981 __ testl(rax, polling_page);
982 }
983 }
984 }
985
986 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
987 {
988 return MachNode::size(ra_); // too many variables; just compute it
989 // the hard way
990 }
991
992 int MachEpilogNode::reloc() const
993 {
994 return 2; // a large enough number
995 }
996
997 const Pipeline* MachEpilogNode::pipeline() const
998 {
999 return MachNode::pipeline_class();
1000 }
1001
1002 int MachEpilogNode::safepoint_offset() const
1003 {
1004 return 0;
1005 }
1006
1007 //=============================================================================
1008
1009 enum RC {
1010 rc_bad,
1011 rc_int,
1012 rc_float,
1013 rc_stack
1014 };
1015
1016 static enum RC rc_class(OptoReg::Name reg)
1017 {
1018 if( !OptoReg::is_valid(reg) ) return rc_bad;
1019
1020 if (OptoReg::is_stack(reg)) return rc_stack;
1021
1022 VMReg r = OptoReg::as_VMReg(reg);
1023
1024 if (r->is_Register()) return rc_int;
1025
1026 assert(r->is_XMMRegister(), "must be");
1027 return rc_float;
1028 }
1029
1030 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1031 PhaseRegAlloc* ra_,
1032 bool do_size,
1033 outputStream* st) const
1034 {
1035
1036 // Get registers to move
1037 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1038 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1039 OptoReg::Name dst_second = ra_->get_reg_second(this);
1040 OptoReg::Name dst_first = ra_->get_reg_first(this);
1041
1042 enum RC src_second_rc = rc_class(src_second);
1043 enum RC src_first_rc = rc_class(src_first);
1044 enum RC dst_second_rc = rc_class(dst_second);
1045 enum RC dst_first_rc = rc_class(dst_first);
1046
1047 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1048 "must move at least 1 register" );
1049
1050 if (src_first == dst_first && src_second == dst_second) {
1051 // Self copy, no move
1052 return 0;
1053 } else if (src_first_rc == rc_stack) {
1054 // mem ->
1055 if (dst_first_rc == rc_stack) {
1056 // mem -> mem
1057 assert(src_second != dst_first, "overlap");
1058 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1059 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1060 // 64-bit
1061 int src_offset = ra_->reg2offset(src_first);
1062 int dst_offset = ra_->reg2offset(dst_first);
1063 if (cbuf) {
1064 emit_opcode(*cbuf, 0xFF);
1065 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1066
1067 emit_opcode(*cbuf, 0x8F);
1068 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1069
1070 #ifndef PRODUCT
1071 } else if (!do_size) {
1072 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1073 "popq [rsp + #%d]",
1074 src_offset,
1075 dst_offset);
1076 #endif
1077 }
1078 return
1079 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1080 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1081 } else {
1082 // 32-bit
1083 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1084 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1085 // No pushl/popl, so:
1086 int src_offset = ra_->reg2offset(src_first);
1087 int dst_offset = ra_->reg2offset(dst_first);
1088 if (cbuf) {
1089 emit_opcode(*cbuf, Assembler::REX_W);
1090 emit_opcode(*cbuf, 0x89);
1091 emit_opcode(*cbuf, 0x44);
1092 emit_opcode(*cbuf, 0x24);
1093 emit_opcode(*cbuf, 0xF8);
1094
1095 emit_opcode(*cbuf, 0x8B);
1096 encode_RegMem(*cbuf,
1097 RAX_enc,
1098 RSP_enc, 0x4, 0, src_offset,
1099 false);
1100
1101 emit_opcode(*cbuf, 0x89);
1102 encode_RegMem(*cbuf,
1103 RAX_enc,
1104 RSP_enc, 0x4, 0, dst_offset,
1105 false);
1106
1107 emit_opcode(*cbuf, Assembler::REX_W);
1108 emit_opcode(*cbuf, 0x8B);
1109 emit_opcode(*cbuf, 0x44);
1110 emit_opcode(*cbuf, 0x24);
1111 emit_opcode(*cbuf, 0xF8);
1112
1113 #ifndef PRODUCT
1114 } else if (!do_size) {
1115 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1116 "movl rax, [rsp + #%d]\n\t"
1117 "movl [rsp + #%d], rax\n\t"
1118 "movq rax, [rsp - #8]",
1119 src_offset,
1120 dst_offset);
1121 #endif
1122 }
1123 return
1124 5 + // movq
1125 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1126 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1127 5; // movq
1128 }
1129 } else if (dst_first_rc == rc_int) {
1130 // mem -> gpr
1131 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1132 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1133 // 64-bit
1134 int offset = ra_->reg2offset(src_first);
1135 if (cbuf) {
1136 if (Matcher::_regEncode[dst_first] < 8) {
1137 emit_opcode(*cbuf, Assembler::REX_W);
1138 } else {
1139 emit_opcode(*cbuf, Assembler::REX_WR);
1140 }
1141 emit_opcode(*cbuf, 0x8B);
1142 encode_RegMem(*cbuf,
1143 Matcher::_regEncode[dst_first],
1144 RSP_enc, 0x4, 0, offset,
1145 false);
1146 #ifndef PRODUCT
1147 } else if (!do_size) {
1148 st->print("movq %s, [rsp + #%d]\t# spill",
1149 Matcher::regName[dst_first],
1150 offset);
1151 #endif
1152 }
1153 return
1154 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1155 } else {
1156 // 32-bit
1157 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1158 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1159 int offset = ra_->reg2offset(src_first);
1160 if (cbuf) {
1161 if (Matcher::_regEncode[dst_first] >= 8) {
1162 emit_opcode(*cbuf, Assembler::REX_R);
1163 }
1164 emit_opcode(*cbuf, 0x8B);
1165 encode_RegMem(*cbuf,
1166 Matcher::_regEncode[dst_first],
1167 RSP_enc, 0x4, 0, offset,
1168 false);
1169 #ifndef PRODUCT
1170 } else if (!do_size) {
1171 st->print("movl %s, [rsp + #%d]\t# spill",
1172 Matcher::regName[dst_first],
1173 offset);
1174 #endif
1175 }
1176 return
1177 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1178 ((Matcher::_regEncode[dst_first] < 8)
1179 ? 3
1180 : 4); // REX
1181 }
1182 } else if (dst_first_rc == rc_float) {
1183 // mem-> xmm
1184 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1185 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1186 // 64-bit
1187 int offset = ra_->reg2offset(src_first);
1188 if (cbuf) {
1189 MacroAssembler _masm(cbuf);
1190 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1191 #ifndef PRODUCT
1192 } else if (!do_size) {
1193 st->print("%s %s, [rsp + #%d]\t# spill",
1194 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1195 Matcher::regName[dst_first],
1196 offset);
1197 #endif
1198 }
1199 return
1200 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1201 ((Matcher::_regEncode[dst_first] >= 8)
1202 ? 6
1203 : (5 + ((UseAVX>0)?1:0))); // REX
1204 } else {
1205 // 32-bit
1206 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1207 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1208 int offset = ra_->reg2offset(src_first);
1209 if (cbuf) {
1210 MacroAssembler _masm(cbuf);
1211 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1212 #ifndef PRODUCT
1213 } else if (!do_size) {
1214 st->print("movss %s, [rsp + #%d]\t# spill",
1215 Matcher::regName[dst_first],
1216 offset);
1217 #endif
1218 }
1219 return
1220 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1221 ((Matcher::_regEncode[dst_first] >= 8)
1222 ? 6
1223 : (5 + ((UseAVX>0)?1:0))); // REX
1224 }
1225 }
1226 } else if (src_first_rc == rc_int) {
1227 // gpr ->
1228 if (dst_first_rc == rc_stack) {
1229 // gpr -> mem
1230 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1232 // 64-bit
1233 int offset = ra_->reg2offset(dst_first);
1234 if (cbuf) {
1235 if (Matcher::_regEncode[src_first] < 8) {
1236 emit_opcode(*cbuf, Assembler::REX_W);
1237 } else {
1238 emit_opcode(*cbuf, Assembler::REX_WR);
1239 }
1240 emit_opcode(*cbuf, 0x89);
1241 encode_RegMem(*cbuf,
1242 Matcher::_regEncode[src_first],
1243 RSP_enc, 0x4, 0, offset,
1244 false);
1245 #ifndef PRODUCT
1246 } else if (!do_size) {
1247 st->print("movq [rsp + #%d], %s\t# spill",
1248 offset,
1249 Matcher::regName[src_first]);
1250 #endif
1251 }
1252 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1253 } else {
1254 // 32-bit
1255 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1256 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1257 int offset = ra_->reg2offset(dst_first);
1258 if (cbuf) {
1259 if (Matcher::_regEncode[src_first] >= 8) {
1260 emit_opcode(*cbuf, Assembler::REX_R);
1261 }
1262 emit_opcode(*cbuf, 0x89);
1263 encode_RegMem(*cbuf,
1264 Matcher::_regEncode[src_first],
1265 RSP_enc, 0x4, 0, offset,
1266 false);
1267 #ifndef PRODUCT
1268 } else if (!do_size) {
1269 st->print("movl [rsp + #%d], %s\t# spill",
1270 offset,
1271 Matcher::regName[src_first]);
1272 #endif
1273 }
1274 return
1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1276 ((Matcher::_regEncode[src_first] < 8)
1277 ? 3
1278 : 4); // REX
1279 }
1280 } else if (dst_first_rc == rc_int) {
1281 // gpr -> gpr
1282 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1283 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1284 // 64-bit
1285 if (cbuf) {
1286 if (Matcher::_regEncode[dst_first] < 8) {
1287 if (Matcher::_regEncode[src_first] < 8) {
1288 emit_opcode(*cbuf, Assembler::REX_W);
1289 } else {
1290 emit_opcode(*cbuf, Assembler::REX_WB);
1291 }
1292 } else {
1293 if (Matcher::_regEncode[src_first] < 8) {
1294 emit_opcode(*cbuf, Assembler::REX_WR);
1295 } else {
1296 emit_opcode(*cbuf, Assembler::REX_WRB);
1297 }
1298 }
1299 emit_opcode(*cbuf, 0x8B);
1300 emit_rm(*cbuf, 0x3,
1301 Matcher::_regEncode[dst_first] & 7,
1302 Matcher::_regEncode[src_first] & 7);
1303 #ifndef PRODUCT
1304 } else if (!do_size) {
1305 st->print("movq %s, %s\t# spill",
1306 Matcher::regName[dst_first],
1307 Matcher::regName[src_first]);
1308 #endif
1309 }
1310 return 3; // REX
1311 } else {
1312 // 32-bit
1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1315 if (cbuf) {
1316 if (Matcher::_regEncode[dst_first] < 8) {
1317 if (Matcher::_regEncode[src_first] >= 8) {
1318 emit_opcode(*cbuf, Assembler::REX_B);
1319 }
1320 } else {
1321 if (Matcher::_regEncode[src_first] < 8) {
1322 emit_opcode(*cbuf, Assembler::REX_R);
1323 } else {
1324 emit_opcode(*cbuf, Assembler::REX_RB);
1325 }
1326 }
1327 emit_opcode(*cbuf, 0x8B);
1328 emit_rm(*cbuf, 0x3,
1329 Matcher::_regEncode[dst_first] & 7,
1330 Matcher::_regEncode[src_first] & 7);
1331 #ifndef PRODUCT
1332 } else if (!do_size) {
1333 st->print("movl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 return
1339 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1340 ? 2
1341 : 3; // REX
1342 }
1343 } else if (dst_first_rc == rc_float) {
1344 // gpr -> xmm
1345 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1346 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1347 // 64-bit
1348 if (cbuf) {
1349 MacroAssembler _masm(cbuf);
1350 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1351 #ifndef PRODUCT
1352 } else if (!do_size) {
1353 st->print("movdq %s, %s\t# spill",
1354 Matcher::regName[dst_first],
1355 Matcher::regName[src_first]);
1356 #endif
1357 }
1358 return 5; // REX
1359 } else {
1360 // 32-bit
1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1363 if (cbuf) {
1364 MacroAssembler _masm(cbuf);
1365 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1366 #ifndef PRODUCT
1367 } else if (!do_size) {
1368 st->print("movdl %s, %s\t# spill",
1369 Matcher::regName[dst_first],
1370 Matcher::regName[src_first]);
1371 #endif
1372 }
1373 return
1374 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1375 ? 5
1376 : (4 + ((UseAVX>0)?1:0)); // REX
1377 }
1378 }
1379 } else if (src_first_rc == rc_float) {
1380 // xmm ->
1381 if (dst_first_rc == rc_stack) {
1382 // xmm -> mem
1383 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1384 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1385 // 64-bit
1386 int offset = ra_->reg2offset(dst_first);
1387 if (cbuf) {
1388 MacroAssembler _masm(cbuf);
1389 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1390 #ifndef PRODUCT
1391 } else if (!do_size) {
1392 st->print("movsd [rsp + #%d], %s\t# spill",
1393 offset,
1394 Matcher::regName[src_first]);
1395 #endif
1396 }
1397 return
1398 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1399 ((Matcher::_regEncode[src_first] >= 8)
1400 ? 6
1401 : (5 + ((UseAVX>0)?1:0))); // REX
1402 } else {
1403 // 32-bit
1404 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1405 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1406 int offset = ra_->reg2offset(dst_first);
1407 if (cbuf) {
1408 MacroAssembler _masm(cbuf);
1409 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1410 #ifndef PRODUCT
1411 } else if (!do_size) {
1412 st->print("movss [rsp + #%d], %s\t# spill",
1413 offset,
1414 Matcher::regName[src_first]);
1415 #endif
1416 }
1417 return
1418 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1419 ((Matcher::_regEncode[src_first] >=8)
1420 ? 6
1421 : (5 + ((UseAVX>0)?1:0))); // REX
1422 }
1423 } else if (dst_first_rc == rc_int) {
1424 // xmm -> gpr
1425 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1426 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1427 // 64-bit
1428 if (cbuf) {
1429 MacroAssembler _masm(cbuf);
1430 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1431 #ifndef PRODUCT
1432 } else if (!do_size) {
1433 st->print("movdq %s, %s\t# spill",
1434 Matcher::regName[dst_first],
1435 Matcher::regName[src_first]);
1436 #endif
1437 }
1438 return 5; // REX
1439 } else {
1440 // 32-bit
1441 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1442 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1443 if (cbuf) {
1444 MacroAssembler _masm(cbuf);
1445 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1446 #ifndef PRODUCT
1447 } else if (!do_size) {
1448 st->print("movdl %s, %s\t# spill",
1449 Matcher::regName[dst_first],
1450 Matcher::regName[src_first]);
1451 #endif
1452 }
1453 return
1454 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1455 ? 5
1456 : (4 + ((UseAVX>0)?1:0)); // REX
1457 }
1458 } else if (dst_first_rc == rc_float) {
1459 // xmm -> xmm
1460 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1461 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 // 64-bit
1463 if (cbuf) {
1464 MacroAssembler _masm(cbuf);
1465 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1466 #ifndef PRODUCT
1467 } else if (!do_size) {
1468 st->print("%s %s, %s\t# spill",
1469 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1470 Matcher::regName[dst_first],
1471 Matcher::regName[src_first]);
1472 #endif
1473 }
1474 return
1475 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1476 ? 5
1477 : (4 + ((UseAVX>0)?1:0)); // REX
1478 } else {
1479 // 32-bit
1480 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1481 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1482 if (cbuf) {
1483 MacroAssembler _masm(cbuf);
1484 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1485 #ifndef PRODUCT
1486 } else if (!do_size) {
1487 st->print("%s %s, %s\t# spill",
1488 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1489 Matcher::regName[dst_first],
1490 Matcher::regName[src_first]);
1491 #endif
1492 }
1493 return ((UseAVX>0) ? 5:
1494 ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1495 ? (UseXmmRegToRegMoveAll ? 4 : 5)
1496 : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX
1497 }
1498 }
1499 }
1500
1501 assert(0," foo ");
1502 Unimplemented();
1503
1504 return 0;
1505 }
1506
1507 #ifndef PRODUCT
1508 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1509 {
1510 implementation(NULL, ra_, false, st);
1511 }
1512 #endif
1513
1514 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1515 {
1516 implementation(&cbuf, ra_, false, NULL);
1517 }
1518
1519 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1520 {
1521 return implementation(NULL, ra_, true, NULL);
1522 }
1523
1524 //=============================================================================
1525 #ifndef PRODUCT
1526 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_reg_first(this);
1530 st->print("leaq %s, [rsp + #%d]\t# box lock",
1531 Matcher::regName[reg], offset);
1532 }
1533 #endif
1534
1535 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1536 {
1537 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1538 int reg = ra_->get_encode(this);
1539 if (offset >= 0x80) {
1540 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1541 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1542 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1543 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1544 emit_d32(cbuf, offset);
1545 } else {
1546 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1547 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1548 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1549 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1550 emit_d8(cbuf, offset);
1551 }
1552 }
1553
1554 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1555 {
1556 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1557 return (offset < 0x80) ? 5 : 8; // REX
1558 }
1559
1560 //=============================================================================
1561
1562 // emit call stub, compiled java to interpreter
1563 void emit_java_to_interp(CodeBuffer& cbuf)
1564 {
1565 // Stub is fixed up when the corresponding call is converted from
1566 // calling compiled code to calling interpreted code.
1567 // movq rbx, 0
1568 // jmp -5 # to self
1569
1570 address mark = cbuf.insts_mark(); // get mark within main instrs section
1571
1572 // Note that the code buffer's insts_mark is always relative to insts.
1573 // That's why we must use the macroassembler to generate a stub.
1574 MacroAssembler _masm(&cbuf);
1575
1576 address base =
1577 __ start_a_stub(Compile::MAX_stubs_size);
1578 if (base == NULL) return; // CodeBuffer::expand failed
1579 // static stub relocation stores the instruction address of the call
1580 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1581 // static stub relocation also tags the methodOop in the code-stream.
1582 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1583 // This is recognized as unresolved by relocs/nativeinst/ic code
1584 __ jump(RuntimeAddress(__ pc()));
1585
1586 // Update current stubs pointer and restore insts_end.
1587 __ end_a_stub();
1588 }
1589
1590 // size of call stub, compiled java to interpretor
1591 uint size_java_to_interp()
1592 {
1593 return 15; // movq (1+1+8); jmp (1+4)
1594 }
1595
1596 // relocation entries for call stub, compiled java to interpretor
1597 uint reloc_java_to_interp()
1598 {
1599 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1600 }
1601
1602 //=============================================================================
1603 #ifndef PRODUCT
1604 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1605 {
1606 if (UseCompressedOops) {
1607 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1608 if (Universe::narrow_oop_shift() != 0) {
1609 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1610 }
1611 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1612 } else {
1613 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1614 "# Inline cache check");
1615 }
1616 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1617 st->print_cr("\tnop\t# nops to align entry point");
1618 }
1619 #endif
1620
1621 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1622 {
1623 MacroAssembler masm(&cbuf);
1624 uint insts_size = cbuf.insts_size();
1625 if (UseCompressedOops) {
1626 masm.load_klass(rscratch1, j_rarg0);
1627 masm.cmpptr(rax, rscratch1);
1628 } else {
1629 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1630 }
1631
1632 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1633
1634 /* WARNING these NOPs are critical so that verified entry point is properly
1635 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1636 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1637 if (OptoBreakpoint) {
1638 // Leave space for int3
1639 nops_cnt -= 1;
1640 }
1641 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1642 if (nops_cnt > 0)
1643 masm.nop(nops_cnt);
1644 }
1645
1646 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1647 {
1648 return MachNode::size(ra_); // too many variables; just compute it
1649 // the hard way
1650 }
1651
1652
1653 //=============================================================================
1654 uint size_exception_handler()
1655 {
1656 // NativeCall instruction size is the same as NativeJump.
1657 // Note that this value is also credited (in output.cpp) to
1658 // the size of the code section.
1659 return NativeJump::instruction_size;
1660 }
1661
1662 // Emit exception handler code.
1663 int emit_exception_handler(CodeBuffer& cbuf)
1664 {
1665
1666 // Note that the code buffer's insts_mark is always relative to insts.
1667 // That's why we must use the macroassembler to generate a handler.
1668 MacroAssembler _masm(&cbuf);
1669 address base =
1670 __ start_a_stub(size_exception_handler());
1671 if (base == NULL) return 0; // CodeBuffer::expand failed
1672 int offset = __ offset();
1673 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1674 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1675 __ end_a_stub();
1676 return offset;
1677 }
1678
1679 uint size_deopt_handler()
1680 {
1681 // three 5 byte instructions
1682 return 15;
1683 }
1684
1685 // Emit deopt handler code.
1686 int emit_deopt_handler(CodeBuffer& cbuf)
1687 {
1688
1689 // Note that the code buffer's insts_mark is always relative to insts.
1690 // That's why we must use the macroassembler to generate a handler.
1691 MacroAssembler _masm(&cbuf);
1692 address base =
1693 __ start_a_stub(size_deopt_handler());
1694 if (base == NULL) return 0; // CodeBuffer::expand failed
1695 int offset = __ offset();
1696 address the_pc = (address) __ pc();
1697 Label next;
1698 // push a "the_pc" on the stack without destroying any registers
1699 // as they all may be live.
1700
1701 // push address of "next"
1702 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1703 __ bind(next);
1704 // adjust it so it matches "the_pc"
1705 __ subptr(Address(rsp, 0), __ offset() - offset);
1706 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1707 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1708 __ end_a_stub();
1709 return offset;
1710 }
1711
1712
1713 const bool Matcher::match_rule_supported(int opcode) {
1714 if (!has_match_rule(opcode))
1715 return false;
1716
1717 switch (opcode) {
1718 case Op_PopCountI:
1719 case Op_PopCountL:
1720 if (!UsePopCountInstruction)
1721 return false;
1722 break;
1723 }
1724
1725 return true; // Per default match rules are supported.
1726 }
1727
1728 int Matcher::regnum_to_fpu_offset(int regnum)
1729 {
1730 return regnum - 32; // The FP registers are in the second chunk
1731 }
1732
1733 // This is UltraSparc specific, true just means we have fast l2f conversion
1734 const bool Matcher::convL2FSupported(void) {
1735 return true;
1736 }
1737
1738 // Vector width in bytes
1739 const uint Matcher::vector_width_in_bytes(void) {
1740 return 8;
1741 }
1742
1743 // Vector ideal reg
1744 const uint Matcher::vector_ideal_reg(void) {
1745 return Op_RegD;
1746 }
1747
1748 // Is this branch offset short enough that a short branch can be used?
1749 //
1750 // NOTE: If the platform does not provide any short branch variants, then
1751 // this method should return false for offset 0.
1752 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1753 // The passed offset is relative to address of the branch.
1754 // On 86 a branch displacement is calculated relative to address
1755 // of a next instruction.
1756 offset -= br_size;
1757
1758 // the short version of jmpConUCF2 contains multiple branches,
1759 // making the reach slightly less
1760 if (rule == jmpConUCF2_rule)
1761 return (-126 <= offset && offset <= 125);
1762 return (-128 <= offset && offset <= 127);
1763 }
1764
1765 const bool Matcher::isSimpleConstant64(jlong value) {
1766 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1767 //return value == (int) value; // Cf. storeImmL and immL32.
1768
1769 // Probably always true, even if a temp register is required.
1770 return true;
1771 }
1772
1773 // The ecx parameter to rep stosq for the ClearArray node is in words.
1774 const bool Matcher::init_array_count_is_in_bytes = false;
1775
1776 // Threshold size for cleararray.
1777 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1778
1779 // No additional cost for CMOVL.
1780 const int Matcher::long_cmove_cost() { return 0; }
1781
1782 // No CMOVF/CMOVD with SSE2
1783 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1784
1785 // Should the Matcher clone shifts on addressing modes, expecting them
1786 // to be subsumed into complex addressing expressions or compute them
1787 // into registers? True for Intel but false for most RISCs
1788 const bool Matcher::clone_shift_expressions = true;
1789
1790 // Do we need to mask the count passed to shift instructions or does
1791 // the cpu only look at the lower 5/6 bits anyway?
1792 const bool Matcher::need_masked_shift_count = false;
1793
1794 bool Matcher::narrow_oop_use_complex_address() {
1795 assert(UseCompressedOops, "only for compressed oops code");
1796 return (LogMinObjAlignmentInBytes <= 3);
1797 }
1798
1799 // Is it better to copy float constants, or load them directly from
1800 // memory? Intel can load a float constant from a direct address,
1801 // requiring no extra registers. Most RISCs will have to materialize
1802 // an address into a register first, so they would do better to copy
1803 // the constant from stack.
1804 const bool Matcher::rematerialize_float_constants = true; // XXX
1805
1806 // If CPU can load and store mis-aligned doubles directly then no
1807 // fixup is needed. Else we split the double into 2 integer pieces
1808 // and move it piece-by-piece. Only happens when passing doubles into
1809 // C code as the Java calling convention forces doubles to be aligned.
1810 const bool Matcher::misaligned_doubles_ok = true;
1811
1812 // No-op on amd64
1813 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1814
1815 // Advertise here if the CPU requires explicit rounding operations to
1816 // implement the UseStrictFP mode.
1817 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1818
1819 // Are floats conerted to double when stored to stack during deoptimization?
1820 // On x64 it is stored without convertion so we can use normal access.
1821 bool Matcher::float_in_double() { return false; }
1822
1823 // Do ints take an entire long register or just half?
1824 const bool Matcher::int_in_long = true;
1825
1826 // Return whether or not this register is ever used as an argument.
1827 // This function is used on startup to build the trampoline stubs in
1828 // generateOptoStub. Registers not mentioned will be killed by the VM
1829 // call in the trampoline, and arguments in those registers not be
1830 // available to the callee.
1831 bool Matcher::can_be_java_arg(int reg)
1832 {
1833 return
1834 reg == RDI_num || reg == RDI_H_num ||
1835 reg == RSI_num || reg == RSI_H_num ||
1836 reg == RDX_num || reg == RDX_H_num ||
1837 reg == RCX_num || reg == RCX_H_num ||
1838 reg == R8_num || reg == R8_H_num ||
1839 reg == R9_num || reg == R9_H_num ||
1840 reg == R12_num || reg == R12_H_num ||
1841 reg == XMM0_num || reg == XMM0_H_num ||
1842 reg == XMM1_num || reg == XMM1_H_num ||
1843 reg == XMM2_num || reg == XMM2_H_num ||
1844 reg == XMM3_num || reg == XMM3_H_num ||
1845 reg == XMM4_num || reg == XMM4_H_num ||
1846 reg == XMM5_num || reg == XMM5_H_num ||
1847 reg == XMM6_num || reg == XMM6_H_num ||
1848 reg == XMM7_num || reg == XMM7_H_num;
1849 }
1850
1851 bool Matcher::is_spillable_arg(int reg)
1852 {
1853 return can_be_java_arg(reg);
1854 }
1855
1856 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1857 // In 64 bit mode a code which use multiply when
1858 // devisor is constant is faster than hardware
1859 // DIV instruction (it uses MulHiL).
1860 return false;
1861 }
1862
1863 // Register for DIVI projection of divmodI
1864 RegMask Matcher::divI_proj_mask() {
1865 return INT_RAX_REG_mask();
1866 }
1867
1868 // Register for MODI projection of divmodI
1869 RegMask Matcher::modI_proj_mask() {
1870 return INT_RDX_REG_mask();
1871 }
1872
1873 // Register for DIVL projection of divmodL
1874 RegMask Matcher::divL_proj_mask() {
1875 return LONG_RAX_REG_mask();
1876 }
1877
1878 // Register for MODL projection of divmodL
1879 RegMask Matcher::modL_proj_mask() {
1880 return LONG_RDX_REG_mask();
1881 }
1882
1883 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1884 return PTR_RBP_REG_mask();
1885 }
1886
1887 static Address build_address(int b, int i, int s, int d) {
1888 Register index = as_Register(i);
1889 Address::ScaleFactor scale = (Address::ScaleFactor)s;
1890 if (index == rsp) {
1891 index = noreg;
1892 scale = Address::no_scale;
1893 }
1894 Address addr(as_Register(b), index, scale, d);
1895 return addr;
1896 }
1897
1898 %}
1899
1900 //----------ENCODING BLOCK-----------------------------------------------------
1901 // This block specifies the encoding classes used by the compiler to
1902 // output byte streams. Encoding classes are parameterized macros
1903 // used by Machine Instruction Nodes in order to generate the bit
1904 // encoding of the instruction. Operands specify their base encoding
1905 // interface with the interface keyword. There are currently
1906 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1907 // COND_INTER. REG_INTER causes an operand to generate a function
1908 // which returns its register number when queried. CONST_INTER causes
1909 // an operand to generate a function which returns the value of the
1910 // constant when queried. MEMORY_INTER causes an operand to generate
1911 // four functions which return the Base Register, the Index Register,
1912 // the Scale Value, and the Offset Value of the operand when queried.
1913 // COND_INTER causes an operand to generate six functions which return
1914 // the encoding code (ie - encoding bits for the instruction)
1915 // associated with each basic boolean condition for a conditional
1916 // instruction.
1917 //
1918 // Instructions specify two basic values for encoding. Again, a
1919 // function is available to check if the constant displacement is an
1920 // oop. They use the ins_encode keyword to specify their encoding
1921 // classes (which must be a sequence of enc_class names, and their
1922 // parameters, specified in the encoding block), and they use the
1923 // opcode keyword to specify, in order, their primary, secondary, and
1924 // tertiary opcode. Only the opcode sections which a particular
1925 // instruction needs for encoding need to be specified.
1926 encode %{
1927 // Build emit functions for each basic byte or larger field in the
1928 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1929 // from C++ code in the enc_class source block. Emit functions will
1930 // live in the main source block for now. In future, we can
1931 // generalize this by adding a syntax that specifies the sizes of
1932 // fields in an order, so that the adlc can build the emit functions
1933 // automagically
1934
1935 // Emit primary opcode
1936 enc_class OpcP
1937 %{
1938 emit_opcode(cbuf, $primary);
1939 %}
1940
1941 // Emit secondary opcode
1942 enc_class OpcS
1943 %{
1944 emit_opcode(cbuf, $secondary);
1945 %}
1946
1947 // Emit tertiary opcode
1948 enc_class OpcT
1949 %{
1950 emit_opcode(cbuf, $tertiary);
1951 %}
1952
1953 // Emit opcode directly
1954 enc_class Opcode(immI d8)
1955 %{
1956 emit_opcode(cbuf, $d8$$constant);
1957 %}
1958
1959 // Emit size prefix
1960 enc_class SizePrefix
1961 %{
1962 emit_opcode(cbuf, 0x66);
1963 %}
1964
1965 enc_class reg(rRegI reg)
1966 %{
1967 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1968 %}
1969
1970 enc_class reg_reg(rRegI dst, rRegI src)
1971 %{
1972 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1973 %}
1974
1975 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1976 %{
1977 emit_opcode(cbuf, $opcode$$constant);
1978 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1979 %}
1980
1981 enc_class cdql_enc(no_rax_rdx_RegI div)
1982 %{
1983 // Full implementation of Java idiv and irem; checks for
1984 // special case as described in JVM spec., p.243 & p.271.
1985 //
1986 // normal case special case
1987 //
1988 // input : rax: dividend min_int
1989 // reg: divisor -1
1990 //
1991 // output: rax: quotient (= rax idiv reg) min_int
1992 // rdx: remainder (= rax irem reg) 0
1993 //
1994 // Code sequnce:
1995 //
1996 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1997 // 5: 75 07/08 jne e <normal>
1998 // 7: 33 d2 xor %edx,%edx
1999 // [div >= 8 -> offset + 1]
2000 // [REX_B]
2001 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2002 // c: 74 03/04 je 11 <done>
2003 // 000000000000000e <normal>:
2004 // e: 99 cltd
2005 // [div >= 8 -> offset + 1]
2006 // [REX_B]
2007 // f: f7 f9 idiv $div
2008 // 0000000000000011 <done>:
2009
2010 // cmp $0x80000000,%eax
2011 emit_opcode(cbuf, 0x3d);
2012 emit_d8(cbuf, 0x00);
2013 emit_d8(cbuf, 0x00);
2014 emit_d8(cbuf, 0x00);
2015 emit_d8(cbuf, 0x80);
2016
2017 // jne e <normal>
2018 emit_opcode(cbuf, 0x75);
2019 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2020
2021 // xor %edx,%edx
2022 emit_opcode(cbuf, 0x33);
2023 emit_d8(cbuf, 0xD2);
2024
2025 // cmp $0xffffffffffffffff,%ecx
2026 if ($div$$reg >= 8) {
2027 emit_opcode(cbuf, Assembler::REX_B);
2028 }
2029 emit_opcode(cbuf, 0x83);
2030 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2031 emit_d8(cbuf, 0xFF);
2032
2033 // je 11 <done>
2034 emit_opcode(cbuf, 0x74);
2035 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2036
2037 // <normal>
2038 // cltd
2039 emit_opcode(cbuf, 0x99);
2040
2041 // idivl (note: must be emitted by the user of this rule)
2042 // <done>
2043 %}
2044
2045 enc_class cdqq_enc(no_rax_rdx_RegL div)
2046 %{
2047 // Full implementation of Java ldiv and lrem; checks for
2048 // special case as described in JVM spec., p.243 & p.271.
2049 //
2050 // normal case special case
2051 //
2052 // input : rax: dividend min_long
2053 // reg: divisor -1
2054 //
2055 // output: rax: quotient (= rax idiv reg) min_long
2056 // rdx: remainder (= rax irem reg) 0
2057 //
2058 // Code sequnce:
2059 //
2060 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2061 // 7: 00 00 80
2062 // a: 48 39 d0 cmp %rdx,%rax
2063 // d: 75 08 jne 17 <normal>
2064 // f: 33 d2 xor %edx,%edx
2065 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2066 // 15: 74 05 je 1c <done>
2067 // 0000000000000017 <normal>:
2068 // 17: 48 99 cqto
2069 // 19: 48 f7 f9 idiv $div
2070 // 000000000000001c <done>:
2071
2072 // mov $0x8000000000000000,%rdx
2073 emit_opcode(cbuf, Assembler::REX_W);
2074 emit_opcode(cbuf, 0xBA);
2075 emit_d8(cbuf, 0x00);
2076 emit_d8(cbuf, 0x00);
2077 emit_d8(cbuf, 0x00);
2078 emit_d8(cbuf, 0x00);
2079 emit_d8(cbuf, 0x00);
2080 emit_d8(cbuf, 0x00);
2081 emit_d8(cbuf, 0x00);
2082 emit_d8(cbuf, 0x80);
2083
2084 // cmp %rdx,%rax
2085 emit_opcode(cbuf, Assembler::REX_W);
2086 emit_opcode(cbuf, 0x39);
2087 emit_d8(cbuf, 0xD0);
2088
2089 // jne 17 <normal>
2090 emit_opcode(cbuf, 0x75);
2091 emit_d8(cbuf, 0x08);
2092
2093 // xor %edx,%edx
2094 emit_opcode(cbuf, 0x33);
2095 emit_d8(cbuf, 0xD2);
2096
2097 // cmp $0xffffffffffffffff,$div
2098 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2099 emit_opcode(cbuf, 0x83);
2100 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2101 emit_d8(cbuf, 0xFF);
2102
2103 // je 1e <done>
2104 emit_opcode(cbuf, 0x74);
2105 emit_d8(cbuf, 0x05);
2106
2107 // <normal>
2108 // cqto
2109 emit_opcode(cbuf, Assembler::REX_W);
2110 emit_opcode(cbuf, 0x99);
2111
2112 // idivq (note: must be emitted by the user of this rule)
2113 // <done>
2114 %}
2115
2116 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2117 enc_class OpcSE(immI imm)
2118 %{
2119 // Emit primary opcode and set sign-extend bit
2120 // Check for 8-bit immediate, and set sign extend bit in opcode
2121 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2122 emit_opcode(cbuf, $primary | 0x02);
2123 } else {
2124 // 32-bit immediate
2125 emit_opcode(cbuf, $primary);
2126 }
2127 %}
2128
2129 enc_class OpcSErm(rRegI dst, immI imm)
2130 %{
2131 // OpcSEr/m
2132 int dstenc = $dst$$reg;
2133 if (dstenc >= 8) {
2134 emit_opcode(cbuf, Assembler::REX_B);
2135 dstenc -= 8;
2136 }
2137 // Emit primary opcode and set sign-extend bit
2138 // Check for 8-bit immediate, and set sign extend bit in opcode
2139 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2140 emit_opcode(cbuf, $primary | 0x02);
2141 } else {
2142 // 32-bit immediate
2143 emit_opcode(cbuf, $primary);
2144 }
2145 // Emit r/m byte with secondary opcode, after primary opcode.
2146 emit_rm(cbuf, 0x3, $secondary, dstenc);
2147 %}
2148
2149 enc_class OpcSErm_wide(rRegL dst, immI imm)
2150 %{
2151 // OpcSEr/m
2152 int dstenc = $dst$$reg;
2153 if (dstenc < 8) {
2154 emit_opcode(cbuf, Assembler::REX_W);
2155 } else {
2156 emit_opcode(cbuf, Assembler::REX_WB);
2157 dstenc -= 8;
2158 }
2159 // Emit primary opcode and set sign-extend bit
2160 // Check for 8-bit immediate, and set sign extend bit in opcode
2161 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2162 emit_opcode(cbuf, $primary | 0x02);
2163 } else {
2164 // 32-bit immediate
2165 emit_opcode(cbuf, $primary);
2166 }
2167 // Emit r/m byte with secondary opcode, after primary opcode.
2168 emit_rm(cbuf, 0x3, $secondary, dstenc);
2169 %}
2170
2171 enc_class Con8or32(immI imm)
2172 %{
2173 // Check for 8-bit immediate, and set sign extend bit in opcode
2174 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2175 $$$emit8$imm$$constant;
2176 } else {
2177 // 32-bit immediate
2178 $$$emit32$imm$$constant;
2179 }
2180 %}
2181
2182 enc_class opc2_reg(rRegI dst)
2183 %{
2184 // BSWAP
2185 emit_cc(cbuf, $secondary, $dst$$reg);
2186 %}
2187
2188 enc_class opc3_reg(rRegI dst)
2189 %{
2190 // BSWAP
2191 emit_cc(cbuf, $tertiary, $dst$$reg);
2192 %}
2193
2194 enc_class reg_opc(rRegI div)
2195 %{
2196 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2197 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2198 %}
2199
2200 enc_class enc_cmov(cmpOp cop)
2201 %{
2202 // CMOV
2203 $$$emit8$primary;
2204 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2205 %}
2206
2207 enc_class enc_PartialSubtypeCheck()
2208 %{
2209 Register Rrdi = as_Register(RDI_enc); // result register
2210 Register Rrax = as_Register(RAX_enc); // super class
2211 Register Rrcx = as_Register(RCX_enc); // killed
2212 Register Rrsi = as_Register(RSI_enc); // sub class
2213 Label miss;
2214 const bool set_cond_codes = true;
2215
2216 MacroAssembler _masm(&cbuf);
2217 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2218 NULL, &miss,
2219 /*set_cond_codes:*/ true);
2220 if ($primary) {
2221 __ xorptr(Rrdi, Rrdi);
2222 }
2223 __ bind(miss);
2224 %}
2225
2226 enc_class Java_To_Interpreter(method meth)
2227 %{
2228 // CALL Java_To_Interpreter
2229 // This is the instruction starting address for relocation info.
2230 cbuf.set_insts_mark();
2231 $$$emit8$primary;
2232 // CALL directly to the runtime
2233 emit_d32_reloc(cbuf,
2234 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2235 runtime_call_Relocation::spec(),
2236 RELOC_DISP32);
2237 %}
2238
2239 enc_class Java_Static_Call(method meth)
2240 %{
2241 // JAVA STATIC CALL
2242 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2243 // determine who we intended to call.
2244 cbuf.set_insts_mark();
2245 $$$emit8$primary;
2246
2247 if (!_method) {
2248 emit_d32_reloc(cbuf,
2249 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2250 runtime_call_Relocation::spec(),
2251 RELOC_DISP32);
2252 } else if (_optimized_virtual) {
2253 emit_d32_reloc(cbuf,
2254 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2255 opt_virtual_call_Relocation::spec(),
2256 RELOC_DISP32);
2257 } else {
2258 emit_d32_reloc(cbuf,
2259 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2260 static_call_Relocation::spec(),
2261 RELOC_DISP32);
2262 }
2263 if (_method) {
2264 // Emit stub for static call
2265 emit_java_to_interp(cbuf);
2266 }
2267 %}
2268
2269 enc_class Java_Dynamic_Call(method meth)
2270 %{
2271 // JAVA DYNAMIC CALL
2272 // !!!!!
2273 // Generate "movq rax, -1", placeholder instruction to load oop-info
2274 // emit_call_dynamic_prologue( cbuf );
2275 cbuf.set_insts_mark();
2276
2277 // movq rax, -1
2278 emit_opcode(cbuf, Assembler::REX_W);
2279 emit_opcode(cbuf, 0xB8 | RAX_enc);
2280 emit_d64_reloc(cbuf,
2281 (int64_t) Universe::non_oop_word(),
2282 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2283 address virtual_call_oop_addr = cbuf.insts_mark();
2284 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2285 // who we intended to call.
2286 cbuf.set_insts_mark();
2287 $$$emit8$primary;
2288 emit_d32_reloc(cbuf,
2289 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2290 virtual_call_Relocation::spec(virtual_call_oop_addr),
2291 RELOC_DISP32);
2292 %}
2293
2294 enc_class Java_Compiled_Call(method meth)
2295 %{
2296 // JAVA COMPILED CALL
2297 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2298
2299 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2300 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2301
2302 // callq *disp(%rax)
2303 cbuf.set_insts_mark();
2304 $$$emit8$primary;
2305 if (disp < 0x80) {
2306 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2307 emit_d8(cbuf, disp); // Displacement
2308 } else {
2309 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2310 emit_d32(cbuf, disp); // Displacement
2311 }
2312 %}
2313
2314 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2315 %{
2316 // SAL, SAR, SHR
2317 int dstenc = $dst$$reg;
2318 if (dstenc >= 8) {
2319 emit_opcode(cbuf, Assembler::REX_B);
2320 dstenc -= 8;
2321 }
2322 $$$emit8$primary;
2323 emit_rm(cbuf, 0x3, $secondary, dstenc);
2324 $$$emit8$shift$$constant;
2325 %}
2326
2327 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2328 %{
2329 // SAL, SAR, SHR
2330 int dstenc = $dst$$reg;
2331 if (dstenc < 8) {
2332 emit_opcode(cbuf, Assembler::REX_W);
2333 } else {
2334 emit_opcode(cbuf, Assembler::REX_WB);
2335 dstenc -= 8;
2336 }
2337 $$$emit8$primary;
2338 emit_rm(cbuf, 0x3, $secondary, dstenc);
2339 $$$emit8$shift$$constant;
2340 %}
2341
2342 enc_class load_immI(rRegI dst, immI src)
2343 %{
2344 int dstenc = $dst$$reg;
2345 if (dstenc >= 8) {
2346 emit_opcode(cbuf, Assembler::REX_B);
2347 dstenc -= 8;
2348 }
2349 emit_opcode(cbuf, 0xB8 | dstenc);
2350 $$$emit32$src$$constant;
2351 %}
2352
2353 enc_class load_immL(rRegL dst, immL src)
2354 %{
2355 int dstenc = $dst$$reg;
2356 if (dstenc < 8) {
2357 emit_opcode(cbuf, Assembler::REX_W);
2358 } else {
2359 emit_opcode(cbuf, Assembler::REX_WB);
2360 dstenc -= 8;
2361 }
2362 emit_opcode(cbuf, 0xB8 | dstenc);
2363 emit_d64(cbuf, $src$$constant);
2364 %}
2365
2366 enc_class load_immUL32(rRegL dst, immUL32 src)
2367 %{
2368 // same as load_immI, but this time we care about zeroes in the high word
2369 int dstenc = $dst$$reg;
2370 if (dstenc >= 8) {
2371 emit_opcode(cbuf, Assembler::REX_B);
2372 dstenc -= 8;
2373 }
2374 emit_opcode(cbuf, 0xB8 | dstenc);
2375 $$$emit32$src$$constant;
2376 %}
2377
2378 enc_class load_immL32(rRegL dst, immL32 src)
2379 %{
2380 int dstenc = $dst$$reg;
2381 if (dstenc < 8) {
2382 emit_opcode(cbuf, Assembler::REX_W);
2383 } else {
2384 emit_opcode(cbuf, Assembler::REX_WB);
2385 dstenc -= 8;
2386 }
2387 emit_opcode(cbuf, 0xC7);
2388 emit_rm(cbuf, 0x03, 0x00, dstenc);
2389 $$$emit32$src$$constant;
2390 %}
2391
2392 enc_class load_immP31(rRegP dst, immP32 src)
2393 %{
2394 // same as load_immI, but this time we care about zeroes in the high word
2395 int dstenc = $dst$$reg;
2396 if (dstenc >= 8) {
2397 emit_opcode(cbuf, Assembler::REX_B);
2398 dstenc -= 8;
2399 }
2400 emit_opcode(cbuf, 0xB8 | dstenc);
2401 $$$emit32$src$$constant;
2402 %}
2403
2404 enc_class load_immP(rRegP dst, immP src)
2405 %{
2406 int dstenc = $dst$$reg;
2407 if (dstenc < 8) {
2408 emit_opcode(cbuf, Assembler::REX_W);
2409 } else {
2410 emit_opcode(cbuf, Assembler::REX_WB);
2411 dstenc -= 8;
2412 }
2413 emit_opcode(cbuf, 0xB8 | dstenc);
2414 // This next line should be generated from ADLC
2415 if ($src->constant_is_oop()) {
2416 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2417 } else {
2418 emit_d64(cbuf, $src$$constant);
2419 }
2420 %}
2421
2422 enc_class Con32(immI src)
2423 %{
2424 // Output immediate
2425 $$$emit32$src$$constant;
2426 %}
2427
2428 enc_class Con64(immL src)
2429 %{
2430 // Output immediate
2431 emit_d64($src$$constant);
2432 %}
2433
2434 enc_class Con32F_as_bits(immF src)
2435 %{
2436 // Output Float immediate bits
2437 jfloat jf = $src$$constant;
2438 jint jf_as_bits = jint_cast(jf);
2439 emit_d32(cbuf, jf_as_bits);
2440 %}
2441
2442 enc_class Con16(immI src)
2443 %{
2444 // Output immediate
2445 $$$emit16$src$$constant;
2446 %}
2447
2448 // How is this different from Con32??? XXX
2449 enc_class Con_d32(immI src)
2450 %{
2451 emit_d32(cbuf,$src$$constant);
2452 %}
2453
2454 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2455 // Output immediate memory reference
2456 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2457 emit_d32(cbuf, 0x00);
2458 %}
2459
2460 enc_class lock_prefix()
2461 %{
2462 if (os::is_MP()) {
2463 emit_opcode(cbuf, 0xF0); // lock
2464 }
2465 %}
2466
2467 enc_class REX_mem(memory mem)
2468 %{
2469 if ($mem$$base >= 8) {
2470 if ($mem$$index < 8) {
2471 emit_opcode(cbuf, Assembler::REX_B);
2472 } else {
2473 emit_opcode(cbuf, Assembler::REX_XB);
2474 }
2475 } else {
2476 if ($mem$$index >= 8) {
2477 emit_opcode(cbuf, Assembler::REX_X);
2478 }
2479 }
2480 %}
2481
2482 enc_class REX_mem_wide(memory mem)
2483 %{
2484 if ($mem$$base >= 8) {
2485 if ($mem$$index < 8) {
2486 emit_opcode(cbuf, Assembler::REX_WB);
2487 } else {
2488 emit_opcode(cbuf, Assembler::REX_WXB);
2489 }
2490 } else {
2491 if ($mem$$index < 8) {
2492 emit_opcode(cbuf, Assembler::REX_W);
2493 } else {
2494 emit_opcode(cbuf, Assembler::REX_WX);
2495 }
2496 }
2497 %}
2498
2499 // for byte regs
2500 enc_class REX_breg(rRegI reg)
2501 %{
2502 if ($reg$$reg >= 4) {
2503 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2504 }
2505 %}
2506
2507 // for byte regs
2508 enc_class REX_reg_breg(rRegI dst, rRegI src)
2509 %{
2510 if ($dst$$reg < 8) {
2511 if ($src$$reg >= 4) {
2512 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2513 }
2514 } else {
2515 if ($src$$reg < 8) {
2516 emit_opcode(cbuf, Assembler::REX_R);
2517 } else {
2518 emit_opcode(cbuf, Assembler::REX_RB);
2519 }
2520 }
2521 %}
2522
2523 // for byte regs
2524 enc_class REX_breg_mem(rRegI reg, memory mem)
2525 %{
2526 if ($reg$$reg < 8) {
2527 if ($mem$$base < 8) {
2528 if ($mem$$index >= 8) {
2529 emit_opcode(cbuf, Assembler::REX_X);
2530 } else if ($reg$$reg >= 4) {
2531 emit_opcode(cbuf, Assembler::REX);
2532 }
2533 } else {
2534 if ($mem$$index < 8) {
2535 emit_opcode(cbuf, Assembler::REX_B);
2536 } else {
2537 emit_opcode(cbuf, Assembler::REX_XB);
2538 }
2539 }
2540 } else {
2541 if ($mem$$base < 8) {
2542 if ($mem$$index < 8) {
2543 emit_opcode(cbuf, Assembler::REX_R);
2544 } else {
2545 emit_opcode(cbuf, Assembler::REX_RX);
2546 }
2547 } else {
2548 if ($mem$$index < 8) {
2549 emit_opcode(cbuf, Assembler::REX_RB);
2550 } else {
2551 emit_opcode(cbuf, Assembler::REX_RXB);
2552 }
2553 }
2554 }
2555 %}
2556
2557 enc_class REX_reg(rRegI reg)
2558 %{
2559 if ($reg$$reg >= 8) {
2560 emit_opcode(cbuf, Assembler::REX_B);
2561 }
2562 %}
2563
2564 enc_class REX_reg_wide(rRegI reg)
2565 %{
2566 if ($reg$$reg < 8) {
2567 emit_opcode(cbuf, Assembler::REX_W);
2568 } else {
2569 emit_opcode(cbuf, Assembler::REX_WB);
2570 }
2571 %}
2572
2573 enc_class REX_reg_reg(rRegI dst, rRegI src)
2574 %{
2575 if ($dst$$reg < 8) {
2576 if ($src$$reg >= 8) {
2577 emit_opcode(cbuf, Assembler::REX_B);
2578 }
2579 } else {
2580 if ($src$$reg < 8) {
2581 emit_opcode(cbuf, Assembler::REX_R);
2582 } else {
2583 emit_opcode(cbuf, Assembler::REX_RB);
2584 }
2585 }
2586 %}
2587
2588 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2589 %{
2590 if ($dst$$reg < 8) {
2591 if ($src$$reg < 8) {
2592 emit_opcode(cbuf, Assembler::REX_W);
2593 } else {
2594 emit_opcode(cbuf, Assembler::REX_WB);
2595 }
2596 } else {
2597 if ($src$$reg < 8) {
2598 emit_opcode(cbuf, Assembler::REX_WR);
2599 } else {
2600 emit_opcode(cbuf, Assembler::REX_WRB);
2601 }
2602 }
2603 %}
2604
2605 enc_class REX_reg_mem(rRegI reg, memory mem)
2606 %{
2607 if ($reg$$reg < 8) {
2608 if ($mem$$base < 8) {
2609 if ($mem$$index >= 8) {
2610 emit_opcode(cbuf, Assembler::REX_X);
2611 }
2612 } else {
2613 if ($mem$$index < 8) {
2614 emit_opcode(cbuf, Assembler::REX_B);
2615 } else {
2616 emit_opcode(cbuf, Assembler::REX_XB);
2617 }
2618 }
2619 } else {
2620 if ($mem$$base < 8) {
2621 if ($mem$$index < 8) {
2622 emit_opcode(cbuf, Assembler::REX_R);
2623 } else {
2624 emit_opcode(cbuf, Assembler::REX_RX);
2625 }
2626 } else {
2627 if ($mem$$index < 8) {
2628 emit_opcode(cbuf, Assembler::REX_RB);
2629 } else {
2630 emit_opcode(cbuf, Assembler::REX_RXB);
2631 }
2632 }
2633 }
2634 %}
2635
2636 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2637 %{
2638 if ($reg$$reg < 8) {
2639 if ($mem$$base < 8) {
2640 if ($mem$$index < 8) {
2641 emit_opcode(cbuf, Assembler::REX_W);
2642 } else {
2643 emit_opcode(cbuf, Assembler::REX_WX);
2644 }
2645 } else {
2646 if ($mem$$index < 8) {
2647 emit_opcode(cbuf, Assembler::REX_WB);
2648 } else {
2649 emit_opcode(cbuf, Assembler::REX_WXB);
2650 }
2651 }
2652 } else {
2653 if ($mem$$base < 8) {
2654 if ($mem$$index < 8) {
2655 emit_opcode(cbuf, Assembler::REX_WR);
2656 } else {
2657 emit_opcode(cbuf, Assembler::REX_WRX);
2658 }
2659 } else {
2660 if ($mem$$index < 8) {
2661 emit_opcode(cbuf, Assembler::REX_WRB);
2662 } else {
2663 emit_opcode(cbuf, Assembler::REX_WRXB);
2664 }
2665 }
2666 }
2667 %}
2668
2669 enc_class reg_mem(rRegI ereg, memory mem)
2670 %{
2671 // High registers handle in encode_RegMem
2672 int reg = $ereg$$reg;
2673 int base = $mem$$base;
2674 int index = $mem$$index;
2675 int scale = $mem$$scale;
2676 int disp = $mem$$disp;
2677 bool disp_is_oop = $mem->disp_is_oop();
2678
2679 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
2680 %}
2681
2682 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2683 %{
2684 int rm_byte_opcode = $rm_opcode$$constant;
2685
2686 // High registers handle in encode_RegMem
2687 int base = $mem$$base;
2688 int index = $mem$$index;
2689 int scale = $mem$$scale;
2690 int displace = $mem$$disp;
2691
2692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
2693 // working with static
2694 // globals
2695 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2696 disp_is_oop);
2697 %}
2698
2699 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2700 %{
2701 int reg_encoding = $dst$$reg;
2702 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2703 int index = 0x04; // 0x04 indicates no index
2704 int scale = 0x00; // 0x00 indicates no scale
2705 int displace = $src1$$constant; // 0x00 indicates no displacement
2706 bool disp_is_oop = false;
2707 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2708 disp_is_oop);
2709 %}
2710
2711 enc_class neg_reg(rRegI dst)
2712 %{
2713 int dstenc = $dst$$reg;
2714 if (dstenc >= 8) {
2715 emit_opcode(cbuf, Assembler::REX_B);
2716 dstenc -= 8;
2717 }
2718 // NEG $dst
2719 emit_opcode(cbuf, 0xF7);
2720 emit_rm(cbuf, 0x3, 0x03, dstenc);
2721 %}
2722
2723 enc_class neg_reg_wide(rRegI dst)
2724 %{
2725 int dstenc = $dst$$reg;
2726 if (dstenc < 8) {
2727 emit_opcode(cbuf, Assembler::REX_W);
2728 } else {
2729 emit_opcode(cbuf, Assembler::REX_WB);
2730 dstenc -= 8;
2731 }
2732 // NEG $dst
2733 emit_opcode(cbuf, 0xF7);
2734 emit_rm(cbuf, 0x3, 0x03, dstenc);
2735 %}
2736
2737 enc_class setLT_reg(rRegI dst)
2738 %{
2739 int dstenc = $dst$$reg;
2740 if (dstenc >= 8) {
2741 emit_opcode(cbuf, Assembler::REX_B);
2742 dstenc -= 8;
2743 } else if (dstenc >= 4) {
2744 emit_opcode(cbuf, Assembler::REX);
2745 }
2746 // SETLT $dst
2747 emit_opcode(cbuf, 0x0F);
2748 emit_opcode(cbuf, 0x9C);
2749 emit_rm(cbuf, 0x3, 0x0, dstenc);
2750 %}
2751
2752 enc_class setNZ_reg(rRegI dst)
2753 %{
2754 int dstenc = $dst$$reg;
2755 if (dstenc >= 8) {
2756 emit_opcode(cbuf, Assembler::REX_B);
2757 dstenc -= 8;
2758 } else if (dstenc >= 4) {
2759 emit_opcode(cbuf, Assembler::REX);
2760 }
2761 // SETNZ $dst
2762 emit_opcode(cbuf, 0x0F);
2763 emit_opcode(cbuf, 0x95);
2764 emit_rm(cbuf, 0x3, 0x0, dstenc);
2765 %}
2766
2767
2768 // Compare the lonogs and set -1, 0, or 1 into dst
2769 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2770 %{
2771 int src1enc = $src1$$reg;
2772 int src2enc = $src2$$reg;
2773 int dstenc = $dst$$reg;
2774
2775 // cmpq $src1, $src2
2776 if (src1enc < 8) {
2777 if (src2enc < 8) {
2778 emit_opcode(cbuf, Assembler::REX_W);
2779 } else {
2780 emit_opcode(cbuf, Assembler::REX_WB);
2781 }
2782 } else {
2783 if (src2enc < 8) {
2784 emit_opcode(cbuf, Assembler::REX_WR);
2785 } else {
2786 emit_opcode(cbuf, Assembler::REX_WRB);
2787 }
2788 }
2789 emit_opcode(cbuf, 0x3B);
2790 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2791
2792 // movl $dst, -1
2793 if (dstenc >= 8) {
2794 emit_opcode(cbuf, Assembler::REX_B);
2795 }
2796 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2797 emit_d32(cbuf, -1);
2798
2799 // jl,s done
2800 emit_opcode(cbuf, 0x7C);
2801 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2802
2803 // setne $dst
2804 if (dstenc >= 4) {
2805 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2806 }
2807 emit_opcode(cbuf, 0x0F);
2808 emit_opcode(cbuf, 0x95);
2809 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2810
2811 // movzbl $dst, $dst
2812 if (dstenc >= 4) {
2813 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2814 }
2815 emit_opcode(cbuf, 0x0F);
2816 emit_opcode(cbuf, 0xB6);
2817 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2818 %}
2819
2820 enc_class Push_ResultXD(regD dst) %{
2821 MacroAssembler _masm(&cbuf);
2822 __ fstp_d(Address(rsp, 0));
2823 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2824 __ addptr(rsp, 8);
2825 %}
2826
2827 enc_class Push_SrcXD(regD src) %{
2828 MacroAssembler _masm(&cbuf);
2829 __ subptr(rsp, 8);
2830 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2831 __ fld_d(Address(rsp, 0));
2832 %}
2833
2834
2835 // obj: object to lock
2836 // box: box address (header location) -- killed
2837 // tmp: rax -- killed
2838 // scr: rbx -- killed
2839 //
2840 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2841 // from i486.ad. See that file for comments.
2842 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2843 // use the shorter encoding. (Movl clears the high-order 32-bits).
2844
2845
2846 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2847 %{
2848 Register objReg = as_Register((int)$obj$$reg);
2849 Register boxReg = as_Register((int)$box$$reg);
2850 Register tmpReg = as_Register($tmp$$reg);
2851 Register scrReg = as_Register($scr$$reg);
2852 MacroAssembler masm(&cbuf);
2853
2854 // Verify uniqueness of register assignments -- necessary but not sufficient
2855 assert (objReg != boxReg && objReg != tmpReg &&
2856 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2857
2858 if (_counters != NULL) {
2859 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2860 }
2861 if (EmitSync & 1) {
2862 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2863 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2864 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2865 } else
2866 if (EmitSync & 2) {
2867 Label DONE_LABEL;
2868 if (UseBiasedLocking) {
2869 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2870 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2871 }
2872 // QQQ was movl...
2873 masm.movptr(tmpReg, 0x1);
2874 masm.orptr(tmpReg, Address(objReg, 0));
2875 masm.movptr(Address(boxReg, 0), tmpReg);
2876 if (os::is_MP()) {
2877 masm.lock();
2878 }
2879 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2880 masm.jcc(Assembler::equal, DONE_LABEL);
2881
2882 // Recursive locking
2883 masm.subptr(tmpReg, rsp);
2884 masm.andptr(tmpReg, 7 - os::vm_page_size());
2885 masm.movptr(Address(boxReg, 0), tmpReg);
2886
2887 masm.bind(DONE_LABEL);
2888 masm.nop(); // avoid branch to branch
2889 } else {
2890 Label DONE_LABEL, IsInflated, Egress;
2891
2892 masm.movptr(tmpReg, Address(objReg, 0)) ;
2893 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2894 masm.jcc (Assembler::notZero, IsInflated) ;
2895
2896 // it's stack-locked, biased or neutral
2897 // TODO: optimize markword triage order to reduce the number of
2898 // conditional branches in the most common cases.
2899 // Beware -- there's a subtle invariant that fetch of the markword
2900 // at [FETCH], below, will never observe a biased encoding (*101b).
2901 // If this invariant is not held we'll suffer exclusion (safety) failure.
2902
2903 if (UseBiasedLocking && !UseOptoBiasInlining) {
2904 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
2905 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
2906 }
2907
2908 // was q will it destroy high?
2909 masm.orl (tmpReg, 1) ;
2910 masm.movptr(Address(boxReg, 0), tmpReg) ;
2911 if (os::is_MP()) { masm.lock(); }
2912 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2913 if (_counters != NULL) {
2914 masm.cond_inc32(Assembler::equal,
2915 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2916 }
2917 masm.jcc (Assembler::equal, DONE_LABEL);
2918
2919 // Recursive locking
2920 masm.subptr(tmpReg, rsp);
2921 masm.andptr(tmpReg, 7 - os::vm_page_size());
2922 masm.movptr(Address(boxReg, 0), tmpReg);
2923 if (_counters != NULL) {
2924 masm.cond_inc32(Assembler::equal,
2925 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2926 }
2927 masm.jmp (DONE_LABEL) ;
2928
2929 masm.bind (IsInflated) ;
2930 // It's inflated
2931
2932 // TODO: someday avoid the ST-before-CAS penalty by
2933 // relocating (deferring) the following ST.
2934 // We should also think about trying a CAS without having
2935 // fetched _owner. If the CAS is successful we may
2936 // avoid an RTO->RTS upgrade on the $line.
2937 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2938 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2939
2940 masm.mov (boxReg, tmpReg) ;
2941 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2942 masm.testptr(tmpReg, tmpReg) ;
2943 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2944
2945 // It's inflated and appears unlocked
2946 if (os::is_MP()) { masm.lock(); }
2947 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2948 // Intentional fall-through into DONE_LABEL ...
2949
2950 masm.bind (DONE_LABEL) ;
2951 masm.nop () ; // avoid jmp to jmp
2952 }
2953 %}
2954
2955 // obj: object to unlock
2956 // box: box address (displaced header location), killed
2957 // RBX: killed tmp; cannot be obj nor box
2958 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
2959 %{
2960
2961 Register objReg = as_Register($obj$$reg);
2962 Register boxReg = as_Register($box$$reg);
2963 Register tmpReg = as_Register($tmp$$reg);
2964 MacroAssembler masm(&cbuf);
2965
2966 if (EmitSync & 4) {
2967 masm.cmpptr(rsp, 0) ;
2968 } else
2969 if (EmitSync & 8) {
2970 Label DONE_LABEL;
2971 if (UseBiasedLocking) {
2972 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2973 }
2974
2975 // Check whether the displaced header is 0
2976 //(=> recursive unlock)
2977 masm.movptr(tmpReg, Address(boxReg, 0));
2978 masm.testptr(tmpReg, tmpReg);
2979 masm.jcc(Assembler::zero, DONE_LABEL);
2980
2981 // If not recursive lock, reset the header to displaced header
2982 if (os::is_MP()) {
2983 masm.lock();
2984 }
2985 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2986 masm.bind(DONE_LABEL);
2987 masm.nop(); // avoid branch to branch
2988 } else {
2989 Label DONE_LABEL, Stacked, CheckSucc ;
2990
2991 if (UseBiasedLocking && !UseOptoBiasInlining) {
2992 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2993 }
2994
2995 masm.movptr(tmpReg, Address(objReg, 0)) ;
2996 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
2997 masm.jcc (Assembler::zero, DONE_LABEL) ;
2998 masm.testl (tmpReg, 0x02) ;
2999 masm.jcc (Assembler::zero, Stacked) ;
3000
3001 // It's inflated
3002 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3003 masm.xorptr(boxReg, r15_thread) ;
3004 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3005 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3006 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3007 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3008 masm.jcc (Assembler::notZero, CheckSucc) ;
3009 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3010 masm.jmp (DONE_LABEL) ;
3011
3012 if ((EmitSync & 65536) == 0) {
3013 Label LSuccess, LGoSlowPath ;
3014 masm.bind (CheckSucc) ;
3015 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3016 masm.jcc (Assembler::zero, LGoSlowPath) ;
3017
3018 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3019 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3020 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3021 // are all faster when the write buffer is populated.
3022 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3023 if (os::is_MP()) {
3024 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3025 }
3026 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3027 masm.jcc (Assembler::notZero, LSuccess) ;
3028
3029 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3030 if (os::is_MP()) { masm.lock(); }
3031 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3032 masm.jcc (Assembler::notEqual, LSuccess) ;
3033 // Intentional fall-through into slow-path
3034
3035 masm.bind (LGoSlowPath) ;
3036 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3037 masm.jmp (DONE_LABEL) ;
3038
3039 masm.bind (LSuccess) ;
3040 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3041 masm.jmp (DONE_LABEL) ;
3042 }
3043
3044 masm.bind (Stacked) ;
3045 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3046 if (os::is_MP()) { masm.lock(); }
3047 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3048
3049 if (EmitSync & 65536) {
3050 masm.bind (CheckSucc) ;
3051 }
3052 masm.bind(DONE_LABEL);
3053 if (EmitSync & 32768) {
3054 masm.nop(); // avoid branch to branch
3055 }
3056 }
3057 %}
3058
3059
3060 enc_class enc_rethrow()
3061 %{
3062 cbuf.set_insts_mark();
3063 emit_opcode(cbuf, 0xE9); // jmp entry
3064 emit_d32_reloc(cbuf,
3065 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
3066 runtime_call_Relocation::spec(),
3067 RELOC_DISP32);
3068 %}
3069
3070 %}
3071
3072
3073
3074 //----------FRAME--------------------------------------------------------------
3075 // Definition of frame structure and management information.
3076 //
3077 // S T A C K L A Y O U T Allocators stack-slot number
3078 // | (to get allocators register number
3079 // G Owned by | | v add OptoReg::stack0())
3080 // r CALLER | |
3081 // o | +--------+ pad to even-align allocators stack-slot
3082 // w V | pad0 | numbers; owned by CALLER
3083 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3084 // h ^ | in | 5
3085 // | | args | 4 Holes in incoming args owned by SELF
3086 // | | | | 3
3087 // | | +--------+
3088 // V | | old out| Empty on Intel, window on Sparc
3089 // | old |preserve| Must be even aligned.
3090 // | SP-+--------+----> Matcher::_old_SP, even aligned
3091 // | | in | 3 area for Intel ret address
3092 // Owned by |preserve| Empty on Sparc.
3093 // SELF +--------+
3094 // | | pad2 | 2 pad to align old SP
3095 // | +--------+ 1
3096 // | | locks | 0
3097 // | +--------+----> OptoReg::stack0(), even aligned
3098 // | | pad1 | 11 pad to align new SP
3099 // | +--------+
3100 // | | | 10
3101 // | | spills | 9 spills
3102 // V | | 8 (pad0 slot for callee)
3103 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3104 // ^ | out | 7
3105 // | | args | 6 Holes in outgoing args owned by CALLEE
3106 // Owned by +--------+
3107 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3108 // | new |preserve| Must be even-aligned.
3109 // | SP-+--------+----> Matcher::_new_SP, even aligned
3110 // | | |
3111 //
3112 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3113 // known from SELF's arguments and the Java calling convention.
3114 // Region 6-7 is determined per call site.
3115 // Note 2: If the calling convention leaves holes in the incoming argument
3116 // area, those holes are owned by SELF. Holes in the outgoing area
3117 // are owned by the CALLEE. Holes should not be nessecary in the
3118 // incoming area, as the Java calling convention is completely under
3119 // the control of the AD file. Doubles can be sorted and packed to
3120 // avoid holes. Holes in the outgoing arguments may be nessecary for
3121 // varargs C calling conventions.
3122 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3123 // even aligned with pad0 as needed.
3124 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3125 // region 6-11 is even aligned; it may be padded out more so that
3126 // the region from SP to FP meets the minimum stack alignment.
3127 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3128 // alignment. Region 11, pad1, may be dynamically extended so that
3129 // SP meets the minimum alignment.
3130
3131 frame
3132 %{
3133 // What direction does stack grow in (assumed to be same for C & Java)
3134 stack_direction(TOWARDS_LOW);
3135
3136 // These three registers define part of the calling convention
3137 // between compiled code and the interpreter.
3138 inline_cache_reg(RAX); // Inline Cache Register
3139 interpreter_method_oop_reg(RBX); // Method Oop Register when
3140 // calling interpreter
3141
3142 // Optional: name the operand used by cisc-spilling to access
3143 // [stack_pointer + offset]
3144 cisc_spilling_operand_name(indOffset32);
3145
3146 // Number of stack slots consumed by locking an object
3147 sync_stack_slots(2);
3148
3149 // Compiled code's Frame Pointer
3150 frame_pointer(RSP);
3151
3152 // Interpreter stores its frame pointer in a register which is
3153 // stored to the stack by I2CAdaptors.
3154 // I2CAdaptors convert from interpreted java to compiled java.
3155 interpreter_frame_pointer(RBP);
3156
3157 // Stack alignment requirement
3158 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3159
3160 // Number of stack slots between incoming argument block and the start of
3161 // a new frame. The PROLOG must add this many slots to the stack. The
3162 // EPILOG must remove this many slots. amd64 needs two slots for
3163 // return address.
3164 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
3165
3166 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3167 // for calls to C. Supports the var-args backing area for register parms.
3168 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3169
3170 // The after-PROLOG location of the return address. Location of
3171 // return address specifies a type (REG or STACK) and a number
3172 // representing the register number (i.e. - use a register name) or
3173 // stack slot.
3174 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3175 // Otherwise, it is above the locks and verification slot and alignment word
3176 return_addr(STACK - 2 +
3177 round_to((Compile::current()->in_preserve_stack_slots() +
3178 Compile::current()->fixed_slots()),
3179 stack_alignment_in_slots()));
3180
3181 // Body of function which returns an integer array locating
3182 // arguments either in registers or in stack slots. Passed an array
3183 // of ideal registers called "sig" and a "length" count. Stack-slot
3184 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3185 // arguments for a CALLEE. Incoming stack arguments are
3186 // automatically biased by the preserve_stack_slots field above.
3187
3188 calling_convention
3189 %{
3190 // No difference between ingoing/outgoing just pass false
3191 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3192 %}
3193
3194 c_calling_convention
3195 %{
3196 // This is obviously always outgoing
3197 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3198 %}
3199
3200 // Location of compiled Java return values. Same as C for now.
3201 return_value
3202 %{
3203 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
3204 "only return normal values");
3205
3206 static const int lo[Op_RegL + 1] = {
3207 0,
3208 0,
3209 RAX_num, // Op_RegN
3210 RAX_num, // Op_RegI
3211 RAX_num, // Op_RegP
3212 XMM0_num, // Op_RegF
3213 XMM0_num, // Op_RegD
3214 RAX_num // Op_RegL
3215 };
3216 static const int hi[Op_RegL + 1] = {
3217 0,
3218 0,
3219 OptoReg::Bad, // Op_RegN
3220 OptoReg::Bad, // Op_RegI
3221 RAX_H_num, // Op_RegP
3222 OptoReg::Bad, // Op_RegF
3223 XMM0_H_num, // Op_RegD
3224 RAX_H_num // Op_RegL
3225 };
3226 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
3227 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3228 %}
3229 %}
3230
3231 //----------ATTRIBUTES---------------------------------------------------------
3232 //----------Operand Attributes-------------------------------------------------
3233 op_attrib op_cost(0); // Required cost attribute
3234
3235 //----------Instruction Attributes---------------------------------------------
3236 ins_attrib ins_cost(100); // Required cost attribute
3237 ins_attrib ins_size(8); // Required size attribute (in bits)
3238 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3239 // a non-matching short branch variant
3240 // of some long branch?
3241 ins_attrib ins_alignment(1); // Required alignment attribute (must
3242 // be a power of 2) specifies the
3243 // alignment that some part of the
3244 // instruction (not necessarily the
3245 // start) requires. If > 1, a
3246 // compute_padding() function must be
3247 // provided for the instruction
3248
3249 //----------OPERANDS-----------------------------------------------------------
3250 // Operand definitions must precede instruction definitions for correct parsing
3251 // in the ADLC because operands constitute user defined types which are used in
3252 // instruction definitions.
3253
3254 //----------Simple Operands----------------------------------------------------
3255 // Immediate Operands
3256 // Integer Immediate
3257 operand immI()
3258 %{
3259 match(ConI);
3260
3261 op_cost(10);
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Constant for test vs zero
3267 operand immI0()
3268 %{
3269 predicate(n->get_int() == 0);
3270 match(ConI);
3271
3272 op_cost(0);
3273 format %{ %}
3274 interface(CONST_INTER);
3275 %}
3276
3277 // Constant for increment
3278 operand immI1()
3279 %{
3280 predicate(n->get_int() == 1);
3281 match(ConI);
3282
3283 op_cost(0);
3284 format %{ %}
3285 interface(CONST_INTER);
3286 %}
3287
3288 // Constant for decrement
3289 operand immI_M1()
3290 %{
3291 predicate(n->get_int() == -1);
3292 match(ConI);
3293
3294 op_cost(0);
3295 format %{ %}
3296 interface(CONST_INTER);
3297 %}
3298
3299 // Valid scale values for addressing modes
3300 operand immI2()
3301 %{
3302 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3303 match(ConI);
3304
3305 format %{ %}
3306 interface(CONST_INTER);
3307 %}
3308
3309 operand immI8()
3310 %{
3311 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3312 match(ConI);
3313
3314 op_cost(5);
3315 format %{ %}
3316 interface(CONST_INTER);
3317 %}
3318
3319 operand immI16()
3320 %{
3321 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3322 match(ConI);
3323
3324 op_cost(10);
3325 format %{ %}
3326 interface(CONST_INTER);
3327 %}
3328
3329 // Constant for long shifts
3330 operand immI_32()
3331 %{
3332 predicate( n->get_int() == 32 );
3333 match(ConI);
3334
3335 op_cost(0);
3336 format %{ %}
3337 interface(CONST_INTER);
3338 %}
3339
3340 // Constant for long shifts
3341 operand immI_64()
3342 %{
3343 predicate( n->get_int() == 64 );
3344 match(ConI);
3345
3346 op_cost(0);
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 // Pointer Immediate
3352 operand immP()
3353 %{
3354 match(ConP);
3355
3356 op_cost(10);
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360
3361 // NULL Pointer Immediate
3362 operand immP0()
3363 %{
3364 predicate(n->get_ptr() == 0);
3365 match(ConP);
3366
3367 op_cost(5);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Pointer Immediate
3373 operand immN() %{
3374 match(ConN);
3375
3376 op_cost(10);
3377 format %{ %}
3378 interface(CONST_INTER);
3379 %}
3380
3381 // NULL Pointer Immediate
3382 operand immN0() %{
3383 predicate(n->get_narrowcon() == 0);
3384 match(ConN);
3385
3386 op_cost(5);
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3390
3391 operand immP31()
3392 %{
3393 predicate(!n->as_Type()->type()->isa_oopptr()
3394 && (n->get_ptr() >> 31) == 0);
3395 match(ConP);
3396
3397 op_cost(5);
3398 format %{ %}
3399 interface(CONST_INTER);
3400 %}
3401
3402
3403 // Long Immediate
3404 operand immL()
3405 %{
3406 match(ConL);
3407
3408 op_cost(20);
3409 format %{ %}
3410 interface(CONST_INTER);
3411 %}
3412
3413 // Long Immediate 8-bit
3414 operand immL8()
3415 %{
3416 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3417 match(ConL);
3418
3419 op_cost(5);
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 // Long Immediate 32-bit unsigned
3425 operand immUL32()
3426 %{
3427 predicate(n->get_long() == (unsigned int) (n->get_long()));
3428 match(ConL);
3429
3430 op_cost(10);
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3434
3435 // Long Immediate 32-bit signed
3436 operand immL32()
3437 %{
3438 predicate(n->get_long() == (int) (n->get_long()));
3439 match(ConL);
3440
3441 op_cost(15);
3442 format %{ %}
3443 interface(CONST_INTER);
3444 %}
3445
3446 // Long Immediate zero
3447 operand immL0()
3448 %{
3449 predicate(n->get_long() == 0L);
3450 match(ConL);
3451
3452 op_cost(10);
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 // Constant for increment
3458 operand immL1()
3459 %{
3460 predicate(n->get_long() == 1);
3461 match(ConL);
3462
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Constant for decrement
3468 operand immL_M1()
3469 %{
3470 predicate(n->get_long() == -1);
3471 match(ConL);
3472
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3476
3477 // Long Immediate: the value 10
3478 operand immL10()
3479 %{
3480 predicate(n->get_long() == 10);
3481 match(ConL);
3482
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3486
3487 // Long immediate from 0 to 127.
3488 // Used for a shorter form of long mul by 10.
3489 operand immL_127()
3490 %{
3491 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3492 match(ConL);
3493
3494 op_cost(10);
3495 format %{ %}
3496 interface(CONST_INTER);
3497 %}
3498
3499 // Long Immediate: low 32-bit mask
3500 operand immL_32bits()
3501 %{
3502 predicate(n->get_long() == 0xFFFFFFFFL);
3503 match(ConL);
3504 op_cost(20);
3505
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3509
3510 // Float Immediate zero
3511 operand immF0()
3512 %{
3513 predicate(jint_cast(n->getf()) == 0);
3514 match(ConF);
3515
3516 op_cost(5);
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 // Float Immediate
3522 operand immF()
3523 %{
3524 match(ConF);
3525
3526 op_cost(15);
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530
3531 // Double Immediate zero
3532 operand immD0()
3533 %{
3534 predicate(jlong_cast(n->getd()) == 0);
3535 match(ConD);
3536
3537 op_cost(5);
3538 format %{ %}
3539 interface(CONST_INTER);
3540 %}
3541
3542 // Double Immediate
3543 operand immD()
3544 %{
3545 match(ConD);
3546
3547 op_cost(15);
3548 format %{ %}
3549 interface(CONST_INTER);
3550 %}
3551
3552 // Immediates for special shifts (sign extend)
3553
3554 // Constants for increment
3555 operand immI_16()
3556 %{
3557 predicate(n->get_int() == 16);
3558 match(ConI);
3559
3560 format %{ %}
3561 interface(CONST_INTER);
3562 %}
3563
3564 operand immI_24()
3565 %{
3566 predicate(n->get_int() == 24);
3567 match(ConI);
3568
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 // Constant for byte-wide masking
3574 operand immI_255()
3575 %{
3576 predicate(n->get_int() == 255);
3577 match(ConI);
3578
3579 format %{ %}
3580 interface(CONST_INTER);
3581 %}
3582
3583 // Constant for short-wide masking
3584 operand immI_65535()
3585 %{
3586 predicate(n->get_int() == 65535);
3587 match(ConI);
3588
3589 format %{ %}
3590 interface(CONST_INTER);
3591 %}
3592
3593 // Constant for byte-wide masking
3594 operand immL_255()
3595 %{
3596 predicate(n->get_long() == 255);
3597 match(ConL);
3598
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 // Constant for short-wide masking
3604 operand immL_65535()
3605 %{
3606 predicate(n->get_long() == 65535);
3607 match(ConL);
3608
3609 format %{ %}
3610 interface(CONST_INTER);
3611 %}
3612
3613 // Register Operands
3614 // Integer Register
3615 operand rRegI()
3616 %{
3617 constraint(ALLOC_IN_RC(int_reg));
3618 match(RegI);
3619
3620 match(rax_RegI);
3621 match(rbx_RegI);
3622 match(rcx_RegI);
3623 match(rdx_RegI);
3624 match(rdi_RegI);
3625
3626 format %{ %}
3627 interface(REG_INTER);
3628 %}
3629
3630 // Special Registers
3631 operand rax_RegI()
3632 %{
3633 constraint(ALLOC_IN_RC(int_rax_reg));
3634 match(RegI);
3635 match(rRegI);
3636
3637 format %{ "RAX" %}
3638 interface(REG_INTER);
3639 %}
3640
3641 // Special Registers
3642 operand rbx_RegI()
3643 %{
3644 constraint(ALLOC_IN_RC(int_rbx_reg));
3645 match(RegI);
3646 match(rRegI);
3647
3648 format %{ "RBX" %}
3649 interface(REG_INTER);
3650 %}
3651
3652 operand rcx_RegI()
3653 %{
3654 constraint(ALLOC_IN_RC(int_rcx_reg));
3655 match(RegI);
3656 match(rRegI);
3657
3658 format %{ "RCX" %}
3659 interface(REG_INTER);
3660 %}
3661
3662 operand rdx_RegI()
3663 %{
3664 constraint(ALLOC_IN_RC(int_rdx_reg));
3665 match(RegI);
3666 match(rRegI);
3667
3668 format %{ "RDX" %}
3669 interface(REG_INTER);
3670 %}
3671
3672 operand rdi_RegI()
3673 %{
3674 constraint(ALLOC_IN_RC(int_rdi_reg));
3675 match(RegI);
3676 match(rRegI);
3677
3678 format %{ "RDI" %}
3679 interface(REG_INTER);
3680 %}
3681
3682 operand no_rcx_RegI()
3683 %{
3684 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3685 match(RegI);
3686 match(rax_RegI);
3687 match(rbx_RegI);
3688 match(rdx_RegI);
3689 match(rdi_RegI);
3690
3691 format %{ %}
3692 interface(REG_INTER);
3693 %}
3694
3695 operand no_rax_rdx_RegI()
3696 %{
3697 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3698 match(RegI);
3699 match(rbx_RegI);
3700 match(rcx_RegI);
3701 match(rdi_RegI);
3702
3703 format %{ %}
3704 interface(REG_INTER);
3705 %}
3706
3707 // Pointer Register
3708 operand any_RegP()
3709 %{
3710 constraint(ALLOC_IN_RC(any_reg));
3711 match(RegP);
3712 match(rax_RegP);
3713 match(rbx_RegP);
3714 match(rdi_RegP);
3715 match(rsi_RegP);
3716 match(rbp_RegP);
3717 match(r15_RegP);
3718 match(rRegP);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand rRegP()
3725 %{
3726 constraint(ALLOC_IN_RC(ptr_reg));
3727 match(RegP);
3728 match(rax_RegP);
3729 match(rbx_RegP);
3730 match(rdi_RegP);
3731 match(rsi_RegP);
3732 match(rbp_RegP);
3733 match(r15_RegP); // See Q&A below about r15_RegP.
3734
3735 format %{ %}
3736 interface(REG_INTER);
3737 %}
3738
3739 operand rRegN() %{
3740 constraint(ALLOC_IN_RC(int_reg));
3741 match(RegN);
3742
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3746
3747 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3748 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3749 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3750 // The output of an instruction is controlled by the allocator, which respects
3751 // register class masks, not match rules. Unless an instruction mentions
3752 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3753 // by the allocator as an input.
3754
3755 operand no_rax_RegP()
3756 %{
3757 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3758 match(RegP);
3759 match(rbx_RegP);
3760 match(rsi_RegP);
3761 match(rdi_RegP);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 operand no_rbp_RegP()
3768 %{
3769 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3770 match(RegP);
3771 match(rbx_RegP);
3772 match(rsi_RegP);
3773 match(rdi_RegP);
3774
3775 format %{ %}
3776 interface(REG_INTER);
3777 %}
3778
3779 operand no_rax_rbx_RegP()
3780 %{
3781 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3782 match(RegP);
3783 match(rsi_RegP);
3784 match(rdi_RegP);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 // Special Registers
3791 // Return a pointer value
3792 operand rax_RegP()
3793 %{
3794 constraint(ALLOC_IN_RC(ptr_rax_reg));
3795 match(RegP);
3796 match(rRegP);
3797
3798 format %{ %}
3799 interface(REG_INTER);
3800 %}
3801
3802 // Special Registers
3803 // Return a compressed pointer value
3804 operand rax_RegN()
3805 %{
3806 constraint(ALLOC_IN_RC(int_rax_reg));
3807 match(RegN);
3808 match(rRegN);
3809
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3813
3814 // Used in AtomicAdd
3815 operand rbx_RegP()
3816 %{
3817 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3818 match(RegP);
3819 match(rRegP);
3820
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3824
3825 operand rsi_RegP()
3826 %{
3827 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3828 match(RegP);
3829 match(rRegP);
3830
3831 format %{ %}
3832 interface(REG_INTER);
3833 %}
3834
3835 // Used in rep stosq
3836 operand rdi_RegP()
3837 %{
3838 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3839 match(RegP);
3840 match(rRegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand rbp_RegP()
3847 %{
3848 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3849 match(RegP);
3850 match(rRegP);
3851
3852 format %{ %}
3853 interface(REG_INTER);
3854 %}
3855
3856 operand r15_RegP()
3857 %{
3858 constraint(ALLOC_IN_RC(ptr_r15_reg));
3859 match(RegP);
3860 match(rRegP);
3861
3862 format %{ %}
3863 interface(REG_INTER);
3864 %}
3865
3866 operand rRegL()
3867 %{
3868 constraint(ALLOC_IN_RC(long_reg));
3869 match(RegL);
3870 match(rax_RegL);
3871 match(rdx_RegL);
3872
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877 // Special Registers
3878 operand no_rax_rdx_RegL()
3879 %{
3880 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3881 match(RegL);
3882 match(rRegL);
3883
3884 format %{ %}
3885 interface(REG_INTER);
3886 %}
3887
3888 operand no_rax_RegL()
3889 %{
3890 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3891 match(RegL);
3892 match(rRegL);
3893 match(rdx_RegL);
3894
3895 format %{ %}
3896 interface(REG_INTER);
3897 %}
3898
3899 operand no_rcx_RegL()
3900 %{
3901 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3902 match(RegL);
3903 match(rRegL);
3904
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3908
3909 operand rax_RegL()
3910 %{
3911 constraint(ALLOC_IN_RC(long_rax_reg));
3912 match(RegL);
3913 match(rRegL);
3914
3915 format %{ "RAX" %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand rcx_RegL()
3920 %{
3921 constraint(ALLOC_IN_RC(long_rcx_reg));
3922 match(RegL);
3923 match(rRegL);
3924
3925 format %{ %}
3926 interface(REG_INTER);
3927 %}
3928
3929 operand rdx_RegL()
3930 %{
3931 constraint(ALLOC_IN_RC(long_rdx_reg));
3932 match(RegL);
3933 match(rRegL);
3934
3935 format %{ %}
3936 interface(REG_INTER);
3937 %}
3938
3939 // Flags register, used as output of compare instructions
3940 operand rFlagsReg()
3941 %{
3942 constraint(ALLOC_IN_RC(int_flags));
3943 match(RegFlags);
3944
3945 format %{ "RFLAGS" %}
3946 interface(REG_INTER);
3947 %}
3948
3949 // Flags register, used as output of FLOATING POINT compare instructions
3950 operand rFlagsRegU()
3951 %{
3952 constraint(ALLOC_IN_RC(int_flags));
3953 match(RegFlags);
3954
3955 format %{ "RFLAGS_U" %}
3956 interface(REG_INTER);
3957 %}
3958
3959 operand rFlagsRegUCF() %{
3960 constraint(ALLOC_IN_RC(int_flags));
3961 match(RegFlags);
3962 predicate(false);
3963
3964 format %{ "RFLAGS_U_CF" %}
3965 interface(REG_INTER);
3966 %}
3967
3968 // Float register operands
3969 operand regF()
3970 %{
3971 constraint(ALLOC_IN_RC(float_reg));
3972 match(RegF);
3973
3974 format %{ %}
3975 interface(REG_INTER);
3976 %}
3977
3978 // Double register operands
3979 operand regD()
3980 %{
3981 constraint(ALLOC_IN_RC(double_reg));
3982 match(RegD);
3983
3984 format %{ %}
3985 interface(REG_INTER);
3986 %}
3987
3988
3989 //----------Memory Operands----------------------------------------------------
3990 // Direct Memory Operand
3991 // operand direct(immP addr)
3992 // %{
3993 // match(addr);
3994
3995 // format %{ "[$addr]" %}
3996 // interface(MEMORY_INTER) %{
3997 // base(0xFFFFFFFF);
3998 // index(0x4);
3999 // scale(0x0);
4000 // disp($addr);
4001 // %}
4002 // %}
4003
4004 // Indirect Memory Operand
4005 operand indirect(any_RegP reg)
4006 %{
4007 constraint(ALLOC_IN_RC(ptr_reg));
4008 match(reg);
4009
4010 format %{ "[$reg]" %}
4011 interface(MEMORY_INTER) %{
4012 base($reg);
4013 index(0x4);
4014 scale(0x0);
4015 disp(0x0);
4016 %}
4017 %}
4018
4019 // Indirect Memory Plus Short Offset Operand
4020 operand indOffset8(any_RegP reg, immL8 off)
4021 %{
4022 constraint(ALLOC_IN_RC(ptr_reg));
4023 match(AddP reg off);
4024
4025 format %{ "[$reg + $off (8-bit)]" %}
4026 interface(MEMORY_INTER) %{
4027 base($reg);
4028 index(0x4);
4029 scale(0x0);
4030 disp($off);
4031 %}
4032 %}
4033
4034 // Indirect Memory Plus Long Offset Operand
4035 operand indOffset32(any_RegP reg, immL32 off)
4036 %{
4037 constraint(ALLOC_IN_RC(ptr_reg));
4038 match(AddP reg off);
4039
4040 format %{ "[$reg + $off (32-bit)]" %}
4041 interface(MEMORY_INTER) %{
4042 base($reg);
4043 index(0x4);
4044 scale(0x0);
4045 disp($off);
4046 %}
4047 %}
4048
4049 // Indirect Memory Plus Index Register Plus Offset Operand
4050 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
4051 %{
4052 constraint(ALLOC_IN_RC(ptr_reg));
4053 match(AddP (AddP reg lreg) off);
4054
4055 op_cost(10);
4056 format %{"[$reg + $off + $lreg]" %}
4057 interface(MEMORY_INTER) %{
4058 base($reg);
4059 index($lreg);
4060 scale(0x0);
4061 disp($off);
4062 %}
4063 %}
4064
4065 // Indirect Memory Plus Index Register Plus Offset Operand
4066 operand indIndex(any_RegP reg, rRegL lreg)
4067 %{
4068 constraint(ALLOC_IN_RC(ptr_reg));
4069 match(AddP reg lreg);
4070
4071 op_cost(10);
4072 format %{"[$reg + $lreg]" %}
4073 interface(MEMORY_INTER) %{
4074 base($reg);
4075 index($lreg);
4076 scale(0x0);
4077 disp(0x0);
4078 %}
4079 %}
4080
4081 // Indirect Memory Times Scale Plus Index Register
4082 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
4083 %{
4084 constraint(ALLOC_IN_RC(ptr_reg));
4085 match(AddP reg (LShiftL lreg scale));
4086
4087 op_cost(10);
4088 format %{"[$reg + $lreg << $scale]" %}
4089 interface(MEMORY_INTER) %{
4090 base($reg);
4091 index($lreg);
4092 scale($scale);
4093 disp(0x0);
4094 %}
4095 %}
4096
4097 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4098 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
4099 %{
4100 constraint(ALLOC_IN_RC(ptr_reg));
4101 match(AddP (AddP reg (LShiftL lreg scale)) off);
4102
4103 op_cost(10);
4104 format %{"[$reg + $off + $lreg << $scale]" %}
4105 interface(MEMORY_INTER) %{
4106 base($reg);
4107 index($lreg);
4108 scale($scale);
4109 disp($off);
4110 %}
4111 %}
4112
4113 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4114 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
4115 %{
4116 constraint(ALLOC_IN_RC(ptr_reg));
4117 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4118 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
4119
4120 op_cost(10);
4121 format %{"[$reg + $off + $idx << $scale]" %}
4122 interface(MEMORY_INTER) %{
4123 base($reg);
4124 index($idx);
4125 scale($scale);
4126 disp($off);
4127 %}
4128 %}
4129
4130 // Indirect Narrow Oop Plus Offset Operand
4131 // Note: x86 architecture doesn't support "scale * index + offset" without a base
4132 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
4133 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
4134 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
4135 constraint(ALLOC_IN_RC(ptr_reg));
4136 match(AddP (DecodeN reg) off);
4137
4138 op_cost(10);
4139 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
4140 interface(MEMORY_INTER) %{
4141 base(0xc); // R12
4142 index($reg);
4143 scale(0x3);
4144 disp($off);
4145 %}
4146 %}
4147
4148 // Indirect Memory Operand
4149 operand indirectNarrow(rRegN reg)
4150 %{
4151 predicate(Universe::narrow_oop_shift() == 0);
4152 constraint(ALLOC_IN_RC(ptr_reg));
4153 match(DecodeN reg);
4154
4155 format %{ "[$reg]" %}
4156 interface(MEMORY_INTER) %{
4157 base($reg);
4158 index(0x4);
4159 scale(0x0);
4160 disp(0x0);
4161 %}
4162 %}
4163
4164 // Indirect Memory Plus Short Offset Operand
4165 operand indOffset8Narrow(rRegN reg, immL8 off)
4166 %{
4167 predicate(Universe::narrow_oop_shift() == 0);
4168 constraint(ALLOC_IN_RC(ptr_reg));
4169 match(AddP (DecodeN reg) off);
4170
4171 format %{ "[$reg + $off (8-bit)]" %}
4172 interface(MEMORY_INTER) %{
4173 base($reg);
4174 index(0x4);
4175 scale(0x0);
4176 disp($off);
4177 %}
4178 %}
4179
4180 // Indirect Memory Plus Long Offset Operand
4181 operand indOffset32Narrow(rRegN reg, immL32 off)
4182 %{
4183 predicate(Universe::narrow_oop_shift() == 0);
4184 constraint(ALLOC_IN_RC(ptr_reg));
4185 match(AddP (DecodeN reg) off);
4186
4187 format %{ "[$reg + $off (32-bit)]" %}
4188 interface(MEMORY_INTER) %{
4189 base($reg);
4190 index(0x4);
4191 scale(0x0);
4192 disp($off);
4193 %}
4194 %}
4195
4196 // Indirect Memory Plus Index Register Plus Offset Operand
4197 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4198 %{
4199 predicate(Universe::narrow_oop_shift() == 0);
4200 constraint(ALLOC_IN_RC(ptr_reg));
4201 match(AddP (AddP (DecodeN reg) lreg) off);
4202
4203 op_cost(10);
4204 format %{"[$reg + $off + $lreg]" %}
4205 interface(MEMORY_INTER) %{
4206 base($reg);
4207 index($lreg);
4208 scale(0x0);
4209 disp($off);
4210 %}
4211 %}
4212
4213 // Indirect Memory Plus Index Register Plus Offset Operand
4214 operand indIndexNarrow(rRegN reg, rRegL lreg)
4215 %{
4216 predicate(Universe::narrow_oop_shift() == 0);
4217 constraint(ALLOC_IN_RC(ptr_reg));
4218 match(AddP (DecodeN reg) lreg);
4219
4220 op_cost(10);
4221 format %{"[$reg + $lreg]" %}
4222 interface(MEMORY_INTER) %{
4223 base($reg);
4224 index($lreg);
4225 scale(0x0);
4226 disp(0x0);
4227 %}
4228 %}
4229
4230 // Indirect Memory Times Scale Plus Index Register
4231 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4232 %{
4233 predicate(Universe::narrow_oop_shift() == 0);
4234 constraint(ALLOC_IN_RC(ptr_reg));
4235 match(AddP (DecodeN reg) (LShiftL lreg scale));
4236
4237 op_cost(10);
4238 format %{"[$reg + $lreg << $scale]" %}
4239 interface(MEMORY_INTER) %{
4240 base($reg);
4241 index($lreg);
4242 scale($scale);
4243 disp(0x0);
4244 %}
4245 %}
4246
4247 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4248 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4249 %{
4250 predicate(Universe::narrow_oop_shift() == 0);
4251 constraint(ALLOC_IN_RC(ptr_reg));
4252 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4253
4254 op_cost(10);
4255 format %{"[$reg + $off + $lreg << $scale]" %}
4256 interface(MEMORY_INTER) %{
4257 base($reg);
4258 index($lreg);
4259 scale($scale);
4260 disp($off);
4261 %}
4262 %}
4263
4264 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4265 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4266 %{
4267 constraint(ALLOC_IN_RC(ptr_reg));
4268 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4269 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4270
4271 op_cost(10);
4272 format %{"[$reg + $off + $idx << $scale]" %}
4273 interface(MEMORY_INTER) %{
4274 base($reg);
4275 index($idx);
4276 scale($scale);
4277 disp($off);
4278 %}
4279 %}
4280
4281
4282 //----------Special Memory Operands--------------------------------------------
4283 // Stack Slot Operand - This operand is used for loading and storing temporary
4284 // values on the stack where a match requires a value to
4285 // flow through memory.
4286 operand stackSlotP(sRegP reg)
4287 %{
4288 constraint(ALLOC_IN_RC(stack_slots));
4289 // No match rule because this operand is only generated in matching
4290
4291 format %{ "[$reg]" %}
4292 interface(MEMORY_INTER) %{
4293 base(0x4); // RSP
4294 index(0x4); // No Index
4295 scale(0x0); // No Scale
4296 disp($reg); // Stack Offset
4297 %}
4298 %}
4299
4300 operand stackSlotI(sRegI reg)
4301 %{
4302 constraint(ALLOC_IN_RC(stack_slots));
4303 // No match rule because this operand is only generated in matching
4304
4305 format %{ "[$reg]" %}
4306 interface(MEMORY_INTER) %{
4307 base(0x4); // RSP
4308 index(0x4); // No Index
4309 scale(0x0); // No Scale
4310 disp($reg); // Stack Offset
4311 %}
4312 %}
4313
4314 operand stackSlotF(sRegF reg)
4315 %{
4316 constraint(ALLOC_IN_RC(stack_slots));
4317 // No match rule because this operand is only generated in matching
4318
4319 format %{ "[$reg]" %}
4320 interface(MEMORY_INTER) %{
4321 base(0x4); // RSP
4322 index(0x4); // No Index
4323 scale(0x0); // No Scale
4324 disp($reg); // Stack Offset
4325 %}
4326 %}
4327
4328 operand stackSlotD(sRegD reg)
4329 %{
4330 constraint(ALLOC_IN_RC(stack_slots));
4331 // No match rule because this operand is only generated in matching
4332
4333 format %{ "[$reg]" %}
4334 interface(MEMORY_INTER) %{
4335 base(0x4); // RSP
4336 index(0x4); // No Index
4337 scale(0x0); // No Scale
4338 disp($reg); // Stack Offset
4339 %}
4340 %}
4341 operand stackSlotL(sRegL reg)
4342 %{
4343 constraint(ALLOC_IN_RC(stack_slots));
4344 // No match rule because this operand is only generated in matching
4345
4346 format %{ "[$reg]" %}
4347 interface(MEMORY_INTER) %{
4348 base(0x4); // RSP
4349 index(0x4); // No Index
4350 scale(0x0); // No Scale
4351 disp($reg); // Stack Offset
4352 %}
4353 %}
4354
4355 //----------Conditional Branch Operands----------------------------------------
4356 // Comparison Op - This is the operation of the comparison, and is limited to
4357 // the following set of codes:
4358 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4359 //
4360 // Other attributes of the comparison, such as unsignedness, are specified
4361 // by the comparison instruction that sets a condition code flags register.
4362 // That result is represented by a flags operand whose subtype is appropriate
4363 // to the unsignedness (etc.) of the comparison.
4364 //
4365 // Later, the instruction which matches both the Comparison Op (a Bool) and
4366 // the flags (produced by the Cmp) specifies the coding of the comparison op
4367 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4368
4369 // Comparision Code
4370 operand cmpOp()
4371 %{
4372 match(Bool);
4373
4374 format %{ "" %}
4375 interface(COND_INTER) %{
4376 equal(0x4, "e");
4377 not_equal(0x5, "ne");
4378 less(0xC, "l");
4379 greater_equal(0xD, "ge");
4380 less_equal(0xE, "le");
4381 greater(0xF, "g");
4382 %}
4383 %}
4384
4385 // Comparison Code, unsigned compare. Used by FP also, with
4386 // C2 (unordered) turned into GT or LT already. The other bits
4387 // C0 and C3 are turned into Carry & Zero flags.
4388 operand cmpOpU()
4389 %{
4390 match(Bool);
4391
4392 format %{ "" %}
4393 interface(COND_INTER) %{
4394 equal(0x4, "e");
4395 not_equal(0x5, "ne");
4396 less(0x2, "b");
4397 greater_equal(0x3, "nb");
4398 less_equal(0x6, "be");
4399 greater(0x7, "nbe");
4400 %}
4401 %}
4402
4403
4404 // Floating comparisons that don't require any fixup for the unordered case
4405 operand cmpOpUCF() %{
4406 match(Bool);
4407 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4408 n->as_Bool()->_test._test == BoolTest::ge ||
4409 n->as_Bool()->_test._test == BoolTest::le ||
4410 n->as_Bool()->_test._test == BoolTest::gt);
4411 format %{ "" %}
4412 interface(COND_INTER) %{
4413 equal(0x4, "e");
4414 not_equal(0x5, "ne");
4415 less(0x2, "b");
4416 greater_equal(0x3, "nb");
4417 less_equal(0x6, "be");
4418 greater(0x7, "nbe");
4419 %}
4420 %}
4421
4422
4423 // Floating comparisons that can be fixed up with extra conditional jumps
4424 operand cmpOpUCF2() %{
4425 match(Bool);
4426 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4427 n->as_Bool()->_test._test == BoolTest::eq);
4428 format %{ "" %}
4429 interface(COND_INTER) %{
4430 equal(0x4, "e");
4431 not_equal(0x5, "ne");
4432 less(0x2, "b");
4433 greater_equal(0x3, "nb");
4434 less_equal(0x6, "be");
4435 greater(0x7, "nbe");
4436 %}
4437 %}
4438
4439
4440 //----------OPERAND CLASSES----------------------------------------------------
4441 // Operand Classes are groups of operands that are used as to simplify
4442 // instruction definitions by not requiring the AD writer to specify separate
4443 // instructions for every form of operand when the instruction accepts
4444 // multiple operand types with the same basic encoding and format. The classic
4445 // case of this is memory operands.
4446
4447 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4448 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4449 indCompressedOopOffset,
4450 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4451 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4452 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4453
4454 //----------PIPELINE-----------------------------------------------------------
4455 // Rules which define the behavior of the target architectures pipeline.
4456 pipeline %{
4457
4458 //----------ATTRIBUTES---------------------------------------------------------
4459 attributes %{
4460 variable_size_instructions; // Fixed size instructions
4461 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4462 instruction_unit_size = 1; // An instruction is 1 bytes long
4463 instruction_fetch_unit_size = 16; // The processor fetches one line
4464 instruction_fetch_units = 1; // of 16 bytes
4465
4466 // List of nop instructions
4467 nops( MachNop );
4468 %}
4469
4470 //----------RESOURCES----------------------------------------------------------
4471 // Resources are the functional units available to the machine
4472
4473 // Generic P2/P3 pipeline
4474 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4475 // 3 instructions decoded per cycle.
4476 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4477 // 3 ALU op, only ALU0 handles mul instructions.
4478 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4479 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4480 BR, FPU,
4481 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4482
4483 //----------PIPELINE DESCRIPTION-----------------------------------------------
4484 // Pipeline Description specifies the stages in the machine's pipeline
4485
4486 // Generic P2/P3 pipeline
4487 pipe_desc(S0, S1, S2, S3, S4, S5);
4488
4489 //----------PIPELINE CLASSES---------------------------------------------------
4490 // Pipeline Classes describe the stages in which input and output are
4491 // referenced by the hardware pipeline.
4492
4493 // Naming convention: ialu or fpu
4494 // Then: _reg
4495 // Then: _reg if there is a 2nd register
4496 // Then: _long if it's a pair of instructions implementing a long
4497 // Then: _fat if it requires the big decoder
4498 // Or: _mem if it requires the big decoder and a memory unit.
4499
4500 // Integer ALU reg operation
4501 pipe_class ialu_reg(rRegI dst)
4502 %{
4503 single_instruction;
4504 dst : S4(write);
4505 dst : S3(read);
4506 DECODE : S0; // any decoder
4507 ALU : S3; // any alu
4508 %}
4509
4510 // Long ALU reg operation
4511 pipe_class ialu_reg_long(rRegL dst)
4512 %{
4513 instruction_count(2);
4514 dst : S4(write);
4515 dst : S3(read);
4516 DECODE : S0(2); // any 2 decoders
4517 ALU : S3(2); // both alus
4518 %}
4519
4520 // Integer ALU reg operation using big decoder
4521 pipe_class ialu_reg_fat(rRegI dst)
4522 %{
4523 single_instruction;
4524 dst : S4(write);
4525 dst : S3(read);
4526 D0 : S0; // big decoder only
4527 ALU : S3; // any alu
4528 %}
4529
4530 // Long ALU reg operation using big decoder
4531 pipe_class ialu_reg_long_fat(rRegL dst)
4532 %{
4533 instruction_count(2);
4534 dst : S4(write);
4535 dst : S3(read);
4536 D0 : S0(2); // big decoder only; twice
4537 ALU : S3(2); // any 2 alus
4538 %}
4539
4540 // Integer ALU reg-reg operation
4541 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4542 %{
4543 single_instruction;
4544 dst : S4(write);
4545 src : S3(read);
4546 DECODE : S0; // any decoder
4547 ALU : S3; // any alu
4548 %}
4549
4550 // Long ALU reg-reg operation
4551 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4552 %{
4553 instruction_count(2);
4554 dst : S4(write);
4555 src : S3(read);
4556 DECODE : S0(2); // any 2 decoders
4557 ALU : S3(2); // both alus
4558 %}
4559
4560 // Integer ALU reg-reg operation
4561 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4562 %{
4563 single_instruction;
4564 dst : S4(write);
4565 src : S3(read);
4566 D0 : S0; // big decoder only
4567 ALU : S3; // any alu
4568 %}
4569
4570 // Long ALU reg-reg operation
4571 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4572 %{
4573 instruction_count(2);
4574 dst : S4(write);
4575 src : S3(read);
4576 D0 : S0(2); // big decoder only; twice
4577 ALU : S3(2); // both alus
4578 %}
4579
4580 // Integer ALU reg-mem operation
4581 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4582 %{
4583 single_instruction;
4584 dst : S5(write);
4585 mem : S3(read);
4586 D0 : S0; // big decoder only
4587 ALU : S4; // any alu
4588 MEM : S3; // any mem
4589 %}
4590
4591 // Integer mem operation (prefetch)
4592 pipe_class ialu_mem(memory mem)
4593 %{
4594 single_instruction;
4595 mem : S3(read);
4596 D0 : S0; // big decoder only
4597 MEM : S3; // any mem
4598 %}
4599
4600 // Integer Store to Memory
4601 pipe_class ialu_mem_reg(memory mem, rRegI src)
4602 %{
4603 single_instruction;
4604 mem : S3(read);
4605 src : S5(read);
4606 D0 : S0; // big decoder only
4607 ALU : S4; // any alu
4608 MEM : S3;
4609 %}
4610
4611 // // Long Store to Memory
4612 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4613 // %{
4614 // instruction_count(2);
4615 // mem : S3(read);
4616 // src : S5(read);
4617 // D0 : S0(2); // big decoder only; twice
4618 // ALU : S4(2); // any 2 alus
4619 // MEM : S3(2); // Both mems
4620 // %}
4621
4622 // Integer Store to Memory
4623 pipe_class ialu_mem_imm(memory mem)
4624 %{
4625 single_instruction;
4626 mem : S3(read);
4627 D0 : S0; // big decoder only
4628 ALU : S4; // any alu
4629 MEM : S3;
4630 %}
4631
4632 // Integer ALU0 reg-reg operation
4633 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4634 %{
4635 single_instruction;
4636 dst : S4(write);
4637 src : S3(read);
4638 D0 : S0; // Big decoder only
4639 ALU0 : S3; // only alu0
4640 %}
4641
4642 // Integer ALU0 reg-mem operation
4643 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4644 %{
4645 single_instruction;
4646 dst : S5(write);
4647 mem : S3(read);
4648 D0 : S0; // big decoder only
4649 ALU0 : S4; // ALU0 only
4650 MEM : S3; // any mem
4651 %}
4652
4653 // Integer ALU reg-reg operation
4654 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4655 %{
4656 single_instruction;
4657 cr : S4(write);
4658 src1 : S3(read);
4659 src2 : S3(read);
4660 DECODE : S0; // any decoder
4661 ALU : S3; // any alu
4662 %}
4663
4664 // Integer ALU reg-imm operation
4665 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4666 %{
4667 single_instruction;
4668 cr : S4(write);
4669 src1 : S3(read);
4670 DECODE : S0; // any decoder
4671 ALU : S3; // any alu
4672 %}
4673
4674 // Integer ALU reg-mem operation
4675 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4676 %{
4677 single_instruction;
4678 cr : S4(write);
4679 src1 : S3(read);
4680 src2 : S3(read);
4681 D0 : S0; // big decoder only
4682 ALU : S4; // any alu
4683 MEM : S3;
4684 %}
4685
4686 // Conditional move reg-reg
4687 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4688 %{
4689 instruction_count(4);
4690 y : S4(read);
4691 q : S3(read);
4692 p : S3(read);
4693 DECODE : S0(4); // any decoder
4694 %}
4695
4696 // Conditional move reg-reg
4697 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4698 %{
4699 single_instruction;
4700 dst : S4(write);
4701 src : S3(read);
4702 cr : S3(read);
4703 DECODE : S0; // any decoder
4704 %}
4705
4706 // Conditional move reg-mem
4707 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4708 %{
4709 single_instruction;
4710 dst : S4(write);
4711 src : S3(read);
4712 cr : S3(read);
4713 DECODE : S0; // any decoder
4714 MEM : S3;
4715 %}
4716
4717 // Conditional move reg-reg long
4718 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4719 %{
4720 single_instruction;
4721 dst : S4(write);
4722 src : S3(read);
4723 cr : S3(read);
4724 DECODE : S0(2); // any 2 decoders
4725 %}
4726
4727 // XXX
4728 // // Conditional move double reg-reg
4729 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4730 // %{
4731 // single_instruction;
4732 // dst : S4(write);
4733 // src : S3(read);
4734 // cr : S3(read);
4735 // DECODE : S0; // any decoder
4736 // %}
4737
4738 // Float reg-reg operation
4739 pipe_class fpu_reg(regD dst)
4740 %{
4741 instruction_count(2);
4742 dst : S3(read);
4743 DECODE : S0(2); // any 2 decoders
4744 FPU : S3;
4745 %}
4746
4747 // Float reg-reg operation
4748 pipe_class fpu_reg_reg(regD dst, regD src)
4749 %{
4750 instruction_count(2);
4751 dst : S4(write);
4752 src : S3(read);
4753 DECODE : S0(2); // any 2 decoders
4754 FPU : S3;
4755 %}
4756
4757 // Float reg-reg operation
4758 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4759 %{
4760 instruction_count(3);
4761 dst : S4(write);
4762 src1 : S3(read);
4763 src2 : S3(read);
4764 DECODE : S0(3); // any 3 decoders
4765 FPU : S3(2);
4766 %}
4767
4768 // Float reg-reg operation
4769 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4770 %{
4771 instruction_count(4);
4772 dst : S4(write);
4773 src1 : S3(read);
4774 src2 : S3(read);
4775 src3 : S3(read);
4776 DECODE : S0(4); // any 3 decoders
4777 FPU : S3(2);
4778 %}
4779
4780 // Float reg-reg operation
4781 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4782 %{
4783 instruction_count(4);
4784 dst : S4(write);
4785 src1 : S3(read);
4786 src2 : S3(read);
4787 src3 : S3(read);
4788 DECODE : S1(3); // any 3 decoders
4789 D0 : S0; // Big decoder only
4790 FPU : S3(2);
4791 MEM : S3;
4792 %}
4793
4794 // Float reg-mem operation
4795 pipe_class fpu_reg_mem(regD dst, memory mem)
4796 %{
4797 instruction_count(2);
4798 dst : S5(write);
4799 mem : S3(read);
4800 D0 : S0; // big decoder only
4801 DECODE : S1; // any decoder for FPU POP
4802 FPU : S4;
4803 MEM : S3; // any mem
4804 %}
4805
4806 // Float reg-mem operation
4807 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4808 %{
4809 instruction_count(3);
4810 dst : S5(write);
4811 src1 : S3(read);
4812 mem : S3(read);
4813 D0 : S0; // big decoder only
4814 DECODE : S1(2); // any decoder for FPU POP
4815 FPU : S4;
4816 MEM : S3; // any mem
4817 %}
4818
4819 // Float mem-reg operation
4820 pipe_class fpu_mem_reg(memory mem, regD src)
4821 %{
4822 instruction_count(2);
4823 src : S5(read);
4824 mem : S3(read);
4825 DECODE : S0; // any decoder for FPU PUSH
4826 D0 : S1; // big decoder only
4827 FPU : S4;
4828 MEM : S3; // any mem
4829 %}
4830
4831 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4832 %{
4833 instruction_count(3);
4834 src1 : S3(read);
4835 src2 : S3(read);
4836 mem : S3(read);
4837 DECODE : S0(2); // any decoder for FPU PUSH
4838 D0 : S1; // big decoder only
4839 FPU : S4;
4840 MEM : S3; // any mem
4841 %}
4842
4843 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4844 %{
4845 instruction_count(3);
4846 src1 : S3(read);
4847 src2 : S3(read);
4848 mem : S4(read);
4849 DECODE : S0; // any decoder for FPU PUSH
4850 D0 : S0(2); // big decoder only
4851 FPU : S4;
4852 MEM : S3(2); // any mem
4853 %}
4854
4855 pipe_class fpu_mem_mem(memory dst, memory src1)
4856 %{
4857 instruction_count(2);
4858 src1 : S3(read);
4859 dst : S4(read);
4860 D0 : S0(2); // big decoder only
4861 MEM : S3(2); // any mem
4862 %}
4863
4864 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4865 %{
4866 instruction_count(3);
4867 src1 : S3(read);
4868 src2 : S3(read);
4869 dst : S4(read);
4870 D0 : S0(3); // big decoder only
4871 FPU : S4;
4872 MEM : S3(3); // any mem
4873 %}
4874
4875 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4876 %{
4877 instruction_count(3);
4878 src1 : S4(read);
4879 mem : S4(read);
4880 DECODE : S0; // any decoder for FPU PUSH
4881 D0 : S0(2); // big decoder only
4882 FPU : S4;
4883 MEM : S3(2); // any mem
4884 %}
4885
4886 // Float load constant
4887 pipe_class fpu_reg_con(regD dst)
4888 %{
4889 instruction_count(2);
4890 dst : S5(write);
4891 D0 : S0; // big decoder only for the load
4892 DECODE : S1; // any decoder for FPU POP
4893 FPU : S4;
4894 MEM : S3; // any mem
4895 %}
4896
4897 // Float load constant
4898 pipe_class fpu_reg_reg_con(regD dst, regD src)
4899 %{
4900 instruction_count(3);
4901 dst : S5(write);
4902 src : S3(read);
4903 D0 : S0; // big decoder only for the load
4904 DECODE : S1(2); // any decoder for FPU POP
4905 FPU : S4;
4906 MEM : S3; // any mem
4907 %}
4908
4909 // UnConditional branch
4910 pipe_class pipe_jmp(label labl)
4911 %{
4912 single_instruction;
4913 BR : S3;
4914 %}
4915
4916 // Conditional branch
4917 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4918 %{
4919 single_instruction;
4920 cr : S1(read);
4921 BR : S3;
4922 %}
4923
4924 // Allocation idiom
4925 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4926 %{
4927 instruction_count(1); force_serialization;
4928 fixed_latency(6);
4929 heap_ptr : S3(read);
4930 DECODE : S0(3);
4931 D0 : S2;
4932 MEM : S3;
4933 ALU : S3(2);
4934 dst : S5(write);
4935 BR : S5;
4936 %}
4937
4938 // Generic big/slow expanded idiom
4939 pipe_class pipe_slow()
4940 %{
4941 instruction_count(10); multiple_bundles; force_serialization;
4942 fixed_latency(100);
4943 D0 : S0(2);
4944 MEM : S3(2);
4945 %}
4946
4947 // The real do-nothing guy
4948 pipe_class empty()
4949 %{
4950 instruction_count(0);
4951 %}
4952
4953 // Define the class for the Nop node
4954 define
4955 %{
4956 MachNop = empty;
4957 %}
4958
4959 %}
4960
4961 //----------INSTRUCTIONS-------------------------------------------------------
4962 //
4963 // match -- States which machine-independent subtree may be replaced
4964 // by this instruction.
4965 // ins_cost -- The estimated cost of this instruction is used by instruction
4966 // selection to identify a minimum cost tree of machine
4967 // instructions that matches a tree of machine-independent
4968 // instructions.
4969 // format -- A string providing the disassembly for this instruction.
4970 // The value of an instruction's operand may be inserted
4971 // by referring to it with a '$' prefix.
4972 // opcode -- Three instruction opcodes may be provided. These are referred
4973 // to within an encode class as $primary, $secondary, and $tertiary
4974 // rrspectively. The primary opcode is commonly used to
4975 // indicate the type of machine instruction, while secondary
4976 // and tertiary are often used for prefix options or addressing
4977 // modes.
4978 // ins_encode -- A list of encode classes with parameters. The encode class
4979 // name must have been defined in an 'enc_class' specification
4980 // in the encode section of the architecture description.
4981
4982
4983 //----------Load/Store/Move Instructions---------------------------------------
4984 //----------Load Instructions--------------------------------------------------
4985
4986 // Load Byte (8 bit signed)
4987 instruct loadB(rRegI dst, memory mem)
4988 %{
4989 match(Set dst (LoadB mem));
4990
4991 ins_cost(125);
4992 format %{ "movsbl $dst, $mem\t# byte" %}
4993
4994 ins_encode %{
4995 __ movsbl($dst$$Register, $mem$$Address);
4996 %}
4997
4998 ins_pipe(ialu_reg_mem);
4999 %}
5000
5001 // Load Byte (8 bit signed) into Long Register
5002 instruct loadB2L(rRegL dst, memory mem)
5003 %{
5004 match(Set dst (ConvI2L (LoadB mem)));
5005
5006 ins_cost(125);
5007 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5008
5009 ins_encode %{
5010 __ movsbq($dst$$Register, $mem$$Address);
5011 %}
5012
5013 ins_pipe(ialu_reg_mem);
5014 %}
5015
5016 // Load Unsigned Byte (8 bit UNsigned)
5017 instruct loadUB(rRegI dst, memory mem)
5018 %{
5019 match(Set dst (LoadUB mem));
5020
5021 ins_cost(125);
5022 format %{ "movzbl $dst, $mem\t# ubyte" %}
5023
5024 ins_encode %{
5025 __ movzbl($dst$$Register, $mem$$Address);
5026 %}
5027
5028 ins_pipe(ialu_reg_mem);
5029 %}
5030
5031 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5032 instruct loadUB2L(rRegL dst, memory mem)
5033 %{
5034 match(Set dst (ConvI2L (LoadUB mem)));
5035
5036 ins_cost(125);
5037 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5038
5039 ins_encode %{
5040 __ movzbq($dst$$Register, $mem$$Address);
5041 %}
5042
5043 ins_pipe(ialu_reg_mem);
5044 %}
5045
5046 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
5047 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
5048 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5049 effect(KILL cr);
5050
5051 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
5052 "andl $dst, $mask" %}
5053 ins_encode %{
5054 Register Rdst = $dst$$Register;
5055 __ movzbq(Rdst, $mem$$Address);
5056 __ andl(Rdst, $mask$$constant);
5057 %}
5058 ins_pipe(ialu_reg_mem);
5059 %}
5060
5061 // Load Short (16 bit signed)
5062 instruct loadS(rRegI dst, memory mem)
5063 %{
5064 match(Set dst (LoadS mem));
5065
5066 ins_cost(125);
5067 format %{ "movswl $dst, $mem\t# short" %}
5068
5069 ins_encode %{
5070 __ movswl($dst$$Register, $mem$$Address);
5071 %}
5072
5073 ins_pipe(ialu_reg_mem);
5074 %}
5075
5076 // Load Short (16 bit signed) to Byte (8 bit signed)
5077 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5078 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5079
5080 ins_cost(125);
5081 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5082 ins_encode %{
5083 __ movsbl($dst$$Register, $mem$$Address);
5084 %}
5085 ins_pipe(ialu_reg_mem);
5086 %}
5087
5088 // Load Short (16 bit signed) into Long Register
5089 instruct loadS2L(rRegL dst, memory mem)
5090 %{
5091 match(Set dst (ConvI2L (LoadS mem)));
5092
5093 ins_cost(125);
5094 format %{ "movswq $dst, $mem\t# short -> long" %}
5095
5096 ins_encode %{
5097 __ movswq($dst$$Register, $mem$$Address);
5098 %}
5099
5100 ins_pipe(ialu_reg_mem);
5101 %}
5102
5103 // Load Unsigned Short/Char (16 bit UNsigned)
5104 instruct loadUS(rRegI dst, memory mem)
5105 %{
5106 match(Set dst (LoadUS mem));
5107
5108 ins_cost(125);
5109 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5110
5111 ins_encode %{
5112 __ movzwl($dst$$Register, $mem$$Address);
5113 %}
5114
5115 ins_pipe(ialu_reg_mem);
5116 %}
5117
5118 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5119 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5120 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5121
5122 ins_cost(125);
5123 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5124 ins_encode %{
5125 __ movsbl($dst$$Register, $mem$$Address);
5126 %}
5127 ins_pipe(ialu_reg_mem);
5128 %}
5129
5130 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5131 instruct loadUS2L(rRegL dst, memory mem)
5132 %{
5133 match(Set dst (ConvI2L (LoadUS mem)));
5134
5135 ins_cost(125);
5136 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5137
5138 ins_encode %{
5139 __ movzwq($dst$$Register, $mem$$Address);
5140 %}
5141
5142 ins_pipe(ialu_reg_mem);
5143 %}
5144
5145 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5146 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5147 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5148
5149 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5150 ins_encode %{
5151 __ movzbq($dst$$Register, $mem$$Address);
5152 %}
5153 ins_pipe(ialu_reg_mem);
5154 %}
5155
5156 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
5157 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
5158 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5159 effect(KILL cr);
5160
5161 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5162 "andl $dst, $mask" %}
5163 ins_encode %{
5164 Register Rdst = $dst$$Register;
5165 __ movzwq(Rdst, $mem$$Address);
5166 __ andl(Rdst, $mask$$constant);
5167 %}
5168 ins_pipe(ialu_reg_mem);
5169 %}
5170
5171 // Load Integer
5172 instruct loadI(rRegI dst, memory mem)
5173 %{
5174 match(Set dst (LoadI mem));
5175
5176 ins_cost(125);
5177 format %{ "movl $dst, $mem\t# int" %}
5178
5179 ins_encode %{
5180 __ movl($dst$$Register, $mem$$Address);
5181 %}
5182
5183 ins_pipe(ialu_reg_mem);
5184 %}
5185
5186 // Load Integer (32 bit signed) to Byte (8 bit signed)
5187 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5188 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5189
5190 ins_cost(125);
5191 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5192 ins_encode %{
5193 __ movsbl($dst$$Register, $mem$$Address);
5194 %}
5195 ins_pipe(ialu_reg_mem);
5196 %}
5197
5198 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5199 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5200 match(Set dst (AndI (LoadI mem) mask));
5201
5202 ins_cost(125);
5203 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5204 ins_encode %{
5205 __ movzbl($dst$$Register, $mem$$Address);
5206 %}
5207 ins_pipe(ialu_reg_mem);
5208 %}
5209
5210 // Load Integer (32 bit signed) to Short (16 bit signed)
5211 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5212 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5213
5214 ins_cost(125);
5215 format %{ "movswl $dst, $mem\t# int -> short" %}
5216 ins_encode %{
5217 __ movswl($dst$$Register, $mem$$Address);
5218 %}
5219 ins_pipe(ialu_reg_mem);
5220 %}
5221
5222 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5223 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5224 match(Set dst (AndI (LoadI mem) mask));
5225
5226 ins_cost(125);
5227 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5228 ins_encode %{
5229 __ movzwl($dst$$Register, $mem$$Address);
5230 %}
5231 ins_pipe(ialu_reg_mem);
5232 %}
5233
5234 // Load Integer into Long Register
5235 instruct loadI2L(rRegL dst, memory mem)
5236 %{
5237 match(Set dst (ConvI2L (LoadI mem)));
5238
5239 ins_cost(125);
5240 format %{ "movslq $dst, $mem\t# int -> long" %}
5241
5242 ins_encode %{
5243 __ movslq($dst$$Register, $mem$$Address);
5244 %}
5245
5246 ins_pipe(ialu_reg_mem);
5247 %}
5248
5249 // Load Integer with mask 0xFF into Long Register
5250 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5251 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5252
5253 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5254 ins_encode %{
5255 __ movzbq($dst$$Register, $mem$$Address);
5256 %}
5257 ins_pipe(ialu_reg_mem);
5258 %}
5259
5260 // Load Integer with mask 0xFFFF into Long Register
5261 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5262 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5263
5264 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5265 ins_encode %{
5266 __ movzwq($dst$$Register, $mem$$Address);
5267 %}
5268 ins_pipe(ialu_reg_mem);
5269 %}
5270
5271 // Load Integer with a 32-bit mask into Long Register
5272 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5273 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5274 effect(KILL cr);
5275
5276 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
5277 "andl $dst, $mask" %}
5278 ins_encode %{
5279 Register Rdst = $dst$$Register;
5280 __ movl(Rdst, $mem$$Address);
5281 __ andl(Rdst, $mask$$constant);
5282 %}
5283 ins_pipe(ialu_reg_mem);
5284 %}
5285
5286 // Load Unsigned Integer into Long Register
5287 instruct loadUI2L(rRegL dst, memory mem)
5288 %{
5289 match(Set dst (LoadUI2L mem));
5290
5291 ins_cost(125);
5292 format %{ "movl $dst, $mem\t# uint -> long" %}
5293
5294 ins_encode %{
5295 __ movl($dst$$Register, $mem$$Address);
5296 %}
5297
5298 ins_pipe(ialu_reg_mem);
5299 %}
5300
5301 // Load Long
5302 instruct loadL(rRegL dst, memory mem)
5303 %{
5304 match(Set dst (LoadL mem));
5305
5306 ins_cost(125);
5307 format %{ "movq $dst, $mem\t# long" %}
5308
5309 ins_encode %{
5310 __ movq($dst$$Register, $mem$$Address);
5311 %}
5312
5313 ins_pipe(ialu_reg_mem); // XXX
5314 %}
5315
5316 // Load Range
5317 instruct loadRange(rRegI dst, memory mem)
5318 %{
5319 match(Set dst (LoadRange mem));
5320
5321 ins_cost(125); // XXX
5322 format %{ "movl $dst, $mem\t# range" %}
5323 opcode(0x8B);
5324 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5325 ins_pipe(ialu_reg_mem);
5326 %}
5327
5328 // Load Pointer
5329 instruct loadP(rRegP dst, memory mem)
5330 %{
5331 match(Set dst (LoadP mem));
5332
5333 ins_cost(125); // XXX
5334 format %{ "movq $dst, $mem\t# ptr" %}
5335 opcode(0x8B);
5336 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5337 ins_pipe(ialu_reg_mem); // XXX
5338 %}
5339
5340 // Load Compressed Pointer
5341 instruct loadN(rRegN dst, memory mem)
5342 %{
5343 match(Set dst (LoadN mem));
5344
5345 ins_cost(125); // XXX
5346 format %{ "movl $dst, $mem\t# compressed ptr" %}
5347 ins_encode %{
5348 __ movl($dst$$Register, $mem$$Address);
5349 %}
5350 ins_pipe(ialu_reg_mem); // XXX
5351 %}
5352
5353
5354 // Load Klass Pointer
5355 instruct loadKlass(rRegP dst, memory mem)
5356 %{
5357 match(Set dst (LoadKlass mem));
5358
5359 ins_cost(125); // XXX
5360 format %{ "movq $dst, $mem\t# class" %}
5361 opcode(0x8B);
5362 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5363 ins_pipe(ialu_reg_mem); // XXX
5364 %}
5365
5366 // Load narrow Klass Pointer
5367 instruct loadNKlass(rRegN dst, memory mem)
5368 %{
5369 match(Set dst (LoadNKlass mem));
5370
5371 ins_cost(125); // XXX
5372 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5373 ins_encode %{
5374 __ movl($dst$$Register, $mem$$Address);
5375 %}
5376 ins_pipe(ialu_reg_mem); // XXX
5377 %}
5378
5379 // Load Float
5380 instruct loadF(regF dst, memory mem)
5381 %{
5382 match(Set dst (LoadF mem));
5383
5384 ins_cost(145); // XXX
5385 format %{ "movss $dst, $mem\t# float" %}
5386 ins_encode %{
5387 __ movflt($dst$$XMMRegister, $mem$$Address);
5388 %}
5389 ins_pipe(pipe_slow); // XXX
5390 %}
5391
5392 // Load Double
5393 instruct loadD_partial(regD dst, memory mem)
5394 %{
5395 predicate(!UseXmmLoadAndClearUpper);
5396 match(Set dst (LoadD mem));
5397
5398 ins_cost(145); // XXX
5399 format %{ "movlpd $dst, $mem\t# double" %}
5400 ins_encode %{
5401 __ movdbl($dst$$XMMRegister, $mem$$Address);
5402 %}
5403 ins_pipe(pipe_slow); // XXX
5404 %}
5405
5406 instruct loadD(regD dst, memory mem)
5407 %{
5408 predicate(UseXmmLoadAndClearUpper);
5409 match(Set dst (LoadD mem));
5410
5411 ins_cost(145); // XXX
5412 format %{ "movsd $dst, $mem\t# double" %}
5413 ins_encode %{
5414 __ movdbl($dst$$XMMRegister, $mem$$Address);
5415 %}
5416 ins_pipe(pipe_slow); // XXX
5417 %}
5418
5419 // Load Aligned Packed Byte to XMM register
5420 instruct loadA8B(regD dst, memory mem) %{
5421 match(Set dst (Load8B mem));
5422 ins_cost(125);
5423 format %{ "MOVQ $dst,$mem\t! packed8B" %}
5424 ins_encode %{
5425 __ movq($dst$$XMMRegister, $mem$$Address);
5426 %}
5427 ins_pipe( pipe_slow );
5428 %}
5429
5430 // Load Aligned Packed Short to XMM register
5431 instruct loadA4S(regD dst, memory mem) %{
5432 match(Set dst (Load4S mem));
5433 ins_cost(125);
5434 format %{ "MOVQ $dst,$mem\t! packed4S" %}
5435 ins_encode %{
5436 __ movq($dst$$XMMRegister, $mem$$Address);
5437 %}
5438 ins_pipe( pipe_slow );
5439 %}
5440
5441 // Load Aligned Packed Char to XMM register
5442 instruct loadA4C(regD dst, memory mem) %{
5443 match(Set dst (Load4C mem));
5444 ins_cost(125);
5445 format %{ "MOVQ $dst,$mem\t! packed4C" %}
5446 ins_encode %{
5447 __ movq($dst$$XMMRegister, $mem$$Address);
5448 %}
5449 ins_pipe( pipe_slow );
5450 %}
5451
5452 // Load Aligned Packed Integer to XMM register
5453 instruct load2IU(regD dst, memory mem) %{
5454 match(Set dst (Load2I mem));
5455 ins_cost(125);
5456 format %{ "MOVQ $dst,$mem\t! packed2I" %}
5457 ins_encode %{
5458 __ movq($dst$$XMMRegister, $mem$$Address);
5459 %}
5460 ins_pipe( pipe_slow );
5461 %}
5462
5463 // Load Aligned Packed Single to XMM
5464 instruct loadA2F(regD dst, memory mem) %{
5465 match(Set dst (Load2F mem));
5466 ins_cost(125);
5467 format %{ "MOVQ $dst,$mem\t! packed2F" %}
5468 ins_encode %{
5469 __ movq($dst$$XMMRegister, $mem$$Address);
5470 %}
5471 ins_pipe( pipe_slow );
5472 %}
5473
5474 // Load Effective Address
5475 instruct leaP8(rRegP dst, indOffset8 mem)
5476 %{
5477 match(Set dst mem);
5478
5479 ins_cost(110); // XXX
5480 format %{ "leaq $dst, $mem\t# ptr 8" %}
5481 opcode(0x8D);
5482 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5483 ins_pipe(ialu_reg_reg_fat);
5484 %}
5485
5486 instruct leaP32(rRegP dst, indOffset32 mem)
5487 %{
5488 match(Set dst mem);
5489
5490 ins_cost(110);
5491 format %{ "leaq $dst, $mem\t# ptr 32" %}
5492 opcode(0x8D);
5493 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5494 ins_pipe(ialu_reg_reg_fat);
5495 %}
5496
5497 // instruct leaPIdx(rRegP dst, indIndex mem)
5498 // %{
5499 // match(Set dst mem);
5500
5501 // ins_cost(110);
5502 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5503 // opcode(0x8D);
5504 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5505 // ins_pipe(ialu_reg_reg_fat);
5506 // %}
5507
5508 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5509 %{
5510 match(Set dst mem);
5511
5512 ins_cost(110);
5513 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5514 opcode(0x8D);
5515 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5516 ins_pipe(ialu_reg_reg_fat);
5517 %}
5518
5519 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5520 %{
5521 match(Set dst mem);
5522
5523 ins_cost(110);
5524 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5525 opcode(0x8D);
5526 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5527 ins_pipe(ialu_reg_reg_fat);
5528 %}
5529
5530 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5531 %{
5532 match(Set dst mem);
5533
5534 ins_cost(110);
5535 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5536 opcode(0x8D);
5537 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5538 ins_pipe(ialu_reg_reg_fat);
5539 %}
5540
5541 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5542 %{
5543 match(Set dst mem);
5544
5545 ins_cost(110);
5546 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5547 opcode(0x8D);
5548 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5549 ins_pipe(ialu_reg_reg_fat);
5550 %}
5551
5552 // Load Effective Address which uses Narrow (32-bits) oop
5553 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5554 %{
5555 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5556 match(Set dst mem);
5557
5558 ins_cost(110);
5559 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5560 opcode(0x8D);
5561 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5562 ins_pipe(ialu_reg_reg_fat);
5563 %}
5564
5565 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5566 %{
5567 predicate(Universe::narrow_oop_shift() == 0);
5568 match(Set dst mem);
5569
5570 ins_cost(110); // XXX
5571 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5572 opcode(0x8D);
5573 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5574 ins_pipe(ialu_reg_reg_fat);
5575 %}
5576
5577 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5578 %{
5579 predicate(Universe::narrow_oop_shift() == 0);
5580 match(Set dst mem);
5581
5582 ins_cost(110);
5583 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5584 opcode(0x8D);
5585 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5586 ins_pipe(ialu_reg_reg_fat);
5587 %}
5588
5589 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5590 %{
5591 predicate(Universe::narrow_oop_shift() == 0);
5592 match(Set dst mem);
5593
5594 ins_cost(110);
5595 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5596 opcode(0x8D);
5597 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5598 ins_pipe(ialu_reg_reg_fat);
5599 %}
5600
5601 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5602 %{
5603 predicate(Universe::narrow_oop_shift() == 0);
5604 match(Set dst mem);
5605
5606 ins_cost(110);
5607 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5608 opcode(0x8D);
5609 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5610 ins_pipe(ialu_reg_reg_fat);
5611 %}
5612
5613 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5614 %{
5615 predicate(Universe::narrow_oop_shift() == 0);
5616 match(Set dst mem);
5617
5618 ins_cost(110);
5619 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5620 opcode(0x8D);
5621 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5622 ins_pipe(ialu_reg_reg_fat);
5623 %}
5624
5625 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5626 %{
5627 predicate(Universe::narrow_oop_shift() == 0);
5628 match(Set dst mem);
5629
5630 ins_cost(110);
5631 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5632 opcode(0x8D);
5633 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5634 ins_pipe(ialu_reg_reg_fat);
5635 %}
5636
5637 instruct loadConI(rRegI dst, immI src)
5638 %{
5639 match(Set dst src);
5640
5641 format %{ "movl $dst, $src\t# int" %}
5642 ins_encode(load_immI(dst, src));
5643 ins_pipe(ialu_reg_fat); // XXX
5644 %}
5645
5646 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5647 %{
5648 match(Set dst src);
5649 effect(KILL cr);
5650
5651 ins_cost(50);
5652 format %{ "xorl $dst, $dst\t# int" %}
5653 opcode(0x33); /* + rd */
5654 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5655 ins_pipe(ialu_reg);
5656 %}
5657
5658 instruct loadConL(rRegL dst, immL src)
5659 %{
5660 match(Set dst src);
5661
5662 ins_cost(150);
5663 format %{ "movq $dst, $src\t# long" %}
5664 ins_encode(load_immL(dst, src));
5665 ins_pipe(ialu_reg);
5666 %}
5667
5668 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5669 %{
5670 match(Set dst src);
5671 effect(KILL cr);
5672
5673 ins_cost(50);
5674 format %{ "xorl $dst, $dst\t# long" %}
5675 opcode(0x33); /* + rd */
5676 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5677 ins_pipe(ialu_reg); // XXX
5678 %}
5679
5680 instruct loadConUL32(rRegL dst, immUL32 src)
5681 %{
5682 match(Set dst src);
5683
5684 ins_cost(60);
5685 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5686 ins_encode(load_immUL32(dst, src));
5687 ins_pipe(ialu_reg);
5688 %}
5689
5690 instruct loadConL32(rRegL dst, immL32 src)
5691 %{
5692 match(Set dst src);
5693
5694 ins_cost(70);
5695 format %{ "movq $dst, $src\t# long (32-bit)" %}
5696 ins_encode(load_immL32(dst, src));
5697 ins_pipe(ialu_reg);
5698 %}
5699
5700 instruct loadConP(rRegP dst, immP con) %{
5701 match(Set dst con);
5702
5703 format %{ "movq $dst, $con\t# ptr" %}
5704 ins_encode(load_immP(dst, con));
5705 ins_pipe(ialu_reg_fat); // XXX
5706 %}
5707
5708 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5709 %{
5710 match(Set dst src);
5711 effect(KILL cr);
5712
5713 ins_cost(50);
5714 format %{ "xorl $dst, $dst\t# ptr" %}
5715 opcode(0x33); /* + rd */
5716 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5717 ins_pipe(ialu_reg);
5718 %}
5719
5720 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5721 %{
5722 match(Set dst src);
5723 effect(KILL cr);
5724
5725 ins_cost(60);
5726 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5727 ins_encode(load_immP31(dst, src));
5728 ins_pipe(ialu_reg);
5729 %}
5730
5731 instruct loadConF(regF dst, immF con) %{
5732 match(Set dst con);
5733 ins_cost(125);
5734 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5735 ins_encode %{
5736 __ movflt($dst$$XMMRegister, $constantaddress($con));
5737 %}
5738 ins_pipe(pipe_slow);
5739 %}
5740
5741 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5742 match(Set dst src);
5743 effect(KILL cr);
5744 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5745 ins_encode %{
5746 __ xorq($dst$$Register, $dst$$Register);
5747 %}
5748 ins_pipe(ialu_reg);
5749 %}
5750
5751 instruct loadConN(rRegN dst, immN src) %{
5752 match(Set dst src);
5753
5754 ins_cost(125);
5755 format %{ "movl $dst, $src\t# compressed ptr" %}
5756 ins_encode %{
5757 address con = (address)$src$$constant;
5758 if (con == NULL) {
5759 ShouldNotReachHere();
5760 } else {
5761 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5762 }
5763 %}
5764 ins_pipe(ialu_reg_fat); // XXX
5765 %}
5766
5767 instruct loadConF0(regF dst, immF0 src)
5768 %{
5769 match(Set dst src);
5770 ins_cost(100);
5771
5772 format %{ "xorps $dst, $dst\t# float 0.0" %}
5773 ins_encode %{
5774 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5775 %}
5776 ins_pipe(pipe_slow);
5777 %}
5778
5779 // Use the same format since predicate() can not be used here.
5780 instruct loadConD(regD dst, immD con) %{
5781 match(Set dst con);
5782 ins_cost(125);
5783 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5784 ins_encode %{
5785 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5786 %}
5787 ins_pipe(pipe_slow);
5788 %}
5789
5790 instruct loadConD0(regD dst, immD0 src)
5791 %{
5792 match(Set dst src);
5793 ins_cost(100);
5794
5795 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5796 ins_encode %{
5797 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5798 %}
5799 ins_pipe(pipe_slow);
5800 %}
5801
5802 instruct loadSSI(rRegI dst, stackSlotI src)
5803 %{
5804 match(Set dst src);
5805
5806 ins_cost(125);
5807 format %{ "movl $dst, $src\t# int stk" %}
5808 opcode(0x8B);
5809 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5810 ins_pipe(ialu_reg_mem);
5811 %}
5812
5813 instruct loadSSL(rRegL dst, stackSlotL src)
5814 %{
5815 match(Set dst src);
5816
5817 ins_cost(125);
5818 format %{ "movq $dst, $src\t# long stk" %}
5819 opcode(0x8B);
5820 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5821 ins_pipe(ialu_reg_mem);
5822 %}
5823
5824 instruct loadSSP(rRegP dst, stackSlotP src)
5825 %{
5826 match(Set dst src);
5827
5828 ins_cost(125);
5829 format %{ "movq $dst, $src\t# ptr stk" %}
5830 opcode(0x8B);
5831 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5832 ins_pipe(ialu_reg_mem);
5833 %}
5834
5835 instruct loadSSF(regF dst, stackSlotF src)
5836 %{
5837 match(Set dst src);
5838
5839 ins_cost(125);
5840 format %{ "movss $dst, $src\t# float stk" %}
5841 ins_encode %{
5842 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5843 %}
5844 ins_pipe(pipe_slow); // XXX
5845 %}
5846
5847 // Use the same format since predicate() can not be used here.
5848 instruct loadSSD(regD dst, stackSlotD src)
5849 %{
5850 match(Set dst src);
5851
5852 ins_cost(125);
5853 format %{ "movsd $dst, $src\t# double stk" %}
5854 ins_encode %{
5855 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5856 %}
5857 ins_pipe(pipe_slow); // XXX
5858 %}
5859
5860 // Prefetch instructions.
5861 // Must be safe to execute with invalid address (cannot fault).
5862
5863 instruct prefetchr( memory mem ) %{
5864 predicate(ReadPrefetchInstr==3);
5865 match(PrefetchRead mem);
5866 ins_cost(125);
5867
5868 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5869 ins_encode %{
5870 __ prefetchr($mem$$Address);
5871 %}
5872 ins_pipe(ialu_mem);
5873 %}
5874
5875 instruct prefetchrNTA( memory mem ) %{
5876 predicate(ReadPrefetchInstr==0);
5877 match(PrefetchRead mem);
5878 ins_cost(125);
5879
5880 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5881 ins_encode %{
5882 __ prefetchnta($mem$$Address);
5883 %}
5884 ins_pipe(ialu_mem);
5885 %}
5886
5887 instruct prefetchrT0( memory mem ) %{
5888 predicate(ReadPrefetchInstr==1);
5889 match(PrefetchRead mem);
5890 ins_cost(125);
5891
5892 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5893 ins_encode %{
5894 __ prefetcht0($mem$$Address);
5895 %}
5896 ins_pipe(ialu_mem);
5897 %}
5898
5899 instruct prefetchrT2( memory mem ) %{
5900 predicate(ReadPrefetchInstr==2);
5901 match(PrefetchRead mem);
5902 ins_cost(125);
5903
5904 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5905 ins_encode %{
5906 __ prefetcht2($mem$$Address);
5907 %}
5908 ins_pipe(ialu_mem);
5909 %}
5910
5911 instruct prefetchwNTA( memory mem ) %{
5912 match(PrefetchWrite mem);
5913 ins_cost(125);
5914
5915 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5916 ins_encode %{
5917 __ prefetchnta($mem$$Address);
5918 %}
5919 ins_pipe(ialu_mem);
5920 %}
5921
5922 // Prefetch instructions for allocation.
5923
5924 instruct prefetchAlloc( memory mem ) %{
5925 predicate(AllocatePrefetchInstr==3);
5926 match(PrefetchAllocation mem);
5927 ins_cost(125);
5928
5929 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5930 ins_encode %{
5931 __ prefetchw($mem$$Address);
5932 %}
5933 ins_pipe(ialu_mem);
5934 %}
5935
5936 instruct prefetchAllocNTA( memory mem ) %{
5937 predicate(AllocatePrefetchInstr==0);
5938 match(PrefetchAllocation mem);
5939 ins_cost(125);
5940
5941 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5942 ins_encode %{
5943 __ prefetchnta($mem$$Address);
5944 %}
5945 ins_pipe(ialu_mem);
5946 %}
5947
5948 instruct prefetchAllocT0( memory mem ) %{
5949 predicate(AllocatePrefetchInstr==1);
5950 match(PrefetchAllocation mem);
5951 ins_cost(125);
5952
5953 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5954 ins_encode %{
5955 __ prefetcht0($mem$$Address);
5956 %}
5957 ins_pipe(ialu_mem);
5958 %}
5959
5960 instruct prefetchAllocT2( memory mem ) %{
5961 predicate(AllocatePrefetchInstr==2);
5962 match(PrefetchAllocation mem);
5963 ins_cost(125);
5964
5965 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5966 ins_encode %{
5967 __ prefetcht2($mem$$Address);
5968 %}
5969 ins_pipe(ialu_mem);
5970 %}
5971
5972 //----------Store Instructions-------------------------------------------------
5973
5974 // Store Byte
5975 instruct storeB(memory mem, rRegI src)
5976 %{
5977 match(Set mem (StoreB mem src));
5978
5979 ins_cost(125); // XXX
5980 format %{ "movb $mem, $src\t# byte" %}
5981 opcode(0x88);
5982 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5983 ins_pipe(ialu_mem_reg);
5984 %}
5985
5986 // Store Char/Short
5987 instruct storeC(memory mem, rRegI src)
5988 %{
5989 match(Set mem (StoreC mem src));
5990
5991 ins_cost(125); // XXX
5992 format %{ "movw $mem, $src\t# char/short" %}
5993 opcode(0x89);
5994 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5995 ins_pipe(ialu_mem_reg);
5996 %}
5997
5998 // Store Integer
5999 instruct storeI(memory mem, rRegI src)
6000 %{
6001 match(Set mem (StoreI mem src));
6002
6003 ins_cost(125); // XXX
6004 format %{ "movl $mem, $src\t# int" %}
6005 opcode(0x89);
6006 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6007 ins_pipe(ialu_mem_reg);
6008 %}
6009
6010 // Store Long
6011 instruct storeL(memory mem, rRegL src)
6012 %{
6013 match(Set mem (StoreL mem src));
6014
6015 ins_cost(125); // XXX
6016 format %{ "movq $mem, $src\t# long" %}
6017 opcode(0x89);
6018 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6019 ins_pipe(ialu_mem_reg); // XXX
6020 %}
6021
6022 // Store Pointer
6023 instruct storeP(memory mem, any_RegP src)
6024 %{
6025 match(Set mem (StoreP mem src));
6026
6027 ins_cost(125); // XXX
6028 format %{ "movq $mem, $src\t# ptr" %}
6029 opcode(0x89);
6030 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6031 ins_pipe(ialu_mem_reg);
6032 %}
6033
6034 instruct storeImmP0(memory mem, immP0 zero)
6035 %{
6036 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6037 match(Set mem (StoreP mem zero));
6038
6039 ins_cost(125); // XXX
6040 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6041 ins_encode %{
6042 __ movq($mem$$Address, r12);
6043 %}
6044 ins_pipe(ialu_mem_reg);
6045 %}
6046
6047 // Store NULL Pointer, mark word, or other simple pointer constant.
6048 instruct storeImmP(memory mem, immP31 src)
6049 %{
6050 match(Set mem (StoreP mem src));
6051
6052 ins_cost(150); // XXX
6053 format %{ "movq $mem, $src\t# ptr" %}
6054 opcode(0xC7); /* C7 /0 */
6055 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6056 ins_pipe(ialu_mem_imm);
6057 %}
6058
6059 // Store Compressed Pointer
6060 instruct storeN(memory mem, rRegN src)
6061 %{
6062 match(Set mem (StoreN mem src));
6063
6064 ins_cost(125); // XXX
6065 format %{ "movl $mem, $src\t# compressed ptr" %}
6066 ins_encode %{
6067 __ movl($mem$$Address, $src$$Register);
6068 %}
6069 ins_pipe(ialu_mem_reg);
6070 %}
6071
6072 instruct storeImmN0(memory mem, immN0 zero)
6073 %{
6074 predicate(Universe::narrow_oop_base() == NULL);
6075 match(Set mem (StoreN mem zero));
6076
6077 ins_cost(125); // XXX
6078 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6079 ins_encode %{
6080 __ movl($mem$$Address, r12);
6081 %}
6082 ins_pipe(ialu_mem_reg);
6083 %}
6084
6085 instruct storeImmN(memory mem, immN src)
6086 %{
6087 match(Set mem (StoreN mem src));
6088
6089 ins_cost(150); // XXX
6090 format %{ "movl $mem, $src\t# compressed ptr" %}
6091 ins_encode %{
6092 address con = (address)$src$$constant;
6093 if (con == NULL) {
6094 __ movl($mem$$Address, (int32_t)0);
6095 } else {
6096 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6097 }
6098 %}
6099 ins_pipe(ialu_mem_imm);
6100 %}
6101
6102 // Store Integer Immediate
6103 instruct storeImmI0(memory mem, immI0 zero)
6104 %{
6105 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6106 match(Set mem (StoreI mem zero));
6107
6108 ins_cost(125); // XXX
6109 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6110 ins_encode %{
6111 __ movl($mem$$Address, r12);
6112 %}
6113 ins_pipe(ialu_mem_reg);
6114 %}
6115
6116 instruct storeImmI(memory mem, immI src)
6117 %{
6118 match(Set mem (StoreI mem src));
6119
6120 ins_cost(150);
6121 format %{ "movl $mem, $src\t# int" %}
6122 opcode(0xC7); /* C7 /0 */
6123 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6124 ins_pipe(ialu_mem_imm);
6125 %}
6126
6127 // Store Long Immediate
6128 instruct storeImmL0(memory mem, immL0 zero)
6129 %{
6130 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6131 match(Set mem (StoreL mem zero));
6132
6133 ins_cost(125); // XXX
6134 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6135 ins_encode %{
6136 __ movq($mem$$Address, r12);
6137 %}
6138 ins_pipe(ialu_mem_reg);
6139 %}
6140
6141 instruct storeImmL(memory mem, immL32 src)
6142 %{
6143 match(Set mem (StoreL mem src));
6144
6145 ins_cost(150);
6146 format %{ "movq $mem, $src\t# long" %}
6147 opcode(0xC7); /* C7 /0 */
6148 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6149 ins_pipe(ialu_mem_imm);
6150 %}
6151
6152 // Store Short/Char Immediate
6153 instruct storeImmC0(memory mem, immI0 zero)
6154 %{
6155 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6156 match(Set mem (StoreC mem zero));
6157
6158 ins_cost(125); // XXX
6159 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6160 ins_encode %{
6161 __ movw($mem$$Address, r12);
6162 %}
6163 ins_pipe(ialu_mem_reg);
6164 %}
6165
6166 instruct storeImmI16(memory mem, immI16 src)
6167 %{
6168 predicate(UseStoreImmI16);
6169 match(Set mem (StoreC mem src));
6170
6171 ins_cost(150);
6172 format %{ "movw $mem, $src\t# short/char" %}
6173 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6174 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6175 ins_pipe(ialu_mem_imm);
6176 %}
6177
6178 // Store Byte Immediate
6179 instruct storeImmB0(memory mem, immI0 zero)
6180 %{
6181 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6182 match(Set mem (StoreB mem zero));
6183
6184 ins_cost(125); // XXX
6185 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6186 ins_encode %{
6187 __ movb($mem$$Address, r12);
6188 %}
6189 ins_pipe(ialu_mem_reg);
6190 %}
6191
6192 instruct storeImmB(memory mem, immI8 src)
6193 %{
6194 match(Set mem (StoreB mem src));
6195
6196 ins_cost(150); // XXX
6197 format %{ "movb $mem, $src\t# byte" %}
6198 opcode(0xC6); /* C6 /0 */
6199 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6200 ins_pipe(ialu_mem_imm);
6201 %}
6202
6203 // Store Aligned Packed Byte XMM register to memory
6204 instruct storeA8B(memory mem, regD src) %{
6205 match(Set mem (Store8B mem src));
6206 ins_cost(145);
6207 format %{ "MOVQ $mem,$src\t! packed8B" %}
6208 ins_encode %{
6209 __ movq($mem$$Address, $src$$XMMRegister);
6210 %}
6211 ins_pipe( pipe_slow );
6212 %}
6213
6214 // Store Aligned Packed Char/Short XMM register to memory
6215 instruct storeA4C(memory mem, regD src) %{
6216 match(Set mem (Store4C mem src));
6217 ins_cost(145);
6218 format %{ "MOVQ $mem,$src\t! packed4C" %}
6219 ins_encode %{
6220 __ movq($mem$$Address, $src$$XMMRegister);
6221 %}
6222 ins_pipe( pipe_slow );
6223 %}
6224
6225 // Store Aligned Packed Integer XMM register to memory
6226 instruct storeA2I(memory mem, regD src) %{
6227 match(Set mem (Store2I mem src));
6228 ins_cost(145);
6229 format %{ "MOVQ $mem,$src\t! packed2I" %}
6230 ins_encode %{
6231 __ movq($mem$$Address, $src$$XMMRegister);
6232 %}
6233 ins_pipe( pipe_slow );
6234 %}
6235
6236 // Store CMS card-mark Immediate
6237 instruct storeImmCM0_reg(memory mem, immI0 zero)
6238 %{
6239 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6240 match(Set mem (StoreCM mem zero));
6241
6242 ins_cost(125); // XXX
6243 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6244 ins_encode %{
6245 __ movb($mem$$Address, r12);
6246 %}
6247 ins_pipe(ialu_mem_reg);
6248 %}
6249
6250 instruct storeImmCM0(memory mem, immI0 src)
6251 %{
6252 match(Set mem (StoreCM mem src));
6253
6254 ins_cost(150); // XXX
6255 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6256 opcode(0xC6); /* C6 /0 */
6257 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6258 ins_pipe(ialu_mem_imm);
6259 %}
6260
6261 // Store Aligned Packed Single Float XMM register to memory
6262 instruct storeA2F(memory mem, regD src) %{
6263 match(Set mem (Store2F mem src));
6264 ins_cost(145);
6265 format %{ "MOVQ $mem,$src\t! packed2F" %}
6266 ins_encode %{
6267 __ movq($mem$$Address, $src$$XMMRegister);
6268 %}
6269 ins_pipe( pipe_slow );
6270 %}
6271
6272 // Store Float
6273 instruct storeF(memory mem, regF src)
6274 %{
6275 match(Set mem (StoreF mem src));
6276
6277 ins_cost(95); // XXX
6278 format %{ "movss $mem, $src\t# float" %}
6279 ins_encode %{
6280 __ movflt($mem$$Address, $src$$XMMRegister);
6281 %}
6282 ins_pipe(pipe_slow); // XXX
6283 %}
6284
6285 // Store immediate Float value (it is faster than store from XMM register)
6286 instruct storeF0(memory mem, immF0 zero)
6287 %{
6288 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6289 match(Set mem (StoreF mem zero));
6290
6291 ins_cost(25); // XXX
6292 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6293 ins_encode %{
6294 __ movl($mem$$Address, r12);
6295 %}
6296 ins_pipe(ialu_mem_reg);
6297 %}
6298
6299 instruct storeF_imm(memory mem, immF src)
6300 %{
6301 match(Set mem (StoreF mem src));
6302
6303 ins_cost(50);
6304 format %{ "movl $mem, $src\t# float" %}
6305 opcode(0xC7); /* C7 /0 */
6306 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6307 ins_pipe(ialu_mem_imm);
6308 %}
6309
6310 // Store Double
6311 instruct storeD(memory mem, regD src)
6312 %{
6313 match(Set mem (StoreD mem src));
6314
6315 ins_cost(95); // XXX
6316 format %{ "movsd $mem, $src\t# double" %}
6317 ins_encode %{
6318 __ movdbl($mem$$Address, $src$$XMMRegister);
6319 %}
6320 ins_pipe(pipe_slow); // XXX
6321 %}
6322
6323 // Store immediate double 0.0 (it is faster than store from XMM register)
6324 instruct storeD0_imm(memory mem, immD0 src)
6325 %{
6326 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6327 match(Set mem (StoreD mem src));
6328
6329 ins_cost(50);
6330 format %{ "movq $mem, $src\t# double 0." %}
6331 opcode(0xC7); /* C7 /0 */
6332 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6333 ins_pipe(ialu_mem_imm);
6334 %}
6335
6336 instruct storeD0(memory mem, immD0 zero)
6337 %{
6338 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6339 match(Set mem (StoreD mem zero));
6340
6341 ins_cost(25); // XXX
6342 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6343 ins_encode %{
6344 __ movq($mem$$Address, r12);
6345 %}
6346 ins_pipe(ialu_mem_reg);
6347 %}
6348
6349 instruct storeSSI(stackSlotI dst, rRegI src)
6350 %{
6351 match(Set dst src);
6352
6353 ins_cost(100);
6354 format %{ "movl $dst, $src\t# int stk" %}
6355 opcode(0x89);
6356 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6357 ins_pipe( ialu_mem_reg );
6358 %}
6359
6360 instruct storeSSL(stackSlotL dst, rRegL src)
6361 %{
6362 match(Set dst src);
6363
6364 ins_cost(100);
6365 format %{ "movq $dst, $src\t# long stk" %}
6366 opcode(0x89);
6367 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6368 ins_pipe(ialu_mem_reg);
6369 %}
6370
6371 instruct storeSSP(stackSlotP dst, rRegP src)
6372 %{
6373 match(Set dst src);
6374
6375 ins_cost(100);
6376 format %{ "movq $dst, $src\t# ptr stk" %}
6377 opcode(0x89);
6378 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6379 ins_pipe(ialu_mem_reg);
6380 %}
6381
6382 instruct storeSSF(stackSlotF dst, regF src)
6383 %{
6384 match(Set dst src);
6385
6386 ins_cost(95); // XXX
6387 format %{ "movss $dst, $src\t# float stk" %}
6388 ins_encode %{
6389 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6390 %}
6391 ins_pipe(pipe_slow); // XXX
6392 %}
6393
6394 instruct storeSSD(stackSlotD dst, regD src)
6395 %{
6396 match(Set dst src);
6397
6398 ins_cost(95); // XXX
6399 format %{ "movsd $dst, $src\t# double stk" %}
6400 ins_encode %{
6401 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6402 %}
6403 ins_pipe(pipe_slow); // XXX
6404 %}
6405
6406 //----------BSWAP Instructions-------------------------------------------------
6407 instruct bytes_reverse_int(rRegI dst) %{
6408 match(Set dst (ReverseBytesI dst));
6409
6410 format %{ "bswapl $dst" %}
6411 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6412 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6413 ins_pipe( ialu_reg );
6414 %}
6415
6416 instruct bytes_reverse_long(rRegL dst) %{
6417 match(Set dst (ReverseBytesL dst));
6418
6419 format %{ "bswapq $dst" %}
6420 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6421 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6422 ins_pipe( ialu_reg);
6423 %}
6424
6425 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6426 match(Set dst (ReverseBytesUS dst));
6427 effect(KILL cr);
6428
6429 format %{ "bswapl $dst\n\t"
6430 "shrl $dst,16\n\t" %}
6431 ins_encode %{
6432 __ bswapl($dst$$Register);
6433 __ shrl($dst$$Register, 16);
6434 %}
6435 ins_pipe( ialu_reg );
6436 %}
6437
6438 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6439 match(Set dst (ReverseBytesS dst));
6440 effect(KILL cr);
6441
6442 format %{ "bswapl $dst\n\t"
6443 "sar $dst,16\n\t" %}
6444 ins_encode %{
6445 __ bswapl($dst$$Register);
6446 __ sarl($dst$$Register, 16);
6447 %}
6448 ins_pipe( ialu_reg );
6449 %}
6450
6451 //---------- Zeros Count Instructions ------------------------------------------
6452
6453 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6454 predicate(UseCountLeadingZerosInstruction);
6455 match(Set dst (CountLeadingZerosI src));
6456 effect(KILL cr);
6457
6458 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6459 ins_encode %{
6460 __ lzcntl($dst$$Register, $src$$Register);
6461 %}
6462 ins_pipe(ialu_reg);
6463 %}
6464
6465 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6466 predicate(!UseCountLeadingZerosInstruction);
6467 match(Set dst (CountLeadingZerosI src));
6468 effect(KILL cr);
6469
6470 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6471 "jnz skip\n\t"
6472 "movl $dst, -1\n"
6473 "skip:\n\t"
6474 "negl $dst\n\t"
6475 "addl $dst, 31" %}
6476 ins_encode %{
6477 Register Rdst = $dst$$Register;
6478 Register Rsrc = $src$$Register;
6479 Label skip;
6480 __ bsrl(Rdst, Rsrc);
6481 __ jccb(Assembler::notZero, skip);
6482 __ movl(Rdst, -1);
6483 __ bind(skip);
6484 __ negl(Rdst);
6485 __ addl(Rdst, BitsPerInt - 1);
6486 %}
6487 ins_pipe(ialu_reg);
6488 %}
6489
6490 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6491 predicate(UseCountLeadingZerosInstruction);
6492 match(Set dst (CountLeadingZerosL src));
6493 effect(KILL cr);
6494
6495 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6496 ins_encode %{
6497 __ lzcntq($dst$$Register, $src$$Register);
6498 %}
6499 ins_pipe(ialu_reg);
6500 %}
6501
6502 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6503 predicate(!UseCountLeadingZerosInstruction);
6504 match(Set dst (CountLeadingZerosL src));
6505 effect(KILL cr);
6506
6507 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6508 "jnz skip\n\t"
6509 "movl $dst, -1\n"
6510 "skip:\n\t"
6511 "negl $dst\n\t"
6512 "addl $dst, 63" %}
6513 ins_encode %{
6514 Register Rdst = $dst$$Register;
6515 Register Rsrc = $src$$Register;
6516 Label skip;
6517 __ bsrq(Rdst, Rsrc);
6518 __ jccb(Assembler::notZero, skip);
6519 __ movl(Rdst, -1);
6520 __ bind(skip);
6521 __ negl(Rdst);
6522 __ addl(Rdst, BitsPerLong - 1);
6523 %}
6524 ins_pipe(ialu_reg);
6525 %}
6526
6527 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6528 match(Set dst (CountTrailingZerosI src));
6529 effect(KILL cr);
6530
6531 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6532 "jnz done\n\t"
6533 "movl $dst, 32\n"
6534 "done:" %}
6535 ins_encode %{
6536 Register Rdst = $dst$$Register;
6537 Label done;
6538 __ bsfl(Rdst, $src$$Register);
6539 __ jccb(Assembler::notZero, done);
6540 __ movl(Rdst, BitsPerInt);
6541 __ bind(done);
6542 %}
6543 ins_pipe(ialu_reg);
6544 %}
6545
6546 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6547 match(Set dst (CountTrailingZerosL src));
6548 effect(KILL cr);
6549
6550 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6551 "jnz done\n\t"
6552 "movl $dst, 64\n"
6553 "done:" %}
6554 ins_encode %{
6555 Register Rdst = $dst$$Register;
6556 Label done;
6557 __ bsfq(Rdst, $src$$Register);
6558 __ jccb(Assembler::notZero, done);
6559 __ movl(Rdst, BitsPerLong);
6560 __ bind(done);
6561 %}
6562 ins_pipe(ialu_reg);
6563 %}
6564
6565
6566 //---------- Population Count Instructions -------------------------------------
6567
6568 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6569 predicate(UsePopCountInstruction);
6570 match(Set dst (PopCountI src));
6571 effect(KILL cr);
6572
6573 format %{ "popcnt $dst, $src" %}
6574 ins_encode %{
6575 __ popcntl($dst$$Register, $src$$Register);
6576 %}
6577 ins_pipe(ialu_reg);
6578 %}
6579
6580 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6581 predicate(UsePopCountInstruction);
6582 match(Set dst (PopCountI (LoadI mem)));
6583 effect(KILL cr);
6584
6585 format %{ "popcnt $dst, $mem" %}
6586 ins_encode %{
6587 __ popcntl($dst$$Register, $mem$$Address);
6588 %}
6589 ins_pipe(ialu_reg);
6590 %}
6591
6592 // Note: Long.bitCount(long) returns an int.
6593 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6594 predicate(UsePopCountInstruction);
6595 match(Set dst (PopCountL src));
6596 effect(KILL cr);
6597
6598 format %{ "popcnt $dst, $src" %}
6599 ins_encode %{
6600 __ popcntq($dst$$Register, $src$$Register);
6601 %}
6602 ins_pipe(ialu_reg);
6603 %}
6604
6605 // Note: Long.bitCount(long) returns an int.
6606 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6607 predicate(UsePopCountInstruction);
6608 match(Set dst (PopCountL (LoadL mem)));
6609 effect(KILL cr);
6610
6611 format %{ "popcnt $dst, $mem" %}
6612 ins_encode %{
6613 __ popcntq($dst$$Register, $mem$$Address);
6614 %}
6615 ins_pipe(ialu_reg);
6616 %}
6617
6618
6619 //----------MemBar Instructions-----------------------------------------------
6620 // Memory barrier flavors
6621
6622 instruct membar_acquire()
6623 %{
6624 match(MemBarAcquire);
6625 ins_cost(0);
6626
6627 size(0);
6628 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6629 ins_encode();
6630 ins_pipe(empty);
6631 %}
6632
6633 instruct membar_acquire_lock()
6634 %{
6635 match(MemBarAcquireLock);
6636 ins_cost(0);
6637
6638 size(0);
6639 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6640 ins_encode();
6641 ins_pipe(empty);
6642 %}
6643
6644 instruct membar_release()
6645 %{
6646 match(MemBarRelease);
6647 ins_cost(0);
6648
6649 size(0);
6650 format %{ "MEMBAR-release ! (empty encoding)" %}
6651 ins_encode();
6652 ins_pipe(empty);
6653 %}
6654
6655 instruct membar_release_lock()
6656 %{
6657 match(MemBarReleaseLock);
6658 ins_cost(0);
6659
6660 size(0);
6661 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6662 ins_encode();
6663 ins_pipe(empty);
6664 %}
6665
6666 instruct membar_volatile(rFlagsReg cr) %{
6667 match(MemBarVolatile);
6668 effect(KILL cr);
6669 ins_cost(400);
6670
6671 format %{
6672 $$template
6673 if (os::is_MP()) {
6674 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6675 } else {
6676 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6677 }
6678 %}
6679 ins_encode %{
6680 __ membar(Assembler::StoreLoad);
6681 %}
6682 ins_pipe(pipe_slow);
6683 %}
6684
6685 instruct unnecessary_membar_volatile()
6686 %{
6687 match(MemBarVolatile);
6688 predicate(Matcher::post_store_load_barrier(n));
6689 ins_cost(0);
6690
6691 size(0);
6692 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6693 ins_encode();
6694 ins_pipe(empty);
6695 %}
6696
6697 instruct membar_storestore() %{
6698 match(MemBarStoreStore);
6699 ins_cost(0);
6700
6701 size(0);
6702 format %{ "MEMBAR-storestore (empty encoding)" %}
6703 ins_encode( );
6704 ins_pipe(empty);
6705 %}
6706
6707 //----------Move Instructions--------------------------------------------------
6708
6709 instruct castX2P(rRegP dst, rRegL src)
6710 %{
6711 match(Set dst (CastX2P src));
6712
6713 format %{ "movq $dst, $src\t# long->ptr" %}
6714 ins_encode %{
6715 if ($dst$$reg != $src$$reg) {
6716 __ movptr($dst$$Register, $src$$Register);
6717 }
6718 %}
6719 ins_pipe(ialu_reg_reg); // XXX
6720 %}
6721
6722 instruct castP2X(rRegL dst, rRegP src)
6723 %{
6724 match(Set dst (CastP2X src));
6725
6726 format %{ "movq $dst, $src\t# ptr -> long" %}
6727 ins_encode %{
6728 if ($dst$$reg != $src$$reg) {
6729 __ movptr($dst$$Register, $src$$Register);
6730 }
6731 %}
6732 ins_pipe(ialu_reg_reg); // XXX
6733 %}
6734
6735
6736 // Convert oop pointer into compressed form
6737 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6738 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6739 match(Set dst (EncodeP src));
6740 effect(KILL cr);
6741 format %{ "encode_heap_oop $dst,$src" %}
6742 ins_encode %{
6743 Register s = $src$$Register;
6744 Register d = $dst$$Register;
6745 if (s != d) {
6746 __ movq(d, s);
6747 }
6748 __ encode_heap_oop(d);
6749 %}
6750 ins_pipe(ialu_reg_long);
6751 %}
6752
6753 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6754 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6755 match(Set dst (EncodeP src));
6756 effect(KILL cr);
6757 format %{ "encode_heap_oop_not_null $dst,$src" %}
6758 ins_encode %{
6759 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6760 %}
6761 ins_pipe(ialu_reg_long);
6762 %}
6763
6764 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6765 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6766 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6767 match(Set dst (DecodeN src));
6768 effect(KILL cr);
6769 format %{ "decode_heap_oop $dst,$src" %}
6770 ins_encode %{
6771 Register s = $src$$Register;
6772 Register d = $dst$$Register;
6773 if (s != d) {
6774 __ movq(d, s);
6775 }
6776 __ decode_heap_oop(d);
6777 %}
6778 ins_pipe(ialu_reg_long);
6779 %}
6780
6781 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6782 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6783 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6784 match(Set dst (DecodeN src));
6785 effect(KILL cr);
6786 format %{ "decode_heap_oop_not_null $dst,$src" %}
6787 ins_encode %{
6788 Register s = $src$$Register;
6789 Register d = $dst$$Register;
6790 if (s != d) {
6791 __ decode_heap_oop_not_null(d, s);
6792 } else {
6793 __ decode_heap_oop_not_null(d);
6794 }
6795 %}
6796 ins_pipe(ialu_reg_long);
6797 %}
6798
6799
6800 //----------Conditional Move---------------------------------------------------
6801 // Jump
6802 // dummy instruction for generating temp registers
6803 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6804 match(Jump (LShiftL switch_val shift));
6805 ins_cost(350);
6806 predicate(false);
6807 effect(TEMP dest);
6808
6809 format %{ "leaq $dest, [$constantaddress]\n\t"
6810 "jmp [$dest + $switch_val << $shift]\n\t" %}
6811 ins_encode %{
6812 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6813 // to do that and the compiler is using that register as one it can allocate.
6814 // So we build it all by hand.
6815 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6816 // ArrayAddress dispatch(table, index);
6817 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6818 __ lea($dest$$Register, $constantaddress);
6819 __ jmp(dispatch);
6820 %}
6821 ins_pipe(pipe_jmp);
6822 %}
6823
6824 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6825 match(Jump (AddL (LShiftL switch_val shift) offset));
6826 ins_cost(350);
6827 effect(TEMP dest);
6828
6829 format %{ "leaq $dest, [$constantaddress]\n\t"
6830 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6831 ins_encode %{
6832 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6833 // to do that and the compiler is using that register as one it can allocate.
6834 // So we build it all by hand.
6835 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6836 // ArrayAddress dispatch(table, index);
6837 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6838 __ lea($dest$$Register, $constantaddress);
6839 __ jmp(dispatch);
6840 %}
6841 ins_pipe(pipe_jmp);
6842 %}
6843
6844 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6845 match(Jump switch_val);
6846 ins_cost(350);
6847 effect(TEMP dest);
6848
6849 format %{ "leaq $dest, [$constantaddress]\n\t"
6850 "jmp [$dest + $switch_val]\n\t" %}
6851 ins_encode %{
6852 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6853 // to do that and the compiler is using that register as one it can allocate.
6854 // So we build it all by hand.
6855 // Address index(noreg, switch_reg, Address::times_1);
6856 // ArrayAddress dispatch(table, index);
6857 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6858 __ lea($dest$$Register, $constantaddress);
6859 __ jmp(dispatch);
6860 %}
6861 ins_pipe(pipe_jmp);
6862 %}
6863
6864 // Conditional move
6865 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6866 %{
6867 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6868
6869 ins_cost(200); // XXX
6870 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6871 opcode(0x0F, 0x40);
6872 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6873 ins_pipe(pipe_cmov_reg);
6874 %}
6875
6876 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6877 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6878
6879 ins_cost(200); // XXX
6880 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6881 opcode(0x0F, 0x40);
6882 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6883 ins_pipe(pipe_cmov_reg);
6884 %}
6885
6886 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6887 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6888 ins_cost(200);
6889 expand %{
6890 cmovI_regU(cop, cr, dst, src);
6891 %}
6892 %}
6893
6894 // Conditional move
6895 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6896 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6897
6898 ins_cost(250); // XXX
6899 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6900 opcode(0x0F, 0x40);
6901 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6902 ins_pipe(pipe_cmov_mem);
6903 %}
6904
6905 // Conditional move
6906 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6907 %{
6908 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6909
6910 ins_cost(250); // XXX
6911 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6912 opcode(0x0F, 0x40);
6913 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6914 ins_pipe(pipe_cmov_mem);
6915 %}
6916
6917 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6918 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6919 ins_cost(250);
6920 expand %{
6921 cmovI_memU(cop, cr, dst, src);
6922 %}
6923 %}
6924
6925 // Conditional move
6926 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6927 %{
6928 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6929
6930 ins_cost(200); // XXX
6931 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6932 opcode(0x0F, 0x40);
6933 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6934 ins_pipe(pipe_cmov_reg);
6935 %}
6936
6937 // Conditional move
6938 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6939 %{
6940 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6941
6942 ins_cost(200); // XXX
6943 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6944 opcode(0x0F, 0x40);
6945 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6946 ins_pipe(pipe_cmov_reg);
6947 %}
6948
6949 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6950 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6951 ins_cost(200);
6952 expand %{
6953 cmovN_regU(cop, cr, dst, src);
6954 %}
6955 %}
6956
6957 // Conditional move
6958 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6959 %{
6960 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6961
6962 ins_cost(200); // XXX
6963 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6964 opcode(0x0F, 0x40);
6965 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6966 ins_pipe(pipe_cmov_reg); // XXX
6967 %}
6968
6969 // Conditional move
6970 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6971 %{
6972 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6973
6974 ins_cost(200); // XXX
6975 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6976 opcode(0x0F, 0x40);
6977 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6978 ins_pipe(pipe_cmov_reg); // XXX
6979 %}
6980
6981 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6982 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6983 ins_cost(200);
6984 expand %{
6985 cmovP_regU(cop, cr, dst, src);
6986 %}
6987 %}
6988
6989 // DISABLED: Requires the ADLC to emit a bottom_type call that
6990 // correctly meets the two pointer arguments; one is an incoming
6991 // register but the other is a memory operand. ALSO appears to
6992 // be buggy with implicit null checks.
6993 //
6994 //// Conditional move
6995 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6996 //%{
6997 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6998 // ins_cost(250);
6999 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7000 // opcode(0x0F,0x40);
7001 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7002 // ins_pipe( pipe_cmov_mem );
7003 //%}
7004 //
7005 //// Conditional move
7006 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7007 //%{
7008 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7009 // ins_cost(250);
7010 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7011 // opcode(0x0F,0x40);
7012 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7013 // ins_pipe( pipe_cmov_mem );
7014 //%}
7015
7016 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7017 %{
7018 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7019
7020 ins_cost(200); // XXX
7021 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7022 opcode(0x0F, 0x40);
7023 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7024 ins_pipe(pipe_cmov_reg); // XXX
7025 %}
7026
7027 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7028 %{
7029 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7030
7031 ins_cost(200); // XXX
7032 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7033 opcode(0x0F, 0x40);
7034 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7035 ins_pipe(pipe_cmov_mem); // XXX
7036 %}
7037
7038 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7039 %{
7040 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7041
7042 ins_cost(200); // XXX
7043 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7044 opcode(0x0F, 0x40);
7045 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7046 ins_pipe(pipe_cmov_reg); // XXX
7047 %}
7048
7049 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7050 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7051 ins_cost(200);
7052 expand %{
7053 cmovL_regU(cop, cr, dst, src);
7054 %}
7055 %}
7056
7057 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7058 %{
7059 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7060
7061 ins_cost(200); // XXX
7062 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7063 opcode(0x0F, 0x40);
7064 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7065 ins_pipe(pipe_cmov_mem); // XXX
7066 %}
7067
7068 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7069 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7070 ins_cost(200);
7071 expand %{
7072 cmovL_memU(cop, cr, dst, src);
7073 %}
7074 %}
7075
7076 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7077 %{
7078 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7079
7080 ins_cost(200); // XXX
7081 format %{ "jn$cop skip\t# signed cmove float\n\t"
7082 "movss $dst, $src\n"
7083 "skip:" %}
7084 ins_encode %{
7085 Label Lskip;
7086 // Invert sense of branch from sense of CMOV
7087 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7088 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7089 __ bind(Lskip);
7090 %}
7091 ins_pipe(pipe_slow);
7092 %}
7093
7094 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7095 // %{
7096 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7097
7098 // ins_cost(200); // XXX
7099 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7100 // "movss $dst, $src\n"
7101 // "skip:" %}
7102 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7103 // ins_pipe(pipe_slow);
7104 // %}
7105
7106 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7107 %{
7108 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7109
7110 ins_cost(200); // XXX
7111 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7112 "movss $dst, $src\n"
7113 "skip:" %}
7114 ins_encode %{
7115 Label Lskip;
7116 // Invert sense of branch from sense of CMOV
7117 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7118 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7119 __ bind(Lskip);
7120 %}
7121 ins_pipe(pipe_slow);
7122 %}
7123
7124 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7125 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7126 ins_cost(200);
7127 expand %{
7128 cmovF_regU(cop, cr, dst, src);
7129 %}
7130 %}
7131
7132 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7133 %{
7134 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7135
7136 ins_cost(200); // XXX
7137 format %{ "jn$cop skip\t# signed cmove double\n\t"
7138 "movsd $dst, $src\n"
7139 "skip:" %}
7140 ins_encode %{
7141 Label Lskip;
7142 // Invert sense of branch from sense of CMOV
7143 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7144 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7145 __ bind(Lskip);
7146 %}
7147 ins_pipe(pipe_slow);
7148 %}
7149
7150 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7151 %{
7152 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7153
7154 ins_cost(200); // XXX
7155 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7156 "movsd $dst, $src\n"
7157 "skip:" %}
7158 ins_encode %{
7159 Label Lskip;
7160 // Invert sense of branch from sense of CMOV
7161 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7162 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7163 __ bind(Lskip);
7164 %}
7165 ins_pipe(pipe_slow);
7166 %}
7167
7168 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7169 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7170 ins_cost(200);
7171 expand %{
7172 cmovD_regU(cop, cr, dst, src);
7173 %}
7174 %}
7175
7176 //----------Arithmetic Instructions--------------------------------------------
7177 //----------Addition Instructions----------------------------------------------
7178
7179 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7180 %{
7181 match(Set dst (AddI dst src));
7182 effect(KILL cr);
7183
7184 format %{ "addl $dst, $src\t# int" %}
7185 opcode(0x03);
7186 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7187 ins_pipe(ialu_reg_reg);
7188 %}
7189
7190 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7191 %{
7192 match(Set dst (AddI dst src));
7193 effect(KILL cr);
7194
7195 format %{ "addl $dst, $src\t# int" %}
7196 opcode(0x81, 0x00); /* /0 id */
7197 ins_encode(OpcSErm(dst, src), Con8or32(src));
7198 ins_pipe( ialu_reg );
7199 %}
7200
7201 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7202 %{
7203 match(Set dst (AddI dst (LoadI src)));
7204 effect(KILL cr);
7205
7206 ins_cost(125); // XXX
7207 format %{ "addl $dst, $src\t# int" %}
7208 opcode(0x03);
7209 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7210 ins_pipe(ialu_reg_mem);
7211 %}
7212
7213 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7214 %{
7215 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7216 effect(KILL cr);
7217
7218 ins_cost(150); // XXX
7219 format %{ "addl $dst, $src\t# int" %}
7220 opcode(0x01); /* Opcode 01 /r */
7221 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7222 ins_pipe(ialu_mem_reg);
7223 %}
7224
7225 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7226 %{
7227 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7228 effect(KILL cr);
7229
7230 ins_cost(125); // XXX
7231 format %{ "addl $dst, $src\t# int" %}
7232 opcode(0x81); /* Opcode 81 /0 id */
7233 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7234 ins_pipe(ialu_mem_imm);
7235 %}
7236
7237 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7238 %{
7239 predicate(UseIncDec);
7240 match(Set dst (AddI dst src));
7241 effect(KILL cr);
7242
7243 format %{ "incl $dst\t# int" %}
7244 opcode(0xFF, 0x00); // FF /0
7245 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7246 ins_pipe(ialu_reg);
7247 %}
7248
7249 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7250 %{
7251 predicate(UseIncDec);
7252 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7253 effect(KILL cr);
7254
7255 ins_cost(125); // XXX
7256 format %{ "incl $dst\t# int" %}
7257 opcode(0xFF); /* Opcode FF /0 */
7258 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7259 ins_pipe(ialu_mem_imm);
7260 %}
7261
7262 // XXX why does that use AddI
7263 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7264 %{
7265 predicate(UseIncDec);
7266 match(Set dst (AddI dst src));
7267 effect(KILL cr);
7268
7269 format %{ "decl $dst\t# int" %}
7270 opcode(0xFF, 0x01); // FF /1
7271 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7272 ins_pipe(ialu_reg);
7273 %}
7274
7275 // XXX why does that use AddI
7276 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7277 %{
7278 predicate(UseIncDec);
7279 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7280 effect(KILL cr);
7281
7282 ins_cost(125); // XXX
7283 format %{ "decl $dst\t# int" %}
7284 opcode(0xFF); /* Opcode FF /1 */
7285 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7286 ins_pipe(ialu_mem_imm);
7287 %}
7288
7289 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7290 %{
7291 match(Set dst (AddI src0 src1));
7292
7293 ins_cost(110);
7294 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7295 opcode(0x8D); /* 0x8D /r */
7296 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7297 ins_pipe(ialu_reg_reg);
7298 %}
7299
7300 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7301 %{
7302 match(Set dst (AddL dst src));
7303 effect(KILL cr);
7304
7305 format %{ "addq $dst, $src\t# long" %}
7306 opcode(0x03);
7307 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7308 ins_pipe(ialu_reg_reg);
7309 %}
7310
7311 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7312 %{
7313 match(Set dst (AddL dst src));
7314 effect(KILL cr);
7315
7316 format %{ "addq $dst, $src\t# long" %}
7317 opcode(0x81, 0x00); /* /0 id */
7318 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7319 ins_pipe( ialu_reg );
7320 %}
7321
7322 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7323 %{
7324 match(Set dst (AddL dst (LoadL src)));
7325 effect(KILL cr);
7326
7327 ins_cost(125); // XXX
7328 format %{ "addq $dst, $src\t# long" %}
7329 opcode(0x03);
7330 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7331 ins_pipe(ialu_reg_mem);
7332 %}
7333
7334 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7335 %{
7336 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7337 effect(KILL cr);
7338
7339 ins_cost(150); // XXX
7340 format %{ "addq $dst, $src\t# long" %}
7341 opcode(0x01); /* Opcode 01 /r */
7342 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7343 ins_pipe(ialu_mem_reg);
7344 %}
7345
7346 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7347 %{
7348 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7349 effect(KILL cr);
7350
7351 ins_cost(125); // XXX
7352 format %{ "addq $dst, $src\t# long" %}
7353 opcode(0x81); /* Opcode 81 /0 id */
7354 ins_encode(REX_mem_wide(dst),
7355 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7356 ins_pipe(ialu_mem_imm);
7357 %}
7358
7359 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7360 %{
7361 predicate(UseIncDec);
7362 match(Set dst (AddL dst src));
7363 effect(KILL cr);
7364
7365 format %{ "incq $dst\t# long" %}
7366 opcode(0xFF, 0x00); // FF /0
7367 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7368 ins_pipe(ialu_reg);
7369 %}
7370
7371 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7372 %{
7373 predicate(UseIncDec);
7374 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7375 effect(KILL cr);
7376
7377 ins_cost(125); // XXX
7378 format %{ "incq $dst\t# long" %}
7379 opcode(0xFF); /* Opcode FF /0 */
7380 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7381 ins_pipe(ialu_mem_imm);
7382 %}
7383
7384 // XXX why does that use AddL
7385 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7386 %{
7387 predicate(UseIncDec);
7388 match(Set dst (AddL dst src));
7389 effect(KILL cr);
7390
7391 format %{ "decq $dst\t# long" %}
7392 opcode(0xFF, 0x01); // FF /1
7393 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7394 ins_pipe(ialu_reg);
7395 %}
7396
7397 // XXX why does that use AddL
7398 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7399 %{
7400 predicate(UseIncDec);
7401 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7402 effect(KILL cr);
7403
7404 ins_cost(125); // XXX
7405 format %{ "decq $dst\t# long" %}
7406 opcode(0xFF); /* Opcode FF /1 */
7407 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7408 ins_pipe(ialu_mem_imm);
7409 %}
7410
7411 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7412 %{
7413 match(Set dst (AddL src0 src1));
7414
7415 ins_cost(110);
7416 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7417 opcode(0x8D); /* 0x8D /r */
7418 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7419 ins_pipe(ialu_reg_reg);
7420 %}
7421
7422 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7423 %{
7424 match(Set dst (AddP dst src));
7425 effect(KILL cr);
7426
7427 format %{ "addq $dst, $src\t# ptr" %}
7428 opcode(0x03);
7429 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7430 ins_pipe(ialu_reg_reg);
7431 %}
7432
7433 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7434 %{
7435 match(Set dst (AddP dst src));
7436 effect(KILL cr);
7437
7438 format %{ "addq $dst, $src\t# ptr" %}
7439 opcode(0x81, 0x00); /* /0 id */
7440 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7441 ins_pipe( ialu_reg );
7442 %}
7443
7444 // XXX addP mem ops ????
7445
7446 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7447 %{
7448 match(Set dst (AddP src0 src1));
7449
7450 ins_cost(110);
7451 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7452 opcode(0x8D); /* 0x8D /r */
7453 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7454 ins_pipe(ialu_reg_reg);
7455 %}
7456
7457 instruct checkCastPP(rRegP dst)
7458 %{
7459 match(Set dst (CheckCastPP dst));
7460
7461 size(0);
7462 format %{ "# checkcastPP of $dst" %}
7463 ins_encode(/* empty encoding */);
7464 ins_pipe(empty);
7465 %}
7466
7467 instruct castPP(rRegP dst)
7468 %{
7469 match(Set dst (CastPP dst));
7470
7471 size(0);
7472 format %{ "# castPP of $dst" %}
7473 ins_encode(/* empty encoding */);
7474 ins_pipe(empty);
7475 %}
7476
7477 instruct castII(rRegI dst)
7478 %{
7479 match(Set dst (CastII dst));
7480
7481 size(0);
7482 format %{ "# castII of $dst" %}
7483 ins_encode(/* empty encoding */);
7484 ins_cost(0);
7485 ins_pipe(empty);
7486 %}
7487
7488 // LoadP-locked same as a regular LoadP when used with compare-swap
7489 instruct loadPLocked(rRegP dst, memory mem)
7490 %{
7491 match(Set dst (LoadPLocked mem));
7492
7493 ins_cost(125); // XXX
7494 format %{ "movq $dst, $mem\t# ptr locked" %}
7495 opcode(0x8B);
7496 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7497 ins_pipe(ialu_reg_mem); // XXX
7498 %}
7499
7500 // LoadL-locked - same as a regular LoadL when used with compare-swap
7501 instruct loadLLocked(rRegL dst, memory mem)
7502 %{
7503 match(Set dst (LoadLLocked mem));
7504
7505 ins_cost(125); // XXX
7506 format %{ "movq $dst, $mem\t# long locked" %}
7507 opcode(0x8B);
7508 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7509 ins_pipe(ialu_reg_mem); // XXX
7510 %}
7511
7512 // Conditional-store of the updated heap-top.
7513 // Used during allocation of the shared heap.
7514 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7515
7516 instruct storePConditional(memory heap_top_ptr,
7517 rax_RegP oldval, rRegP newval,
7518 rFlagsReg cr)
7519 %{
7520 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7521
7522 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7523 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7524 opcode(0x0F, 0xB1);
7525 ins_encode(lock_prefix,
7526 REX_reg_mem_wide(newval, heap_top_ptr),
7527 OpcP, OpcS,
7528 reg_mem(newval, heap_top_ptr));
7529 ins_pipe(pipe_cmpxchg);
7530 %}
7531
7532 // Conditional-store of an int value.
7533 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7534 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7535 %{
7536 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7537 effect(KILL oldval);
7538
7539 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7540 opcode(0x0F, 0xB1);
7541 ins_encode(lock_prefix,
7542 REX_reg_mem(newval, mem),
7543 OpcP, OpcS,
7544 reg_mem(newval, mem));
7545 ins_pipe(pipe_cmpxchg);
7546 %}
7547
7548 // Conditional-store of a long value.
7549 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7550 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7551 %{
7552 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7553 effect(KILL oldval);
7554
7555 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7556 opcode(0x0F, 0xB1);
7557 ins_encode(lock_prefix,
7558 REX_reg_mem_wide(newval, mem),
7559 OpcP, OpcS,
7560 reg_mem(newval, mem));
7561 ins_pipe(pipe_cmpxchg);
7562 %}
7563
7564
7565 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7566 instruct compareAndSwapP(rRegI res,
7567 memory mem_ptr,
7568 rax_RegP oldval, rRegP newval,
7569 rFlagsReg cr)
7570 %{
7571 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7572 effect(KILL cr, KILL oldval);
7573
7574 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7575 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7576 "sete $res\n\t"
7577 "movzbl $res, $res" %}
7578 opcode(0x0F, 0xB1);
7579 ins_encode(lock_prefix,
7580 REX_reg_mem_wide(newval, mem_ptr),
7581 OpcP, OpcS,
7582 reg_mem(newval, mem_ptr),
7583 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7584 REX_reg_breg(res, res), // movzbl
7585 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7586 ins_pipe( pipe_cmpxchg );
7587 %}
7588
7589 instruct compareAndSwapL(rRegI res,
7590 memory mem_ptr,
7591 rax_RegL oldval, rRegL newval,
7592 rFlagsReg cr)
7593 %{
7594 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7595 effect(KILL cr, KILL oldval);
7596
7597 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7598 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7599 "sete $res\n\t"
7600 "movzbl $res, $res" %}
7601 opcode(0x0F, 0xB1);
7602 ins_encode(lock_prefix,
7603 REX_reg_mem_wide(newval, mem_ptr),
7604 OpcP, OpcS,
7605 reg_mem(newval, mem_ptr),
7606 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7607 REX_reg_breg(res, res), // movzbl
7608 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7609 ins_pipe( pipe_cmpxchg );
7610 %}
7611
7612 instruct compareAndSwapI(rRegI res,
7613 memory mem_ptr,
7614 rax_RegI oldval, rRegI newval,
7615 rFlagsReg cr)
7616 %{
7617 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7618 effect(KILL cr, KILL oldval);
7619
7620 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7621 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7622 "sete $res\n\t"
7623 "movzbl $res, $res" %}
7624 opcode(0x0F, 0xB1);
7625 ins_encode(lock_prefix,
7626 REX_reg_mem(newval, mem_ptr),
7627 OpcP, OpcS,
7628 reg_mem(newval, mem_ptr),
7629 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7630 REX_reg_breg(res, res), // movzbl
7631 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7632 ins_pipe( pipe_cmpxchg );
7633 %}
7634
7635
7636 instruct compareAndSwapN(rRegI res,
7637 memory mem_ptr,
7638 rax_RegN oldval, rRegN newval,
7639 rFlagsReg cr) %{
7640 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7641 effect(KILL cr, KILL oldval);
7642
7643 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7644 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7645 "sete $res\n\t"
7646 "movzbl $res, $res" %}
7647 opcode(0x0F, 0xB1);
7648 ins_encode(lock_prefix,
7649 REX_reg_mem(newval, mem_ptr),
7650 OpcP, OpcS,
7651 reg_mem(newval, mem_ptr),
7652 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7653 REX_reg_breg(res, res), // movzbl
7654 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7655 ins_pipe( pipe_cmpxchg );
7656 %}
7657
7658 //----------Subtraction Instructions-------------------------------------------
7659
7660 // Integer Subtraction Instructions
7661 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7662 %{
7663 match(Set dst (SubI dst src));
7664 effect(KILL cr);
7665
7666 format %{ "subl $dst, $src\t# int" %}
7667 opcode(0x2B);
7668 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7669 ins_pipe(ialu_reg_reg);
7670 %}
7671
7672 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7673 %{
7674 match(Set dst (SubI dst src));
7675 effect(KILL cr);
7676
7677 format %{ "subl $dst, $src\t# int" %}
7678 opcode(0x81, 0x05); /* Opcode 81 /5 */
7679 ins_encode(OpcSErm(dst, src), Con8or32(src));
7680 ins_pipe(ialu_reg);
7681 %}
7682
7683 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7684 %{
7685 match(Set dst (SubI dst (LoadI src)));
7686 effect(KILL cr);
7687
7688 ins_cost(125);
7689 format %{ "subl $dst, $src\t# int" %}
7690 opcode(0x2B);
7691 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7692 ins_pipe(ialu_reg_mem);
7693 %}
7694
7695 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7696 %{
7697 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7698 effect(KILL cr);
7699
7700 ins_cost(150);
7701 format %{ "subl $dst, $src\t# int" %}
7702 opcode(0x29); /* Opcode 29 /r */
7703 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7704 ins_pipe(ialu_mem_reg);
7705 %}
7706
7707 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7708 %{
7709 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7710 effect(KILL cr);
7711
7712 ins_cost(125); // XXX
7713 format %{ "subl $dst, $src\t# int" %}
7714 opcode(0x81); /* Opcode 81 /5 id */
7715 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7716 ins_pipe(ialu_mem_imm);
7717 %}
7718
7719 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7720 %{
7721 match(Set dst (SubL dst src));
7722 effect(KILL cr);
7723
7724 format %{ "subq $dst, $src\t# long" %}
7725 opcode(0x2B);
7726 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7727 ins_pipe(ialu_reg_reg);
7728 %}
7729
7730 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7731 %{
7732 match(Set dst (SubL dst src));
7733 effect(KILL cr);
7734
7735 format %{ "subq $dst, $src\t# long" %}
7736 opcode(0x81, 0x05); /* Opcode 81 /5 */
7737 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7738 ins_pipe(ialu_reg);
7739 %}
7740
7741 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7742 %{
7743 match(Set dst (SubL dst (LoadL src)));
7744 effect(KILL cr);
7745
7746 ins_cost(125);
7747 format %{ "subq $dst, $src\t# long" %}
7748 opcode(0x2B);
7749 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7750 ins_pipe(ialu_reg_mem);
7751 %}
7752
7753 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7754 %{
7755 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7756 effect(KILL cr);
7757
7758 ins_cost(150);
7759 format %{ "subq $dst, $src\t# long" %}
7760 opcode(0x29); /* Opcode 29 /r */
7761 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7762 ins_pipe(ialu_mem_reg);
7763 %}
7764
7765 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7766 %{
7767 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7768 effect(KILL cr);
7769
7770 ins_cost(125); // XXX
7771 format %{ "subq $dst, $src\t# long" %}
7772 opcode(0x81); /* Opcode 81 /5 id */
7773 ins_encode(REX_mem_wide(dst),
7774 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7775 ins_pipe(ialu_mem_imm);
7776 %}
7777
7778 // Subtract from a pointer
7779 // XXX hmpf???
7780 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7781 %{
7782 match(Set dst (AddP dst (SubI zero src)));
7783 effect(KILL cr);
7784
7785 format %{ "subq $dst, $src\t# ptr - int" %}
7786 opcode(0x2B);
7787 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7788 ins_pipe(ialu_reg_reg);
7789 %}
7790
7791 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7792 %{
7793 match(Set dst (SubI zero dst));
7794 effect(KILL cr);
7795
7796 format %{ "negl $dst\t# int" %}
7797 opcode(0xF7, 0x03); // Opcode F7 /3
7798 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7799 ins_pipe(ialu_reg);
7800 %}
7801
7802 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7803 %{
7804 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7805 effect(KILL cr);
7806
7807 format %{ "negl $dst\t# int" %}
7808 opcode(0xF7, 0x03); // Opcode F7 /3
7809 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7810 ins_pipe(ialu_reg);
7811 %}
7812
7813 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7814 %{
7815 match(Set dst (SubL zero dst));
7816 effect(KILL cr);
7817
7818 format %{ "negq $dst\t# long" %}
7819 opcode(0xF7, 0x03); // Opcode F7 /3
7820 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7821 ins_pipe(ialu_reg);
7822 %}
7823
7824 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7825 %{
7826 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7827 effect(KILL cr);
7828
7829 format %{ "negq $dst\t# long" %}
7830 opcode(0xF7, 0x03); // Opcode F7 /3
7831 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7832 ins_pipe(ialu_reg);
7833 %}
7834
7835
7836 //----------Multiplication/Division Instructions-------------------------------
7837 // Integer Multiplication Instructions
7838 // Multiply Register
7839
7840 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7841 %{
7842 match(Set dst (MulI dst src));
7843 effect(KILL cr);
7844
7845 ins_cost(300);
7846 format %{ "imull $dst, $src\t# int" %}
7847 opcode(0x0F, 0xAF);
7848 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7849 ins_pipe(ialu_reg_reg_alu0);
7850 %}
7851
7852 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7853 %{
7854 match(Set dst (MulI src imm));
7855 effect(KILL cr);
7856
7857 ins_cost(300);
7858 format %{ "imull $dst, $src, $imm\t# int" %}
7859 opcode(0x69); /* 69 /r id */
7860 ins_encode(REX_reg_reg(dst, src),
7861 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7862 ins_pipe(ialu_reg_reg_alu0);
7863 %}
7864
7865 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7866 %{
7867 match(Set dst (MulI dst (LoadI src)));
7868 effect(KILL cr);
7869
7870 ins_cost(350);
7871 format %{ "imull $dst, $src\t# int" %}
7872 opcode(0x0F, 0xAF);
7873 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7874 ins_pipe(ialu_reg_mem_alu0);
7875 %}
7876
7877 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7878 %{
7879 match(Set dst (MulI (LoadI src) imm));
7880 effect(KILL cr);
7881
7882 ins_cost(300);
7883 format %{ "imull $dst, $src, $imm\t# int" %}
7884 opcode(0x69); /* 69 /r id */
7885 ins_encode(REX_reg_mem(dst, src),
7886 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7887 ins_pipe(ialu_reg_mem_alu0);
7888 %}
7889
7890 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7891 %{
7892 match(Set dst (MulL dst src));
7893 effect(KILL cr);
7894
7895 ins_cost(300);
7896 format %{ "imulq $dst, $src\t# long" %}
7897 opcode(0x0F, 0xAF);
7898 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7899 ins_pipe(ialu_reg_reg_alu0);
7900 %}
7901
7902 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7903 %{
7904 match(Set dst (MulL src imm));
7905 effect(KILL cr);
7906
7907 ins_cost(300);
7908 format %{ "imulq $dst, $src, $imm\t# long" %}
7909 opcode(0x69); /* 69 /r id */
7910 ins_encode(REX_reg_reg_wide(dst, src),
7911 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7912 ins_pipe(ialu_reg_reg_alu0);
7913 %}
7914
7915 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7916 %{
7917 match(Set dst (MulL dst (LoadL src)));
7918 effect(KILL cr);
7919
7920 ins_cost(350);
7921 format %{ "imulq $dst, $src\t# long" %}
7922 opcode(0x0F, 0xAF);
7923 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7924 ins_pipe(ialu_reg_mem_alu0);
7925 %}
7926
7927 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7928 %{
7929 match(Set dst (MulL (LoadL src) imm));
7930 effect(KILL cr);
7931
7932 ins_cost(300);
7933 format %{ "imulq $dst, $src, $imm\t# long" %}
7934 opcode(0x69); /* 69 /r id */
7935 ins_encode(REX_reg_mem_wide(dst, src),
7936 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7937 ins_pipe(ialu_reg_mem_alu0);
7938 %}
7939
7940 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7941 %{
7942 match(Set dst (MulHiL src rax));
7943 effect(USE_KILL rax, KILL cr);
7944
7945 ins_cost(300);
7946 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7947 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7948 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7949 ins_pipe(ialu_reg_reg_alu0);
7950 %}
7951
7952 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7953 rFlagsReg cr)
7954 %{
7955 match(Set rax (DivI rax div));
7956 effect(KILL rdx, KILL cr);
7957
7958 ins_cost(30*100+10*100); // XXX
7959 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7960 "jne,s normal\n\t"
7961 "xorl rdx, rdx\n\t"
7962 "cmpl $div, -1\n\t"
7963 "je,s done\n"
7964 "normal: cdql\n\t"
7965 "idivl $div\n"
7966 "done:" %}
7967 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7968 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7969 ins_pipe(ialu_reg_reg_alu0);
7970 %}
7971
7972 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7973 rFlagsReg cr)
7974 %{
7975 match(Set rax (DivL rax div));
7976 effect(KILL rdx, KILL cr);
7977
7978 ins_cost(30*100+10*100); // XXX
7979 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7980 "cmpq rax, rdx\n\t"
7981 "jne,s normal\n\t"
7982 "xorl rdx, rdx\n\t"
7983 "cmpq $div, -1\n\t"
7984 "je,s done\n"
7985 "normal: cdqq\n\t"
7986 "idivq $div\n"
7987 "done:" %}
7988 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7989 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7990 ins_pipe(ialu_reg_reg_alu0);
7991 %}
7992
7993 // Integer DIVMOD with Register, both quotient and mod results
7994 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7995 rFlagsReg cr)
7996 %{
7997 match(DivModI rax div);
7998 effect(KILL cr);
7999
8000 ins_cost(30*100+10*100); // XXX
8001 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8002 "jne,s normal\n\t"
8003 "xorl rdx, rdx\n\t"
8004 "cmpl $div, -1\n\t"
8005 "je,s done\n"
8006 "normal: cdql\n\t"
8007 "idivl $div\n"
8008 "done:" %}
8009 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8010 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8011 ins_pipe(pipe_slow);
8012 %}
8013
8014 // Long DIVMOD with Register, both quotient and mod results
8015 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8016 rFlagsReg cr)
8017 %{
8018 match(DivModL rax div);
8019 effect(KILL cr);
8020
8021 ins_cost(30*100+10*100); // XXX
8022 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8023 "cmpq rax, rdx\n\t"
8024 "jne,s normal\n\t"
8025 "xorl rdx, rdx\n\t"
8026 "cmpq $div, -1\n\t"
8027 "je,s done\n"
8028 "normal: cdqq\n\t"
8029 "idivq $div\n"
8030 "done:" %}
8031 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8032 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8033 ins_pipe(pipe_slow);
8034 %}
8035
8036 //----------- DivL-By-Constant-Expansions--------------------------------------
8037 // DivI cases are handled by the compiler
8038
8039 // Magic constant, reciprocal of 10
8040 instruct loadConL_0x6666666666666667(rRegL dst)
8041 %{
8042 effect(DEF dst);
8043
8044 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8045 ins_encode(load_immL(dst, 0x6666666666666667));
8046 ins_pipe(ialu_reg);
8047 %}
8048
8049 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8050 %{
8051 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8052
8053 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8054 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8055 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8056 ins_pipe(ialu_reg_reg_alu0);
8057 %}
8058
8059 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8060 %{
8061 effect(USE_DEF dst, KILL cr);
8062
8063 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8064 opcode(0xC1, 0x7); /* C1 /7 ib */
8065 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8066 ins_pipe(ialu_reg);
8067 %}
8068
8069 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8070 %{
8071 effect(USE_DEF dst, KILL cr);
8072
8073 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8074 opcode(0xC1, 0x7); /* C1 /7 ib */
8075 ins_encode(reg_opc_imm_wide(dst, 0x2));
8076 ins_pipe(ialu_reg);
8077 %}
8078
8079 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8080 %{
8081 match(Set dst (DivL src div));
8082
8083 ins_cost((5+8)*100);
8084 expand %{
8085 rax_RegL rax; // Killed temp
8086 rFlagsReg cr; // Killed
8087 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8088 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8089 sarL_rReg_63(src, cr); // sarq src, 63
8090 sarL_rReg_2(dst, cr); // sarq rdx, 2
8091 subL_rReg(dst, src, cr); // subl rdx, src
8092 %}
8093 %}
8094
8095 //-----------------------------------------------------------------------------
8096
8097 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8098 rFlagsReg cr)
8099 %{
8100 match(Set rdx (ModI rax div));
8101 effect(KILL rax, KILL cr);
8102
8103 ins_cost(300); // XXX
8104 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8105 "jne,s normal\n\t"
8106 "xorl rdx, rdx\n\t"
8107 "cmpl $div, -1\n\t"
8108 "je,s done\n"
8109 "normal: cdql\n\t"
8110 "idivl $div\n"
8111 "done:" %}
8112 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8113 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8114 ins_pipe(ialu_reg_reg_alu0);
8115 %}
8116
8117 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8118 rFlagsReg cr)
8119 %{
8120 match(Set rdx (ModL rax div));
8121 effect(KILL rax, KILL cr);
8122
8123 ins_cost(300); // XXX
8124 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8125 "cmpq rax, rdx\n\t"
8126 "jne,s normal\n\t"
8127 "xorl rdx, rdx\n\t"
8128 "cmpq $div, -1\n\t"
8129 "je,s done\n"
8130 "normal: cdqq\n\t"
8131 "idivq $div\n"
8132 "done:" %}
8133 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8134 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8135 ins_pipe(ialu_reg_reg_alu0);
8136 %}
8137
8138 // Integer Shift Instructions
8139 // Shift Left by one
8140 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8141 %{
8142 match(Set dst (LShiftI dst shift));
8143 effect(KILL cr);
8144
8145 format %{ "sall $dst, $shift" %}
8146 opcode(0xD1, 0x4); /* D1 /4 */
8147 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8148 ins_pipe(ialu_reg);
8149 %}
8150
8151 // Shift Left by one
8152 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8153 %{
8154 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8155 effect(KILL cr);
8156
8157 format %{ "sall $dst, $shift\t" %}
8158 opcode(0xD1, 0x4); /* D1 /4 */
8159 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8160 ins_pipe(ialu_mem_imm);
8161 %}
8162
8163 // Shift Left by 8-bit immediate
8164 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8165 %{
8166 match(Set dst (LShiftI dst shift));
8167 effect(KILL cr);
8168
8169 format %{ "sall $dst, $shift" %}
8170 opcode(0xC1, 0x4); /* C1 /4 ib */
8171 ins_encode(reg_opc_imm(dst, shift));
8172 ins_pipe(ialu_reg);
8173 %}
8174
8175 // Shift Left by 8-bit immediate
8176 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8177 %{
8178 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8179 effect(KILL cr);
8180
8181 format %{ "sall $dst, $shift" %}
8182 opcode(0xC1, 0x4); /* C1 /4 ib */
8183 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8184 ins_pipe(ialu_mem_imm);
8185 %}
8186
8187 // Shift Left by variable
8188 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8189 %{
8190 match(Set dst (LShiftI dst shift));
8191 effect(KILL cr);
8192
8193 format %{ "sall $dst, $shift" %}
8194 opcode(0xD3, 0x4); /* D3 /4 */
8195 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8196 ins_pipe(ialu_reg_reg);
8197 %}
8198
8199 // Shift Left by variable
8200 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8201 %{
8202 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8203 effect(KILL cr);
8204
8205 format %{ "sall $dst, $shift" %}
8206 opcode(0xD3, 0x4); /* D3 /4 */
8207 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8208 ins_pipe(ialu_mem_reg);
8209 %}
8210
8211 // Arithmetic shift right by one
8212 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8213 %{
8214 match(Set dst (RShiftI dst shift));
8215 effect(KILL cr);
8216
8217 format %{ "sarl $dst, $shift" %}
8218 opcode(0xD1, 0x7); /* D1 /7 */
8219 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8220 ins_pipe(ialu_reg);
8221 %}
8222
8223 // Arithmetic shift right by one
8224 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8225 %{
8226 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8227 effect(KILL cr);
8228
8229 format %{ "sarl $dst, $shift" %}
8230 opcode(0xD1, 0x7); /* D1 /7 */
8231 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8232 ins_pipe(ialu_mem_imm);
8233 %}
8234
8235 // Arithmetic Shift Right by 8-bit immediate
8236 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8237 %{
8238 match(Set dst (RShiftI dst shift));
8239 effect(KILL cr);
8240
8241 format %{ "sarl $dst, $shift" %}
8242 opcode(0xC1, 0x7); /* C1 /7 ib */
8243 ins_encode(reg_opc_imm(dst, shift));
8244 ins_pipe(ialu_mem_imm);
8245 %}
8246
8247 // Arithmetic Shift Right by 8-bit immediate
8248 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8249 %{
8250 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8251 effect(KILL cr);
8252
8253 format %{ "sarl $dst, $shift" %}
8254 opcode(0xC1, 0x7); /* C1 /7 ib */
8255 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8256 ins_pipe(ialu_mem_imm);
8257 %}
8258
8259 // Arithmetic Shift Right by variable
8260 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8261 %{
8262 match(Set dst (RShiftI dst shift));
8263 effect(KILL cr);
8264
8265 format %{ "sarl $dst, $shift" %}
8266 opcode(0xD3, 0x7); /* D3 /7 */
8267 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8268 ins_pipe(ialu_reg_reg);
8269 %}
8270
8271 // Arithmetic Shift Right by variable
8272 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8273 %{
8274 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8275 effect(KILL cr);
8276
8277 format %{ "sarl $dst, $shift" %}
8278 opcode(0xD3, 0x7); /* D3 /7 */
8279 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8280 ins_pipe(ialu_mem_reg);
8281 %}
8282
8283 // Logical shift right by one
8284 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8285 %{
8286 match(Set dst (URShiftI dst shift));
8287 effect(KILL cr);
8288
8289 format %{ "shrl $dst, $shift" %}
8290 opcode(0xD1, 0x5); /* D1 /5 */
8291 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8292 ins_pipe(ialu_reg);
8293 %}
8294
8295 // Logical shift right by one
8296 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8297 %{
8298 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8299 effect(KILL cr);
8300
8301 format %{ "shrl $dst, $shift" %}
8302 opcode(0xD1, 0x5); /* D1 /5 */
8303 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8304 ins_pipe(ialu_mem_imm);
8305 %}
8306
8307 // Logical Shift Right by 8-bit immediate
8308 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8309 %{
8310 match(Set dst (URShiftI dst shift));
8311 effect(KILL cr);
8312
8313 format %{ "shrl $dst, $shift" %}
8314 opcode(0xC1, 0x5); /* C1 /5 ib */
8315 ins_encode(reg_opc_imm(dst, shift));
8316 ins_pipe(ialu_reg);
8317 %}
8318
8319 // Logical Shift Right by 8-bit immediate
8320 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8321 %{
8322 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8323 effect(KILL cr);
8324
8325 format %{ "shrl $dst, $shift" %}
8326 opcode(0xC1, 0x5); /* C1 /5 ib */
8327 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8328 ins_pipe(ialu_mem_imm);
8329 %}
8330
8331 // Logical Shift Right by variable
8332 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8333 %{
8334 match(Set dst (URShiftI dst shift));
8335 effect(KILL cr);
8336
8337 format %{ "shrl $dst, $shift" %}
8338 opcode(0xD3, 0x5); /* D3 /5 */
8339 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8340 ins_pipe(ialu_reg_reg);
8341 %}
8342
8343 // Logical Shift Right by variable
8344 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8345 %{
8346 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8347 effect(KILL cr);
8348
8349 format %{ "shrl $dst, $shift" %}
8350 opcode(0xD3, 0x5); /* D3 /5 */
8351 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8352 ins_pipe(ialu_mem_reg);
8353 %}
8354
8355 // Long Shift Instructions
8356 // Shift Left by one
8357 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8358 %{
8359 match(Set dst (LShiftL dst shift));
8360 effect(KILL cr);
8361
8362 format %{ "salq $dst, $shift" %}
8363 opcode(0xD1, 0x4); /* D1 /4 */
8364 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8365 ins_pipe(ialu_reg);
8366 %}
8367
8368 // Shift Left by one
8369 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8370 %{
8371 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8372 effect(KILL cr);
8373
8374 format %{ "salq $dst, $shift" %}
8375 opcode(0xD1, 0x4); /* D1 /4 */
8376 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8377 ins_pipe(ialu_mem_imm);
8378 %}
8379
8380 // Shift Left by 8-bit immediate
8381 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8382 %{
8383 match(Set dst (LShiftL dst shift));
8384 effect(KILL cr);
8385
8386 format %{ "salq $dst, $shift" %}
8387 opcode(0xC1, 0x4); /* C1 /4 ib */
8388 ins_encode(reg_opc_imm_wide(dst, shift));
8389 ins_pipe(ialu_reg);
8390 %}
8391
8392 // Shift Left by 8-bit immediate
8393 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8394 %{
8395 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8396 effect(KILL cr);
8397
8398 format %{ "salq $dst, $shift" %}
8399 opcode(0xC1, 0x4); /* C1 /4 ib */
8400 ins_encode(REX_mem_wide(dst), OpcP,
8401 RM_opc_mem(secondary, dst), Con8or32(shift));
8402 ins_pipe(ialu_mem_imm);
8403 %}
8404
8405 // Shift Left by variable
8406 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8407 %{
8408 match(Set dst (LShiftL dst shift));
8409 effect(KILL cr);
8410
8411 format %{ "salq $dst, $shift" %}
8412 opcode(0xD3, 0x4); /* D3 /4 */
8413 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8414 ins_pipe(ialu_reg_reg);
8415 %}
8416
8417 // Shift Left by variable
8418 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8419 %{
8420 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8421 effect(KILL cr);
8422
8423 format %{ "salq $dst, $shift" %}
8424 opcode(0xD3, 0x4); /* D3 /4 */
8425 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8426 ins_pipe(ialu_mem_reg);
8427 %}
8428
8429 // Arithmetic shift right by one
8430 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8431 %{
8432 match(Set dst (RShiftL dst shift));
8433 effect(KILL cr);
8434
8435 format %{ "sarq $dst, $shift" %}
8436 opcode(0xD1, 0x7); /* D1 /7 */
8437 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8438 ins_pipe(ialu_reg);
8439 %}
8440
8441 // Arithmetic shift right by one
8442 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8443 %{
8444 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8445 effect(KILL cr);
8446
8447 format %{ "sarq $dst, $shift" %}
8448 opcode(0xD1, 0x7); /* D1 /7 */
8449 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8450 ins_pipe(ialu_mem_imm);
8451 %}
8452
8453 // Arithmetic Shift Right by 8-bit immediate
8454 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8455 %{
8456 match(Set dst (RShiftL dst shift));
8457 effect(KILL cr);
8458
8459 format %{ "sarq $dst, $shift" %}
8460 opcode(0xC1, 0x7); /* C1 /7 ib */
8461 ins_encode(reg_opc_imm_wide(dst, shift));
8462 ins_pipe(ialu_mem_imm);
8463 %}
8464
8465 // Arithmetic Shift Right by 8-bit immediate
8466 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8467 %{
8468 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8469 effect(KILL cr);
8470
8471 format %{ "sarq $dst, $shift" %}
8472 opcode(0xC1, 0x7); /* C1 /7 ib */
8473 ins_encode(REX_mem_wide(dst), OpcP,
8474 RM_opc_mem(secondary, dst), Con8or32(shift));
8475 ins_pipe(ialu_mem_imm);
8476 %}
8477
8478 // Arithmetic Shift Right by variable
8479 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8480 %{
8481 match(Set dst (RShiftL dst shift));
8482 effect(KILL cr);
8483
8484 format %{ "sarq $dst, $shift" %}
8485 opcode(0xD3, 0x7); /* D3 /7 */
8486 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8487 ins_pipe(ialu_reg_reg);
8488 %}
8489
8490 // Arithmetic Shift Right by variable
8491 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8492 %{
8493 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8494 effect(KILL cr);
8495
8496 format %{ "sarq $dst, $shift" %}
8497 opcode(0xD3, 0x7); /* D3 /7 */
8498 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8499 ins_pipe(ialu_mem_reg);
8500 %}
8501
8502 // Logical shift right by one
8503 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8504 %{
8505 match(Set dst (URShiftL dst shift));
8506 effect(KILL cr);
8507
8508 format %{ "shrq $dst, $shift" %}
8509 opcode(0xD1, 0x5); /* D1 /5 */
8510 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8511 ins_pipe(ialu_reg);
8512 %}
8513
8514 // Logical shift right by one
8515 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8516 %{
8517 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8518 effect(KILL cr);
8519
8520 format %{ "shrq $dst, $shift" %}
8521 opcode(0xD1, 0x5); /* D1 /5 */
8522 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8523 ins_pipe(ialu_mem_imm);
8524 %}
8525
8526 // Logical Shift Right by 8-bit immediate
8527 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8528 %{
8529 match(Set dst (URShiftL dst shift));
8530 effect(KILL cr);
8531
8532 format %{ "shrq $dst, $shift" %}
8533 opcode(0xC1, 0x5); /* C1 /5 ib */
8534 ins_encode(reg_opc_imm_wide(dst, shift));
8535 ins_pipe(ialu_reg);
8536 %}
8537
8538
8539 // Logical Shift Right by 8-bit immediate
8540 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8541 %{
8542 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8543 effect(KILL cr);
8544
8545 format %{ "shrq $dst, $shift" %}
8546 opcode(0xC1, 0x5); /* C1 /5 ib */
8547 ins_encode(REX_mem_wide(dst), OpcP,
8548 RM_opc_mem(secondary, dst), Con8or32(shift));
8549 ins_pipe(ialu_mem_imm);
8550 %}
8551
8552 // Logical Shift Right by variable
8553 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8554 %{
8555 match(Set dst (URShiftL dst shift));
8556 effect(KILL cr);
8557
8558 format %{ "shrq $dst, $shift" %}
8559 opcode(0xD3, 0x5); /* D3 /5 */
8560 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8561 ins_pipe(ialu_reg_reg);
8562 %}
8563
8564 // Logical Shift Right by variable
8565 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8566 %{
8567 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8568 effect(KILL cr);
8569
8570 format %{ "shrq $dst, $shift" %}
8571 opcode(0xD3, 0x5); /* D3 /5 */
8572 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8573 ins_pipe(ialu_mem_reg);
8574 %}
8575
8576 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8577 // This idiom is used by the compiler for the i2b bytecode.
8578 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8579 %{
8580 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8581
8582 format %{ "movsbl $dst, $src\t# i2b" %}
8583 opcode(0x0F, 0xBE);
8584 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8585 ins_pipe(ialu_reg_reg);
8586 %}
8587
8588 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8589 // This idiom is used by the compiler the i2s bytecode.
8590 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8591 %{
8592 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8593
8594 format %{ "movswl $dst, $src\t# i2s" %}
8595 opcode(0x0F, 0xBF);
8596 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8597 ins_pipe(ialu_reg_reg);
8598 %}
8599
8600 // ROL/ROR instructions
8601
8602 // ROL expand
8603 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8604 effect(KILL cr, USE_DEF dst);
8605
8606 format %{ "roll $dst" %}
8607 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8608 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8609 ins_pipe(ialu_reg);
8610 %}
8611
8612 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8613 effect(USE_DEF dst, USE shift, KILL cr);
8614
8615 format %{ "roll $dst, $shift" %}
8616 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8617 ins_encode( reg_opc_imm(dst, shift) );
8618 ins_pipe(ialu_reg);
8619 %}
8620
8621 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8622 %{
8623 effect(USE_DEF dst, USE shift, KILL cr);
8624
8625 format %{ "roll $dst, $shift" %}
8626 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8627 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8628 ins_pipe(ialu_reg_reg);
8629 %}
8630 // end of ROL expand
8631
8632 // Rotate Left by one
8633 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8634 %{
8635 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8636
8637 expand %{
8638 rolI_rReg_imm1(dst, cr);
8639 %}
8640 %}
8641
8642 // Rotate Left by 8-bit immediate
8643 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8644 %{
8645 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8646 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8647
8648 expand %{
8649 rolI_rReg_imm8(dst, lshift, cr);
8650 %}
8651 %}
8652
8653 // Rotate Left by variable
8654 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8655 %{
8656 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8657
8658 expand %{
8659 rolI_rReg_CL(dst, shift, cr);
8660 %}
8661 %}
8662
8663 // Rotate Left by variable
8664 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8665 %{
8666 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8667
8668 expand %{
8669 rolI_rReg_CL(dst, shift, cr);
8670 %}
8671 %}
8672
8673 // ROR expand
8674 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8675 %{
8676 effect(USE_DEF dst, KILL cr);
8677
8678 format %{ "rorl $dst" %}
8679 opcode(0xD1, 0x1); /* D1 /1 */
8680 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8681 ins_pipe(ialu_reg);
8682 %}
8683
8684 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8685 %{
8686 effect(USE_DEF dst, USE shift, KILL cr);
8687
8688 format %{ "rorl $dst, $shift" %}
8689 opcode(0xC1, 0x1); /* C1 /1 ib */
8690 ins_encode(reg_opc_imm(dst, shift));
8691 ins_pipe(ialu_reg);
8692 %}
8693
8694 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8695 %{
8696 effect(USE_DEF dst, USE shift, KILL cr);
8697
8698 format %{ "rorl $dst, $shift" %}
8699 opcode(0xD3, 0x1); /* D3 /1 */
8700 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8701 ins_pipe(ialu_reg_reg);
8702 %}
8703 // end of ROR expand
8704
8705 // Rotate Right by one
8706 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8707 %{
8708 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8709
8710 expand %{
8711 rorI_rReg_imm1(dst, cr);
8712 %}
8713 %}
8714
8715 // Rotate Right by 8-bit immediate
8716 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8717 %{
8718 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8719 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8720
8721 expand %{
8722 rorI_rReg_imm8(dst, rshift, cr);
8723 %}
8724 %}
8725
8726 // Rotate Right by variable
8727 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8728 %{
8729 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8730
8731 expand %{
8732 rorI_rReg_CL(dst, shift, cr);
8733 %}
8734 %}
8735
8736 // Rotate Right by variable
8737 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8738 %{
8739 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8740
8741 expand %{
8742 rorI_rReg_CL(dst, shift, cr);
8743 %}
8744 %}
8745
8746 // for long rotate
8747 // ROL expand
8748 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8749 effect(USE_DEF dst, KILL cr);
8750
8751 format %{ "rolq $dst" %}
8752 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8753 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8754 ins_pipe(ialu_reg);
8755 %}
8756
8757 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8758 effect(USE_DEF dst, USE shift, KILL cr);
8759
8760 format %{ "rolq $dst, $shift" %}
8761 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8762 ins_encode( reg_opc_imm_wide(dst, shift) );
8763 ins_pipe(ialu_reg);
8764 %}
8765
8766 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8767 %{
8768 effect(USE_DEF dst, USE shift, KILL cr);
8769
8770 format %{ "rolq $dst, $shift" %}
8771 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8772 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8773 ins_pipe(ialu_reg_reg);
8774 %}
8775 // end of ROL expand
8776
8777 // Rotate Left by one
8778 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8779 %{
8780 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8781
8782 expand %{
8783 rolL_rReg_imm1(dst, cr);
8784 %}
8785 %}
8786
8787 // Rotate Left by 8-bit immediate
8788 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8789 %{
8790 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8791 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8792
8793 expand %{
8794 rolL_rReg_imm8(dst, lshift, cr);
8795 %}
8796 %}
8797
8798 // Rotate Left by variable
8799 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8800 %{
8801 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8802
8803 expand %{
8804 rolL_rReg_CL(dst, shift, cr);
8805 %}
8806 %}
8807
8808 // Rotate Left by variable
8809 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8810 %{
8811 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8812
8813 expand %{
8814 rolL_rReg_CL(dst, shift, cr);
8815 %}
8816 %}
8817
8818 // ROR expand
8819 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8820 %{
8821 effect(USE_DEF dst, KILL cr);
8822
8823 format %{ "rorq $dst" %}
8824 opcode(0xD1, 0x1); /* D1 /1 */
8825 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8826 ins_pipe(ialu_reg);
8827 %}
8828
8829 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8830 %{
8831 effect(USE_DEF dst, USE shift, KILL cr);
8832
8833 format %{ "rorq $dst, $shift" %}
8834 opcode(0xC1, 0x1); /* C1 /1 ib */
8835 ins_encode(reg_opc_imm_wide(dst, shift));
8836 ins_pipe(ialu_reg);
8837 %}
8838
8839 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8840 %{
8841 effect(USE_DEF dst, USE shift, KILL cr);
8842
8843 format %{ "rorq $dst, $shift" %}
8844 opcode(0xD3, 0x1); /* D3 /1 */
8845 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8846 ins_pipe(ialu_reg_reg);
8847 %}
8848 // end of ROR expand
8849
8850 // Rotate Right by one
8851 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8852 %{
8853 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8854
8855 expand %{
8856 rorL_rReg_imm1(dst, cr);
8857 %}
8858 %}
8859
8860 // Rotate Right by 8-bit immediate
8861 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8862 %{
8863 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8864 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8865
8866 expand %{
8867 rorL_rReg_imm8(dst, rshift, cr);
8868 %}
8869 %}
8870
8871 // Rotate Right by variable
8872 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8873 %{
8874 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8875
8876 expand %{
8877 rorL_rReg_CL(dst, shift, cr);
8878 %}
8879 %}
8880
8881 // Rotate Right by variable
8882 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8883 %{
8884 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8885
8886 expand %{
8887 rorL_rReg_CL(dst, shift, cr);
8888 %}
8889 %}
8890
8891 // Logical Instructions
8892
8893 // Integer Logical Instructions
8894
8895 // And Instructions
8896 // And Register with Register
8897 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8898 %{
8899 match(Set dst (AndI dst src));
8900 effect(KILL cr);
8901
8902 format %{ "andl $dst, $src\t# int" %}
8903 opcode(0x23);
8904 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8905 ins_pipe(ialu_reg_reg);
8906 %}
8907
8908 // And Register with Immediate 255
8909 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8910 %{
8911 match(Set dst (AndI dst src));
8912
8913 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8914 opcode(0x0F, 0xB6);
8915 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8916 ins_pipe(ialu_reg);
8917 %}
8918
8919 // And Register with Immediate 255 and promote to long
8920 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8921 %{
8922 match(Set dst (ConvI2L (AndI src mask)));
8923
8924 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8925 opcode(0x0F, 0xB6);
8926 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8927 ins_pipe(ialu_reg);
8928 %}
8929
8930 // And Register with Immediate 65535
8931 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8932 %{
8933 match(Set dst (AndI dst src));
8934
8935 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8936 opcode(0x0F, 0xB7);
8937 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8938 ins_pipe(ialu_reg);
8939 %}
8940
8941 // And Register with Immediate 65535 and promote to long
8942 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8943 %{
8944 match(Set dst (ConvI2L (AndI src mask)));
8945
8946 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8947 opcode(0x0F, 0xB7);
8948 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8949 ins_pipe(ialu_reg);
8950 %}
8951
8952 // And Register with Immediate
8953 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8954 %{
8955 match(Set dst (AndI dst src));
8956 effect(KILL cr);
8957
8958 format %{ "andl $dst, $src\t# int" %}
8959 opcode(0x81, 0x04); /* Opcode 81 /4 */
8960 ins_encode(OpcSErm(dst, src), Con8or32(src));
8961 ins_pipe(ialu_reg);
8962 %}
8963
8964 // And Register with Memory
8965 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8966 %{
8967 match(Set dst (AndI dst (LoadI src)));
8968 effect(KILL cr);
8969
8970 ins_cost(125);
8971 format %{ "andl $dst, $src\t# int" %}
8972 opcode(0x23);
8973 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8974 ins_pipe(ialu_reg_mem);
8975 %}
8976
8977 // And Memory with Register
8978 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8979 %{
8980 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8981 effect(KILL cr);
8982
8983 ins_cost(150);
8984 format %{ "andl $dst, $src\t# int" %}
8985 opcode(0x21); /* Opcode 21 /r */
8986 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8987 ins_pipe(ialu_mem_reg);
8988 %}
8989
8990 // And Memory with Immediate
8991 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8992 %{
8993 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8994 effect(KILL cr);
8995
8996 ins_cost(125);
8997 format %{ "andl $dst, $src\t# int" %}
8998 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8999 ins_encode(REX_mem(dst), OpcSE(src),
9000 RM_opc_mem(secondary, dst), Con8or32(src));
9001 ins_pipe(ialu_mem_imm);
9002 %}
9003
9004 // Or Instructions
9005 // Or Register with Register
9006 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9007 %{
9008 match(Set dst (OrI dst src));
9009 effect(KILL cr);
9010
9011 format %{ "orl $dst, $src\t# int" %}
9012 opcode(0x0B);
9013 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9014 ins_pipe(ialu_reg_reg);
9015 %}
9016
9017 // Or Register with Immediate
9018 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9019 %{
9020 match(Set dst (OrI dst src));
9021 effect(KILL cr);
9022
9023 format %{ "orl $dst, $src\t# int" %}
9024 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9025 ins_encode(OpcSErm(dst, src), Con8or32(src));
9026 ins_pipe(ialu_reg);
9027 %}
9028
9029 // Or Register with Memory
9030 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9031 %{
9032 match(Set dst (OrI dst (LoadI src)));
9033 effect(KILL cr);
9034
9035 ins_cost(125);
9036 format %{ "orl $dst, $src\t# int" %}
9037 opcode(0x0B);
9038 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9039 ins_pipe(ialu_reg_mem);
9040 %}
9041
9042 // Or Memory with Register
9043 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9044 %{
9045 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9046 effect(KILL cr);
9047
9048 ins_cost(150);
9049 format %{ "orl $dst, $src\t# int" %}
9050 opcode(0x09); /* Opcode 09 /r */
9051 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9052 ins_pipe(ialu_mem_reg);
9053 %}
9054
9055 // Or Memory with Immediate
9056 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9057 %{
9058 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9059 effect(KILL cr);
9060
9061 ins_cost(125);
9062 format %{ "orl $dst, $src\t# int" %}
9063 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9064 ins_encode(REX_mem(dst), OpcSE(src),
9065 RM_opc_mem(secondary, dst), Con8or32(src));
9066 ins_pipe(ialu_mem_imm);
9067 %}
9068
9069 // Xor Instructions
9070 // Xor Register with Register
9071 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9072 %{
9073 match(Set dst (XorI dst src));
9074 effect(KILL cr);
9075
9076 format %{ "xorl $dst, $src\t# int" %}
9077 opcode(0x33);
9078 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9079 ins_pipe(ialu_reg_reg);
9080 %}
9081
9082 // Xor Register with Immediate -1
9083 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9084 match(Set dst (XorI dst imm));
9085
9086 format %{ "not $dst" %}
9087 ins_encode %{
9088 __ notl($dst$$Register);
9089 %}
9090 ins_pipe(ialu_reg);
9091 %}
9092
9093 // Xor Register with Immediate
9094 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9095 %{
9096 match(Set dst (XorI dst src));
9097 effect(KILL cr);
9098
9099 format %{ "xorl $dst, $src\t# int" %}
9100 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9101 ins_encode(OpcSErm(dst, src), Con8or32(src));
9102 ins_pipe(ialu_reg);
9103 %}
9104
9105 // Xor Register with Memory
9106 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9107 %{
9108 match(Set dst (XorI dst (LoadI src)));
9109 effect(KILL cr);
9110
9111 ins_cost(125);
9112 format %{ "xorl $dst, $src\t# int" %}
9113 opcode(0x33);
9114 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9115 ins_pipe(ialu_reg_mem);
9116 %}
9117
9118 // Xor Memory with Register
9119 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9120 %{
9121 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9122 effect(KILL cr);
9123
9124 ins_cost(150);
9125 format %{ "xorl $dst, $src\t# int" %}
9126 opcode(0x31); /* Opcode 31 /r */
9127 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9128 ins_pipe(ialu_mem_reg);
9129 %}
9130
9131 // Xor Memory with Immediate
9132 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9133 %{
9134 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9135 effect(KILL cr);
9136
9137 ins_cost(125);
9138 format %{ "xorl $dst, $src\t# int" %}
9139 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9140 ins_encode(REX_mem(dst), OpcSE(src),
9141 RM_opc_mem(secondary, dst), Con8or32(src));
9142 ins_pipe(ialu_mem_imm);
9143 %}
9144
9145
9146 // Long Logical Instructions
9147
9148 // And Instructions
9149 // And Register with Register
9150 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9151 %{
9152 match(Set dst (AndL dst src));
9153 effect(KILL cr);
9154
9155 format %{ "andq $dst, $src\t# long" %}
9156 opcode(0x23);
9157 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9158 ins_pipe(ialu_reg_reg);
9159 %}
9160
9161 // And Register with Immediate 255
9162 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9163 %{
9164 match(Set dst (AndL dst src));
9165
9166 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9167 opcode(0x0F, 0xB6);
9168 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9169 ins_pipe(ialu_reg);
9170 %}
9171
9172 // And Register with Immediate 65535
9173 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9174 %{
9175 match(Set dst (AndL dst src));
9176
9177 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9178 opcode(0x0F, 0xB7);
9179 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9180 ins_pipe(ialu_reg);
9181 %}
9182
9183 // And Register with Immediate
9184 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9185 %{
9186 match(Set dst (AndL dst src));
9187 effect(KILL cr);
9188
9189 format %{ "andq $dst, $src\t# long" %}
9190 opcode(0x81, 0x04); /* Opcode 81 /4 */
9191 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9192 ins_pipe(ialu_reg);
9193 %}
9194
9195 // And Register with Memory
9196 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9197 %{
9198 match(Set dst (AndL dst (LoadL src)));
9199 effect(KILL cr);
9200
9201 ins_cost(125);
9202 format %{ "andq $dst, $src\t# long" %}
9203 opcode(0x23);
9204 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9205 ins_pipe(ialu_reg_mem);
9206 %}
9207
9208 // And Memory with Register
9209 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9210 %{
9211 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9212 effect(KILL cr);
9213
9214 ins_cost(150);
9215 format %{ "andq $dst, $src\t# long" %}
9216 opcode(0x21); /* Opcode 21 /r */
9217 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9218 ins_pipe(ialu_mem_reg);
9219 %}
9220
9221 // And Memory with Immediate
9222 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9223 %{
9224 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9225 effect(KILL cr);
9226
9227 ins_cost(125);
9228 format %{ "andq $dst, $src\t# long" %}
9229 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9230 ins_encode(REX_mem_wide(dst), OpcSE(src),
9231 RM_opc_mem(secondary, dst), Con8or32(src));
9232 ins_pipe(ialu_mem_imm);
9233 %}
9234
9235 // Or Instructions
9236 // Or Register with Register
9237 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9238 %{
9239 match(Set dst (OrL dst src));
9240 effect(KILL cr);
9241
9242 format %{ "orq $dst, $src\t# long" %}
9243 opcode(0x0B);
9244 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9245 ins_pipe(ialu_reg_reg);
9246 %}
9247
9248 // Use any_RegP to match R15 (TLS register) without spilling.
9249 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9250 match(Set dst (OrL dst (CastP2X src)));
9251 effect(KILL cr);
9252
9253 format %{ "orq $dst, $src\t# long" %}
9254 opcode(0x0B);
9255 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9256 ins_pipe(ialu_reg_reg);
9257 %}
9258
9259
9260 // Or Register with Immediate
9261 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9262 %{
9263 match(Set dst (OrL dst src));
9264 effect(KILL cr);
9265
9266 format %{ "orq $dst, $src\t# long" %}
9267 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9268 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9269 ins_pipe(ialu_reg);
9270 %}
9271
9272 // Or Register with Memory
9273 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9274 %{
9275 match(Set dst (OrL dst (LoadL src)));
9276 effect(KILL cr);
9277
9278 ins_cost(125);
9279 format %{ "orq $dst, $src\t# long" %}
9280 opcode(0x0B);
9281 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9282 ins_pipe(ialu_reg_mem);
9283 %}
9284
9285 // Or Memory with Register
9286 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9287 %{
9288 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9289 effect(KILL cr);
9290
9291 ins_cost(150);
9292 format %{ "orq $dst, $src\t# long" %}
9293 opcode(0x09); /* Opcode 09 /r */
9294 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9295 ins_pipe(ialu_mem_reg);
9296 %}
9297
9298 // Or Memory with Immediate
9299 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9300 %{
9301 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9302 effect(KILL cr);
9303
9304 ins_cost(125);
9305 format %{ "orq $dst, $src\t# long" %}
9306 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9307 ins_encode(REX_mem_wide(dst), OpcSE(src),
9308 RM_opc_mem(secondary, dst), Con8or32(src));
9309 ins_pipe(ialu_mem_imm);
9310 %}
9311
9312 // Xor Instructions
9313 // Xor Register with Register
9314 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9315 %{
9316 match(Set dst (XorL dst src));
9317 effect(KILL cr);
9318
9319 format %{ "xorq $dst, $src\t# long" %}
9320 opcode(0x33);
9321 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9322 ins_pipe(ialu_reg_reg);
9323 %}
9324
9325 // Xor Register with Immediate -1
9326 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9327 match(Set dst (XorL dst imm));
9328
9329 format %{ "notq $dst" %}
9330 ins_encode %{
9331 __ notq($dst$$Register);
9332 %}
9333 ins_pipe(ialu_reg);
9334 %}
9335
9336 // Xor Register with Immediate
9337 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9338 %{
9339 match(Set dst (XorL dst src));
9340 effect(KILL cr);
9341
9342 format %{ "xorq $dst, $src\t# long" %}
9343 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9344 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9345 ins_pipe(ialu_reg);
9346 %}
9347
9348 // Xor Register with Memory
9349 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9350 %{
9351 match(Set dst (XorL dst (LoadL src)));
9352 effect(KILL cr);
9353
9354 ins_cost(125);
9355 format %{ "xorq $dst, $src\t# long" %}
9356 opcode(0x33);
9357 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9358 ins_pipe(ialu_reg_mem);
9359 %}
9360
9361 // Xor Memory with Register
9362 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9363 %{
9364 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9365 effect(KILL cr);
9366
9367 ins_cost(150);
9368 format %{ "xorq $dst, $src\t# long" %}
9369 opcode(0x31); /* Opcode 31 /r */
9370 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9371 ins_pipe(ialu_mem_reg);
9372 %}
9373
9374 // Xor Memory with Immediate
9375 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9376 %{
9377 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9378 effect(KILL cr);
9379
9380 ins_cost(125);
9381 format %{ "xorq $dst, $src\t# long" %}
9382 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9383 ins_encode(REX_mem_wide(dst), OpcSE(src),
9384 RM_opc_mem(secondary, dst), Con8or32(src));
9385 ins_pipe(ialu_mem_imm);
9386 %}
9387
9388 // Convert Int to Boolean
9389 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9390 %{
9391 match(Set dst (Conv2B src));
9392 effect(KILL cr);
9393
9394 format %{ "testl $src, $src\t# ci2b\n\t"
9395 "setnz $dst\n\t"
9396 "movzbl $dst, $dst" %}
9397 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9398 setNZ_reg(dst),
9399 REX_reg_breg(dst, dst), // movzbl
9400 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9401 ins_pipe(pipe_slow); // XXX
9402 %}
9403
9404 // Convert Pointer to Boolean
9405 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9406 %{
9407 match(Set dst (Conv2B src));
9408 effect(KILL cr);
9409
9410 format %{ "testq $src, $src\t# cp2b\n\t"
9411 "setnz $dst\n\t"
9412 "movzbl $dst, $dst" %}
9413 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9414 setNZ_reg(dst),
9415 REX_reg_breg(dst, dst), // movzbl
9416 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9417 ins_pipe(pipe_slow); // XXX
9418 %}
9419
9420 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9421 %{
9422 match(Set dst (CmpLTMask p q));
9423 effect(KILL cr);
9424
9425 ins_cost(400); // XXX
9426 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9427 "setlt $dst\n\t"
9428 "movzbl $dst, $dst\n\t"
9429 "negl $dst" %}
9430 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9431 setLT_reg(dst),
9432 REX_reg_breg(dst, dst), // movzbl
9433 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9434 neg_reg(dst));
9435 ins_pipe(pipe_slow);
9436 %}
9437
9438 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9439 %{
9440 match(Set dst (CmpLTMask dst zero));
9441 effect(KILL cr);
9442
9443 ins_cost(100); // XXX
9444 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9445 opcode(0xC1, 0x7); /* C1 /7 ib */
9446 ins_encode(reg_opc_imm(dst, 0x1F));
9447 ins_pipe(ialu_reg);
9448 %}
9449
9450
9451 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
9452 %{
9453 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9454 effect(TEMP tmp, KILL cr);
9455
9456 ins_cost(400); // XXX
9457 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9458 "sbbl $tmp, $tmp\n\t"
9459 "andl $tmp, $y\n\t"
9460 "addl $p, $tmp" %}
9461 ins_encode %{
9462 Register Rp = $p$$Register;
9463 Register Rq = $q$$Register;
9464 Register Ry = $y$$Register;
9465 Register Rt = $tmp$$Register;
9466 __ subl(Rp, Rq);
9467 __ sbbl(Rt, Rt);
9468 __ andl(Rt, Ry);
9469 __ addl(Rp, Rt);
9470 %}
9471 ins_pipe(pipe_cmplt);
9472 %}
9473
9474 //---------- FP Instructions------------------------------------------------
9475
9476 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9477 %{
9478 match(Set cr (CmpF src1 src2));
9479
9480 ins_cost(145);
9481 format %{ "ucomiss $src1, $src2\n\t"
9482 "jnp,s exit\n\t"
9483 "pushfq\t# saw NaN, set CF\n\t"
9484 "andq [rsp], #0xffffff2b\n\t"
9485 "popfq\n"
9486 "exit:" %}
9487 ins_encode %{
9488 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9489 emit_cmpfp_fixup(_masm);
9490 %}
9491 ins_pipe(pipe_slow);
9492 %}
9493
9494 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9495 match(Set cr (CmpF src1 src2));
9496
9497 ins_cost(100);
9498 format %{ "ucomiss $src1, $src2" %}
9499 ins_encode %{
9500 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9501 %}
9502 ins_pipe(pipe_slow);
9503 %}
9504
9505 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9506 %{
9507 match(Set cr (CmpF src1 (LoadF src2)));
9508
9509 ins_cost(145);
9510 format %{ "ucomiss $src1, $src2\n\t"
9511 "jnp,s exit\n\t"
9512 "pushfq\t# saw NaN, set CF\n\t"
9513 "andq [rsp], #0xffffff2b\n\t"
9514 "popfq\n"
9515 "exit:" %}
9516 ins_encode %{
9517 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9518 emit_cmpfp_fixup(_masm);
9519 %}
9520 ins_pipe(pipe_slow);
9521 %}
9522
9523 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9524 match(Set cr (CmpF src1 (LoadF src2)));
9525
9526 ins_cost(100);
9527 format %{ "ucomiss $src1, $src2" %}
9528 ins_encode %{
9529 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9530 %}
9531 ins_pipe(pipe_slow);
9532 %}
9533
9534 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9535 match(Set cr (CmpF src con));
9536
9537 ins_cost(145);
9538 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9539 "jnp,s exit\n\t"
9540 "pushfq\t# saw NaN, set CF\n\t"
9541 "andq [rsp], #0xffffff2b\n\t"
9542 "popfq\n"
9543 "exit:" %}
9544 ins_encode %{
9545 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9546 emit_cmpfp_fixup(_masm);
9547 %}
9548 ins_pipe(pipe_slow);
9549 %}
9550
9551 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9552 match(Set cr (CmpF src con));
9553 ins_cost(100);
9554 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9555 ins_encode %{
9556 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9557 %}
9558 ins_pipe(pipe_slow);
9559 %}
9560
9561 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9562 %{
9563 match(Set cr (CmpD src1 src2));
9564
9565 ins_cost(145);
9566 format %{ "ucomisd $src1, $src2\n\t"
9567 "jnp,s exit\n\t"
9568 "pushfq\t# saw NaN, set CF\n\t"
9569 "andq [rsp], #0xffffff2b\n\t"
9570 "popfq\n"
9571 "exit:" %}
9572 ins_encode %{
9573 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9574 emit_cmpfp_fixup(_masm);
9575 %}
9576 ins_pipe(pipe_slow);
9577 %}
9578
9579 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9580 match(Set cr (CmpD src1 src2));
9581
9582 ins_cost(100);
9583 format %{ "ucomisd $src1, $src2 test" %}
9584 ins_encode %{
9585 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9586 %}
9587 ins_pipe(pipe_slow);
9588 %}
9589
9590 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9591 %{
9592 match(Set cr (CmpD src1 (LoadD src2)));
9593
9594 ins_cost(145);
9595 format %{ "ucomisd $src1, $src2\n\t"
9596 "jnp,s exit\n\t"
9597 "pushfq\t# saw NaN, set CF\n\t"
9598 "andq [rsp], #0xffffff2b\n\t"
9599 "popfq\n"
9600 "exit:" %}
9601 ins_encode %{
9602 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9603 emit_cmpfp_fixup(_masm);
9604 %}
9605 ins_pipe(pipe_slow);
9606 %}
9607
9608 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9609 match(Set cr (CmpD src1 (LoadD src2)));
9610
9611 ins_cost(100);
9612 format %{ "ucomisd $src1, $src2" %}
9613 ins_encode %{
9614 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9615 %}
9616 ins_pipe(pipe_slow);
9617 %}
9618
9619 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9620 match(Set cr (CmpD src con));
9621
9622 ins_cost(145);
9623 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9624 "jnp,s exit\n\t"
9625 "pushfq\t# saw NaN, set CF\n\t"
9626 "andq [rsp], #0xffffff2b\n\t"
9627 "popfq\n"
9628 "exit:" %}
9629 ins_encode %{
9630 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9631 emit_cmpfp_fixup(_masm);
9632 %}
9633 ins_pipe(pipe_slow);
9634 %}
9635
9636 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9637 match(Set cr (CmpD src con));
9638 ins_cost(100);
9639 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9640 ins_encode %{
9641 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9642 %}
9643 ins_pipe(pipe_slow);
9644 %}
9645
9646 // Compare into -1,0,1
9647 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9648 %{
9649 match(Set dst (CmpF3 src1 src2));
9650 effect(KILL cr);
9651
9652 ins_cost(275);
9653 format %{ "ucomiss $src1, $src2\n\t"
9654 "movl $dst, #-1\n\t"
9655 "jp,s done\n\t"
9656 "jb,s done\n\t"
9657 "setne $dst\n\t"
9658 "movzbl $dst, $dst\n"
9659 "done:" %}
9660 ins_encode %{
9661 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9662 emit_cmpfp3(_masm, $dst$$Register);
9663 %}
9664 ins_pipe(pipe_slow);
9665 %}
9666
9667 // Compare into -1,0,1
9668 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9669 %{
9670 match(Set dst (CmpF3 src1 (LoadF src2)));
9671 effect(KILL cr);
9672
9673 ins_cost(275);
9674 format %{ "ucomiss $src1, $src2\n\t"
9675 "movl $dst, #-1\n\t"
9676 "jp,s done\n\t"
9677 "jb,s done\n\t"
9678 "setne $dst\n\t"
9679 "movzbl $dst, $dst\n"
9680 "done:" %}
9681 ins_encode %{
9682 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9683 emit_cmpfp3(_masm, $dst$$Register);
9684 %}
9685 ins_pipe(pipe_slow);
9686 %}
9687
9688 // Compare into -1,0,1
9689 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9690 match(Set dst (CmpF3 src con));
9691 effect(KILL cr);
9692
9693 ins_cost(275);
9694 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9695 "movl $dst, #-1\n\t"
9696 "jp,s done\n\t"
9697 "jb,s done\n\t"
9698 "setne $dst\n\t"
9699 "movzbl $dst, $dst\n"
9700 "done:" %}
9701 ins_encode %{
9702 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9703 emit_cmpfp3(_masm, $dst$$Register);
9704 %}
9705 ins_pipe(pipe_slow);
9706 %}
9707
9708 // Compare into -1,0,1
9709 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9710 %{
9711 match(Set dst (CmpD3 src1 src2));
9712 effect(KILL cr);
9713
9714 ins_cost(275);
9715 format %{ "ucomisd $src1, $src2\n\t"
9716 "movl $dst, #-1\n\t"
9717 "jp,s done\n\t"
9718 "jb,s done\n\t"
9719 "setne $dst\n\t"
9720 "movzbl $dst, $dst\n"
9721 "done:" %}
9722 ins_encode %{
9723 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9724 emit_cmpfp3(_masm, $dst$$Register);
9725 %}
9726 ins_pipe(pipe_slow);
9727 %}
9728
9729 // Compare into -1,0,1
9730 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9731 %{
9732 match(Set dst (CmpD3 src1 (LoadD src2)));
9733 effect(KILL cr);
9734
9735 ins_cost(275);
9736 format %{ "ucomisd $src1, $src2\n\t"
9737 "movl $dst, #-1\n\t"
9738 "jp,s done\n\t"
9739 "jb,s done\n\t"
9740 "setne $dst\n\t"
9741 "movzbl $dst, $dst\n"
9742 "done:" %}
9743 ins_encode %{
9744 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9745 emit_cmpfp3(_masm, $dst$$Register);
9746 %}
9747 ins_pipe(pipe_slow);
9748 %}
9749
9750 // Compare into -1,0,1
9751 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9752 match(Set dst (CmpD3 src con));
9753 effect(KILL cr);
9754
9755 ins_cost(275);
9756 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9757 "movl $dst, #-1\n\t"
9758 "jp,s done\n\t"
9759 "jb,s done\n\t"
9760 "setne $dst\n\t"
9761 "movzbl $dst, $dst\n"
9762 "done:" %}
9763 ins_encode %{
9764 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9765 emit_cmpfp3(_masm, $dst$$Register);
9766 %}
9767 ins_pipe(pipe_slow);
9768 %}
9769
9770 // -----------Trig and Trancendental Instructions------------------------------
9771 instruct cosD_reg(regD dst) %{
9772 match(Set dst (CosD dst));
9773
9774 format %{ "dcos $dst\n\t" %}
9775 opcode(0xD9, 0xFF);
9776 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9777 ins_pipe( pipe_slow );
9778 %}
9779
9780 instruct sinD_reg(regD dst) %{
9781 match(Set dst (SinD dst));
9782
9783 format %{ "dsin $dst\n\t" %}
9784 opcode(0xD9, 0xFE);
9785 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9786 ins_pipe( pipe_slow );
9787 %}
9788
9789 instruct tanD_reg(regD dst) %{
9790 match(Set dst (TanD dst));
9791
9792 format %{ "dtan $dst\n\t" %}
9793 ins_encode( Push_SrcXD(dst),
9794 Opcode(0xD9), Opcode(0xF2), //fptan
9795 Opcode(0xDD), Opcode(0xD8), //fstp st
9796 Push_ResultXD(dst) );
9797 ins_pipe( pipe_slow );
9798 %}
9799
9800 instruct log10D_reg(regD dst) %{
9801 // The source and result Double operands in XMM registers
9802 match(Set dst (Log10D dst));
9803 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9804 // fyl2x ; compute log_10(2) * log_2(x)
9805 format %{ "fldlg2\t\t\t#Log10\n\t"
9806 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9807 %}
9808 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9809 Push_SrcXD(dst),
9810 Opcode(0xD9), Opcode(0xF1), // fyl2x
9811 Push_ResultXD(dst));
9812
9813 ins_pipe( pipe_slow );
9814 %}
9815
9816 instruct logD_reg(regD dst) %{
9817 // The source and result Double operands in XMM registers
9818 match(Set dst (LogD dst));
9819 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9820 // fyl2x ; compute log_e(2) * log_2(x)
9821 format %{ "fldln2\t\t\t#Log_e\n\t"
9822 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9823 %}
9824 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9825 Push_SrcXD(dst),
9826 Opcode(0xD9), Opcode(0xF1), // fyl2x
9827 Push_ResultXD(dst));
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9832 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9833 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9834 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9835 ins_encode %{
9836 __ subptr(rsp, 8);
9837 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9838 __ fld_d(Address(rsp, 0));
9839 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9840 __ fld_d(Address(rsp, 0));
9841 __ fast_pow();
9842 __ fstp_d(Address(rsp, 0));
9843 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9844 __ addptr(rsp, 8);
9845 %}
9846 ins_pipe( pipe_slow );
9847 %}
9848
9849 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9850 match(Set dst (ExpD src));
9851 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9852 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9853 ins_encode %{
9854 __ subptr(rsp, 8);
9855 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9856 __ fld_d(Address(rsp, 0));
9857 __ fast_exp();
9858 __ fstp_d(Address(rsp, 0));
9859 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9860 __ addptr(rsp, 8);
9861 %}
9862 ins_pipe( pipe_slow );
9863 %}
9864
9865 //----------Arithmetic Conversion Instructions---------------------------------
9866
9867 instruct roundFloat_nop(regF dst)
9868 %{
9869 match(Set dst (RoundFloat dst));
9870
9871 ins_cost(0);
9872 ins_encode();
9873 ins_pipe(empty);
9874 %}
9875
9876 instruct roundDouble_nop(regD dst)
9877 %{
9878 match(Set dst (RoundDouble dst));
9879
9880 ins_cost(0);
9881 ins_encode();
9882 ins_pipe(empty);
9883 %}
9884
9885 instruct convF2D_reg_reg(regD dst, regF src)
9886 %{
9887 match(Set dst (ConvF2D src));
9888
9889 format %{ "cvtss2sd $dst, $src" %}
9890 ins_encode %{
9891 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9892 %}
9893 ins_pipe(pipe_slow); // XXX
9894 %}
9895
9896 instruct convF2D_reg_mem(regD dst, memory src)
9897 %{
9898 match(Set dst (ConvF2D (LoadF src)));
9899
9900 format %{ "cvtss2sd $dst, $src" %}
9901 ins_encode %{
9902 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9903 %}
9904 ins_pipe(pipe_slow); // XXX
9905 %}
9906
9907 instruct convD2F_reg_reg(regF dst, regD src)
9908 %{
9909 match(Set dst (ConvD2F src));
9910
9911 format %{ "cvtsd2ss $dst, $src" %}
9912 ins_encode %{
9913 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9914 %}
9915 ins_pipe(pipe_slow); // XXX
9916 %}
9917
9918 instruct convD2F_reg_mem(regF dst, memory src)
9919 %{
9920 match(Set dst (ConvD2F (LoadD src)));
9921
9922 format %{ "cvtsd2ss $dst, $src" %}
9923 ins_encode %{
9924 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9925 %}
9926 ins_pipe(pipe_slow); // XXX
9927 %}
9928
9929 // XXX do mem variants
9930 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9931 %{
9932 match(Set dst (ConvF2I src));
9933 effect(KILL cr);
9934
9935 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9936 "cmpl $dst, #0x80000000\n\t"
9937 "jne,s done\n\t"
9938 "subq rsp, #8\n\t"
9939 "movss [rsp], $src\n\t"
9940 "call f2i_fixup\n\t"
9941 "popq $dst\n"
9942 "done: "%}
9943 ins_encode %{
9944 Label done;
9945 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9946 __ cmpl($dst$$Register, 0x80000000);
9947 __ jccb(Assembler::notEqual, done);
9948 __ subptr(rsp, 8);
9949 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9950 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9951 __ pop($dst$$Register);
9952 __ bind(done);
9953 %}
9954 ins_pipe(pipe_slow);
9955 %}
9956
9957 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9958 %{
9959 match(Set dst (ConvF2L src));
9960 effect(KILL cr);
9961
9962 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9963 "cmpq $dst, [0x8000000000000000]\n\t"
9964 "jne,s done\n\t"
9965 "subq rsp, #8\n\t"
9966 "movss [rsp], $src\n\t"
9967 "call f2l_fixup\n\t"
9968 "popq $dst\n"
9969 "done: "%}
9970 ins_encode %{
9971 Label done;
9972 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9973 __ cmp64($dst$$Register,
9974 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9975 __ jccb(Assembler::notEqual, done);
9976 __ subptr(rsp, 8);
9977 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9978 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9979 __ pop($dst$$Register);
9980 __ bind(done);
9981 %}
9982 ins_pipe(pipe_slow);
9983 %}
9984
9985 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9986 %{
9987 match(Set dst (ConvD2I src));
9988 effect(KILL cr);
9989
9990 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9991 "cmpl $dst, #0x80000000\n\t"
9992 "jne,s done\n\t"
9993 "subq rsp, #8\n\t"
9994 "movsd [rsp], $src\n\t"
9995 "call d2i_fixup\n\t"
9996 "popq $dst\n"
9997 "done: "%}
9998 ins_encode %{
9999 Label done;
10000 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10001 __ cmpl($dst$$Register, 0x80000000);
10002 __ jccb(Assembler::notEqual, done);
10003 __ subptr(rsp, 8);
10004 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10005 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10006 __ pop($dst$$Register);
10007 __ bind(done);
10008 %}
10009 ins_pipe(pipe_slow);
10010 %}
10011
10012 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10013 %{
10014 match(Set dst (ConvD2L src));
10015 effect(KILL cr);
10016
10017 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10018 "cmpq $dst, [0x8000000000000000]\n\t"
10019 "jne,s done\n\t"
10020 "subq rsp, #8\n\t"
10021 "movsd [rsp], $src\n\t"
10022 "call d2l_fixup\n\t"
10023 "popq $dst\n"
10024 "done: "%}
10025 ins_encode %{
10026 Label done;
10027 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10028 __ cmp64($dst$$Register,
10029 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10030 __ jccb(Assembler::notEqual, done);
10031 __ subptr(rsp, 8);
10032 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10033 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10034 __ pop($dst$$Register);
10035 __ bind(done);
10036 %}
10037 ins_pipe(pipe_slow);
10038 %}
10039
10040 instruct convI2F_reg_reg(regF dst, rRegI src)
10041 %{
10042 predicate(!UseXmmI2F);
10043 match(Set dst (ConvI2F src));
10044
10045 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10046 ins_encode %{
10047 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10048 %}
10049 ins_pipe(pipe_slow); // XXX
10050 %}
10051
10052 instruct convI2F_reg_mem(regF dst, memory src)
10053 %{
10054 match(Set dst (ConvI2F (LoadI src)));
10055
10056 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10057 ins_encode %{
10058 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10059 %}
10060 ins_pipe(pipe_slow); // XXX
10061 %}
10062
10063 instruct convI2D_reg_reg(regD dst, rRegI src)
10064 %{
10065 predicate(!UseXmmI2D);
10066 match(Set dst (ConvI2D src));
10067
10068 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10069 ins_encode %{
10070 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10071 %}
10072 ins_pipe(pipe_slow); // XXX
10073 %}
10074
10075 instruct convI2D_reg_mem(regD dst, memory src)
10076 %{
10077 match(Set dst (ConvI2D (LoadI src)));
10078
10079 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10080 ins_encode %{
10081 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10082 %}
10083 ins_pipe(pipe_slow); // XXX
10084 %}
10085
10086 instruct convXI2F_reg(regF dst, rRegI src)
10087 %{
10088 predicate(UseXmmI2F);
10089 match(Set dst (ConvI2F src));
10090
10091 format %{ "movdl $dst, $src\n\t"
10092 "cvtdq2psl $dst, $dst\t# i2f" %}
10093 ins_encode %{
10094 __ movdl($dst$$XMMRegister, $src$$Register);
10095 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10096 %}
10097 ins_pipe(pipe_slow); // XXX
10098 %}
10099
10100 instruct convXI2D_reg(regD dst, rRegI src)
10101 %{
10102 predicate(UseXmmI2D);
10103 match(Set dst (ConvI2D src));
10104
10105 format %{ "movdl $dst, $src\n\t"
10106 "cvtdq2pdl $dst, $dst\t# i2d" %}
10107 ins_encode %{
10108 __ movdl($dst$$XMMRegister, $src$$Register);
10109 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10110 %}
10111 ins_pipe(pipe_slow); // XXX
10112 %}
10113
10114 instruct convL2F_reg_reg(regF dst, rRegL src)
10115 %{
10116 match(Set dst (ConvL2F src));
10117
10118 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10119 ins_encode %{
10120 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10121 %}
10122 ins_pipe(pipe_slow); // XXX
10123 %}
10124
10125 instruct convL2F_reg_mem(regF dst, memory src)
10126 %{
10127 match(Set dst (ConvL2F (LoadL src)));
10128
10129 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10130 ins_encode %{
10131 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10132 %}
10133 ins_pipe(pipe_slow); // XXX
10134 %}
10135
10136 instruct convL2D_reg_reg(regD dst, rRegL src)
10137 %{
10138 match(Set dst (ConvL2D src));
10139
10140 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10141 ins_encode %{
10142 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10143 %}
10144 ins_pipe(pipe_slow); // XXX
10145 %}
10146
10147 instruct convL2D_reg_mem(regD dst, memory src)
10148 %{
10149 match(Set dst (ConvL2D (LoadL src)));
10150
10151 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10152 ins_encode %{
10153 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10154 %}
10155 ins_pipe(pipe_slow); // XXX
10156 %}
10157
10158 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10159 %{
10160 match(Set dst (ConvI2L src));
10161
10162 ins_cost(125);
10163 format %{ "movslq $dst, $src\t# i2l" %}
10164 ins_encode %{
10165 __ movslq($dst$$Register, $src$$Register);
10166 %}
10167 ins_pipe(ialu_reg_reg);
10168 %}
10169
10170 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10171 // %{
10172 // match(Set dst (ConvI2L src));
10173 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10174 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10175 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10176 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10177 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10178 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10179
10180 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10181 // ins_encode(enc_copy(dst, src));
10182 // // opcode(0x63); // needs REX.W
10183 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10184 // ins_pipe(ialu_reg_reg);
10185 // %}
10186
10187 // Zero-extend convert int to long
10188 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10189 %{
10190 match(Set dst (AndL (ConvI2L src) mask));
10191
10192 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10193 ins_encode %{
10194 if ($dst$$reg != $src$$reg) {
10195 __ movl($dst$$Register, $src$$Register);
10196 }
10197 %}
10198 ins_pipe(ialu_reg_reg);
10199 %}
10200
10201 // Zero-extend convert int to long
10202 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10203 %{
10204 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10205
10206 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10207 ins_encode %{
10208 __ movl($dst$$Register, $src$$Address);
10209 %}
10210 ins_pipe(ialu_reg_mem);
10211 %}
10212
10213 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10214 %{
10215 match(Set dst (AndL src mask));
10216
10217 format %{ "movl $dst, $src\t# zero-extend long" %}
10218 ins_encode %{
10219 __ movl($dst$$Register, $src$$Register);
10220 %}
10221 ins_pipe(ialu_reg_reg);
10222 %}
10223
10224 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10225 %{
10226 match(Set dst (ConvL2I src));
10227
10228 format %{ "movl $dst, $src\t# l2i" %}
10229 ins_encode %{
10230 __ movl($dst$$Register, $src$$Register);
10231 %}
10232 ins_pipe(ialu_reg_reg);
10233 %}
10234
10235
10236 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10237 match(Set dst (MoveF2I src));
10238 effect(DEF dst, USE src);
10239
10240 ins_cost(125);
10241 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10242 ins_encode %{
10243 __ movl($dst$$Register, Address(rsp, $src$$disp));
10244 %}
10245 ins_pipe(ialu_reg_mem);
10246 %}
10247
10248 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10249 match(Set dst (MoveI2F src));
10250 effect(DEF dst, USE src);
10251
10252 ins_cost(125);
10253 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10254 ins_encode %{
10255 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10256 %}
10257 ins_pipe(pipe_slow);
10258 %}
10259
10260 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10261 match(Set dst (MoveD2L src));
10262 effect(DEF dst, USE src);
10263
10264 ins_cost(125);
10265 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10266 ins_encode %{
10267 __ movq($dst$$Register, Address(rsp, $src$$disp));
10268 %}
10269 ins_pipe(ialu_reg_mem);
10270 %}
10271
10272 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10273 predicate(!UseXmmLoadAndClearUpper);
10274 match(Set dst (MoveL2D src));
10275 effect(DEF dst, USE src);
10276
10277 ins_cost(125);
10278 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10279 ins_encode %{
10280 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10281 %}
10282 ins_pipe(pipe_slow);
10283 %}
10284
10285 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10286 predicate(UseXmmLoadAndClearUpper);
10287 match(Set dst (MoveL2D src));
10288 effect(DEF dst, USE src);
10289
10290 ins_cost(125);
10291 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10292 ins_encode %{
10293 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10294 %}
10295 ins_pipe(pipe_slow);
10296 %}
10297
10298
10299 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10300 match(Set dst (MoveF2I src));
10301 effect(DEF dst, USE src);
10302
10303 ins_cost(95); // XXX
10304 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10305 ins_encode %{
10306 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10307 %}
10308 ins_pipe(pipe_slow);
10309 %}
10310
10311 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10312 match(Set dst (MoveI2F src));
10313 effect(DEF dst, USE src);
10314
10315 ins_cost(100);
10316 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10317 ins_encode %{
10318 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10319 %}
10320 ins_pipe( ialu_mem_reg );
10321 %}
10322
10323 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10324 match(Set dst (MoveD2L src));
10325 effect(DEF dst, USE src);
10326
10327 ins_cost(95); // XXX
10328 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10329 ins_encode %{
10330 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10331 %}
10332 ins_pipe(pipe_slow);
10333 %}
10334
10335 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10336 match(Set dst (MoveL2D src));
10337 effect(DEF dst, USE src);
10338
10339 ins_cost(100);
10340 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10341 ins_encode %{
10342 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10343 %}
10344 ins_pipe(ialu_mem_reg);
10345 %}
10346
10347 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10348 match(Set dst (MoveF2I src));
10349 effect(DEF dst, USE src);
10350 ins_cost(85);
10351 format %{ "movd $dst,$src\t# MoveF2I" %}
10352 ins_encode %{
10353 __ movdl($dst$$Register, $src$$XMMRegister);
10354 %}
10355 ins_pipe( pipe_slow );
10356 %}
10357
10358 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10359 match(Set dst (MoveD2L src));
10360 effect(DEF dst, USE src);
10361 ins_cost(85);
10362 format %{ "movd $dst,$src\t# MoveD2L" %}
10363 ins_encode %{
10364 __ movdq($dst$$Register, $src$$XMMRegister);
10365 %}
10366 ins_pipe( pipe_slow );
10367 %}
10368
10369 // The next instructions have long latency and use Int unit. Set high cost.
10370 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10371 match(Set dst (MoveI2F src));
10372 effect(DEF dst, USE src);
10373 ins_cost(300);
10374 format %{ "movd $dst,$src\t# MoveI2F" %}
10375 ins_encode %{
10376 __ movdl($dst$$XMMRegister, $src$$Register);
10377 %}
10378 ins_pipe( pipe_slow );
10379 %}
10380
10381 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10382 match(Set dst (MoveL2D src));
10383 effect(DEF dst, USE src);
10384 ins_cost(300);
10385 format %{ "movd $dst,$src\t# MoveL2D" %}
10386 ins_encode %{
10387 __ movdq($dst$$XMMRegister, $src$$Register);
10388 %}
10389 ins_pipe( pipe_slow );
10390 %}
10391
10392 // Replicate scalar to packed byte (1 byte) values in xmm
10393 instruct Repl8B_reg(regD dst, regD src) %{
10394 match(Set dst (Replicate8B src));
10395 format %{ "MOVDQA $dst,$src\n\t"
10396 "PUNPCKLBW $dst,$dst\n\t"
10397 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10398 ins_encode %{
10399 if ($dst$$reg != $src$$reg) {
10400 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
10401 }
10402 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
10403 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10404 %}
10405 ins_pipe( pipe_slow );
10406 %}
10407
10408 // Replicate scalar to packed byte (1 byte) values in xmm
10409 instruct Repl8B_rRegI(regD dst, rRegI src) %{
10410 match(Set dst (Replicate8B src));
10411 format %{ "MOVD $dst,$src\n\t"
10412 "PUNPCKLBW $dst,$dst\n\t"
10413 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10414 ins_encode %{
10415 __ movdl($dst$$XMMRegister, $src$$Register);
10416 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
10417 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10418 %}
10419 ins_pipe( pipe_slow );
10420 %}
10421
10422 // Replicate scalar zero to packed byte (1 byte) values in xmm
10423 instruct Repl8B_immI0(regD dst, immI0 zero) %{
10424 match(Set dst (Replicate8B zero));
10425 format %{ "PXOR $dst,$dst\t! replicate8B" %}
10426 ins_encode %{
10427 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10428 %}
10429 ins_pipe( fpu_reg_reg );
10430 %}
10431
10432 // Replicate scalar to packed shore (2 byte) values in xmm
10433 instruct Repl4S_reg(regD dst, regD src) %{
10434 match(Set dst (Replicate4S src));
10435 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
10436 ins_encode %{
10437 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10438 %}
10439 ins_pipe( fpu_reg_reg );
10440 %}
10441
10442 // Replicate scalar to packed shore (2 byte) values in xmm
10443 instruct Repl4S_rRegI(regD dst, rRegI src) %{
10444 match(Set dst (Replicate4S src));
10445 format %{ "MOVD $dst,$src\n\t"
10446 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
10447 ins_encode %{
10448 __ movdl($dst$$XMMRegister, $src$$Register);
10449 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10450 %}
10451 ins_pipe( fpu_reg_reg );
10452 %}
10453
10454 // Replicate scalar zero to packed short (2 byte) values in xmm
10455 instruct Repl4S_immI0(regD dst, immI0 zero) %{
10456 match(Set dst (Replicate4S zero));
10457 format %{ "PXOR $dst,$dst\t! replicate4S" %}
10458 ins_encode %{
10459 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10460 %}
10461 ins_pipe( fpu_reg_reg );
10462 %}
10463
10464 // Replicate scalar to packed char (2 byte) values in xmm
10465 instruct Repl4C_reg(regD dst, regD src) %{
10466 match(Set dst (Replicate4C src));
10467 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
10468 ins_encode %{
10469 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10470 %}
10471 ins_pipe( fpu_reg_reg );
10472 %}
10473
10474 // Replicate scalar to packed char (2 byte) values in xmm
10475 instruct Repl4C_rRegI(regD dst, rRegI src) %{
10476 match(Set dst (Replicate4C src));
10477 format %{ "MOVD $dst,$src\n\t"
10478 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
10479 ins_encode %{
10480 __ movdl($dst$$XMMRegister, $src$$Register);
10481 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10482 %}
10483 ins_pipe( fpu_reg_reg );
10484 %}
10485
10486 // Replicate scalar zero to packed char (2 byte) values in xmm
10487 instruct Repl4C_immI0(regD dst, immI0 zero) %{
10488 match(Set dst (Replicate4C zero));
10489 format %{ "PXOR $dst,$dst\t! replicate4C" %}
10490 ins_encode %{
10491 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10492 %}
10493 ins_pipe( fpu_reg_reg );
10494 %}
10495
10496 // Replicate scalar to packed integer (4 byte) values in xmm
10497 instruct Repl2I_reg(regD dst, regD src) %{
10498 match(Set dst (Replicate2I src));
10499 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
10500 ins_encode %{
10501 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10502 %}
10503 ins_pipe( fpu_reg_reg );
10504 %}
10505
10506 // Replicate scalar to packed integer (4 byte) values in xmm
10507 instruct Repl2I_rRegI(regD dst, rRegI src) %{
10508 match(Set dst (Replicate2I src));
10509 format %{ "MOVD $dst,$src\n\t"
10510 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
10511 ins_encode %{
10512 __ movdl($dst$$XMMRegister, $src$$Register);
10513 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10514 %}
10515 ins_pipe( fpu_reg_reg );
10516 %}
10517
10518 // Replicate scalar zero to packed integer (2 byte) values in xmm
10519 instruct Repl2I_immI0(regD dst, immI0 zero) %{
10520 match(Set dst (Replicate2I zero));
10521 format %{ "PXOR $dst,$dst\t! replicate2I" %}
10522 ins_encode %{
10523 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10524 %}
10525 ins_pipe( fpu_reg_reg );
10526 %}
10527
10528 // Replicate scalar to packed single precision floating point values in xmm
10529 instruct Repl2F_reg(regD dst, regD src) %{
10530 match(Set dst (Replicate2F src));
10531 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10532 ins_encode %{
10533 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
10534 %}
10535 ins_pipe( fpu_reg_reg );
10536 %}
10537
10538 // Replicate scalar to packed single precision floating point values in xmm
10539 instruct Repl2F_regF(regD dst, regF src) %{
10540 match(Set dst (Replicate2F src));
10541 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10542 ins_encode %{
10543 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
10544 %}
10545 ins_pipe( fpu_reg_reg );
10546 %}
10547
10548 // Replicate scalar to packed single precision floating point values in xmm
10549 instruct Repl2F_immF0(regD dst, immF0 zero) %{
10550 match(Set dst (Replicate2F zero));
10551 format %{ "PXOR $dst,$dst\t! replicate2F" %}
10552 ins_encode %{
10553 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10554 %}
10555 ins_pipe( fpu_reg_reg );
10556 %}
10557
10558
10559 // =======================================================================
10560 // fast clearing of an array
10561 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10562 rFlagsReg cr)
10563 %{
10564 match(Set dummy (ClearArray cnt base));
10565 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10566
10567 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10568 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10569 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10570 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10571 ins_pipe(pipe_slow);
10572 %}
10573
10574 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10575 rax_RegI result, regD tmp1, rFlagsReg cr)
10576 %{
10577 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10578 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10579
10580 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10581 ins_encode %{
10582 __ string_compare($str1$$Register, $str2$$Register,
10583 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10584 $tmp1$$XMMRegister);
10585 %}
10586 ins_pipe( pipe_slow );
10587 %}
10588
10589 // fast search of substring with known size.
10590 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10591 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10592 %{
10593 predicate(UseSSE42Intrinsics);
10594 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10595 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10596
10597 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10598 ins_encode %{
10599 int icnt2 = (int)$int_cnt2$$constant;
10600 if (icnt2 >= 8) {
10601 // IndexOf for constant substrings with size >= 8 elements
10602 // which don't need to be loaded through stack.
10603 __ string_indexofC8($str1$$Register, $str2$$Register,
10604 $cnt1$$Register, $cnt2$$Register,
10605 icnt2, $result$$Register,
10606 $vec$$XMMRegister, $tmp$$Register);
10607 } else {
10608 // Small strings are loaded through stack if they cross page boundary.
10609 __ string_indexof($str1$$Register, $str2$$Register,
10610 $cnt1$$Register, $cnt2$$Register,
10611 icnt2, $result$$Register,
10612 $vec$$XMMRegister, $tmp$$Register);
10613 }
10614 %}
10615 ins_pipe( pipe_slow );
10616 %}
10617
10618 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10619 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10620 %{
10621 predicate(UseSSE42Intrinsics);
10622 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10623 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10624
10625 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10626 ins_encode %{
10627 __ string_indexof($str1$$Register, $str2$$Register,
10628 $cnt1$$Register, $cnt2$$Register,
10629 (-1), $result$$Register,
10630 $vec$$XMMRegister, $tmp$$Register);
10631 %}
10632 ins_pipe( pipe_slow );
10633 %}
10634
10635 // fast string equals
10636 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10637 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10638 %{
10639 match(Set result (StrEquals (Binary str1 str2) cnt));
10640 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10641
10642 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10643 ins_encode %{
10644 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10645 $cnt$$Register, $result$$Register, $tmp3$$Register,
10646 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10647 %}
10648 ins_pipe( pipe_slow );
10649 %}
10650
10651 // fast array equals
10652 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10653 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10654 %{
10655 match(Set result (AryEq ary1 ary2));
10656 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10657 //ins_cost(300);
10658
10659 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10660 ins_encode %{
10661 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10662 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10663 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10664 %}
10665 ins_pipe( pipe_slow );
10666 %}
10667
10668 //----------Control Flow Instructions------------------------------------------
10669 // Signed compare Instructions
10670
10671 // XXX more variants!!
10672 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10673 %{
10674 match(Set cr (CmpI op1 op2));
10675 effect(DEF cr, USE op1, USE op2);
10676
10677 format %{ "cmpl $op1, $op2" %}
10678 opcode(0x3B); /* Opcode 3B /r */
10679 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10680 ins_pipe(ialu_cr_reg_reg);
10681 %}
10682
10683 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10684 %{
10685 match(Set cr (CmpI op1 op2));
10686
10687 format %{ "cmpl $op1, $op2" %}
10688 opcode(0x81, 0x07); /* Opcode 81 /7 */
10689 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10690 ins_pipe(ialu_cr_reg_imm);
10691 %}
10692
10693 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10694 %{
10695 match(Set cr (CmpI op1 (LoadI op2)));
10696
10697 ins_cost(500); // XXX
10698 format %{ "cmpl $op1, $op2" %}
10699 opcode(0x3B); /* Opcode 3B /r */
10700 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10701 ins_pipe(ialu_cr_reg_mem);
10702 %}
10703
10704 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10705 %{
10706 match(Set cr (CmpI src zero));
10707
10708 format %{ "testl $src, $src" %}
10709 opcode(0x85);
10710 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10711 ins_pipe(ialu_cr_reg_imm);
10712 %}
10713
10714 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10715 %{
10716 match(Set cr (CmpI (AndI src con) zero));
10717
10718 format %{ "testl $src, $con" %}
10719 opcode(0xF7, 0x00);
10720 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10721 ins_pipe(ialu_cr_reg_imm);
10722 %}
10723
10724 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10725 %{
10726 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10727
10728 format %{ "testl $src, $mem" %}
10729 opcode(0x85);
10730 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10731 ins_pipe(ialu_cr_reg_mem);
10732 %}
10733
10734 // Unsigned compare Instructions; really, same as signed except they
10735 // produce an rFlagsRegU instead of rFlagsReg.
10736 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10737 %{
10738 match(Set cr (CmpU op1 op2));
10739
10740 format %{ "cmpl $op1, $op2\t# unsigned" %}
10741 opcode(0x3B); /* Opcode 3B /r */
10742 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10743 ins_pipe(ialu_cr_reg_reg);
10744 %}
10745
10746 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10747 %{
10748 match(Set cr (CmpU op1 op2));
10749
10750 format %{ "cmpl $op1, $op2\t# unsigned" %}
10751 opcode(0x81,0x07); /* Opcode 81 /7 */
10752 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10753 ins_pipe(ialu_cr_reg_imm);
10754 %}
10755
10756 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10757 %{
10758 match(Set cr (CmpU op1 (LoadI op2)));
10759
10760 ins_cost(500); // XXX
10761 format %{ "cmpl $op1, $op2\t# unsigned" %}
10762 opcode(0x3B); /* Opcode 3B /r */
10763 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10764 ins_pipe(ialu_cr_reg_mem);
10765 %}
10766
10767 // // // Cisc-spilled version of cmpU_rReg
10768 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10769 // //%{
10770 // // match(Set cr (CmpU (LoadI op1) op2));
10771 // //
10772 // // format %{ "CMPu $op1,$op2" %}
10773 // // ins_cost(500);
10774 // // opcode(0x39); /* Opcode 39 /r */
10775 // // ins_encode( OpcP, reg_mem( op1, op2) );
10776 // //%}
10777
10778 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10779 %{
10780 match(Set cr (CmpU src zero));
10781
10782 format %{ "testl $src, $src\t# unsigned" %}
10783 opcode(0x85);
10784 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10785 ins_pipe(ialu_cr_reg_imm);
10786 %}
10787
10788 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10789 %{
10790 match(Set cr (CmpP op1 op2));
10791
10792 format %{ "cmpq $op1, $op2\t# ptr" %}
10793 opcode(0x3B); /* Opcode 3B /r */
10794 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10795 ins_pipe(ialu_cr_reg_reg);
10796 %}
10797
10798 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10799 %{
10800 match(Set cr (CmpP op1 (LoadP op2)));
10801
10802 ins_cost(500); // XXX
10803 format %{ "cmpq $op1, $op2\t# ptr" %}
10804 opcode(0x3B); /* Opcode 3B /r */
10805 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10806 ins_pipe(ialu_cr_reg_mem);
10807 %}
10808
10809 // // // Cisc-spilled version of cmpP_rReg
10810 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10811 // //%{
10812 // // match(Set cr (CmpP (LoadP op1) op2));
10813 // //
10814 // // format %{ "CMPu $op1,$op2" %}
10815 // // ins_cost(500);
10816 // // opcode(0x39); /* Opcode 39 /r */
10817 // // ins_encode( OpcP, reg_mem( op1, op2) );
10818 // //%}
10819
10820 // XXX this is generalized by compP_rReg_mem???
10821 // Compare raw pointer (used in out-of-heap check).
10822 // Only works because non-oop pointers must be raw pointers
10823 // and raw pointers have no anti-dependencies.
10824 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10825 %{
10826 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
10827 match(Set cr (CmpP op1 (LoadP op2)));
10828
10829 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10830 opcode(0x3B); /* Opcode 3B /r */
10831 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10832 ins_pipe(ialu_cr_reg_mem);
10833 %}
10834
10835 // This will generate a signed flags result. This should be OK since
10836 // any compare to a zero should be eq/neq.
10837 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10838 %{
10839 match(Set cr (CmpP src zero));
10840
10841 format %{ "testq $src, $src\t# ptr" %}
10842 opcode(0x85);
10843 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10844 ins_pipe(ialu_cr_reg_imm);
10845 %}
10846
10847 // This will generate a signed flags result. This should be OK since
10848 // any compare to a zero should be eq/neq.
10849 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10850 %{
10851 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10852 match(Set cr (CmpP (LoadP op) zero));
10853
10854 ins_cost(500); // XXX
10855 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10856 opcode(0xF7); /* Opcode F7 /0 */
10857 ins_encode(REX_mem_wide(op),
10858 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10859 ins_pipe(ialu_cr_reg_imm);
10860 %}
10861
10862 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10863 %{
10864 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
10865 match(Set cr (CmpP (LoadP mem) zero));
10866
10867 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10868 ins_encode %{
10869 __ cmpq(r12, $mem$$Address);
10870 %}
10871 ins_pipe(ialu_cr_reg_mem);
10872 %}
10873
10874 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10875 %{
10876 match(Set cr (CmpN op1 op2));
10877
10878 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10879 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10880 ins_pipe(ialu_cr_reg_reg);
10881 %}
10882
10883 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10884 %{
10885 match(Set cr (CmpN src (LoadN mem)));
10886
10887 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10888 ins_encode %{
10889 __ cmpl($src$$Register, $mem$$Address);
10890 %}
10891 ins_pipe(ialu_cr_reg_mem);
10892 %}
10893
10894 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10895 match(Set cr (CmpN op1 op2));
10896
10897 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10898 ins_encode %{
10899 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10900 %}
10901 ins_pipe(ialu_cr_reg_imm);
10902 %}
10903
10904 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10905 %{
10906 match(Set cr (CmpN src (LoadN mem)));
10907
10908 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10909 ins_encode %{
10910 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10911 %}
10912 ins_pipe(ialu_cr_reg_mem);
10913 %}
10914
10915 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10916 match(Set cr (CmpN src zero));
10917
10918 format %{ "testl $src, $src\t# compressed ptr" %}
10919 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10920 ins_pipe(ialu_cr_reg_imm);
10921 %}
10922
10923 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10924 %{
10925 predicate(Universe::narrow_oop_base() != NULL);
10926 match(Set cr (CmpN (LoadN mem) zero));
10927
10928 ins_cost(500); // XXX
10929 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10930 ins_encode %{
10931 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10932 %}
10933 ins_pipe(ialu_cr_reg_mem);
10934 %}
10935
10936 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10937 %{
10938 predicate(Universe::narrow_oop_base() == NULL);
10939 match(Set cr (CmpN (LoadN mem) zero));
10940
10941 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10942 ins_encode %{
10943 __ cmpl(r12, $mem$$Address);
10944 %}
10945 ins_pipe(ialu_cr_reg_mem);
10946 %}
10947
10948 // Yanked all unsigned pointer compare operations.
10949 // Pointer compares are done with CmpP which is already unsigned.
10950
10951 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10952 %{
10953 match(Set cr (CmpL op1 op2));
10954
10955 format %{ "cmpq $op1, $op2" %}
10956 opcode(0x3B); /* Opcode 3B /r */
10957 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10958 ins_pipe(ialu_cr_reg_reg);
10959 %}
10960
10961 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10962 %{
10963 match(Set cr (CmpL op1 op2));
10964
10965 format %{ "cmpq $op1, $op2" %}
10966 opcode(0x81, 0x07); /* Opcode 81 /7 */
10967 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10968 ins_pipe(ialu_cr_reg_imm);
10969 %}
10970
10971 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10972 %{
10973 match(Set cr (CmpL op1 (LoadL op2)));
10974
10975 format %{ "cmpq $op1, $op2" %}
10976 opcode(0x3B); /* Opcode 3B /r */
10977 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10978 ins_pipe(ialu_cr_reg_mem);
10979 %}
10980
10981 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10982 %{
10983 match(Set cr (CmpL src zero));
10984
10985 format %{ "testq $src, $src" %}
10986 opcode(0x85);
10987 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10988 ins_pipe(ialu_cr_reg_imm);
10989 %}
10990
10991 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10992 %{
10993 match(Set cr (CmpL (AndL src con) zero));
10994
10995 format %{ "testq $src, $con\t# long" %}
10996 opcode(0xF7, 0x00);
10997 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10998 ins_pipe(ialu_cr_reg_imm);
10999 %}
11000
11001 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11002 %{
11003 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11004
11005 format %{ "testq $src, $mem" %}
11006 opcode(0x85);
11007 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11008 ins_pipe(ialu_cr_reg_mem);
11009 %}
11010
11011 // Manifest a CmpL result in an integer register. Very painful.
11012 // This is the test to avoid.
11013 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11014 %{
11015 match(Set dst (CmpL3 src1 src2));
11016 effect(KILL flags);
11017
11018 ins_cost(275); // XXX
11019 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11020 "movl $dst, -1\n\t"
11021 "jl,s done\n\t"
11022 "setne $dst\n\t"
11023 "movzbl $dst, $dst\n\t"
11024 "done:" %}
11025 ins_encode(cmpl3_flag(src1, src2, dst));
11026 ins_pipe(pipe_slow);
11027 %}
11028
11029 //----------Max and Min--------------------------------------------------------
11030 // Min Instructions
11031
11032 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11033 %{
11034 effect(USE_DEF dst, USE src, USE cr);
11035
11036 format %{ "cmovlgt $dst, $src\t# min" %}
11037 opcode(0x0F, 0x4F);
11038 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11039 ins_pipe(pipe_cmov_reg);
11040 %}
11041
11042
11043 instruct minI_rReg(rRegI dst, rRegI src)
11044 %{
11045 match(Set dst (MinI dst src));
11046
11047 ins_cost(200);
11048 expand %{
11049 rFlagsReg cr;
11050 compI_rReg(cr, dst, src);
11051 cmovI_reg_g(dst, src, cr);
11052 %}
11053 %}
11054
11055 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11056 %{
11057 effect(USE_DEF dst, USE src, USE cr);
11058
11059 format %{ "cmovllt $dst, $src\t# max" %}
11060 opcode(0x0F, 0x4C);
11061 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11062 ins_pipe(pipe_cmov_reg);
11063 %}
11064
11065
11066 instruct maxI_rReg(rRegI dst, rRegI src)
11067 %{
11068 match(Set dst (MaxI dst src));
11069
11070 ins_cost(200);
11071 expand %{
11072 rFlagsReg cr;
11073 compI_rReg(cr, dst, src);
11074 cmovI_reg_l(dst, src, cr);
11075 %}
11076 %}
11077
11078 // ============================================================================
11079 // Branch Instructions
11080
11081 // Jump Direct - Label defines a relative address from JMP+1
11082 instruct jmpDir(label labl)
11083 %{
11084 match(Goto);
11085 effect(USE labl);
11086
11087 ins_cost(300);
11088 format %{ "jmp $labl" %}
11089 size(5);
11090 ins_encode %{
11091 Label* L = $labl$$label;
11092 __ jmp(*L, false); // Always long jump
11093 %}
11094 ins_pipe(pipe_jmp);
11095 %}
11096
11097 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11098 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11099 %{
11100 match(If cop cr);
11101 effect(USE labl);
11102
11103 ins_cost(300);
11104 format %{ "j$cop $labl" %}
11105 size(6);
11106 ins_encode %{
11107 Label* L = $labl$$label;
11108 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11109 %}
11110 ins_pipe(pipe_jcc);
11111 %}
11112
11113 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11114 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11115 %{
11116 match(CountedLoopEnd cop cr);
11117 effect(USE labl);
11118
11119 ins_cost(300);
11120 format %{ "j$cop $labl\t# loop end" %}
11121 size(6);
11122 ins_encode %{
11123 Label* L = $labl$$label;
11124 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11125 %}
11126 ins_pipe(pipe_jcc);
11127 %}
11128
11129 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11130 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11131 match(CountedLoopEnd cop cmp);
11132 effect(USE labl);
11133
11134 ins_cost(300);
11135 format %{ "j$cop,u $labl\t# loop end" %}
11136 size(6);
11137 ins_encode %{
11138 Label* L = $labl$$label;
11139 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11140 %}
11141 ins_pipe(pipe_jcc);
11142 %}
11143
11144 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11145 match(CountedLoopEnd cop cmp);
11146 effect(USE labl);
11147
11148 ins_cost(200);
11149 format %{ "j$cop,u $labl\t# loop end" %}
11150 size(6);
11151 ins_encode %{
11152 Label* L = $labl$$label;
11153 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11154 %}
11155 ins_pipe(pipe_jcc);
11156 %}
11157
11158 // Jump Direct Conditional - using unsigned comparison
11159 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11160 match(If cop cmp);
11161 effect(USE labl);
11162
11163 ins_cost(300);
11164 format %{ "j$cop,u $labl" %}
11165 size(6);
11166 ins_encode %{
11167 Label* L = $labl$$label;
11168 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11169 %}
11170 ins_pipe(pipe_jcc);
11171 %}
11172
11173 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11174 match(If cop cmp);
11175 effect(USE labl);
11176
11177 ins_cost(200);
11178 format %{ "j$cop,u $labl" %}
11179 size(6);
11180 ins_encode %{
11181 Label* L = $labl$$label;
11182 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11183 %}
11184 ins_pipe(pipe_jcc);
11185 %}
11186
11187 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11188 match(If cop cmp);
11189 effect(USE labl);
11190
11191 ins_cost(200);
11192 format %{ $$template
11193 if ($cop$$cmpcode == Assembler::notEqual) {
11194 $$emit$$"jp,u $labl\n\t"
11195 $$emit$$"j$cop,u $labl"
11196 } else {
11197 $$emit$$"jp,u done\n\t"
11198 $$emit$$"j$cop,u $labl\n\t"
11199 $$emit$$"done:"
11200 }
11201 %}
11202 ins_encode %{
11203 Label* l = $labl$$label;
11204 if ($cop$$cmpcode == Assembler::notEqual) {
11205 __ jcc(Assembler::parity, *l, false);
11206 __ jcc(Assembler::notEqual, *l, false);
11207 } else if ($cop$$cmpcode == Assembler::equal) {
11208 Label done;
11209 __ jccb(Assembler::parity, done);
11210 __ jcc(Assembler::equal, *l, false);
11211 __ bind(done);
11212 } else {
11213 ShouldNotReachHere();
11214 }
11215 %}
11216 ins_pipe(pipe_jcc);
11217 %}
11218
11219 // ============================================================================
11220 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11221 // superklass array for an instance of the superklass. Set a hidden
11222 // internal cache on a hit (cache is checked with exposed code in
11223 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11224 // encoding ALSO sets flags.
11225
11226 instruct partialSubtypeCheck(rdi_RegP result,
11227 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11228 rFlagsReg cr)
11229 %{
11230 match(Set result (PartialSubtypeCheck sub super));
11231 effect(KILL rcx, KILL cr);
11232
11233 ins_cost(1100); // slightly larger than the next version
11234 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11235 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11236 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11237 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11238 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11239 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11240 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11241 "miss:\t" %}
11242
11243 opcode(0x1); // Force a XOR of RDI
11244 ins_encode(enc_PartialSubtypeCheck());
11245 ins_pipe(pipe_slow);
11246 %}
11247
11248 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11249 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11250 immP0 zero,
11251 rdi_RegP result)
11252 %{
11253 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11254 effect(KILL rcx, KILL result);
11255
11256 ins_cost(1000);
11257 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11258 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11259 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11260 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11261 "jne,s miss\t\t# Missed: flags nz\n\t"
11262 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11263 "miss:\t" %}
11264
11265 opcode(0x0); // No need to XOR RDI
11266 ins_encode(enc_PartialSubtypeCheck());
11267 ins_pipe(pipe_slow);
11268 %}
11269
11270 // ============================================================================
11271 // Branch Instructions -- short offset versions
11272 //
11273 // These instructions are used to replace jumps of a long offset (the default
11274 // match) with jumps of a shorter offset. These instructions are all tagged
11275 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11276 // match rules in general matching. Instead, the ADLC generates a conversion
11277 // method in the MachNode which can be used to do in-place replacement of the
11278 // long variant with the shorter variant. The compiler will determine if a
11279 // branch can be taken by the is_short_branch_offset() predicate in the machine
11280 // specific code section of the file.
11281
11282 // Jump Direct - Label defines a relative address from JMP+1
11283 instruct jmpDir_short(label labl) %{
11284 match(Goto);
11285 effect(USE labl);
11286
11287 ins_cost(300);
11288 format %{ "jmp,s $labl" %}
11289 size(2);
11290 ins_encode %{
11291 Label* L = $labl$$label;
11292 __ jmpb(*L);
11293 %}
11294 ins_pipe(pipe_jmp);
11295 ins_short_branch(1);
11296 %}
11297
11298 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11299 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11300 match(If cop cr);
11301 effect(USE labl);
11302
11303 ins_cost(300);
11304 format %{ "j$cop,s $labl" %}
11305 size(2);
11306 ins_encode %{
11307 Label* L = $labl$$label;
11308 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11309 %}
11310 ins_pipe(pipe_jcc);
11311 ins_short_branch(1);
11312 %}
11313
11314 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11315 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11316 match(CountedLoopEnd cop cr);
11317 effect(USE labl);
11318
11319 ins_cost(300);
11320 format %{ "j$cop,s $labl\t# loop end" %}
11321 size(2);
11322 ins_encode %{
11323 Label* L = $labl$$label;
11324 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11325 %}
11326 ins_pipe(pipe_jcc);
11327 ins_short_branch(1);
11328 %}
11329
11330 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11331 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11332 match(CountedLoopEnd cop cmp);
11333 effect(USE labl);
11334
11335 ins_cost(300);
11336 format %{ "j$cop,us $labl\t# loop end" %}
11337 size(2);
11338 ins_encode %{
11339 Label* L = $labl$$label;
11340 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11341 %}
11342 ins_pipe(pipe_jcc);
11343 ins_short_branch(1);
11344 %}
11345
11346 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11347 match(CountedLoopEnd cop cmp);
11348 effect(USE labl);
11349
11350 ins_cost(300);
11351 format %{ "j$cop,us $labl\t# loop end" %}
11352 size(2);
11353 ins_encode %{
11354 Label* L = $labl$$label;
11355 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11356 %}
11357 ins_pipe(pipe_jcc);
11358 ins_short_branch(1);
11359 %}
11360
11361 // Jump Direct Conditional - using unsigned comparison
11362 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11363 match(If cop cmp);
11364 effect(USE labl);
11365
11366 ins_cost(300);
11367 format %{ "j$cop,us $labl" %}
11368 size(2);
11369 ins_encode %{
11370 Label* L = $labl$$label;
11371 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11372 %}
11373 ins_pipe(pipe_jcc);
11374 ins_short_branch(1);
11375 %}
11376
11377 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11378 match(If cop cmp);
11379 effect(USE labl);
11380
11381 ins_cost(300);
11382 format %{ "j$cop,us $labl" %}
11383 size(2);
11384 ins_encode %{
11385 Label* L = $labl$$label;
11386 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11387 %}
11388 ins_pipe(pipe_jcc);
11389 ins_short_branch(1);
11390 %}
11391
11392 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11393 match(If cop cmp);
11394 effect(USE labl);
11395
11396 ins_cost(300);
11397 format %{ $$template
11398 if ($cop$$cmpcode == Assembler::notEqual) {
11399 $$emit$$"jp,u,s $labl\n\t"
11400 $$emit$$"j$cop,u,s $labl"
11401 } else {
11402 $$emit$$"jp,u,s done\n\t"
11403 $$emit$$"j$cop,u,s $labl\n\t"
11404 $$emit$$"done:"
11405 }
11406 %}
11407 size(4);
11408 ins_encode %{
11409 Label* l = $labl$$label;
11410 if ($cop$$cmpcode == Assembler::notEqual) {
11411 __ jccb(Assembler::parity, *l);
11412 __ jccb(Assembler::notEqual, *l);
11413 } else if ($cop$$cmpcode == Assembler::equal) {
11414 Label done;
11415 __ jccb(Assembler::parity, done);
11416 __ jccb(Assembler::equal, *l);
11417 __ bind(done);
11418 } else {
11419 ShouldNotReachHere();
11420 }
11421 %}
11422 ins_pipe(pipe_jcc);
11423 ins_short_branch(1);
11424 %}
11425
11426 // ============================================================================
11427 // inlined locking and unlocking
11428
11429 instruct cmpFastLock(rFlagsReg cr,
11430 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
11431 %{
11432 match(Set cr (FastLock object box));
11433 effect(TEMP tmp, TEMP scr, USE_KILL box);
11434
11435 ins_cost(300);
11436 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11437 ins_encode(Fast_Lock(object, box, tmp, scr));
11438 ins_pipe(pipe_slow);
11439 %}
11440
11441 instruct cmpFastUnlock(rFlagsReg cr,
11442 rRegP object, rax_RegP box, rRegP tmp)
11443 %{
11444 match(Set cr (FastUnlock object box));
11445 effect(TEMP tmp, USE_KILL box);
11446
11447 ins_cost(300);
11448 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11449 ins_encode(Fast_Unlock(object, box, tmp));
11450 ins_pipe(pipe_slow);
11451 %}
11452
11453
11454 // ============================================================================
11455 // Safepoint Instructions
11456 instruct safePoint_poll(rFlagsReg cr)
11457 %{
11458 predicate(!Assembler::is_polling_page_far());
11459 match(SafePoint);
11460 effect(KILL cr);
11461
11462 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11463 "# Safepoint: poll for GC" %}
11464 ins_cost(125);
11465 ins_encode %{
11466 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11467 __ testl(rax, addr);
11468 %}
11469 ins_pipe(ialu_reg_mem);
11470 %}
11471
11472 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11473 %{
11474 predicate(Assembler::is_polling_page_far());
11475 match(SafePoint poll);
11476 effect(KILL cr, USE poll);
11477
11478 format %{ "testl rax, [$poll]\t"
11479 "# Safepoint: poll for GC" %}
11480 ins_cost(125);
11481 ins_encode %{
11482 __ relocate(relocInfo::poll_type);
11483 __ testl(rax, Address($poll$$Register, 0));
11484 %}
11485 ins_pipe(ialu_reg_mem);
11486 %}
11487
11488 // ============================================================================
11489 // Procedure Call/Return Instructions
11490 // Call Java Static Instruction
11491 // Note: If this code changes, the corresponding ret_addr_offset() and
11492 // compute_padding() functions will have to be adjusted.
11493 instruct CallStaticJavaDirect(method meth) %{
11494 match(CallStaticJava);
11495 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11496 effect(USE meth);
11497
11498 ins_cost(300);
11499 format %{ "call,static " %}
11500 opcode(0xE8); /* E8 cd */
11501 ins_encode(Java_Static_Call(meth), call_epilog);
11502 ins_pipe(pipe_slow);
11503 ins_alignment(4);
11504 %}
11505
11506 // Call Java Static Instruction (method handle version)
11507 // Note: If this code changes, the corresponding ret_addr_offset() and
11508 // compute_padding() functions will have to be adjusted.
11509 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11510 match(CallStaticJava);
11511 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11512 effect(USE meth);
11513 // RBP is saved by all callees (for interpreter stack correction).
11514 // We use it here for a similar purpose, in {preserve,restore}_SP.
11515
11516 ins_cost(300);
11517 format %{ "call,static/MethodHandle " %}
11518 opcode(0xE8); /* E8 cd */
11519 ins_encode(preserve_SP,
11520 Java_Static_Call(meth),
11521 restore_SP,
11522 call_epilog);
11523 ins_pipe(pipe_slow);
11524 ins_alignment(4);
11525 %}
11526
11527 // Call Java Dynamic Instruction
11528 // Note: If this code changes, the corresponding ret_addr_offset() and
11529 // compute_padding() functions will have to be adjusted.
11530 instruct CallDynamicJavaDirect(method meth)
11531 %{
11532 match(CallDynamicJava);
11533 effect(USE meth);
11534
11535 ins_cost(300);
11536 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11537 "call,dynamic " %}
11538 opcode(0xE8); /* E8 cd */
11539 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11540 ins_pipe(pipe_slow);
11541 ins_alignment(4);
11542 %}
11543
11544 // Call Runtime Instruction
11545 instruct CallRuntimeDirect(method meth)
11546 %{
11547 match(CallRuntime);
11548 effect(USE meth);
11549
11550 ins_cost(300);
11551 format %{ "call,runtime " %}
11552 opcode(0xE8); /* E8 cd */
11553 ins_encode(Java_To_Runtime(meth));
11554 ins_pipe(pipe_slow);
11555 %}
11556
11557 // Call runtime without safepoint
11558 instruct CallLeafDirect(method meth)
11559 %{
11560 match(CallLeaf);
11561 effect(USE meth);
11562
11563 ins_cost(300);
11564 format %{ "call_leaf,runtime " %}
11565 opcode(0xE8); /* E8 cd */
11566 ins_encode(Java_To_Runtime(meth));
11567 ins_pipe(pipe_slow);
11568 %}
11569
11570 // Call runtime without safepoint
11571 instruct CallLeafNoFPDirect(method meth)
11572 %{
11573 match(CallLeafNoFP);
11574 effect(USE meth);
11575
11576 ins_cost(300);
11577 format %{ "call_leaf_nofp,runtime " %}
11578 opcode(0xE8); /* E8 cd */
11579 ins_encode(Java_To_Runtime(meth));
11580 ins_pipe(pipe_slow);
11581 %}
11582
11583 // Return Instruction
11584 // Remove the return address & jump to it.
11585 // Notice: We always emit a nop after a ret to make sure there is room
11586 // for safepoint patching
11587 instruct Ret()
11588 %{
11589 match(Return);
11590
11591 format %{ "ret" %}
11592 opcode(0xC3);
11593 ins_encode(OpcP);
11594 ins_pipe(pipe_jmp);
11595 %}
11596
11597 // Tail Call; Jump from runtime stub to Java code.
11598 // Also known as an 'interprocedural jump'.
11599 // Target of jump will eventually return to caller.
11600 // TailJump below removes the return address.
11601 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11602 %{
11603 match(TailCall jump_target method_oop);
11604
11605 ins_cost(300);
11606 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11607 opcode(0xFF, 0x4); /* Opcode FF /4 */
11608 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11609 ins_pipe(pipe_jmp);
11610 %}
11611
11612 // Tail Jump; remove the return address; jump to target.
11613 // TailCall above leaves the return address around.
11614 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11615 %{
11616 match(TailJump jump_target ex_oop);
11617
11618 ins_cost(300);
11619 format %{ "popq rdx\t# pop return address\n\t"
11620 "jmp $jump_target" %}
11621 opcode(0xFF, 0x4); /* Opcode FF /4 */
11622 ins_encode(Opcode(0x5a), // popq rdx
11623 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11624 ins_pipe(pipe_jmp);
11625 %}
11626
11627 // Create exception oop: created by stack-crawling runtime code.
11628 // Created exception is now available to this handler, and is setup
11629 // just prior to jumping to this handler. No code emitted.
11630 instruct CreateException(rax_RegP ex_oop)
11631 %{
11632 match(Set ex_oop (CreateEx));
11633
11634 size(0);
11635 // use the following format syntax
11636 format %{ "# exception oop is in rax; no code emitted" %}
11637 ins_encode();
11638 ins_pipe(empty);
11639 %}
11640
11641 // Rethrow exception:
11642 // The exception oop will come in the first argument position.
11643 // Then JUMP (not call) to the rethrow stub code.
11644 instruct RethrowException()
11645 %{
11646 match(Rethrow);
11647
11648 // use the following format syntax
11649 format %{ "jmp rethrow_stub" %}
11650 ins_encode(enc_rethrow);
11651 ins_pipe(pipe_jmp);
11652 %}
11653
11654
11655 // ============================================================================
11656 // This name is KNOWN by the ADLC and cannot be changed.
11657 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11658 // for this guy.
11659 instruct tlsLoadP(r15_RegP dst) %{
11660 match(Set dst (ThreadLocal));
11661 effect(DEF dst);
11662
11663 size(0);
11664 format %{ "# TLS is in R15" %}
11665 ins_encode( /*empty encoding*/ );
11666 ins_pipe(ialu_reg_reg);
11667 %}
11668
11669
11670 //----------PEEPHOLE RULES-----------------------------------------------------
11671 // These must follow all instruction definitions as they use the names
11672 // defined in the instructions definitions.
11673 //
11674 // peepmatch ( root_instr_name [preceding_instruction]* );
11675 //
11676 // peepconstraint %{
11677 // (instruction_number.operand_name relational_op instruction_number.operand_name
11678 // [, ...] );
11679 // // instruction numbers are zero-based using left to right order in peepmatch
11680 //
11681 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11682 // // provide an instruction_number.operand_name for each operand that appears
11683 // // in the replacement instruction's match rule
11684 //
11685 // ---------VM FLAGS---------------------------------------------------------
11686 //
11687 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11688 //
11689 // Each peephole rule is given an identifying number starting with zero and
11690 // increasing by one in the order seen by the parser. An individual peephole
11691 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11692 // on the command-line.
11693 //
11694 // ---------CURRENT LIMITATIONS----------------------------------------------
11695 //
11696 // Only match adjacent instructions in same basic block
11697 // Only equality constraints
11698 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11699 // Only one replacement instruction
11700 //
11701 // ---------EXAMPLE----------------------------------------------------------
11702 //
11703 // // pertinent parts of existing instructions in architecture description
11704 // instruct movI(rRegI dst, rRegI src)
11705 // %{
11706 // match(Set dst (CopyI src));
11707 // %}
11708 //
11709 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11710 // %{
11711 // match(Set dst (AddI dst src));
11712 // effect(KILL cr);
11713 // %}
11714 //
11715 // // Change (inc mov) to lea
11716 // peephole %{
11717 // // increment preceeded by register-register move
11718 // peepmatch ( incI_rReg movI );
11719 // // require that the destination register of the increment
11720 // // match the destination register of the move
11721 // peepconstraint ( 0.dst == 1.dst );
11722 // // construct a replacement instruction that sets
11723 // // the destination to ( move's source register + one )
11724 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11725 // %}
11726 //
11727
11728 // Implementation no longer uses movX instructions since
11729 // machine-independent system no longer uses CopyX nodes.
11730 //
11731 // peephole
11732 // %{
11733 // peepmatch (incI_rReg movI);
11734 // peepconstraint (0.dst == 1.dst);
11735 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11736 // %}
11737
11738 // peephole
11739 // %{
11740 // peepmatch (decI_rReg movI);
11741 // peepconstraint (0.dst == 1.dst);
11742 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11743 // %}
11744
11745 // peephole
11746 // %{
11747 // peepmatch (addI_rReg_imm movI);
11748 // peepconstraint (0.dst == 1.dst);
11749 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11750 // %}
11751
11752 // peephole
11753 // %{
11754 // peepmatch (incL_rReg movL);
11755 // peepconstraint (0.dst == 1.dst);
11756 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11757 // %}
11758
11759 // peephole
11760 // %{
11761 // peepmatch (decL_rReg movL);
11762 // peepconstraint (0.dst == 1.dst);
11763 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11764 // %}
11765
11766 // peephole
11767 // %{
11768 // peepmatch (addL_rReg_imm movL);
11769 // peepconstraint (0.dst == 1.dst);
11770 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11771 // %}
11772
11773 // peephole
11774 // %{
11775 // peepmatch (addP_rReg_imm movP);
11776 // peepconstraint (0.dst == 1.dst);
11777 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11778 // %}
11779
11780 // // Change load of spilled value to only a spill
11781 // instruct storeI(memory mem, rRegI src)
11782 // %{
11783 // match(Set mem (StoreI mem src));
11784 // %}
11785 //
11786 // instruct loadI(rRegI dst, memory mem)
11787 // %{
11788 // match(Set dst (LoadI mem));
11789 // %}
11790 //
11791
11792 peephole
11793 %{
11794 peepmatch (loadI storeI);
11795 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11796 peepreplace (storeI(1.mem 1.mem 1.src));
11797 %}
11798
11799 peephole
11800 %{
11801 peepmatch (loadL storeL);
11802 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11803 peepreplace (storeL(1.mem 1.mem 1.src));
11804 %}
11805
11806 //----------SMARTSPILL RULES---------------------------------------------------
11807 // These must follow all instruction definitions as they use the names
11808 // defined in the instructions definitions.