Print this page
| Split |
Close |
| Expand all |
| Collapse all |
--- old/src/cpu/sparc/vm/vm_version_sparc.cpp
+++ new/src/cpu/sparc/vm/vm_version_sparc.cpp
1 1 /*
2 - * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
2 + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #include "precompiled.hpp"
26 26 #include "assembler_sparc.inline.hpp"
27 27 #include "memory/resourceArea.hpp"
28 28 #include "runtime/java.hpp"
29 29 #include "runtime/stubCodeGenerator.hpp"
30 30 #include "vm_version_sparc.hpp"
31 31 #ifdef TARGET_OS_FAMILY_linux
32 32 # include "os_linux.inline.hpp"
33 33 #endif
34 34 #ifdef TARGET_OS_FAMILY_solaris
35 35 # include "os_solaris.inline.hpp"
36 36 #endif
37 37
38 38 int VM_Version::_features = VM_Version::unknown_m;
39 39 const char* VM_Version::_features_str = "";
40 40
41 41 void VM_Version::initialize() {
42 42 _features = determine_features();
43 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 45 PrefetchFieldsAhead = prefetch_fields_ahead();
46 46
47 47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
48 48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
49 49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
50 50
51 51 // Allocation prefetch settings
52 52 intx cache_line_size = prefetch_data_size();
53 53 if( cache_line_size > AllocatePrefetchStepSize )
54 54 AllocatePrefetchStepSize = cache_line_size;
55 55
56 56 assert(AllocatePrefetchLines > 0, "invalid value");
57 57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
58 58 AllocatePrefetchLines = 3;
59 59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 61 AllocateInstancePrefetchLines = 1;
62 62
63 63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 64 AllocatePrefetchStyle = allocate_prefetch_style();
65 65
66 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 67 (AllocatePrefetchDistance > 0), "invalid value");
68 68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 69 (AllocatePrefetchDistance <= 0)) {
70 70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 71 }
72 72
73 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 74 warning("BIS instructions are not available on this CPU");
75 75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 76 }
77 77
78 78 if (has_v9()) {
79 79 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
80 80 if (ArraycopySrcPrefetchDistance >= 4096)
81 81 ArraycopySrcPrefetchDistance = 4064;
82 82 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
83 83 if (ArraycopyDstPrefetchDistance >= 4096)
84 84 ArraycopyDstPrefetchDistance = 4064;
85 85 } else {
86 86 if (ArraycopySrcPrefetchDistance > 0) {
87 87 warning("prefetch instructions are not available on this CPU");
88 88 FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0);
89 89 }
90 90 if (ArraycopyDstPrefetchDistance > 0) {
91 91 warning("prefetch instructions are not available on this CPU");
92 92 FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0);
93 93 }
94 94 }
95 95
96 96 UseSSE = 0; // Only on x86 and x64
97 97
98 98 _supports_cx8 = has_v9();
99 99
100 100 if (is_niagara()) {
101 101 // Indirect branch is the same cost as direct
102 102 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
103 103 FLAG_SET_DEFAULT(UseInlineCaches, false);
104 104 }
105 105 // Align loops on a single instruction boundary.
106 106 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
107 107 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
108 108 }
109 109 // When using CMS, we cannot use memset() in BOT updates because
110 110 // the sun4v/CMT version in libc_psr uses BIS which exposes
111 111 // "phantom zeros" to concurrent readers. See 6948537.
112 112 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
113 113 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
114 114 }
115 115 #ifdef _LP64
116 116 // 32-bit oops don't make sense for the 64-bit VM on sparc
117 117 // since the 32-bit VM has the same registers and smaller objects.
118 118 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
119 119 #endif // _LP64
120 120 #ifdef COMPILER2
121 121 // Indirect branch is the same cost as direct
122 122 if (FLAG_IS_DEFAULT(UseJumpTables)) {
123 123 FLAG_SET_DEFAULT(UseJumpTables, true);
124 124 }
125 125 // Single-issue, so entry and loop tops are
126 126 // aligned on a single instruction boundary
127 127 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
128 128 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
129 129 }
130 130 if (is_niagara_plus()) {
131 131 if (has_blk_init() && UseTLAB &&
132 132 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
133 133 // Use BIS instruction for TLAB allocation prefetch.
134 134 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
135 135 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
136 136 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
137 137 }
138 138 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
139 139 // Use smaller prefetch distance with BIS
140 140 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
141 141 }
142 142 }
143 143 if (is_T4()) {
144 144 // Double number of prefetched cache lines on T4
145 145 // since L2 cache line size is smaller (32 bytes).
146 146 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
147 147 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
148 148 }
149 149 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
150 150 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
151 151 }
152 152 }
153 153 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
154 154 // Use different prefetch distance without BIS
155 155 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
156 156 }
157 157 if (AllocatePrefetchInstr == 1) {
158 158 // Need a space at the end of TLAB for BIS since it
159 159 // will fault when accessing memory outside of heap.
160 160
161 161 // +1 for rounding up to next cache line, +1 to be safe
162 162 int lines = AllocatePrefetchLines + 2;
163 163 int step_size = AllocatePrefetchStepSize;
164 164 int distance = AllocatePrefetchDistance;
165 165 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
166 166 }
167 167 }
168 168 #endif
169 169 }
170 170
171 171 // Use hardware population count instruction if available.
172 172 if (has_hardware_popc()) {
173 173 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
174 174 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
175 175 }
176 176 } else if (UsePopCountInstruction) {
177 177 warning("POPC instruction is not available on this CPU");
178 178 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
179 179 }
180 180
181 181 // T4 and newer Sparc cpus have new compare and branch instruction.
182 182 if (has_cbcond()) {
183 183 if (FLAG_IS_DEFAULT(UseCBCond)) {
184 184 FLAG_SET_DEFAULT(UseCBCond, true);
185 185 }
186 186 } else if (UseCBCond) {
187 187 warning("CBCOND instruction is not available on this CPU");
188 188 FLAG_SET_DEFAULT(UseCBCond, false);
189 189 }
190 190
191 191 assert(BlockZeroingLowLimit > 0, "invalid value");
192 192 if (has_block_zeroing()) {
193 193 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
194 194 FLAG_SET_DEFAULT(UseBlockZeroing, true);
195 195 }
196 196 } else if (UseBlockZeroing) {
197 197 warning("BIS zeroing instructions are not available on this CPU");
198 198 FLAG_SET_DEFAULT(UseBlockZeroing, false);
199 199 }
200 200
201 201 assert(BlockCopyLowLimit > 0, "invalid value");
202 202 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
203 203 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
|
↓ open down ↓ |
191 lines elided |
↑ open up ↑ |
204 204 FLAG_SET_DEFAULT(UseBlockCopy, true);
205 205 }
206 206 } else if (UseBlockCopy) {
207 207 warning("BIS instructions are not available or expensive on this CPU");
208 208 FLAG_SET_DEFAULT(UseBlockCopy, false);
209 209 }
210 210
211 211 #ifdef COMPILER2
212 212 // T4 and newer Sparc cpus have fast RDPC.
213 213 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
214 -// FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
214 + FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
215 215 }
216 216
217 217 // Currently not supported anywhere.
218 218 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
219 219
220 220 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
221 221 #endif
222 222
223 223 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
224 224 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
225 225
226 226 char buf[512];
227 227 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
228 228 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
229 229 (has_hardware_popc() ? ", popc" : ""),
230 230 (has_vis1() ? ", vis1" : ""),
231 231 (has_vis2() ? ", vis2" : ""),
232 232 (has_vis3() ? ", vis3" : ""),
233 233 (has_blk_init() ? ", blk_init" : ""),
234 234 (has_cbcond() ? ", cbcond" : ""),
235 235 (is_ultra3() ? ", ultra3" : ""),
236 236 (is_sun4v() ? ", sun4v" : ""),
237 237 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
238 238 (is_sparc64() ? ", sparc64" : ""),
239 239 (!has_hardware_mul32() ? ", no-mul32" : ""),
240 240 (!has_hardware_div32() ? ", no-div32" : ""),
241 241 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
242 242
243 243 // buf is started with ", " or is empty
244 244 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
245 245
246 246 // UseVIS is set to the smallest of what hardware supports and what
247 247 // the command line requires. I.e., you cannot set UseVIS to 3 on
248 248 // older UltraSparc which do not support it.
249 249 if (UseVIS > 3) UseVIS=3;
250 250 if (UseVIS < 0) UseVIS=0;
251 251 if (!has_vis3()) // Drop to 2 if no VIS3 support
252 252 UseVIS = MIN2((intx)2,UseVIS);
253 253 if (!has_vis2()) // Drop to 1 if no VIS2 support
254 254 UseVIS = MIN2((intx)1,UseVIS);
255 255 if (!has_vis1()) // Drop to 0 if no VIS1 support
256 256 UseVIS = 0;
257 257
258 258 #ifndef PRODUCT
259 259 if (PrintMiscellaneous && Verbose) {
260 260 tty->print("Allocation");
261 261 if (AllocatePrefetchStyle <= 0) {
262 262 tty->print_cr(": no prefetching");
263 263 } else {
264 264 tty->print(" prefetching: ");
265 265 if (AllocatePrefetchInstr == 0) {
266 266 tty->print("PREFETCH");
267 267 } else if (AllocatePrefetchInstr == 1) {
268 268 tty->print("BIS");
269 269 }
270 270 if (AllocatePrefetchLines > 1) {
271 271 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
272 272 } else {
273 273 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
274 274 }
275 275 }
276 276 if (PrefetchCopyIntervalInBytes > 0) {
277 277 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
278 278 }
279 279 if (PrefetchScanIntervalInBytes > 0) {
280 280 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
281 281 }
282 282 if (PrefetchFieldsAhead > 0) {
283 283 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
284 284 }
285 285 }
286 286 #endif // PRODUCT
287 287 }
288 288
289 289 void VM_Version::print_features() {
290 290 tty->print_cr("Version:%s", cpu_features());
291 291 }
292 292
293 293 int VM_Version::determine_features() {
294 294 if (UseV8InstrsOnly) {
295 295 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
296 296 return generic_v8_m;
297 297 }
298 298
299 299 int features = platform_features(unknown_m); // platform_features() is os_arch specific
300 300
301 301 if (features == unknown_m) {
302 302 features = generic_v9_m;
303 303 warning("Cannot recognize SPARC version. Default to V9");
304 304 }
305 305
306 306 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
307 307 if (UseNiagaraInstrs) { // Force code generation for Niagara
308 308 if (is_T_family(features)) {
309 309 // Happy to accomodate...
310 310 } else {
311 311 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
312 312 features |= T_family_m;
313 313 }
314 314 } else {
315 315 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
316 316 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
317 317 features &= ~(T_family_m | T1_model_m);
318 318 } else {
319 319 // Happy to accomodate...
320 320 }
321 321 }
322 322
323 323 return features;
324 324 }
325 325
326 326 static int saved_features = 0;
327 327
328 328 void VM_Version::allow_all() {
329 329 saved_features = _features;
330 330 _features = all_features_m;
331 331 }
332 332
333 333 void VM_Version::revert() {
334 334 _features = saved_features;
335 335 }
336 336
337 337 unsigned int VM_Version::calc_parallel_worker_threads() {
338 338 unsigned int result;
339 339 if (is_niagara_plus()) {
340 340 result = nof_parallel_worker_threads(5, 16, 8);
341 341 } else {
342 342 result = nof_parallel_worker_threads(5, 8, 8);
343 343 }
344 344 return result;
345 345 }
|
↓ open down ↓ |
121 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX