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--- old/src/share/vm/opto/machnode.cpp
+++ new/src/share/vm/opto/machnode.cpp
1 1 /*
2 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #include "precompiled.hpp"
26 26 #include "gc_interface/collectedHeap.hpp"
27 27 #include "opto/machnode.hpp"
28 28 #include "opto/regalloc.hpp"
29 29
30 30 //=============================================================================
31 31 // Return the value requested
32 32 // result register lookup, corresponding to int_format
33 33 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
34 34 return (int)ra_->get_encode(node);
35 35 }
36 36 // input register lookup, corresponding to ext_format
37 37 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
38 38 return (int)(ra_->get_encode(node->in(idx)));
39 39 }
40 40 intptr_t MachOper::constant() const { return 0x00; }
41 41 bool MachOper::constant_is_oop() const { return false; }
42 42 jdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; }
43 43 jfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; }
44 44 jlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; }
45 45 TypeOopPtr *MachOper::oop() const { return NULL; }
46 46 int MachOper::ccode() const { return 0x00; }
47 47 // A zero, default, indicates this value is not needed.
48 48 // May need to lookup the base register, as done in int_ and ext_format
49 49 int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
50 50 int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
51 51 int MachOper::scale() const { return 0x00; }
52 52 int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
53 53 int MachOper::constant_disp() const { return 0; }
54 54 int MachOper::base_position() const { return -1; } // no base input
55 55 int MachOper::index_position() const { return -1; } // no index input
56 56 // Check for PC-Relative displacement
57 57 bool MachOper::disp_is_oop() const { return false; }
58 58 // Return the label
59 59 Label* MachOper::label() const { ShouldNotReachHere(); return 0; }
60 60 intptr_t MachOper::method() const { ShouldNotReachHere(); return 0; }
61 61
62 62
63 63 //------------------------------negate-----------------------------------------
64 64 // Negate conditional branches. Error for non-branch operands
65 65 void MachOper::negate() {
66 66 ShouldNotCallThis();
67 67 }
68 68
69 69 //-----------------------------type--------------------------------------------
70 70 const Type *MachOper::type() const {
71 71 return Type::BOTTOM;
72 72 }
73 73
74 74 //------------------------------in_RegMask-------------------------------------
75 75 const RegMask *MachOper::in_RegMask(int index) const {
76 76 ShouldNotReachHere();
77 77 return NULL;
78 78 }
79 79
80 80 //------------------------------dump_spec--------------------------------------
81 81 // Print any per-operand special info
82 82 #ifndef PRODUCT
83 83 void MachOper::dump_spec(outputStream *st) const { }
84 84 #endif
85 85
86 86 //------------------------------hash-------------------------------------------
87 87 // Print any per-operand special info
88 88 uint MachOper::hash() const {
89 89 ShouldNotCallThis();
90 90 return 5;
91 91 }
92 92
93 93 //------------------------------cmp--------------------------------------------
94 94 // Print any per-operand special info
95 95 uint MachOper::cmp( const MachOper &oper ) const {
96 96 ShouldNotCallThis();
97 97 return opcode() == oper.opcode();
98 98 }
99 99
100 100 //------------------------------hash-------------------------------------------
101 101 // Print any per-operand special info
102 102 uint labelOper::hash() const {
103 103 return _block_num;
104 104 }
105 105
106 106 //------------------------------cmp--------------------------------------------
107 107 // Print any per-operand special info
108 108 uint labelOper::cmp( const MachOper &oper ) const {
109 109 return (opcode() == oper.opcode()) && (_label == oper.label());
110 110 }
111 111
112 112 //------------------------------hash-------------------------------------------
113 113 // Print any per-operand special info
114 114 uint methodOper::hash() const {
115 115 return (uint)_method;
116 116 }
117 117
118 118 //------------------------------cmp--------------------------------------------
119 119 // Print any per-operand special info
120 120 uint methodOper::cmp( const MachOper &oper ) const {
121 121 return (opcode() == oper.opcode()) && (_method == oper.method());
122 122 }
123 123
124 124
125 125 //=============================================================================
126 126 //------------------------------MachNode---------------------------------------
127 127
128 128 //------------------------------emit-------------------------------------------
129 129 void MachNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
130 130 #ifdef ASSERT
131 131 tty->print("missing MachNode emit function: ");
132 132 dump();
133 133 #endif
134 134 ShouldNotCallThis();
135 135 }
136 136
137 137 //------------------------------size-------------------------------------------
138 138 // Size of instruction in bytes
139 139 uint MachNode::size(PhaseRegAlloc *ra_) const {
140 140 // If a virtual was not defined for this specific instruction,
141 141 // Call the helper which finds the size by emitting the bits.
142 142 return MachNode::emit_size(ra_);
143 143 }
144 144
145 145 //------------------------------size-------------------------------------------
146 146 // Helper function that computes size by emitting code
147 147 uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
148 148 // Emit into a trash buffer and count bytes emitted.
149 149 assert(ra_ == ra_->C->regalloc(), "sanity");
150 150 return ra_->C->scratch_emit_size(this);
151 151 }
152 152
153 153
154 154
155 155 //------------------------------hash-------------------------------------------
156 156 uint MachNode::hash() const {
157 157 uint no = num_opnds();
158 158 uint sum = rule();
159 159 for( uint i=0; i<no; i++ )
160 160 sum += _opnds[i]->hash();
161 161 return sum+Node::hash();
162 162 }
163 163
164 164 //-----------------------------cmp---------------------------------------------
165 165 uint MachNode::cmp( const Node &node ) const {
166 166 MachNode& n = *((Node&)node).as_Mach();
167 167 uint no = num_opnds();
168 168 if( no != n.num_opnds() ) return 0;
169 169 if( rule() != n.rule() ) return 0;
170 170 for( uint i=0; i<no; i++ ) // All operands must match
171 171 if( !_opnds[i]->cmp( *n._opnds[i] ) )
172 172 return 0; // mis-matched operands
173 173 return 1; // match
174 174 }
175 175
176 176 // Return an equivalent instruction using memory for cisc_operand position
177 177 MachNode *MachNode::cisc_version(int offset, Compile* C) {
178 178 ShouldNotCallThis();
179 179 return NULL;
180 180 }
181 181
182 182 void MachNode::use_cisc_RegMask() {
183 183 ShouldNotReachHere();
184 184 }
185 185
186 186
187 187 //-----------------------------in_RegMask--------------------------------------
188 188 const RegMask &MachNode::in_RegMask( uint idx ) const {
189 189 uint numopnds = num_opnds(); // Virtual call for number of operands
190 190 uint skipped = oper_input_base(); // Sum of leaves skipped so far
191 191 if( idx < skipped ) {
192 192 assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
193 193 assert( idx == 1, "expected base ptr here" );
194 194 // debug info can be anywhere
195 195 return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
196 196 }
197 197 uint opcnt = 1; // First operand
198 198 uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
199 199 while( idx >= skipped+num_edges ) {
200 200 skipped += num_edges;
201 201 opcnt++; // Bump operand count
202 202 assert( opcnt < numopnds, "Accessing non-existent operand" );
203 203 num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
204 204 }
205 205
206 206 const RegMask *rm = cisc_RegMask();
207 207 if( rm == NULL || (int)opcnt != cisc_operand() ) {
208 208 rm = _opnds[opcnt]->in_RegMask(idx-skipped);
209 209 }
210 210 return *rm;
211 211 }
212 212
213 213 //-----------------------------memory_inputs--------------------------------
214 214 const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
215 215 const MachOper* oper = memory_operand();
216 216
217 217 if (oper == (MachOper*)-1) {
218 218 base = NodeSentinel;
219 219 index = NodeSentinel;
220 220 } else {
221 221 base = NULL;
222 222 index = NULL;
223 223 if (oper != NULL) {
224 224 // It has a unique memory operand. Find its index.
225 225 int oper_idx = num_opnds();
226 226 while (--oper_idx >= 0) {
227 227 if (_opnds[oper_idx] == oper) break;
228 228 }
229 229 int oper_pos = operand_index(oper_idx);
230 230 int base_pos = oper->base_position();
231 231 if (base_pos >= 0) {
232 232 base = _in[oper_pos+base_pos];
233 233 }
234 234 int index_pos = oper->index_position();
235 235 if (index_pos >= 0) {
236 236 index = _in[oper_pos+index_pos];
237 237 }
238 238 }
239 239 }
240 240
241 241 return oper;
242 242 }
243 243
244 244 //-----------------------------get_base_and_disp----------------------------
245 245 const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
246 246
247 247 // Find the memory inputs using our helper function
248 248 Node* base;
249 249 Node* index;
250 250 const MachOper* oper = memory_inputs(base, index);
251 251
252 252 if (oper == NULL) {
253 253 // Base has been set to NULL
254 254 offset = 0;
255 255 } else if (oper == (MachOper*)-1) {
256 256 // Base has been set to NodeSentinel
257 257 // There is not a unique memory use here. We will fall to AliasIdxBot.
258 258 offset = Type::OffsetBot;
259 259 } else {
260 260 // Base may be NULL, even if offset turns out to be != 0
261 261
262 262 intptr_t disp = oper->constant_disp();
263 263 int scale = oper->scale();
264 264 // Now we have collected every part of the ADLC MEMORY_INTER.
265 265 // See if it adds up to a base + offset.
266 266 if (index != NULL) {
267 267 const Type* t_index = index->bottom_type();
268 268 if (t_index->isa_narrowoop()) { // EncodeN, LoadN, LoadConN, LoadNKlass.
269 269 // Memory references through narrow oops have a
270 270 // funny base so grab the type from the index:
271 271 // [R12 + narrow_oop_reg<<3 + offset]
272 272 assert(base == NULL, "Memory references through narrow oops have no base");
273 273 offset = disp;
274 274 adr_type = t_index->make_ptr()->add_offset(offset);
275 275 return NULL;
276 276 } else if (!index->is_Con()) {
277 277 disp = Type::OffsetBot;
278 278 } else if (disp != Type::OffsetBot) {
279 279 const TypeX* ti = t_index->isa_intptr_t();
280 280 if (ti == NULL) {
281 281 disp = Type::OffsetBot; // a random constant??
282 282 } else {
283 283 disp += ti->get_con() << scale;
284 284 }
285 285 }
286 286 }
287 287 offset = disp;
288 288
289 289 // In i486.ad, indOffset32X uses base==RegI and disp==RegP,
290 290 // this will prevent alias analysis without the following support:
291 291 // Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
292 292 // Add the offset determined by the "base", or use Type::OffsetBot.
293 293 if( adr_type == TYPE_PTR_SENTINAL ) {
294 294 const TypePtr *t_disp = oper->disp_as_type(); // only !NULL for indOffset32X
295 295 if (t_disp != NULL) {
296 296 offset = Type::OffsetBot;
297 297 const Type* t_base = base->bottom_type();
298 298 if (t_base->isa_intptr_t()) {
299 299 const TypeX *t_offset = t_base->is_intptr_t();
300 300 if( t_offset->is_con() ) {
301 301 offset = t_offset->get_con();
302 302 }
303 303 }
304 304 adr_type = t_disp->add_offset(offset);
305 305 } else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) {
306 306 // Use ideal type if it is oop ptr.
307 307 const TypePtr *tp = oper->type()->isa_ptr();
308 308 if( tp != NULL) {
309 309 adr_type = tp;
310 310 }
311 311 }
312 312 }
313 313
314 314 }
315 315 return base;
316 316 }
317 317
318 318
319 319 //---------------------------------adr_type---------------------------------
320 320 const class TypePtr *MachNode::adr_type() const {
321 321 intptr_t offset = 0;
322 322 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
323 323 const Node *base = get_base_and_disp(offset, adr_type);
324 324 if( adr_type != TYPE_PTR_SENTINAL ) {
325 325 return adr_type; // get_base_and_disp has the answer
326 326 }
327 327
328 328 // Direct addressing modes have no base node, simply an indirect
329 329 // offset, which is always to raw memory.
330 330 // %%%%% Someday we'd like to allow constant oop offsets which
331 331 // would let Intel load from static globals in 1 instruction.
332 332 // Currently Intel requires 2 instructions and a register temp.
333 333 if (base == NULL) {
334 334 // NULL base, zero offset means no memory at all (a null pointer!)
335 335 if (offset == 0) {
336 336 return NULL;
337 337 }
338 338 // NULL base, any offset means any pointer whatever
339 339 if (offset == Type::OffsetBot) {
340 340 return TypePtr::BOTTOM;
341 341 }
342 342 // %%% make offset be intptr_t
343 343 assert(!Universe::heap()->is_in_reserved((oop)offset), "must be a raw ptr");
344 344 return TypeRawPtr::BOTTOM;
345 345 }
346 346
347 347 // base of -1 with no particular offset means all of memory
348 348 if (base == NodeSentinel) return TypePtr::BOTTOM;
349 349
350 350 const Type* t = base->bottom_type();
351 351 if (UseCompressedOops && Universe::narrow_oop_shift() == 0) {
352 352 // 32-bit unscaled narrow oop can be the base of any address expression
353 353 t = t->make_ptr();
354 354 }
355 355 if (t->isa_intptr_t() && offset != 0 && offset != Type::OffsetBot) {
356 356 // We cannot assert that the offset does not look oop-ish here.
357 357 // Depending on the heap layout the cardmark base could land
358 358 // inside some oopish region. It definitely does for Win2K.
359 359 // The sum of cardmark-base plus shift-by-9-oop lands outside
360 360 // the oop-ish area but we can't assert for that statically.
361 361 return TypeRawPtr::BOTTOM;
362 362 }
363 363
364 364 const TypePtr *tp = t->isa_ptr();
365 365
366 366 // be conservative if we do not recognize the type
367 367 if (tp == NULL) {
368 368 assert(false, "this path may produce not optimal code");
369 369 return TypePtr::BOTTOM;
370 370 }
371 371 assert(tp->base() != Type::AnyPtr, "not a bare pointer");
372 372
373 373 return tp->add_offset(offset);
374 374 }
375 375
376 376
377 377 //-----------------------------operand_index---------------------------------
378 378 int MachNode::operand_index( uint operand ) const {
379 379 if( operand < 1 ) return -1;
380 380 assert(operand < num_opnds(), "oob");
381 381 if( _opnds[operand]->num_edges() == 0 ) return -1;
382 382
383 383 uint skipped = oper_input_base(); // Sum of leaves skipped so far
384 384 for (uint opcnt = 1; opcnt < operand; opcnt++) {
385 385 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
386 386 skipped += num_edges;
387 387 }
388 388 return skipped;
389 389 }
390 390
391 391
392 392 //------------------------------peephole---------------------------------------
393 393 // Apply peephole rule(s) to this instruction
394 394 MachNode *MachNode::peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C ) {
395 395 return NULL;
396 396 }
397 397
398 398 //------------------------------add_case_label---------------------------------
399 399 // Adds the label for the case
400 400 void MachNode::add_case_label( int index_num, Label* blockLabel) {
401 401 ShouldNotCallThis();
402 402 }
403 403
404 404 //------------------------------method_set-------------------------------------
405 405 // Set the absolute address of a method
406 406 void MachNode::method_set( intptr_t addr ) {
407 407 ShouldNotCallThis();
408 408 }
409 409
410 410 //------------------------------rematerialize----------------------------------
411 411 bool MachNode::rematerialize() const {
412 412 // Temps are always rematerializable
413 413 if (is_MachTemp()) return true;
414 414
415 415 uint r = rule(); // Match rule
416 416 if( r < Matcher::_begin_rematerialize ||
417 417 r >= Matcher::_end_rematerialize )
418 418 return false;
419 419
420 420 // For 2-address instructions, the input live range is also the output
421 421 // live range. Remateralizing does not make progress on the that live range.
422 422 if( two_adr() ) return false;
423 423
424 424 // Check for rematerializing float constants, or not
425 425 if( !Matcher::rematerialize_float_constants ) {
426 426 int op = ideal_Opcode();
427 427 if( op == Op_ConF || op == Op_ConD )
428 428 return false;
429 429 }
430 430
431 431 // Defining flags - can't spill these! Must remateralize.
432 432 if( ideal_reg() == Op_RegFlags )
433 433 return true;
434 434
435 435 // Stretching lots of inputs - don't do it.
436 436 if( req() > 2 )
437 437 return false;
438 438
439 439 // Don't remateralize somebody with bound inputs - it stretches a
440 440 // fixed register lifetime.
441 441 uint idx = oper_input_base();
442 442 if( req() > idx ) {
443 443 const RegMask &rm = in_RegMask(idx);
444 444 if( rm.is_bound1() || rm.is_bound2() )
445 445 return false;
446 446 }
447 447
448 448 return true;
449 449 }
450 450
451 451 #ifndef PRODUCT
452 452 //------------------------------dump_spec--------------------------------------
453 453 // Print any per-operand special info
454 454 void MachNode::dump_spec(outputStream *st) const {
455 455 uint cnt = num_opnds();
456 456 for( uint i=0; i<cnt; i++ )
457 457 _opnds[i]->dump_spec(st);
458 458 const TypePtr *t = adr_type();
459 459 if( t ) {
460 460 Compile* C = Compile::current();
461 461 if( C->alias_type(t)->is_volatile() )
462 462 st->print(" Volatile!");
463 463 }
464 464 }
465 465
466 466 //------------------------------dump_format------------------------------------
467 467 // access to virtual
468 468 void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
469 469 format(ra, st); // access to virtual
470 470 }
471 471 #endif
472 472
473 473 //=============================================================================
474 474 #ifndef PRODUCT
475 475 void MachTypeNode::dump_spec(outputStream *st) const {
476 476 _bottom_type->dump_on(st);
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477 477 }
478 478 #endif
479 479
480 480
481 481 //=============================================================================
482 482 int MachConstantNode::constant_offset() {
483 483 int offset = _constant.offset();
484 484 // Bind the offset lazily.
485 485 if (offset == -1) {
486 486 Compile::ConstantTable& constant_table = Compile::current()->constant_table();
487 + // If called from Compile::scratch_emit_size assume the worst-case
488 + // for load offsets: half the constant table size.
489 + // NOTE: Don't return or calculate the actual offset (which might
490 + // be zero) because that leads to problems with e.g. jumpXtnd on
491 + // some architectures (cf. add-optimization in SPARC jumpXtnd).
492 + if (Compile::current()->in_scratch_emit_size())
493 + return constant_table.size() / 2;
487 494 offset = constant_table.table_base_offset() + constant_table.find_offset(_constant);
488 495 _constant.set_offset(offset);
489 496 }
490 497 return offset;
491 498 }
492 499
493 500
494 501 //=============================================================================
495 502 #ifndef PRODUCT
496 503 void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
497 504 int reg = ra_->get_reg_first(in(1)->in(_vidx));
498 505 tty->print("%s %s", Name(), Matcher::regName[reg]);
499 506 }
500 507 #endif
501 508
502 509 void MachNullCheckNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
503 510 // only emits entries in the null-pointer exception handler table
504 511 }
505 512 void MachNullCheckNode::label_set(Label* label, uint block_num) {
506 513 // Nothing to emit
507 514 }
508 515 void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
509 516 // Nothing to emit
510 517 }
511 518
512 519 const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
513 520 if( idx == 0 ) return RegMask::Empty;
514 521 else return in(1)->as_Mach()->out_RegMask();
515 522 }
516 523
517 524 //=============================================================================
518 525 const Type *MachProjNode::bottom_type() const {
519 526 if( _ideal_reg == fat_proj ) return Type::BOTTOM;
520 527 // Try the normal mechanism first
521 528 const Type *t = in(0)->bottom_type();
522 529 if( t->base() == Type::Tuple ) {
523 530 const TypeTuple *tt = t->is_tuple();
524 531 if (_con < tt->cnt())
525 532 return tt->field_at(_con);
526 533 }
527 534 // Else use generic type from ideal register set
528 535 assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
529 536 return Type::mreg2type[_ideal_reg];
530 537 }
531 538
532 539 const TypePtr *MachProjNode::adr_type() const {
533 540 if (bottom_type() == Type::MEMORY) {
534 541 // in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
535 542 const TypePtr* adr_type = in(0)->adr_type();
536 543 #ifdef ASSERT
537 544 if (!is_error_reported() && !Node::in_dump())
538 545 assert(adr_type != NULL, "source must have adr_type");
539 546 #endif
540 547 return adr_type;
541 548 }
542 549 assert(bottom_type()->base() != Type::Memory, "no other memories?");
543 550 return NULL;
544 551 }
545 552
546 553 #ifndef PRODUCT
547 554 void MachProjNode::dump_spec(outputStream *st) const {
548 555 ProjNode::dump_spec(st);
549 556 switch (_ideal_reg) {
550 557 case unmatched_proj: st->print("/unmatched"); break;
551 558 case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(); break;
552 559 }
553 560 }
554 561 #endif
555 562
556 563 //=============================================================================
557 564 #ifndef PRODUCT
558 565 void MachIfNode::dump_spec(outputStream *st) const {
559 566 st->print("P=%f, C=%f",_prob, _fcnt);
560 567 }
561 568 #endif
562 569
563 570 //=============================================================================
564 571 uint MachReturnNode::size_of() const { return sizeof(*this); }
565 572
566 573 //------------------------------Registers--------------------------------------
567 574 const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
568 575 return _in_rms[idx];
569 576 }
570 577
571 578 const TypePtr *MachReturnNode::adr_type() const {
572 579 // most returns and calls are assumed to consume & modify all of memory
573 580 // the matcher will copy non-wide adr_types from ideal originals
574 581 return _adr_type;
575 582 }
576 583
577 584 //=============================================================================
578 585 const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
579 586
580 587 //------------------------------Registers--------------------------------------
581 588 const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
582 589 // Values in the domain use the users calling convention, embodied in the
583 590 // _in_rms array of RegMasks.
584 591 if( idx < TypeFunc::Parms ) return _in_rms[idx];
585 592
586 593 if (SafePointNode::needs_polling_address_input() &&
587 594 idx == TypeFunc::Parms &&
588 595 ideal_Opcode() == Op_SafePoint) {
589 596 return MachNode::in_RegMask(idx);
590 597 }
591 598
592 599 // Values outside the domain represent debug info
593 600 return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
594 601 }
595 602
596 603
597 604 //=============================================================================
598 605
599 606 uint MachCallNode::cmp( const Node &n ) const
600 607 { return _tf == ((MachCallNode&)n)._tf; }
601 608 const Type *MachCallNode::bottom_type() const { return tf()->range(); }
602 609 const Type *MachCallNode::Value(PhaseTransform *phase) const { return tf()->range(); }
603 610
604 611 #ifndef PRODUCT
605 612 void MachCallNode::dump_spec(outputStream *st) const {
606 613 st->print("# ");
607 614 tf()->dump_on(st);
608 615 if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
609 616 if (jvms() != NULL) jvms()->dump_spec(st);
610 617 }
611 618 #endif
612 619
613 620
614 621 bool MachCallNode::return_value_is_used() const {
615 622 if (tf()->range()->cnt() == TypeFunc::Parms) {
616 623 // void return
617 624 return false;
618 625 }
619 626
620 627 // find the projection corresponding to the return value
621 628 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
622 629 Node *use = fast_out(i);
623 630 if (!use->is_Proj()) continue;
624 631 if (use->as_Proj()->_con == TypeFunc::Parms) {
625 632 return true;
626 633 }
627 634 }
628 635 return false;
629 636 }
630 637
631 638
632 639 //------------------------------Registers--------------------------------------
633 640 const RegMask &MachCallNode::in_RegMask( uint idx ) const {
634 641 // Values in the domain use the users calling convention, embodied in the
635 642 // _in_rms array of RegMasks.
636 643 if (idx < tf()->domain()->cnt()) return _in_rms[idx];
637 644 // Values outside the domain represent debug info
638 645 return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
639 646 }
640 647
641 648 //=============================================================================
642 649 uint MachCallJavaNode::size_of() const { return sizeof(*this); }
643 650 uint MachCallJavaNode::cmp( const Node &n ) const {
644 651 MachCallJavaNode &call = (MachCallJavaNode&)n;
645 652 return MachCallNode::cmp(call) && _method->equals(call._method);
646 653 }
647 654 #ifndef PRODUCT
648 655 void MachCallJavaNode::dump_spec(outputStream *st) const {
649 656 if (_method_handle_invoke)
650 657 st->print("MethodHandle ");
651 658 if (_method) {
652 659 _method->print_short_name(st);
653 660 st->print(" ");
654 661 }
655 662 MachCallNode::dump_spec(st);
656 663 }
657 664 #endif
658 665
659 666 //------------------------------Registers--------------------------------------
660 667 const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
661 668 // Values in the domain use the users calling convention, embodied in the
662 669 // _in_rms array of RegMasks.
663 670 if (idx < tf()->domain()->cnt()) return _in_rms[idx];
664 671 // Values outside the domain represent debug info
665 672 Matcher* m = Compile::current()->matcher();
666 673 // If this call is a MethodHandle invoke we have to use a different
667 674 // debugmask which does not include the register we use to save the
668 675 // SP over MH invokes.
669 676 RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
670 677 return *debugmask[in(idx)->ideal_reg()];
671 678 }
672 679
673 680 //=============================================================================
674 681 uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
675 682 uint MachCallStaticJavaNode::cmp( const Node &n ) const {
676 683 MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
677 684 return MachCallJavaNode::cmp(call) && _name == call._name;
678 685 }
679 686
680 687 //----------------------------uncommon_trap_request----------------------------
681 688 // If this is an uncommon trap, return the request code, else zero.
682 689 int MachCallStaticJavaNode::uncommon_trap_request() const {
683 690 if (_name != NULL && !strcmp(_name, "uncommon_trap")) {
684 691 return CallStaticJavaNode::extract_uncommon_trap_request(this);
685 692 }
686 693 return 0;
687 694 }
688 695
689 696 #ifndef PRODUCT
690 697 // Helper for summarizing uncommon_trap arguments.
691 698 void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
692 699 int trap_req = uncommon_trap_request();
693 700 if (trap_req != 0) {
694 701 char buf[100];
695 702 st->print("(%s)",
696 703 Deoptimization::format_trap_request(buf, sizeof(buf),
697 704 trap_req));
698 705 }
699 706 }
700 707
701 708 void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
702 709 st->print("Static ");
703 710 if (_name != NULL) {
704 711 st->print("wrapper for: %s", _name );
705 712 dump_trap_args(st);
706 713 st->print(" ");
707 714 }
708 715 MachCallJavaNode::dump_spec(st);
709 716 }
710 717 #endif
711 718
712 719 //=============================================================================
713 720 #ifndef PRODUCT
714 721 void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
715 722 st->print("Dynamic ");
716 723 MachCallJavaNode::dump_spec(st);
717 724 }
718 725 #endif
719 726 //=============================================================================
720 727 uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
721 728 uint MachCallRuntimeNode::cmp( const Node &n ) const {
722 729 MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
723 730 return MachCallNode::cmp(call) && !strcmp(_name,call._name);
724 731 }
725 732 #ifndef PRODUCT
726 733 void MachCallRuntimeNode::dump_spec(outputStream *st) const {
727 734 st->print("%s ",_name);
728 735 MachCallNode::dump_spec(st);
729 736 }
730 737 #endif
731 738 //=============================================================================
732 739 // A shared JVMState for all HaltNodes. Indicates the start of debug info
733 740 // is at TypeFunc::Parms. Only required for SOE register spill handling -
734 741 // to indicate where the stack-slot-only debug info inputs begin.
735 742 // There is no other JVM state needed here.
736 743 JVMState jvms_for_throw(0);
737 744 JVMState *MachHaltNode::jvms() const {
738 745 return &jvms_for_throw;
739 746 }
740 747
741 748 //=============================================================================
742 749 #ifndef PRODUCT
743 750 void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
744 751 st->print("B%d", _block_num);
745 752 }
746 753 #endif // PRODUCT
747 754
748 755 //=============================================================================
749 756 #ifndef PRODUCT
750 757 void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
751 758 st->print(INTPTR_FORMAT, _method);
752 759 }
753 760 #endif // PRODUCT
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