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--- old/src/cpu/sparc/vm/vm_version_sparc.cpp
+++ new/src/cpu/sparc/vm/vm_version_sparc.cpp
1 1 /*
2 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #include "precompiled.hpp"
26 26 #include "assembler_sparc.inline.hpp"
27 27 #include "memory/resourceArea.hpp"
28 28 #include "runtime/java.hpp"
29 29 #include "runtime/stubCodeGenerator.hpp"
30 30 #include "vm_version_sparc.hpp"
31 31 #ifdef TARGET_OS_FAMILY_linux
32 32 # include "os_linux.inline.hpp"
33 33 #endif
34 34 #ifdef TARGET_OS_FAMILY_solaris
35 35 # include "os_solaris.inline.hpp"
36 36 #endif
37 37
38 38 int VM_Version::_features = VM_Version::unknown_m;
39 39 const char* VM_Version::_features_str = "";
40 40
41 41 void VM_Version::initialize() {
42 42 _features = determine_features();
43 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 45 PrefetchFieldsAhead = prefetch_fields_ahead();
46 46
47 47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
48 48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
49 49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
50 50
51 51 // Allocation prefetch settings
52 52 intx cache_line_size = prefetch_data_size();
53 53 if( cache_line_size > AllocatePrefetchStepSize )
54 54 AllocatePrefetchStepSize = cache_line_size;
55 55
56 56 assert(AllocatePrefetchLines > 0, "invalid value");
57 57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
58 58 AllocatePrefetchLines = 3;
59 59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 61 AllocateInstancePrefetchLines = 1;
62 62
63 63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 64 AllocatePrefetchStyle = allocate_prefetch_style();
65 65
66 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 67 (AllocatePrefetchDistance > 0), "invalid value");
68 68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 69 (AllocatePrefetchDistance <= 0)) {
70 70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 71 }
72 72
73 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 74 warning("BIS instructions are not available on this CPU");
75 75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 76 }
77 77
78 78 if (has_v9()) {
79 79 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
80 80 if (ArraycopySrcPrefetchDistance >= 4096)
81 81 ArraycopySrcPrefetchDistance = 4064;
82 82 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
83 83 if (ArraycopyDstPrefetchDistance >= 4096)
84 84 ArraycopyDstPrefetchDistance = 4064;
85 85 } else {
86 86 if (ArraycopySrcPrefetchDistance > 0) {
87 87 warning("prefetch instructions are not available on this CPU");
88 88 FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0);
89 89 }
90 90 if (ArraycopyDstPrefetchDistance > 0) {
91 91 warning("prefetch instructions are not available on this CPU");
92 92 FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0);
93 93 }
94 94 }
95 95
96 96 UseSSE = 0; // Only on x86 and x64
97 97
98 98 _supports_cx8 = has_v9();
99 99 _supports_atomic_getset4 = true; // swap instruction
100 100
101 101 if (is_niagara()) {
102 102 // Indirect branch is the same cost as direct
103 103 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
104 104 FLAG_SET_DEFAULT(UseInlineCaches, false);
105 105 }
106 106 // Align loops on a single instruction boundary.
107 107 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
108 108 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
109 109 }
110 110 // When using CMS or G1, we cannot use memset() in BOT updates
111 111 // because the sun4v/CMT version in libc_psr uses BIS which
112 112 // exposes "phantom zeros" to concurrent readers. See 6948537.
113 113 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
114 114 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
115 115 }
116 116 #ifdef _LP64
117 117 // 32-bit oops don't make sense for the 64-bit VM on sparc
118 118 // since the 32-bit VM has the same registers and smaller objects.
119 119 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
120 120 #endif // _LP64
121 121 #ifdef COMPILER2
122 122 // Indirect branch is the same cost as direct
123 123 if (FLAG_IS_DEFAULT(UseJumpTables)) {
124 124 FLAG_SET_DEFAULT(UseJumpTables, true);
125 125 }
126 126 // Single-issue, so entry and loop tops are
127 127 // aligned on a single instruction boundary
128 128 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
129 129 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
130 130 }
131 131 if (is_niagara_plus()) {
132 132 if (has_blk_init() && UseTLAB &&
133 133 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
134 134 // Use BIS instruction for TLAB allocation prefetch.
135 135 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
136 136 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
137 137 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
138 138 }
139 139 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
140 140 // Use smaller prefetch distance with BIS
141 141 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
142 142 }
143 143 }
144 144 if (is_T4()) {
145 145 // Double number of prefetched cache lines on T4
146 146 // since L2 cache line size is smaller (32 bytes).
147 147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
148 148 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
149 149 }
150 150 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
151 151 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
152 152 }
153 153 }
154 154 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
155 155 // Use different prefetch distance without BIS
156 156 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
157 157 }
158 158 if (AllocatePrefetchInstr == 1) {
159 159 // Need a space at the end of TLAB for BIS since it
160 160 // will fault when accessing memory outside of heap.
161 161
162 162 // +1 for rounding up to next cache line, +1 to be safe
163 163 int lines = AllocatePrefetchLines + 2;
164 164 int step_size = AllocatePrefetchStepSize;
165 165 int distance = AllocatePrefetchDistance;
166 166 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
167 167 }
168 168 }
169 169 #endif
170 170 }
171 171
172 172 // Use hardware population count instruction if available.
173 173 if (has_hardware_popc()) {
174 174 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
175 175 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
176 176 }
177 177 } else if (UsePopCountInstruction) {
178 178 warning("POPC instruction is not available on this CPU");
179 179 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
180 180 }
181 181
182 182 // T4 and newer Sparc cpus have new compare and branch instruction.
183 183 if (has_cbcond()) {
184 184 if (FLAG_IS_DEFAULT(UseCBCond)) {
185 185 FLAG_SET_DEFAULT(UseCBCond, true);
186 186 }
187 187 } else if (UseCBCond) {
188 188 warning("CBCOND instruction is not available on this CPU");
189 189 FLAG_SET_DEFAULT(UseCBCond, false);
190 190 }
191 191
192 192 assert(BlockZeroingLowLimit > 0, "invalid value");
193 193 if (has_block_zeroing()) {
194 194 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
195 195 FLAG_SET_DEFAULT(UseBlockZeroing, true);
196 196 }
197 197 } else if (UseBlockZeroing) {
198 198 warning("BIS zeroing instructions are not available on this CPU");
199 199 FLAG_SET_DEFAULT(UseBlockZeroing, false);
200 200 }
201 201
202 202 assert(BlockCopyLowLimit > 0, "invalid value");
203 203 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
204 204 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
205 205 FLAG_SET_DEFAULT(UseBlockCopy, true);
206 206 }
207 207 } else if (UseBlockCopy) {
208 208 warning("BIS instructions are not available or expensive on this CPU");
209 209 FLAG_SET_DEFAULT(UseBlockCopy, false);
210 210 }
211 211
212 212 #ifdef COMPILER2
213 213 // T4 and newer Sparc cpus have fast RDPC.
214 214 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
215 215 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
216 216 }
217 217
218 218 // Currently not supported anywhere.
219 219 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
220 220
221 221 MaxVectorSize = 8;
222 222
223 223 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
224 224 #endif
225 225
226 226 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
227 227 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
228 228
229 229 char buf[512];
230 230 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
231 231 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
232 232 (has_hardware_popc() ? ", popc" : ""),
233 233 (has_vis1() ? ", vis1" : ""),
234 234 (has_vis2() ? ", vis2" : ""),
235 235 (has_vis3() ? ", vis3" : ""),
236 236 (has_blk_init() ? ", blk_init" : ""),
237 237 (has_cbcond() ? ", cbcond" : ""),
238 238 (is_ultra3() ? ", ultra3" : ""),
239 239 (is_sun4v() ? ", sun4v" : ""),
240 240 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
241 241 (is_sparc64() ? ", sparc64" : ""),
242 242 (!has_hardware_mul32() ? ", no-mul32" : ""),
243 243 (!has_hardware_div32() ? ", no-div32" : ""),
244 244 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
245 245
246 246 // buf is started with ", " or is empty
247 247 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
248 248
249 249 // UseVIS is set to the smallest of what hardware supports and what
250 250 // the command line requires. I.e., you cannot set UseVIS to 3 on
251 251 // older UltraSparc which do not support it.
252 252 if (UseVIS > 3) UseVIS=3;
253 253 if (UseVIS < 0) UseVIS=0;
254 254 if (!has_vis3()) // Drop to 2 if no VIS3 support
255 255 UseVIS = MIN2((intx)2,UseVIS);
256 256 if (!has_vis2()) // Drop to 1 if no VIS2 support
257 257 UseVIS = MIN2((intx)1,UseVIS);
258 258 if (!has_vis1()) // Drop to 0 if no VIS1 support
259 259 UseVIS = 0;
260 260
261 261 #ifndef PRODUCT
262 262 if (PrintMiscellaneous && Verbose) {
263 263 tty->print("Allocation");
264 264 if (AllocatePrefetchStyle <= 0) {
265 265 tty->print_cr(": no prefetching");
266 266 } else {
267 267 tty->print(" prefetching: ");
268 268 if (AllocatePrefetchInstr == 0) {
269 269 tty->print("PREFETCH");
270 270 } else if (AllocatePrefetchInstr == 1) {
271 271 tty->print("BIS");
272 272 }
273 273 if (AllocatePrefetchLines > 1) {
274 274 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
275 275 } else {
276 276 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
277 277 }
278 278 }
279 279 if (PrefetchCopyIntervalInBytes > 0) {
280 280 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
281 281 }
282 282 if (PrefetchScanIntervalInBytes > 0) {
283 283 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
284 284 }
285 285 if (PrefetchFieldsAhead > 0) {
286 286 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
287 287 }
288 288 }
289 289 #endif // PRODUCT
290 290 }
291 291
292 292 void VM_Version::print_features() {
293 293 tty->print_cr("Version:%s", cpu_features());
294 294 }
295 295
296 296 int VM_Version::determine_features() {
297 297 if (UseV8InstrsOnly) {
298 298 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
299 299 return generic_v8_m;
300 300 }
301 301
302 302 int features = platform_features(unknown_m); // platform_features() is os_arch specific
303 303
304 304 if (features == unknown_m) {
305 305 features = generic_v9_m;
306 306 warning("Cannot recognize SPARC version. Default to V9");
307 307 }
308 308
309 309 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
310 310 if (UseNiagaraInstrs) { // Force code generation for Niagara
311 311 if (is_T_family(features)) {
312 312 // Happy to accomodate...
313 313 } else {
314 314 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
315 315 features |= T_family_m;
316 316 }
317 317 } else {
318 318 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
319 319 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
320 320 features &= ~(T_family_m | T1_model_m);
321 321 } else {
322 322 // Happy to accomodate...
323 323 }
324 324 }
325 325
326 326 return features;
327 327 }
328 328
329 329 static int saved_features = 0;
330 330
331 331 void VM_Version::allow_all() {
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332 332 saved_features = _features;
333 333 _features = all_features_m;
334 334 }
335 335
336 336 void VM_Version::revert() {
337 337 _features = saved_features;
338 338 }
339 339
340 340 unsigned int VM_Version::calc_parallel_worker_threads() {
341 341 unsigned int result;
342 - if (is_niagara_plus()) {
342 + if (is_M_series()) {
343 + // for now, use same gc thread calculation for M-series as for niagara-plus
344 + // in future, we may want to tweak parameters for nof_parallel_worker_thread
345 + result = nof_parallel_worker_threads(5, 16, 8);
346 + } else if (is_niagara_plus()) {
343 347 result = nof_parallel_worker_threads(5, 16, 8);
344 348 } else {
345 349 result = nof_parallel_worker_threads(5, 8, 8);
346 350 }
347 351 return result;
348 352 }
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