1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version: public Abstract_VM_Version { 32 protected: 33 enum Feature_Flag { 34 v8_instructions = 0, 35 hardware_mul32 = 1, 36 hardware_div32 = 2, 37 hardware_fsmuld = 3, 38 hardware_popc = 4, 39 v9_instructions = 5, 40 vis1_instructions = 6, 41 vis2_instructions = 7, 42 sun4v_instructions = 8, 43 blk_init_instructions = 9, 44 fmaf_instructions = 10, 45 fmau_instructions = 11, 46 vis3_instructions = 12, 47 cbcond_instructions = 13, 48 sparc64_family = 14, 49 M_family = 15, 50 T_family = 16, 51 T1_model = 17 52 }; 53 54 enum Feature_Flag_Set { 55 unknown_m = 0, 56 all_features_m = -1, 57 58 v8_instructions_m = 1 << v8_instructions, 59 hardware_mul32_m = 1 << hardware_mul32, 60 hardware_div32_m = 1 << hardware_div32, 61 hardware_fsmuld_m = 1 << hardware_fsmuld, 62 hardware_popc_m = 1 << hardware_popc, 63 v9_instructions_m = 1 << v9_instructions, 64 vis1_instructions_m = 1 << vis1_instructions, 65 vis2_instructions_m = 1 << vis2_instructions, 66 sun4v_m = 1 << sun4v_instructions, 67 blk_init_instructions_m = 1 << blk_init_instructions, 68 fmaf_instructions_m = 1 << fmaf_instructions, 69 fmau_instructions_m = 1 << fmau_instructions, 70 vis3_instructions_m = 1 << vis3_instructions, 71 cbcond_instructions_m = 1 << cbcond_instructions, 72 sparc64_family_m = 1 << sparc64_family, 73 M_family_m = 1 << M_family, 74 T_family_m = 1 << T_family, 75 T1_model_m = 1 << T1_model, 76 77 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 78 generic_v9_m = generic_v8_m | v9_instructions_m, 79 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 80 81 // Temporary until we have something more accurate 82 niagara1_unique_m = sun4v_m, 83 niagara1_m = generic_v9_m | niagara1_unique_m 84 }; 85 86 static int _features; 87 static const char* _features_str; 88 89 static void print_features(); 90 static int determine_features(); 91 static int platform_features(int features); 92 93 // Returns true if the platform is in the niagara line (T series) 94 static bool is_M_family(int features) { return (features & M_family_m) != 0; } 95 static bool is_T_family(int features) { return (features & T_family_m) != 0; } 96 static bool is_niagara() { return is_T_family(_features); } 97 DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } ) 98 99 // Returns true if it is niagara1 (T1). 100 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } 101 102 static int maximum_niagara1_processor_count() { return 32; } 103 104 public: 105 // Initialization 106 static void initialize(); 107 108 // Instruction support 109 static bool has_v8() { return (_features & v8_instructions_m) != 0; } 110 static bool has_v9() { return (_features & v9_instructions_m) != 0; } 111 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } 112 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } 113 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } 114 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } 115 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } 116 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } 117 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } 118 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } 119 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } 120 121 static bool supports_compare_and_exchange() 122 { return has_v9(); } 123 124 // Returns true if the platform is in the niagara line (T series) 125 // and newer than the niagara1. 126 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } 127 128 static bool is_M_series() { return is_M_family(_features); } 129 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } 130 131 // Fujitsu SPARC64 132 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } 133 134 static bool is_sun4v() { return (_features & sun4v_m) != 0; } 135 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } 136 137 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } 138 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } 139 140 // T4 and newer Sparc have fast RDPC instruction. 141 static bool has_fast_rdpc() { return is_T4(); } 142 143 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. 144 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } 145 146 static const char* cpu_features() { return _features_str; } 147 148 static intx prefetch_data_size() { 149 return is_T4() ? 32 : 64; // default prefetch block size on sparc 150 } 151 152 // Prefetch 153 static intx prefetch_copy_interval_in_bytes() { 154 intx interval = PrefetchCopyIntervalInBytes; 155 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 156 } 157 static intx prefetch_scan_interval_in_bytes() { 158 intx interval = PrefetchScanIntervalInBytes; 159 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 160 } 161 static intx prefetch_fields_ahead() { 162 intx count = PrefetchFieldsAhead; 163 return count >= 0 ? count : (is_ultra3() ? 1 : 0); 164 } 165 166 static intx allocate_prefetch_distance() { 167 // This method should be called before allocate_prefetch_style(). 168 intx count = AllocatePrefetchDistance; 169 if (count < 0) { // default is not defined ? 170 count = 512; 171 } 172 return count; 173 } 174 static intx allocate_prefetch_style() { 175 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 176 // Return 0 if AllocatePrefetchDistance was not defined. 177 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 178 } 179 180 // Legacy 181 static bool v8_instructions_work() { return has_v8() && !has_v9(); } 182 static bool v9_instructions_work() { return has_v9(); } 183 184 // Assembler testing 185 static void allow_all(); 186 static void revert(); 187 188 // Override the Abstract_VM_Version implementation. 189 static uint page_size_count() { return is_sun4v() ? 4 : 2; } 190 191 // Calculates the number of parallel threads 192 static unsigned int calc_parallel_worker_threads(); 193 }; 194 195 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP