src/cpu/x86/vm/assembler_x86.cpp
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src/cpu/x86/vm/assembler_x86.cpp

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 165   if (valid_index) {
 166     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
 167     madr._rspec = rspec;
 168     return madr;
 169   } else {
 170     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
 171     madr._rspec = rspec;
 172     return madr;
 173   }
 174 }
 175 
 176 // Implementation of Assembler
 177 
 178 int AbstractAssembler::code_fill_byte() {
 179   return (u_char)'\xF4'; // hlt
 180 }
 181 
 182 // make this go away someday
 183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
 184   if (rtype == relocInfo::none)
 185         emit_long(data);
 186   else  emit_data(data, Relocation::spec_simple(rtype), format);
 187 }
 188 
 189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
 190   assert(imm_operand == 0, "default format must be immediate in this file");
 191   assert(inst_mark() != NULL, "must be inside InstructionMark");
 192   if (rspec.type() !=  relocInfo::none) {
 193     #ifdef ASSERT
 194       check_relocation(rspec, format);
 195     #endif
 196     // Do not use AbstractAssembler::relocate, which is not intended for
 197     // embedded words.  Instead, relocate to the enclosing instruction.
 198 
 199     // hack. call32 is too wide for mask so use disp32
 200     if (format == call32_operand)
 201       code_section()->relocate(inst_mark(), rspec, disp32_operand);
 202     else
 203       code_section()->relocate(inst_mark(), rspec, format);
 204   }
 205   emit_long(data);
 206 }
 207 
 208 static int encode(Register r) {
 209   int enc = r->encoding();
 210   if (enc >= 8) {
 211     enc -= 8;
 212   }
 213   return enc;
 214 }
 215 
 216 static int encode(XMMRegister r) {
 217   int enc = r->encoding();
 218   if (enc >= 8) {
 219     enc -= 8;
 220   }
 221   return enc;
 222 }
 223 
 224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
 225   assert(dst->has_byte_register(), "must have byte register");
 226   assert(isByte(op1) && isByte(op2), "wrong opcode");
 227   assert(isByte(imm8), "not a byte");
 228   assert((op1 & 0x01) == 0, "should be 8bit operation");
 229   emit_int8(op1);
 230   emit_int8(op2 | encode(dst));
 231   emit_int8(imm8);
 232 }
 233 
 234 
 235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
 236   assert(isByte(op1) && isByte(op2), "wrong opcode");
 237   assert((op1 & 0x01) == 1, "should be 32bit operation");
 238   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 239   if (is8bit(imm32)) {
 240     emit_int8(op1 | 0x02); // set sign bit
 241     emit_int8(op2 | encode(dst));
 242     emit_int8(imm32 & 0xFF);
 243   } else {
 244     emit_int8(op1);
 245     emit_int8(op2 | encode(dst));
 246     emit_long(imm32);
 247   }
 248 }
 249 
 250 // Force generation of a 4 byte immediate value even if it fits into 8bit
 251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
 252   assert(isByte(op1) && isByte(op2), "wrong opcode");
 253   assert((op1 & 0x01) == 1, "should be 32bit operation");
 254   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 255   emit_int8(op1);
 256   emit_int8(op2 | encode(dst));
 257   emit_long(imm32);
 258 }
 259 
 260 // immediate-to-memory forms
 261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
 262   assert((op1 & 0x01) == 1, "should be 32bit operation");
 263   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 264   if (is8bit(imm32)) {
 265     emit_int8(op1 | 0x02); // set sign bit
 266     emit_operand(rm, adr, 1);
 267     emit_int8(imm32 & 0xFF);
 268   } else {
 269     emit_int8(op1);
 270     emit_operand(rm, adr, 4);
 271     emit_long(imm32);
 272   }
 273 }
 274 
 275 
 276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
 277   assert(isByte(op1) && isByte(op2), "wrong opcode");
 278   emit_int8(op1);
 279   emit_int8(op2 | encode(dst) << 3 | encode(src));
 280 }
 281 
 282 
 283 void Assembler::emit_operand(Register reg, Register base, Register index,
 284                              Address::ScaleFactor scale, int disp,
 285                              RelocationHolder const& rspec,
 286                              int rip_relative_correction) {
 287   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
 288 
 289   // Encode the registers as needed in the fields they are used in
 290 
 291   int regenc = encode(reg) << 3;


 959   emit_int8(0);    // 8-bits offset (1 byte)
 960 }
 961 
 962 void Assembler::addr_nop_5() {
 963   assert(UseAddressNop, "no CPU support");
 964   // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
 965   emit_int8(0x0F);
 966   emit_int8(0x1F);
 967   emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
 968   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 969   emit_int8(0);    // 8-bits offset (1 byte)
 970 }
 971 
 972 void Assembler::addr_nop_7() {
 973   assert(UseAddressNop, "no CPU support");
 974   // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
 975   emit_int8(0x0F);
 976   emit_int8(0x1F);
 977   emit_int8((unsigned char)0x80);
 978                    // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
 979   emit_long(0);    // 32-bits offset (4 bytes)
 980 }
 981 
 982 void Assembler::addr_nop_8() {
 983   assert(UseAddressNop, "no CPU support");
 984   // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
 985   emit_int8(0x0F);
 986   emit_int8(0x1F);
 987   emit_int8((unsigned char)0x84);
 988                    // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
 989   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 990   emit_long(0);    // 32-bits offset (4 bytes)
 991 }
 992 
 993 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
 994   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 995   emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
 996 }
 997 
 998 void Assembler::addsd(XMMRegister dst, Address src) {
 999   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1000   emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1001 }
1002 
1003 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1004   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1005   emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1006 }
1007 
1008 void Assembler::addss(XMMRegister dst, Address src) {
1009   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1010   emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);


1059   assert(VM_Version::supports_aes(), "");
1060   InstructionMark im(this);
1061   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062   emit_int8((unsigned char)0xDD);
1063   emit_operand(dst, src);
1064 }
1065 
1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1067   assert(VM_Version::supports_aes(), "");
1068   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1069   emit_int8((unsigned char)0xDD);
1070   emit_int8((unsigned char)(0xC0 | encode));
1071 }
1072 
1073 
1074 void Assembler::andl(Address dst, int32_t imm32) {
1075   InstructionMark im(this);
1076   prefix(dst);
1077   emit_int8((unsigned char)0x81);
1078   emit_operand(rsp, dst, 4);
1079   emit_long(imm32);
1080 }
1081 
1082 void Assembler::andl(Register dst, int32_t imm32) {
1083   prefix(dst);
1084   emit_arith(0x81, 0xE0, dst, imm32);
1085 }
1086 
1087 void Assembler::andl(Register dst, Address src) {
1088   InstructionMark im(this);
1089   prefix(src, dst);
1090   emit_int8(0x23);
1091   emit_operand(dst, src);
1092 }
1093 
1094 void Assembler::andl(Register dst, Register src) {
1095   (void) prefix_and_encode(dst->encoding(), src->encoding());
1096   emit_arith(0x23, 0xC0, dst, src);
1097 }
1098 
1099 void Assembler::bsfl(Register dst, Register src) {


1187   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1188   prefix(src, dst);
1189   emit_int8(0x0F);
1190   emit_int8(0x40 | cc);
1191   emit_operand(dst, src);
1192 }
1193 
1194 void Assembler::cmpb(Address dst, int imm8) {
1195   InstructionMark im(this);
1196   prefix(dst);
1197   emit_int8((unsigned char)0x80);
1198   emit_operand(rdi, dst, 1);
1199   emit_int8(imm8);
1200 }
1201 
1202 void Assembler::cmpl(Address dst, int32_t imm32) {
1203   InstructionMark im(this);
1204   prefix(dst);
1205   emit_int8((unsigned char)0x81);
1206   emit_operand(rdi, dst, 4);
1207   emit_long(imm32);
1208 }
1209 
1210 void Assembler::cmpl(Register dst, int32_t imm32) {
1211   prefix(dst);
1212   emit_arith(0x81, 0xF8, dst, imm32);
1213 }
1214 
1215 void Assembler::cmpl(Register dst, Register src) {
1216   (void) prefix_and_encode(dst->encoding(), src->encoding());
1217   emit_arith(0x3B, 0xC0, dst, src);
1218 }
1219 
1220 
1221 void Assembler::cmpl(Register dst, Address  src) {
1222   InstructionMark im(this);
1223   prefix(src, dst);
1224   emit_int8((unsigned char)0x3B);
1225   emit_operand(dst, src);
1226 }
1227 


1391   emit_int8((unsigned char)(0xF0 | encode));
1392 }
1393 
1394 void Assembler::imull(Register dst, Register src) {
1395   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1396   emit_int8(0x0F);
1397   emit_int8((unsigned char)0xAF);
1398   emit_int8((unsigned char)(0xC0 | encode));
1399 }
1400 
1401 
1402 void Assembler::imull(Register dst, Register src, int value) {
1403   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1404   if (is8bit(value)) {
1405     emit_int8(0x6B);
1406     emit_int8((unsigned char)(0xC0 | encode));
1407     emit_int8(value & 0xFF);
1408   } else {
1409     emit_int8(0x69);
1410     emit_int8((unsigned char)(0xC0 | encode));
1411     emit_long(value);
1412   }
1413 }
1414 
1415 void Assembler::incl(Address dst) {
1416   // Don't use it directly. Use MacroAssembler::increment() instead.
1417   InstructionMark im(this);
1418   prefix(dst);
1419   emit_int8((unsigned char)0xFF);
1420   emit_operand(rax, dst);
1421 }
1422 
1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1424   InstructionMark im(this);
1425   assert((0 <= cc) && (cc < 16), "illegal cc");
1426   if (L.is_bound()) {
1427     address dst = target(L);
1428     assert(dst != NULL, "jcc most probably wrong");
1429 
1430     const int short_size = 2;
1431     const int long_size = 6;
1432     intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1433     if (maybe_short && is8bit(offs - short_size)) {
1434       // 0111 tttn #8-bit disp
1435       emit_int8(0x70 | cc);
1436       emit_int8((offs - short_size) & 0xFF);
1437     } else {
1438       // 0000 1111 1000 tttn #32-bit disp
1439       assert(is_simm32(offs - long_size),
1440              "must be 32bit offset (call4)");
1441       emit_int8(0x0F);
1442       emit_int8((unsigned char)(0x80 | cc));
1443       emit_long(offs - long_size);
1444     }
1445   } else {
1446     // Note: could eliminate cond. jumps to this jump if condition
1447     //       is the same however, seems to be rather unlikely case.
1448     // Note: use jccb() if label to be bound is very close to get
1449     //       an 8-bit displacement
1450     L.add_patch_at(code(), locator());
1451     emit_int8(0x0F);
1452     emit_int8((unsigned char)(0x80 | cc));
1453     emit_long(0);
1454   }
1455 }
1456 
1457 void Assembler::jccb(Condition cc, Label& L) {
1458   if (L.is_bound()) {
1459     const int short_size = 2;
1460     address entry = target(L);
1461 #ifdef ASSERT
1462     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1463     intptr_t delta = short_branch_delta();
1464     if (delta != 0) {
1465       dist += (dist < 0 ? (-delta) :delta);
1466     }
1467     assert(is8bit(dist), "Dispacement too large for a short jmp");
1468 #endif
1469     intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1470     // 0111 tttn #8-bit disp
1471     emit_int8(0x70 | cc);
1472     emit_int8((offs - short_size) & 0xFF);
1473   } else {


1481 void Assembler::jmp(Address adr) {
1482   InstructionMark im(this);
1483   prefix(adr);
1484   emit_int8((unsigned char)0xFF);
1485   emit_operand(rsp, adr);
1486 }
1487 
1488 void Assembler::jmp(Label& L, bool maybe_short) {
1489   if (L.is_bound()) {
1490     address entry = target(L);
1491     assert(entry != NULL, "jmp most probably wrong");
1492     InstructionMark im(this);
1493     const int short_size = 2;
1494     const int long_size = 5;
1495     intptr_t offs = entry - pc();
1496     if (maybe_short && is8bit(offs - short_size)) {
1497       emit_int8((unsigned char)0xEB);
1498       emit_int8((offs - short_size) & 0xFF);
1499     } else {
1500       emit_int8((unsigned char)0xE9);
1501       emit_long(offs - long_size);
1502     }
1503   } else {
1504     // By default, forward jumps are always 32-bit displacements, since
1505     // we can't yet know where the label will be bound.  If you're sure that
1506     // the forward jump will not run beyond 256 bytes, use jmpb to
1507     // force an 8-bit displacement.
1508     InstructionMark im(this);
1509     L.add_patch_at(code(), locator());
1510     emit_int8((unsigned char)0xE9);
1511     emit_long(0);
1512   }
1513 }
1514 
1515 void Assembler::jmp(Register entry) {
1516   int encode = prefix_and_encode(entry->encoding());
1517   emit_int8((unsigned char)0xFF);
1518   emit_int8((unsigned char)(0xE0 | encode));
1519 }
1520 
1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1522   InstructionMark im(this);
1523   emit_int8((unsigned char)0xE9);
1524   assert(dest != NULL, "must have a target");
1525   intptr_t disp = dest - (pc() + sizeof(int32_t));
1526   assert(is_simm32(disp), "must be 32bit offset (jmp)");
1527   emit_data(disp, rspec.reloc(), call32_operand);
1528 }
1529 
1530 void Assembler::jmpb(Label& L) {
1531   if (L.is_bound()) {


1715   emit_int8(0x6F);
1716   emit_operand(dst, src);
1717 }
1718 
1719 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1720   assert(UseAVX, "");
1721   InstructionMark im(this);
1722   bool vector256 = true;
1723   // swap src<->dst for encoding
1724   assert(src != xnoreg, "sanity");
1725   vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1726   emit_int8(0x7F);
1727   emit_operand(src, dst);
1728 }
1729 
1730 // Uses zero extension on 64bit
1731 
1732 void Assembler::movl(Register dst, int32_t imm32) {
1733   int encode = prefix_and_encode(dst->encoding());
1734   emit_int8((unsigned char)(0xB8 | encode));
1735   emit_long(imm32);
1736 }
1737 
1738 void Assembler::movl(Register dst, Register src) {
1739   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1740   emit_int8((unsigned char)0x8B);
1741   emit_int8((unsigned char)(0xC0 | encode));
1742 }
1743 
1744 void Assembler::movl(Register dst, Address src) {
1745   InstructionMark im(this);
1746   prefix(src, dst);
1747   emit_int8((unsigned char)0x8B);
1748   emit_operand(dst, src);
1749 }
1750 
1751 void Assembler::movl(Address dst, int32_t imm32) {
1752   InstructionMark im(this);
1753   prefix(dst);
1754   emit_int8((unsigned char)0xC7);
1755   emit_operand(rax, dst, 4);
1756   emit_long(imm32);
1757 }
1758 
1759 void Assembler::movl(Address dst, Register src) {
1760   InstructionMark im(this);
1761   prefix(dst, src);
1762   emit_int8((unsigned char)0x89);
1763   emit_operand(src, dst);
1764 }
1765 
1766 // New cpus require to use movsd and movss to avoid partial register stall
1767 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1768 // The selection is done in MacroAssembler::movdbl() and movflt().
1769 void Assembler::movlpd(XMMRegister dst, Address src) {
1770   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1771   emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1772 }
1773 
1774 void Assembler::movq( MMXRegister dst, Address src ) {
1775   assert( VM_Version::supports_mmx(), "" );
1776   emit_int8(0x0F);


2482 void Assembler::punpckldq(XMMRegister dst, Address src) {
2483   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2484   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2485   emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2486 }
2487 
2488 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2489   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2490   emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2491 }
2492 
2493 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2494   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495   emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2496 }
2497 
2498 void Assembler::push(int32_t imm32) {
2499   // in 64bits we push 64bits onto the stack but only
2500   // take a 32bit immediate
2501   emit_int8(0x68);
2502   emit_long(imm32);
2503 }
2504 
2505 void Assembler::push(Register src) {
2506   int encode = prefix_and_encode(src->encoding());
2507 
2508   emit_int8(0x50 | encode);
2509 }
2510 
2511 void Assembler::pushf() {
2512   emit_int8((unsigned char)0x9C);
2513 }
2514 
2515 #ifndef _LP64 // no 32bit push/pop on amd64
2516 void Assembler::pushl(Address src) {
2517   // Note this will push 64bit on 64bit
2518   InstructionMark im(this);
2519   prefix(src);
2520   emit_int8((unsigned char)0xFF);
2521   emit_operand(rsi, src);
2522 }


2768 }
2769 
2770 void Assembler::testb(Register dst, int imm8) {
2771   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2772   (void) prefix_and_encode(dst->encoding(), true);
2773   emit_arith_b(0xF6, 0xC0, dst, imm8);
2774 }
2775 
2776 void Assembler::testl(Register dst, int32_t imm32) {
2777   // not using emit_arith because test
2778   // doesn't support sign-extension of
2779   // 8bit operands
2780   int encode = dst->encoding();
2781   if (encode == 0) {
2782     emit_int8((unsigned char)0xA9);
2783   } else {
2784     encode = prefix_and_encode(encode);
2785     emit_int8((unsigned char)0xF7);
2786     emit_int8((unsigned char)(0xC0 | encode));
2787   }
2788   emit_long(imm32);
2789 }
2790 
2791 void Assembler::testl(Register dst, Register src) {
2792   (void) prefix_and_encode(dst->encoding(), src->encoding());
2793   emit_arith(0x85, 0xC0, dst, src);
2794 }
2795 
2796 void Assembler::testl(Register dst, Address  src) {
2797   InstructionMark im(this);
2798   prefix(src, dst);
2799   emit_int8((unsigned char)0x85);
2800   emit_operand(dst, src);
2801 }
2802 
2803 void Assembler::ucomisd(XMMRegister dst, Address src) {
2804   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2805   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2806 }
2807 
2808 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {


4703   emit_arith(0x81, 0xC0, dst, imm32);
4704 }
4705 
4706 void Assembler::addq(Register dst, Address src) {
4707   InstructionMark im(this);
4708   prefixq(src, dst);
4709   emit_int8(0x03);
4710   emit_operand(dst, src);
4711 }
4712 
4713 void Assembler::addq(Register dst, Register src) {
4714   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4715   emit_arith(0x03, 0xC0, dst, src);
4716 }
4717 
4718 void Assembler::andq(Address dst, int32_t imm32) {
4719   InstructionMark im(this);
4720   prefixq(dst);
4721   emit_int8((unsigned char)0x81);
4722   emit_operand(rsp, dst, 4);
4723   emit_long(imm32);
4724 }
4725 
4726 void Assembler::andq(Register dst, int32_t imm32) {
4727   (void) prefixq_and_encode(dst->encoding());
4728   emit_arith(0x81, 0xE0, dst, imm32);
4729 }
4730 
4731 void Assembler::andq(Register dst, Address src) {
4732   InstructionMark im(this);
4733   prefixq(src, dst);
4734   emit_int8(0x23);
4735   emit_operand(dst, src);
4736 }
4737 
4738 void Assembler::andq(Register dst, Register src) {
4739   (int) prefixq_and_encode(dst->encoding(), src->encoding());
4740   emit_arith(0x23, 0xC0, dst, src);
4741 }
4742 
4743 void Assembler::bsfq(Register dst, Register src) {


4776 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4777   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4778   emit_int8(0x0F);
4779   emit_int8(0x40 | cc);
4780   emit_int8((unsigned char)(0xC0 | encode));
4781 }
4782 
4783 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4784   InstructionMark im(this);
4785   prefixq(src, dst);
4786   emit_int8(0x0F);
4787   emit_int8(0x40 | cc);
4788   emit_operand(dst, src);
4789 }
4790 
4791 void Assembler::cmpq(Address dst, int32_t imm32) {
4792   InstructionMark im(this);
4793   prefixq(dst);
4794   emit_int8((unsigned char)0x81);
4795   emit_operand(rdi, dst, 4);
4796   emit_long(imm32);
4797 }
4798 
4799 void Assembler::cmpq(Register dst, int32_t imm32) {
4800   (void) prefixq_and_encode(dst->encoding());
4801   emit_arith(0x81, 0xF8, dst, imm32);
4802 }
4803 
4804 void Assembler::cmpq(Address dst, Register src) {
4805   InstructionMark im(this);
4806   prefixq(dst, src);
4807   emit_int8(0x3B);
4808   emit_operand(src, dst);
4809 }
4810 
4811 void Assembler::cmpq(Register dst, Register src) {
4812   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4813   emit_arith(0x3B, 0xC0, dst, src);
4814 }
4815 
4816 void Assembler::cmpq(Register dst, Address  src) {


4915   emit_int8((unsigned char)0xF7);
4916   emit_int8((unsigned char)(0xF8 | encode));
4917 }
4918 
4919 void Assembler::imulq(Register dst, Register src) {
4920   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4921   emit_int8(0x0F);
4922   emit_int8((unsigned char)0xAF);
4923   emit_int8((unsigned char)(0xC0 | encode));
4924 }
4925 
4926 void Assembler::imulq(Register dst, Register src, int value) {
4927   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4928   if (is8bit(value)) {
4929     emit_int8(0x6B);
4930     emit_int8((unsigned char)(0xC0 | encode));
4931     emit_int8(value & 0xFF);
4932   } else {
4933     emit_int8(0x69);
4934     emit_int8((unsigned char)(0xC0 | encode));
4935     emit_long(value);
4936   }
4937 }
4938 
4939 void Assembler::incl(Register dst) {
4940   // Don't use it directly. Use MacroAssembler::incrementl() instead.
4941   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4942   int encode = prefix_and_encode(dst->encoding());
4943   emit_int8((unsigned char)0xFF);
4944   emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946 
4947 void Assembler::incq(Register dst) {
4948   // Don't use it directly. Use MacroAssembler::incrementq() instead.
4949   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4950   int encode = prefixq_and_encode(dst->encoding());
4951   emit_int8((unsigned char)0xFF);
4952   emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954 
4955 void Assembler::incq(Address dst) {


5068   emit_int8(0x0F);
5069   emit_int8((unsigned char)0xBE);
5070   emit_operand(dst, src);
5071 }
5072 
5073 void Assembler::movsbq(Register dst, Register src) {
5074   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5075   emit_int8(0x0F);
5076   emit_int8((unsigned char)0xBE);
5077   emit_int8((unsigned char)(0xC0 | encode));
5078 }
5079 
5080 void Assembler::movslq(Register dst, int32_t imm32) {
5081   // dbx shows movslq(rcx, 3) as movq     $0x0000000049000000,(%rbx)
5082   // and movslq(r8, 3); as movl     $0x0000000048000000,(%rbx)
5083   // as a result we shouldn't use until tested at runtime...
5084   ShouldNotReachHere();
5085   InstructionMark im(this);
5086   int encode = prefixq_and_encode(dst->encoding());
5087   emit_int8((unsigned char)(0xC7 | encode));
5088   emit_long(imm32);
5089 }
5090 
5091 void Assembler::movslq(Address dst, int32_t imm32) {
5092   assert(is_simm32(imm32), "lost bits");
5093   InstructionMark im(this);
5094   prefixq(dst);
5095   emit_int8((unsigned char)0xC7);
5096   emit_operand(rax, dst, 4);
5097   emit_long(imm32);
5098 }
5099 
5100 void Assembler::movslq(Register dst, Address src) {
5101   InstructionMark im(this);
5102   prefixq(src, dst);
5103   emit_int8(0x63);
5104   emit_operand(dst, src);
5105 }
5106 
5107 void Assembler::movslq(Register dst, Register src) {
5108   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5109   emit_int8(0x63);
5110   emit_int8((unsigned char)(0xC0 | encode));
5111 }
5112 
5113 void Assembler::movswq(Register dst, Address src) {
5114   InstructionMark im(this);
5115   prefixq(src, dst);
5116   emit_int8(0x0F);
5117   emit_int8((unsigned char)0xBF);


5155   emit_int8((unsigned char)(0xC0 | encode));
5156 }
5157 
5158 void Assembler::negq(Register dst) {
5159   int encode = prefixq_and_encode(dst->encoding());
5160   emit_int8((unsigned char)0xF7);
5161   emit_int8((unsigned char)(0xD8 | encode));
5162 }
5163 
5164 void Assembler::notq(Register dst) {
5165   int encode = prefixq_and_encode(dst->encoding());
5166   emit_int8((unsigned char)0xF7);
5167   emit_int8((unsigned char)(0xD0 | encode));
5168 }
5169 
5170 void Assembler::orq(Address dst, int32_t imm32) {
5171   InstructionMark im(this);
5172   prefixq(dst);
5173   emit_int8((unsigned char)0x81);
5174   emit_operand(rcx, dst, 4);
5175   emit_long(imm32);
5176 }
5177 
5178 void Assembler::orq(Register dst, int32_t imm32) {
5179   (void) prefixq_and_encode(dst->encoding());
5180   emit_arith(0x81, 0xC8, dst, imm32);
5181 }
5182 
5183 void Assembler::orq(Register dst, Address src) {
5184   InstructionMark im(this);
5185   prefixq(src, dst);
5186   emit_int8(0x0B);
5187   emit_operand(dst, src);
5188 }
5189 
5190 void Assembler::orq(Register dst, Register src) {
5191   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5192   emit_arith(0x0B, 0xC0, dst, src);
5193 }
5194 
5195 void Assembler::popa() { // 64bit


5390 }
5391 
5392 void Assembler::subq(Register dst, Register src) {
5393   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5394   emit_arith(0x2B, 0xC0, dst, src);
5395 }
5396 
5397 void Assembler::testq(Register dst, int32_t imm32) {
5398   // not using emit_arith because test
5399   // doesn't support sign-extension of
5400   // 8bit operands
5401   int encode = dst->encoding();
5402   if (encode == 0) {
5403     prefix(REX_W);
5404     emit_int8((unsigned char)0xA9);
5405   } else {
5406     encode = prefixq_and_encode(encode);
5407     emit_int8((unsigned char)0xF7);
5408     emit_int8((unsigned char)(0xC0 | encode));
5409   }
5410   emit_long(imm32);
5411 }
5412 
5413 void Assembler::testq(Register dst, Register src) {
5414   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5415   emit_arith(0x85, 0xC0, dst, src);
5416 }
5417 
5418 void Assembler::xaddq(Address dst, Register src) {
5419   InstructionMark im(this);
5420   prefixq(dst, src);
5421   emit_int8(0x0F);
5422   emit_int8((unsigned char)0xC1);
5423   emit_operand(src, dst);
5424 }
5425 
5426 void Assembler::xchgq(Register dst, Address src) {
5427   InstructionMark im(this);
5428   prefixq(src, dst);
5429   emit_int8((unsigned char)0x87);
5430   emit_operand(dst, src);




 165   if (valid_index) {
 166     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
 167     madr._rspec = rspec;
 168     return madr;
 169   } else {
 170     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
 171     madr._rspec = rspec;
 172     return madr;
 173   }
 174 }
 175 
 176 // Implementation of Assembler
 177 
 178 int AbstractAssembler::code_fill_byte() {
 179   return (u_char)'\xF4'; // hlt
 180 }
 181 
 182 // make this go away someday
 183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
 184   if (rtype == relocInfo::none)
 185         emit_int32(data);
 186   else  emit_data(data, Relocation::spec_simple(rtype), format);
 187 }
 188 
 189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
 190   assert(imm_operand == 0, "default format must be immediate in this file");
 191   assert(inst_mark() != NULL, "must be inside InstructionMark");
 192   if (rspec.type() !=  relocInfo::none) {
 193     #ifdef ASSERT
 194       check_relocation(rspec, format);
 195     #endif
 196     // Do not use AbstractAssembler::relocate, which is not intended for
 197     // embedded words.  Instead, relocate to the enclosing instruction.
 198 
 199     // hack. call32 is too wide for mask so use disp32
 200     if (format == call32_operand)
 201       code_section()->relocate(inst_mark(), rspec, disp32_operand);
 202     else
 203       code_section()->relocate(inst_mark(), rspec, format);
 204   }
 205   emit_int32(data);
 206 }
 207 
 208 static int encode(Register r) {
 209   int enc = r->encoding();
 210   if (enc >= 8) {
 211     enc -= 8;
 212   }
 213   return enc;
 214 }
 215 
 216 static int encode(XMMRegister r) {
 217   int enc = r->encoding();
 218   if (enc >= 8) {
 219     enc -= 8;
 220   }
 221   return enc;
 222 }
 223 
 224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
 225   assert(dst->has_byte_register(), "must have byte register");
 226   assert(isByte(op1) && isByte(op2), "wrong opcode");
 227   assert(isByte(imm8), "not a byte");
 228   assert((op1 & 0x01) == 0, "should be 8bit operation");
 229   emit_int8(op1);
 230   emit_int8(op2 | encode(dst));
 231   emit_int8(imm8);
 232 }
 233 
 234 
 235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
 236   assert(isByte(op1) && isByte(op2), "wrong opcode");
 237   assert((op1 & 0x01) == 1, "should be 32bit operation");
 238   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 239   if (is8bit(imm32)) {
 240     emit_int8(op1 | 0x02); // set sign bit
 241     emit_int8(op2 | encode(dst));
 242     emit_int8(imm32 & 0xFF);
 243   } else {
 244     emit_int8(op1);
 245     emit_int8(op2 | encode(dst));
 246     emit_int32(imm32);
 247   }
 248 }
 249 
 250 // Force generation of a 4 byte immediate value even if it fits into 8bit
 251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
 252   assert(isByte(op1) && isByte(op2), "wrong opcode");
 253   assert((op1 & 0x01) == 1, "should be 32bit operation");
 254   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 255   emit_int8(op1);
 256   emit_int8(op2 | encode(dst));
 257   emit_int32(imm32);
 258 }
 259 
 260 // immediate-to-memory forms
 261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
 262   assert((op1 & 0x01) == 1, "should be 32bit operation");
 263   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 264   if (is8bit(imm32)) {
 265     emit_int8(op1 | 0x02); // set sign bit
 266     emit_operand(rm, adr, 1);
 267     emit_int8(imm32 & 0xFF);
 268   } else {
 269     emit_int8(op1);
 270     emit_operand(rm, adr, 4);
 271     emit_int32(imm32);
 272   }
 273 }
 274 
 275 
 276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
 277   assert(isByte(op1) && isByte(op2), "wrong opcode");
 278   emit_int8(op1);
 279   emit_int8(op2 | encode(dst) << 3 | encode(src));
 280 }
 281 
 282 
 283 void Assembler::emit_operand(Register reg, Register base, Register index,
 284                              Address::ScaleFactor scale, int disp,
 285                              RelocationHolder const& rspec,
 286                              int rip_relative_correction) {
 287   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
 288 
 289   // Encode the registers as needed in the fields they are used in
 290 
 291   int regenc = encode(reg) << 3;


 959   emit_int8(0);    // 8-bits offset (1 byte)
 960 }
 961 
 962 void Assembler::addr_nop_5() {
 963   assert(UseAddressNop, "no CPU support");
 964   // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
 965   emit_int8(0x0F);
 966   emit_int8(0x1F);
 967   emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
 968   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 969   emit_int8(0);    // 8-bits offset (1 byte)
 970 }
 971 
 972 void Assembler::addr_nop_7() {
 973   assert(UseAddressNop, "no CPU support");
 974   // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
 975   emit_int8(0x0F);
 976   emit_int8(0x1F);
 977   emit_int8((unsigned char)0x80);
 978                    // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
 979   emit_int32(0);   // 32-bits offset (4 bytes)
 980 }
 981 
 982 void Assembler::addr_nop_8() {
 983   assert(UseAddressNop, "no CPU support");
 984   // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
 985   emit_int8(0x0F);
 986   emit_int8(0x1F);
 987   emit_int8((unsigned char)0x84);
 988                    // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
 989   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 990   emit_int32(0);   // 32-bits offset (4 bytes)
 991 }
 992 
 993 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
 994   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 995   emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
 996 }
 997 
 998 void Assembler::addsd(XMMRegister dst, Address src) {
 999   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1000   emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1001 }
1002 
1003 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1004   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1005   emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1006 }
1007 
1008 void Assembler::addss(XMMRegister dst, Address src) {
1009   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1010   emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);


1059   assert(VM_Version::supports_aes(), "");
1060   InstructionMark im(this);
1061   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062   emit_int8((unsigned char)0xDD);
1063   emit_operand(dst, src);
1064 }
1065 
1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1067   assert(VM_Version::supports_aes(), "");
1068   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1069   emit_int8((unsigned char)0xDD);
1070   emit_int8((unsigned char)(0xC0 | encode));
1071 }
1072 
1073 
1074 void Assembler::andl(Address dst, int32_t imm32) {
1075   InstructionMark im(this);
1076   prefix(dst);
1077   emit_int8((unsigned char)0x81);
1078   emit_operand(rsp, dst, 4);
1079   emit_int32(imm32);
1080 }
1081 
1082 void Assembler::andl(Register dst, int32_t imm32) {
1083   prefix(dst);
1084   emit_arith(0x81, 0xE0, dst, imm32);
1085 }
1086 
1087 void Assembler::andl(Register dst, Address src) {
1088   InstructionMark im(this);
1089   prefix(src, dst);
1090   emit_int8(0x23);
1091   emit_operand(dst, src);
1092 }
1093 
1094 void Assembler::andl(Register dst, Register src) {
1095   (void) prefix_and_encode(dst->encoding(), src->encoding());
1096   emit_arith(0x23, 0xC0, dst, src);
1097 }
1098 
1099 void Assembler::bsfl(Register dst, Register src) {


1187   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1188   prefix(src, dst);
1189   emit_int8(0x0F);
1190   emit_int8(0x40 | cc);
1191   emit_operand(dst, src);
1192 }
1193 
1194 void Assembler::cmpb(Address dst, int imm8) {
1195   InstructionMark im(this);
1196   prefix(dst);
1197   emit_int8((unsigned char)0x80);
1198   emit_operand(rdi, dst, 1);
1199   emit_int8(imm8);
1200 }
1201 
1202 void Assembler::cmpl(Address dst, int32_t imm32) {
1203   InstructionMark im(this);
1204   prefix(dst);
1205   emit_int8((unsigned char)0x81);
1206   emit_operand(rdi, dst, 4);
1207   emit_int32(imm32);
1208 }
1209 
1210 void Assembler::cmpl(Register dst, int32_t imm32) {
1211   prefix(dst);
1212   emit_arith(0x81, 0xF8, dst, imm32);
1213 }
1214 
1215 void Assembler::cmpl(Register dst, Register src) {
1216   (void) prefix_and_encode(dst->encoding(), src->encoding());
1217   emit_arith(0x3B, 0xC0, dst, src);
1218 }
1219 
1220 
1221 void Assembler::cmpl(Register dst, Address  src) {
1222   InstructionMark im(this);
1223   prefix(src, dst);
1224   emit_int8((unsigned char)0x3B);
1225   emit_operand(dst, src);
1226 }
1227 


1391   emit_int8((unsigned char)(0xF0 | encode));
1392 }
1393 
1394 void Assembler::imull(Register dst, Register src) {
1395   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1396   emit_int8(0x0F);
1397   emit_int8((unsigned char)0xAF);
1398   emit_int8((unsigned char)(0xC0 | encode));
1399 }
1400 
1401 
1402 void Assembler::imull(Register dst, Register src, int value) {
1403   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1404   if (is8bit(value)) {
1405     emit_int8(0x6B);
1406     emit_int8((unsigned char)(0xC0 | encode));
1407     emit_int8(value & 0xFF);
1408   } else {
1409     emit_int8(0x69);
1410     emit_int8((unsigned char)(0xC0 | encode));
1411     emit_int32(value);
1412   }
1413 }
1414 
1415 void Assembler::incl(Address dst) {
1416   // Don't use it directly. Use MacroAssembler::increment() instead.
1417   InstructionMark im(this);
1418   prefix(dst);
1419   emit_int8((unsigned char)0xFF);
1420   emit_operand(rax, dst);
1421 }
1422 
1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1424   InstructionMark im(this);
1425   assert((0 <= cc) && (cc < 16), "illegal cc");
1426   if (L.is_bound()) {
1427     address dst = target(L);
1428     assert(dst != NULL, "jcc most probably wrong");
1429 
1430     const int short_size = 2;
1431     const int long_size = 6;
1432     intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1433     if (maybe_short && is8bit(offs - short_size)) {
1434       // 0111 tttn #8-bit disp
1435       emit_int8(0x70 | cc);
1436       emit_int8((offs - short_size) & 0xFF);
1437     } else {
1438       // 0000 1111 1000 tttn #32-bit disp
1439       assert(is_simm32(offs - long_size),
1440              "must be 32bit offset (call4)");
1441       emit_int8(0x0F);
1442       emit_int8((unsigned char)(0x80 | cc));
1443       emit_int32(offs - long_size);
1444     }
1445   } else {
1446     // Note: could eliminate cond. jumps to this jump if condition
1447     //       is the same however, seems to be rather unlikely case.
1448     // Note: use jccb() if label to be bound is very close to get
1449     //       an 8-bit displacement
1450     L.add_patch_at(code(), locator());
1451     emit_int8(0x0F);
1452     emit_int8((unsigned char)(0x80 | cc));
1453     emit_int32(0);
1454   }
1455 }
1456 
1457 void Assembler::jccb(Condition cc, Label& L) {
1458   if (L.is_bound()) {
1459     const int short_size = 2;
1460     address entry = target(L);
1461 #ifdef ASSERT
1462     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1463     intptr_t delta = short_branch_delta();
1464     if (delta != 0) {
1465       dist += (dist < 0 ? (-delta) :delta);
1466     }
1467     assert(is8bit(dist), "Dispacement too large for a short jmp");
1468 #endif
1469     intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1470     // 0111 tttn #8-bit disp
1471     emit_int8(0x70 | cc);
1472     emit_int8((offs - short_size) & 0xFF);
1473   } else {


1481 void Assembler::jmp(Address adr) {
1482   InstructionMark im(this);
1483   prefix(adr);
1484   emit_int8((unsigned char)0xFF);
1485   emit_operand(rsp, adr);
1486 }
1487 
1488 void Assembler::jmp(Label& L, bool maybe_short) {
1489   if (L.is_bound()) {
1490     address entry = target(L);
1491     assert(entry != NULL, "jmp most probably wrong");
1492     InstructionMark im(this);
1493     const int short_size = 2;
1494     const int long_size = 5;
1495     intptr_t offs = entry - pc();
1496     if (maybe_short && is8bit(offs - short_size)) {
1497       emit_int8((unsigned char)0xEB);
1498       emit_int8((offs - short_size) & 0xFF);
1499     } else {
1500       emit_int8((unsigned char)0xE9);
1501       emit_int32(offs - long_size);
1502     }
1503   } else {
1504     // By default, forward jumps are always 32-bit displacements, since
1505     // we can't yet know where the label will be bound.  If you're sure that
1506     // the forward jump will not run beyond 256 bytes, use jmpb to
1507     // force an 8-bit displacement.
1508     InstructionMark im(this);
1509     L.add_patch_at(code(), locator());
1510     emit_int8((unsigned char)0xE9);
1511     emit_int32(0);
1512   }
1513 }
1514 
1515 void Assembler::jmp(Register entry) {
1516   int encode = prefix_and_encode(entry->encoding());
1517   emit_int8((unsigned char)0xFF);
1518   emit_int8((unsigned char)(0xE0 | encode));
1519 }
1520 
1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1522   InstructionMark im(this);
1523   emit_int8((unsigned char)0xE9);
1524   assert(dest != NULL, "must have a target");
1525   intptr_t disp = dest - (pc() + sizeof(int32_t));
1526   assert(is_simm32(disp), "must be 32bit offset (jmp)");
1527   emit_data(disp, rspec.reloc(), call32_operand);
1528 }
1529 
1530 void Assembler::jmpb(Label& L) {
1531   if (L.is_bound()) {


1715   emit_int8(0x6F);
1716   emit_operand(dst, src);
1717 }
1718 
1719 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1720   assert(UseAVX, "");
1721   InstructionMark im(this);
1722   bool vector256 = true;
1723   // swap src<->dst for encoding
1724   assert(src != xnoreg, "sanity");
1725   vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1726   emit_int8(0x7F);
1727   emit_operand(src, dst);
1728 }
1729 
1730 // Uses zero extension on 64bit
1731 
1732 void Assembler::movl(Register dst, int32_t imm32) {
1733   int encode = prefix_and_encode(dst->encoding());
1734   emit_int8((unsigned char)(0xB8 | encode));
1735   emit_int32(imm32);
1736 }
1737 
1738 void Assembler::movl(Register dst, Register src) {
1739   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1740   emit_int8((unsigned char)0x8B);
1741   emit_int8((unsigned char)(0xC0 | encode));
1742 }
1743 
1744 void Assembler::movl(Register dst, Address src) {
1745   InstructionMark im(this);
1746   prefix(src, dst);
1747   emit_int8((unsigned char)0x8B);
1748   emit_operand(dst, src);
1749 }
1750 
1751 void Assembler::movl(Address dst, int32_t imm32) {
1752   InstructionMark im(this);
1753   prefix(dst);
1754   emit_int8((unsigned char)0xC7);
1755   emit_operand(rax, dst, 4);
1756   emit_int32(imm32);
1757 }
1758 
1759 void Assembler::movl(Address dst, Register src) {
1760   InstructionMark im(this);
1761   prefix(dst, src);
1762   emit_int8((unsigned char)0x89);
1763   emit_operand(src, dst);
1764 }
1765 
1766 // New cpus require to use movsd and movss to avoid partial register stall
1767 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1768 // The selection is done in MacroAssembler::movdbl() and movflt().
1769 void Assembler::movlpd(XMMRegister dst, Address src) {
1770   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1771   emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1772 }
1773 
1774 void Assembler::movq( MMXRegister dst, Address src ) {
1775   assert( VM_Version::supports_mmx(), "" );
1776   emit_int8(0x0F);


2482 void Assembler::punpckldq(XMMRegister dst, Address src) {
2483   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2484   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2485   emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2486 }
2487 
2488 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2489   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2490   emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2491 }
2492 
2493 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2494   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495   emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2496 }
2497 
2498 void Assembler::push(int32_t imm32) {
2499   // in 64bits we push 64bits onto the stack but only
2500   // take a 32bit immediate
2501   emit_int8(0x68);
2502   emit_int32(imm32);
2503 }
2504 
2505 void Assembler::push(Register src) {
2506   int encode = prefix_and_encode(src->encoding());
2507 
2508   emit_int8(0x50 | encode);
2509 }
2510 
2511 void Assembler::pushf() {
2512   emit_int8((unsigned char)0x9C);
2513 }
2514 
2515 #ifndef _LP64 // no 32bit push/pop on amd64
2516 void Assembler::pushl(Address src) {
2517   // Note this will push 64bit on 64bit
2518   InstructionMark im(this);
2519   prefix(src);
2520   emit_int8((unsigned char)0xFF);
2521   emit_operand(rsi, src);
2522 }


2768 }
2769 
2770 void Assembler::testb(Register dst, int imm8) {
2771   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2772   (void) prefix_and_encode(dst->encoding(), true);
2773   emit_arith_b(0xF6, 0xC0, dst, imm8);
2774 }
2775 
2776 void Assembler::testl(Register dst, int32_t imm32) {
2777   // not using emit_arith because test
2778   // doesn't support sign-extension of
2779   // 8bit operands
2780   int encode = dst->encoding();
2781   if (encode == 0) {
2782     emit_int8((unsigned char)0xA9);
2783   } else {
2784     encode = prefix_and_encode(encode);
2785     emit_int8((unsigned char)0xF7);
2786     emit_int8((unsigned char)(0xC0 | encode));
2787   }
2788   emit_int32(imm32);
2789 }
2790 
2791 void Assembler::testl(Register dst, Register src) {
2792   (void) prefix_and_encode(dst->encoding(), src->encoding());
2793   emit_arith(0x85, 0xC0, dst, src);
2794 }
2795 
2796 void Assembler::testl(Register dst, Address  src) {
2797   InstructionMark im(this);
2798   prefix(src, dst);
2799   emit_int8((unsigned char)0x85);
2800   emit_operand(dst, src);
2801 }
2802 
2803 void Assembler::ucomisd(XMMRegister dst, Address src) {
2804   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2805   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2806 }
2807 
2808 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {


4703   emit_arith(0x81, 0xC0, dst, imm32);
4704 }
4705 
4706 void Assembler::addq(Register dst, Address src) {
4707   InstructionMark im(this);
4708   prefixq(src, dst);
4709   emit_int8(0x03);
4710   emit_operand(dst, src);
4711 }
4712 
4713 void Assembler::addq(Register dst, Register src) {
4714   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4715   emit_arith(0x03, 0xC0, dst, src);
4716 }
4717 
4718 void Assembler::andq(Address dst, int32_t imm32) {
4719   InstructionMark im(this);
4720   prefixq(dst);
4721   emit_int8((unsigned char)0x81);
4722   emit_operand(rsp, dst, 4);
4723   emit_int32(imm32);
4724 }
4725 
4726 void Assembler::andq(Register dst, int32_t imm32) {
4727   (void) prefixq_and_encode(dst->encoding());
4728   emit_arith(0x81, 0xE0, dst, imm32);
4729 }
4730 
4731 void Assembler::andq(Register dst, Address src) {
4732   InstructionMark im(this);
4733   prefixq(src, dst);
4734   emit_int8(0x23);
4735   emit_operand(dst, src);
4736 }
4737 
4738 void Assembler::andq(Register dst, Register src) {
4739   (int) prefixq_and_encode(dst->encoding(), src->encoding());
4740   emit_arith(0x23, 0xC0, dst, src);
4741 }
4742 
4743 void Assembler::bsfq(Register dst, Register src) {


4776 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4777   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4778   emit_int8(0x0F);
4779   emit_int8(0x40 | cc);
4780   emit_int8((unsigned char)(0xC0 | encode));
4781 }
4782 
4783 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4784   InstructionMark im(this);
4785   prefixq(src, dst);
4786   emit_int8(0x0F);
4787   emit_int8(0x40 | cc);
4788   emit_operand(dst, src);
4789 }
4790 
4791 void Assembler::cmpq(Address dst, int32_t imm32) {
4792   InstructionMark im(this);
4793   prefixq(dst);
4794   emit_int8((unsigned char)0x81);
4795   emit_operand(rdi, dst, 4);
4796   emit_int32(imm32);
4797 }
4798 
4799 void Assembler::cmpq(Register dst, int32_t imm32) {
4800   (void) prefixq_and_encode(dst->encoding());
4801   emit_arith(0x81, 0xF8, dst, imm32);
4802 }
4803 
4804 void Assembler::cmpq(Address dst, Register src) {
4805   InstructionMark im(this);
4806   prefixq(dst, src);
4807   emit_int8(0x3B);
4808   emit_operand(src, dst);
4809 }
4810 
4811 void Assembler::cmpq(Register dst, Register src) {
4812   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4813   emit_arith(0x3B, 0xC0, dst, src);
4814 }
4815 
4816 void Assembler::cmpq(Register dst, Address  src) {


4915   emit_int8((unsigned char)0xF7);
4916   emit_int8((unsigned char)(0xF8 | encode));
4917 }
4918 
4919 void Assembler::imulq(Register dst, Register src) {
4920   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4921   emit_int8(0x0F);
4922   emit_int8((unsigned char)0xAF);
4923   emit_int8((unsigned char)(0xC0 | encode));
4924 }
4925 
4926 void Assembler::imulq(Register dst, Register src, int value) {
4927   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4928   if (is8bit(value)) {
4929     emit_int8(0x6B);
4930     emit_int8((unsigned char)(0xC0 | encode));
4931     emit_int8(value & 0xFF);
4932   } else {
4933     emit_int8(0x69);
4934     emit_int8((unsigned char)(0xC0 | encode));
4935     emit_int32(value);
4936   }
4937 }
4938 
4939 void Assembler::incl(Register dst) {
4940   // Don't use it directly. Use MacroAssembler::incrementl() instead.
4941   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4942   int encode = prefix_and_encode(dst->encoding());
4943   emit_int8((unsigned char)0xFF);
4944   emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946 
4947 void Assembler::incq(Register dst) {
4948   // Don't use it directly. Use MacroAssembler::incrementq() instead.
4949   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4950   int encode = prefixq_and_encode(dst->encoding());
4951   emit_int8((unsigned char)0xFF);
4952   emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954 
4955 void Assembler::incq(Address dst) {


5068   emit_int8(0x0F);
5069   emit_int8((unsigned char)0xBE);
5070   emit_operand(dst, src);
5071 }
5072 
5073 void Assembler::movsbq(Register dst, Register src) {
5074   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5075   emit_int8(0x0F);
5076   emit_int8((unsigned char)0xBE);
5077   emit_int8((unsigned char)(0xC0 | encode));
5078 }
5079 
5080 void Assembler::movslq(Register dst, int32_t imm32) {
5081   // dbx shows movslq(rcx, 3) as movq     $0x0000000049000000,(%rbx)
5082   // and movslq(r8, 3); as movl     $0x0000000048000000,(%rbx)
5083   // as a result we shouldn't use until tested at runtime...
5084   ShouldNotReachHere();
5085   InstructionMark im(this);
5086   int encode = prefixq_and_encode(dst->encoding());
5087   emit_int8((unsigned char)(0xC7 | encode));
5088   emit_int32(imm32);
5089 }
5090 
5091 void Assembler::movslq(Address dst, int32_t imm32) {
5092   assert(is_simm32(imm32), "lost bits");
5093   InstructionMark im(this);
5094   prefixq(dst);
5095   emit_int8((unsigned char)0xC7);
5096   emit_operand(rax, dst, 4);
5097   emit_int32(imm32);
5098 }
5099 
5100 void Assembler::movslq(Register dst, Address src) {
5101   InstructionMark im(this);
5102   prefixq(src, dst);
5103   emit_int8(0x63);
5104   emit_operand(dst, src);
5105 }
5106 
5107 void Assembler::movslq(Register dst, Register src) {
5108   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5109   emit_int8(0x63);
5110   emit_int8((unsigned char)(0xC0 | encode));
5111 }
5112 
5113 void Assembler::movswq(Register dst, Address src) {
5114   InstructionMark im(this);
5115   prefixq(src, dst);
5116   emit_int8(0x0F);
5117   emit_int8((unsigned char)0xBF);


5155   emit_int8((unsigned char)(0xC0 | encode));
5156 }
5157 
5158 void Assembler::negq(Register dst) {
5159   int encode = prefixq_and_encode(dst->encoding());
5160   emit_int8((unsigned char)0xF7);
5161   emit_int8((unsigned char)(0xD8 | encode));
5162 }
5163 
5164 void Assembler::notq(Register dst) {
5165   int encode = prefixq_and_encode(dst->encoding());
5166   emit_int8((unsigned char)0xF7);
5167   emit_int8((unsigned char)(0xD0 | encode));
5168 }
5169 
5170 void Assembler::orq(Address dst, int32_t imm32) {
5171   InstructionMark im(this);
5172   prefixq(dst);
5173   emit_int8((unsigned char)0x81);
5174   emit_operand(rcx, dst, 4);
5175   emit_int32(imm32);
5176 }
5177 
5178 void Assembler::orq(Register dst, int32_t imm32) {
5179   (void) prefixq_and_encode(dst->encoding());
5180   emit_arith(0x81, 0xC8, dst, imm32);
5181 }
5182 
5183 void Assembler::orq(Register dst, Address src) {
5184   InstructionMark im(this);
5185   prefixq(src, dst);
5186   emit_int8(0x0B);
5187   emit_operand(dst, src);
5188 }
5189 
5190 void Assembler::orq(Register dst, Register src) {
5191   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5192   emit_arith(0x0B, 0xC0, dst, src);
5193 }
5194 
5195 void Assembler::popa() { // 64bit


5390 }
5391 
5392 void Assembler::subq(Register dst, Register src) {
5393   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5394   emit_arith(0x2B, 0xC0, dst, src);
5395 }
5396 
5397 void Assembler::testq(Register dst, int32_t imm32) {
5398   // not using emit_arith because test
5399   // doesn't support sign-extension of
5400   // 8bit operands
5401   int encode = dst->encoding();
5402   if (encode == 0) {
5403     prefix(REX_W);
5404     emit_int8((unsigned char)0xA9);
5405   } else {
5406     encode = prefixq_and_encode(encode);
5407     emit_int8((unsigned char)0xF7);
5408     emit_int8((unsigned char)(0xC0 | encode));
5409   }
5410   emit_int32(imm32);
5411 }
5412 
5413 void Assembler::testq(Register dst, Register src) {
5414   (void) prefixq_and_encode(dst->encoding(), src->encoding());
5415   emit_arith(0x85, 0xC0, dst, src);
5416 }
5417 
5418 void Assembler::xaddq(Address dst, Register src) {
5419   InstructionMark im(this);
5420   prefixq(dst, src);
5421   emit_int8(0x0F);
5422   emit_int8((unsigned char)0xC1);
5423   emit_operand(src, dst);
5424 }
5425 
5426 void Assembler::xchgq(Register dst, Address src) {
5427   InstructionMark im(this);
5428   prefixq(src, dst);
5429   emit_int8((unsigned char)0x87);
5430   emit_operand(dst, src);


src/cpu/x86/vm/assembler_x86.cpp
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