--- old/src/cpu/x86/vm/assembler_x86.cpp	2014-04-24 15:52:55.000000000 -1000
+++ new/src/cpu/x86/vm/assembler_x86.cpp	2014-04-24 15:52:55.000000000 -1000
@@ -104,11 +104,9 @@
 }
 
 // exceedingly dangerous constructor
-Address::Address(int disp, address loc, relocInfo::relocType rtype) {
-  _base  = noreg;
-  _index = noreg;
-  _scale = no_scale;
-  _disp  = disp;
+Address::Address(int disp, address loc, relocInfo::relocType rtype) :
+  _scale(no_scale),
+  _disp(disp) {
   switch (rtype) {
     case relocInfo::external_word_type:
       _rspec = external_word_Relocation::spec(loc);
@@ -162,7 +160,7 @@
   if (disp_reloc != relocInfo::none) {
     rspec = Relocation::spec_simple(disp_reloc);
   }
-  bool valid_index = index != rsp->encoding();
+  bool valid_index = index != rsp.encoding();
   if (valid_index) {
     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
     madr._rspec = rspec;
@@ -206,8 +204,8 @@
   emit_int32(data);
 }
 
-static int encode(Register r) {
-  int enc = r->encoding();
+static int encode(AbstractRegister r) {
+  int enc = r.encoding();
   if (enc >= 8) {
     enc -= 8;
   }
@@ -215,7 +213,7 @@
 }
 
 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
-  assert(dst->has_byte_register(), "must have byte register");
+  assert(dst.has_byte_register(), "must have byte register");
   assert(isByte(op1) && isByte(op2), "wrong opcode");
   assert(isByte(imm8), "not a byte");
   assert((op1 & 0x01) == 0, "should be 8bit operation");
@@ -273,7 +271,7 @@
 }
 
 
-void Assembler::emit_operand(Register reg, Register base, Register index,
+void Assembler::emit_operand(AbstractRegister reg, Register base, Register index,
                              Address::ScaleFactor scale, int disp,
                              RelocationHolder const& rspec,
                              int rip_relative_correction) {
@@ -282,11 +280,11 @@
   // Encode the registers as needed in the fields they are used in
 
   int regenc = encode(reg) << 3;
-  int indexenc = index->is_valid() ? encode(index) << 3 : 0;
-  int baseenc = base->is_valid() ? encode(base) : 0;
+  int indexenc = index.is_valid() ? encode(index) << 3 : 0;
+  int baseenc = base.is_valid() ? encode(base) : 0;
 
-  if (base->is_valid()) {
-    if (index->is_valid()) {
+  if (base.is_valid()) {
+    if (index.is_valid()) {
       assert(scale != Address::no_scale, "inconsistent address");
       // [base + index*scale + disp]
       if (disp == 0 && rtype == relocInfo::none  &&
@@ -352,7 +350,7 @@
       }
     }
   } else {
-    if (index->is_valid()) {
+    if (index.is_valid()) {
       assert(scale != Address::no_scale, "inconsistent address");
       // [index*scale + disp]
       // [00 reg 100][ss index 101] disp32
@@ -391,12 +389,6 @@
   }
 }
 
-void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
-                             Address::ScaleFactor scale, int disp,
-                             RelocationHolder const& rspec) {
-  emit_operand((Register)reg, base, index, scale, disp, rspec);
-}
-
 // Secret local extension to Assembler::WhichOperand:
 #define end_pc_operand (_WhichOperand_limit)
 
@@ -842,7 +834,7 @@
 #endif // ASSERT
 
 void Assembler::emit_operand32(Register reg, Address adr) {
-  assert(reg->encoding() < 8, "no extended registers");
+  assert(reg.encoding() < 8, "no extended registers");
   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
                adr._rspec);
@@ -863,13 +855,13 @@
 // MMX operations
 void Assembler::emit_operand(MMXRegister reg, Address adr) {
   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
-  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
 }
 
 // work around gcc (3.2.1-7a) bug
 void Assembler::emit_operand(Address adr, MMXRegister reg) {
   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
-  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
 }
 
 
@@ -909,7 +901,7 @@
 }
 
 void Assembler::adcl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x13, 0xC0, dst, src);
 }
 
@@ -939,7 +931,7 @@
 }
 
 void Assembler::addl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x03, 0xC0, dst, src);
 }
 
@@ -1085,7 +1077,7 @@
 }
 
 void Assembler::andl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x23, 0xC0, dst, src);
 }
 
@@ -1105,21 +1097,21 @@
 }
 
 void Assembler::bsfl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBC);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::bsrl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBD);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::bswapl(Register reg) { // bswap
-  int encode = prefix_and_encode(reg->encoding());
+  int encode = prefix_and_encode(reg.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)(0xC8 | encode));
 }
@@ -1192,7 +1184,7 @@
 }
 
 void Assembler::call(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8((unsigned char)(0xD0 | encode));
 }
@@ -1228,7 +1220,7 @@
 
 void Assembler::cmovl(Condition cc, Register dst, Register src) {
   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8(0x40 | cc);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -1265,7 +1257,7 @@
 }
 
 void Assembler::cmpl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x3B, 0xC0, dst, src);
 }
 
@@ -1432,19 +1424,19 @@
 }
 
 void Assembler::idivl(Register src) {
-  int encode = prefix_and_encode(src->encoding());
+  int encode = prefix_and_encode(src.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xF8 | encode));
 }
 
 void Assembler::divl(Register src) { // Unsigned
-  int encode = prefix_and_encode(src->encoding());
+  int encode = prefix_and_encode(src.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xF0 | encode));
 }
 
 void Assembler::imull(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xAF);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -1452,7 +1444,7 @@
 
 
 void Assembler::imull(Register dst, Register src, int value) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   if (is8bit(value)) {
     emit_int8(0x6B);
     emit_int8((unsigned char)(0xC0 | encode));
@@ -1574,7 +1566,7 @@
 }
 
 void Assembler::jmp(Register entry) {
-  int encode = prefix_and_encode(entry->encoding());
+  int encode = prefix_and_encode(entry.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8((unsigned char)(0xE0 | encode));
 }
@@ -1644,7 +1636,7 @@
 void Assembler::lzcntl(Register dst, Register src) {
   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
   emit_int8((unsigned char)0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBD);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -1680,7 +1672,7 @@
 }
 
 void Assembler::movb(Register dst, Address src) {
-  NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
+  NOT_LP64(assert(dst.has_byte_register(), "must have byte register"));
   InstructionMark im(this);
   prefix(src, dst, true);
   emit_int8((unsigned char)0x8A);
@@ -1698,7 +1690,7 @@
 
 
 void Assembler::movb(Address dst, Register src) {
-  assert(src->has_byte_register(), "must have byte register");
+  assert(src.has_byte_register(), "must have byte register");
   InstructionMark im(this);
   prefix(dst, src, true);
   emit_int8((unsigned char)0x88);
@@ -1796,13 +1788,13 @@
 // Uses zero extension on 64bit
 
 void Assembler::movl(Register dst, int32_t imm32) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)(0xB8 | encode));
   emit_int32(imm32);
 }
 
 void Assembler::movl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x8B);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -1882,8 +1874,8 @@
 }
 
 void Assembler::movsbl(Register dst, Register src) { // movsxb
-  NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
-  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+  NOT_LP64(assert(src.has_byte_register(), "must have byte register"));
+  int encode = prefix_and_encode(dst.encoding(), src.encoding(), true);
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBE);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -1934,7 +1926,7 @@
 }
 
 void Assembler::movswl(Register dst, Register src) { // movsxw
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBF);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -1975,8 +1967,8 @@
 }
 
 void Assembler::movzbl(Register dst, Register src) { // movzxb
-  NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
-  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+  NOT_LP64(assert(src.has_byte_register(), "must have byte register"));
+  int encode = prefix_and_encode(dst.encoding(), src.encoding(), true);
   emit_int8(0x0F);
   emit_int8((unsigned char)0xB6);
   emit_int8(0xC0 | encode);
@@ -1991,7 +1983,7 @@
 }
 
 void Assembler::movzwl(Register dst, Register src) { // movzxw
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xB7);
   emit_int8(0xC0 | encode);
@@ -2005,7 +1997,7 @@
 }
 
 void Assembler::mull(Register src) {
-  int encode = prefix_and_encode(src->encoding());
+  int encode = prefix_and_encode(src.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xE0 | encode));
 }
@@ -2031,7 +2023,7 @@
 }
 
 void Assembler::negl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xD8 | encode));
 }
@@ -2290,7 +2282,7 @@
 }
 
 void Assembler::notl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xD0 | encode));
 }
@@ -2314,7 +2306,7 @@
 }
 
 void Assembler::orl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x0B, 0xC0, dst, src);
 }
 
@@ -2366,7 +2358,7 @@
 
 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
   assert(VM_Version::supports_sse4_1(), "");
-  int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
+  int encode = simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
   emit_int8(0x16);
   emit_int8((unsigned char)(0xC0 | encode));
   emit_int8(imm8);
@@ -2374,7 +2366,7 @@
 
 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
   assert(VM_Version::supports_sse4_1(), "");
-  int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
+  int encode = simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
   emit_int8(0x16);
   emit_int8((unsigned char)(0xC0 | encode));
   emit_int8(imm8);
@@ -2382,7 +2374,7 @@
 
 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
   assert(VM_Version::supports_sse4_1(), "");
-  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
+  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src.encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
   emit_int8(0x22);
   emit_int8((unsigned char)(0xC0 | encode));
   emit_int8(imm8);
@@ -2390,7 +2382,7 @@
 
 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
   assert(VM_Version::supports_sse4_1(), "");
-  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
+  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src.encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
   emit_int8(0x22);
   emit_int8((unsigned char)(0xC0 | encode));
   emit_int8(imm8);
@@ -2413,7 +2405,7 @@
 
 // generic
 void Assembler::pop(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8(0x58 | encode);
 }
 
@@ -2430,7 +2422,7 @@
 void Assembler::popcntl(Register dst, Register src) {
   assert(VM_Version::supports_popcnt(), "must support");
   emit_int8((unsigned char)0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xB8);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -2589,7 +2581,7 @@
   InstructionMark im(this);
   bool vector256 = true;
   assert(dst != xnoreg, "sanity");
-  int dst_enc = dst->encoding();
+  int dst_enc = dst.encoding();
   // swap src<->dst for encoding
   vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
   emit_int8(0x17);
@@ -2639,7 +2631,7 @@
 }
 
 void Assembler::push(Register src) {
-  int encode = prefix_and_encode(src->encoding());
+  int encode = prefix_and_encode(src.encoding());
 
   emit_int8(0x50 | encode);
 }
@@ -2660,7 +2652,7 @@
 
 void Assembler::rcll(Register dst, int imm8) {
   assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   if (imm8 == 1) {
     emit_int8((unsigned char)0xD1);
     emit_int8((unsigned char)(0xD0 | encode));
@@ -2737,7 +2729,7 @@
 }
 
 void Assembler::sarl(Register dst, int imm8) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   assert(isShiftCount(imm8), "illegal shift count");
   if (imm8 == 1) {
     emit_int8((unsigned char)0xD1);
@@ -2750,7 +2742,7 @@
 }
 
 void Assembler::sarl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8((unsigned char)(0xF8 | encode));
 }
@@ -2775,13 +2767,13 @@
 }
 
 void Assembler::sbbl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x1B, 0xC0, dst, src);
 }
 
 void Assembler::setb(Condition cc, Register dst) {
   assert(0 <= cc && cc < 16, "illegal cc");
-  int encode = prefix_and_encode(dst->encoding(), true);
+  int encode = prefix_and_encode(dst.encoding(), true);
   emit_int8(0x0F);
   emit_int8((unsigned char)0x90 | cc);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -2789,7 +2781,7 @@
 
 void Assembler::shll(Register dst, int imm8) {
   assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   if (imm8 == 1 ) {
     emit_int8((unsigned char)0xD1);
     emit_int8((unsigned char)(0xE0 | encode));
@@ -2801,21 +2793,21 @@
 }
 
 void Assembler::shll(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8((unsigned char)(0xE0 | encode));
 }
 
 void Assembler::shrl(Register dst, int imm8) {
   assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xC1);
   emit_int8((unsigned char)(0xE8 | encode));
   emit_int8(imm8);
 }
 
 void Assembler::shrl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8((unsigned char)(0xE8 | encode));
 }
@@ -2890,7 +2882,7 @@
 }
 
 void Assembler::subl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x2B, 0xC0, dst, src);
 }
 
@@ -2915,8 +2907,8 @@
 }
 
 void Assembler::testb(Register dst, int imm8) {
-  NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
-  (void) prefix_and_encode(dst->encoding(), true);
+  NOT_LP64(assert(dst.has_byte_register(), "must have byte register"));
+  (void) prefix_and_encode(dst.encoding(), true);
   emit_arith_b(0xF6, 0xC0, dst, imm8);
 }
 
@@ -2924,7 +2916,7 @@
   // not using emit_arith because test
   // doesn't support sign-extension of
   // 8bit operands
-  int encode = dst->encoding();
+  int encode = dst.encoding();
   if (encode == 0) {
     emit_int8((unsigned char)0xA9);
   } else {
@@ -2936,7 +2928,7 @@
 }
 
 void Assembler::testl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x85, 0xC0, dst, src);
 }
 
@@ -2950,7 +2942,7 @@
 void Assembler::tzcntl(Register dst, Register src) {
   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
   emit_int8((unsigned char)0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBC);
   emit_int8((unsigned char)0xC0 | encode);
@@ -2959,7 +2951,7 @@
 void Assembler::tzcntq(Register dst, Register src) {
   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
   emit_int8((unsigned char)0xF3);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBC);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -3025,7 +3017,7 @@
 }
 
 void Assembler::xchgl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  int encode = prefix_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x87);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -3055,7 +3047,7 @@
 }
 
 void Assembler::xorl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  (void) prefix_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x33, 0xC0, dst, src);
 }
 
@@ -3500,8 +3492,8 @@
 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
   assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
   InstructionMark im(this);
-  int dst_enc = dst->encoding();
-  int nds_enc = nds->is_valid() ? nds->encoding() : 0;
+  int dst_enc = dst.encoding();
+  int nds_enc = nds.is_valid() ? nds.encoding() : 0;
   vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
   emit_int8(0x40);
   emit_operand(dst, src);
@@ -3784,7 +3776,7 @@
   InstructionMark im(this);
   bool vector256 = true;
   assert(dst != xnoreg, "sanity");
-  int dst_enc = dst->encoding();
+  int dst_enc = dst.encoding();
   // swap src<->dst for encoding
   vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
   emit_int8(0x18);
@@ -3798,7 +3790,7 @@
   InstructionMark im(this);
   bool vector256 = true;
   assert(src != xnoreg, "sanity");
-  int src_enc = src->encoding();
+  int src_enc = src.encoding();
   vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
   emit_int8(0x19);
   emit_operand(src, dst);
@@ -3822,7 +3814,7 @@
   InstructionMark im(this);
   bool vector256 = true;
   assert(dst != xnoreg, "sanity");
-  int dst_enc = dst->encoding();
+  int dst_enc = dst.encoding();
   // swap src<->dst for encoding
   vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
   emit_int8(0x38);
@@ -3836,7 +3828,7 @@
   InstructionMark im(this);
   bool vector256 = true;
   assert(src != xnoreg, "sanity");
-  int src_enc = src->encoding();
+  int src_enc = src.encoding();
   vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
   emit_int8(0x39);
   emit_operand(src, dst);
@@ -3877,7 +3869,7 @@
   // NO PREFIX AS NEVER 64BIT
   InstructionMark im(this);
   emit_int8((unsigned char)0x81);
-  emit_int8((unsigned char)(0xF8 | src1->encoding()));
+  emit_int8((unsigned char)(0xF8 | src1.encoding()));
   emit_data(imm32, rspec, 0);
 }
 
@@ -3901,7 +3893,7 @@
 
 void Assembler::decl(Register dst) {
   // Don't use it directly. Use MacroAssembler::decrementl() instead.
- emit_int8(0x48 | dst->encoding());
+ emit_int8(0x48 | dst.encoding());
 }
 
 #endif // _LP64
@@ -4424,8 +4416,8 @@
 
 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
   if (UseAVX > 0) {
-    int xreg_enc = xreg->encoding();
-    int  nds_enc = nds->is_valid() ? nds->encoding() : 0;
+    int xreg_enc = xreg.encoding();
+    int  nds_enc = nds.is_valid() ? nds.encoding() : 0;
     vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
   } else {
     assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
@@ -4434,10 +4426,10 @@
 }
 
 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
-  int dst_enc = dst->encoding();
-  int src_enc = src->encoding();
+  int dst_enc = dst.encoding();
+  int src_enc = src.encoding();
   if (UseAVX > 0) {
-    int nds_enc = nds->is_valid() ? nds->encoding() : 0;
+    int nds_enc = nds.is_valid() ? nds.encoding() : 0;
     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
   } else {
     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
@@ -4492,7 +4484,7 @@
 
 void Assembler::incl(Register dst) {
   // Don't use it directly. Use MacroAssembler::incrementl() instead.
-  emit_int8(0x40 | dst->encoding());
+  emit_int8(0x40 | dst.encoding());
 }
 
 void Assembler::lea(Register dst, Address src) {
@@ -4508,7 +4500,7 @@
 
 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
   InstructionMark im(this);
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)(0xB8 | encode));
   emit_data((int)imm32, rspec, 0);
 }
@@ -4530,25 +4522,25 @@
 void Assembler::set_byte_if_not_zero(Register dst) {
   emit_int8(0x0F);
   emit_int8((unsigned char)0x95);
-  emit_int8((unsigned char)(0xE0 | dst->encoding()));
+  emit_int8((unsigned char)(0xE0 | dst.encoding()));
 }
 
 void Assembler::shldl(Register dst, Register src) {
   emit_int8(0x0F);
   emit_int8((unsigned char)0xA5);
-  emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
+  emit_int8((unsigned char)(0xC0 | src.encoding() << 3 | dst.encoding()));
 }
 
 void Assembler::shrdl(Register dst, Register src) {
   emit_int8(0x0F);
   emit_int8((unsigned char)0xAD);
-  emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
+  emit_int8((unsigned char)(0xC0 | src.encoding() << 3 | dst.encoding()));
 }
 
 #else // LP64
 
 void Assembler::set_byte_if_not_zero(Register dst) {
-  int enc = prefix_and_encode(dst->encoding(), true);
+  int enc = prefix_and_encode(dst.encoding(), true);
   emit_int8(0x0F);
   emit_int8((unsigned char)0x95);
   emit_int8((unsigned char)(0xE0 | enc));
@@ -4719,7 +4711,7 @@
 }
 
 void Assembler::prefix(Register reg) {
-  if (reg->encoding() >= 8) {
+  if (reg.encoding() >= 8) {
     prefix(REX_B);
   }
 }
@@ -4756,7 +4748,7 @@
 
 
 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
-  if (reg->encoding() < 8) {
+  if (reg.encoding() < 8) {
     if (adr.base_needs_rex()) {
       if (adr.index_needs_rex()) {
         prefix(REX_XB);
@@ -4766,7 +4758,7 @@
     } else {
       if (adr.index_needs_rex()) {
         prefix(REX_X);
-      } else if (byteinst && reg->encoding() >= 4 ) {
+      } else if (byteinst && reg.encoding() >= 4 ) {
         prefix(REX);
       }
     }
@@ -4788,7 +4780,7 @@
 }
 
 void Assembler::prefixq(Address adr, Register src) {
-  if (src->encoding() < 8) {
+  if (src.encoding() < 8) {
     if (adr.base_needs_rex()) {
       if (adr.index_needs_rex()) {
         prefix(REX_WXB);
@@ -4820,7 +4812,7 @@
 }
 
 void Assembler::prefix(Address adr, XMMRegister reg) {
-  if (reg->encoding() < 8) {
+  if (reg.encoding() < 8) {
     if (adr.base_needs_rex()) {
       if (adr.index_needs_rex()) {
         prefix(REX_XB);
@@ -4850,7 +4842,7 @@
 }
 
 void Assembler::prefixq(Address adr, XMMRegister src) {
-  if (src->encoding() < 8) {
+  if (src.encoding() < 8) {
     if (adr.base_needs_rex()) {
       if (adr.index_needs_rex()) {
         prefix(REX_WXB);
@@ -4882,7 +4874,7 @@
 }
 
 void Assembler::adcq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xD0, dst, imm32);
 }
 
@@ -4894,7 +4886,7 @@
 }
 
 void Assembler::adcq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x13, 0xC0, dst, src);
 }
 
@@ -4912,7 +4904,7 @@
 }
 
 void Assembler::addq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xC0, dst, imm32);
 }
 
@@ -4924,7 +4916,7 @@
 }
 
 void Assembler::addq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x03, 0xC0, dst, src);
 }
 
@@ -4937,7 +4929,7 @@
 }
 
 void Assembler::andq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xE0, dst, imm32);
 }
 
@@ -4949,7 +4941,7 @@
 }
 
 void Assembler::andq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x23, 0xC0, dst, src);
 }
 
@@ -4969,21 +4961,21 @@
 }
 
 void Assembler::bsfq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBC);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::bsrq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBD);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::bswapq(Register reg) {
-  int encode = prefixq_and_encode(reg->encoding());
+  int encode = prefixq_and_encode(reg.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)(0xC8 | encode));
 }
@@ -5046,7 +5038,7 @@
 }
 
 void Assembler::cmovq(Condition cc, Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8(0x40 | cc);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -5069,7 +5061,7 @@
 }
 
 void Assembler::cmpq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xF8, dst, imm32);
 }
 
@@ -5081,7 +5073,7 @@
 }
 
 void Assembler::cmpq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x3B, 0xC0, dst, src);
 }
 
@@ -5147,7 +5139,7 @@
 void Assembler::decl(Register dst) {
   // Don't use it directly. Use MacroAssembler::decrementl() instead.
   // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8((unsigned char)(0xC8 | encode));
 }
@@ -5155,7 +5147,7 @@
 void Assembler::decq(Register dst) {
   // Don't use it directly. Use MacroAssembler::decrementq() instead.
   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8(0xC8 | encode);
 }
@@ -5183,20 +5175,20 @@
 }
 
 void Assembler::idivq(Register src) {
-  int encode = prefixq_and_encode(src->encoding());
+  int encode = prefixq_and_encode(src.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xF8 | encode));
 }
 
 void Assembler::imulq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xAF);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::imulq(Register dst, Register src, int value) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   if (is8bit(value)) {
     emit_int8(0x6B);
     emit_int8((unsigned char)(0xC0 | encode));
@@ -5219,7 +5211,7 @@
 void Assembler::incl(Register dst) {
   // Don't use it directly. Use MacroAssembler::incrementl() instead.
   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -5227,7 +5219,7 @@
 void Assembler::incq(Register dst) {
   // Don't use it directly. Use MacroAssembler::incrementq() instead.
   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xFF);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -5253,21 +5245,21 @@
 
 void Assembler::mov64(Register dst, int64_t imm64) {
   InstructionMark im(this);
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)(0xB8 | encode));
   emit_int64(imm64);
 }
 
 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
   InstructionMark im(this);
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8(0xB8 | encode);
   emit_data64(imm64, rspec);
 }
 
 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
   InstructionMark im(this);
-  int encode = prefix_and_encode(dst->encoding());
+  int encode = prefix_and_encode(dst.encoding());
   emit_int8((unsigned char)(0xB8 | encode));
   emit_data((int)imm32, rspec, narrow_oop_operand);
 }
@@ -5282,7 +5274,7 @@
 
 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
   InstructionMark im(this);
-  int encode = prefix_and_encode(src1->encoding());
+  int encode = prefix_and_encode(src1.encoding());
   emit_int8((unsigned char)0x81);
   emit_int8((unsigned char)(0xF8 | encode));
   emit_data((int)imm32, rspec, narrow_oop_operand);
@@ -5299,7 +5291,7 @@
 void Assembler::lzcntq(Register dst, Register src) {
   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
   emit_int8((unsigned char)0xF3);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBD);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -5323,7 +5315,7 @@
 }
 
 void Assembler::movq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x8B);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -5351,7 +5343,7 @@
 }
 
 void Assembler::movsbq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xBE);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -5363,7 +5355,7 @@
   // as a result we shouldn't use until tested at runtime...
   ShouldNotReachHere();
   InstructionMark im(this);
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)(0xC7 | encode));
   emit_int32(imm32);
 }
@@ -5385,7 +5377,7 @@
 }
 
 void Assembler::movslq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x63);
   emit_int8((unsigned char)(0xC0 | encode));
 }
@@ -5399,7 +5391,7 @@
 }
 
 void Assembler::movswq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x0F);
   emit_int8((unsigned char)0xBF);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -5414,7 +5406,7 @@
 }
 
 void Assembler::movzbq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8(0x0F);
   emit_int8((unsigned char)0xB6);
   emit_int8(0xC0 | encode);
@@ -5429,20 +5421,20 @@
 }
 
 void Assembler::movzwq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x0F);
   emit_int8((unsigned char)0xB7);
   emit_int8((unsigned char)(0xC0 | encode));
 }
 
 void Assembler::negq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xD8 | encode));
 }
 
 void Assembler::notq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xF7);
   emit_int8((unsigned char)(0xD0 | encode));
 }
@@ -5456,7 +5448,7 @@
 }
 
 void Assembler::orq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xC8, dst, imm32);
 }
 
@@ -5468,7 +5460,7 @@
 }
 
 void Assembler::orq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x0B, 0xC0, dst, src);
 }
 
@@ -5506,7 +5498,7 @@
 void Assembler::popcntq(Register dst, Register src) {
   assert(VM_Version::supports_popcnt(), "must support");
   emit_int8((unsigned char)0xF3);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x0F);
   emit_int8((unsigned char)0xB8);
   emit_int8((unsigned char)(0xC0 | encode));
@@ -5553,7 +5545,7 @@
 
 void Assembler::rclq(Register dst, int imm8) {
   assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   if (imm8 == 1) {
     emit_int8((unsigned char)0xD1);
     emit_int8((unsigned char)(0xD0 | encode));
@@ -5565,7 +5557,7 @@
 }
 void Assembler::sarq(Register dst, int imm8) {
   assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   if (imm8 == 1) {
     emit_int8((unsigned char)0xD1);
     emit_int8((unsigned char)(0xF8 | encode));
@@ -5577,7 +5569,7 @@
 }
 
 void Assembler::sarq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8((unsigned char)(0xF8 | encode));
 }
@@ -5589,7 +5581,7 @@
 }
 
 void Assembler::sbbq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xD8, dst, imm32);
 }
 
@@ -5601,13 +5593,13 @@
 }
 
 void Assembler::sbbq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x1B, 0xC0, dst, src);
 }
 
 void Assembler::shlq(Register dst, int imm8) {
   assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   if (imm8 == 1) {
     emit_int8((unsigned char)0xD1);
     emit_int8((unsigned char)(0xE0 | encode));
@@ -5619,21 +5611,21 @@
 }
 
 void Assembler::shlq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8((unsigned char)(0xE0 | encode));
 }
 
 void Assembler::shrq(Register dst, int imm8) {
   assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xC1);
   emit_int8((unsigned char)(0xE8 | encode));
   emit_int8(imm8);
 }
 
 void Assembler::shrq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
+  int encode = prefixq_and_encode(dst.encoding());
   emit_int8((unsigned char)0xD3);
   emit_int8(0xE8 | encode);
 }
@@ -5652,13 +5644,13 @@
 }
 
 void Assembler::subq(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith(0x81, 0xE8, dst, imm32);
 }
 
 // Force generation of a 4 byte immediate value even if it fits into 8bit
 void Assembler::subq_imm32(Register dst, int32_t imm32) {
-  (void) prefixq_and_encode(dst->encoding());
+  (void) prefixq_and_encode(dst.encoding());
   emit_arith_imm32(0x81, 0xE8, dst, imm32);
 }
 
@@ -5670,7 +5662,7 @@
 }
 
 void Assembler::subq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x2B, 0xC0, dst, src);
 }
 
@@ -5678,7 +5670,7 @@
   // not using emit_arith because test
   // doesn't support sign-extension of
   // 8bit operands
-  int encode = dst->encoding();
+  int encode = dst.encoding();
   if (encode == 0) {
     prefix(REX_W);
     emit_int8((unsigned char)0xA9);
@@ -5691,7 +5683,7 @@
 }
 
 void Assembler::testq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x85, 0xC0, dst, src);
 }
 
@@ -5711,13 +5703,13 @@
 }
 
 void Assembler::xchgq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  int encode = prefixq_and_encode(dst.encoding(), src.encoding());
   emit_int8((unsigned char)0x87);
   emit_int8((unsigned char)(0xc0 | encode));
 }
 
 void Assembler::xorq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  (void) prefixq_and_encode(dst.encoding(), src.encoding());
   emit_arith(0x33, 0xC0, dst, src);
 }