1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29
30 class BiasedLockingCounters;
31
32 // Contains all the definitions needed for x86 assembly code generation.
33
34 // Address is an abstraction used to represent a memory location
35 // using any of the amd64 addressing modes with one object.
36 //
37 // Note: A register location is represented via a Register, not
38 // via an address for efficiency & simplicity reasons.
39
40 class ArrayAddress;
41
42 class Address VALUE_OBJ_CLASS_SPEC {
43 public:
44 enum ScaleFactor {
45 no_scale = -1,
46 times_1 = 0,
47 times_2 = 1,
48 times_4 = 2,
49 times_8 = 3,
50 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
51 };
52 static ScaleFactor times(int size) {
53 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
54 if (size == 8) return times_8;
55 if (size == 4) return times_4;
56 if (size == 2) return times_2;
57 return times_1;
58 }
59 static int scale_size(ScaleFactor scale) {
60 assert(scale != no_scale, "");
61 assert(((1 << (int)times_1) == 1 &&
62 (1 << (int)times_2) == 2 &&
63 (1 << (int)times_4) == 4 &&
64 (1 << (int)times_8) == 8), "");
65 return (1 << (int)scale);
66 }
67
68 private:
69 Register _base;
70 Register _index;
71 ScaleFactor _scale;
72 int _disp;
73 RelocationHolder _rspec;
74
75 // Easily misused constructors make them private
76 // %%% can we make these go away?
77 NOT_LP64(Address(address loc, RelocationHolder spec);)
78 Address(int disp, address loc, relocInfo::relocType rtype);
79 Address(int disp, address loc, RelocationHolder spec);
80
81 public:
82
83 int disp() { return _disp; }
84 // creation
85 Address()
86 : _base(noreg),
87 _index(noreg),
88 _scale(no_scale),
89 _disp(0) {
90 }
91
92 // No default displacement otherwise Register can be implicitly
93 // converted to 0(Register) which is quite a different animal.
94
95 Address(Register base, int disp)
96 : _base(base),
97 _index(noreg),
98 _scale(no_scale),
99 _disp(disp) {
100 }
101
102 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
103 : _base (base),
104 _index(index),
105 _scale(scale),
106 _disp (disp) {
107 assert(!index.is_valid() == (scale == Address::no_scale),
108 "inconsistent address");
109 }
110
111 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
112 : _base (base),
113 _index(index.register_or_noreg()),
114 _scale(scale),
115 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
116 if (!index.is_register()) scale = Address::no_scale;
117 assert(!_index.is_valid() == (scale == Address::no_scale),
118 "inconsistent address");
119 }
120
121 Address plus_disp(int disp) const {
122 Address a = (*this);
123 a._disp += disp;
124 return a;
125 }
126 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
127 Address a = (*this);
128 a._disp += disp.constant_or_zero() * scale_size(scale);
129 if (disp.is_register()) {
130 assert(!a.index().is_valid(), "competing indexes");
131 a._index = disp.as_register();
132 a._scale = scale;
133 }
134 return a;
135 }
136 bool is_same_address(Address a) const {
137 // disregard _rspec
138 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
139 }
140
141 // The following two overloads are used in connection with the
142 // ByteSize type (see sizes.hpp). They simplify the use of
143 // ByteSize'd arguments in assembly code. Note that their equivalent
144 // for the optimized build are the member functions with int disp
145 // argument since ByteSize is mapped to an int type in that case.
146 //
147 // Note: DO NOT introduce similar overloaded functions for WordSize
148 // arguments as in the optimized mode, both ByteSize and WordSize
149 // are mapped to the same type and thus the compiler cannot make a
150 // distinction anymore (=> compiler errors).
151
152 #ifdef ASSERT
153 Address(Register base, ByteSize disp)
154 : _base(base),
155 _index(noreg),
156 _scale(no_scale),
157 _disp(in_bytes(disp)) {
158 }
159
160 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
161 : _base(base),
162 _index(index),
163 _scale(scale),
164 _disp(in_bytes(disp)) {
165 assert(!index.is_valid() == (scale == Address::no_scale),
166 "inconsistent address");
167 }
168
169 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
170 : _base (base),
171 _index(index.register_or_noreg()),
172 _scale(scale),
173 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
174 if (!index.is_register()) scale = Address::no_scale;
175 assert(!_index.is_valid() == (scale == Address::no_scale),
176 "inconsistent address");
177 }
178
179 #endif // ASSERT
180
181 // accessors
182 bool uses(Register reg) const { return _base == reg || _index == reg; }
183 Register base() const { return _base; }
184 Register index() const { return _index; }
185 ScaleFactor scale() const { return _scale; }
186 int disp() const { return _disp; }
187
188 // Convert the raw encoding form into the form expected by the constructor for
189 // Address. An index of 4 (rsp) corresponds to having no index, so convert
190 // that to noreg for the Address constructor.
191 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
192
193 static Address make_array(ArrayAddress);
194
195 private:
196 bool base_needs_rex() const {
197 return _base != noreg && _base.encoding() >= 8;
198 }
199
200 bool index_needs_rex() const {
201 return _index != noreg && _index.encoding() >= 8;
202 }
203
204 relocInfo::relocType reloc() const { return _rspec.type(); }
205
206 friend class Assembler;
207 friend class MacroAssembler;
208 friend class LIR_Assembler; // base/index/scale/disp
209 };
210
211 //
212 // AddressLiteral has been split out from Address because operands of this type
213 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
214 // the few instructions that need to deal with address literals are unique and the
215 // MacroAssembler does not have to implement every instruction in the Assembler
216 // in order to search for address literals that may need special handling depending
217 // on the instruction and the platform. As small step on the way to merging i486/amd64
218 // directories.
219 //
220 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
221 friend class ArrayAddress;
222 RelocationHolder _rspec;
223 // Typically we use AddressLiterals we want to use their rval
224 // However in some situations we want the lval (effect address) of the item.
225 // We provide a special factory for making those lvals.
226 bool _is_lval;
227
228 // If the target is far we'll need to load the ea of this to
229 // a register to reach it. Otherwise if near we can do rip
230 // relative addressing.
231
232 address _target;
233
234 protected:
235 // creation
236 AddressLiteral()
237 : _is_lval(false),
238 _target(NULL)
239 {}
240
241 public:
242
243
244 AddressLiteral(address target, relocInfo::relocType rtype);
245
246 AddressLiteral(address target, RelocationHolder const& rspec)
247 : _rspec(rspec),
248 _is_lval(false),
249 _target(target)
250 {}
251
252 AddressLiteral addr() {
253 AddressLiteral ret = *this;
254 ret._is_lval = true;
255 return ret;
256 }
257
258
259 private:
260
261 address target() { return _target; }
262 bool is_lval() { return _is_lval; }
263
264 relocInfo::relocType reloc() const { return _rspec.type(); }
265 const RelocationHolder& rspec() const { return _rspec; }
266
267 friend class Assembler;
268 friend class MacroAssembler;
269 friend class Address;
270 friend class LIR_Assembler;
271 };
272
273 // Convience classes
274 class RuntimeAddress: public AddressLiteral {
275
276 public:
277
278 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
279
280 };
281
282 class ExternalAddress: public AddressLiteral {
283 private:
284 static relocInfo::relocType reloc_for_target(address target) {
285 // Sometimes ExternalAddress is used for values which aren't
286 // exactly addresses, like the card table base.
287 // external_word_type can't be used for values in the first page
288 // so just skip the reloc in that case.
289 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
290 }
291
292 public:
293
294 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
295
296 };
297
298 class InternalAddress: public AddressLiteral {
299
300 public:
301
302 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
303
304 };
305
306 // x86 can do array addressing as a single operation since disp can be an absolute
307 // address amd64 can't. We create a class that expresses the concept but does extra
308 // magic on amd64 to get the final result
309
310 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
311 private:
312
313 AddressLiteral _base;
314 Address _index;
315
316 public:
317
318 ArrayAddress() {};
319 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
320 AddressLiteral base() { return _base; }
321 Address index() { return _index; }
322
323 };
324
325 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
326
327 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
328 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
329 // is what you get. The Assembler is generating code into a CodeBuffer.
330
331 class Assembler : public AbstractAssembler {
332 friend class AbstractAssembler; // for the non-virtual hack
333 friend class LIR_Assembler; // as_Address()
334 friend class StubGenerator;
335
336 public:
337 enum Condition { // The x86 condition codes used for conditional jumps/moves.
338 zero = 0x4,
339 notZero = 0x5,
340 equal = 0x4,
341 notEqual = 0x5,
342 less = 0xc,
343 lessEqual = 0xe,
344 greater = 0xf,
345 greaterEqual = 0xd,
346 below = 0x2,
347 belowEqual = 0x6,
348 above = 0x7,
349 aboveEqual = 0x3,
350 overflow = 0x0,
351 noOverflow = 0x1,
352 carrySet = 0x2,
353 carryClear = 0x3,
354 negative = 0x8,
355 positive = 0x9,
356 parity = 0xa,
357 noParity = 0xb
358 };
359
360 enum Prefix {
361 // segment overrides
362 CS_segment = 0x2e,
363 SS_segment = 0x36,
364 DS_segment = 0x3e,
365 ES_segment = 0x26,
366 FS_segment = 0x64,
367 GS_segment = 0x65,
368
369 REX = 0x40,
370
371 REX_B = 0x41,
372 REX_X = 0x42,
373 REX_XB = 0x43,
374 REX_R = 0x44,
375 REX_RB = 0x45,
376 REX_RX = 0x46,
377 REX_RXB = 0x47,
378
379 REX_W = 0x48,
380
381 REX_WB = 0x49,
382 REX_WX = 0x4A,
383 REX_WXB = 0x4B,
384 REX_WR = 0x4C,
385 REX_WRB = 0x4D,
386 REX_WRX = 0x4E,
387 REX_WRXB = 0x4F,
388
389 VEX_3bytes = 0xC4,
390 VEX_2bytes = 0xC5
391 };
392
393 enum VexPrefix {
394 VEX_B = 0x20,
395 VEX_X = 0x40,
396 VEX_R = 0x80,
397 VEX_W = 0x80
398 };
399
400 enum VexSimdPrefix {
401 VEX_SIMD_NONE = 0x0,
402 VEX_SIMD_66 = 0x1,
403 VEX_SIMD_F3 = 0x2,
404 VEX_SIMD_F2 = 0x3
405 };
406
407 enum VexOpcode {
408 VEX_OPCODE_NONE = 0x0,
409 VEX_OPCODE_0F = 0x1,
410 VEX_OPCODE_0F_38 = 0x2,
411 VEX_OPCODE_0F_3A = 0x3
412 };
413
414 enum WhichOperand {
415 // input to locate_operand, and format code for relocations
416 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
417 disp32_operand = 1, // embedded 32-bit displacement or address
418 call32_operand = 2, // embedded 32-bit self-relative displacement
419 #ifndef _LP64
420 _WhichOperand_limit = 3
421 #else
422 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
423 _WhichOperand_limit = 4
424 #endif
425 };
426
427
428
429 // NOTE: The general philopsophy of the declarations here is that 64bit versions
430 // of instructions are freely declared without the need for wrapping them an ifdef.
431 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
432 // In the .cpp file the implementations are wrapped so that they are dropped out
433 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
434 // to the size it was prior to merging up the 32bit and 64bit assemblers.
435 //
436 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
437 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
438
439 private:
440
441
442 // 64bit prefixes
443 int prefix_and_encode(int reg_enc, bool byteinst = false);
444 int prefixq_and_encode(int reg_enc);
445
446 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
447 int prefixq_and_encode(int dst_enc, int src_enc);
448
449 void prefix(Register reg);
450 void prefix(Address adr);
451 void prefixq(Address adr);
452
453 void prefix(Address adr, Register reg, bool byteinst = false);
454 void prefix(Address adr, XMMRegister reg);
455 void prefixq(Address adr, Register reg);
456 void prefixq(Address adr, XMMRegister reg);
457
458 void prefetch_prefix(Address src);
459
460 void rex_prefix(Address adr, XMMRegister xreg,
461 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
462 int rex_prefix_and_encode(int dst_enc, int src_enc,
463 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
464
465 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
466 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
467 bool vector256);
468
469 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
470 VexSimdPrefix pre, VexOpcode opc,
471 bool vex_w, bool vector256);
472
473 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
474 VexSimdPrefix pre, bool vector256 = false) {
475 int dst_enc = dst.encoding();
476 int nds_enc = nds.is_valid() ? nds.encoding() : 0;
477 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
478 }
479
480 void vex_prefix_0F38(Register dst, Register nds, Address src) {
481 bool vex_w = false;
482 bool vector256 = false;
483 vex_prefix(src, nds.encoding(), dst.encoding(),
484 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
485 }
486
487 void vex_prefix_0F38_q(Register dst, Register nds, Address src) {
488 bool vex_w = true;
489 bool vector256 = false;
490 vex_prefix(src, nds.encoding(), dst.encoding(),
491 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
492 }
493 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
494 VexSimdPrefix pre, VexOpcode opc,
495 bool vex_w, bool vector256);
496
497 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) {
498 bool vex_w = false;
499 bool vector256 = false;
500 return vex_prefix_and_encode(dst.encoding(), nds.encoding(), src.encoding(),
501 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
502 }
503 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) {
504 bool vex_w = true;
505 bool vector256 = false;
506 return vex_prefix_and_encode(dst.encoding(), nds.encoding(), src.encoding(),
507 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
508 }
509 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
510 VexSimdPrefix pre, bool vector256 = false,
511 VexOpcode opc = VEX_OPCODE_0F) {
512 int src_enc = src.encoding();
513 int dst_enc = dst.encoding();
514 int nds_enc = nds.is_valid() ? nds.encoding() : 0;
515 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
516 }
517
518 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
519 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
520 bool rex_w = false, bool vector256 = false);
521
522 void simd_prefix(XMMRegister dst, Address src,
523 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
524 simd_prefix(dst, xnoreg, src, pre, opc);
525 }
526
527 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
528 simd_prefix(src, dst, pre);
529 }
530 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
531 VexSimdPrefix pre) {
532 bool rex_w = true;
533 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
534 }
535
536 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
537 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
538 bool rex_w = false, bool vector256 = false);
539
540 // Move/convert 32-bit integer value.
541 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
542 VexSimdPrefix pre) {
543 // It is OK to cast from Register to XMMRegister to pass argument here
544 // since only encoding is used in simd_prefix_and_encode() and number of
545 // Gen and Xmm registers are the same.
546 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src.encoding()), pre);
547 }
548 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
549 return simd_prefix_and_encode(dst, xnoreg, src, pre);
550 }
551 int simd_prefix_and_encode(Register dst, XMMRegister src,
552 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
553 return simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, pre, opc);
554 }
555
556 // Move/convert 64-bit integer value.
557 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
558 VexSimdPrefix pre) {
559 bool rex_w = true;
560 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src.encoding()), pre, VEX_OPCODE_0F, rex_w);
561 }
562 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
563 return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
564 }
565 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
566 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
567 bool rex_w = true;
568 return simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, pre, opc, rex_w);
569 }
570
571 // Helper functions for groups of instructions
572 void emit_arith_b(int op1, int op2, Register dst, int imm8);
573
574 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
575 // Force generation of a 4 byte immediate value even if it fits into 8bit
576 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
577 void emit_arith(int op1, int op2, Register dst, Register src);
578
579 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
580 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
581 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
582 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
583 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
584 Address src, VexSimdPrefix pre, bool vector256);
585 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
586 XMMRegister src, VexSimdPrefix pre, bool vector256);
587
588 void emit_operand(AbstractRegister reg,
589 Register base, Register index, Address::ScaleFactor scale,
590 int disp,
591 RelocationHolder const& rspec,
592 int rip_relative_correction = 0);
593
594 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
595
596 // operands that only take the original 32bit registers
597 void emit_operand32(Register reg, Address adr);
598
599 void emit_operand(XMMRegister reg, Address adr);
600
601 void emit_operand(MMXRegister reg, Address adr);
602
603 // workaround gcc (3.2.1-7) bug
604 void emit_operand(Address adr, MMXRegister reg);
605
606
607 // Immediate-to-memory forms
608 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
609
610 void emit_farith(int b1, int b2, int i);
611
612
613 protected:
614 #ifdef ASSERT
615 void check_relocation(RelocationHolder const& rspec, int format);
616 #endif
617
618 void emit_data(jint data, relocInfo::relocType rtype, int format);
619 void emit_data(jint data, RelocationHolder const& rspec, int format);
620 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
621 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
622
623 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
624
625 // These are all easily abused and hence protected
626
627 // 32BIT ONLY SECTION
628 #ifndef _LP64
629 // Make these disappear in 64bit mode since they would never be correct
630 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
631 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
632
633 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
634 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
635
636 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
637 #else
638 // 64BIT ONLY SECTION
639 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
640
641 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
642 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
643
644 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
645 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
646 #endif // _LP64
647
648 // These are unique in that we are ensured by the caller that the 32bit
649 // relative in these instructions will always be able to reach the potentially
650 // 64bit address described by entry. Since they can take a 64bit address they
651 // don't have the 32 suffix like the other instructions in this class.
652
653 void call_literal(address entry, RelocationHolder const& rspec);
654 void jmp_literal(address entry, RelocationHolder const& rspec);
655
656 // Avoid using directly section
657 // Instructions in this section are actually usable by anyone without danger
658 // of failure but have performance issues that are addressed my enhanced
659 // instructions which will do the proper thing base on the particular cpu.
660 // We protect them because we don't trust you...
661
662 // Don't use next inc() and dec() methods directly. INC & DEC instructions
663 // could cause a partial flag stall since they don't set CF flag.
664 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
665 // which call inc() & dec() or add() & sub() in accordance with
666 // the product flag UseIncDec value.
667
668 void decl(Register dst);
669 void decl(Address dst);
670 void decq(Register dst);
671 void decq(Address dst);
672
673 void incl(Register dst);
674 void incl(Address dst);
675 void incq(Register dst);
676 void incq(Address dst);
677
678 // New cpus require use of movsd and movss to avoid partial register stall
679 // when loading from memory. But for old Opteron use movlpd instead of movsd.
680 // The selection is done in MacroAssembler::movdbl() and movflt().
681
682 // Move Scalar Single-Precision Floating-Point Values
683 void movss(XMMRegister dst, Address src);
684 void movss(XMMRegister dst, XMMRegister src);
685 void movss(Address dst, XMMRegister src);
686
687 // Move Scalar Double-Precision Floating-Point Values
688 void movsd(XMMRegister dst, Address src);
689 void movsd(XMMRegister dst, XMMRegister src);
690 void movsd(Address dst, XMMRegister src);
691 void movlpd(XMMRegister dst, Address src);
692
693 // New cpus require use of movaps and movapd to avoid partial register stall
694 // when moving between registers.
695 void movaps(XMMRegister dst, XMMRegister src);
696 void movapd(XMMRegister dst, XMMRegister src);
697
698 // End avoid using directly
699
700
701 // Instruction prefixes
702 void prefix(Prefix p);
703
704 public:
705
706 // Creation
707 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
708
709 // Decoding
710 static address locate_operand(address inst, WhichOperand which);
711 static address locate_next_instruction(address inst);
712
713 // Utilities
714 static bool is_polling_page_far() NOT_LP64({ return false;});
715
716 // Generic instructions
717 // Does 32bit or 64bit as needed for the platform. In some sense these
718 // belong in macro assembler but there is no need for both varieties to exist
719
720 void lea(Register dst, Address src);
721
722 void mov(Register dst, Register src);
723
724 void pusha();
725 void popa();
726
727 void pushf();
728 void popf();
729
730 void push(int32_t imm32);
731
732 void push(Register src);
733
734 void pop(Register dst);
735
736 // These are dummies to prevent surprise implicit conversions to Register
737 void push(void* v);
738 void pop(void* v);
739
740 // These do register sized moves/scans
741 void rep_mov();
742 void rep_stos();
743 void rep_stosb();
744 void repne_scan();
745 #ifdef _LP64
746 void repne_scanl();
747 #endif
748
749 // Vanilla instructions in lexical order
750
751 void adcl(Address dst, int32_t imm32);
752 void adcl(Address dst, Register src);
753 void adcl(Register dst, int32_t imm32);
754 void adcl(Register dst, Address src);
755 void adcl(Register dst, Register src);
756
757 void adcq(Register dst, int32_t imm32);
758 void adcq(Register dst, Address src);
759 void adcq(Register dst, Register src);
760
761 void addl(Address dst, int32_t imm32);
762 void addl(Address dst, Register src);
763 void addl(Register dst, int32_t imm32);
764 void addl(Register dst, Address src);
765 void addl(Register dst, Register src);
766
767 void addq(Address dst, int32_t imm32);
768 void addq(Address dst, Register src);
769 void addq(Register dst, int32_t imm32);
770 void addq(Register dst, Address src);
771 void addq(Register dst, Register src);
772
773 void addr_nop_4();
774 void addr_nop_5();
775 void addr_nop_7();
776 void addr_nop_8();
777
778 // Add Scalar Double-Precision Floating-Point Values
779 void addsd(XMMRegister dst, Address src);
780 void addsd(XMMRegister dst, XMMRegister src);
781
782 // Add Scalar Single-Precision Floating-Point Values
783 void addss(XMMRegister dst, Address src);
784 void addss(XMMRegister dst, XMMRegister src);
785
786 // AES instructions
787 void aesdec(XMMRegister dst, Address src);
788 void aesdec(XMMRegister dst, XMMRegister src);
789 void aesdeclast(XMMRegister dst, Address src);
790 void aesdeclast(XMMRegister dst, XMMRegister src);
791 void aesenc(XMMRegister dst, Address src);
792 void aesenc(XMMRegister dst, XMMRegister src);
793 void aesenclast(XMMRegister dst, Address src);
794 void aesenclast(XMMRegister dst, XMMRegister src);
795
796
797 void andl(Address dst, int32_t imm32);
798 void andl(Register dst, int32_t imm32);
799 void andl(Register dst, Address src);
800 void andl(Register dst, Register src);
801
802 void andq(Address dst, int32_t imm32);
803 void andq(Register dst, int32_t imm32);
804 void andq(Register dst, Address src);
805 void andq(Register dst, Register src);
806
807 // BMI instructions
808 void andnl(Register dst, Register src1, Register src2);
809 void andnl(Register dst, Register src1, Address src2);
810 void andnq(Register dst, Register src1, Register src2);
811 void andnq(Register dst, Register src1, Address src2);
812
813 void blsil(Register dst, Register src);
814 void blsil(Register dst, Address src);
815 void blsiq(Register dst, Register src);
816 void blsiq(Register dst, Address src);
817
818 void blsmskl(Register dst, Register src);
819 void blsmskl(Register dst, Address src);
820 void blsmskq(Register dst, Register src);
821 void blsmskq(Register dst, Address src);
822
823 void blsrl(Register dst, Register src);
824 void blsrl(Register dst, Address src);
825 void blsrq(Register dst, Register src);
826 void blsrq(Register dst, Address src);
827
828 void bsfl(Register dst, Register src);
829 void bsrl(Register dst, Register src);
830
831 #ifdef _LP64
832 void bsfq(Register dst, Register src);
833 void bsrq(Register dst, Register src);
834 #endif
835
836 void bswapl(Register reg);
837
838 void bswapq(Register reg);
839
840 void call(Label& L, relocInfo::relocType rtype);
841 void call(Register reg); // push pc; pc <- reg
842 void call(Address adr); // push pc; pc <- adr
843
844 void cdql();
845
846 void cdqq();
847
848 void cld();
849
850 void clflush(Address adr);
851
852 void cmovl(Condition cc, Register dst, Register src);
853 void cmovl(Condition cc, Register dst, Address src);
854
855 void cmovq(Condition cc, Register dst, Register src);
856 void cmovq(Condition cc, Register dst, Address src);
857
858
859 void cmpb(Address dst, int imm8);
860
861 void cmpl(Address dst, int32_t imm32);
862
863 void cmpl(Register dst, int32_t imm32);
864 void cmpl(Register dst, Register src);
865 void cmpl(Register dst, Address src);
866
867 void cmpq(Address dst, int32_t imm32);
868 void cmpq(Address dst, Register src);
869
870 void cmpq(Register dst, int32_t imm32);
871 void cmpq(Register dst, Register src);
872 void cmpq(Register dst, Address src);
873
874 // these are dummies used to catch attempting to convert NULL to Register
875 void cmpl(Register dst, void* junk); // dummy
876 void cmpq(Register dst, void* junk); // dummy
877
878 void cmpw(Address dst, int imm16);
879
880 void cmpxchg8 (Address adr);
881
882 void cmpxchgl(Register reg, Address adr);
883
884 void cmpxchgq(Register reg, Address adr);
885
886 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
887 void comisd(XMMRegister dst, Address src);
888 void comisd(XMMRegister dst, XMMRegister src);
889
890 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
891 void comiss(XMMRegister dst, Address src);
892 void comiss(XMMRegister dst, XMMRegister src);
893
894 // Identify processor type and features
895 void cpuid();
896
897 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
898 void cvtsd2ss(XMMRegister dst, XMMRegister src);
899 void cvtsd2ss(XMMRegister dst, Address src);
900
901 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
902 void cvtsi2sdl(XMMRegister dst, Register src);
903 void cvtsi2sdl(XMMRegister dst, Address src);
904 void cvtsi2sdq(XMMRegister dst, Register src);
905 void cvtsi2sdq(XMMRegister dst, Address src);
906
907 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
908 void cvtsi2ssl(XMMRegister dst, Register src);
909 void cvtsi2ssl(XMMRegister dst, Address src);
910 void cvtsi2ssq(XMMRegister dst, Register src);
911 void cvtsi2ssq(XMMRegister dst, Address src);
912
913 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
914 void cvtdq2pd(XMMRegister dst, XMMRegister src);
915
916 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
917 void cvtdq2ps(XMMRegister dst, XMMRegister src);
918
919 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
920 void cvtss2sd(XMMRegister dst, XMMRegister src);
921 void cvtss2sd(XMMRegister dst, Address src);
922
923 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
924 void cvttsd2sil(Register dst, Address src);
925 void cvttsd2sil(Register dst, XMMRegister src);
926 void cvttsd2siq(Register dst, XMMRegister src);
927
928 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
929 void cvttss2sil(Register dst, XMMRegister src);
930 void cvttss2siq(Register dst, XMMRegister src);
931
932 // Divide Scalar Double-Precision Floating-Point Values
933 void divsd(XMMRegister dst, Address src);
934 void divsd(XMMRegister dst, XMMRegister src);
935
936 // Divide Scalar Single-Precision Floating-Point Values
937 void divss(XMMRegister dst, Address src);
938 void divss(XMMRegister dst, XMMRegister src);
939
940 void emms();
941
942 void fabs();
943
944 void fadd(int i);
945
946 void fadd_d(Address src);
947 void fadd_s(Address src);
948
949 // "Alternate" versions of x87 instructions place result down in FPU
950 // stack instead of on TOS
951
952 void fadda(int i); // "alternate" fadd
953 void faddp(int i = 1);
954
955 void fchs();
956
957 void fcom(int i);
958
959 void fcomp(int i = 1);
960 void fcomp_d(Address src);
961 void fcomp_s(Address src);
962
963 void fcompp();
964
965 void fcos();
966
967 void fdecstp();
968
969 void fdiv(int i);
970 void fdiv_d(Address src);
971 void fdivr_s(Address src);
972 void fdiva(int i); // "alternate" fdiv
973 void fdivp(int i = 1);
974
975 void fdivr(int i);
976 void fdivr_d(Address src);
977 void fdiv_s(Address src);
978
979 void fdivra(int i); // "alternate" reversed fdiv
980
981 void fdivrp(int i = 1);
982
983 void ffree(int i = 0);
984
985 void fild_d(Address adr);
986 void fild_s(Address adr);
987
988 void fincstp();
989
990 void finit();
991
992 void fist_s (Address adr);
993 void fistp_d(Address adr);
994 void fistp_s(Address adr);
995
996 void fld1();
997
998 void fld_d(Address adr);
999 void fld_s(Address adr);
1000 void fld_s(int index);
1001 void fld_x(Address adr); // extended-precision (80-bit) format
1002
1003 void fldcw(Address src);
1004
1005 void fldenv(Address src);
1006
1007 void fldlg2();
1008
1009 void fldln2();
1010
1011 void fldz();
1012
1013 void flog();
1014 void flog10();
1015
1016 void fmul(int i);
1017
1018 void fmul_d(Address src);
1019 void fmul_s(Address src);
1020
1021 void fmula(int i); // "alternate" fmul
1022
1023 void fmulp(int i = 1);
1024
1025 void fnsave(Address dst);
1026
1027 void fnstcw(Address src);
1028
1029 void fnstsw_ax();
1030
1031 void fprem();
1032 void fprem1();
1033
1034 void frstor(Address src);
1035
1036 void fsin();
1037
1038 void fsqrt();
1039
1040 void fst_d(Address adr);
1041 void fst_s(Address adr);
1042
1043 void fstp_d(Address adr);
1044 void fstp_d(int index);
1045 void fstp_s(Address adr);
1046 void fstp_x(Address adr); // extended-precision (80-bit) format
1047
1048 void fsub(int i);
1049 void fsub_d(Address src);
1050 void fsub_s(Address src);
1051
1052 void fsuba(int i); // "alternate" fsub
1053
1054 void fsubp(int i = 1);
1055
1056 void fsubr(int i);
1057 void fsubr_d(Address src);
1058 void fsubr_s(Address src);
1059
1060 void fsubra(int i); // "alternate" reversed fsub
1061
1062 void fsubrp(int i = 1);
1063
1064 void ftan();
1065
1066 void ftst();
1067
1068 void fucomi(int i = 1);
1069 void fucomip(int i = 1);
1070
1071 void fwait();
1072
1073 void fxch(int i = 1);
1074
1075 void fxrstor(Address src);
1076
1077 void fxsave(Address dst);
1078
1079 void fyl2x();
1080 void frndint();
1081 void f2xm1();
1082 void fldl2e();
1083
1084 void hlt();
1085
1086 void idivl(Register src);
1087 void divl(Register src); // Unsigned division
1088
1089 void idivq(Register src);
1090
1091 void imull(Register dst, Register src);
1092 void imull(Register dst, Register src, int value);
1093 void imull(Register dst, Address src);
1094
1095 void imulq(Register dst, Register src);
1096 void imulq(Register dst, Register src, int value);
1097 #ifdef _LP64
1098 void imulq(Register dst, Address src);
1099 #endif
1100
1101
1102 // jcc is the generic conditional branch generator to run-
1103 // time routines, jcc is used for branches to labels. jcc
1104 // takes a branch opcode (cc) and a label (L) and generates
1105 // either a backward branch or a forward branch and links it
1106 // to the label fixup chain. Usage:
1107 //
1108 // Label L; // unbound label
1109 // jcc(cc, L); // forward branch to unbound label
1110 // bind(L); // bind label to the current pc
1111 // jcc(cc, L); // backward branch to bound label
1112 // bind(L); // illegal: a label may be bound only once
1113 //
1114 // Note: The same Label can be used for forward and backward branches
1115 // but it may be bound only once.
1116
1117 void jcc(Condition cc, Label& L, bool maybe_short = true);
1118
1119 // Conditional jump to a 8-bit offset to L.
1120 // WARNING: be very careful using this for forward jumps. If the label is
1121 // not bound within an 8-bit offset of this instruction, a run-time error
1122 // will occur.
1123 void jccb(Condition cc, Label& L);
1124
1125 void jmp(Address entry); // pc <- entry
1126
1127 // Label operations & relative jumps (PPUM Appendix D)
1128 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1129
1130 void jmp(Register entry); // pc <- entry
1131
1132 // Unconditional 8-bit offset jump to L.
1133 // WARNING: be very careful using this for forward jumps. If the label is
1134 // not bound within an 8-bit offset of this instruction, a run-time error
1135 // will occur.
1136 void jmpb(Label& L);
1137
1138 void ldmxcsr( Address src );
1139
1140 void leal(Register dst, Address src);
1141
1142 void leaq(Register dst, Address src);
1143
1144 void lfence();
1145
1146 void lock();
1147
1148 void lzcntl(Register dst, Register src);
1149
1150 #ifdef _LP64
1151 void lzcntq(Register dst, Register src);
1152 #endif
1153
1154 enum Membar_mask_bits {
1155 StoreStore = 1 << 3,
1156 LoadStore = 1 << 2,
1157 StoreLoad = 1 << 1,
1158 LoadLoad = 1 << 0
1159 };
1160
1161 // Serializes memory and blows flags
1162 void membar(Membar_mask_bits order_constraint) {
1163 if (os::is_MP()) {
1164 // We only have to handle StoreLoad
1165 if (order_constraint & StoreLoad) {
1166 // All usable chips support "locked" instructions which suffice
1167 // as barriers, and are much faster than the alternative of
1168 // using cpuid instruction. We use here a locked add [esp],0.
1169 // This is conveniently otherwise a no-op except for blowing
1170 // flags.
1171 // Any change to this code may need to revisit other places in
1172 // the code where this idiom is used, in particular the
1173 // orderAccess code.
1174 lock();
1175 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1176 }
1177 }
1178 }
1179
1180 void mfence();
1181
1182 // Moves
1183
1184 void mov64(Register dst, int64_t imm64);
1185
1186 void movb(Address dst, Register src);
1187 void movb(Address dst, int imm8);
1188 void movb(Register dst, Address src);
1189
1190 void movdl(XMMRegister dst, Register src);
1191 void movdl(Register dst, XMMRegister src);
1192 void movdl(XMMRegister dst, Address src);
1193 void movdl(Address dst, XMMRegister src);
1194
1195 // Move Double Quadword
1196 void movdq(XMMRegister dst, Register src);
1197 void movdq(Register dst, XMMRegister src);
1198
1199 // Move Aligned Double Quadword
1200 void movdqa(XMMRegister dst, XMMRegister src);
1201 void movdqa(XMMRegister dst, Address src);
1202
1203 // Move Unaligned Double Quadword
1204 void movdqu(Address dst, XMMRegister src);
1205 void movdqu(XMMRegister dst, Address src);
1206 void movdqu(XMMRegister dst, XMMRegister src);
1207
1208 // Move Unaligned 256bit Vector
1209 void vmovdqu(Address dst, XMMRegister src);
1210 void vmovdqu(XMMRegister dst, Address src);
1211 void vmovdqu(XMMRegister dst, XMMRegister src);
1212
1213 // Move lower 64bit to high 64bit in 128bit register
1214 void movlhps(XMMRegister dst, XMMRegister src);
1215
1216 void movl(Register dst, int32_t imm32);
1217 void movl(Address dst, int32_t imm32);
1218 void movl(Register dst, Register src);
1219 void movl(Register dst, Address src);
1220 void movl(Address dst, Register src);
1221
1222 // These dummies prevent using movl from converting a zero (like NULL) into Register
1223 // by giving the compiler two choices it can't resolve
1224
1225 void movl(Address dst, void* junk);
1226 void movl(Register dst, void* junk);
1227
1228 #ifdef _LP64
1229 void movq(Register dst, Register src);
1230 void movq(Register dst, Address src);
1231 void movq(Address dst, Register src);
1232 #endif
1233
1234 void movq(Address dst, MMXRegister src );
1235 void movq(MMXRegister dst, Address src );
1236
1237 #ifdef _LP64
1238 // These dummies prevent using movq from converting a zero (like NULL) into Register
1239 // by giving the compiler two choices it can't resolve
1240
1241 void movq(Address dst, void* dummy);
1242 void movq(Register dst, void* dummy);
1243 #endif
1244
1245 // Move Quadword
1246 void movq(Address dst, XMMRegister src);
1247 void movq(XMMRegister dst, Address src);
1248
1249 void movsbl(Register dst, Address src);
1250 void movsbl(Register dst, Register src);
1251
1252 #ifdef _LP64
1253 void movsbq(Register dst, Address src);
1254 void movsbq(Register dst, Register src);
1255
1256 // Move signed 32bit immediate to 64bit extending sign
1257 void movslq(Address dst, int32_t imm64);
1258 void movslq(Register dst, int32_t imm64);
1259
1260 void movslq(Register dst, Address src);
1261 void movslq(Register dst, Register src);
1262 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1263 #endif
1264
1265 void movswl(Register dst, Address src);
1266 void movswl(Register dst, Register src);
1267
1268 #ifdef _LP64
1269 void movswq(Register dst, Address src);
1270 void movswq(Register dst, Register src);
1271 #endif
1272
1273 void movw(Address dst, int imm16);
1274 void movw(Register dst, Address src);
1275 void movw(Address dst, Register src);
1276
1277 void movzbl(Register dst, Address src);
1278 void movzbl(Register dst, Register src);
1279
1280 #ifdef _LP64
1281 void movzbq(Register dst, Address src);
1282 void movzbq(Register dst, Register src);
1283 #endif
1284
1285 void movzwl(Register dst, Address src);
1286 void movzwl(Register dst, Register src);
1287
1288 #ifdef _LP64
1289 void movzwq(Register dst, Address src);
1290 void movzwq(Register dst, Register src);
1291 #endif
1292
1293 void mull(Address src);
1294 void mull(Register src);
1295
1296 // Multiply Scalar Double-Precision Floating-Point Values
1297 void mulsd(XMMRegister dst, Address src);
1298 void mulsd(XMMRegister dst, XMMRegister src);
1299
1300 // Multiply Scalar Single-Precision Floating-Point Values
1301 void mulss(XMMRegister dst, Address src);
1302 void mulss(XMMRegister dst, XMMRegister src);
1303
1304 void negl(Register dst);
1305
1306 #ifdef _LP64
1307 void negq(Register dst);
1308 #endif
1309
1310 void nop(int i = 1);
1311
1312 void notl(Register dst);
1313
1314 #ifdef _LP64
1315 void notq(Register dst);
1316 #endif
1317
1318 void orl(Address dst, int32_t imm32);
1319 void orl(Register dst, int32_t imm32);
1320 void orl(Register dst, Address src);
1321 void orl(Register dst, Register src);
1322
1323 void orq(Address dst, int32_t imm32);
1324 void orq(Register dst, int32_t imm32);
1325 void orq(Register dst, Address src);
1326 void orq(Register dst, Register src);
1327
1328 // Pack with unsigned saturation
1329 void packuswb(XMMRegister dst, XMMRegister src);
1330 void packuswb(XMMRegister dst, Address src);
1331 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1332
1333 // Pemutation of 64bit words
1334 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256);
1335
1336 void pause();
1337
1338 // SSE4.2 string instructions
1339 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1340 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1341
1342 // SSE 4.1 extract
1343 void pextrd(Register dst, XMMRegister src, int imm8);
1344 void pextrq(Register dst, XMMRegister src, int imm8);
1345
1346 // SSE 4.1 insert
1347 void pinsrd(XMMRegister dst, Register src, int imm8);
1348 void pinsrq(XMMRegister dst, Register src, int imm8);
1349
1350 // SSE4.1 packed move
1351 void pmovzxbw(XMMRegister dst, XMMRegister src);
1352 void pmovzxbw(XMMRegister dst, Address src);
1353
1354 #ifndef _LP64 // no 32bit push/pop on amd64
1355 void popl(Address dst);
1356 #endif
1357
1358 #ifdef _LP64
1359 void popq(Address dst);
1360 #endif
1361
1362 void popcntl(Register dst, Address src);
1363 void popcntl(Register dst, Register src);
1364
1365 #ifdef _LP64
1366 void popcntq(Register dst, Address src);
1367 void popcntq(Register dst, Register src);
1368 #endif
1369
1370 // Prefetches (SSE, SSE2, 3DNOW only)
1371
1372 void prefetchnta(Address src);
1373 void prefetchr(Address src);
1374 void prefetcht0(Address src);
1375 void prefetcht1(Address src);
1376 void prefetcht2(Address src);
1377 void prefetchw(Address src);
1378
1379 // Shuffle Bytes
1380 void pshufb(XMMRegister dst, XMMRegister src);
1381 void pshufb(XMMRegister dst, Address src);
1382
1383 // Shuffle Packed Doublewords
1384 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1385 void pshufd(XMMRegister dst, Address src, int mode);
1386
1387 // Shuffle Packed Low Words
1388 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1389 void pshuflw(XMMRegister dst, Address src, int mode);
1390
1391 // Shift Right by bytes Logical DoubleQuadword Immediate
1392 void psrldq(XMMRegister dst, int shift);
1393
1394 // Logical Compare 128bit
1395 void ptest(XMMRegister dst, XMMRegister src);
1396 void ptest(XMMRegister dst, Address src);
1397 // Logical Compare 256bit
1398 void vptest(XMMRegister dst, XMMRegister src);
1399 void vptest(XMMRegister dst, Address src);
1400
1401 // Interleave Low Bytes
1402 void punpcklbw(XMMRegister dst, XMMRegister src);
1403 void punpcklbw(XMMRegister dst, Address src);
1404
1405 // Interleave Low Doublewords
1406 void punpckldq(XMMRegister dst, XMMRegister src);
1407 void punpckldq(XMMRegister dst, Address src);
1408
1409 // Interleave Low Quadwords
1410 void punpcklqdq(XMMRegister dst, XMMRegister src);
1411
1412 #ifndef _LP64 // no 32bit push/pop on amd64
1413 void pushl(Address src);
1414 #endif
1415
1416 void pushq(Address src);
1417
1418 void rcll(Register dst, int imm8);
1419
1420 void rclq(Register dst, int imm8);
1421
1422 void rdtsc();
1423
1424 void ret(int imm16);
1425
1426 void sahf();
1427
1428 void sarl(Register dst, int imm8);
1429 void sarl(Register dst);
1430
1431 void sarq(Register dst, int imm8);
1432 void sarq(Register dst);
1433
1434 void sbbl(Address dst, int32_t imm32);
1435 void sbbl(Register dst, int32_t imm32);
1436 void sbbl(Register dst, Address src);
1437 void sbbl(Register dst, Register src);
1438
1439 void sbbq(Address dst, int32_t imm32);
1440 void sbbq(Register dst, int32_t imm32);
1441 void sbbq(Register dst, Address src);
1442 void sbbq(Register dst, Register src);
1443
1444 void setb(Condition cc, Register dst);
1445
1446 void shldl(Register dst, Register src);
1447
1448 void shll(Register dst, int imm8);
1449 void shll(Register dst);
1450
1451 void shlq(Register dst, int imm8);
1452 void shlq(Register dst);
1453
1454 void shrdl(Register dst, Register src);
1455
1456 void shrl(Register dst, int imm8);
1457 void shrl(Register dst);
1458
1459 void shrq(Register dst, int imm8);
1460 void shrq(Register dst);
1461
1462 void smovl(); // QQQ generic?
1463
1464 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1465 void sqrtsd(XMMRegister dst, Address src);
1466 void sqrtsd(XMMRegister dst, XMMRegister src);
1467
1468 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1469 void sqrtss(XMMRegister dst, Address src);
1470 void sqrtss(XMMRegister dst, XMMRegister src);
1471
1472 void std();
1473
1474 void stmxcsr( Address dst );
1475
1476 void subl(Address dst, int32_t imm32);
1477 void subl(Address dst, Register src);
1478 void subl(Register dst, int32_t imm32);
1479 void subl(Register dst, Address src);
1480 void subl(Register dst, Register src);
1481
1482 void subq(Address dst, int32_t imm32);
1483 void subq(Address dst, Register src);
1484 void subq(Register dst, int32_t imm32);
1485 void subq(Register dst, Address src);
1486 void subq(Register dst, Register src);
1487
1488 // Force generation of a 4 byte immediate value even if it fits into 8bit
1489 void subl_imm32(Register dst, int32_t imm32);
1490 void subq_imm32(Register dst, int32_t imm32);
1491
1492 // Subtract Scalar Double-Precision Floating-Point Values
1493 void subsd(XMMRegister dst, Address src);
1494 void subsd(XMMRegister dst, XMMRegister src);
1495
1496 // Subtract Scalar Single-Precision Floating-Point Values
1497 void subss(XMMRegister dst, Address src);
1498 void subss(XMMRegister dst, XMMRegister src);
1499
1500 void testb(Register dst, int imm8);
1501
1502 void testl(Register dst, int32_t imm32);
1503 void testl(Register dst, Register src);
1504 void testl(Register dst, Address src);
1505
1506 void testq(Register dst, int32_t imm32);
1507 void testq(Register dst, Register src);
1508
1509 // BMI - count trailing zeros
1510 void tzcntl(Register dst, Register src);
1511 void tzcntq(Register dst, Register src);
1512
1513 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1514 void ucomisd(XMMRegister dst, Address src);
1515 void ucomisd(XMMRegister dst, XMMRegister src);
1516
1517 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1518 void ucomiss(XMMRegister dst, Address src);
1519 void ucomiss(XMMRegister dst, XMMRegister src);
1520
1521 void xabort(int8_t imm8);
1522
1523 void xaddl(Address dst, Register src);
1524
1525 void xaddq(Address dst, Register src);
1526
1527 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1528
1529 void xchgl(Register reg, Address adr);
1530 void xchgl(Register dst, Register src);
1531
1532 void xchgq(Register reg, Address adr);
1533 void xchgq(Register dst, Register src);
1534
1535 void xend();
1536
1537 // Get Value of Extended Control Register
1538 void xgetbv();
1539
1540 void xorl(Register dst, int32_t imm32);
1541 void xorl(Register dst, Address src);
1542 void xorl(Register dst, Register src);
1543
1544 void xorq(Register dst, Address src);
1545 void xorq(Register dst, Register src);
1546
1547 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1548
1549 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1550
1551 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1552 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1553 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1554 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1555 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1556 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1557 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1558 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1559 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1560 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1561 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1562 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1563 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1564 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1565 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1566 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1567
1568
1569 //====================VECTOR ARITHMETIC=====================================
1570
1571 // Add Packed Floating-Point Values
1572 void addpd(XMMRegister dst, XMMRegister src);
1573 void addps(XMMRegister dst, XMMRegister src);
1574 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1575 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1576 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1577 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1578
1579 // Subtract Packed Floating-Point Values
1580 void subpd(XMMRegister dst, XMMRegister src);
1581 void subps(XMMRegister dst, XMMRegister src);
1582 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1583 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1584 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1585 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1586
1587 // Multiply Packed Floating-Point Values
1588 void mulpd(XMMRegister dst, XMMRegister src);
1589 void mulps(XMMRegister dst, XMMRegister src);
1590 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1591 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1592 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1593 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1594
1595 // Divide Packed Floating-Point Values
1596 void divpd(XMMRegister dst, XMMRegister src);
1597 void divps(XMMRegister dst, XMMRegister src);
1598 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1599 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1600 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1601 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1602
1603 // Bitwise Logical AND of Packed Floating-Point Values
1604 void andpd(XMMRegister dst, XMMRegister src);
1605 void andps(XMMRegister dst, XMMRegister src);
1606 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1607 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1608 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1609 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1610
1611 // Bitwise Logical XOR of Packed Floating-Point Values
1612 void xorpd(XMMRegister dst, XMMRegister src);
1613 void xorps(XMMRegister dst, XMMRegister src);
1614 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1615 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1616 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1617 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1618
1619 // Add packed integers
1620 void paddb(XMMRegister dst, XMMRegister src);
1621 void paddw(XMMRegister dst, XMMRegister src);
1622 void paddd(XMMRegister dst, XMMRegister src);
1623 void paddq(XMMRegister dst, XMMRegister src);
1624 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1625 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1626 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1627 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1628 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1629 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1630 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1631 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1632
1633 // Sub packed integers
1634 void psubb(XMMRegister dst, XMMRegister src);
1635 void psubw(XMMRegister dst, XMMRegister src);
1636 void psubd(XMMRegister dst, XMMRegister src);
1637 void psubq(XMMRegister dst, XMMRegister src);
1638 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1639 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1640 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1641 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1642 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1643 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1644 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1645 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1646
1647 // Multiply packed integers (only shorts and ints)
1648 void pmullw(XMMRegister dst, XMMRegister src);
1649 void pmulld(XMMRegister dst, XMMRegister src);
1650 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1651 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1652 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1653 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1654
1655 // Shift left packed integers
1656 void psllw(XMMRegister dst, int shift);
1657 void pslld(XMMRegister dst, int shift);
1658 void psllq(XMMRegister dst, int shift);
1659 void psllw(XMMRegister dst, XMMRegister shift);
1660 void pslld(XMMRegister dst, XMMRegister shift);
1661 void psllq(XMMRegister dst, XMMRegister shift);
1662 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1663 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1664 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1665 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1666 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1667 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1668
1669 // Logical shift right packed integers
1670 void psrlw(XMMRegister dst, int shift);
1671 void psrld(XMMRegister dst, int shift);
1672 void psrlq(XMMRegister dst, int shift);
1673 void psrlw(XMMRegister dst, XMMRegister shift);
1674 void psrld(XMMRegister dst, XMMRegister shift);
1675 void psrlq(XMMRegister dst, XMMRegister shift);
1676 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1677 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1678 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1679 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1680 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1681 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1682
1683 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1684 void psraw(XMMRegister dst, int shift);
1685 void psrad(XMMRegister dst, int shift);
1686 void psraw(XMMRegister dst, XMMRegister shift);
1687 void psrad(XMMRegister dst, XMMRegister shift);
1688 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1689 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1690 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1691 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1692
1693 // And packed integers
1694 void pand(XMMRegister dst, XMMRegister src);
1695 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1696 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1697
1698 // Or packed integers
1699 void por(XMMRegister dst, XMMRegister src);
1700 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1701 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1702
1703 // Xor packed integers
1704 void pxor(XMMRegister dst, XMMRegister src);
1705 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1706 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1707
1708 // Copy low 128bit into high 128bit of YMM registers.
1709 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1710 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1711
1712 // Load/store high 128bit of YMM registers which does not destroy other half.
1713 void vinsertf128h(XMMRegister dst, Address src);
1714 void vinserti128h(XMMRegister dst, Address src);
1715 void vextractf128h(Address dst, XMMRegister src);
1716 void vextracti128h(Address dst, XMMRegister src);
1717
1718 // duplicate 4-bytes integer data from src into 8 locations in dest
1719 void vpbroadcastd(XMMRegister dst, XMMRegister src);
1720
1721 // Carry-Less Multiplication Quadword
1722 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
1723
1724 // AVX instruction which is used to clear upper 128 bits of YMM registers and
1725 // to avoid transaction penalty between AVX and SSE states. There is no
1726 // penalty if legacy SSE instructions are encoded using VEX prefix because
1727 // they always clear upper 128 bits. It should be used before calling
1728 // runtime code and native libraries.
1729 void vzeroupper();
1730
1731 protected:
1732 // Next instructions require address alignment 16 bytes SSE mode.
1733 // They should be called only from corresponding MacroAssembler instructions.
1734 void andpd(XMMRegister dst, Address src);
1735 void andps(XMMRegister dst, Address src);
1736 void xorpd(XMMRegister dst, Address src);
1737 void xorps(XMMRegister dst, Address src);
1738
1739 };
1740
1741 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP