--- old/src/cpu/x86/vm/assembler_x86.hpp 2014-04-24 15:52:56.000000000 -1000 +++ new/src/cpu/x86/vm/assembler_x86.hpp 2014-04-24 15:52:56.000000000 -1000 @@ -31,119 +31,6 @@ // Contains all the definitions needed for x86 assembly code generation. -// Calling convention -class Argument VALUE_OBJ_CLASS_SPEC { - public: - enum { -#ifdef _LP64 -#ifdef _WIN64 - n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) - n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) -#else - n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) - n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) -#endif // _WIN64 - n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... - n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... -#else - n_register_parameters = 0 // 0 registers used to pass arguments -#endif // _LP64 - }; -}; - - -#ifdef _LP64 -// Symbolically name the register arguments used by the c calling convention. -// Windows is different from linux/solaris. So much for standards... - -#ifdef _WIN64 - -REGISTER_DECLARATION(Register, c_rarg0, rcx); -REGISTER_DECLARATION(Register, c_rarg1, rdx); -REGISTER_DECLARATION(Register, c_rarg2, r8); -REGISTER_DECLARATION(Register, c_rarg3, r9); - -REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); -REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); -REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); -REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); - -#else - -REGISTER_DECLARATION(Register, c_rarg0, rdi); -REGISTER_DECLARATION(Register, c_rarg1, rsi); -REGISTER_DECLARATION(Register, c_rarg2, rdx); -REGISTER_DECLARATION(Register, c_rarg3, rcx); -REGISTER_DECLARATION(Register, c_rarg4, r8); -REGISTER_DECLARATION(Register, c_rarg5, r9); - -REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); -REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); -REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); -REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); -REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); -REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); -REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); -REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); - -#endif // _WIN64 - -// Symbolically name the register arguments used by the Java calling convention. -// We have control over the convention for java so we can do what we please. -// What pleases us is to offset the java calling convention so that when -// we call a suitable jni method the arguments are lined up and we don't -// have to do little shuffling. A suitable jni method is non-static and a -// small number of arguments (two fewer args on windows) -// -// |-------------------------------------------------------| -// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | -// |-------------------------------------------------------| -// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) -// | rdi rsi rdx rcx r8 r9 | solaris/linux -// |-------------------------------------------------------| -// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | -// |-------------------------------------------------------| - -REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); -REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); -REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); -// Windows runs out of register args here -#ifdef _WIN64 -REGISTER_DECLARATION(Register, j_rarg3, rdi); -REGISTER_DECLARATION(Register, j_rarg4, rsi); -#else -REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); -REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); -#endif /* _WIN64 */ -REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); - -REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); -REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); -REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); -REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); -REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); -REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); -REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); -REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); - -REGISTER_DECLARATION(Register, rscratch1, r10); // volatile -REGISTER_DECLARATION(Register, rscratch2, r11); // volatile - -REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved -REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved - -#else -// rscratch1 will apear in 32bit code that is dead but of course must compile -// Using noreg ensures if the dead code is incorrectly live and executed it -// will cause an assertion failure -#define rscratch1 noreg -#define rscratch2 noreg - -#endif // _LP64 - -// JSR 292 fixed register usages: -REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); - // Address is an abstraction used to represent a memory location // using any of the amd64 addressing modes with one object. // @@ -217,7 +104,7 @@ _index(index), _scale(scale), _disp (disp) { - assert(!index->is_valid() == (scale == Address::no_scale), + assert(!index.is_valid() == (scale == Address::no_scale), "inconsistent address"); } @@ -227,7 +114,7 @@ _scale(scale), _disp (disp + (index.constant_or_zero() * scale_size(scale))) { if (!index.is_register()) scale = Address::no_scale; - assert(!_index->is_valid() == (scale == Address::no_scale), + assert(!_index.is_valid() == (scale == Address::no_scale), "inconsistent address"); } @@ -240,7 +127,7 @@ Address a = (*this); a._disp += disp.constant_or_zero() * scale_size(scale); if (disp.is_register()) { - assert(!a.index()->is_valid(), "competing indexes"); + assert(!a.index().is_valid(), "competing indexes"); a._index = disp.as_register(); a._scale = scale; } @@ -275,7 +162,7 @@ _index(index), _scale(scale), _disp(in_bytes(disp)) { - assert(!index->is_valid() == (scale == Address::no_scale), + assert(!index.is_valid() == (scale == Address::no_scale), "inconsistent address"); } @@ -285,7 +172,7 @@ _scale(scale), _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { if (!index.is_register()) scale = Address::no_scale; - assert(!_index->is_valid() == (scale == Address::no_scale), + assert(!_index.is_valid() == (scale == Address::no_scale), "inconsistent address"); } @@ -307,11 +194,11 @@ private: bool base_needs_rex() const { - return _base != noreg && _base->encoding() >= 8; + return _base != noreg && _base.encoding() >= 8; } bool index_needs_rex() const { - return _index != noreg &&_index->encoding() >= 8; + return _index != noreg && _index.encoding() >= 8; } relocInfo::relocType reloc() const { return _rspec.type(); } @@ -585,22 +472,22 @@ void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, VexSimdPrefix pre, bool vector256 = false) { - int dst_enc = dst->encoding(); - int nds_enc = nds->is_valid() ? nds->encoding() : 0; + int dst_enc = dst.encoding(); + int nds_enc = nds.is_valid() ? nds.encoding() : 0; vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); } void vex_prefix_0F38(Register dst, Register nds, Address src) { bool vex_w = false; bool vector256 = false; - vex_prefix(src, nds->encoding(), dst->encoding(), + vex_prefix(src, nds.encoding(), dst.encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); } void vex_prefix_0F38_q(Register dst, Register nds, Address src) { bool vex_w = true; bool vector256 = false; - vex_prefix(src, nds->encoding(), dst->encoding(), + vex_prefix(src, nds.encoding(), dst.encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); } int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, @@ -610,21 +497,21 @@ int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { bool vex_w = false; bool vector256 = false; - return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), + return vex_prefix_and_encode(dst.encoding(), nds.encoding(), src.encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); } int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { bool vex_w = true; bool vector256 = false; - return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), + return vex_prefix_and_encode(dst.encoding(), nds.encoding(), src.encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); } int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, bool vector256 = false, VexOpcode opc = VEX_OPCODE_0F) { - int src_enc = src->encoding(); - int dst_enc = dst->encoding(); - int nds_enc = nds->is_valid() ? nds->encoding() : 0; + int src_enc = src.encoding(); + int dst_enc = dst.encoding(); + int nds_enc = nds.is_valid() ? nds.encoding() : 0; return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); } @@ -656,21 +543,21 @@ // It is OK to cast from Register to XMMRegister to pass argument here // since only encoding is used in simd_prefix_and_encode() and number of // Gen and Xmm registers are the same. - return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); + return simd_prefix_and_encode(dst, nds, as_XMMRegister(src.encoding()), pre); } int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { return simd_prefix_and_encode(dst, xnoreg, src, pre); } int simd_prefix_and_encode(Register dst, XMMRegister src, VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { - return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); + return simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, pre, opc); } // Move/convert 64-bit integer value. int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, VexSimdPrefix pre) { bool rex_w = true; - return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); + return simd_prefix_and_encode(dst, nds, as_XMMRegister(src.encoding()), pre, VEX_OPCODE_0F, rex_w); } int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { return simd_prefix_and_encode_q(dst, xnoreg, src, pre); @@ -678,7 +565,7 @@ int simd_prefix_and_encode_q(Register dst, XMMRegister src, VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { bool rex_w = true; - return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); + return simd_prefix_and_encode(as_XMMRegister(dst.encoding()), xnoreg, src, pre, opc, rex_w); } // Helper functions for groups of instructions @@ -698,7 +585,7 @@ void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, bool vector256); - void emit_operand(Register reg, + void emit_operand(AbstractRegister reg, Register base, Register index, Address::ScaleFactor scale, int disp, RelocationHolder const& rspec, @@ -709,11 +596,6 @@ // operands that only take the original 32bit registers void emit_operand32(Register reg, Address adr); - void emit_operand(XMMRegister reg, - Register base, Register index, Address::ScaleFactor scale, - int disp, - RelocationHolder const& rspec); - void emit_operand(XMMRegister reg, Address adr); void emit_operand(MMXRegister reg, Address adr);