src/cpu/x86/vm/c1_FrameMap_x86.cpp
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src/cpu/x86/vm/c1_FrameMap_x86.cpp

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  42     opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
  43   } else if (r_1->is_Register()) {
  44     Register reg = r_1->as_Register();
  45     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
  46       Register reg2 = r_2->as_Register();
  47 #ifdef _LP64
  48       assert(reg2 == reg, "must be same register");
  49       opr = as_long_opr(reg);
  50 #else
  51       opr = as_long_opr(reg2, reg);
  52 #endif // _LP64
  53     } else if (type == T_OBJECT || type == T_ARRAY) {
  54       opr = as_oop_opr(reg);
  55     } else if (type == T_METADATA) {
  56       opr = as_metadata_opr(reg);
  57     } else {
  58       opr = as_opr(reg);
  59     }
  60   } else if (r_1->is_FloatRegister()) {
  61     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  62     int num = r_1->as_FloatRegister()->encoding();
  63     if (type == T_FLOAT) {
  64       opr = LIR_OprFact::single_fpu(num);
  65     } else {
  66       opr = LIR_OprFact::double_fpu(num);
  67     }
  68   } else if (r_1->is_XMMRegister()) {
  69     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  70     int num = r_1->as_XMMRegister()->encoding();
  71     if (type == T_FLOAT) {
  72       opr = LIR_OprFact::single_xmm(num);
  73     } else {
  74       opr = LIR_OprFact::double_xmm(num);
  75     }
  76   } else {
  77     ShouldNotReachHere();
  78   }
  79   return opr;
  80 }
  81 
  82 
  83 LIR_Opr FrameMap::rsi_opr;
  84 LIR_Opr FrameMap::rdi_opr;
  85 LIR_Opr FrameMap::rbx_opr;
  86 LIR_Opr FrameMap::rax_opr;
  87 LIR_Opr FrameMap::rdx_opr;
  88 LIR_Opr FrameMap::rcx_opr;
  89 LIR_Opr FrameMap::rsp_opr;
  90 LIR_Opr FrameMap::rbp_opr;


 127 // the allocator
 128 LIR_Opr  FrameMap::r8_oop_opr;
 129 LIR_Opr  FrameMap::r9_oop_opr;
 130 LIR_Opr FrameMap::r11_oop_opr;
 131 LIR_Opr FrameMap::r12_oop_opr;
 132 LIR_Opr FrameMap::r13_oop_opr;
 133 LIR_Opr FrameMap::r14_oop_opr;
 134 
 135 LIR_Opr  FrameMap::r8_metadata_opr;
 136 LIR_Opr  FrameMap::r9_metadata_opr;
 137 LIR_Opr FrameMap::r11_metadata_opr;
 138 LIR_Opr FrameMap::r12_metadata_opr;
 139 LIR_Opr FrameMap::r13_metadata_opr;
 140 LIR_Opr FrameMap::r14_metadata_opr;
 141 #endif // _LP64
 142 
 143 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
 144 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
 145 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
 146 
 147 XMMRegister FrameMap::_xmm_regs [] = { 0, };
 148 
 149 XMMRegister FrameMap::nr2xmmreg(int rnr) {
 150   assert(_init_done, "tables not initialized");
 151   return _xmm_regs[rnr];
 152 }
 153 
 154 //--------------------------------------------------------
 155 //               FrameMap
 156 //--------------------------------------------------------
 157 
 158 void FrameMap::initialize() {
 159   assert(!_init_done, "once");
 160 
 161   assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
 162   map_register(0, rsi);  rsi_opr = LIR_OprFact::single_cpu(0);
 163   map_register(1, rdi);  rdi_opr = LIR_OprFact::single_cpu(1);
 164   map_register(2, rbx);  rbx_opr = LIR_OprFact::single_cpu(2);
 165   map_register(3, rax);  rax_opr = LIR_OprFact::single_cpu(3);
 166   map_register(4, rdx);  rdx_opr = LIR_OprFact::single_cpu(4);
 167   map_register(5, rcx);  rcx_opr = LIR_OprFact::single_cpu(5);


 316 //   | ret addr |
 317 //   +----------+
 318 //   |  args    |
 319 //   | .........|
 320 
 321 
 322 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
 323 // This is the offset from sp() in the frame of the slot for the index,
 324 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
 325 //
 326 //           framesize +
 327 //           stack0         stack0          0  <- VMReg
 328 //             |              | <registers> |
 329 //  ...........|..............|.............|
 330 //      0 1 2 3 x x 4 5 6 ... |                <- local indices
 331 //      ^           ^        sp()                 ( x x indicate link
 332 //      |           |                               and return addr)
 333 //  arguments   non-argument locals
 334 
 335 
 336 VMReg FrameMap::fpu_regname (int n) {
 337   // Return the OptoReg name for the fpu stack slot "n"
 338   // A spilled fpu stack slot comprises to two single-word OptoReg's.
 339   return as_FloatRegister(n)->as_VMReg();
 340 }
 341 
 342 LIR_Opr FrameMap::stack_pointer() {
 343   return FrameMap::rsp_opr;
 344 }
 345 
 346 
 347 // JSR 292
 348 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
 349   assert(rbp == rbp_mh_SP_save, "must be same register");
 350   return rbp_opr;
 351 }
 352 
 353 
 354 bool FrameMap::validate_frame() {
 355   return true;
 356 }


  42     opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
  43   } else if (r_1->is_Register()) {
  44     Register reg = r_1->as_Register();
  45     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
  46       Register reg2 = r_2->as_Register();
  47 #ifdef _LP64
  48       assert(reg2 == reg, "must be same register");
  49       opr = as_long_opr(reg);
  50 #else
  51       opr = as_long_opr(reg2, reg);
  52 #endif // _LP64
  53     } else if (type == T_OBJECT || type == T_ARRAY) {
  54       opr = as_oop_opr(reg);
  55     } else if (type == T_METADATA) {
  56       opr = as_metadata_opr(reg);
  57     } else {
  58       opr = as_opr(reg);
  59     }
  60   } else if (r_1->is_FloatRegister()) {
  61     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  62     int num = r_1->as_FloatRegister().encoding();
  63     if (type == T_FLOAT) {
  64       opr = LIR_OprFact::single_fpu(num);
  65     } else {
  66       opr = LIR_OprFact::double_fpu(num);
  67     }
  68   } else if (r_1->is_XMMRegister()) {
  69     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  70     int num = r_1->as_XMMRegister().encoding();
  71     if (type == T_FLOAT) {
  72       opr = LIR_OprFact::single_xmm(num);
  73     } else {
  74       opr = LIR_OprFact::double_xmm(num);
  75     }
  76   } else {
  77     ShouldNotReachHere();
  78   }
  79   return opr;
  80 }
  81 
  82 
  83 LIR_Opr FrameMap::rsi_opr;
  84 LIR_Opr FrameMap::rdi_opr;
  85 LIR_Opr FrameMap::rbx_opr;
  86 LIR_Opr FrameMap::rax_opr;
  87 LIR_Opr FrameMap::rdx_opr;
  88 LIR_Opr FrameMap::rcx_opr;
  89 LIR_Opr FrameMap::rsp_opr;
  90 LIR_Opr FrameMap::rbp_opr;


 127 // the allocator
 128 LIR_Opr  FrameMap::r8_oop_opr;
 129 LIR_Opr  FrameMap::r9_oop_opr;
 130 LIR_Opr FrameMap::r11_oop_opr;
 131 LIR_Opr FrameMap::r12_oop_opr;
 132 LIR_Opr FrameMap::r13_oop_opr;
 133 LIR_Opr FrameMap::r14_oop_opr;
 134 
 135 LIR_Opr  FrameMap::r8_metadata_opr;
 136 LIR_Opr  FrameMap::r9_metadata_opr;
 137 LIR_Opr FrameMap::r11_metadata_opr;
 138 LIR_Opr FrameMap::r12_metadata_opr;
 139 LIR_Opr FrameMap::r13_metadata_opr;
 140 LIR_Opr FrameMap::r14_metadata_opr;
 141 #endif // _LP64
 142 
 143 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
 144 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
 145 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
 146 
 147 XMMRegister FrameMap::_xmm_regs[];
 148 
 149 XMMRegister FrameMap::nr2xmmreg(int rnr) {
 150   assert(_init_done, "tables not initialized");
 151   return _xmm_regs[rnr];
 152 }
 153 
 154 //--------------------------------------------------------
 155 //               FrameMap
 156 //--------------------------------------------------------
 157 
 158 void FrameMap::initialize() {
 159   assert(!_init_done, "once");
 160 
 161   assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
 162   map_register(0, rsi);  rsi_opr = LIR_OprFact::single_cpu(0);
 163   map_register(1, rdi);  rdi_opr = LIR_OprFact::single_cpu(1);
 164   map_register(2, rbx);  rbx_opr = LIR_OprFact::single_cpu(2);
 165   map_register(3, rax);  rax_opr = LIR_OprFact::single_cpu(3);
 166   map_register(4, rdx);  rdx_opr = LIR_OprFact::single_cpu(4);
 167   map_register(5, rcx);  rcx_opr = LIR_OprFact::single_cpu(5);


 316 //   | ret addr |
 317 //   +----------+
 318 //   |  args    |
 319 //   | .........|
 320 
 321 
 322 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
 323 // This is the offset from sp() in the frame of the slot for the index,
 324 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
 325 //
 326 //           framesize +
 327 //           stack0         stack0          0  <- VMReg
 328 //             |              | <registers> |
 329 //  ...........|..............|.............|
 330 //      0 1 2 3 x x 4 5 6 ... |                <- local indices
 331 //      ^           ^        sp()                 ( x x indicate link
 332 //      |           |                               and return addr)
 333 //  arguments   non-argument locals
 334 
 335 
 336 VMReg FrameMap::fpu_regname(int n) {
 337   // Return the OptoReg name for the fpu stack slot "n"
 338   // A spilled fpu stack slot comprises to two single-word OptoReg's.
 339   return as_FloatRegister(n).as_VMReg();
 340 }
 341 
 342 LIR_Opr FrameMap::stack_pointer() {
 343   return FrameMap::rsp_opr;
 344 }
 345 
 346 
 347 // JSR 292
 348 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
 349   assert(rbp == rbp_mh_SP_save, "must be same register");
 350   return rbp_opr;
 351 }
 352 
 353 
 354 bool FrameMap::validate_frame() {
 355   return true;
 356 }
src/cpu/x86/vm/c1_FrameMap_x86.cpp
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