498   patch[3] = 0xFE;
 499 
 500   // First patch dummy jmp in place
 501   *(int32_t*)verified_entry = *(int32_t *)patch;
 502 
 503   n_jump->wrote(0);
 504 
 505   // Patch 5th byte (from jump instruction)
 506   verified_entry[4] = code_buffer[4];
 507 
 508   n_jump->wrote(4);
 509 
 510   // Patch bytes 0-3 (from jump instruction)
 511   *(int32_t*)verified_entry = *(int32_t *)code_buffer;
 512   // Invalidate.  Opteron requires a flush after every write.
 513   n_jump->wrote(0);
 514 
 515 }
 516 
 517 void NativePopReg::insert(address code_pos, Register reg) {
 518   assert(reg->encoding() < 8, "no space for REX");
 519   assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
 520   *code_pos = (u_char)(instruction_code | reg->encoding());
 521   ICache::invalidate_range(code_pos, instruction_size);
 522 }
 523 
 524 
 525 void NativeIllegalInstruction::insert(address code_pos) {
 526   assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
 527   *(short *)code_pos = instruction_code;
 528   ICache::invalidate_range(code_pos, instruction_size);
 529 }
 530 
 531 void NativeGeneralJump::verify() {
 532   assert(((NativeInstruction *)this)->is_jump() ||
 533          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
 534 }
 535 
 536 
 537 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
 538   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
 539 #ifdef AMD64
 540   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");

 498   patch[3] = 0xFE;
 499 
 500   // First patch dummy jmp in place
 501   *(int32_t*)verified_entry = *(int32_t *)patch;
 502 
 503   n_jump->wrote(0);
 504 
 505   // Patch 5th byte (from jump instruction)
 506   verified_entry[4] = code_buffer[4];
 507 
 508   n_jump->wrote(4);
 509 
 510   // Patch bytes 0-3 (from jump instruction)
 511   *(int32_t*)verified_entry = *(int32_t *)code_buffer;
 512   // Invalidate.  Opteron requires a flush after every write.
 513   n_jump->wrote(0);
 514 
 515 }
 516 
 517 void NativePopReg::insert(address code_pos, Register reg) {
 518   assert(reg.encoding() < 8, "no space for REX");
 519   assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
 520   *code_pos = (u_char)(instruction_code | reg.encoding());
 521   ICache::invalidate_range(code_pos, instruction_size);
 522 }
 523 
 524 
 525 void NativeIllegalInstruction::insert(address code_pos) {
 526   assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
 527   *(short *)code_pos = instruction_code;
 528   ICache::invalidate_range(code_pos, instruction_size);
 529 }
 530 
 531 void NativeGeneralJump::verify() {
 532   assert(((NativeInstruction *)this)->is_jump() ||
 533          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
 534 }
 535 
 536 
 537 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
 538   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
 539 #ifdef AMD64
 540   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");