14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_REGISTER_X86_HPP 26 #define CPU_X86_VM_REGISTER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "vm_version_x86.hpp" 30 31 class VMRegImpl; 32 typedef VMRegImpl* VMReg; 33 34 // Use Register as shortcut 35 class RegisterImpl; 36 typedef RegisterImpl* Register; 37 38 39 // The implementation of integer registers for the ia32 architecture 40 inline Register as_Register(int encoding) { 41 return (Register)(intptr_t) encoding; 42 } 43 44 class RegisterImpl: public AbstractRegisterImpl { 45 public: 46 enum { 47 #ifndef AMD64 48 number_of_registers = 8, 49 number_of_byte_registers = 4 50 #else 51 number_of_registers = 16, 52 number_of_byte_registers = 16 53 #endif // AMD64 54 }; 55 56 // derived registers, offsets, and addresses 57 Register successor() const { return as_Register(encoding() + 1); } 58 59 // construction 60 inline friend Register as_Register(int encoding); 61 62 VMReg as_VMReg(); 63 64 // accessors 65 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 66 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 67 bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; } 68 const char* name() const; 69 }; 70 71 // The integer registers of the ia32/amd64 architecture 72 73 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); 74 75 76 CONSTANT_REGISTER_DECLARATION(Register, rax, (0)); 77 CONSTANT_REGISTER_DECLARATION(Register, rcx, (1)); 78 CONSTANT_REGISTER_DECLARATION(Register, rdx, (2)); 79 CONSTANT_REGISTER_DECLARATION(Register, rbx, (3)); 80 CONSTANT_REGISTER_DECLARATION(Register, rsp, (4)); 81 CONSTANT_REGISTER_DECLARATION(Register, rbp, (5)); 82 CONSTANT_REGISTER_DECLARATION(Register, rsi, (6)); 83 CONSTANT_REGISTER_DECLARATION(Register, rdi, (7)); 84 #ifdef AMD64 85 CONSTANT_REGISTER_DECLARATION(Register, r8, (8)); 86 CONSTANT_REGISTER_DECLARATION(Register, r9, (9)); 87 CONSTANT_REGISTER_DECLARATION(Register, r10, (10)); 88 CONSTANT_REGISTER_DECLARATION(Register, r11, (11)); 89 CONSTANT_REGISTER_DECLARATION(Register, r12, (12)); 90 CONSTANT_REGISTER_DECLARATION(Register, r13, (13)); 91 CONSTANT_REGISTER_DECLARATION(Register, r14, (14)); 92 CONSTANT_REGISTER_DECLARATION(Register, r15, (15)); 93 #endif // AMD64 94 95 // Use FloatRegister as shortcut 96 class FloatRegisterImpl; 97 typedef FloatRegisterImpl* FloatRegister; 98 99 inline FloatRegister as_FloatRegister(int encoding) { 100 return (FloatRegister)(intptr_t) encoding; 101 } 102 103 // The implementation of floating point registers for the ia32 architecture 104 class FloatRegisterImpl: public AbstractRegisterImpl { 105 public: 106 enum { 107 number_of_registers = 8 108 }; 109 110 // construction 111 inline friend FloatRegister as_FloatRegister(int encoding); 112 113 VMReg as_VMReg(); 114 115 // derived registers, offsets, and addresses 116 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } 117 118 // accessors 119 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 120 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 121 const char* name() const; 122 123 }; 124 125 // Use XMMRegister as shortcut 126 class XMMRegisterImpl; 127 typedef XMMRegisterImpl* XMMRegister; 128 129 // Use MMXRegister as shortcut 130 class MMXRegisterImpl; 131 typedef MMXRegisterImpl* MMXRegister; 132 133 inline XMMRegister as_XMMRegister(int encoding) { 134 return (XMMRegister)(intptr_t)encoding; 135 } 136 137 inline MMXRegister as_MMXRegister(int encoding) { 138 return (MMXRegister)(intptr_t)encoding; 139 } 140 141 // The implementation of XMM registers for the IA32 architecture 142 class XMMRegisterImpl: public AbstractRegisterImpl { 143 public: 144 enum { 145 #ifndef AMD64 146 number_of_registers = 8 147 #else 148 number_of_registers = 16 149 #endif // AMD64 150 }; 151 152 // construction 153 friend XMMRegister as_XMMRegister(int encoding); 154 155 VMReg as_VMReg(); 156 157 // derived registers, offsets, and addresses 158 XMMRegister successor() const { return as_XMMRegister(encoding() + 1); } 159 160 // accessors 161 int encoding() const { assert(is_valid(), err_msg("invalid register (%d)", (int)(intptr_t)this )); return (intptr_t)this; } 162 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 163 const char* name() const; 164 }; 165 166 167 // The XMM registers, for P3 and up chips 168 CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1)); 169 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0)); 170 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1)); 171 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2)); 172 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3)); 173 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4)); 174 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5)); 175 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6)); 176 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7)); 177 #ifdef AMD64 178 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8)); 179 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9)); 180 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10)); 181 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11)); 182 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12)); 183 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13)); 184 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14)); 185 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15)); 186 #endif // AMD64 187 188 // Only used by the 32bit stubGenerator. These can't be described by vmreg and hence 189 // can't be described in oopMaps and therefore can't be used by the compilers (at least 190 // were deopt might wan't to see them). 191 192 // The MMX registers, for P3 and up chips 193 CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1)); 194 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0)); 195 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1)); 196 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2)); 197 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3)); 198 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4)); 199 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5)); 200 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6)); 201 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7)); 202 203 204 // Need to know the total number of registers of all sorts for SharedInfo. 205 // Define a class that exports it. 206 class ConcreteRegisterImpl : public AbstractRegisterImpl { 207 public: 208 enum { 209 // A big enough number for C2: all the registers plus flags 210 // This number must be large enough to cover REG_COUNT (defined by c2) registers. 211 // There is no requirement that any ordering here matches any ordering c2 gives 212 // it's optoregs. 213 214 number_of_registers = RegisterImpl::number_of_registers + 215 #ifdef AMD64 216 RegisterImpl::number_of_registers + // "H" half of a 64bit register 217 #endif // AMD64 218 2 * FloatRegisterImpl::number_of_registers + 219 8 * XMMRegisterImpl::number_of_registers + 220 1 // eflags 221 }; 222 223 static const int max_gpr; 224 static const int max_fpr; 225 static const int max_xmm; 226 227 }; 228 229 #endif // CPU_X86_VM_REGISTER_X86_HPP | 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_REGISTER_X86_HPP 26 #define CPU_X86_VM_REGISTER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "vm_version_x86.hpp" 30 31 class VMRegImpl; 32 typedef VMRegImpl* VMReg; 33 34 /** 35 * The implementation of integer registers for the IA32 architecture. 36 */ 37 class Register: public AbstractRegister { 38 public: 39 enum { 40 #ifndef AMD64 41 number_of_registers = 8, 42 number_of_byte_registers = 4 43 #else 44 number_of_registers = 16, 45 number_of_byte_registers = 16 46 #endif // AMD64 47 }; 48 49 /** 50 * Constructor to construct an invalid register. 51 */ 52 Register() : AbstractRegister(-1) {} 53 54 Register(int encoding) : AbstractRegister(encoding) {} 55 56 // derived registers, offsets, and addresses 57 Register successor() const { 58 return Register(encoding() + 1); 59 } 60 61 // construction 62 inline friend Register as_Register(int encoding); 63 64 VMReg as_VMReg() const; 65 66 bool is_valid() const { 67 return 0 <= encoding() && encoding() < number_of_registers; 68 } 69 70 bool has_byte_register() const { 71 return 0 <= encoding() && encoding() < number_of_byte_registers; 72 } 73 74 const char* name() const; 75 }; 76 77 inline Register as_Register(int encoding) { 78 return Register(encoding); 79 } 80 81 /** 82 * The implementation of floating point registers for the IA32 architecture. 83 */ 84 class FloatRegister: public AbstractRegister { 85 public: 86 enum { 87 number_of_registers = 8 88 }; 89 90 /** 91 * Constructor to construct an invalid register. 92 */ 93 FloatRegister() : AbstractRegister(-1) {} 94 95 FloatRegister(int encoding) : AbstractRegister(encoding) {} 96 97 // construction 98 inline friend FloatRegister as_FloatRegister(int encoding); 99 100 VMReg as_VMReg() const; 101 102 // derived registers, offsets, and addresses 103 FloatRegister successor() const { 104 return FloatRegister(encoding() + 1); 105 } 106 107 bool is_valid() const { 108 return 0 <= encoding() && encoding() < number_of_registers; 109 } 110 111 const char* name() const; 112 }; 113 114 inline FloatRegister as_FloatRegister(int encoding) { 115 return FloatRegister(encoding); 116 } 117 118 /** 119 * The implementation of MMX registers for the IA32 architecture. 120 */ 121 class MMXRegister: public AbstractRegister { 122 public: 123 enum { 124 number_of_registers = 8 125 }; 126 127 MMXRegister(int encoding) : AbstractRegister(encoding) {} 128 129 // construction 130 friend MMXRegister as_MMXRegister(int encoding); 131 132 VMReg as_VMReg() const; 133 134 // derived registers, offsets, and addresses 135 MMXRegister successor() const { 136 return MMXRegister(encoding() + 1); 137 } 138 139 bool is_valid() const { 140 return 0 <= encoding() && encoding() < number_of_registers; 141 } 142 143 const char* name() const; 144 }; 145 146 inline MMXRegister as_MMXRegister(int encoding) { 147 return MMXRegister(encoding); 148 } 149 150 /** 151 * The implementation of XMM registers for the IA32 architecture. 152 */ 153 class XMMRegister: public AbstractRegister { 154 public: 155 enum { 156 #ifndef AMD64 157 number_of_registers = 8 158 #else 159 number_of_registers = 16 160 #endif // AMD64 161 }; 162 163 /** 164 * Constructor to construct an invalid register. 165 */ 166 XMMRegister() : AbstractRegister(-1) {} 167 168 XMMRegister(int encoding) : AbstractRegister(encoding) {} 169 170 // construction 171 friend XMMRegister as_XMMRegister(int encoding); 172 173 VMReg as_VMReg() const; 174 175 // derived registers, offsets, and addresses 176 XMMRegister successor() const { 177 return XMMRegister(encoding() + 1); 178 } 179 180 bool is_valid() const { 181 return 0 <= encoding() && encoding() < number_of_registers; 182 } 183 184 const char* name() const; 185 }; 186 187 inline XMMRegister as_XMMRegister(int encoding) { 188 return XMMRegister(encoding); 189 } 190 191 /** 192 * Need to know the total number of registers of all sorts for SharedInfo. Define a class that exports it. 193 */ 194 class ConcreteRegisterImpl : public AbstractRegister { 195 public: 196 enum { 197 // A big enough number for C2: all the registers plus flags 198 // This number must be large enough to cover REG_COUNT (defined by c2) registers. 199 // There is no requirement that any ordering here matches any ordering c2 gives 200 // it's optoregs. 201 202 number_of_registers = Register::number_of_registers + 203 #ifdef AMD64 204 Register::number_of_registers + // "H" half of a 64bit register 205 #endif // AMD64 206 2 * FloatRegister::number_of_registers + 207 8 * XMMRegister::number_of_registers + 208 1 // eflags 209 }; 210 211 static const int max_gpr; 212 static const int max_fpr; 213 static const int max_xmm; 214 215 }; 216 217 // Calling convention 218 class Argument VALUE_OBJ_CLASS_SPEC { 219 public: 220 enum { 221 #ifdef _LP64 222 #ifdef _WIN64 223 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 224 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 225 #else 226 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 227 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 228 #endif // _WIN64 229 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 230 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 231 #else 232 n_register_parameters = 0 // 0 registers used to pass arguments 233 #endif // _LP64 234 }; 235 }; 236 237 /* 238 * CPU registers. 239 */ 240 static const Register noreg(-1); 241 242 static const Register rax(0); 243 static const Register rcx(1); 244 static const Register rdx(2); 245 static const Register rbx(3); 246 static const Register rsp(4); 247 static const Register rbp(5); 248 static const Register rsi(6); 249 static const Register rdi(7); 250 251 #ifdef AMD64 252 static const Register r8(8); 253 static const Register r9(9); 254 static const Register r10(10); 255 static const Register r11(11); 256 static const Register r12(12); 257 static const Register r13(13); 258 static const Register r14(14); 259 static const Register r15(15); 260 #endif 261 262 /* 263 * XMM registers. 264 */ 265 static const XMMRegister xnoreg(-1); 266 267 static const XMMRegister xmm0(0); 268 static const XMMRegister xmm1(1); 269 static const XMMRegister xmm2(2); 270 static const XMMRegister xmm3(3); 271 static const XMMRegister xmm4(4); 272 static const XMMRegister xmm5(5); 273 static const XMMRegister xmm6(6); 274 static const XMMRegister xmm7(7); 275 276 #ifdef AMD64 277 static const XMMRegister xmm8(8); 278 static const XMMRegister xmm9(9); 279 static const XMMRegister xmm10(10); 280 static const XMMRegister xmm11(11); 281 static const XMMRegister xmm12(12); 282 static const XMMRegister xmm13(13); 283 static const XMMRegister xmm14(14); 284 static const XMMRegister xmm15(15); 285 #endif 286 287 /* 288 * MMX registers. 289 * 290 * Only used by the 32bit stubGenerator. These can't be described by vmreg and hence 291 * can't be described in oopMaps and therefore can't be used by the compilers (at least 292 * were deopt might wan't to see them). 293 */ 294 static const MMXRegister mnoreg(-1); 295 296 static const MMXRegister mmx0(0); 297 static const MMXRegister mmx1(1); 298 static const MMXRegister mmx2(2); 299 static const MMXRegister mmx3(3); 300 static const MMXRegister mmx4(4); 301 static const MMXRegister mmx5(5); 302 static const MMXRegister mmx6(6); 303 static const MMXRegister mmx7(7); 304 305 #ifdef _LP64 306 // Symbolically name the register arguments used by the c calling convention. 307 // Windows is different from linux/solaris. So much for standards... 308 309 #ifdef _WIN64 310 311 static const Register c_rarg0 = rcx; 312 static const Register c_rarg1 = rdx; 313 static const Register c_rarg2 = r8; 314 static const Register c_rarg3 = r9; 315 316 static const XMMRegister c_farg0 = xmm0; 317 static const XMMRegister c_farg1 = xmm1; 318 static const XMMRegister c_farg2 = xmm2; 319 static const XMMRegister c_farg3 = xmm3; 320 321 #else 322 323 static const Register c_rarg0 = rdi; 324 static const Register c_rarg1 = rsi; 325 static const Register c_rarg2 = rdx; 326 static const Register c_rarg3 = rcx; 327 static const Register c_rarg4 = r8; 328 static const Register c_rarg5 = r9; 329 330 static const XMMRegister c_farg0 = xmm0; 331 static const XMMRegister c_farg1 = xmm1; 332 static const XMMRegister c_farg2 = xmm2; 333 static const XMMRegister c_farg3 = xmm3; 334 static const XMMRegister c_farg4 = xmm4; 335 static const XMMRegister c_farg5 = xmm5; 336 static const XMMRegister c_farg6 = xmm6; 337 static const XMMRegister c_farg7 = xmm7; 338 339 #endif // _WIN64 340 341 // Symbolically name the register arguments used by the Java calling convention. 342 // We have control over the convention for java so we can do what we please. 343 // What pleases us is to offset the java calling convention so that when 344 // we call a suitable jni method the arguments are lined up and we don't 345 // have to do little shuffling. A suitable jni method is non-static and a 346 // small number of arguments (two fewer args on windows) 347 // 348 // |-------------------------------------------------------| 349 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 350 // |-------------------------------------------------------| 351 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 352 // | rdi rsi rdx rcx r8 r9 | solaris/linux 353 // |-------------------------------------------------------| 354 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 355 // |-------------------------------------------------------| 356 357 static const Register j_rarg0 = c_rarg1; 358 static const Register j_rarg1 = c_rarg2; 359 static const Register j_rarg2 = c_rarg3; 360 // Windows runs out of register args here 361 static const Register j_rarg3 = NOT_WIN64(c_rarg4) WIN64_ONLY(rdi); 362 static const Register j_rarg4 = NOT_WIN64(c_rarg5) WIN64_ONLY(rsi); 363 static const Register j_rarg5 = c_rarg0; 364 365 static const XMMRegister j_farg0 = xmm0; 366 static const XMMRegister j_farg1 = xmm1; 367 static const XMMRegister j_farg2 = xmm2; 368 static const XMMRegister j_farg3 = xmm3; 369 static const XMMRegister j_farg4 = xmm4; 370 static const XMMRegister j_farg5 = xmm5; 371 static const XMMRegister j_farg6 = xmm6; 372 static const XMMRegister j_farg7 = xmm7; 373 374 static const Register rscratch1 = r10; // volatile 375 static const Register rscratch2 = r11; // volatile 376 377 static const Register r12_heapbase = r12; // callee-saved 378 static const Register r15_thread = r15; // callee-saved 379 380 #else 381 // rscratch1 will appear in 32bit code that is dead but of course must compile. 382 // Using noreg ensures if the dead code is incorrectly live and executed it 383 // will cause an assertion failure. 384 385 static const Register rscratch1 = noreg; 386 static const Register rscratch2 = noreg; 387 388 #endif // _LP64 389 390 // JSR 292 fixed register usages: 391 static const Register rbp_mh_SP_save = rbp; 392 393 #endif // CPU_X86_VM_REGISTER_X86_HPP |