--- old/src/cpu/x86/vm/x86_64.ad	2014-04-24 15:53:07.000000000 -1000
+++ new/src/cpu/x86/vm/x86_64.ad	2014-04-24 15:53:07.000000000 -1000
@@ -67,66 +67,66 @@
 // Turn off SOE in java-code due to frequent use of uncommon-traps.
 // Now that allocator is better, turn on RSI and RDI as SOE registers.
 
-reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
-reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
+reg_def RAX  (SOC, SOC, Op_RegI,  0, rax.as_VMReg());
+reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax.as_VMReg()->next());
 
-reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
-reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
+reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx.as_VMReg());
+reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx.as_VMReg()->next());
 
-reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
-reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
+reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx.as_VMReg());
+reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx.as_VMReg()->next());
 
-reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
-reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
+reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx.as_VMReg());
+reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx.as_VMReg()->next());
 
-reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
-reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
+reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp.as_VMReg());
+reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp.as_VMReg()->next());
 
 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
-reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
-reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
+reg_def RBP  (NS, SOE, Op_RegI,  5, rbp.as_VMReg());
+reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp.as_VMReg()->next());
 
 #ifdef _WIN64
 
-reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
-reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
+reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi.as_VMReg());
+reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi.as_VMReg()->next());
 
-reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
-reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
+reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi.as_VMReg());
+reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi.as_VMReg()->next());
 
 #else
 
-reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
-reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
+reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi.as_VMReg());
+reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi.as_VMReg()->next());
 
-reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
-reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
+reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi.as_VMReg());
+reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi.as_VMReg()->next());
 
 #endif
 
-reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
-reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
+reg_def R8   (SOC, SOC, Op_RegI,  8, r8.as_VMReg());
+reg_def R8_H (SOC, SOC, Op_RegI,  8, r8.as_VMReg()->next());
 
-reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
-reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
+reg_def R9   (SOC, SOC, Op_RegI,  9, r9.as_VMReg());
+reg_def R9_H (SOC, SOC, Op_RegI,  9, r9.as_VMReg()->next());
 
-reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
-reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
+reg_def R10  (SOC, SOC, Op_RegI, 10, r10.as_VMReg());
+reg_def R10_H(SOC, SOC, Op_RegI, 10, r10.as_VMReg()->next());
 
-reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
-reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
+reg_def R11  (SOC, SOC, Op_RegI, 11, r11.as_VMReg());
+reg_def R11_H(SOC, SOC, Op_RegI, 11, r11.as_VMReg()->next());
 
-reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
-reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
+reg_def R12  (SOC, SOE, Op_RegI, 12, r12.as_VMReg());
+reg_def R12_H(SOC, SOE, Op_RegI, 12, r12.as_VMReg()->next());
 
-reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
-reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
+reg_def R13  (SOC, SOE, Op_RegI, 13, r13.as_VMReg());
+reg_def R13_H(SOC, SOE, Op_RegI, 13, r13.as_VMReg()->next());
 
-reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
-reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
+reg_def R14  (SOC, SOE, Op_RegI, 14, r14.as_VMReg());
+reg_def R14_H(SOC, SOE, Op_RegI, 14, r14.as_VMReg()->next());
 
-reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
-reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
+reg_def R15  (SOC, SOE, Op_RegI, 15, r15.as_VMReg());
+reg_def R15_H(SOC, SOE, Op_RegI, 15, r15.as_VMReg()->next());
 
 
 // Floating Point Registers