1 /*
   2  * Copyright (c) 2005, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "utilities/bitMap.inline.hpp"
  35 #ifdef TARGET_ARCH_x86
  36 # include "vmreg_x86.inline.hpp"
  37 #endif
  38 #ifdef TARGET_ARCH_sparc
  39 # include "vmreg_sparc.inline.hpp"
  40 #endif
  41 #ifdef TARGET_ARCH_zero
  42 # include "vmreg_zero.inline.hpp"
  43 #endif
  44 #ifdef TARGET_ARCH_arm
  45 # include "vmreg_arm.inline.hpp"
  46 #endif
  47 #ifdef TARGET_ARCH_ppc
  48 # include "vmreg_ppc.inline.hpp"
  49 #endif
  50 
  51 
  52 #ifndef PRODUCT
  53 
  54   static LinearScanStatistic _stat_before_alloc;
  55   static LinearScanStatistic _stat_after_asign;
  56   static LinearScanStatistic _stat_final;
  57 
  58   static LinearScanTimers _total_timer;
  59 
  60   // helper macro for short definition of timer
  61   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  62 
  63   // helper macro for short definition of trace-output inside code
  64   #define TRACE_LINEAR_SCAN(level, code)       \
  65     if (TraceLinearScanLevel >= level) {       \
  66       code;                                    \
  67     }
  68 
  69 #else
  70 
  71   #define TIME_LINEAR_SCAN(timer_name)
  72   #define TRACE_LINEAR_SCAN(level, code)
  73 
  74 #endif
  75 
  76 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  77 #ifdef _LP64
  78 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  79 #else
  80 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  81 #endif
  82 
  83 
  84 // Implementation of LinearScan
  85 
  86 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  87  : _compilation(ir->compilation())
  88  , _ir(ir)
  89  , _gen(gen)
  90  , _frame_map(frame_map)
  91  , _num_virtual_regs(gen->max_virtual_register_number())
  92  , _has_fpu_registers(false)
  93  , _num_calls(-1)
  94  , _max_spills(0)
  95  , _unused_spill_slot(-1)
  96  , _intervals(0)   // initialized later with correct length
  97  , _new_intervals_from_allocation(new IntervalList())
  98  , _sorted_intervals(NULL)
  99  , _needs_full_resort(false)
 100  , _lir_ops(0)     // initialized later with correct length
 101  , _block_of_op(0) // initialized later with correct length
 102  , _has_info(0)
 103  , _has_call(0)
 104  , _scope_value_cache(0) // initialized later with correct length
 105  , _interval_in_loop(0, 0) // initialized later with correct length
 106  , _cached_blocks(*ir->linear_scan_order())
 107 #ifdef X86
 108  , _fpu_stack_allocator(NULL)
 109 #endif
 110 {
 111   assert(this->ir() != NULL,          "check if valid");
 112   assert(this->compilation() != NULL, "check if valid");
 113   assert(this->gen() != NULL,         "check if valid");
 114   assert(this->frame_map() != NULL,   "check if valid");
 115 }
 116 
 117 
 118 // ********** functions for converting LIR-Operands to register numbers
 119 //
 120 // Emulate a flat register file comprising physical integer registers,
 121 // physical floating-point registers and virtual registers, in that order.
 122 // Virtual registers already have appropriate numbers, since V0 is
 123 // the number of physical registers.
 124 // Returns -1 for hi word if opr is a single word operand.
 125 //
 126 // Note: the inverse operation (calculating an operand for register numbers)
 127 //       is done in calc_operand_for_interval()
 128 
 129 int LinearScan::reg_num(LIR_Opr opr) {
 130   assert(opr->is_register(), "should not call this otherwise");
 131 
 132   if (opr->is_virtual_register()) {
 133     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 134     return opr->vreg_number();
 135   } else if (opr->is_single_cpu()) {
 136     return opr->cpu_regnr();
 137   } else if (opr->is_double_cpu()) {
 138     return opr->cpu_regnrLo();
 139 #ifdef X86
 140   } else if (opr->is_single_xmm()) {
 141     return opr->fpu_regnr() + pd_first_xmm_reg;
 142   } else if (opr->is_double_xmm()) {
 143     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 144 #endif
 145   } else if (opr->is_single_fpu()) {
 146     return opr->fpu_regnr() + pd_first_fpu_reg;
 147   } else if (opr->is_double_fpu()) {
 148     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 149   } else {
 150     ShouldNotReachHere();
 151     return -1;
 152   }
 153 }
 154 
 155 int LinearScan::reg_numHi(LIR_Opr opr) {
 156   assert(opr->is_register(), "should not call this otherwise");
 157 
 158   if (opr->is_virtual_register()) {
 159     return -1;
 160   } else if (opr->is_single_cpu()) {
 161     return -1;
 162   } else if (opr->is_double_cpu()) {
 163     return opr->cpu_regnrHi();
 164 #ifdef X86
 165   } else if (opr->is_single_xmm()) {
 166     return -1;
 167   } else if (opr->is_double_xmm()) {
 168     return -1;
 169 #endif
 170   } else if (opr->is_single_fpu()) {
 171     return -1;
 172   } else if (opr->is_double_fpu()) {
 173     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 174   } else {
 175     ShouldNotReachHere();
 176     return -1;
 177   }
 178 }
 179 
 180 
 181 // ********** functions for classification of intervals
 182 
 183 bool LinearScan::is_precolored_interval(const Interval* i) {
 184   return i->reg_num() < LinearScan::nof_regs;
 185 }
 186 
 187 bool LinearScan::is_virtual_interval(const Interval* i) {
 188   return i->reg_num() >= LIR_OprDesc::vreg_base;
 189 }
 190 
 191 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 192   return i->reg_num() < LinearScan::nof_cpu_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return i->reg_num() >= LIR_OprDesc::vreg_base;
 198 #else
 199   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 204   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 205 }
 206 
 207 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 208 #if defined(__SOFTFP__) || defined(E500V2)
 209   return false;
 210 #else
 211   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 212 #endif // __SOFTFP__ or E500V2
 213 }
 214 
 215 bool LinearScan::is_in_fpu_register(const Interval* i) {
 216   // fixed intervals not needed for FPU stack allocation
 217   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 218 }
 219 
 220 bool LinearScan::is_oop_interval(const Interval* i) {
 221   // fixed intervals never contain oops
 222   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 223 }
 224 
 225 
 226 // ********** General helper functions
 227 
 228 // compute next unused stack index that can be used for spilling
 229 int LinearScan::allocate_spill_slot(bool double_word) {
 230   int spill_slot;
 231   if (double_word) {
 232     if ((_max_spills & 1) == 1) {
 233       // alignment of double-word values
 234       // the hole because of the alignment is filled with the next single-word value
 235       assert(_unused_spill_slot == -1, "wasting a spill slot");
 236       _unused_spill_slot = _max_spills;
 237       _max_spills++;
 238     }
 239     spill_slot = _max_spills;
 240     _max_spills += 2;
 241 
 242   } else if (_unused_spill_slot != -1) {
 243     // re-use hole that was the result of a previous double-word alignment
 244     spill_slot = _unused_spill_slot;
 245     _unused_spill_slot = -1;
 246 
 247   } else {
 248     spill_slot = _max_spills;
 249     _max_spills++;
 250   }
 251 
 252   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 253 
 254   // the class OopMapValue uses only 11 bits for storing the name of the
 255   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 256   // that is not reported in product builds. Prevent this by checking the
 257   // spill slot here (altough this value and the later used location name
 258   // are slightly different)
 259   if (result > 2000) {
 260     bailout("too many stack slots used");
 261   }
 262 
 263   return result;
 264 }
 265 
 266 void LinearScan::assign_spill_slot(Interval* it) {
 267   // assign the canonical spill slot of the parent (if a part of the interval
 268   // is already spilled) or allocate a new spill slot
 269   if (it->canonical_spill_slot() >= 0) {
 270     it->assign_reg(it->canonical_spill_slot());
 271   } else {
 272     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 273     it->set_canonical_spill_slot(spill);
 274     it->assign_reg(spill);
 275   }
 276 }
 277 
 278 void LinearScan::propagate_spill_slots() {
 279   if (!frame_map()->finalize_frame(max_spills())) {
 280     bailout("frame too large");
 281   }
 282 }
 283 
 284 // create a new interval with a predefined reg_num
 285 // (only used for parent intervals that are created during the building phase)
 286 Interval* LinearScan::create_interval(int reg_num) {
 287   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 288 
 289   Interval* interval = new Interval(reg_num);
 290   _intervals.at_put(reg_num, interval);
 291 
 292   // assign register number for precolored intervals
 293   if (reg_num < LIR_OprDesc::vreg_base) {
 294     interval->assign_reg(reg_num);
 295   }
 296   return interval;
 297 }
 298 
 299 // assign a new reg_num to the interval and append it to the list of intervals
 300 // (only used for child intervals that are created during register allocation)
 301 void LinearScan::append_interval(Interval* it) {
 302   it->set_reg_num(_intervals.length());
 303   _intervals.append(it);
 304   _new_intervals_from_allocation->append(it);
 305 }
 306 
 307 // copy the vreg-flags if an interval is split
 308 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 309   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 310     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 311   }
 312   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 313     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 314   }
 315 
 316   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 317   //       intervals (only the very beginning of the interval must be in memory)
 318 }
 319 
 320 
 321 // ********** spill move optimization
 322 // eliminate moves from register to stack if stack slot is known to be correct
 323 
 324 // called during building of intervals
 325 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 326   assert(interval->is_split_parent(), "can only be called for split parents");
 327 
 328   switch (interval->spill_state()) {
 329     case noDefinitionFound:
 330       assert(interval->spill_definition_pos() == -1, "must no be set before");
 331       interval->set_spill_definition_pos(def_pos);
 332       interval->set_spill_state(oneDefinitionFound);
 333       break;
 334 
 335     case oneDefinitionFound:
 336       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 337       if (def_pos < interval->spill_definition_pos() - 2) {
 338         // second definition found, so no spill optimization possible for this interval
 339         interval->set_spill_state(noOptimization);
 340       } else {
 341         // two consecutive definitions (because of two-operand LIR form)
 342         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 343       }
 344       break;
 345 
 346     case noOptimization:
 347       // nothing to do
 348       break;
 349 
 350     default:
 351       assert(false, "other states not allowed at this time");
 352   }
 353 }
 354 
 355 // called during register allocation
 356 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 357   switch (interval->spill_state()) {
 358     case oneDefinitionFound: {
 359       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 360       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 361 
 362       if (def_loop_depth < spill_loop_depth) {
 363         // the loop depth of the spilling position is higher then the loop depth
 364         // at the definition of the interval -> move write to memory out of loop
 365         // by storing at definitin of the interval
 366         interval->set_spill_state(storeAtDefinition);
 367       } else {
 368         // the interval is currently spilled only once, so for now there is no
 369         // reason to store the interval at the definition
 370         interval->set_spill_state(oneMoveInserted);
 371       }
 372       break;
 373     }
 374 
 375     case oneMoveInserted: {
 376       // the interval is spilled more then once, so it is better to store it to
 377       // memory at the definition
 378       interval->set_spill_state(storeAtDefinition);
 379       break;
 380     }
 381 
 382     case storeAtDefinition:
 383     case startInMemory:
 384     case noOptimization:
 385     case noDefinitionFound:
 386       // nothing to do
 387       break;
 388 
 389     default:
 390       assert(false, "other states not allowed at this time");
 391   }
 392 }
 393 
 394 
 395 bool LinearScan::must_store_at_definition(const Interval* i) {
 396   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 397 }
 398 
 399 // called once before asignment of register numbers
 400 void LinearScan::eliminate_spill_moves() {
 401   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 402   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 403 
 404   // collect all intervals that must be stored after their definion.
 405   // the list is sorted by Interval::spill_definition_pos
 406   Interval* interval;
 407   Interval* temp_list;
 408   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 409 
 410 #ifdef ASSERT
 411   Interval* prev = NULL;
 412   Interval* temp = interval;
 413   while (temp != Interval::end()) {
 414     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 415     if (prev != NULL) {
 416       assert(temp->from() >= prev->from(), "intervals not sorted");
 417       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 418     }
 419 
 420     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 421     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 422     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 423 
 424     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 425 
 426     temp = temp->next();
 427   }
 428 #endif
 429 
 430   LIR_InsertionBuffer insertion_buffer;
 431   int num_blocks = block_count();
 432   for (int i = 0; i < num_blocks; i++) {
 433     BlockBegin* block = block_at(i);
 434     LIR_OpList* instructions = block->lir()->instructions_list();
 435     int         num_inst = instructions->length();
 436     bool        has_new = false;
 437 
 438     // iterate all instructions of the block. skip the first because it is always a label
 439     for (int j = 1; j < num_inst; j++) {
 440       LIR_Op* op = instructions->at(j);
 441       int op_id = op->id();
 442 
 443       if (op_id == -1) {
 444         // remove move from register to stack if the stack slot is guaranteed to be correct.
 445         // only moves that have been inserted by LinearScan can be removed.
 446         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 447         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 448         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 449 
 450         LIR_Op1* op1 = (LIR_Op1*)op;
 451         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 452 
 453         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 454           // move target is a stack slot that is always correct, so eliminate instruction
 455           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 456           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 457         }
 458 
 459       } else {
 460         // insert move from register to stack just after the beginning of the interval
 461         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 462         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 463 
 464         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 465           if (!has_new) {
 466             // prepare insertion buffer (appended when all instructions of the block are processed)
 467             insertion_buffer.init(block->lir());
 468             has_new = true;
 469           }
 470 
 471           LIR_Opr from_opr = operand_for_interval(interval);
 472           LIR_Opr to_opr = canonical_spill_opr(interval);
 473           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 474           assert(to_opr->is_stack(), "to operand must be a stack slot");
 475 
 476           insertion_buffer.move(j, from_opr, to_opr);
 477           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 478 
 479           interval = interval->next();
 480         }
 481       }
 482     } // end of instruction iteration
 483 
 484     if (has_new) {
 485       block->lir()->append(&insertion_buffer);
 486     }
 487   } // end of block iteration
 488 
 489   assert(interval == Interval::end(), "missed an interval");
 490 }
 491 
 492 
 493 // ********** Phase 1: number all instructions in all blocks
 494 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 495 
 496 void LinearScan::number_instructions() {
 497   {
 498     // dummy-timer to measure the cost of the timer itself
 499     // (this time is then subtracted from all other timers to get the real value)
 500     TIME_LINEAR_SCAN(timer_do_nothing);
 501   }
 502   TIME_LINEAR_SCAN(timer_number_instructions);
 503 
 504   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 505   int num_blocks = block_count();
 506   int num_instructions = 0;
 507   int i;
 508   for (i = 0; i < num_blocks; i++) {
 509     num_instructions += block_at(i)->lir()->instructions_list()->length();
 510   }
 511 
 512   // initialize with correct length
 513   _lir_ops = LIR_OpArray(num_instructions);
 514   _block_of_op = BlockBeginArray(num_instructions);
 515 
 516   int op_id = 0;
 517   int idx = 0;
 518 
 519   for (i = 0; i < num_blocks; i++) {
 520     BlockBegin* block = block_at(i);
 521     block->set_first_lir_instruction_id(op_id);
 522     LIR_OpList* instructions = block->lir()->instructions_list();
 523 
 524     int num_inst = instructions->length();
 525     for (int j = 0; j < num_inst; j++) {
 526       LIR_Op* op = instructions->at(j);
 527       op->set_id(op_id);
 528 
 529       _lir_ops.at_put(idx, op);
 530       _block_of_op.at_put(idx, block);
 531       assert(lir_op_with_id(op_id) == op, "must match");
 532 
 533       idx++;
 534       op_id += 2; // numbering of lir_ops by two
 535     }
 536     block->set_last_lir_instruction_id(op_id - 2);
 537   }
 538   assert(idx == num_instructions, "must match");
 539   assert(idx * 2 == op_id, "must match");
 540 
 541   _has_call = BitMap(num_instructions); _has_call.clear();
 542   _has_info = BitMap(num_instructions); _has_info.clear();
 543 }
 544 
 545 
 546 // ********** Phase 2: compute local live sets separately for each block
 547 // (sets live_gen and live_kill for each block)
 548 
 549 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 550   LIR_Opr opr = value->operand();
 551   Constant* con = value->as_Constant();
 552 
 553   // check some asumptions about debug information
 554   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 555   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 556   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 557 
 558   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 559     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 560     int reg = opr->vreg_number();
 561     if (!live_kill.at(reg)) {
 562       live_gen.set_bit(reg);
 563       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 564     }
 565   }
 566 }
 567 
 568 
 569 void LinearScan::compute_local_live_sets() {
 570   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 571 
 572   int  num_blocks = block_count();
 573   int  live_size = live_set_size();
 574   bool local_has_fpu_registers = false;
 575   int  local_num_calls = 0;
 576   LIR_OpVisitState visitor;
 577 
 578   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 579   local_interval_in_loop.clear();
 580 
 581   // iterate all blocks
 582   for (int i = 0; i < num_blocks; i++) {
 583     BlockBegin* block = block_at(i);
 584 
 585     BitMap live_gen(live_size);  live_gen.clear();
 586     BitMap live_kill(live_size); live_kill.clear();
 587 
 588     if (block->is_set(BlockBegin::exception_entry_flag)) {
 589       // Phi functions at the begin of an exception handler are
 590       // implicitly defined (= killed) at the beginning of the block.
 591       for_each_phi_fun(block, phi,
 592         live_kill.set_bit(phi->operand()->vreg_number())
 593       );
 594     }
 595 
 596     LIR_OpList* instructions = block->lir()->instructions_list();
 597     int num_inst = instructions->length();
 598 
 599     // iterate all instructions of the block. skip the first because it is always a label
 600     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 601     for (int j = 1; j < num_inst; j++) {
 602       LIR_Op* op = instructions->at(j);
 603 
 604       // visit operation to collect all operands
 605       visitor.visit(op);
 606 
 607       if (visitor.has_call()) {
 608         _has_call.set_bit(op->id() >> 1);
 609         local_num_calls++;
 610       }
 611       if (visitor.info_count() > 0) {
 612         _has_info.set_bit(op->id() >> 1);
 613       }
 614 
 615       // iterate input operands of instruction
 616       int k, n, reg;
 617       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 618       for (k = 0; k < n; k++) {
 619         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 620         assert(opr->is_register(), "visitor should only return register operands");
 621 
 622         if (opr->is_virtual_register()) {
 623           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 624           reg = opr->vreg_number();
 625           if (!live_kill.at(reg)) {
 626             live_gen.set_bit(reg);
 627             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 628           }
 629           if (block->loop_index() >= 0) {
 630             local_interval_in_loop.set_bit(reg, block->loop_index());
 631           }
 632           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 633         }
 634 
 635 #ifdef ASSERT
 636         // fixed intervals are never live at block boundaries, so
 637         // they need not be processed in live sets.
 638         // this is checked by these assertions to be sure about it.
 639         // the entry block may have incoming values in registers, which is ok.
 640         if (!opr->is_virtual_register() && block != ir()->start()) {
 641           reg = reg_num(opr);
 642           if (is_processed_reg_num(reg)) {
 643             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 644           }
 645           reg = reg_numHi(opr);
 646           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 647             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 648           }
 649         }
 650 #endif
 651       }
 652 
 653       // Add uses of live locals from interpreter's point of view for proper debug information generation
 654       n = visitor.info_count();
 655       for (k = 0; k < n; k++) {
 656         CodeEmitInfo* info = visitor.info_at(k);
 657         ValueStack* stack = info->stack();
 658         for_each_state_value(stack, value,
 659           set_live_gen_kill(value, op, live_gen, live_kill)
 660         );
 661       }
 662 
 663       // iterate temp operands of instruction
 664       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 665       for (k = 0; k < n; k++) {
 666         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 667         assert(opr->is_register(), "visitor should only return register operands");
 668 
 669         if (opr->is_virtual_register()) {
 670           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 671           reg = opr->vreg_number();
 672           live_kill.set_bit(reg);
 673           if (block->loop_index() >= 0) {
 674             local_interval_in_loop.set_bit(reg, block->loop_index());
 675           }
 676           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 677         }
 678 
 679 #ifdef ASSERT
 680         // fixed intervals are never live at block boundaries, so
 681         // they need not be processed in live sets
 682         // process them only in debug mode so that this can be checked
 683         if (!opr->is_virtual_register()) {
 684           reg = reg_num(opr);
 685           if (is_processed_reg_num(reg)) {
 686             live_kill.set_bit(reg_num(opr));
 687           }
 688           reg = reg_numHi(opr);
 689           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 690             live_kill.set_bit(reg);
 691           }
 692         }
 693 #endif
 694       }
 695 
 696       // iterate output operands of instruction
 697       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 698       for (k = 0; k < n; k++) {
 699         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 700         assert(opr->is_register(), "visitor should only return register operands");
 701 
 702         if (opr->is_virtual_register()) {
 703           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 704           reg = opr->vreg_number();
 705           live_kill.set_bit(reg);
 706           if (block->loop_index() >= 0) {
 707             local_interval_in_loop.set_bit(reg, block->loop_index());
 708           }
 709           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 710         }
 711 
 712 #ifdef ASSERT
 713         // fixed intervals are never live at block boundaries, so
 714         // they need not be processed in live sets
 715         // process them only in debug mode so that this can be checked
 716         if (!opr->is_virtual_register()) {
 717           reg = reg_num(opr);
 718           if (is_processed_reg_num(reg)) {
 719             live_kill.set_bit(reg_num(opr));
 720           }
 721           reg = reg_numHi(opr);
 722           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 723             live_kill.set_bit(reg);
 724           }
 725         }
 726 #endif
 727       }
 728     } // end of instruction iteration
 729 
 730     block->set_live_gen (live_gen);
 731     block->set_live_kill(live_kill);
 732     block->set_live_in  (BitMap(live_size)); block->live_in().clear();
 733     block->set_live_out (BitMap(live_size)); block->live_out().clear();
 734 
 735     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 736     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 737   } // end of block iteration
 738 
 739   // propagate local calculated information into LinearScan object
 740   _has_fpu_registers = local_has_fpu_registers;
 741   compilation()->set_has_fpu_code(local_has_fpu_registers);
 742 
 743   _num_calls = local_num_calls;
 744   _interval_in_loop = local_interval_in_loop;
 745 }
 746 
 747 
 748 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 749 // (sets live_in and live_out for each block)
 750 
 751 void LinearScan::compute_global_live_sets() {
 752   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 753 
 754   int  num_blocks = block_count();
 755   bool change_occurred;
 756   bool change_occurred_in_block;
 757   int  iteration_count = 0;
 758   BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
 759 
 760   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 761   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 762   // Exception handlers must be processed because not all live values are
 763   // present in the state array, e.g. because of global value numbering
 764   do {
 765     change_occurred = false;
 766 
 767     // iterate all blocks in reverse order
 768     for (int i = num_blocks - 1; i >= 0; i--) {
 769       BlockBegin* block = block_at(i);
 770 
 771       change_occurred_in_block = false;
 772 
 773       // live_out(block) is the union of live_in(sux), for successors sux of block
 774       int n = block->number_of_sux();
 775       int e = block->number_of_exception_handlers();
 776       if (n + e > 0) {
 777         // block has successors
 778         if (n > 0) {
 779           live_out.set_from(block->sux_at(0)->live_in());
 780           for (int j = 1; j < n; j++) {
 781             live_out.set_union(block->sux_at(j)->live_in());
 782           }
 783         } else {
 784           live_out.clear();
 785         }
 786         for (int j = 0; j < e; j++) {
 787           live_out.set_union(block->exception_handler_at(j)->live_in());
 788         }
 789 
 790         if (!block->live_out().is_same(live_out)) {
 791           // A change occurred.  Swap the old and new live out sets to avoid copying.
 792           BitMap temp = block->live_out();
 793           block->set_live_out(live_out);
 794           live_out = temp;
 795 
 796           change_occurred = true;
 797           change_occurred_in_block = true;
 798         }
 799       }
 800 
 801       if (iteration_count == 0 || change_occurred_in_block) {
 802         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 803         // note: live_in has to be computed only in first iteration or if live_out has changed!
 804         BitMap live_in = block->live_in();
 805         live_in.set_from(block->live_out());
 806         live_in.set_difference(block->live_kill());
 807         live_in.set_union(block->live_gen());
 808       }
 809 
 810 #ifndef PRODUCT
 811       if (TraceLinearScanLevel >= 4) {
 812         char c = ' ';
 813         if (iteration_count == 0 || change_occurred_in_block) {
 814           c = '*';
 815         }
 816         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 817         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 818       }
 819 #endif
 820     }
 821     iteration_count++;
 822 
 823     if (change_occurred && iteration_count > 50) {
 824       BAILOUT("too many iterations in compute_global_live_sets");
 825     }
 826   } while (change_occurred);
 827 
 828 
 829 #ifdef ASSERT
 830   // check that fixed intervals are not live at block boundaries
 831   // (live set must be empty at fixed intervals)
 832   for (int i = 0; i < num_blocks; i++) {
 833     BlockBegin* block = block_at(i);
 834     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 835       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 836       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 837       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 838     }
 839   }
 840 #endif
 841 
 842   // check that the live_in set of the first block is empty
 843   BitMap live_in_args(ir()->start()->live_in().size());
 844   live_in_args.clear();
 845   if (!ir()->start()->live_in().is_same(live_in_args)) {
 846 #ifdef ASSERT
 847     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 848     tty->print_cr("affected registers:");
 849     print_bitmap(ir()->start()->live_in());
 850 
 851     // print some additional information to simplify debugging
 852     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 853       if (ir()->start()->live_in().at(i)) {
 854         Instruction* instr = gen()->instruction_for_vreg(i);
 855         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 856 
 857         for (int j = 0; j < num_blocks; j++) {
 858           BlockBegin* block = block_at(j);
 859           if (block->live_gen().at(i)) {
 860             tty->print_cr("  used in block B%d", block->block_id());
 861           }
 862           if (block->live_kill().at(i)) {
 863             tty->print_cr("  defined in block B%d", block->block_id());
 864           }
 865         }
 866       }
 867     }
 868 
 869 #endif
 870     // when this fails, virtual registers are used before they are defined.
 871     assert(false, "live_in set of first block must be empty");
 872     // bailout of if this occurs in product mode.
 873     bailout("live_in set of first block not empty");
 874   }
 875 }
 876 
 877 
 878 // ********** Phase 4: build intervals
 879 // (fills the list _intervals)
 880 
 881 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 882   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 883   LIR_Opr opr = value->operand();
 884   Constant* con = value->as_Constant();
 885 
 886   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 887     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 888     add_use(opr, from, to, use_kind);
 889   }
 890 }
 891 
 892 
 893 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 894   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 895   assert(opr->is_register(), "should not be called otherwise");
 896 
 897   if (opr->is_virtual_register()) {
 898     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 899     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 900 
 901   } else {
 902     int reg = reg_num(opr);
 903     if (is_processed_reg_num(reg)) {
 904       add_def(reg, def_pos, use_kind, opr->type_register());
 905     }
 906     reg = reg_numHi(opr);
 907     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 908       add_def(reg, def_pos, use_kind, opr->type_register());
 909     }
 910   }
 911 }
 912 
 913 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 914   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 915   assert(opr->is_register(), "should not be called otherwise");
 916 
 917   if (opr->is_virtual_register()) {
 918     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 919     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 920 
 921   } else {
 922     int reg = reg_num(opr);
 923     if (is_processed_reg_num(reg)) {
 924       add_use(reg, from, to, use_kind, opr->type_register());
 925     }
 926     reg = reg_numHi(opr);
 927     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 928       add_use(reg, from, to, use_kind, opr->type_register());
 929     }
 930   }
 931 }
 932 
 933 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 934   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 935   assert(opr->is_register(), "should not be called otherwise");
 936 
 937   if (opr->is_virtual_register()) {
 938     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 939     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 940 
 941   } else {
 942     int reg = reg_num(opr);
 943     if (is_processed_reg_num(reg)) {
 944       add_temp(reg, temp_pos, use_kind, opr->type_register());
 945     }
 946     reg = reg_numHi(opr);
 947     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 948       add_temp(reg, temp_pos, use_kind, opr->type_register());
 949     }
 950   }
 951 }
 952 
 953 
 954 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 955   Interval* interval = interval_at(reg_num);
 956   if (interval != NULL) {
 957     assert(interval->reg_num() == reg_num, "wrong interval");
 958 
 959     if (type != T_ILLEGAL) {
 960       interval->set_type(type);
 961     }
 962 
 963     Range* r = interval->first();
 964     if (r->from() <= def_pos) {
 965       // Update the starting point (when a range is first created for a use, its
 966       // start is the beginning of the current block until a def is encountered.)
 967       r->set_from(def_pos);
 968       interval->add_use_pos(def_pos, use_kind);
 969 
 970     } else {
 971       // Dead value - make vacuous interval
 972       // also add use_kind for dead intervals
 973       interval->add_range(def_pos, def_pos + 1);
 974       interval->add_use_pos(def_pos, use_kind);
 975       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 976     }
 977 
 978   } else {
 979     // Dead value - make vacuous interval
 980     // also add use_kind for dead intervals
 981     interval = create_interval(reg_num);
 982     if (type != T_ILLEGAL) {
 983       interval->set_type(type);
 984     }
 985 
 986     interval->add_range(def_pos, def_pos + 1);
 987     interval->add_use_pos(def_pos, use_kind);
 988     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 989   }
 990 
 991   change_spill_definition_pos(interval, def_pos);
 992   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 993         // detection of method-parameters and roundfp-results
 994         // TODO: move this directly to position where use-kind is computed
 995     interval->set_spill_state(startInMemory);
 996   }
 997 }
 998 
 999 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
1000   Interval* interval = interval_at(reg_num);
1001   if (interval == NULL) {
1002     interval = create_interval(reg_num);
1003   }
1004   assert(interval->reg_num() == reg_num, "wrong interval");
1005 
1006   if (type != T_ILLEGAL) {
1007     interval->set_type(type);
1008   }
1009 
1010   interval->add_range(from, to);
1011   interval->add_use_pos(to, use_kind);
1012 }
1013 
1014 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1015   Interval* interval = interval_at(reg_num);
1016   if (interval == NULL) {
1017     interval = create_interval(reg_num);
1018   }
1019   assert(interval->reg_num() == reg_num, "wrong interval");
1020 
1021   if (type != T_ILLEGAL) {
1022     interval->set_type(type);
1023   }
1024 
1025   interval->add_range(temp_pos, temp_pos + 1);
1026   interval->add_use_pos(temp_pos, use_kind);
1027 }
1028 
1029 
1030 // the results of this functions are used for optimizing spilling and reloading
1031 // if the functions return shouldHaveRegister and the interval is spilled,
1032 // it is not reloaded to a register.
1033 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1034   if (op->code() == lir_move) {
1035     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1036     LIR_Op1* move = (LIR_Op1*)op;
1037     LIR_Opr res = move->result_opr();
1038     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1039 
1040     if (result_in_memory) {
1041       // Begin of an interval with must_start_in_memory set.
1042       // This interval will always get a stack slot first, so return noUse.
1043       return noUse;
1044 
1045     } else if (move->in_opr()->is_stack()) {
1046       // method argument (condition must be equal to handle_method_arguments)
1047       return noUse;
1048 
1049     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1050       // Move from register to register
1051       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1052         // special handling of phi-function moves inside osr-entry blocks
1053         // input operand must have a register instead of output operand (leads to better register allocation)
1054         return shouldHaveRegister;
1055       }
1056     }
1057   }
1058 
1059   if (opr->is_virtual() &&
1060       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1061     // result is a stack-slot, so prevent immediate reloading
1062     return noUse;
1063   }
1064 
1065   // all other operands require a register
1066   return mustHaveRegister;
1067 }
1068 
1069 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1070   if (op->code() == lir_move) {
1071     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1072     LIR_Op1* move = (LIR_Op1*)op;
1073     LIR_Opr res = move->result_opr();
1074     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1075 
1076     if (result_in_memory) {
1077       // Move to an interval with must_start_in_memory set.
1078       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1079       return mustHaveRegister;
1080 
1081     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1082       // Move from register to register
1083       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1084         // special handling of phi-function moves inside osr-entry blocks
1085         // input operand must have a register instead of output operand (leads to better register allocation)
1086         return mustHaveRegister;
1087       }
1088 
1089       // The input operand is not forced to a register (moves from stack to register are allowed),
1090       // but it is faster if the input operand is in a register
1091       return shouldHaveRegister;
1092     }
1093   }
1094 
1095 
1096 #ifdef X86
1097   if (op->code() == lir_cmove) {
1098     // conditional moves can handle stack operands
1099     assert(op->result_opr()->is_register(), "result must always be in a register");
1100     return shouldHaveRegister;
1101   }
1102 
1103   // optimizations for second input operand of arithmehtic operations on Intel
1104   // this operand is allowed to be on the stack in some cases
1105   BasicType opr_type = opr->type_register();
1106   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1107     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1108       // SSE float instruction (T_DOUBLE only supported with SSE2)
1109       switch (op->code()) {
1110         case lir_cmp:
1111         case lir_add:
1112         case lir_sub:
1113         case lir_mul:
1114         case lir_div:
1115         {
1116           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1117           LIR_Op2* op2 = (LIR_Op2*)op;
1118           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1119             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1120             return shouldHaveRegister;
1121           }
1122         }
1123       }
1124     } else {
1125       // FPU stack float instruction
1126       switch (op->code()) {
1127         case lir_add:
1128         case lir_sub:
1129         case lir_mul:
1130         case lir_div:
1131         {
1132           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1133           LIR_Op2* op2 = (LIR_Op2*)op;
1134           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1135             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1136             return shouldHaveRegister;
1137           }
1138         }
1139       }
1140     }
1141     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1142     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1143     // T_OBJECT doesn't get spilled along with T_LONG.
1144   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1145     // integer instruction (note: long operands must always be in register)
1146     switch (op->code()) {
1147       case lir_cmp:
1148       case lir_add:
1149       case lir_sub:
1150       case lir_logic_and:
1151       case lir_logic_or:
1152       case lir_logic_xor:
1153       {
1154         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1155         LIR_Op2* op2 = (LIR_Op2*)op;
1156         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1157           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1158           return shouldHaveRegister;
1159         }
1160       }
1161     }
1162   }
1163 #endif // X86
1164 
1165   // all other operands require a register
1166   return mustHaveRegister;
1167 }
1168 
1169 
1170 void LinearScan::handle_method_arguments(LIR_Op* op) {
1171   // special handling for method arguments (moves from stack to virtual register):
1172   // the interval gets no register assigned, but the stack slot.
1173   // it is split before the first use by the register allocator.
1174 
1175   if (op->code() == lir_move) {
1176     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1177     LIR_Op1* move = (LIR_Op1*)op;
1178 
1179     if (move->in_opr()->is_stack()) {
1180 #ifdef ASSERT
1181       int arg_size = compilation()->method()->arg_size();
1182       LIR_Opr o = move->in_opr();
1183       if (o->is_single_stack()) {
1184         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1185       } else if (o->is_double_stack()) {
1186         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1187       } else {
1188         ShouldNotReachHere();
1189       }
1190 
1191       assert(move->id() > 0, "invalid id");
1192       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1193       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1194 
1195       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1196 #endif
1197 
1198       Interval* interval = interval_at(reg_num(move->result_opr()));
1199 
1200       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1201       interval->set_canonical_spill_slot(stack_slot);
1202       interval->assign_reg(stack_slot);
1203     }
1204   }
1205 }
1206 
1207 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1208   // special handling for doubleword move from memory to register:
1209   // in this case the registers of the input address and the result
1210   // registers must not overlap -> add a temp range for the input registers
1211   if (op->code() == lir_move) {
1212     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1213     LIR_Op1* move = (LIR_Op1*)op;
1214 
1215     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1216       LIR_Address* address = move->in_opr()->as_address_ptr();
1217       if (address != NULL) {
1218         if (address->base()->is_valid()) {
1219           add_temp(address->base(), op->id(), noUse);
1220         }
1221         if (address->index()->is_valid()) {
1222           add_temp(address->index(), op->id(), noUse);
1223         }
1224       }
1225     }
1226   }
1227 }
1228 
1229 void LinearScan::add_register_hints(LIR_Op* op) {
1230   switch (op->code()) {
1231     case lir_move:      // fall through
1232     case lir_convert: {
1233       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1234       LIR_Op1* move = (LIR_Op1*)op;
1235 
1236       LIR_Opr move_from = move->in_opr();
1237       LIR_Opr move_to = move->result_opr();
1238 
1239       if (move_to->is_register() && move_from->is_register()) {
1240         Interval* from = interval_at(reg_num(move_from));
1241         Interval* to = interval_at(reg_num(move_to));
1242         if (from != NULL && to != NULL) {
1243           to->set_register_hint(from);
1244           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1245         }
1246       }
1247       break;
1248     }
1249     case lir_cmove: {
1250       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1251       LIR_Op2* cmove = (LIR_Op2*)op;
1252 
1253       LIR_Opr move_from = cmove->in_opr1();
1254       LIR_Opr move_to = cmove->result_opr();
1255 
1256       if (move_to->is_register() && move_from->is_register()) {
1257         Interval* from = interval_at(reg_num(move_from));
1258         Interval* to = interval_at(reg_num(move_to));
1259         if (from != NULL && to != NULL) {
1260           to->set_register_hint(from);
1261           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1262         }
1263       }
1264       break;
1265     }
1266   }
1267 }
1268 
1269 
1270 void LinearScan::build_intervals() {
1271   TIME_LINEAR_SCAN(timer_build_intervals);
1272 
1273   // initialize interval list with expected number of intervals
1274   // (32 is added to have some space for split children without having to resize the list)
1275   _intervals = IntervalList(num_virtual_regs() + 32);
1276   // initialize all slots that are used by build_intervals
1277   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1278 
1279   // create a list with all caller-save registers (cpu, fpu, xmm)
1280   // when an instruction is a call, a temp range is created for all these registers
1281   int num_caller_save_registers = 0;
1282   int caller_save_registers[LinearScan::nof_regs];
1283 
1284   int i;
1285   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1286     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1287     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1288     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1289     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1290   }
1291 
1292   // temp ranges for fpu registers are only created when the method has
1293   // virtual fpu operands. Otherwise no allocation for fpu registers is
1294   // perfomed and so the temp ranges would be useless
1295   if (has_fpu_registers()) {
1296 #ifdef X86
1297     if (UseSSE < 2) {
1298 #endif
1299       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1300         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1301         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1302         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1303         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1304       }
1305 #ifdef X86
1306     }
1307     if (UseSSE > 0) {
1308       for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
1309         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1310         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1311         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1312         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1313       }
1314     }
1315 #endif
1316   }
1317   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1318 
1319 
1320   LIR_OpVisitState visitor;
1321 
1322   // iterate all blocks in reverse order
1323   for (i = block_count() - 1; i >= 0; i--) {
1324     BlockBegin* block = block_at(i);
1325     LIR_OpList* instructions = block->lir()->instructions_list();
1326     int         block_from =   block->first_lir_instruction_id();
1327     int         block_to =     block->last_lir_instruction_id();
1328 
1329     assert(block_from == instructions->at(0)->id(), "must be");
1330     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1331 
1332     // Update intervals for registers live at the end of this block;
1333     BitMap live = block->live_out();
1334     int size = (int)live.size();
1335     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1336       assert(live.at(number), "should not stop here otherwise");
1337       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1338       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1339 
1340       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1341 
1342       // add special use positions for loop-end blocks when the
1343       // interval is used anywhere inside this loop.  It's possible
1344       // that the block was part of a non-natural loop, so it might
1345       // have an invalid loop index.
1346       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1347           block->loop_index() != -1 &&
1348           is_interval_in_loop(number, block->loop_index())) {
1349         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1350       }
1351     }
1352 
1353     // iterate all instructions of the block in reverse order.
1354     // skip the first instruction because it is always a label
1355     // definitions of intervals are processed before uses
1356     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1357     for (int j = instructions->length() - 1; j >= 1; j--) {
1358       LIR_Op* op = instructions->at(j);
1359       int op_id = op->id();
1360 
1361       // visit operation to collect all operands
1362       visitor.visit(op);
1363 
1364       // add a temp range for each register if operation destroys caller-save registers
1365       if (visitor.has_call()) {
1366         for (int k = 0; k < num_caller_save_registers; k++) {
1367           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1368         }
1369         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1370       }
1371 
1372       // Add any platform dependent temps
1373       pd_add_temps(op);
1374 
1375       // visit definitions (output and temp operands)
1376       int k, n;
1377       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1378       for (k = 0; k < n; k++) {
1379         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1380         assert(opr->is_register(), "visitor should only return register operands");
1381         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1382       }
1383 
1384       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1385       for (k = 0; k < n; k++) {
1386         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1387         assert(opr->is_register(), "visitor should only return register operands");
1388         add_temp(opr, op_id, mustHaveRegister);
1389       }
1390 
1391       // visit uses (input operands)
1392       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1393       for (k = 0; k < n; k++) {
1394         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1395         assert(opr->is_register(), "visitor should only return register operands");
1396         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1397       }
1398 
1399       // Add uses of live locals from interpreter's point of view for proper
1400       // debug information generation
1401       // Treat these operands as temp values (if the life range is extended
1402       // to a call site, the value would be in a register at the call otherwise)
1403       n = visitor.info_count();
1404       for (k = 0; k < n; k++) {
1405         CodeEmitInfo* info = visitor.info_at(k);
1406         ValueStack* stack = info->stack();
1407         for_each_state_value(stack, value,
1408           add_use(value, block_from, op_id + 1, noUse);
1409         );
1410       }
1411 
1412       // special steps for some instructions (especially moves)
1413       handle_method_arguments(op);
1414       handle_doubleword_moves(op);
1415       add_register_hints(op);
1416 
1417     } // end of instruction iteration
1418   } // end of block iteration
1419 
1420 
1421   // add the range [0, 1[ to all fixed intervals
1422   // -> the register allocator need not handle unhandled fixed intervals
1423   for (int n = 0; n < LinearScan::nof_regs; n++) {
1424     Interval* interval = interval_at(n);
1425     if (interval != NULL) {
1426       interval->add_range(0, 1);
1427     }
1428   }
1429 }
1430 
1431 
1432 // ********** Phase 5: actual register allocation
1433 
1434 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1435   if (*a != NULL) {
1436     if (*b != NULL) {
1437       return (*a)->from() - (*b)->from();
1438     } else {
1439       return -1;
1440     }
1441   } else {
1442     if (*b != NULL) {
1443       return 1;
1444     } else {
1445       return 0;
1446     }
1447   }
1448 }
1449 
1450 #ifndef PRODUCT
1451 bool LinearScan::is_sorted(IntervalArray* intervals) {
1452   int from = -1;
1453   int i, j;
1454   for (i = 0; i < intervals->length(); i ++) {
1455     Interval* it = intervals->at(i);
1456     if (it != NULL) {
1457       if (from > it->from()) {
1458         assert(false, "");
1459         return false;
1460       }
1461       from = it->from();
1462     }
1463   }
1464 
1465   // check in both directions if sorted list and unsorted list contain same intervals
1466   for (i = 0; i < interval_count(); i++) {
1467     if (interval_at(i) != NULL) {
1468       int num_found = 0;
1469       for (j = 0; j < intervals->length(); j++) {
1470         if (interval_at(i) == intervals->at(j)) {
1471           num_found++;
1472         }
1473       }
1474       assert(num_found == 1, "lists do not contain same intervals");
1475     }
1476   }
1477   for (j = 0; j < intervals->length(); j++) {
1478     int num_found = 0;
1479     for (i = 0; i < interval_count(); i++) {
1480       if (interval_at(i) == intervals->at(j)) {
1481         num_found++;
1482       }
1483     }
1484     assert(num_found == 1, "lists do not contain same intervals");
1485   }
1486 
1487   return true;
1488 }
1489 #endif
1490 
1491 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1492   if (*prev != NULL) {
1493     (*prev)->set_next(interval);
1494   } else {
1495     *first = interval;
1496   }
1497   *prev = interval;
1498 }
1499 
1500 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1501   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1502 
1503   *list1 = *list2 = Interval::end();
1504 
1505   Interval* list1_prev = NULL;
1506   Interval* list2_prev = NULL;
1507   Interval* v;
1508 
1509   const int n = _sorted_intervals->length();
1510   for (int i = 0; i < n; i++) {
1511     v = _sorted_intervals->at(i);
1512     if (v == NULL) continue;
1513 
1514     if (is_list1(v)) {
1515       add_to_list(list1, &list1_prev, v);
1516     } else if (is_list2 == NULL || is_list2(v)) {
1517       add_to_list(list2, &list2_prev, v);
1518     }
1519   }
1520 
1521   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1522   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1523 
1524   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1525   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1526 }
1527 
1528 
1529 void LinearScan::sort_intervals_before_allocation() {
1530   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1531 
1532   if (_needs_full_resort) {
1533     // There is no known reason why this should occur but just in case...
1534     assert(false, "should never occur");
1535     // Re-sort existing interval list because an Interval::from() has changed
1536     _sorted_intervals->sort(interval_cmp);
1537     _needs_full_resort = false;
1538   }
1539 
1540   IntervalList* unsorted_list = &_intervals;
1541   int unsorted_len = unsorted_list->length();
1542   int sorted_len = 0;
1543   int unsorted_idx;
1544   int sorted_idx = 0;
1545   int sorted_from_max = -1;
1546 
1547   // calc number of items for sorted list (sorted list must not contain NULL values)
1548   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1549     if (unsorted_list->at(unsorted_idx) != NULL) {
1550       sorted_len++;
1551     }
1552   }
1553   IntervalArray* sorted_list = new IntervalArray(sorted_len);
1554 
1555   // special sorting algorithm: the original interval-list is almost sorted,
1556   // only some intervals are swapped. So this is much faster than a complete QuickSort
1557   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1558     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1559 
1560     if (cur_interval != NULL) {
1561       int cur_from = cur_interval->from();
1562 
1563       if (sorted_from_max <= cur_from) {
1564         sorted_list->at_put(sorted_idx++, cur_interval);
1565         sorted_from_max = cur_interval->from();
1566       } else {
1567         // the asumption that the intervals are already sorted failed,
1568         // so this interval must be sorted in manually
1569         int j;
1570         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1571           sorted_list->at_put(j + 1, sorted_list->at(j));
1572         }
1573         sorted_list->at_put(j + 1, cur_interval);
1574         sorted_idx++;
1575       }
1576     }
1577   }
1578   _sorted_intervals = sorted_list;
1579   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1580 }
1581 
1582 void LinearScan::sort_intervals_after_allocation() {
1583   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1584 
1585   if (_needs_full_resort) {
1586     // Re-sort existing interval list because an Interval::from() has changed
1587     _sorted_intervals->sort(interval_cmp);
1588     _needs_full_resort = false;
1589   }
1590 
1591   IntervalArray* old_list      = _sorted_intervals;
1592   IntervalList*  new_list      = _new_intervals_from_allocation;
1593   int old_len = old_list->length();
1594   int new_len = new_list->length();
1595 
1596   if (new_len == 0) {
1597     // no intervals have been added during allocation, so sorted list is already up to date
1598     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1599     return;
1600   }
1601 
1602   // conventional sort-algorithm for new intervals
1603   new_list->sort(interval_cmp);
1604 
1605   // merge old and new list (both already sorted) into one combined list
1606   IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1607   int old_idx = 0;
1608   int new_idx = 0;
1609 
1610   while (old_idx + new_idx < old_len + new_len) {
1611     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1612       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1613       old_idx++;
1614     } else {
1615       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1616       new_idx++;
1617     }
1618   }
1619 
1620   _sorted_intervals = combined_list;
1621   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1622 }
1623 
1624 
1625 void LinearScan::allocate_registers() {
1626   TIME_LINEAR_SCAN(timer_allocate_registers);
1627 
1628   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1629   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1630 
1631   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
1632   if (has_fpu_registers()) {
1633     create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1634 #ifdef ASSERT
1635   } else {
1636     // fpu register allocation is omitted because no virtual fpu registers are present
1637     // just check this again...
1638     create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1639     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1640 #endif
1641   }
1642 
1643   // allocate cpu registers
1644   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1645   cpu_lsw.walk();
1646   cpu_lsw.finish_allocation();
1647 
1648   if (has_fpu_registers()) {
1649     // allocate fpu registers
1650     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1651     fpu_lsw.walk();
1652     fpu_lsw.finish_allocation();
1653   }
1654 }
1655 
1656 
1657 // ********** Phase 6: resolve data flow
1658 // (insert moves at edges between blocks if intervals have been split)
1659 
1660 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1661 // instead of returning NULL
1662 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1663   Interval* result = interval->split_child_at_op_id(op_id, mode);
1664   if (result != NULL) {
1665     return result;
1666   }
1667 
1668   assert(false, "must find an interval, but do a clean bailout in product mode");
1669   result = new Interval(LIR_OprDesc::vreg_base);
1670   result->assign_reg(0);
1671   result->set_type(T_INT);
1672   BAILOUT_("LinearScan: interval is NULL", result);
1673 }
1674 
1675 
1676 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1677   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1678   assert(interval_at(reg_num) != NULL, "no interval found");
1679 
1680   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1681 }
1682 
1683 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1684   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1685   assert(interval_at(reg_num) != NULL, "no interval found");
1686 
1687   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1688 }
1689 
1690 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1691   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1692   assert(interval_at(reg_num) != NULL, "no interval found");
1693 
1694   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1695 }
1696 
1697 
1698 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1699   DEBUG_ONLY(move_resolver.check_empty());
1700 
1701   const int num_regs = num_virtual_regs();
1702   const int size = live_set_size();
1703   const BitMap live_at_edge = to_block->live_in();
1704 
1705   // visit all registers where the live_at_edge bit is set
1706   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1707     assert(r < num_regs, "live information set for not exisiting interval");
1708     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1709 
1710     Interval* from_interval = interval_at_block_end(from_block, r);
1711     Interval* to_interval = interval_at_block_begin(to_block, r);
1712 
1713     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1714       // need to insert move instruction
1715       move_resolver.add_mapping(from_interval, to_interval);
1716     }
1717   }
1718 }
1719 
1720 
1721 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1722   if (from_block->number_of_sux() <= 1) {
1723     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1724 
1725     LIR_OpList* instructions = from_block->lir()->instructions_list();
1726     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1727     if (branch != NULL) {
1728       // insert moves before branch
1729       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1730       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1731     } else {
1732       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1733     }
1734 
1735   } else {
1736     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1737 #ifdef ASSERT
1738     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1739 
1740     // because the number of predecessor edges matches the number of
1741     // successor edges, blocks which are reached by switch statements
1742     // may have be more than one predecessor but it will be guaranteed
1743     // that all predecessors will be the same.
1744     for (int i = 0; i < to_block->number_of_preds(); i++) {
1745       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1746     }
1747 #endif
1748 
1749     move_resolver.set_insert_position(to_block->lir(), 0);
1750   }
1751 }
1752 
1753 
1754 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1755 void LinearScan::resolve_data_flow() {
1756   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1757 
1758   int num_blocks = block_count();
1759   MoveResolver move_resolver(this);
1760   BitMap block_completed(num_blocks);  block_completed.clear();
1761   BitMap already_resolved(num_blocks); already_resolved.clear();
1762 
1763   int i;
1764   for (i = 0; i < num_blocks; i++) {
1765     BlockBegin* block = block_at(i);
1766 
1767     // check if block has only one predecessor and only one successor
1768     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1769       LIR_OpList* instructions = block->lir()->instructions_list();
1770       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1771       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1772       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1773 
1774       // check if block is empty (only label and branch)
1775       if (instructions->length() == 2) {
1776         BlockBegin* pred = block->pred_at(0);
1777         BlockBegin* sux = block->sux_at(0);
1778 
1779         // prevent optimization of two consecutive blocks
1780         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1781           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1782           block_completed.set_bit(block->linear_scan_number());
1783 
1784           // directly resolve between pred and sux (without looking at the empty block between)
1785           resolve_collect_mappings(pred, sux, move_resolver);
1786           if (move_resolver.has_mappings()) {
1787             move_resolver.set_insert_position(block->lir(), 0);
1788             move_resolver.resolve_and_append_moves();
1789           }
1790         }
1791       }
1792     }
1793   }
1794 
1795 
1796   for (i = 0; i < num_blocks; i++) {
1797     if (!block_completed.at(i)) {
1798       BlockBegin* from_block = block_at(i);
1799       already_resolved.set_from(block_completed);
1800 
1801       int num_sux = from_block->number_of_sux();
1802       for (int s = 0; s < num_sux; s++) {
1803         BlockBegin* to_block = from_block->sux_at(s);
1804 
1805         // check for duplicate edges between the same blocks (can happen with switch blocks)
1806         if (!already_resolved.at(to_block->linear_scan_number())) {
1807           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1808           already_resolved.set_bit(to_block->linear_scan_number());
1809 
1810           // collect all intervals that have been split between from_block and to_block
1811           resolve_collect_mappings(from_block, to_block, move_resolver);
1812           if (move_resolver.has_mappings()) {
1813             resolve_find_insert_pos(from_block, to_block, move_resolver);
1814             move_resolver.resolve_and_append_moves();
1815           }
1816         }
1817       }
1818     }
1819   }
1820 }
1821 
1822 
1823 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1824   if (interval_at(reg_num) == NULL) {
1825     // if a phi function is never used, no interval is created -> ignore this
1826     return;
1827   }
1828 
1829   Interval* interval = interval_at_block_begin(block, reg_num);
1830   int reg = interval->assigned_reg();
1831   int regHi = interval->assigned_regHi();
1832 
1833   if ((reg < nof_regs && interval->always_in_memory()) ||
1834       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1835     // the interval is split to get a short range that is located on the stack
1836     // in the following two cases:
1837     // * the interval started in memory (e.g. method parameter), but is currently in a register
1838     //   this is an optimization for exception handling that reduces the number of moves that
1839     //   are necessary for resolving the states when an exception uses this exception handler
1840     // * the interval would be on the fpu stack at the begin of the exception handler
1841     //   this is not allowed because of the complicated fpu stack handling on Intel
1842 
1843     // range that will be spilled to memory
1844     int from_op_id = block->first_lir_instruction_id();
1845     int to_op_id = from_op_id + 1;  // short live range of length 1
1846     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1847            "no split allowed between exception entry and first instruction");
1848 
1849     if (interval->from() != from_op_id) {
1850       // the part before from_op_id is unchanged
1851       interval = interval->split(from_op_id);
1852       interval->assign_reg(reg, regHi);
1853       append_interval(interval);
1854     } else {
1855       _needs_full_resort = true;
1856     }
1857     assert(interval->from() == from_op_id, "must be true now");
1858 
1859     Interval* spilled_part = interval;
1860     if (interval->to() != to_op_id) {
1861       // the part after to_op_id is unchanged
1862       spilled_part = interval->split_from_start(to_op_id);
1863       append_interval(spilled_part);
1864       move_resolver.add_mapping(spilled_part, interval);
1865     }
1866     assign_spill_slot(spilled_part);
1867 
1868     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1869   }
1870 }
1871 
1872 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1873   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1874   DEBUG_ONLY(move_resolver.check_empty());
1875 
1876   // visit all registers where the live_in bit is set
1877   int size = live_set_size();
1878   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1879     resolve_exception_entry(block, r, move_resolver);
1880   }
1881 
1882   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1883   for_each_phi_fun(block, phi,
1884     resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1885   );
1886 
1887   if (move_resolver.has_mappings()) {
1888     // insert moves after first instruction
1889     move_resolver.set_insert_position(block->lir(), 0);
1890     move_resolver.resolve_and_append_moves();
1891   }
1892 }
1893 
1894 
1895 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1896   if (interval_at(reg_num) == NULL) {
1897     // if a phi function is never used, no interval is created -> ignore this
1898     return;
1899   }
1900 
1901   // the computation of to_interval is equal to resolve_collect_mappings,
1902   // but from_interval is more complicated because of phi functions
1903   BlockBegin* to_block = handler->entry_block();
1904   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1905 
1906   if (phi != NULL) {
1907     // phi function of the exception entry block
1908     // no moves are created for this phi function in the LIR_Generator, so the
1909     // interval at the throwing instruction must be searched using the operands
1910     // of the phi function
1911     Value from_value = phi->operand_at(handler->phi_operand());
1912 
1913     // with phi functions it can happen that the same from_value is used in
1914     // multiple mappings, so notify move-resolver that this is allowed
1915     move_resolver.set_multiple_reads_allowed();
1916 
1917     Constant* con = from_value->as_Constant();
1918     if (con != NULL && !con->is_pinned()) {
1919       // unpinned constants may have no register, so add mapping from constant to interval
1920       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1921     } else {
1922       // search split child at the throwing op_id
1923       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1924       move_resolver.add_mapping(from_interval, to_interval);
1925     }
1926 
1927   } else {
1928     // no phi function, so use reg_num also for from_interval
1929     // search split child at the throwing op_id
1930     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1931     if (from_interval != to_interval) {
1932       // optimization to reduce number of moves: when to_interval is on stack and
1933       // the stack slot is known to be always correct, then no move is necessary
1934       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1935         move_resolver.add_mapping(from_interval, to_interval);
1936       }
1937     }
1938   }
1939 }
1940 
1941 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1942   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1943 
1944   DEBUG_ONLY(move_resolver.check_empty());
1945   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1946   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1947   assert(handler->entry_code() == NULL, "code already present");
1948 
1949   // visit all registers where the live_in bit is set
1950   BlockBegin* block = handler->entry_block();
1951   int size = live_set_size();
1952   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1953     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1954   }
1955 
1956   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1957   for_each_phi_fun(block, phi,
1958     resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1959   );
1960 
1961   if (move_resolver.has_mappings()) {
1962     LIR_List* entry_code = new LIR_List(compilation());
1963     move_resolver.set_insert_position(entry_code, 0);
1964     move_resolver.resolve_and_append_moves();
1965 
1966     entry_code->jump(handler->entry_block());
1967     handler->set_entry_code(entry_code);
1968   }
1969 }
1970 
1971 
1972 void LinearScan::resolve_exception_handlers() {
1973   MoveResolver move_resolver(this);
1974   LIR_OpVisitState visitor;
1975   int num_blocks = block_count();
1976 
1977   int i;
1978   for (i = 0; i < num_blocks; i++) {
1979     BlockBegin* block = block_at(i);
1980     if (block->is_set(BlockBegin::exception_entry_flag)) {
1981       resolve_exception_entry(block, move_resolver);
1982     }
1983   }
1984 
1985   for (i = 0; i < num_blocks; i++) {
1986     BlockBegin* block = block_at(i);
1987     LIR_List* ops = block->lir();
1988     int num_ops = ops->length();
1989 
1990     // iterate all instructions of the block. skip the first because it is always a label
1991     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1992     for (int j = 1; j < num_ops; j++) {
1993       LIR_Op* op = ops->at(j);
1994       int op_id = op->id();
1995 
1996       if (op_id != -1 && has_info(op_id)) {
1997         // visit operation to collect all operands
1998         visitor.visit(op);
1999         assert(visitor.info_count() > 0, "should not visit otherwise");
2000 
2001         XHandlers* xhandlers = visitor.all_xhandler();
2002         int n = xhandlers->length();
2003         for (int k = 0; k < n; k++) {
2004           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2005         }
2006 
2007 #ifdef ASSERT
2008       } else {
2009         visitor.visit(op);
2010         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2011 #endif
2012       }
2013     }
2014   }
2015 }
2016 
2017 
2018 // ********** Phase 7: assign register numbers back to LIR
2019 // (includes computation of debug information and oop maps)
2020 
2021 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2022   VMReg reg = interval->cached_vm_reg();
2023   if (!reg->is_valid() ) {
2024     reg = vm_reg_for_operand(operand_for_interval(interval));
2025     interval->set_cached_vm_reg(reg);
2026   }
2027   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2028   return reg;
2029 }
2030 
2031 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2032   assert(opr->is_oop(), "currently only implemented for oop operands");
2033   return frame_map()->regname(opr);
2034 }
2035 
2036 
2037 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2038   LIR_Opr opr = interval->cached_opr();
2039   if (opr->is_illegal()) {
2040     opr = calc_operand_for_interval(interval);
2041     interval->set_cached_opr(opr);
2042   }
2043 
2044   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2045   return opr;
2046 }
2047 
2048 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2049   int assigned_reg = interval->assigned_reg();
2050   BasicType type = interval->type();
2051 
2052   if (assigned_reg >= nof_regs) {
2053     // stack slot
2054     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2055     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2056 
2057   } else {
2058     // register
2059     switch (type) {
2060       case T_OBJECT: {
2061         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2062         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2063         return LIR_OprFact::single_cpu_oop(assigned_reg);
2064       }
2065 
2066       case T_ADDRESS: {
2067         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2068         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2069         return LIR_OprFact::single_cpu_address(assigned_reg);
2070       }
2071 
2072       case T_METADATA: {
2073         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2074         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2075         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2076       }
2077 
2078 #ifdef __SOFTFP__
2079       case T_FLOAT:  // fall through
2080 #endif // __SOFTFP__
2081       case T_INT: {
2082         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2083         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2084         return LIR_OprFact::single_cpu(assigned_reg);
2085       }
2086 
2087 #ifdef __SOFTFP__
2088       case T_DOUBLE:  // fall through
2089 #endif // __SOFTFP__
2090       case T_LONG: {
2091         int assigned_regHi = interval->assigned_regHi();
2092         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2093         assert(num_physical_regs(T_LONG) == 1 ||
2094                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2095 
2096         assert(assigned_reg != assigned_regHi, "invalid allocation");
2097         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2098                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2099         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2100         if (requires_adjacent_regs(T_LONG)) {
2101           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2102         }
2103 
2104 #ifdef _LP64
2105         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2106 #else
2107 #if defined(SPARC) || defined(PPC)
2108         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2109 #else
2110         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2111 #endif // SPARC
2112 #endif // LP64
2113       }
2114 
2115 #ifndef __SOFTFP__
2116       case T_FLOAT: {
2117 #ifdef X86
2118         if (UseSSE >= 1) {
2119           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2120           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2121           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2122         }
2123 #endif
2124 
2125         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2126         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2127         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2128       }
2129 
2130       case T_DOUBLE: {
2131 #ifdef X86
2132         if (UseSSE >= 2) {
2133           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2134           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2135           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2136         }
2137 #endif
2138 
2139 #ifdef SPARC
2140         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2144 #elif defined(ARM)
2145         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2147         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2148         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2149 #else
2150         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2151         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2152         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2153 #endif
2154         return result;
2155       }
2156 #endif // __SOFTFP__
2157 
2158       default: {
2159         ShouldNotReachHere();
2160         return LIR_OprFact::illegalOpr;
2161       }
2162     }
2163   }
2164 }
2165 
2166 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2167   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2168   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2169 }
2170 
2171 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2172   assert(opr->is_virtual(), "should not call this otherwise");
2173 
2174   Interval* interval = interval_at(opr->vreg_number());
2175   assert(interval != NULL, "interval must exist");
2176 
2177   if (op_id != -1) {
2178 #ifdef ASSERT
2179     BlockBegin* block = block_of_op_with_id(op_id);
2180     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2181       // check if spill moves could have been appended at the end of this block, but
2182       // before the branch instruction. So the split child information for this branch would
2183       // be incorrect.
2184       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2185       if (branch != NULL) {
2186         if (block->live_out().at(opr->vreg_number())) {
2187           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2188           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2189         }
2190       }
2191     }
2192 #endif
2193 
2194     // operands are not changed when an interval is split during allocation,
2195     // so search the right interval here
2196     interval = split_child_at_op_id(interval, op_id, mode);
2197   }
2198 
2199   LIR_Opr res = operand_for_interval(interval);
2200 
2201 #ifdef X86
2202   // new semantic for is_last_use: not only set on definite end of interval,
2203   // but also before hole
2204   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2205   // last use information is completely correct
2206   // information is only needed for fpu stack allocation
2207   if (res->is_fpu_register()) {
2208     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2209       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2210       res = res->make_last_use();
2211     }
2212   }
2213 #endif
2214 
2215   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2216 
2217   return res;
2218 }
2219 
2220 
2221 #ifdef ASSERT
2222 // some methods used to check correctness of debug information
2223 
2224 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2225   if (values == NULL) {
2226     return;
2227   }
2228 
2229   for (int i = 0; i < values->length(); i++) {
2230     ScopeValue* value = values->at(i);
2231 
2232     if (value->is_location()) {
2233       Location location = ((LocationValue*)value)->location();
2234       assert(location.where() == Location::on_stack, "value is in register");
2235     }
2236   }
2237 }
2238 
2239 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2240   if (values == NULL) {
2241     return;
2242   }
2243 
2244   for (int i = 0; i < values->length(); i++) {
2245     MonitorValue* value = values->at(i);
2246 
2247     if (value->owner()->is_location()) {
2248       Location location = ((LocationValue*)value->owner())->location();
2249       assert(location.where() == Location::on_stack, "owner is in register");
2250     }
2251     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2252   }
2253 }
2254 
2255 void assert_equal(Location l1, Location l2) {
2256   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2257 }
2258 
2259 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2260   if (v1->is_location()) {
2261     assert(v2->is_location(), "");
2262     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2263   } else if (v1->is_constant_int()) {
2264     assert(v2->is_constant_int(), "");
2265     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2266   } else if (v1->is_constant_double()) {
2267     assert(v2->is_constant_double(), "");
2268     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2269   } else if (v1->is_constant_long()) {
2270     assert(v2->is_constant_long(), "");
2271     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2272   } else if (v1->is_constant_oop()) {
2273     assert(v2->is_constant_oop(), "");
2274     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2275   } else {
2276     ShouldNotReachHere();
2277   }
2278 }
2279 
2280 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2281   assert_equal(m1->owner(), m2->owner());
2282   assert_equal(m1->basic_lock(), m2->basic_lock());
2283 }
2284 
2285 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2286   assert(d1->scope() == d2->scope(), "not equal");
2287   assert(d1->bci() == d2->bci(), "not equal");
2288 
2289   if (d1->locals() != NULL) {
2290     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2291     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2292     for (int i = 0; i < d1->locals()->length(); i++) {
2293       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2294     }
2295   } else {
2296     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2297   }
2298 
2299   if (d1->expressions() != NULL) {
2300     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2301     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2302     for (int i = 0; i < d1->expressions()->length(); i++) {
2303       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2304     }
2305   } else {
2306     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2307   }
2308 
2309   if (d1->monitors() != NULL) {
2310     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2311     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2312     for (int i = 0; i < d1->monitors()->length(); i++) {
2313       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2314     }
2315   } else {
2316     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2317   }
2318 
2319   if (d1->caller() != NULL) {
2320     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2321     assert_equal(d1->caller(), d2->caller());
2322   } else {
2323     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2324   }
2325 }
2326 
2327 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2328   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2329     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2330     switch (code) {
2331       case Bytecodes::_ifnull    : // fall through
2332       case Bytecodes::_ifnonnull : // fall through
2333       case Bytecodes::_ifeq      : // fall through
2334       case Bytecodes::_ifne      : // fall through
2335       case Bytecodes::_iflt      : // fall through
2336       case Bytecodes::_ifge      : // fall through
2337       case Bytecodes::_ifgt      : // fall through
2338       case Bytecodes::_ifle      : // fall through
2339       case Bytecodes::_if_icmpeq : // fall through
2340       case Bytecodes::_if_icmpne : // fall through
2341       case Bytecodes::_if_icmplt : // fall through
2342       case Bytecodes::_if_icmpge : // fall through
2343       case Bytecodes::_if_icmpgt : // fall through
2344       case Bytecodes::_if_icmple : // fall through
2345       case Bytecodes::_if_acmpeq : // fall through
2346       case Bytecodes::_if_acmpne :
2347         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2348         break;
2349     }
2350   }
2351 }
2352 
2353 #endif // ASSERT
2354 
2355 
2356 IntervalWalker* LinearScan::init_compute_oop_maps() {
2357   // setup lists of potential oops for walking
2358   Interval* oop_intervals;
2359   Interval* non_oop_intervals;
2360 
2361   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2362 
2363   // intervals that have no oops inside need not to be processed
2364   // to ensure a walking until the last instruction id, add a dummy interval
2365   // with a high operation id
2366   non_oop_intervals = new Interval(any_reg);
2367   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2368 
2369   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2370 }
2371 
2372 
2373 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2374   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2375 
2376   // walk before the current operation -> intervals that start at
2377   // the operation (= output operands of the operation) are not
2378   // included in the oop map
2379   iw->walk_before(op->id());
2380 
2381   int frame_size = frame_map()->framesize();
2382   int arg_count = frame_map()->oop_map_arg_count();
2383   OopMap* map = new OopMap(frame_size, arg_count);
2384 
2385   // Check if this is a patch site.
2386   bool is_patch_info = false;
2387   if (op->code() == lir_move) {
2388     assert(!is_call_site, "move must not be a call site");
2389     assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2390     LIR_Op1* move = (LIR_Op1*)op;
2391 
2392     is_patch_info = move->patch_code() != lir_patch_none;
2393   }
2394 
2395   // Iterate through active intervals
2396   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2397     int assigned_reg = interval->assigned_reg();
2398 
2399     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2400     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2401     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2402 
2403     // Check if this range covers the instruction. Intervals that
2404     // start or end at the current operation are not included in the
2405     // oop map, except in the case of patching moves.  For patching
2406     // moves, any intervals which end at this instruction are included
2407     // in the oop map since we may safepoint while doing the patch
2408     // before we've consumed the inputs.
2409     if (is_patch_info || op->id() < interval->current_to()) {
2410 
2411       // caller-save registers must not be included into oop-maps at calls
2412       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2413 
2414       VMReg name = vm_reg_for_interval(interval);
2415       set_oop(map, name);
2416 
2417       // Spill optimization: when the stack value is guaranteed to be always correct,
2418       // then it must be added to the oop map even if the interval is currently in a register
2419       if (interval->always_in_memory() &&
2420           op->id() > interval->spill_definition_pos() &&
2421           interval->assigned_reg() != interval->canonical_spill_slot()) {
2422         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2423         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2424         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2425 
2426         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2427       }
2428     }
2429   }
2430 
2431   // add oops from lock stack
2432   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2433   int locks_count = info->stack()->total_locks_size();
2434   for (int i = 0; i < locks_count; i++) {
2435     set_oop(map, frame_map()->monitor_object_regname(i));
2436   }
2437 
2438   return map;
2439 }
2440 
2441 
2442 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2443   assert(visitor.info_count() > 0, "no oop map needed");
2444 
2445   // compute oop_map only for first CodeEmitInfo
2446   // because it is (in most cases) equal for all other infos of the same operation
2447   CodeEmitInfo* first_info = visitor.info_at(0);
2448   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2449 
2450   for (int i = 0; i < visitor.info_count(); i++) {
2451     CodeEmitInfo* info = visitor.info_at(i);
2452     OopMap* oop_map = first_oop_map;
2453 
2454     // compute worst case interpreter size in case of a deoptimization
2455     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2456 
2457     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2458       // this info has a different number of locks then the precomputed oop map
2459       // (possible for lock and unlock instructions) -> compute oop map with
2460       // correct lock information
2461       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2462     }
2463 
2464     if (info->_oop_map == NULL) {
2465       info->_oop_map = oop_map;
2466     } else {
2467       // a CodeEmitInfo can not be shared between different LIR-instructions
2468       // because interval splitting can occur anywhere between two instructions
2469       // and so the oop maps must be different
2470       // -> check if the already set oop_map is exactly the one calculated for this operation
2471       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2472     }
2473   }
2474 }
2475 
2476 
2477 // frequently used constants
2478 // Allocate them with new so they are never destroyed (otherwise, a
2479 // forced exit could destroy these objects while they are still in
2480 // use).
2481 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2482 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2483 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
2484 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2485 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2486 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2487 
2488 void LinearScan::init_compute_debug_info() {
2489   // cache for frequently used scope values
2490   // (cpu registers and stack slots)
2491   _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2492 }
2493 
2494 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2495   Location loc;
2496   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2497     bailout("too large frame");
2498   }
2499   ScopeValue* object_scope_value = new LocationValue(loc);
2500 
2501   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2502     bailout("too large frame");
2503   }
2504   return new MonitorValue(object_scope_value, loc);
2505 }
2506 
2507 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2508   Location loc;
2509   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2510     bailout("too large frame");
2511   }
2512   return new LocationValue(loc);
2513 }
2514 
2515 
2516 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2517   assert(opr->is_constant(), "should not be called otherwise");
2518 
2519   LIR_Const* c = opr->as_constant_ptr();
2520   BasicType t = c->type();
2521   switch (t) {
2522     case T_OBJECT: {
2523       jobject value = c->as_jobject();
2524       if (value == NULL) {
2525         scope_values->append(_oop_null_scope_value);
2526       } else {
2527         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2528       }
2529       return 1;
2530     }
2531 
2532     case T_INT: // fall through
2533     case T_FLOAT: {
2534       int value = c->as_jint_bits();
2535       switch (value) {
2536         case -1: scope_values->append(_int_m1_scope_value); break;
2537         case 0:  scope_values->append(_int_0_scope_value); break;
2538         case 1:  scope_values->append(_int_1_scope_value); break;
2539         case 2:  scope_values->append(_int_2_scope_value); break;
2540         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2541       }
2542       return 1;
2543     }
2544 
2545     case T_LONG: // fall through
2546     case T_DOUBLE: {
2547 #ifdef _LP64
2548       scope_values->append(_int_0_scope_value);
2549       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2550 #else
2551       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2552         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2553         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2554       } else {
2555         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2556         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2557       }
2558 #endif
2559       return 2;
2560     }
2561 
2562     case T_ADDRESS: {
2563 #ifdef _LP64
2564       scope_values->append(new ConstantLongValue(c->as_jint()));
2565 #else
2566       scope_values->append(new ConstantIntValue(c->as_jint()));
2567 #endif
2568       return 1;
2569     }
2570 
2571     default:
2572       ShouldNotReachHere();
2573       return -1;
2574   }
2575 }
2576 
2577 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2578   if (opr->is_single_stack()) {
2579     int stack_idx = opr->single_stack_ix();
2580     bool is_oop = opr->is_oop_register();
2581     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2582 
2583     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2584     if (sv == NULL) {
2585       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2586       sv = location_for_name(stack_idx, loc_type);
2587       _scope_value_cache.at_put(cache_idx, sv);
2588     }
2589 
2590     // check if cached value is correct
2591     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2592 
2593     scope_values->append(sv);
2594     return 1;
2595 
2596   } else if (opr->is_single_cpu()) {
2597     bool is_oop = opr->is_oop_register();
2598     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2599     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2600 
2601     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2602     if (sv == NULL) {
2603       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2604       VMReg rname = frame_map()->regname(opr);
2605       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2606       _scope_value_cache.at_put(cache_idx, sv);
2607     }
2608 
2609     // check if cached value is correct
2610     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2611 
2612     scope_values->append(sv);
2613     return 1;
2614 
2615 #ifdef X86
2616   } else if (opr->is_single_xmm()) {
2617     VMReg rname = opr->as_xmm_float_reg().as_VMReg();
2618     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2619 
2620     scope_values->append(sv);
2621     return 1;
2622 #endif
2623 
2624   } else if (opr->is_single_fpu()) {
2625 #ifdef X86
2626     // the exact location of fpu stack values is only known
2627     // during fpu stack allocation, so the stack allocator object
2628     // must be present
2629     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2630     assert(_fpu_stack_allocator != NULL, "must be present");
2631     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2632 #endif
2633 
2634     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2635     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2636 #ifndef __SOFTFP__
2637 #ifndef VM_LITTLE_ENDIAN
2638     if (! float_saved_as_double) {
2639       // On big endian system, we may have an issue if float registers use only
2640       // the low half of the (same) double registers.
2641       // Both the float and the double could have the same regnr but would correspond
2642       // to two different addresses once saved.
2643 
2644       // get next safely (no assertion checks)
2645       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2646       if (next->is_reg() &&
2647           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2648         // the back-end does use the same numbering for the double and the float
2649         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2650       }
2651     }
2652 #endif
2653 #endif
2654     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2655 
2656     scope_values->append(sv);
2657     return 1;
2658 
2659   } else {
2660     // double-size operands
2661 
2662     ScopeValue* first;
2663     ScopeValue* second;
2664 
2665     if (opr->is_double_stack()) {
2666 #ifdef _LP64
2667       Location loc1;
2668       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2669       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2670         bailout("too large frame");
2671       }
2672       // Does this reverse on x86 vs. sparc?
2673       first =  new LocationValue(loc1);
2674       second = _int_0_scope_value;
2675 #else
2676       Location loc1, loc2;
2677       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2678         bailout("too large frame");
2679       }
2680       first =  new LocationValue(loc1);
2681       second = new LocationValue(loc2);
2682 #endif // _LP64
2683 
2684     } else if (opr->is_double_cpu()) {
2685 #ifdef _LP64
2686       VMReg rname_first = opr->as_register_lo().as_VMReg();
2687       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2688       second = _int_0_scope_value;
2689 #else
2690       VMReg rname_first = opr->as_register_lo().as_VMReg();
2691       VMReg rname_second = opr->as_register_hi().as_VMReg();
2692 
2693       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2694         // lo/hi and swapped relative to first and second, so swap them
2695         VMReg tmp = rname_first;
2696         rname_first = rname_second;
2697         rname_second = tmp;
2698       }
2699 
2700       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2701       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2702 #endif //_LP64
2703 
2704 
2705 #ifdef X86
2706     } else if (opr->is_double_xmm()) {
2707       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2708       VMReg rname_first  = opr->as_xmm_double_reg().as_VMReg();
2709 #  ifdef _LP64
2710       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2711       second = _int_0_scope_value;
2712 #  else
2713       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2714       // %%% This is probably a waste but we'll keep things as they were for now
2715       if (true) {
2716         VMReg rname_second = rname_first->next();
2717         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2718       }
2719 #  endif
2720 #endif
2721 
2722     } else if (opr->is_double_fpu()) {
2723       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2724       // the double as float registers in the native ordering. On X86,
2725       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2726       // the low-order word of the double and fpu_regnrLo + 1 is the
2727       // name for the other half.  *first and *second must represent the
2728       // least and most significant words, respectively.
2729 
2730 #ifdef X86
2731       // the exact location of fpu stack values is only known
2732       // during fpu stack allocation, so the stack allocator object
2733       // must be present
2734       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2735       assert(_fpu_stack_allocator != NULL, "must be present");
2736       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2737 
2738       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2739 #endif
2740 #ifdef SPARC
2741       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2742 #endif
2743 #ifdef ARM
2744       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2745 #endif
2746 #ifdef PPC
2747       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2748 #endif
2749 
2750 #ifdef VM_LITTLE_ENDIAN
2751       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2752 #else
2753       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2754 #endif
2755 
2756 #ifdef _LP64
2757       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2758       second = _int_0_scope_value;
2759 #else
2760       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2761       // %%% This is probably a waste but we'll keep things as they were for now
2762       if (true) {
2763         VMReg rname_second = rname_first->next();
2764         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2765       }
2766 #endif
2767 
2768     } else {
2769       ShouldNotReachHere();
2770       first = NULL;
2771       second = NULL;
2772     }
2773 
2774     assert(first != NULL && second != NULL, "must be set");
2775     // The convention the interpreter uses is that the second local
2776     // holds the first raw word of the native double representation.
2777     // This is actually reasonable, since locals and stack arrays
2778     // grow downwards in all implementations.
2779     // (If, on some machine, the interpreter's Java locals or stack
2780     // were to grow upwards, the embedded doubles would be word-swapped.)
2781     scope_values->append(second);
2782     scope_values->append(first);
2783     return 2;
2784   }
2785 }
2786 
2787 
2788 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2789   if (value != NULL) {
2790     LIR_Opr opr = value->operand();
2791     Constant* con = value->as_Constant();
2792 
2793     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2794     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2795 
2796     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2797       // Unpinned constants may have a virtual operand for a part of the lifetime
2798       // or may be illegal when it was optimized away,
2799       // so always use a constant operand
2800       opr = LIR_OprFact::value_type(con->type());
2801     }
2802     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2803 
2804     if (opr->is_virtual()) {
2805       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2806 
2807       BlockBegin* block = block_of_op_with_id(op_id);
2808       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2809         // generating debug information for the last instruction of a block.
2810         // if this instruction is a branch, spill moves are inserted before this branch
2811         // and so the wrong operand would be returned (spill moves at block boundaries are not
2812         // considered in the live ranges of intervals)
2813         // Solution: use the first op_id of the branch target block instead.
2814         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2815           if (block->live_out().at(opr->vreg_number())) {
2816             op_id = block->sux_at(0)->first_lir_instruction_id();
2817             mode = LIR_OpVisitState::outputMode;
2818           }
2819         }
2820       }
2821 
2822       // Get current location of operand
2823       // The operand must be live because debug information is considered when building the intervals
2824       // if the interval is not live, color_lir_opr will cause an assertion failure
2825       opr = color_lir_opr(opr, op_id, mode);
2826       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2827 
2828       // Append to ScopeValue array
2829       return append_scope_value_for_operand(opr, scope_values);
2830 
2831     } else {
2832       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2833       assert(opr->is_constant(), "operand must be constant");
2834 
2835       return append_scope_value_for_constant(opr, scope_values);
2836     }
2837   } else {
2838     // append a dummy value because real value not needed
2839     scope_values->append(_illegal_value);
2840     return 1;
2841   }
2842 }
2843 
2844 
2845 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2846   IRScopeDebugInfo* caller_debug_info = NULL;
2847 
2848   ValueStack* caller_state = cur_state->caller_state();
2849   if (caller_state != NULL) {
2850     // process recursively to compute outermost scope first
2851     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2852   }
2853 
2854   // initialize these to null.
2855   // If we don't need deopt info or there are no locals, expressions or monitors,
2856   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2857   GrowableArray<ScopeValue*>*   locals      = NULL;
2858   GrowableArray<ScopeValue*>*   expressions = NULL;
2859   GrowableArray<MonitorValue*>* monitors    = NULL;
2860 
2861   // describe local variable values
2862   int nof_locals = cur_state->locals_size();
2863   if (nof_locals > 0) {
2864     locals = new GrowableArray<ScopeValue*>(nof_locals);
2865 
2866     int pos = 0;
2867     while (pos < nof_locals) {
2868       assert(pos < cur_state->locals_size(), "why not?");
2869 
2870       Value local = cur_state->local_at(pos);
2871       pos += append_scope_value(op_id, local, locals);
2872 
2873       assert(locals->length() == pos, "must match");
2874     }
2875     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2876     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2877   } else if (cur_scope->method()->max_locals() > 0) {
2878     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2879     nof_locals = cur_scope->method()->max_locals();
2880     locals = new GrowableArray<ScopeValue*>(nof_locals);
2881     for(int i = 0; i < nof_locals; i++) {
2882       locals->append(_illegal_value);
2883     }
2884   }
2885 
2886   // describe expression stack
2887   int nof_stack = cur_state->stack_size();
2888   if (nof_stack > 0) {
2889     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2890 
2891     int pos = 0;
2892     while (pos < nof_stack) {
2893       Value expression = cur_state->stack_at_inc(pos);
2894       append_scope_value(op_id, expression, expressions);
2895 
2896       assert(expressions->length() == pos, "must match");
2897     }
2898     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2899   }
2900 
2901   // describe monitors
2902   int nof_locks = cur_state->locks_size();
2903   if (nof_locks > 0) {
2904     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2905     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2906     for (int i = 0; i < nof_locks; i++) {
2907       monitors->append(location_for_monitor_index(lock_offset + i));
2908     }
2909   }
2910 
2911   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2912 }
2913 
2914 
2915 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2916   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2917 
2918   IRScope* innermost_scope = info->scope();
2919   ValueStack* innermost_state = info->stack();
2920 
2921   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2922 
2923   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2924 
2925   if (info->_scope_debug_info == NULL) {
2926     // compute debug information
2927     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2928   } else {
2929     // debug information already set. Check that it is correct from the current point of view
2930     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2931   }
2932 }
2933 
2934 
2935 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2936   LIR_OpVisitState visitor;
2937   int num_inst = instructions->length();
2938   bool has_dead = false;
2939 
2940   for (int j = 0; j < num_inst; j++) {
2941     LIR_Op* op = instructions->at(j);
2942     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2943       has_dead = true;
2944       continue;
2945     }
2946     int op_id = op->id();
2947 
2948     // visit instruction to get list of operands
2949     visitor.visit(op);
2950 
2951     // iterate all modes of the visitor and process all virtual operands
2952     for_each_visitor_mode(mode) {
2953       int n = visitor.opr_count(mode);
2954       for (int k = 0; k < n; k++) {
2955         LIR_Opr opr = visitor.opr_at(mode, k);
2956         if (opr->is_virtual_register()) {
2957           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2958         }
2959       }
2960     }
2961 
2962     if (visitor.info_count() > 0) {
2963       // exception handling
2964       if (compilation()->has_exception_handlers()) {
2965         XHandlers* xhandlers = visitor.all_xhandler();
2966         int n = xhandlers->length();
2967         for (int k = 0; k < n; k++) {
2968           XHandler* handler = xhandlers->handler_at(k);
2969           if (handler->entry_code() != NULL) {
2970             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2971           }
2972         }
2973       } else {
2974         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2975       }
2976 
2977       // compute oop map
2978       assert(iw != NULL, "needed for compute_oop_map");
2979       compute_oop_map(iw, visitor, op);
2980 
2981       // compute debug information
2982       if (!use_fpu_stack_allocation()) {
2983         // compute debug information if fpu stack allocation is not needed.
2984         // when fpu stack allocation is needed, the debug information can not
2985         // be computed here because the exact location of fpu operands is not known
2986         // -> debug information is created inside the fpu stack allocator
2987         int n = visitor.info_count();
2988         for (int k = 0; k < n; k++) {
2989           compute_debug_info(visitor.info_at(k), op_id);
2990         }
2991       }
2992     }
2993 
2994 #ifdef ASSERT
2995     // make sure we haven't made the op invalid.
2996     op->verify();
2997 #endif
2998 
2999     // remove useless moves
3000     if (op->code() == lir_move) {
3001       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3002       LIR_Op1* move = (LIR_Op1*)op;
3003       LIR_Opr src = move->in_opr();
3004       LIR_Opr dst = move->result_opr();
3005       if (dst == src ||
3006           !dst->is_pointer() && !src->is_pointer() &&
3007           src->is_same_register(dst)) {
3008         instructions->at_put(j, NULL);
3009         has_dead = true;
3010       }
3011     }
3012   }
3013 
3014   if (has_dead) {
3015     // iterate all instructions of the block and remove all null-values.
3016     int insert_point = 0;
3017     for (int j = 0; j < num_inst; j++) {
3018       LIR_Op* op = instructions->at(j);
3019       if (op != NULL) {
3020         if (insert_point != j) {
3021           instructions->at_put(insert_point, op);
3022         }
3023         insert_point++;
3024       }
3025     }
3026     instructions->truncate(insert_point);
3027   }
3028 }
3029 
3030 void LinearScan::assign_reg_num() {
3031   TIME_LINEAR_SCAN(timer_assign_reg_num);
3032 
3033   init_compute_debug_info();
3034   IntervalWalker* iw = init_compute_oop_maps();
3035 
3036   int num_blocks = block_count();
3037   for (int i = 0; i < num_blocks; i++) {
3038     BlockBegin* block = block_at(i);
3039     assign_reg_num(block->lir()->instructions_list(), iw);
3040   }
3041 }
3042 
3043 
3044 void LinearScan::do_linear_scan() {
3045   NOT_PRODUCT(_total_timer.begin_method());
3046 
3047   number_instructions();
3048 
3049   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3050 
3051   compute_local_live_sets();
3052   compute_global_live_sets();
3053   CHECK_BAILOUT();
3054 
3055   build_intervals();
3056   CHECK_BAILOUT();
3057   sort_intervals_before_allocation();
3058 
3059   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3060   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3061 
3062   allocate_registers();
3063   CHECK_BAILOUT();
3064 
3065   resolve_data_flow();
3066   if (compilation()->has_exception_handlers()) {
3067     resolve_exception_handlers();
3068   }
3069   // fill in number of spill slots into frame_map
3070   propagate_spill_slots();
3071   CHECK_BAILOUT();
3072 
3073   NOT_PRODUCT(print_intervals("After Register Allocation"));
3074   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3075 
3076   sort_intervals_after_allocation();
3077 
3078   DEBUG_ONLY(verify());
3079 
3080   eliminate_spill_moves();
3081   assign_reg_num();
3082   CHECK_BAILOUT();
3083 
3084   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3085   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3086 
3087   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3088 
3089     if (use_fpu_stack_allocation()) {
3090       allocate_fpu_stack(); // Only has effect on Intel
3091       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3092     }
3093   }
3094 
3095   { TIME_LINEAR_SCAN(timer_optimize_lir);
3096 
3097     EdgeMoveOptimizer::optimize(ir()->code());
3098     ControlFlowOptimizer::optimize(ir()->code());
3099     // check that cfg is still correct after optimizations
3100     ir()->verify();
3101   }
3102 
3103   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3104   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3105   NOT_PRODUCT(_total_timer.end_method(this));
3106 }
3107 
3108 
3109 // ********** Printing functions
3110 
3111 #ifndef PRODUCT
3112 
3113 void LinearScan::print_timers(double total) {
3114   _total_timer.print(total);
3115 }
3116 
3117 void LinearScan::print_statistics() {
3118   _stat_before_alloc.print("before allocation");
3119   _stat_after_asign.print("after assignment of register");
3120   _stat_final.print("after optimization");
3121 }
3122 
3123 void LinearScan::print_bitmap(BitMap& b) {
3124   for (unsigned int i = 0; i < b.size(); i++) {
3125     if (b.at(i)) tty->print("%d ", i);
3126   }
3127   tty->cr();
3128 }
3129 
3130 void LinearScan::print_intervals(const char* label) {
3131   if (TraceLinearScanLevel >= 1) {
3132     int i;
3133     tty->cr();
3134     tty->print_cr("%s", label);
3135 
3136     for (i = 0; i < interval_count(); i++) {
3137       Interval* interval = interval_at(i);
3138       if (interval != NULL) {
3139         interval->print();
3140       }
3141     }
3142 
3143     tty->cr();
3144     tty->print_cr("--- Basic Blocks ---");
3145     for (i = 0; i < block_count(); i++) {
3146       BlockBegin* block = block_at(i);
3147       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3148     }
3149     tty->cr();
3150     tty->cr();
3151   }
3152 
3153   if (PrintCFGToFile) {
3154     CFGPrinter::print_intervals(&_intervals, label);
3155   }
3156 }
3157 
3158 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3159   if (TraceLinearScanLevel >= level) {
3160     tty->cr();
3161     tty->print_cr("%s", label);
3162     print_LIR(ir()->linear_scan_order());
3163     tty->cr();
3164   }
3165 
3166   if (level == 1 && PrintCFGToFile) {
3167     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3168   }
3169 }
3170 
3171 #endif //PRODUCT
3172 
3173 
3174 // ********** verification functions for allocation
3175 // (check that all intervals have a correct register and that no registers are overwritten)
3176 #ifdef ASSERT
3177 
3178 void LinearScan::verify() {
3179   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3180   verify_intervals();
3181 
3182   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3183   verify_no_oops_in_fixed_intervals();
3184 
3185   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3186   verify_constants();
3187 
3188   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3189   verify_registers();
3190 
3191   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3192 }
3193 
3194 void LinearScan::verify_intervals() {
3195   int len = interval_count();
3196   bool has_error = false;
3197 
3198   for (int i = 0; i < len; i++) {
3199     Interval* i1 = interval_at(i);
3200     if (i1 == NULL) continue;
3201 
3202     i1->check_split_children();
3203 
3204     if (i1->reg_num() != i) {
3205       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3206       has_error = true;
3207     }
3208 
3209     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3210       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3211       has_error = true;
3212     }
3213 
3214     if (i1->assigned_reg() == any_reg) {
3215       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3216       has_error = true;
3217     }
3218 
3219     if (i1->assigned_reg() == i1->assigned_regHi()) {
3220       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3221       has_error = true;
3222     }
3223 
3224     if (!is_processed_reg_num(i1->assigned_reg())) {
3225       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3226       has_error = true;
3227     }
3228 
3229     if (i1->first() == Range::end()) {
3230       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3231       has_error = true;
3232     }
3233 
3234     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3235       if (r->from() >= r->to()) {
3236         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3237         has_error = true;
3238       }
3239     }
3240 
3241     for (int j = i + 1; j < len; j++) {
3242       Interval* i2 = interval_at(j);
3243       if (i2 == NULL) continue;
3244 
3245       // special intervals that are created in MoveResolver
3246       // -> ignore them because the range information has no meaning there
3247       if (i1->from() == 1 && i1->to() == 2) continue;
3248       if (i2->from() == 1 && i2->to() == 2) continue;
3249 
3250       int r1 = i1->assigned_reg();
3251       int r1Hi = i1->assigned_regHi();
3252       int r2 = i2->assigned_reg();
3253       int r2Hi = i2->assigned_regHi();
3254       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3255         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3256         i1->print(); tty->cr();
3257         i2->print(); tty->cr();
3258         has_error = true;
3259       }
3260     }
3261   }
3262 
3263   assert(has_error == false, "register allocation invalid");
3264 }
3265 
3266 
3267 void LinearScan::verify_no_oops_in_fixed_intervals() {
3268   Interval* fixed_intervals;
3269   Interval* other_intervals;
3270   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3271 
3272   // to ensure a walking until the last instruction id, add a dummy interval
3273   // with a high operation id
3274   other_intervals = new Interval(any_reg);
3275   other_intervals->add_range(max_jint - 2, max_jint - 1);
3276   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3277 
3278   LIR_OpVisitState visitor;
3279   for (int i = 0; i < block_count(); i++) {
3280     BlockBegin* block = block_at(i);
3281 
3282     LIR_OpList* instructions = block->lir()->instructions_list();
3283 
3284     for (int j = 0; j < instructions->length(); j++) {
3285       LIR_Op* op = instructions->at(j);
3286       int op_id = op->id();
3287 
3288       visitor.visit(op);
3289 
3290       if (visitor.info_count() > 0) {
3291         iw->walk_before(op->id());
3292         bool check_live = true;
3293         if (op->code() == lir_move) {
3294           LIR_Op1* move = (LIR_Op1*)op;
3295           check_live = (move->patch_code() == lir_patch_none);
3296         }
3297         LIR_OpBranch* branch = op->as_OpBranch();
3298         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3299           // Don't bother checking the stub in this case since the
3300           // exception stub will never return to normal control flow.
3301           check_live = false;
3302         }
3303 
3304         // Make sure none of the fixed registers is live across an
3305         // oopmap since we can't handle that correctly.
3306         if (check_live) {
3307           for (Interval* interval = iw->active_first(fixedKind);
3308                interval != Interval::end();
3309                interval = interval->next()) {
3310             if (interval->current_to() > op->id() + 1) {
3311               // This interval is live out of this op so make sure
3312               // that this interval represents some value that's
3313               // referenced by this op either as an input or output.
3314               bool ok = false;
3315               for_each_visitor_mode(mode) {
3316                 int n = visitor.opr_count(mode);
3317                 for (int k = 0; k < n; k++) {
3318                   LIR_Opr opr = visitor.opr_at(mode, k);
3319                   if (opr->is_fixed_cpu()) {
3320                     if (interval_at(reg_num(opr)) == interval) {
3321                       ok = true;
3322                       break;
3323                     }
3324                     int hi = reg_numHi(opr);
3325                     if (hi != -1 && interval_at(hi) == interval) {
3326                       ok = true;
3327                       break;
3328                     }
3329                   }
3330                 }
3331               }
3332               assert(ok, "fixed intervals should never be live across an oopmap point");
3333             }
3334           }
3335         }
3336       }
3337 
3338       // oop-maps at calls do not contain registers, so check is not needed
3339       if (!visitor.has_call()) {
3340 
3341         for_each_visitor_mode(mode) {
3342           int n = visitor.opr_count(mode);
3343           for (int k = 0; k < n; k++) {
3344             LIR_Opr opr = visitor.opr_at(mode, k);
3345 
3346             if (opr->is_fixed_cpu() && opr->is_oop()) {
3347               // operand is a non-virtual cpu register and contains an oop
3348               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3349 
3350               Interval* interval = interval_at(reg_num(opr));
3351               assert(interval != NULL, "no interval");
3352 
3353               if (mode == LIR_OpVisitState::inputMode) {
3354                 if (interval->to() >= op_id + 1) {
3355                   assert(interval->to() < op_id + 2 ||
3356                          interval->has_hole_between(op_id, op_id + 2),
3357                          "oop input operand live after instruction");
3358                 }
3359               } else if (mode == LIR_OpVisitState::outputMode) {
3360                 if (interval->from() <= op_id - 1) {
3361                   assert(interval->has_hole_between(op_id - 1, op_id),
3362                          "oop input operand live after instruction");
3363                 }
3364               }
3365             }
3366           }
3367         }
3368       }
3369     }
3370   }
3371 }
3372 
3373 
3374 void LinearScan::verify_constants() {
3375   int num_regs = num_virtual_regs();
3376   int size = live_set_size();
3377   int num_blocks = block_count();
3378 
3379   for (int i = 0; i < num_blocks; i++) {
3380     BlockBegin* block = block_at(i);
3381     BitMap live_at_edge = block->live_in();
3382 
3383     // visit all registers where the live_at_edge bit is set
3384     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3385       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3386 
3387       Value value = gen()->instruction_for_vreg(r);
3388 
3389       assert(value != NULL, "all intervals live across block boundaries must have Value");
3390       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3391       assert(value->operand()->vreg_number() == r, "register number must match");
3392       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3393     }
3394   }
3395 }
3396 
3397 
3398 class RegisterVerifier: public StackObj {
3399  private:
3400   LinearScan*   _allocator;
3401   BlockList     _work_list;      // all blocks that must be processed
3402   IntervalsList _saved_states;   // saved information of previous check
3403 
3404   // simplified access to methods of LinearScan
3405   Compilation*  compilation() const              { return _allocator->compilation(); }
3406   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3407   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3408 
3409   // currently, only registers are processed
3410   int           state_size()                     { return LinearScan::nof_regs; }
3411 
3412   // accessors
3413   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3414   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3415   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3416 
3417   // helper functions
3418   IntervalList* copy(IntervalList* input_state);
3419   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3420   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3421 
3422   void process_block(BlockBegin* block);
3423   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3424   void process_successor(BlockBegin* block, IntervalList* input_state);
3425   void process_operations(LIR_List* ops, IntervalList* input_state);
3426 
3427  public:
3428   RegisterVerifier(LinearScan* allocator)
3429     : _allocator(allocator)
3430     , _work_list(16)
3431     , _saved_states(BlockBegin::number_of_blocks(), NULL)
3432   { }
3433 
3434   void verify(BlockBegin* start);
3435 };
3436 
3437 
3438 // entry function from LinearScan that starts the verification
3439 void LinearScan::verify_registers() {
3440   RegisterVerifier verifier(this);
3441   verifier.verify(block_at(0));
3442 }
3443 
3444 
3445 void RegisterVerifier::verify(BlockBegin* start) {
3446   // setup input registers (method arguments) for first block
3447   IntervalList* input_state = new IntervalList(state_size(), NULL);
3448   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3449   for (int n = 0; n < args->length(); n++) {
3450     LIR_Opr opr = args->at(n);
3451     if (opr->is_register()) {
3452       Interval* interval = interval_at(reg_num(opr));
3453 
3454       if (interval->assigned_reg() < state_size()) {
3455         input_state->at_put(interval->assigned_reg(), interval);
3456       }
3457       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3458         input_state->at_put(interval->assigned_regHi(), interval);
3459       }
3460     }
3461   }
3462 
3463   set_state_for_block(start, input_state);
3464   add_to_work_list(start);
3465 
3466   // main loop for verification
3467   do {
3468     BlockBegin* block = _work_list.at(0);
3469     _work_list.remove_at(0);
3470 
3471     process_block(block);
3472   } while (!_work_list.is_empty());
3473 }
3474 
3475 void RegisterVerifier::process_block(BlockBegin* block) {
3476   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3477 
3478   // must copy state because it is modified
3479   IntervalList* input_state = copy(state_for_block(block));
3480 
3481   if (TraceLinearScanLevel >= 4) {
3482     tty->print_cr("Input-State of intervals:");
3483     tty->print("    ");
3484     for (int i = 0; i < state_size(); i++) {
3485       if (input_state->at(i) != NULL) {
3486         tty->print(" %4d", input_state->at(i)->reg_num());
3487       } else {
3488         tty->print("   __");
3489       }
3490     }
3491     tty->cr();
3492     tty->cr();
3493   }
3494 
3495   // process all operations of the block
3496   process_operations(block->lir(), input_state);
3497 
3498   // iterate all successors
3499   for (int i = 0; i < block->number_of_sux(); i++) {
3500     process_successor(block->sux_at(i), input_state);
3501   }
3502 }
3503 
3504 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3505   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3506 
3507   // must copy state because it is modified
3508   input_state = copy(input_state);
3509 
3510   if (xhandler->entry_code() != NULL) {
3511     process_operations(xhandler->entry_code(), input_state);
3512   }
3513   process_successor(xhandler->entry_block(), input_state);
3514 }
3515 
3516 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3517   IntervalList* saved_state = state_for_block(block);
3518 
3519   if (saved_state != NULL) {
3520     // this block was already processed before.
3521     // check if new input_state is consistent with saved_state
3522 
3523     bool saved_state_correct = true;
3524     for (int i = 0; i < state_size(); i++) {
3525       if (input_state->at(i) != saved_state->at(i)) {
3526         // current input_state and previous saved_state assume a different
3527         // interval in this register -> assume that this register is invalid
3528         if (saved_state->at(i) != NULL) {
3529           // invalidate old calculation only if it assumed that
3530           // register was valid. when the register was already invalid,
3531           // then the old calculation was correct.
3532           saved_state_correct = false;
3533           saved_state->at_put(i, NULL);
3534 
3535           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3536         }
3537       }
3538     }
3539 
3540     if (saved_state_correct) {
3541       // already processed block with correct input_state
3542       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3543     } else {
3544       // must re-visit this block
3545       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3546       add_to_work_list(block);
3547     }
3548 
3549   } else {
3550     // block was not processed before, so set initial input_state
3551     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3552 
3553     set_state_for_block(block, copy(input_state));
3554     add_to_work_list(block);
3555   }
3556 }
3557 
3558 
3559 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3560   IntervalList* copy_state = new IntervalList(input_state->length());
3561   copy_state->push_all(input_state);
3562   return copy_state;
3563 }
3564 
3565 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3566   if (reg != LinearScan::any_reg && reg < state_size()) {
3567     if (interval != NULL) {
3568       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3569     } else if (input_state->at(reg) != NULL) {
3570       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3571     }
3572 
3573     input_state->at_put(reg, interval);
3574   }
3575 }
3576 
3577 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3578   if (reg != LinearScan::any_reg && reg < state_size()) {
3579     if (input_state->at(reg) != interval) {
3580       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3581       return true;
3582     }
3583   }
3584   return false;
3585 }
3586 
3587 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3588   // visit all instructions of the block
3589   LIR_OpVisitState visitor;
3590   bool has_error = false;
3591 
3592   for (int i = 0; i < ops->length(); i++) {
3593     LIR_Op* op = ops->at(i);
3594     visitor.visit(op);
3595 
3596     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3597 
3598     // check if input operands are correct
3599     int j;
3600     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3601     for (j = 0; j < n; j++) {
3602       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3603       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3604         Interval* interval = interval_at(reg_num(opr));
3605         if (op->id() != -1) {
3606           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3607         }
3608 
3609         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3610         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3611 
3612         // When an operand is marked with is_last_use, then the fpu stack allocator
3613         // removes the register from the fpu stack -> the register contains no value
3614         if (opr->is_last_use()) {
3615           state_put(input_state, interval->assigned_reg(),   NULL);
3616           state_put(input_state, interval->assigned_regHi(), NULL);
3617         }
3618       }
3619     }
3620 
3621     // invalidate all caller save registers at calls
3622     if (visitor.has_call()) {
3623       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3624         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3625       }
3626       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3627         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3628       }
3629 
3630 #ifdef X86
3631       for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
3632         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3633       }
3634 #endif
3635     }
3636 
3637     // process xhandler before output and temp operands
3638     XHandlers* xhandlers = visitor.all_xhandler();
3639     n = xhandlers->length();
3640     for (int k = 0; k < n; k++) {
3641       process_xhandler(xhandlers->handler_at(k), input_state);
3642     }
3643 
3644     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3645     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3646     for (j = 0; j < n; j++) {
3647       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3648       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3649         Interval* interval = interval_at(reg_num(opr));
3650         if (op->id() != -1) {
3651           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3652         }
3653 
3654         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3655         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3656       }
3657     }
3658 
3659     // set output operands
3660     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3661     for (j = 0; j < n; j++) {
3662       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3663       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3664         Interval* interval = interval_at(reg_num(opr));
3665         if (op->id() != -1) {
3666           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3667         }
3668 
3669         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3670         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3671       }
3672     }
3673   }
3674   assert(has_error == false, "Error in register allocation");
3675 }
3676 
3677 #endif // ASSERT
3678 
3679 
3680 
3681 // **** Implementation of MoveResolver ******************************
3682 
3683 MoveResolver::MoveResolver(LinearScan* allocator) :
3684   _allocator(allocator),
3685   _multiple_reads_allowed(false),
3686   _mapping_from(8),
3687   _mapping_from_opr(8),
3688   _mapping_to(8),
3689   _insert_list(NULL),
3690   _insert_idx(-1),
3691   _insertion_buffer()
3692 {
3693   for (int i = 0; i < LinearScan::nof_regs; i++) {
3694     _register_blocked[i] = 0;
3695   }
3696   DEBUG_ONLY(check_empty());
3697 }
3698 
3699 
3700 #ifdef ASSERT
3701 
3702 void MoveResolver::check_empty() {
3703   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3704   for (int i = 0; i < LinearScan::nof_regs; i++) {
3705     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3706   }
3707   assert(_multiple_reads_allowed == false, "must have default value");
3708 }
3709 
3710 void MoveResolver::verify_before_resolve() {
3711   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3712   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3713   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3714 
3715   int i, j;
3716   if (!_multiple_reads_allowed) {
3717     for (i = 0; i < _mapping_from.length(); i++) {
3718       for (j = i + 1; j < _mapping_from.length(); j++) {
3719         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3720       }
3721     }
3722   }
3723 
3724   for (i = 0; i < _mapping_to.length(); i++) {
3725     for (j = i + 1; j < _mapping_to.length(); j++) {
3726       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3727     }
3728   }
3729 
3730 
3731   BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3732   used_regs.clear();
3733   if (!_multiple_reads_allowed) {
3734     for (i = 0; i < _mapping_from.length(); i++) {
3735       Interval* it = _mapping_from.at(i);
3736       if (it != NULL) {
3737         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3738         used_regs.set_bit(it->assigned_reg());
3739 
3740         if (it->assigned_regHi() != LinearScan::any_reg) {
3741           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3742           used_regs.set_bit(it->assigned_regHi());
3743         }
3744       }
3745     }
3746   }
3747 
3748   used_regs.clear();
3749   for (i = 0; i < _mapping_to.length(); i++) {
3750     Interval* it = _mapping_to.at(i);
3751     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3752     used_regs.set_bit(it->assigned_reg());
3753 
3754     if (it->assigned_regHi() != LinearScan::any_reg) {
3755       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3756       used_regs.set_bit(it->assigned_regHi());
3757     }
3758   }
3759 
3760   used_regs.clear();
3761   for (i = 0; i < _mapping_from.length(); i++) {
3762     Interval* it = _mapping_from.at(i);
3763     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3764       used_regs.set_bit(it->assigned_reg());
3765     }
3766   }
3767   for (i = 0; i < _mapping_to.length(); i++) {
3768     Interval* it = _mapping_to.at(i);
3769     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3770   }
3771 }
3772 
3773 #endif // ASSERT
3774 
3775 
3776 // mark assigned_reg and assigned_regHi of the interval as blocked
3777 void MoveResolver::block_registers(Interval* it) {
3778   int reg = it->assigned_reg();
3779   if (reg < LinearScan::nof_regs) {
3780     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3781     set_register_blocked(reg, 1);
3782   }
3783   reg = it->assigned_regHi();
3784   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3785     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3786     set_register_blocked(reg, 1);
3787   }
3788 }
3789 
3790 // mark assigned_reg and assigned_regHi of the interval as unblocked
3791 void MoveResolver::unblock_registers(Interval* it) {
3792   int reg = it->assigned_reg();
3793   if (reg < LinearScan::nof_regs) {
3794     assert(register_blocked(reg) > 0, "register already marked as unused");
3795     set_register_blocked(reg, -1);
3796   }
3797   reg = it->assigned_regHi();
3798   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3799     assert(register_blocked(reg) > 0, "register already marked as unused");
3800     set_register_blocked(reg, -1);
3801   }
3802 }
3803 
3804 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3805 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3806   int from_reg = -1;
3807   int from_regHi = -1;
3808   if (from != NULL) {
3809     from_reg = from->assigned_reg();
3810     from_regHi = from->assigned_regHi();
3811   }
3812 
3813   int reg = to->assigned_reg();
3814   if (reg < LinearScan::nof_regs) {
3815     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3816       return false;
3817     }
3818   }
3819   reg = to->assigned_regHi();
3820   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3821     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3822       return false;
3823     }
3824   }
3825 
3826   return true;
3827 }
3828 
3829 
3830 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3831   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3832   _insertion_buffer.init(list);
3833 }
3834 
3835 void MoveResolver::append_insertion_buffer() {
3836   if (_insertion_buffer.initialized()) {
3837     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3838   }
3839   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3840 
3841   _insert_list = NULL;
3842   _insert_idx = -1;
3843 }
3844 
3845 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3846   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3847   assert(from_interval->type() == to_interval->type(), "move between different types");
3848   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3849   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3850 
3851   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3852   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3853 
3854   if (!_multiple_reads_allowed) {
3855     // the last_use flag is an optimization for FPU stack allocation. When the same
3856     // input interval is used in more than one move, then it is too difficult to determine
3857     // if this move is really the last use.
3858     from_opr = from_opr->make_last_use();
3859   }
3860   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3861 
3862   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3863 }
3864 
3865 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3866   assert(from_opr->type() == to_interval->type(), "move between different types");
3867   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3868   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3869 
3870   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3871   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3872 
3873   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3874 }
3875 
3876 
3877 void MoveResolver::resolve_mappings() {
3878   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3879   DEBUG_ONLY(verify_before_resolve());
3880 
3881   // Block all registers that are used as input operands of a move.
3882   // When a register is blocked, no move to this register is emitted.
3883   // This is necessary for detecting cycles in moves.
3884   int i;
3885   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3886     Interval* from_interval = _mapping_from.at(i);
3887     if (from_interval != NULL) {
3888       block_registers(from_interval);
3889     }
3890   }
3891 
3892   int spill_candidate = -1;
3893   while (_mapping_from.length() > 0) {
3894     bool processed_interval = false;
3895 
3896     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3897       Interval* from_interval = _mapping_from.at(i);
3898       Interval* to_interval = _mapping_to.at(i);
3899 
3900       if (save_to_process_move(from_interval, to_interval)) {
3901         // this inverval can be processed because target is free
3902         if (from_interval != NULL) {
3903           insert_move(from_interval, to_interval);
3904           unblock_registers(from_interval);
3905         } else {
3906           insert_move(_mapping_from_opr.at(i), to_interval);
3907         }
3908         _mapping_from.remove_at(i);
3909         _mapping_from_opr.remove_at(i);
3910         _mapping_to.remove_at(i);
3911 
3912         processed_interval = true;
3913       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3914         // this interval cannot be processed now because target is not free
3915         // it starts in a register, so it is a possible candidate for spilling
3916         spill_candidate = i;
3917       }
3918     }
3919 
3920     if (!processed_interval) {
3921       // no move could be processed because there is a cycle in the move list
3922       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3923       assert(spill_candidate != -1, "no interval in register for spilling found");
3924 
3925       // create a new spill interval and assign a stack slot to it
3926       Interval* from_interval = _mapping_from.at(spill_candidate);
3927       Interval* spill_interval = new Interval(-1);
3928       spill_interval->set_type(from_interval->type());
3929 
3930       // add a dummy range because real position is difficult to calculate
3931       // Note: this range is a special case when the integrity of the allocation is checked
3932       spill_interval->add_range(1, 2);
3933 
3934       //       do not allocate a new spill slot for temporary interval, but
3935       //       use spill slot assigned to from_interval. Otherwise moves from
3936       //       one stack slot to another can happen (not allowed by LIR_Assembler
3937       int spill_slot = from_interval->canonical_spill_slot();
3938       if (spill_slot < 0) {
3939         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3940         from_interval->set_canonical_spill_slot(spill_slot);
3941       }
3942       spill_interval->assign_reg(spill_slot);
3943       allocator()->append_interval(spill_interval);
3944 
3945       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3946 
3947       // insert a move from register to stack and update the mapping
3948       insert_move(from_interval, spill_interval);
3949       _mapping_from.at_put(spill_candidate, spill_interval);
3950       unblock_registers(from_interval);
3951     }
3952   }
3953 
3954   // reset to default value
3955   _multiple_reads_allowed = false;
3956 
3957   // check that all intervals have been processed
3958   DEBUG_ONLY(check_empty());
3959 }
3960 
3961 
3962 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3963   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3964   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3965 
3966   create_insertion_buffer(insert_list);
3967   _insert_list = insert_list;
3968   _insert_idx = insert_idx;
3969 }
3970 
3971 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3972   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3973 
3974   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3975     // insert position changed -> resolve current mappings
3976     resolve_mappings();
3977   }
3978 
3979   if (insert_list != _insert_list) {
3980     // block changed -> append insertion_buffer because it is
3981     // bound to a specific block and create a new insertion_buffer
3982     append_insertion_buffer();
3983     create_insertion_buffer(insert_list);
3984   }
3985 
3986   _insert_list = insert_list;
3987   _insert_idx = insert_idx;
3988 }
3989 
3990 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3991   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3992 
3993   _mapping_from.append(from_interval);
3994   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3995   _mapping_to.append(to_interval);
3996 }
3997 
3998 
3999 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4000   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4001   assert(from_opr->is_constant(), "only for constants");
4002 
4003   _mapping_from.append(NULL);
4004   _mapping_from_opr.append(from_opr);
4005   _mapping_to.append(to_interval);
4006 }
4007 
4008 void MoveResolver::resolve_and_append_moves() {
4009   if (has_mappings()) {
4010     resolve_mappings();
4011   }
4012   append_insertion_buffer();
4013 }
4014 
4015 
4016 
4017 // **** Implementation of Range *************************************
4018 
4019 Range::Range(int from, int to, Range* next) :
4020   _from(from),
4021   _to(to),
4022   _next(next)
4023 {
4024 }
4025 
4026 // initialize sentinel
4027 Range* Range::_end = NULL;
4028 void Range::initialize(Arena* arena) {
4029   _end = new (arena) Range(max_jint, max_jint, NULL);
4030 }
4031 
4032 int Range::intersects_at(Range* r2) const {
4033   const Range* r1 = this;
4034 
4035   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4036   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4037 
4038   do {
4039     if (r1->from() < r2->from()) {
4040       if (r1->to() <= r2->from()) {
4041         r1 = r1->next(); if (r1 == _end) return -1;
4042       } else {
4043         return r2->from();
4044       }
4045     } else if (r2->from() < r1->from()) {
4046       if (r2->to() <= r1->from()) {
4047         r2 = r2->next(); if (r2 == _end) return -1;
4048       } else {
4049         return r1->from();
4050       }
4051     } else { // r1->from() == r2->from()
4052       if (r1->from() == r1->to()) {
4053         r1 = r1->next(); if (r1 == _end) return -1;
4054       } else if (r2->from() == r2->to()) {
4055         r2 = r2->next(); if (r2 == _end) return -1;
4056       } else {
4057         return r1->from();
4058       }
4059     }
4060   } while (true);
4061 }
4062 
4063 #ifndef PRODUCT
4064 void Range::print(outputStream* out) const {
4065   out->print("[%d, %d[ ", _from, _to);
4066 }
4067 #endif
4068 
4069 
4070 
4071 // **** Implementation of Interval **********************************
4072 
4073 // initialize sentinel
4074 Interval* Interval::_end = NULL;
4075 void Interval::initialize(Arena* arena) {
4076   Range::initialize(arena);
4077   _end = new (arena) Interval(-1);
4078 }
4079 
4080 Interval::Interval(int reg_num) :
4081   _reg_num(reg_num),
4082   _type(T_ILLEGAL),
4083   _first(Range::end()),
4084   _use_pos_and_kinds(12),
4085   _current(Range::end()),
4086   _next(_end),
4087   _state(invalidState),
4088   _assigned_reg(LinearScan::any_reg),
4089   _assigned_regHi(LinearScan::any_reg),
4090   _cached_to(-1),
4091   _cached_opr(LIR_OprFact::illegalOpr),
4092   _cached_vm_reg(VMRegImpl::Bad()),
4093   _split_children(0),
4094   _canonical_spill_slot(-1),
4095   _insert_move_when_activated(false),
4096   _register_hint(NULL),
4097   _spill_state(noDefinitionFound),
4098   _spill_definition_pos(-1)
4099 {
4100   _split_parent = this;
4101   _current_split_child = this;
4102 }
4103 
4104 int Interval::calc_to() {
4105   assert(_first != Range::end(), "interval has no range");
4106 
4107   Range* r = _first;
4108   while (r->next() != Range::end()) {
4109     r = r->next();
4110   }
4111   return r->to();
4112 }
4113 
4114 
4115 #ifdef ASSERT
4116 // consistency check of split-children
4117 void Interval::check_split_children() {
4118   if (_split_children.length() > 0) {
4119     assert(is_split_parent(), "only split parents can have children");
4120 
4121     for (int i = 0; i < _split_children.length(); i++) {
4122       Interval* i1 = _split_children.at(i);
4123 
4124       assert(i1->split_parent() == this, "not a split child of this interval");
4125       assert(i1->type() == type(), "must be equal for all split children");
4126       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4127 
4128       for (int j = i + 1; j < _split_children.length(); j++) {
4129         Interval* i2 = _split_children.at(j);
4130 
4131         assert(i1->reg_num() != i2->reg_num(), "same register number");
4132 
4133         if (i1->from() < i2->from()) {
4134           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4135         } else {
4136           assert(i2->from() < i1->from(), "intervals start at same op_id");
4137           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4138         }
4139       }
4140     }
4141   }
4142 }
4143 #endif // ASSERT
4144 
4145 Interval* Interval::register_hint(bool search_split_child) const {
4146   if (!search_split_child) {
4147     return _register_hint;
4148   }
4149 
4150   if (_register_hint != NULL) {
4151     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4152 
4153     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4154       return _register_hint;
4155 
4156     } else if (_register_hint->_split_children.length() > 0) {
4157       // search the first split child that has a register assigned
4158       int len = _register_hint->_split_children.length();
4159       for (int i = 0; i < len; i++) {
4160         Interval* cur = _register_hint->_split_children.at(i);
4161 
4162         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4163           return cur;
4164         }
4165       }
4166     }
4167   }
4168 
4169   // no hint interval found that has a register assigned
4170   return NULL;
4171 }
4172 
4173 
4174 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4175   assert(is_split_parent(), "can only be called for split parents");
4176   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4177 
4178   Interval* result;
4179   if (_split_children.length() == 0) {
4180     result = this;
4181   } else {
4182     result = NULL;
4183     int len = _split_children.length();
4184 
4185     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4186     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4187 
4188     int i;
4189     for (i = 0; i < len; i++) {
4190       Interval* cur = _split_children.at(i);
4191       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4192         if (i > 0) {
4193           // exchange current split child to start of list (faster access for next call)
4194           _split_children.at_put(i, _split_children.at(0));
4195           _split_children.at_put(0, cur);
4196         }
4197 
4198         // interval found
4199         result = cur;
4200         break;
4201       }
4202     }
4203 
4204 #ifdef ASSERT
4205     for (i = 0; i < len; i++) {
4206       Interval* tmp = _split_children.at(i);
4207       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4208         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4209         result->print();
4210         tmp->print();
4211         assert(false, "two valid result intervals found");
4212       }
4213     }
4214 #endif
4215   }
4216 
4217   assert(result != NULL, "no matching interval found");
4218   assert(result->covers(op_id, mode), "op_id not covered by interval");
4219 
4220   return result;
4221 }
4222 
4223 
4224 // returns the last split child that ends before the given op_id
4225 Interval* Interval::split_child_before_op_id(int op_id) {
4226   assert(op_id >= 0, "invalid op_id");
4227 
4228   Interval* parent = split_parent();
4229   Interval* result = NULL;
4230 
4231   int len = parent->_split_children.length();
4232   assert(len > 0, "no split children available");
4233 
4234   for (int i = len - 1; i >= 0; i--) {
4235     Interval* cur = parent->_split_children.at(i);
4236     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4237       result = cur;
4238     }
4239   }
4240 
4241   assert(result != NULL, "no split child found");
4242   return result;
4243 }
4244 
4245 
4246 // checks if op_id is covered by any split child
4247 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4248   assert(is_split_parent(), "can only be called for split parents");
4249   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4250 
4251   if (_split_children.length() == 0) {
4252     // simple case if interval was not split
4253     return covers(op_id, mode);
4254 
4255   } else {
4256     // extended case: check all split children
4257     int len = _split_children.length();
4258     for (int i = 0; i < len; i++) {
4259       Interval* cur = _split_children.at(i);
4260       if (cur->covers(op_id, mode)) {
4261         return true;
4262       }
4263     }
4264     return false;
4265   }
4266 }
4267 
4268 
4269 // Note: use positions are sorted descending -> first use has highest index
4270 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4271   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4272 
4273   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4274     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4275       return _use_pos_and_kinds.at(i);
4276     }
4277   }
4278   return max_jint;
4279 }
4280 
4281 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4282   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4283 
4284   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4285     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4286       return _use_pos_and_kinds.at(i);
4287     }
4288   }
4289   return max_jint;
4290 }
4291 
4292 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4293   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4294 
4295   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4296     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4297       return _use_pos_and_kinds.at(i);
4298     }
4299   }
4300   return max_jint;
4301 }
4302 
4303 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4304   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4305 
4306   int prev = 0;
4307   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4308     if (_use_pos_and_kinds.at(i) > from) {
4309       return prev;
4310     }
4311     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4312       prev = _use_pos_and_kinds.at(i);
4313     }
4314   }
4315   return prev;
4316 }
4317 
4318 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4319   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4320 
4321   // do not add use positions for precolored intervals because
4322   // they are never used
4323   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4324 #ifdef ASSERT
4325     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4326     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4327       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4328       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4329       if (i > 0) {
4330         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4331       }
4332     }
4333 #endif
4334 
4335     // Note: add_use is called in descending order, so list gets sorted
4336     //       automatically by just appending new use positions
4337     int len = _use_pos_and_kinds.length();
4338     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4339       _use_pos_and_kinds.append(pos);
4340       _use_pos_and_kinds.append(use_kind);
4341     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4342       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4343       _use_pos_and_kinds.at_put(len - 1, use_kind);
4344     }
4345   }
4346 }
4347 
4348 void Interval::add_range(int from, int to) {
4349   assert(from < to, "invalid range");
4350   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4351   assert(from <= first()->to(), "not inserting at begin of interval");
4352 
4353   if (first()->from() <= to) {
4354     // join intersecting ranges
4355     first()->set_from(MIN2(from, first()->from()));
4356     first()->set_to  (MAX2(to,   first()->to()));
4357   } else {
4358     // insert new range
4359     _first = new Range(from, to, first());
4360   }
4361 }
4362 
4363 Interval* Interval::new_split_child() {
4364   // allocate new interval
4365   Interval* result = new Interval(-1);
4366   result->set_type(type());
4367 
4368   Interval* parent = split_parent();
4369   result->_split_parent = parent;
4370   result->set_register_hint(parent);
4371 
4372   // insert new interval in children-list of parent
4373   if (parent->_split_children.length() == 0) {
4374     assert(is_split_parent(), "list must be initialized at first split");
4375 
4376     parent->_split_children = IntervalList(4);
4377     parent->_split_children.append(this);
4378   }
4379   parent->_split_children.append(result);
4380 
4381   return result;
4382 }
4383 
4384 // split this interval at the specified position and return
4385 // the remainder as a new interval.
4386 //
4387 // when an interval is split, a bi-directional link is established between the original interval
4388 // (the split parent) and the intervals that are split off this interval (the split children)
4389 // When a split child is split again, the new created interval is also a direct child
4390 // of the original parent (there is no tree of split children stored, but a flat list)
4391 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4392 //
4393 // Note: The new interval has no valid reg_num
4394 Interval* Interval::split(int split_pos) {
4395   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4396 
4397   // allocate new interval
4398   Interval* result = new_split_child();
4399 
4400   // split the ranges
4401   Range* prev = NULL;
4402   Range* cur = _first;
4403   while (cur != Range::end() && cur->to() <= split_pos) {
4404     prev = cur;
4405     cur = cur->next();
4406   }
4407   assert(cur != Range::end(), "split interval after end of last range");
4408 
4409   if (cur->from() < split_pos) {
4410     result->_first = new Range(split_pos, cur->to(), cur->next());
4411     cur->set_to(split_pos);
4412     cur->set_next(Range::end());
4413 
4414   } else {
4415     assert(prev != NULL, "split before start of first range");
4416     result->_first = cur;
4417     prev->set_next(Range::end());
4418   }
4419   result->_current = result->_first;
4420   _cached_to = -1; // clear cached value
4421 
4422   // split list of use positions
4423   int total_len = _use_pos_and_kinds.length();
4424   int start_idx = total_len - 2;
4425   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4426     start_idx -= 2;
4427   }
4428 
4429   intStack new_use_pos_and_kinds(total_len - start_idx);
4430   int i;
4431   for (i = start_idx + 2; i < total_len; i++) {
4432     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4433   }
4434 
4435   _use_pos_and_kinds.truncate(start_idx + 2);
4436   result->_use_pos_and_kinds = _use_pos_and_kinds;
4437   _use_pos_and_kinds = new_use_pos_and_kinds;
4438 
4439 #ifdef ASSERT
4440   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4441   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4442   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4443 
4444   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4445     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4446     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4447   }
4448   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4449     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4450     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4451   }
4452 #endif
4453 
4454   return result;
4455 }
4456 
4457 // split this interval at the specified position and return
4458 // the head as a new interval (the original interval is the tail)
4459 //
4460 // Currently, only the first range can be split, and the new interval
4461 // must not have split positions
4462 Interval* Interval::split_from_start(int split_pos) {
4463   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4464   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4465   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4466   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4467 
4468   // allocate new interval
4469   Interval* result = new_split_child();
4470 
4471   // the new created interval has only one range (checked by assertion above),
4472   // so the splitting of the ranges is very simple
4473   result->add_range(_first->from(), split_pos);
4474 
4475   if (split_pos == _first->to()) {
4476     assert(_first->next() != Range::end(), "must not be at end");
4477     _first = _first->next();
4478   } else {
4479     _first->set_from(split_pos);
4480   }
4481 
4482   return result;
4483 }
4484 
4485 
4486 // returns true if the op_id is inside the interval
4487 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4488   Range* cur  = _first;
4489 
4490   while (cur != Range::end() && cur->to() < op_id) {
4491     cur = cur->next();
4492   }
4493   if (cur != Range::end()) {
4494     assert(cur->to() != cur->next()->from(), "ranges not separated");
4495 
4496     if (mode == LIR_OpVisitState::outputMode) {
4497       return cur->from() <= op_id && op_id < cur->to();
4498     } else {
4499       return cur->from() <= op_id && op_id <= cur->to();
4500     }
4501   }
4502   return false;
4503 }
4504 
4505 // returns true if the interval has any hole between hole_from and hole_to
4506 // (even if the hole has only the length 1)
4507 bool Interval::has_hole_between(int hole_from, int hole_to) {
4508   assert(hole_from < hole_to, "check");
4509   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4510 
4511   Range* cur  = _first;
4512   while (cur != Range::end()) {
4513     assert(cur->to() < cur->next()->from(), "no space between ranges");
4514 
4515     // hole-range starts before this range -> hole
4516     if (hole_from < cur->from()) {
4517       return true;
4518 
4519     // hole-range completely inside this range -> no hole
4520     } else if (hole_to <= cur->to()) {
4521       return false;
4522 
4523     // overlapping of hole-range with this range -> hole
4524     } else if (hole_from <= cur->to()) {
4525       return true;
4526     }
4527 
4528     cur = cur->next();
4529   }
4530 
4531   return false;
4532 }
4533 
4534 
4535 #ifndef PRODUCT
4536 void Interval::print(outputStream* out) const {
4537   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4538   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4539 
4540   const char* type_name;
4541   LIR_Opr opr = LIR_OprFact::illegal();
4542   if (reg_num() < LIR_OprDesc::vreg_base) {
4543     type_name = "fixed";
4544     // need a temporary operand for fixed intervals because type() cannot be called
4545     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4546       opr = LIR_OprFact::single_cpu(assigned_reg());
4547     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4548       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4549 #ifdef X86
4550     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
4551       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4552 #endif
4553     } else {
4554       ShouldNotReachHere();
4555     }
4556   } else {
4557     type_name = type2name(type());
4558     if (assigned_reg() != -1 &&
4559         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4560       opr = LinearScan::calc_operand_for_interval(this);
4561     }
4562   }
4563 
4564   out->print("%d %s ", reg_num(), type_name);
4565   if (opr->is_valid()) {
4566     out->print("\"");
4567     opr->print(out);
4568     out->print("\" ");
4569   }
4570   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4571 
4572   // print ranges
4573   Range* cur = _first;
4574   while (cur != Range::end()) {
4575     cur->print(out);
4576     cur = cur->next();
4577     assert(cur != NULL, "range list not closed with range sentinel");
4578   }
4579 
4580   // print use positions
4581   int prev = 0;
4582   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4583   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4584     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4585     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4586 
4587     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4588     prev = _use_pos_and_kinds.at(i);
4589   }
4590 
4591   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4592   out->cr();
4593 }
4594 #endif
4595 
4596 
4597 
4598 // **** Implementation of IntervalWalker ****************************
4599 
4600 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4601  : _compilation(allocator->compilation())
4602  , _allocator(allocator)
4603 {
4604   _unhandled_first[fixedKind] = unhandled_fixed_first;
4605   _unhandled_first[anyKind]   = unhandled_any_first;
4606   _active_first[fixedKind]    = Interval::end();
4607   _inactive_first[fixedKind]  = Interval::end();
4608   _active_first[anyKind]      = Interval::end();
4609   _inactive_first[anyKind]    = Interval::end();
4610   _current_position = -1;
4611   _current = NULL;
4612   next_interval();
4613 }
4614 
4615 
4616 // append interval at top of list
4617 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4618   interval->set_next(*list); *list = interval;
4619 }
4620 
4621 
4622 // append interval in order of current range from()
4623 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4624   Interval* prev = NULL;
4625   Interval* cur  = *list;
4626   while (cur->current_from() < interval->current_from()) {
4627     prev = cur; cur = cur->next();
4628   }
4629   if (prev == NULL) {
4630     *list = interval;
4631   } else {
4632     prev->set_next(interval);
4633   }
4634   interval->set_next(cur);
4635 }
4636 
4637 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4638   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4639 
4640   Interval* prev = NULL;
4641   Interval* cur  = *list;
4642   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4643     prev = cur; cur = cur->next();
4644   }
4645   if (prev == NULL) {
4646     *list = interval;
4647   } else {
4648     prev->set_next(interval);
4649   }
4650   interval->set_next(cur);
4651 }
4652 
4653 
4654 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4655   while (*list != Interval::end() && *list != i) {
4656     list = (*list)->next_addr();
4657   }
4658   if (*list != Interval::end()) {
4659     assert(*list == i, "check");
4660     *list = (*list)->next();
4661     return true;
4662   } else {
4663     return false;
4664   }
4665 }
4666 
4667 void IntervalWalker::remove_from_list(Interval* i) {
4668   bool deleted;
4669 
4670   if (i->state() == activeState) {
4671     deleted = remove_from_list(active_first_addr(anyKind), i);
4672   } else {
4673     assert(i->state() == inactiveState, "invalid state");
4674     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4675   }
4676 
4677   assert(deleted, "interval has not been found in list");
4678 }
4679 
4680 
4681 void IntervalWalker::walk_to(IntervalState state, int from) {
4682   assert (state == activeState || state == inactiveState, "wrong state");
4683   for_each_interval_kind(kind) {
4684     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4685     Interval* next   = *prev;
4686     while (next->current_from() <= from) {
4687       Interval* cur = next;
4688       next = cur->next();
4689 
4690       bool range_has_changed = false;
4691       while (cur->current_to() <= from) {
4692         cur->next_range();
4693         range_has_changed = true;
4694       }
4695 
4696       // also handle move from inactive list to active list
4697       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4698 
4699       if (range_has_changed) {
4700         // remove cur from list
4701         *prev = next;
4702         if (cur->current_at_end()) {
4703           // move to handled state (not maintained as a list)
4704           cur->set_state(handledState);
4705           interval_moved(cur, kind, state, handledState);
4706         } else if (cur->current_from() <= from){
4707           // sort into active list
4708           append_sorted(active_first_addr(kind), cur);
4709           cur->set_state(activeState);
4710           if (*prev == cur) {
4711             assert(state == activeState, "check");
4712             prev = cur->next_addr();
4713           }
4714           interval_moved(cur, kind, state, activeState);
4715         } else {
4716           // sort into inactive list
4717           append_sorted(inactive_first_addr(kind), cur);
4718           cur->set_state(inactiveState);
4719           if (*prev == cur) {
4720             assert(state == inactiveState, "check");
4721             prev = cur->next_addr();
4722           }
4723           interval_moved(cur, kind, state, inactiveState);
4724         }
4725       } else {
4726         prev = cur->next_addr();
4727         continue;
4728       }
4729     }
4730   }
4731 }
4732 
4733 
4734 void IntervalWalker::next_interval() {
4735   IntervalKind kind;
4736   Interval* any   = _unhandled_first[anyKind];
4737   Interval* fixed = _unhandled_first[fixedKind];
4738 
4739   if (any != Interval::end()) {
4740     // intervals may start at same position -> prefer fixed interval
4741     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4742 
4743     assert (kind == fixedKind && fixed->from() <= any->from() ||
4744             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4745     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4746 
4747   } else if (fixed != Interval::end()) {
4748     kind = fixedKind;
4749   } else {
4750     _current = NULL; return;
4751   }
4752   _current_kind = kind;
4753   _current = _unhandled_first[kind];
4754   _unhandled_first[kind] = _current->next();
4755   _current->set_next(Interval::end());
4756   _current->rewind_range();
4757 }
4758 
4759 
4760 void IntervalWalker::walk_to(int lir_op_id) {
4761   assert(_current_position <= lir_op_id, "can not walk backwards");
4762   while (current() != NULL) {
4763     bool is_active = current()->from() <= lir_op_id;
4764     int id = is_active ? current()->from() : lir_op_id;
4765 
4766     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4767 
4768     // set _current_position prior to call of walk_to
4769     _current_position = id;
4770 
4771     // call walk_to even if _current_position == id
4772     walk_to(activeState, id);
4773     walk_to(inactiveState, id);
4774 
4775     if (is_active) {
4776       current()->set_state(activeState);
4777       if (activate_current()) {
4778         append_sorted(active_first_addr(current_kind()), current());
4779         interval_moved(current(), current_kind(), unhandledState, activeState);
4780       }
4781 
4782       next_interval();
4783     } else {
4784       return;
4785     }
4786   }
4787 }
4788 
4789 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4790 #ifndef PRODUCT
4791   if (TraceLinearScanLevel >= 4) {
4792     #define print_state(state) \
4793     switch(state) {\
4794       case unhandledState: tty->print("unhandled"); break;\
4795       case activeState: tty->print("active"); break;\
4796       case inactiveState: tty->print("inactive"); break;\
4797       case handledState: tty->print("handled"); break;\
4798       default: ShouldNotReachHere(); \
4799     }
4800 
4801     print_state(from); tty->print(" to "); print_state(to);
4802     tty->fill_to(23);
4803     interval->print();
4804 
4805     #undef print_state
4806   }
4807 #endif
4808 }
4809 
4810 
4811 
4812 // **** Implementation of LinearScanWalker **************************
4813 
4814 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4815   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4816   , _move_resolver(allocator)
4817 {
4818   for (int i = 0; i < LinearScan::nof_regs; i++) {
4819     _spill_intervals[i] = new IntervalList(2);
4820   }
4821 }
4822 
4823 
4824 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4825   for (int i = _first_reg; i <= _last_reg; i++) {
4826     _use_pos[i] = max_jint;
4827 
4828     if (!only_process_use_pos) {
4829       _block_pos[i] = max_jint;
4830       _spill_intervals[i]->clear();
4831     }
4832   }
4833 }
4834 
4835 inline void LinearScanWalker::exclude_from_use(int reg) {
4836   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4837   if (reg >= _first_reg && reg <= _last_reg) {
4838     _use_pos[reg] = 0;
4839   }
4840 }
4841 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4842   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4843 
4844   exclude_from_use(i->assigned_reg());
4845   exclude_from_use(i->assigned_regHi());
4846 }
4847 
4848 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4849   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4850 
4851   if (reg >= _first_reg && reg <= _last_reg) {
4852     if (_use_pos[reg] > use_pos) {
4853       _use_pos[reg] = use_pos;
4854     }
4855     if (!only_process_use_pos) {
4856       _spill_intervals[reg]->append(i);
4857     }
4858   }
4859 }
4860 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4861   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4862   if (use_pos != -1) {
4863     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4864     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4865   }
4866 }
4867 
4868 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4869   if (reg >= _first_reg && reg <= _last_reg) {
4870     if (_block_pos[reg] > block_pos) {
4871       _block_pos[reg] = block_pos;
4872     }
4873     if (_use_pos[reg] > block_pos) {
4874       _use_pos[reg] = block_pos;
4875     }
4876   }
4877 }
4878 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4879   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4880   if (block_pos != -1) {
4881     set_block_pos(i->assigned_reg(), i, block_pos);
4882     set_block_pos(i->assigned_regHi(), i, block_pos);
4883   }
4884 }
4885 
4886 
4887 void LinearScanWalker::free_exclude_active_fixed() {
4888   Interval* list = active_first(fixedKind);
4889   while (list != Interval::end()) {
4890     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4891     exclude_from_use(list);
4892     list = list->next();
4893   }
4894 }
4895 
4896 void LinearScanWalker::free_exclude_active_any() {
4897   Interval* list = active_first(anyKind);
4898   while (list != Interval::end()) {
4899     exclude_from_use(list);
4900     list = list->next();
4901   }
4902 }
4903 
4904 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4905   Interval* list = inactive_first(fixedKind);
4906   while (list != Interval::end()) {
4907     if (cur->to() <= list->current_from()) {
4908       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4909       set_use_pos(list, list->current_from(), true);
4910     } else {
4911       set_use_pos(list, list->current_intersects_at(cur), true);
4912     }
4913     list = list->next();
4914   }
4915 }
4916 
4917 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4918   Interval* list = inactive_first(anyKind);
4919   while (list != Interval::end()) {
4920     set_use_pos(list, list->current_intersects_at(cur), true);
4921     list = list->next();
4922   }
4923 }
4924 
4925 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4926   Interval* list = unhandled_first(kind);
4927   while (list != Interval::end()) {
4928     set_use_pos(list, list->intersects_at(cur), true);
4929     if (kind == fixedKind && cur->to() <= list->from()) {
4930       set_use_pos(list, list->from(), true);
4931     }
4932     list = list->next();
4933   }
4934 }
4935 
4936 void LinearScanWalker::spill_exclude_active_fixed() {
4937   Interval* list = active_first(fixedKind);
4938   while (list != Interval::end()) {
4939     exclude_from_use(list);
4940     list = list->next();
4941   }
4942 }
4943 
4944 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4945   Interval* list = unhandled_first(fixedKind);
4946   while (list != Interval::end()) {
4947     set_block_pos(list, list->intersects_at(cur));
4948     list = list->next();
4949   }
4950 }
4951 
4952 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4953   Interval* list = inactive_first(fixedKind);
4954   while (list != Interval::end()) {
4955     if (cur->to() > list->current_from()) {
4956       set_block_pos(list, list->current_intersects_at(cur));
4957     } else {
4958       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4959     }
4960 
4961     list = list->next();
4962   }
4963 }
4964 
4965 void LinearScanWalker::spill_collect_active_any() {
4966   Interval* list = active_first(anyKind);
4967   while (list != Interval::end()) {
4968     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4969     list = list->next();
4970   }
4971 }
4972 
4973 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4974   Interval* list = inactive_first(anyKind);
4975   while (list != Interval::end()) {
4976     if (list->current_intersects(cur)) {
4977       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4978     }
4979     list = list->next();
4980   }
4981 }
4982 
4983 
4984 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4985   // output all moves here. When source and target are equal, the move is
4986   // optimized away later in assign_reg_nums
4987 
4988   op_id = (op_id + 1) & ~1;
4989   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4990   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4991 
4992   // calculate index of instruction inside instruction list of current block
4993   // the minimal index (for a block with no spill moves) can be calculated because the
4994   // numbering of instructions is known.
4995   // When the block already contains spill moves, the index must be increased until the
4996   // correct index is reached.
4997   LIR_OpList* list = op_block->lir()->instructions_list();
4998   int index = (op_id - list->at(0)->id()) / 2;
4999   assert(list->at(index)->id() <= op_id, "error in calculation");
5000 
5001   while (list->at(index)->id() != op_id) {
5002     index++;
5003     assert(0 <= index && index < list->length(), "index out of bounds");
5004   }
5005   assert(1 <= index && index < list->length(), "index out of bounds");
5006   assert(list->at(index)->id() == op_id, "error in calculation");
5007 
5008   // insert new instruction before instruction at position index
5009   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5010   _move_resolver.add_mapping(src_it, dst_it);
5011 }
5012 
5013 
5014 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5015   int from_block_nr = min_block->linear_scan_number();
5016   int to_block_nr = max_block->linear_scan_number();
5017 
5018   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5019   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5020   assert(from_block_nr < to_block_nr, "must cross block boundary");
5021 
5022   // Try to split at end of max_block. If this would be after
5023   // max_split_pos, then use the begin of max_block
5024   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5025   if (optimal_split_pos > max_split_pos) {
5026     optimal_split_pos = max_block->first_lir_instruction_id();
5027   }
5028 
5029   int min_loop_depth = max_block->loop_depth();
5030   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5031     BlockBegin* cur = block_at(i);
5032 
5033     if (cur->loop_depth() < min_loop_depth) {
5034       // block with lower loop-depth found -> split at the end of this block
5035       min_loop_depth = cur->loop_depth();
5036       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5037     }
5038   }
5039   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5040 
5041   return optimal_split_pos;
5042 }
5043 
5044 
5045 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5046   int optimal_split_pos = -1;
5047   if (min_split_pos == max_split_pos) {
5048     // trivial case, no optimization of split position possible
5049     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5050     optimal_split_pos = min_split_pos;
5051 
5052   } else {
5053     assert(min_split_pos < max_split_pos, "must be true then");
5054     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5055 
5056     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5057     // beginning of a block, then min_split_pos is also a possible split position.
5058     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5059     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5060 
5061     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5062     // when an interval ends at the end of the last block of the method
5063     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5064     // block at this op_id)
5065     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5066 
5067     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5068     if (min_block == max_block) {
5069       // split position cannot be moved to block boundary, so split as late as possible
5070       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5071       optimal_split_pos = max_split_pos;
5072 
5073     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5074       // Do not move split position if the interval has a hole before max_split_pos.
5075       // Intervals resulting from Phi-Functions have more than one definition (marked
5076       // as mustHaveRegister) with a hole before each definition. When the register is needed
5077       // for the second definition, an earlier reloading is unnecessary.
5078       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5079       optimal_split_pos = max_split_pos;
5080 
5081     } else {
5082       // seach optimal block boundary between min_split_pos and max_split_pos
5083       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5084 
5085       if (do_loop_optimization) {
5086         // Loop optimization: if a loop-end marker is found between min- and max-position,
5087         // then split before this loop
5088         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5089         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5090 
5091         assert(loop_end_pos > min_split_pos, "invalid order");
5092         if (loop_end_pos < max_split_pos) {
5093           // loop-end marker found between min- and max-position
5094           // if it is not the end marker for the same loop as the min-position, then move
5095           // the max-position to this loop block.
5096           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5097           // of the interval (normally, only mustHaveRegister causes a reloading)
5098           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5099 
5100           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5101           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5102 
5103           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5104           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5105             optimal_split_pos = -1;
5106             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5107           } else {
5108             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5109           }
5110         }
5111       }
5112 
5113       if (optimal_split_pos == -1) {
5114         // not calculated by loop optimization
5115         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5116       }
5117     }
5118   }
5119   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5120 
5121   return optimal_split_pos;
5122 }
5123 
5124 
5125 /*
5126   split an interval at the optimal position between min_split_pos and
5127   max_split_pos in two parts:
5128   1) the left part has already a location assigned
5129   2) the right part is sorted into to the unhandled-list
5130 */
5131 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5132   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5133   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5134 
5135   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5136   assert(current_position() < min_split_pos, "cannot split before current position");
5137   assert(min_split_pos <= max_split_pos,     "invalid order");
5138   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5139 
5140   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5141 
5142   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5143   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5144   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5145 
5146   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5147     // the split position would be just before the end of the interval
5148     // -> no split at all necessary
5149     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5150     return;
5151   }
5152 
5153   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5154   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5155 
5156   if (!allocator()->is_block_begin(optimal_split_pos)) {
5157     // move position before actual instruction (odd op_id)
5158     optimal_split_pos = (optimal_split_pos - 1) | 1;
5159   }
5160 
5161   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5162   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5163   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5164 
5165   Interval* split_part = it->split(optimal_split_pos);
5166 
5167   allocator()->append_interval(split_part);
5168   allocator()->copy_register_flags(it, split_part);
5169   split_part->set_insert_move_when_activated(move_necessary);
5170   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5171 
5172   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5173   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5174   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5175 }
5176 
5177 /*
5178   split an interval at the optimal position between min_split_pos and
5179   max_split_pos in two parts:
5180   1) the left part has already a location assigned
5181   2) the right part is always on the stack and therefore ignored in further processing
5182 */
5183 void LinearScanWalker::split_for_spilling(Interval* it) {
5184   // calculate allowed range of splitting position
5185   int max_split_pos = current_position();
5186   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5187 
5188   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5189   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5190 
5191   assert(it->state() == activeState,     "why spill interval that is not active?");
5192   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5193   assert(min_split_pos <= max_split_pos, "invalid order");
5194   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5195   assert(current_position() < it->to(),  "interval must not end before current position");
5196 
5197   if (min_split_pos == it->from()) {
5198     // the whole interval is never used, so spill it entirely to memory
5199     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5200     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5201 
5202     allocator()->assign_spill_slot(it);
5203     allocator()->change_spill_state(it, min_split_pos);
5204 
5205     // Also kick parent intervals out of register to memory when they have no use
5206     // position. This avoids short interval in register surrounded by intervals in
5207     // memory -> avoid useless moves from memory to register and back
5208     Interval* parent = it;
5209     while (parent != NULL && parent->is_split_child()) {
5210       parent = parent->split_child_before_op_id(parent->from());
5211 
5212       if (parent->assigned_reg() < LinearScan::nof_regs) {
5213         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5214           // parent is never used, so kick it out of its assigned register
5215           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5216           allocator()->assign_spill_slot(parent);
5217         } else {
5218           // do not go further back because the register is actually used by the interval
5219           parent = NULL;
5220         }
5221       }
5222     }
5223 
5224   } else {
5225     // search optimal split pos, split interval and spill only the right hand part
5226     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5227 
5228     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5229     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5230     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5231 
5232     if (!allocator()->is_block_begin(optimal_split_pos)) {
5233       // move position before actual instruction (odd op_id)
5234       optimal_split_pos = (optimal_split_pos - 1) | 1;
5235     }
5236 
5237     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5238     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5239     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5240 
5241     Interval* spilled_part = it->split(optimal_split_pos);
5242     allocator()->append_interval(spilled_part);
5243     allocator()->assign_spill_slot(spilled_part);
5244     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5245 
5246     if (!allocator()->is_block_begin(optimal_split_pos)) {
5247       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5248       insert_move(optimal_split_pos, it, spilled_part);
5249     }
5250 
5251     // the current_split_child is needed later when moves are inserted for reloading
5252     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5253     spilled_part->make_current_split_child();
5254 
5255     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5256     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5257     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5258   }
5259 }
5260 
5261 
5262 void LinearScanWalker::split_stack_interval(Interval* it) {
5263   int min_split_pos = current_position() + 1;
5264   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5265 
5266   split_before_usage(it, min_split_pos, max_split_pos);
5267 }
5268 
5269 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5270   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5271   int max_split_pos = register_available_until;
5272 
5273   split_before_usage(it, min_split_pos, max_split_pos);
5274 }
5275 
5276 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5277   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5278 
5279   int current_pos = current_position();
5280   if (it->state() == inactiveState) {
5281     // the interval is currently inactive, so no spill slot is needed for now.
5282     // when the split part is activated, the interval has a new chance to get a register,
5283     // so in the best case no stack slot is necessary
5284     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5285     split_before_usage(it, current_pos + 1, current_pos + 1);
5286 
5287   } else {
5288     // search the position where the interval must have a register and split
5289     // at the optimal position before.
5290     // The new created part is added to the unhandled list and will get a register
5291     // when it is activated
5292     int min_split_pos = current_pos + 1;
5293     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5294 
5295     split_before_usage(it, min_split_pos, max_split_pos);
5296 
5297     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5298     split_for_spilling(it);
5299   }
5300 }
5301 
5302 
5303 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5304   int min_full_reg = any_reg;
5305   int max_partial_reg = any_reg;
5306 
5307   for (int i = _first_reg; i <= _last_reg; i++) {
5308     if (i == ignore_reg) {
5309       // this register must be ignored
5310 
5311     } else if (_use_pos[i] >= interval_to) {
5312       // this register is free for the full interval
5313       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5314         min_full_reg = i;
5315       }
5316     } else if (_use_pos[i] > reg_needed_until) {
5317       // this register is at least free until reg_needed_until
5318       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5319         max_partial_reg = i;
5320       }
5321     }
5322   }
5323 
5324   if (min_full_reg != any_reg) {
5325     return min_full_reg;
5326   } else if (max_partial_reg != any_reg) {
5327     *need_split = true;
5328     return max_partial_reg;
5329   } else {
5330     return any_reg;
5331   }
5332 }
5333 
5334 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5335   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5336 
5337   int min_full_reg = any_reg;
5338   int max_partial_reg = any_reg;
5339 
5340   for (int i = _first_reg; i < _last_reg; i+=2) {
5341     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5342       // this register is free for the full interval
5343       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5344         min_full_reg = i;
5345       }
5346     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5347       // this register is at least free until reg_needed_until
5348       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5349         max_partial_reg = i;
5350       }
5351     }
5352   }
5353 
5354   if (min_full_reg != any_reg) {
5355     return min_full_reg;
5356   } else if (max_partial_reg != any_reg) {
5357     *need_split = true;
5358     return max_partial_reg;
5359   } else {
5360     return any_reg;
5361   }
5362 }
5363 
5364 
5365 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5366   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5367 
5368   init_use_lists(true);
5369   free_exclude_active_fixed();
5370   free_exclude_active_any();
5371   free_collect_inactive_fixed(cur);
5372   free_collect_inactive_any(cur);
5373 //  free_collect_unhandled(fixedKind, cur);
5374   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5375 
5376   // _use_pos contains the start of the next interval that has this register assigned
5377   // (either as a fixed register or a normal allocated register in the past)
5378   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5379   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5380   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5381 
5382   int hint_reg, hint_regHi;
5383   Interval* register_hint = cur->register_hint();
5384   if (register_hint != NULL) {
5385     hint_reg = register_hint->assigned_reg();
5386     hint_regHi = register_hint->assigned_regHi();
5387 
5388     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5389       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5390       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5391     }
5392     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5393 
5394   } else {
5395     hint_reg = any_reg;
5396     hint_regHi = any_reg;
5397   }
5398   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5399   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5400 
5401   // the register must be free at least until this position
5402   int reg_needed_until = cur->from() + 1;
5403   int interval_to = cur->to();
5404 
5405   bool need_split = false;
5406   int split_pos = -1;
5407   int reg = any_reg;
5408   int regHi = any_reg;
5409 
5410   if (_adjacent_regs) {
5411     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5412     regHi = reg + 1;
5413     if (reg == any_reg) {
5414       return false;
5415     }
5416     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5417 
5418   } else {
5419     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5420     if (reg == any_reg) {
5421       return false;
5422     }
5423     split_pos = _use_pos[reg];
5424 
5425     if (_num_phys_regs == 2) {
5426       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5427 
5428       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5429         // do not split interval if only one register can be assigned until the split pos
5430         // (when one register is found for the whole interval, split&spill is only
5431         // performed for the hi register)
5432         return false;
5433 
5434       } else if (regHi != any_reg) {
5435         split_pos = MIN2(split_pos, _use_pos[regHi]);
5436 
5437         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5438         if (reg > regHi) {
5439           int temp = reg;
5440           reg = regHi;
5441           regHi = temp;
5442         }
5443       }
5444     }
5445   }
5446 
5447   cur->assign_reg(reg, regHi);
5448   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5449 
5450   assert(split_pos > 0, "invalid split_pos");
5451   if (need_split) {
5452     // register not available for full interval, so split it
5453     split_when_partial_register_available(cur, split_pos);
5454   }
5455 
5456   // only return true if interval is completely assigned
5457   return _num_phys_regs == 1 || regHi != any_reg;
5458 }
5459 
5460 
5461 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5462   int max_reg = any_reg;
5463 
5464   for (int i = _first_reg; i <= _last_reg; i++) {
5465     if (i == ignore_reg) {
5466       // this register must be ignored
5467 
5468     } else if (_use_pos[i] > reg_needed_until) {
5469       if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5470         max_reg = i;
5471       }
5472     }
5473   }
5474 
5475   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5476     *need_split = true;
5477   }
5478 
5479   return max_reg;
5480 }
5481 
5482 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5483   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5484 
5485   int max_reg = any_reg;
5486 
5487   for (int i = _first_reg; i < _last_reg; i+=2) {
5488     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5489       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5490         max_reg = i;
5491       }
5492     }
5493   }
5494 
5495   if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5496     *need_split = true;
5497   }
5498 
5499   return max_reg;
5500 }
5501 
5502 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5503   assert(reg != any_reg, "no register assigned");
5504 
5505   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5506     Interval* it = _spill_intervals[reg]->at(i);
5507     remove_from_list(it);
5508     split_and_spill_interval(it);
5509   }
5510 
5511   if (regHi != any_reg) {
5512     IntervalList* processed = _spill_intervals[reg];
5513     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5514       Interval* it = _spill_intervals[regHi]->at(i);
5515       if (processed->index_of(it) == -1) {
5516         remove_from_list(it);
5517         split_and_spill_interval(it);
5518       }
5519     }
5520   }
5521 }
5522 
5523 
5524 // Split an Interval and spill it to memory so that cur can be placed in a register
5525 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5526   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5527 
5528   // collect current usage of registers
5529   init_use_lists(false);
5530   spill_exclude_active_fixed();
5531 //  spill_block_unhandled_fixed(cur);
5532   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5533   spill_block_inactive_fixed(cur);
5534   spill_collect_active_any();
5535   spill_collect_inactive_any(cur);
5536 
5537 #ifndef PRODUCT
5538   if (TraceLinearScanLevel >= 4) {
5539     tty->print_cr("      state of registers:");
5540     for (int i = _first_reg; i <= _last_reg; i++) {
5541       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5542       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5543         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5544       }
5545       tty->cr();
5546     }
5547   }
5548 #endif
5549 
5550   // the register must be free at least until this position
5551   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5552   int interval_to = cur->to();
5553   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5554 
5555   int split_pos = 0;
5556   int use_pos = 0;
5557   bool need_split = false;
5558   int reg, regHi;
5559 
5560   if (_adjacent_regs) {
5561     reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5562     regHi = reg + 1;
5563 
5564     if (reg != any_reg) {
5565       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5566       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5567     }
5568   } else {
5569     reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5570     regHi = any_reg;
5571 
5572     if (reg != any_reg) {
5573       use_pos = _use_pos[reg];
5574       split_pos = _block_pos[reg];
5575 
5576       if (_num_phys_regs == 2) {
5577         if (cur->assigned_reg() != any_reg) {
5578           regHi = reg;
5579           reg = cur->assigned_reg();
5580         } else {
5581           regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5582           if (regHi != any_reg) {
5583             use_pos = MIN2(use_pos, _use_pos[regHi]);
5584             split_pos = MIN2(split_pos, _block_pos[regHi]);
5585           }
5586         }
5587 
5588         if (regHi != any_reg && reg > regHi) {
5589           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5590           int temp = reg;
5591           reg = regHi;
5592           regHi = temp;
5593         }
5594       }
5595     }
5596   }
5597 
5598   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5599     // the first use of cur is later than the spilling position -> spill cur
5600     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5601 
5602     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5603       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5604       // assign a reasonable register and do a bailout in product mode to avoid errors
5605       allocator()->assign_spill_slot(cur);
5606       BAILOUT("LinearScan: no register found");
5607     }
5608 
5609     split_and_spill_interval(cur);
5610   } else {
5611     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5612     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5613     assert(split_pos > 0, "invalid split_pos");
5614     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5615 
5616     cur->assign_reg(reg, regHi);
5617     if (need_split) {
5618       // register not available for full interval, so split it
5619       split_when_partial_register_available(cur, split_pos);
5620     }
5621 
5622     // perform splitting and spilling for all affected intervalls
5623     split_and_spill_intersecting_intervals(reg, regHi);
5624   }
5625 }
5626 
5627 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5628 #ifdef X86
5629   // fast calculation of intervals that can never get a register because the
5630   // the next instruction is a call that blocks all registers
5631   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5632 
5633   // check if this interval is the result of a split operation
5634   // (an interval got a register until this position)
5635   int pos = cur->from();
5636   if ((pos & 1) == 1) {
5637     // the current instruction is a call that blocks all registers
5638     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5639       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5640 
5641       // safety check that there is really no register available
5642       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5643       return true;
5644     }
5645 
5646   }
5647 #endif
5648   return false;
5649 }
5650 
5651 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5652   BasicType type = cur->type();
5653   _num_phys_regs = LinearScan::num_physical_regs(type);
5654   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5655 
5656   if (pd_init_regs_for_alloc(cur)) {
5657     // the appropriate register range was selected.
5658   } else if (type == T_FLOAT || type == T_DOUBLE) {
5659     _first_reg = pd_first_fpu_reg;
5660     _last_reg = pd_last_fpu_reg;
5661   } else {
5662     _first_reg = pd_first_cpu_reg;
5663     _last_reg = FrameMap::last_cpu_reg();
5664   }
5665 
5666   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5667   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5668 }
5669 
5670 
5671 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5672   if (op->code() != lir_move) {
5673     return false;
5674   }
5675   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5676 
5677   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5678   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5679   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5680 }
5681 
5682 // optimization (especially for phi functions of nested loops):
5683 // assign same spill slot to non-intersecting intervals
5684 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5685   if (cur->is_split_child()) {
5686     // optimization is only suitable for split parents
5687     return;
5688   }
5689 
5690   Interval* register_hint = cur->register_hint(false);
5691   if (register_hint == NULL) {
5692     // cur is not the target of a move, otherwise register_hint would be set
5693     return;
5694   }
5695   assert(register_hint->is_split_parent(), "register hint must be split parent");
5696 
5697   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5698     // combining the stack slots for intervals where spill move optimization is applied
5699     // is not benefitial and would cause problems
5700     return;
5701   }
5702 
5703   int begin_pos = cur->from();
5704   int end_pos = cur->to();
5705   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5706     // safety check that lir_op_with_id is allowed
5707     return;
5708   }
5709 
5710   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5711     // cur and register_hint are not connected with two moves
5712     return;
5713   }
5714 
5715   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5716   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5717   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5718     // register_hint must be split, otherwise the re-writing of use positions does not work
5719     return;
5720   }
5721 
5722   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5723   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5724   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5725   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5726 
5727   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5728     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5729     return;
5730   }
5731   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5732 
5733   // modify intervals such that cur gets the same stack slot as register_hint
5734   // delete use positions to prevent the intervals to get a register at beginning
5735   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5736   cur->remove_first_use_pos();
5737   end_hint->remove_first_use_pos();
5738 }
5739 
5740 
5741 // allocate a physical register or memory location to an interval
5742 bool LinearScanWalker::activate_current() {
5743   Interval* cur = current();
5744   bool result = true;
5745 
5746   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5747   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5748 
5749   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5750     // activating an interval that has a stack slot assigned -> split it at first use position
5751     // used for method parameters
5752     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5753 
5754     split_stack_interval(cur);
5755     result = false;
5756 
5757   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5758     // activating an interval that must start in a stack slot, but may get a register later
5759     // used for lir_roundfp: rounding is done by store to stack and reload later
5760     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5761     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5762 
5763     allocator()->assign_spill_slot(cur);
5764     split_stack_interval(cur);
5765     result = false;
5766 
5767   } else if (cur->assigned_reg() == any_reg) {
5768     // interval has not assigned register -> normal allocation
5769     // (this is the normal case for most intervals)
5770     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5771 
5772     // assign same spill slot to non-intersecting intervals
5773     combine_spilled_intervals(cur);
5774 
5775     init_vars_for_alloc(cur);
5776     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5777       // no empty register available.
5778       // split and spill another interval so that this interval gets a register
5779       alloc_locked_reg(cur);
5780     }
5781 
5782     // spilled intervals need not be move to active-list
5783     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5784       result = false;
5785     }
5786   }
5787 
5788   // load spilled values that become active from stack slot to register
5789   if (cur->insert_move_when_activated()) {
5790     assert(cur->is_split_child(), "must be");
5791     assert(cur->current_split_child() != NULL, "must be");
5792     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5793     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5794 
5795     insert_move(cur->from(), cur->current_split_child(), cur);
5796   }
5797   cur->make_current_split_child();
5798 
5799   return result; // true = interval is moved to active list
5800 }
5801 
5802 
5803 // Implementation of EdgeMoveOptimizer
5804 
5805 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5806   _edge_instructions(4),
5807   _edge_instructions_idx(4)
5808 {
5809 }
5810 
5811 void EdgeMoveOptimizer::optimize(BlockList* code) {
5812   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5813 
5814   // ignore the first block in the list (index 0 is not processed)
5815   for (int i = code->length() - 1; i >= 1; i--) {
5816     BlockBegin* block = code->at(i);
5817 
5818     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5819       optimizer.optimize_moves_at_block_end(block);
5820     }
5821     if (block->number_of_sux() == 2) {
5822       optimizer.optimize_moves_at_block_begin(block);
5823     }
5824   }
5825 }
5826 
5827 
5828 // clear all internal data structures
5829 void EdgeMoveOptimizer::init_instructions() {
5830   _edge_instructions.clear();
5831   _edge_instructions_idx.clear();
5832 }
5833 
5834 // append a lir-instruction-list and the index of the current operation in to the list
5835 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5836   _edge_instructions.append(instructions);
5837   _edge_instructions_idx.append(instructions_idx);
5838 }
5839 
5840 // return the current operation of the given edge (predecessor or successor)
5841 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5842   LIR_OpList* instructions = _edge_instructions.at(edge);
5843   int idx = _edge_instructions_idx.at(edge);
5844 
5845   if (idx < instructions->length()) {
5846     return instructions->at(idx);
5847   } else {
5848     return NULL;
5849   }
5850 }
5851 
5852 // removes the current operation of the given edge (predecessor or successor)
5853 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5854   LIR_OpList* instructions = _edge_instructions.at(edge);
5855   int idx = _edge_instructions_idx.at(edge);
5856   instructions->remove_at(idx);
5857 
5858   if (decrement_index) {
5859     _edge_instructions_idx.at_put(edge, idx - 1);
5860   }
5861 }
5862 
5863 
5864 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5865   if (op1 == NULL || op2 == NULL) {
5866     // at least one block is already empty -> no optimization possible
5867     return true;
5868   }
5869 
5870   if (op1->code() == lir_move && op2->code() == lir_move) {
5871     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5872     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5873     LIR_Op1* move1 = (LIR_Op1*)op1;
5874     LIR_Op1* move2 = (LIR_Op1*)op2;
5875     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5876       // these moves are exactly equal and can be optimized
5877       return false;
5878     }
5879 
5880   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5881     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5882     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5883     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5884     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5885     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5886       // equal FPU stack operations can be optimized
5887       return false;
5888     }
5889 
5890   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5891     // equal FPU stack operations can be optimized
5892     return false;
5893   }
5894 
5895   // no optimization possible
5896   return true;
5897 }
5898 
5899 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5900   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5901 
5902   if (block->is_predecessor(block)) {
5903     // currently we can't handle this correctly.
5904     return;
5905   }
5906 
5907   init_instructions();
5908   int num_preds = block->number_of_preds();
5909   assert(num_preds > 1, "do not call otherwise");
5910   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5911 
5912   // setup a list with the lir-instructions of all predecessors
5913   int i;
5914   for (i = 0; i < num_preds; i++) {
5915     BlockBegin* pred = block->pred_at(i);
5916     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5917 
5918     if (pred->number_of_sux() != 1) {
5919       // this can happen with switch-statements where multiple edges are between
5920       // the same blocks.
5921       return;
5922     }
5923 
5924     assert(pred->number_of_sux() == 1, "can handle only one successor");
5925     assert(pred->sux_at(0) == block, "invalid control flow");
5926     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5927     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5928     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5929 
5930     if (pred_instructions->last()->info() != NULL) {
5931       // can not optimize instructions when debug info is needed
5932       return;
5933     }
5934 
5935     // ignore the unconditional branch at the end of the block
5936     append_instructions(pred_instructions, pred_instructions->length() - 2);
5937   }
5938 
5939 
5940   // process lir-instructions while all predecessors end with the same instruction
5941   while (true) {
5942     LIR_Op* op = instruction_at(0);
5943     for (i = 1; i < num_preds; i++) {
5944       if (operations_different(op, instruction_at(i))) {
5945         // these instructions are different and cannot be optimized ->
5946         // no further optimization possible
5947         return;
5948       }
5949     }
5950 
5951     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5952 
5953     // insert the instruction at the beginning of the current block
5954     block->lir()->insert_before(1, op);
5955 
5956     // delete the instruction at the end of all predecessors
5957     for (i = 0; i < num_preds; i++) {
5958       remove_cur_instruction(i, true);
5959     }
5960   }
5961 }
5962 
5963 
5964 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5965   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5966 
5967   init_instructions();
5968   int num_sux = block->number_of_sux();
5969 
5970   LIR_OpList* cur_instructions = block->lir()->instructions_list();
5971 
5972   assert(num_sux == 2, "method should not be called otherwise");
5973   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5974   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5975   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5976 
5977   if (cur_instructions->last()->info() != NULL) {
5978     // can no optimize instructions when debug info is needed
5979     return;
5980   }
5981 
5982   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5983   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5984     // not a valid case for optimization
5985     // currently, only blocks that end with two branches (conditional branch followed
5986     // by unconditional branch) are optimized
5987     return;
5988   }
5989 
5990   // now it is guaranteed that the block ends with two branch instructions.
5991   // the instructions are inserted at the end of the block before these two branches
5992   int insert_idx = cur_instructions->length() - 2;
5993 
5994   int i;
5995 #ifdef ASSERT
5996   for (i = insert_idx - 1; i >= 0; i--) {
5997     LIR_Op* op = cur_instructions->at(i);
5998     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
5999       assert(false, "block with two successors can have only two branch instructions");
6000     }
6001   }
6002 #endif
6003 
6004   // setup a list with the lir-instructions of all successors
6005   for (i = 0; i < num_sux; i++) {
6006     BlockBegin* sux = block->sux_at(i);
6007     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6008 
6009     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6010 
6011     if (sux->number_of_preds() != 1) {
6012       // this can happen with switch-statements where multiple edges are between
6013       // the same blocks.
6014       return;
6015     }
6016     assert(sux->pred_at(0) == block, "invalid control flow");
6017     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6018 
6019     // ignore the label at the beginning of the block
6020     append_instructions(sux_instructions, 1);
6021   }
6022 
6023   // process lir-instructions while all successors begin with the same instruction
6024   while (true) {
6025     LIR_Op* op = instruction_at(0);
6026     for (i = 1; i < num_sux; i++) {
6027       if (operations_different(op, instruction_at(i))) {
6028         // these instructions are different and cannot be optimized ->
6029         // no further optimization possible
6030         return;
6031       }
6032     }
6033 
6034     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6035 
6036     // insert instruction at end of current block
6037     block->lir()->insert_before(insert_idx, op);
6038     insert_idx++;
6039 
6040     // delete the instructions at the beginning of all successors
6041     for (i = 0; i < num_sux; i++) {
6042       remove_cur_instruction(i, false);
6043     }
6044   }
6045 }
6046 
6047 
6048 // Implementation of ControlFlowOptimizer
6049 
6050 ControlFlowOptimizer::ControlFlowOptimizer() :
6051   _original_preds(4)
6052 {
6053 }
6054 
6055 void ControlFlowOptimizer::optimize(BlockList* code) {
6056   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6057 
6058   // push the OSR entry block to the end so that we're not jumping over it.
6059   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6060   if (osr_entry) {
6061     int index = osr_entry->linear_scan_number();
6062     assert(code->at(index) == osr_entry, "wrong index");
6063     code->remove_at(index);
6064     code->append(osr_entry);
6065   }
6066 
6067   optimizer.reorder_short_loops(code);
6068   optimizer.delete_empty_blocks(code);
6069   optimizer.delete_unnecessary_jumps(code);
6070   optimizer.delete_jumps_to_return(code);
6071 }
6072 
6073 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6074   int i = header_idx + 1;
6075   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6076   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6077     i++;
6078   }
6079 
6080   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6081     int end_idx = i - 1;
6082     BlockBegin* end_block = code->at(end_idx);
6083 
6084     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6085       // short loop from header_idx to end_idx found -> reorder blocks such that
6086       // the header_block is the last block instead of the first block of the loop
6087       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6088                                          end_idx - header_idx + 1,
6089                                          header_block->block_id(), end_block->block_id()));
6090 
6091       for (int j = header_idx; j < end_idx; j++) {
6092         code->at_put(j, code->at(j + 1));
6093       }
6094       code->at_put(end_idx, header_block);
6095 
6096       // correct the flags so that any loop alignment occurs in the right place.
6097       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6098       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6099       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6100     }
6101   }
6102 }
6103 
6104 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6105   for (int i = code->length() - 1; i >= 0; i--) {
6106     BlockBegin* block = code->at(i);
6107 
6108     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6109       reorder_short_loop(code, block, i);
6110     }
6111   }
6112 
6113   DEBUG_ONLY(verify(code));
6114 }
6115 
6116 // only blocks with exactly one successor can be deleted. Such blocks
6117 // must always end with an unconditional branch to this successor
6118 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6119   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6120     return false;
6121   }
6122 
6123   LIR_OpList* instructions = block->lir()->instructions_list();
6124 
6125   assert(instructions->length() >= 2, "block must have label and branch");
6126   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6127   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6128   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6129   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6130 
6131   // block must have exactly one successor
6132 
6133   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6134     return true;
6135   }
6136   return false;
6137 }
6138 
6139 // substitute branch targets in all branch-instructions of this blocks
6140 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6141   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6142 
6143   LIR_OpList* instructions = block->lir()->instructions_list();
6144 
6145   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6146   for (int i = instructions->length() - 1; i >= 1; i--) {
6147     LIR_Op* op = instructions->at(i);
6148 
6149     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6150       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6151       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6152 
6153       if (branch->block() == target_from) {
6154         branch->change_block(target_to);
6155       }
6156       if (branch->ublock() == target_from) {
6157         branch->change_ublock(target_to);
6158       }
6159     }
6160   }
6161 }
6162 
6163 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6164   int old_pos = 0;
6165   int new_pos = 0;
6166   int num_blocks = code->length();
6167 
6168   while (old_pos < num_blocks) {
6169     BlockBegin* block = code->at(old_pos);
6170 
6171     if (can_delete_block(block)) {
6172       BlockBegin* new_target = block->sux_at(0);
6173 
6174       // propagate backward branch target flag for correct code alignment
6175       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6176         new_target->set(BlockBegin::backward_branch_target_flag);
6177       }
6178 
6179       // collect a list with all predecessors that contains each predecessor only once
6180       // the predecessors of cur are changed during the substitution, so a copy of the
6181       // predecessor list is necessary
6182       int j;
6183       _original_preds.clear();
6184       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6185         BlockBegin* pred = block->pred_at(j);
6186         if (_original_preds.index_of(pred) == -1) {
6187           _original_preds.append(pred);
6188         }
6189       }
6190 
6191       for (j = _original_preds.length() - 1; j >= 0; j--) {
6192         BlockBegin* pred = _original_preds.at(j);
6193         substitute_branch_target(pred, block, new_target);
6194         pred->substitute_sux(block, new_target);
6195       }
6196     } else {
6197       // adjust position of this block in the block list if blocks before
6198       // have been deleted
6199       if (new_pos != old_pos) {
6200         code->at_put(new_pos, code->at(old_pos));
6201       }
6202       new_pos++;
6203     }
6204     old_pos++;
6205   }
6206   code->truncate(new_pos);
6207 
6208   DEBUG_ONLY(verify(code));
6209 }
6210 
6211 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6212   // skip the last block because there a branch is always necessary
6213   for (int i = code->length() - 2; i >= 0; i--) {
6214     BlockBegin* block = code->at(i);
6215     LIR_OpList* instructions = block->lir()->instructions_list();
6216 
6217     LIR_Op* last_op = instructions->last();
6218     if (last_op->code() == lir_branch) {
6219       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6220       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6221 
6222       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6223       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6224 
6225       if (last_branch->info() == NULL) {
6226         if (last_branch->block() == code->at(i + 1)) {
6227 
6228           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6229 
6230           // delete last branch instruction
6231           instructions->truncate(instructions->length() - 1);
6232 
6233         } else {
6234           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6235           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6236             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6237             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6238 
6239             if (prev_branch->stub() == NULL) {
6240 
6241               LIR_Op2* prev_cmp = NULL;
6242 
6243               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6244                 prev_op = instructions->at(j);
6245                 if (prev_op->code() == lir_cmp) {
6246                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6247                   prev_cmp = (LIR_Op2*)prev_op;
6248                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6249                 }
6250               }
6251               assert(prev_cmp != NULL, "should have found comp instruction for branch");
6252               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6253 
6254                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6255 
6256                 // eliminate a conditional branch to the immediate successor
6257                 prev_branch->change_block(last_branch->block());
6258                 prev_branch->negate_cond();
6259                 prev_cmp->set_condition(prev_branch->cond());
6260                 instructions->truncate(instructions->length() - 1);
6261               }
6262             }
6263           }
6264         }
6265       }
6266     }
6267   }
6268 
6269   DEBUG_ONLY(verify(code));
6270 }
6271 
6272 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6273 #ifdef ASSERT
6274   BitMap return_converted(BlockBegin::number_of_blocks());
6275   return_converted.clear();
6276 #endif
6277 
6278   for (int i = code->length() - 1; i >= 0; i--) {
6279     BlockBegin* block = code->at(i);
6280     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6281     LIR_Op*     cur_last_op = cur_instructions->last();
6282 
6283     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6284     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6285       // the block contains only a label and a return
6286       // if a predecessor ends with an unconditional jump to this block, then the jump
6287       // can be replaced with a return instruction
6288       //
6289       // Note: the original block with only a return statement cannot be deleted completely
6290       //       because the predecessors might have other (conditional) jumps to this block
6291       //       -> this may lead to unnecesary return instructions in the final code
6292 
6293       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6294       assert(block->number_of_sux() == 0 ||
6295              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6296              "blocks that end with return must not have successors");
6297 
6298       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6299       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6300 
6301       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6302         BlockBegin* pred = block->pred_at(j);
6303         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6304         LIR_Op*     pred_last_op = pred_instructions->last();
6305 
6306         if (pred_last_op->code() == lir_branch) {
6307           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6308           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6309 
6310           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6311             // replace the jump to a return with a direct return
6312             // Note: currently the edge between the blocks is not deleted
6313             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6314 #ifdef ASSERT
6315             return_converted.set_bit(pred->block_id());
6316 #endif
6317           }
6318         }
6319       }
6320     }
6321   }
6322 }
6323 
6324 
6325 #ifdef ASSERT
6326 void ControlFlowOptimizer::verify(BlockList* code) {
6327   for (int i = 0; i < code->length(); i++) {
6328     BlockBegin* block = code->at(i);
6329     LIR_OpList* instructions = block->lir()->instructions_list();
6330 
6331     int j;
6332     for (j = 0; j < instructions->length(); j++) {
6333       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6334 
6335       if (op_branch != NULL) {
6336         assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6337         assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6338       }
6339     }
6340 
6341     for (j = 0; j < block->number_of_sux() - 1; j++) {
6342       BlockBegin* sux = block->sux_at(j);
6343       assert(code->index_of(sux) != -1, "successor not valid");
6344     }
6345 
6346     for (j = 0; j < block->number_of_preds() - 1; j++) {
6347       BlockBegin* pred = block->pred_at(j);
6348       assert(code->index_of(pred) != -1, "successor not valid");
6349     }
6350   }
6351 }
6352 #endif
6353 
6354 
6355 #ifndef PRODUCT
6356 
6357 // Implementation of LinearStatistic
6358 
6359 const char* LinearScanStatistic::counter_name(int counter_idx) {
6360   switch (counter_idx) {
6361     case counter_method:          return "compiled methods";
6362     case counter_fpu_method:      return "methods using fpu";
6363     case counter_loop_method:     return "methods with loops";
6364     case counter_exception_method:return "methods with xhandler";
6365 
6366     case counter_loop:            return "loops";
6367     case counter_block:           return "blocks";
6368     case counter_loop_block:      return "blocks inside loop";
6369     case counter_exception_block: return "exception handler entries";
6370     case counter_interval:        return "intervals";
6371     case counter_fixed_interval:  return "fixed intervals";
6372     case counter_range:           return "ranges";
6373     case counter_fixed_range:     return "fixed ranges";
6374     case counter_use_pos:         return "use positions";
6375     case counter_fixed_use_pos:   return "fixed use positions";
6376     case counter_spill_slots:     return "spill slots";
6377 
6378     // counter for classes of lir instructions
6379     case counter_instruction:     return "total instructions";
6380     case counter_label:           return "labels";
6381     case counter_entry:           return "method entries";
6382     case counter_return:          return "method returns";
6383     case counter_call:            return "method calls";
6384     case counter_move:            return "moves";
6385     case counter_cmp:             return "compare";
6386     case counter_cond_branch:     return "conditional branches";
6387     case counter_uncond_branch:   return "unconditional branches";
6388     case counter_stub_branch:     return "branches to stub";
6389     case counter_alu:             return "artithmetic + logic";
6390     case counter_alloc:           return "allocations";
6391     case counter_sync:            return "synchronisation";
6392     case counter_throw:           return "throw";
6393     case counter_unwind:          return "unwind";
6394     case counter_typecheck:       return "type+null-checks";
6395     case counter_fpu_stack:       return "fpu-stack";
6396     case counter_misc_inst:       return "other instructions";
6397     case counter_other_inst:      return "misc. instructions";
6398 
6399     // counter for different types of moves
6400     case counter_move_total:      return "total moves";
6401     case counter_move_reg_reg:    return "register->register";
6402     case counter_move_reg_stack:  return "register->stack";
6403     case counter_move_stack_reg:  return "stack->register";
6404     case counter_move_stack_stack:return "stack->stack";
6405     case counter_move_reg_mem:    return "register->memory";
6406     case counter_move_mem_reg:    return "memory->register";
6407     case counter_move_const_any:  return "constant->any";
6408 
6409     case blank_line_1:            return "";
6410     case blank_line_2:            return "";
6411 
6412     default: ShouldNotReachHere(); return "";
6413   }
6414 }
6415 
6416 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6417   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6418     return counter_method;
6419   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6420     return counter_block;
6421   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6422     return counter_instruction;
6423   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6424     return counter_move_total;
6425   }
6426   return invalid_counter;
6427 }
6428 
6429 LinearScanStatistic::LinearScanStatistic() {
6430   for (int i = 0; i < number_of_counters; i++) {
6431     _counters_sum[i] = 0;
6432     _counters_max[i] = -1;
6433   }
6434 
6435 }
6436 
6437 // add the method-local numbers to the total sum
6438 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6439   for (int i = 0; i < number_of_counters; i++) {
6440     _counters_sum[i] += method_statistic._counters_sum[i];
6441     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6442   }
6443 }
6444 
6445 void LinearScanStatistic::print(const char* title) {
6446   if (CountLinearScan || TraceLinearScanLevel > 0) {
6447     tty->cr();
6448     tty->print_cr("***** LinearScan statistic - %s *****", title);
6449 
6450     for (int i = 0; i < number_of_counters; i++) {
6451       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6452         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6453 
6454         if (base_counter(i) != invalid_counter) {
6455           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6456         } else {
6457           tty->print("           ");
6458         }
6459 
6460         if (_counters_max[i] >= 0) {
6461           tty->print("%8d", _counters_max[i]);
6462         }
6463       }
6464       tty->cr();
6465     }
6466   }
6467 }
6468 
6469 void LinearScanStatistic::collect(LinearScan* allocator) {
6470   inc_counter(counter_method);
6471   if (allocator->has_fpu_registers()) {
6472     inc_counter(counter_fpu_method);
6473   }
6474   if (allocator->num_loops() > 0) {
6475     inc_counter(counter_loop_method);
6476   }
6477   inc_counter(counter_loop, allocator->num_loops());
6478   inc_counter(counter_spill_slots, allocator->max_spills());
6479 
6480   int i;
6481   for (i = 0; i < allocator->interval_count(); i++) {
6482     Interval* cur = allocator->interval_at(i);
6483 
6484     if (cur != NULL) {
6485       inc_counter(counter_interval);
6486       inc_counter(counter_use_pos, cur->num_use_positions());
6487       if (LinearScan::is_precolored_interval(cur)) {
6488         inc_counter(counter_fixed_interval);
6489         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6490       }
6491 
6492       Range* range = cur->first();
6493       while (range != Range::end()) {
6494         inc_counter(counter_range);
6495         if (LinearScan::is_precolored_interval(cur)) {
6496           inc_counter(counter_fixed_range);
6497         }
6498         range = range->next();
6499       }
6500     }
6501   }
6502 
6503   bool has_xhandlers = false;
6504   // Note: only count blocks that are in code-emit order
6505   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6506     BlockBegin* cur = allocator->ir()->code()->at(i);
6507 
6508     inc_counter(counter_block);
6509     if (cur->loop_depth() > 0) {
6510       inc_counter(counter_loop_block);
6511     }
6512     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6513       inc_counter(counter_exception_block);
6514       has_xhandlers = true;
6515     }
6516 
6517     LIR_OpList* instructions = cur->lir()->instructions_list();
6518     for (int j = 0; j < instructions->length(); j++) {
6519       LIR_Op* op = instructions->at(j);
6520 
6521       inc_counter(counter_instruction);
6522 
6523       switch (op->code()) {
6524         case lir_label:           inc_counter(counter_label); break;
6525         case lir_std_entry:
6526         case lir_osr_entry:       inc_counter(counter_entry); break;
6527         case lir_return:          inc_counter(counter_return); break;
6528 
6529         case lir_rtcall:
6530         case lir_static_call:
6531         case lir_optvirtual_call:
6532         case lir_virtual_call:    inc_counter(counter_call); break;
6533 
6534         case lir_move: {
6535           inc_counter(counter_move);
6536           inc_counter(counter_move_total);
6537 
6538           LIR_Opr in = op->as_Op1()->in_opr();
6539           LIR_Opr res = op->as_Op1()->result_opr();
6540           if (in->is_register()) {
6541             if (res->is_register()) {
6542               inc_counter(counter_move_reg_reg);
6543             } else if (res->is_stack()) {
6544               inc_counter(counter_move_reg_stack);
6545             } else if (res->is_address()) {
6546               inc_counter(counter_move_reg_mem);
6547             } else {
6548               ShouldNotReachHere();
6549             }
6550           } else if (in->is_stack()) {
6551             if (res->is_register()) {
6552               inc_counter(counter_move_stack_reg);
6553             } else {
6554               inc_counter(counter_move_stack_stack);
6555             }
6556           } else if (in->is_address()) {
6557             assert(res->is_register(), "must be");
6558             inc_counter(counter_move_mem_reg);
6559           } else if (in->is_constant()) {
6560             inc_counter(counter_move_const_any);
6561           } else {
6562             ShouldNotReachHere();
6563           }
6564           break;
6565         }
6566 
6567         case lir_cmp:             inc_counter(counter_cmp); break;
6568 
6569         case lir_branch:
6570         case lir_cond_float_branch: {
6571           LIR_OpBranch* branch = op->as_OpBranch();
6572           if (branch->block() == NULL) {
6573             inc_counter(counter_stub_branch);
6574           } else if (branch->cond() == lir_cond_always) {
6575             inc_counter(counter_uncond_branch);
6576           } else {
6577             inc_counter(counter_cond_branch);
6578           }
6579           break;
6580         }
6581 
6582         case lir_neg:
6583         case lir_add:
6584         case lir_sub:
6585         case lir_mul:
6586         case lir_mul_strictfp:
6587         case lir_div:
6588         case lir_div_strictfp:
6589         case lir_rem:
6590         case lir_sqrt:
6591         case lir_sin:
6592         case lir_cos:
6593         case lir_abs:
6594         case lir_log10:
6595         case lir_log:
6596         case lir_pow:
6597         case lir_exp:
6598         case lir_logic_and:
6599         case lir_logic_or:
6600         case lir_logic_xor:
6601         case lir_shl:
6602         case lir_shr:
6603         case lir_ushr:            inc_counter(counter_alu); break;
6604 
6605         case lir_alloc_object:
6606         case lir_alloc_array:     inc_counter(counter_alloc); break;
6607 
6608         case lir_monaddr:
6609         case lir_lock:
6610         case lir_unlock:          inc_counter(counter_sync); break;
6611 
6612         case lir_throw:           inc_counter(counter_throw); break;
6613 
6614         case lir_unwind:          inc_counter(counter_unwind); break;
6615 
6616         case lir_null_check:
6617         case lir_leal:
6618         case lir_instanceof:
6619         case lir_checkcast:
6620         case lir_store_check:     inc_counter(counter_typecheck); break;
6621 
6622         case lir_fpop_raw:
6623         case lir_fxch:
6624         case lir_fld:             inc_counter(counter_fpu_stack); break;
6625 
6626         case lir_nop:
6627         case lir_push:
6628         case lir_pop:
6629         case lir_convert:
6630         case lir_roundfp:
6631         case lir_cmove:           inc_counter(counter_misc_inst); break;
6632 
6633         default:                  inc_counter(counter_other_inst); break;
6634       }
6635     }
6636   }
6637 
6638   if (has_xhandlers) {
6639     inc_counter(counter_exception_method);
6640   }
6641 }
6642 
6643 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6644   if (CountLinearScan || TraceLinearScanLevel > 0) {
6645 
6646     LinearScanStatistic local_statistic = LinearScanStatistic();
6647 
6648     local_statistic.collect(allocator);
6649     global_statistic.sum_up(local_statistic);
6650 
6651     if (TraceLinearScanLevel > 2) {
6652       local_statistic.print("current local statistic");
6653     }
6654   }
6655 }
6656 
6657 
6658 // Implementation of LinearTimers
6659 
6660 LinearScanTimers::LinearScanTimers() {
6661   for (int i = 0; i < number_of_timers; i++) {
6662     timer(i)->reset();
6663   }
6664 }
6665 
6666 const char* LinearScanTimers::timer_name(int idx) {
6667   switch (idx) {
6668     case timer_do_nothing:               return "Nothing (Time Check)";
6669     case timer_number_instructions:      return "Number Instructions";
6670     case timer_compute_local_live_sets:  return "Local Live Sets";
6671     case timer_compute_global_live_sets: return "Global Live Sets";
6672     case timer_build_intervals:          return "Build Intervals";
6673     case timer_sort_intervals_before:    return "Sort Intervals Before";
6674     case timer_allocate_registers:       return "Allocate Registers";
6675     case timer_resolve_data_flow:        return "Resolve Data Flow";
6676     case timer_sort_intervals_after:     return "Sort Intervals After";
6677     case timer_eliminate_spill_moves:    return "Spill optimization";
6678     case timer_assign_reg_num:           return "Assign Reg Num";
6679     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6680     case timer_optimize_lir:             return "Optimize LIR";
6681     default: ShouldNotReachHere();       return "";
6682   }
6683 }
6684 
6685 void LinearScanTimers::begin_method() {
6686   if (TimeEachLinearScan) {
6687     // reset all timers to measure only current method
6688     for (int i = 0; i < number_of_timers; i++) {
6689       timer(i)->reset();
6690     }
6691   }
6692 }
6693 
6694 void LinearScanTimers::end_method(LinearScan* allocator) {
6695   if (TimeEachLinearScan) {
6696 
6697     double c = timer(timer_do_nothing)->seconds();
6698     double total = 0;
6699     for (int i = 1; i < number_of_timers; i++) {
6700       total += timer(i)->seconds() - c;
6701     }
6702 
6703     if (total >= 0.0005) {
6704       // print all information in one line for automatic processing
6705       tty->print("@"); allocator->compilation()->method()->print_name();
6706 
6707       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6708       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6709       tty->print("@ %d ", allocator->block_count());
6710       tty->print("@ %d ", allocator->num_virtual_regs());
6711       tty->print("@ %d ", allocator->interval_count());
6712       tty->print("@ %d ", allocator->_num_calls);
6713       tty->print("@ %d ", allocator->num_loops());
6714 
6715       tty->print("@ %6.6f ", total);
6716       for (int i = 1; i < number_of_timers; i++) {
6717         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6718       }
6719       tty->cr();
6720     }
6721   }
6722 }
6723 
6724 void LinearScanTimers::print(double total_time) {
6725   if (TimeLinearScan) {
6726     // correction value: sum of dummy-timer that only measures the time that
6727     // is necesary to start and stop itself
6728     double c = timer(timer_do_nothing)->seconds();
6729 
6730     for (int i = 0; i < number_of_timers; i++) {
6731       double t = timer(i)->seconds();
6732       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6733     }
6734   }
6735 }
6736 
6737 #endif // #ifndef PRODUCT