860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
2461 _input_size_in_bits = EVEX_64bit;
2462 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, /* no_mask_reg */ true,
2463 VEX_OPCODE_0F, /* rex_w */ true);
2464 } else {
2465 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2466 }
2467 emit_int8((unsigned char)0xD6);
2468 emit_operand(src, dst);
2469 }
2470
2471 void Assembler::movsbl(Register dst, Address src) { // movsxb
2472 InstructionMark im(this);
2473 prefix(src, dst);
2474 emit_int8(0x0F);
2475 emit_int8((unsigned char)0xBE);
2476 emit_operand(dst, src);
2477 }
2478
2479 void Assembler::movsbl(Register dst, Register src) { // movsxb
2480 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2481 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2482 emit_int8(0x0F);
2483 emit_int8((unsigned char)0xBE);
2484 emit_int8((unsigned char)(0xC0 | encode));
2485 }
2486
2487 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2488 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2489 if (VM_Version::supports_evex()) {
2490 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2491 } else {
2492 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2493 }
2494 }
2495
2496 void Assembler::movsd(XMMRegister dst, Address src) {
2497 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2498 if (VM_Version::supports_evex()) {
2499 _tuple_type = EVEX_T1S;
2500 _input_size_in_bits = EVEX_64bit;
2501 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2578 }
2579
2580 void Assembler::movw(Address dst, Register src) {
2581 InstructionMark im(this);
2582 emit_int8(0x66);
2583 prefix(dst, src);
2584 emit_int8((unsigned char)0x89);
2585 emit_operand(src, dst);
2586 }
2587
2588 void Assembler::movzbl(Register dst, Address src) { // movzxb
2589 InstructionMark im(this);
2590 prefix(src, dst);
2591 emit_int8(0x0F);
2592 emit_int8((unsigned char)0xB6);
2593 emit_operand(dst, src);
2594 }
2595
2596 void Assembler::movzbl(Register dst, Register src) { // movzxb
2597 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2598 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2599 emit_int8(0x0F);
2600 emit_int8((unsigned char)0xB6);
2601 emit_int8(0xC0 | encode);
2602 }
2603
2604 void Assembler::movzwl(Register dst, Address src) { // movzxw
2605 InstructionMark im(this);
2606 prefix(src, dst);
2607 emit_int8(0x0F);
2608 emit_int8((unsigned char)0xB7);
2609 emit_operand(dst, src);
2610 }
2611
2612 void Assembler::movzwl(Register dst, Register src) { // movzxw
2613 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2614 emit_int8(0x0F);
2615 emit_int8((unsigned char)0xB7);
2616 emit_int8(0xC0 | encode);
2617 }
2618
6432 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6433 if (reg_enc >= 8) {
6434 prefix(REX_B);
6435 reg_enc -= 8;
6436 } else if (byteinst && reg_enc >= 4) {
6437 prefix(REX);
6438 }
6439 return reg_enc;
6440 }
6441
6442 int Assembler::prefixq_and_encode(int reg_enc) {
6443 if (reg_enc < 8) {
6444 prefix(REX_W);
6445 } else {
6446 prefix(REX_WB);
6447 reg_enc -= 8;
6448 }
6449 return reg_enc;
6450 }
6451
6452 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
6453 if (dst_enc < 8) {
6454 if (src_enc >= 8) {
6455 prefix(REX_B);
6456 src_enc -= 8;
6457 } else if (byteinst && src_enc >= 4) {
6458 prefix(REX);
6459 }
6460 } else {
6461 if (src_enc < 8) {
6462 prefix(REX_R);
6463 } else {
6464 prefix(REX_RB);
6465 src_enc -= 8;
6466 }
6467 dst_enc -= 8;
6468 }
6469 return dst_enc << 3 | src_enc;
6470 }
6471
6472 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6473 if (dst_enc < 8) {
6474 if (src_enc < 8) {
6475 prefix(REX_W);
6476 } else {
6477 prefix(REX_WB);
|
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 int vex_opcode;
881 // First byte
882 if ((0xFF & *inst) == VEX_3bytes) {
883 vex_opcode = VEX_OPCODE_MASK & *ip;
884 ip++; // third byte
885 is_64bit = ((VEX_W & *ip) == VEX_W);
886 } else {
887 vex_opcode = VEX_OPCODE_0F;
888 }
889 ip++; // opcode
890 // To find the end of instruction (which == end_pc_operand).
891 switch (vex_opcode) {
892 case VEX_OPCODE_0F:
893 switch (0xFF & *ip) {
894 case 0x70: // pshufd r, r/a, #8
895 case 0x71: // ps[rl|ra|ll]w r, #8
896 case 0x72: // ps[rl|ra|ll]d r, #8
897 case 0x73: // ps[rl|ra|ll]q r, #8
898 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
899 case 0xC4: // pinsrw r, r, r/a, #8
900 case 0xC5: // pextrw r/a, r, #8
901 case 0xC6: // shufp[s|d] r, r, r/a, #8
902 tail_size = 1; // the imm8
903 break;
904 }
905 break;
906 case VEX_OPCODE_0F_3A:
907 tail_size = 1;
908 break;
909 }
910 ip++; // skip opcode
911 debug_only(has_disp32 = true); // has both kinds of operands!
912 break;
913
914 case 0x62: // EVEX_4bytes
915 assert((UseAVX > 0), "shouldn't have EVEX prefix");
916 assert(ip == inst+1, "no prefixes allowed");
917 // no EVEX collisions, all instructions that have 0x62 opcodes
918 // have EVEX versions and are subopcodes of 0x66
919 ip++; // skip P0 and exmaine W in P1
920 is_64bit = ((VEX_W & *ip) == VEX_W);
921 ip++; // move to P2
922 ip++; // skip P2, move to opcode
923 // To find the end of instruction (which == end_pc_operand).
924 switch (0xFF & *ip) {
925 case 0x61: // pcmpestri r, r/a, #8
926 case 0x70: // pshufd r, r/a, #8
927 case 0x73: // psrldq r, #8
2475 _input_size_in_bits = EVEX_64bit;
2476 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, /* no_mask_reg */ true,
2477 VEX_OPCODE_0F, /* rex_w */ true);
2478 } else {
2479 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2480 }
2481 emit_int8((unsigned char)0xD6);
2482 emit_operand(src, dst);
2483 }
2484
2485 void Assembler::movsbl(Register dst, Address src) { // movsxb
2486 InstructionMark im(this);
2487 prefix(src, dst);
2488 emit_int8(0x0F);
2489 emit_int8((unsigned char)0xBE);
2490 emit_operand(dst, src);
2491 }
2492
2493 void Assembler::movsbl(Register dst, Register src) { // movsxb
2494 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2495 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2496 emit_int8(0x0F);
2497 emit_int8((unsigned char)0xBE);
2498 emit_int8((unsigned char)(0xC0 | encode));
2499 }
2500
2501 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2502 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2503 if (VM_Version::supports_evex()) {
2504 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2505 } else {
2506 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2507 }
2508 }
2509
2510 void Assembler::movsd(XMMRegister dst, Address src) {
2511 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2512 if (VM_Version::supports_evex()) {
2513 _tuple_type = EVEX_T1S;
2514 _input_size_in_bits = EVEX_64bit;
2515 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2592 }
2593
2594 void Assembler::movw(Address dst, Register src) {
2595 InstructionMark im(this);
2596 emit_int8(0x66);
2597 prefix(dst, src);
2598 emit_int8((unsigned char)0x89);
2599 emit_operand(src, dst);
2600 }
2601
2602 void Assembler::movzbl(Register dst, Address src) { // movzxb
2603 InstructionMark im(this);
2604 prefix(src, dst);
2605 emit_int8(0x0F);
2606 emit_int8((unsigned char)0xB6);
2607 emit_operand(dst, src);
2608 }
2609
2610 void Assembler::movzbl(Register dst, Register src) { // movzxb
2611 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2612 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2613 emit_int8(0x0F);
2614 emit_int8((unsigned char)0xB6);
2615 emit_int8(0xC0 | encode);
2616 }
2617
2618 void Assembler::movzwl(Register dst, Address src) { // movzxw
2619 InstructionMark im(this);
2620 prefix(src, dst);
2621 emit_int8(0x0F);
2622 emit_int8((unsigned char)0xB7);
2623 emit_operand(dst, src);
2624 }
2625
2626 void Assembler::movzwl(Register dst, Register src) { // movzxw
2627 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2628 emit_int8(0x0F);
2629 emit_int8((unsigned char)0xB7);
2630 emit_int8(0xC0 | encode);
2631 }
2632
6446 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6447 if (reg_enc >= 8) {
6448 prefix(REX_B);
6449 reg_enc -= 8;
6450 } else if (byteinst && reg_enc >= 4) {
6451 prefix(REX);
6452 }
6453 return reg_enc;
6454 }
6455
6456 int Assembler::prefixq_and_encode(int reg_enc) {
6457 if (reg_enc < 8) {
6458 prefix(REX_W);
6459 } else {
6460 prefix(REX_WB);
6461 reg_enc -= 8;
6462 }
6463 return reg_enc;
6464 }
6465
6466 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6467 if (dst_enc < 8) {
6468 if (src_enc >= 8) {
6469 prefix(REX_B);
6470 src_enc -= 8;
6471 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6472 prefix(REX);
6473 }
6474 } else {
6475 if (src_enc < 8) {
6476 prefix(REX_R);
6477 } else {
6478 prefix(REX_RB);
6479 src_enc -= 8;
6480 }
6481 dst_enc -= 8;
6482 }
6483 return dst_enc << 3 | src_enc;
6484 }
6485
6486 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6487 if (dst_enc < 8) {
6488 if (src_enc < 8) {
6489 prefix(REX_W);
6490 } else {
6491 prefix(REX_WB);
|