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src/cpu/x86/vm/assembler_x86.hpp

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*** 534,544 **** enum VexOpcode { VEX_OPCODE_NONE = 0x0, VEX_OPCODE_0F = 0x1, VEX_OPCODE_0F_38 = 0x2, ! VEX_OPCODE_0F_3A = 0x3 }; enum AvxVectorLen { AVX_128bit = 0x0, AVX_256bit = 0x1, --- 534,545 ---- enum VexOpcode { VEX_OPCODE_NONE = 0x0, VEX_OPCODE_0F = 0x1, VEX_OPCODE_0F_38 = 0x2, ! VEX_OPCODE_0F_3A = 0x3, ! VEX_OPCODE_MASK = 0x1F }; enum AvxVectorLen { AVX_128bit = 0x0, AVX_256bit = 0x1,
*** 610,620 **** // 64bit prefixes int prefix_and_encode(int reg_enc, bool byteinst = false); int prefixq_and_encode(int reg_enc); ! int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); int prefixq_and_encode(int dst_enc, int src_enc); void prefix(Register reg); void prefix(Register dst, Register src, Prefix p); void prefix(Register dst, Address adr, Prefix p); --- 611,624 ---- // 64bit prefixes int prefix_and_encode(int reg_enc, bool byteinst = false); int prefixq_and_encode(int reg_enc); ! int prefix_and_encode(int dst_enc, int src_enc) { ! return prefix_and_encode(dst_enc, false, src_enc, false); ! } ! int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); int prefixq_and_encode(int dst_enc, int src_enc); void prefix(Register reg); void prefix(Register dst, Register src, Prefix p); void prefix(Register dst, Address adr, Prefix p);
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