1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument VALUE_OBJ_CLASS_SPEC {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address VALUE_OBJ_CLASS_SPEC {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   ScaleFactor      _scale;
 188   int              _disp;
 189   RelocationHolder _rspec;
 190 
 191   // Easily misused constructors make them private
 192   // %%% can we make these go away?
 193   NOT_LP64(Address(address loc, RelocationHolder spec);)
 194   Address(int disp, address loc, relocInfo::relocType rtype);
 195   Address(int disp, address loc, RelocationHolder spec);
 196 
 197  public:
 198 
 199  int disp() { return _disp; }
 200   // creation
 201   Address()
 202     : _base(noreg),
 203       _index(noreg),
 204       _scale(no_scale),
 205       _disp(0) {
 206   }
 207 
 208   // No default displacement otherwise Register can be implicitly
 209   // converted to 0(Register) which is quite a different animal.
 210 
 211   Address(Register base, int disp)
 212     : _base(base),
 213       _index(noreg),
 214       _scale(no_scale),
 215       _disp(disp) {
 216   }
 217 
 218   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 219     : _base (base),
 220       _index(index),
 221       _scale(scale),
 222       _disp (disp) {
 223     assert(!index->is_valid() == (scale == Address::no_scale),
 224            "inconsistent address");
 225   }
 226 
 227   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 228     : _base (base),
 229       _index(index.register_or_noreg()),
 230       _scale(scale),
 231       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 232     if (!index.is_register())  scale = Address::no_scale;
 233     assert(!_index->is_valid() == (scale == Address::no_scale),
 234            "inconsistent address");
 235   }
 236 
 237   Address plus_disp(int disp) const {
 238     Address a = (*this);
 239     a._disp += disp;
 240     return a;
 241   }
 242   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 243     Address a = (*this);
 244     a._disp += disp.constant_or_zero() * scale_size(scale);
 245     if (disp.is_register()) {
 246       assert(!a.index()->is_valid(), "competing indexes");
 247       a._index = disp.as_register();
 248       a._scale = scale;
 249     }
 250     return a;
 251   }
 252   bool is_same_address(Address a) const {
 253     // disregard _rspec
 254     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 255   }
 256 
 257   // The following two overloads are used in connection with the
 258   // ByteSize type (see sizes.hpp).  They simplify the use of
 259   // ByteSize'd arguments in assembly code. Note that their equivalent
 260   // for the optimized build are the member functions with int disp
 261   // argument since ByteSize is mapped to an int type in that case.
 262   //
 263   // Note: DO NOT introduce similar overloaded functions for WordSize
 264   // arguments as in the optimized mode, both ByteSize and WordSize
 265   // are mapped to the same type and thus the compiler cannot make a
 266   // distinction anymore (=> compiler errors).
 267 
 268 #ifdef ASSERT
 269   Address(Register base, ByteSize disp)
 270     : _base(base),
 271       _index(noreg),
 272       _scale(no_scale),
 273       _disp(in_bytes(disp)) {
 274   }
 275 
 276   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 277     : _base(base),
 278       _index(index),
 279       _scale(scale),
 280       _disp(in_bytes(disp)) {
 281     assert(!index->is_valid() == (scale == Address::no_scale),
 282            "inconsistent address");
 283   }
 284 
 285   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 286     : _base (base),
 287       _index(index.register_or_noreg()),
 288       _scale(scale),
 289       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 290     if (!index.is_register())  scale = Address::no_scale;
 291     assert(!_index->is_valid() == (scale == Address::no_scale),
 292            "inconsistent address");
 293   }
 294 
 295 #endif // ASSERT
 296 
 297   // accessors
 298   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 299   Register    base()             const { return _base;  }
 300   Register    index()            const { return _index; }
 301   ScaleFactor scale()            const { return _scale; }
 302   int         disp()             const { return _disp;  }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base != noreg && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index != noreg &&_index->encoding() >= 8;
 318   }
 319 
 320   relocInfo::relocType reloc() const { return _rspec.type(); }
 321 
 322   friend class Assembler;
 323   friend class MacroAssembler;
 324   friend class LIR_Assembler; // base/index/scale/disp
 325 };
 326 
 327 //
 328 // AddressLiteral has been split out from Address because operands of this type
 329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 330 // the few instructions that need to deal with address literals are unique and the
 331 // MacroAssembler does not have to implement every instruction in the Assembler
 332 // in order to search for address literals that may need special handling depending
 333 // on the instruction and the platform. As small step on the way to merging i486/amd64
 334 // directories.
 335 //
 336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 337   friend class ArrayAddress;
 338   RelocationHolder _rspec;
 339   // Typically we use AddressLiterals we want to use their rval
 340   // However in some situations we want the lval (effect address) of the item.
 341   // We provide a special factory for making those lvals.
 342   bool _is_lval;
 343 
 344   // If the target is far we'll need to load the ea of this to
 345   // a register to reach it. Otherwise if near we can do rip
 346   // relative addressing.
 347 
 348   address          _target;
 349 
 350  protected:
 351   // creation
 352   AddressLiteral()
 353     : _is_lval(false),
 354       _target(NULL)
 355   {}
 356 
 357   public:
 358 
 359 
 360   AddressLiteral(address target, relocInfo::relocType rtype);
 361 
 362   AddressLiteral(address target, RelocationHolder const& rspec)
 363     : _rspec(rspec),
 364       _is_lval(false),
 365       _target(target)
 366   {}
 367 
 368   AddressLiteral addr() {
 369     AddressLiteral ret = *this;
 370     ret._is_lval = true;
 371     return ret;
 372   }
 373 
 374 
 375  private:
 376 
 377   address target() { return _target; }
 378   bool is_lval() { return _is_lval; }
 379 
 380   relocInfo::relocType reloc() const { return _rspec.type(); }
 381   const RelocationHolder& rspec() const { return _rspec; }
 382 
 383   friend class Assembler;
 384   friend class MacroAssembler;
 385   friend class Address;
 386   friend class LIR_Assembler;
 387 };
 388 
 389 // Convience classes
 390 class RuntimeAddress: public AddressLiteral {
 391 
 392   public:
 393 
 394   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 395 
 396 };
 397 
 398 class ExternalAddress: public AddressLiteral {
 399  private:
 400   static relocInfo::relocType reloc_for_target(address target) {
 401     // Sometimes ExternalAddress is used for values which aren't
 402     // exactly addresses, like the card table base.
 403     // external_word_type can't be used for values in the first page
 404     // so just skip the reloc in that case.
 405     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 406   }
 407 
 408  public:
 409 
 410   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 411 
 412 };
 413 
 414 class InternalAddress: public AddressLiteral {
 415 
 416   public:
 417 
 418   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 419 
 420 };
 421 
 422 // x86 can do array addressing as a single operation since disp can be an absolute
 423 // address amd64 can't. We create a class that expresses the concept but does extra
 424 // magic on amd64 to get the final result
 425 
 426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 427   private:
 428 
 429   AddressLiteral _base;
 430   Address        _index;
 431 
 432   public:
 433 
 434   ArrayAddress() {};
 435   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 436   AddressLiteral base() { return _base; }
 437   Address index() { return _index; }
 438 
 439 };
 440 
 441 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 442 // See fxsave and xsave(EVEX enabled) documentation for layout
 443 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 444 
 445 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 446 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 447 // is what you get. The Assembler is generating code into a CodeBuffer.
 448 
 449 class Assembler : public AbstractAssembler  {
 450   friend class AbstractAssembler; // for the non-virtual hack
 451   friend class LIR_Assembler; // as_Address()
 452   friend class StubGenerator;
 453 
 454  public:
 455   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 456     zero          = 0x4,
 457     notZero       = 0x5,
 458     equal         = 0x4,
 459     notEqual      = 0x5,
 460     less          = 0xc,
 461     lessEqual     = 0xe,
 462     greater       = 0xf,
 463     greaterEqual  = 0xd,
 464     below         = 0x2,
 465     belowEqual    = 0x6,
 466     above         = 0x7,
 467     aboveEqual    = 0x3,
 468     overflow      = 0x0,
 469     noOverflow    = 0x1,
 470     carrySet      = 0x2,
 471     carryClear    = 0x3,
 472     negative      = 0x8,
 473     positive      = 0x9,
 474     parity        = 0xa,
 475     noParity      = 0xb
 476   };
 477 
 478   enum Prefix {
 479     // segment overrides
 480     CS_segment = 0x2e,
 481     SS_segment = 0x36,
 482     DS_segment = 0x3e,
 483     ES_segment = 0x26,
 484     FS_segment = 0x64,
 485     GS_segment = 0x65,
 486 
 487     REX        = 0x40,
 488 
 489     REX_B      = 0x41,
 490     REX_X      = 0x42,
 491     REX_XB     = 0x43,
 492     REX_R      = 0x44,
 493     REX_RB     = 0x45,
 494     REX_RX     = 0x46,
 495     REX_RXB    = 0x47,
 496 
 497     REX_W      = 0x48,
 498 
 499     REX_WB     = 0x49,
 500     REX_WX     = 0x4A,
 501     REX_WXB    = 0x4B,
 502     REX_WR     = 0x4C,
 503     REX_WRB    = 0x4D,
 504     REX_WRX    = 0x4E,
 505     REX_WRXB   = 0x4F,
 506 
 507     VEX_3bytes = 0xC4,
 508     VEX_2bytes = 0xC5,
 509     EVEX_4bytes = 0x62,
 510     Prefix_EMPTY = 0x0
 511   };
 512 
 513   enum VexPrefix {
 514     VEX_B = 0x20,
 515     VEX_X = 0x40,
 516     VEX_R = 0x80,
 517     VEX_W = 0x80
 518   };
 519 
 520   enum ExexPrefix {
 521     EVEX_F  = 0x04,
 522     EVEX_V  = 0x08,
 523     EVEX_Rb = 0x10,
 524     EVEX_X  = 0x40,
 525     EVEX_Z  = 0x80
 526   };
 527 
 528   enum VexSimdPrefix {
 529     VEX_SIMD_NONE = 0x0,
 530     VEX_SIMD_66   = 0x1,
 531     VEX_SIMD_F3   = 0x2,
 532     VEX_SIMD_F2   = 0x3
 533   };
 534 
 535   enum VexOpcode {
 536     VEX_OPCODE_NONE  = 0x0,
 537     VEX_OPCODE_0F    = 0x1,
 538     VEX_OPCODE_0F_38 = 0x2,
 539     VEX_OPCODE_0F_3A = 0x3

 540   };
 541 
 542   enum AvxVectorLen {
 543     AVX_128bit = 0x0,
 544     AVX_256bit = 0x1,
 545     AVX_512bit = 0x2,
 546     AVX_NoVec  = 0x4
 547   };
 548 
 549   enum EvexTupleType {
 550     EVEX_FV   = 0,
 551     EVEX_HV   = 4,
 552     EVEX_FVM  = 6,
 553     EVEX_T1S  = 7,
 554     EVEX_T1F  = 11,
 555     EVEX_T2   = 13,
 556     EVEX_T4   = 15,
 557     EVEX_T8   = 17,
 558     EVEX_HVM  = 18,
 559     EVEX_QVM  = 19,
 560     EVEX_OVM  = 20,
 561     EVEX_M128 = 21,
 562     EVEX_DUP  = 22,
 563     EVEX_ETUP = 23
 564   };
 565 
 566   enum EvexInputSizeInBits {
 567     EVEX_8bit  = 0,
 568     EVEX_16bit = 1,
 569     EVEX_32bit = 2,
 570     EVEX_64bit = 3
 571   };
 572 
 573   enum WhichOperand {
 574     // input to locate_operand, and format code for relocations
 575     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 576     disp32_operand = 1,          // embedded 32-bit displacement or address
 577     call32_operand = 2,          // embedded 32-bit self-relative displacement
 578 #ifndef _LP64
 579     _WhichOperand_limit = 3
 580 #else
 581      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 582     _WhichOperand_limit = 4
 583 #endif
 584   };
 585 
 586 
 587 
 588   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 589   // of instructions are freely declared without the need for wrapping them an ifdef.
 590   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 591   // In the .cpp file the implementations are wrapped so that they are dropped out
 592   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 593   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 594   //
 595   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 596   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 597 
 598 private:
 599 
 600   int _evex_encoding;
 601   int _input_size_in_bits;
 602   int _avx_vector_len;
 603   int _tuple_type;
 604   bool _is_evex_instruction;
 605   bool _legacy_mode_bw;
 606   bool _legacy_mode_dq;
 607   bool _legacy_mode_vl;
 608   bool _legacy_mode_vlbw;
 609   bool _instruction_uses_vl;
 610 
 611   // 64bit prefixes
 612   int prefix_and_encode(int reg_enc, bool byteinst = false);
 613   int prefixq_and_encode(int reg_enc);
 614 
 615   int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);



 616   int prefixq_and_encode(int dst_enc, int src_enc);
 617 
 618   void prefix(Register reg);
 619   void prefix(Register dst, Register src, Prefix p);
 620   void prefix(Register dst, Address adr, Prefix p);
 621   void prefix(Address adr);
 622   void prefixq(Address adr);
 623 
 624   void prefix(Address adr, Register reg,  bool byteinst = false);
 625   void prefix(Address adr, XMMRegister reg);
 626   void prefixq(Address adr, Register reg);
 627   void prefixq(Address adr, XMMRegister reg);
 628 
 629   void prefetch_prefix(Address src);
 630 
 631   void rex_prefix(Address adr, XMMRegister xreg,
 632                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 633   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 634                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 635 
 636   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
 637                   int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 638                   int vector_len);
 639 
 640   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
 641                    int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 642                    bool is_extended_context, bool is_merge_context,
 643                    int vector_len, bool no_mask_reg );
 644 
 645   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 646                   VexSimdPrefix pre, VexOpcode opc,
 647                   bool vex_w, int vector_len,
 648                   bool legacy_mode = false, bool no_mask_reg = false);
 649 
 650   void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
 651                   VexSimdPrefix pre, int vector_len = AVX_128bit,
 652                   bool no_mask_reg = false, bool legacy_mode = false) {
 653     int dst_enc = dst->encoding();
 654     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 655     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector_len, legacy_mode, no_mask_reg);
 656   }
 657 
 658   void vex_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 659                     VexSimdPrefix pre, int vector_len = AVX_128bit,
 660                     bool no_mask_reg = false) {
 661     int dst_enc = dst->encoding();
 662     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 663     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
 664   }
 665 
 666   void vex_prefix_0F38(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 667     bool vex_w = false;
 668     int vector_len = AVX_128bit;
 669     vex_prefix(src, nds->encoding(), dst->encoding(),
 670                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 671                vector_len, no_mask_reg);
 672   }
 673 
 674   void vex_prefix_0F38_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 675     bool vex_w = false;
 676     int vector_len = AVX_128bit;
 677     vex_prefix(src, nds->encoding(), dst->encoding(),
 678                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 679                vector_len, true, no_mask_reg);
 680   }
 681 
 682   void vex_prefix_0F38_q(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 683     bool vex_w = true;
 684     int vector_len = AVX_128bit;
 685     vex_prefix(src, nds->encoding(), dst->encoding(),
 686                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 687                vector_len, no_mask_reg);
 688   }
 689 
 690   void vex_prefix_0F38_q_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 691     bool vex_w = true;
 692     int vector_len = AVX_128bit;
 693     vex_prefix(src, nds->encoding(), dst->encoding(),
 694                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 695                vector_len, true, no_mask_reg);
 696   }
 697 
 698   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 699                              VexSimdPrefix pre, VexOpcode opc,
 700                              bool vex_w, int vector_len,
 701                              bool legacy_mode, bool no_mask_reg);
 702 
 703   int  vex_prefix_0F38_and_encode(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 704     bool vex_w = false;
 705     int vector_len = AVX_128bit;
 706     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 707                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 708                                  false, no_mask_reg);
 709   }
 710 
 711   int  vex_prefix_0F38_and_encode_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 712     bool vex_w = false;
 713     int vector_len = AVX_128bit;
 714     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 715       VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 716       true, no_mask_reg);
 717   }
 718 
 719   int  vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 720     bool vex_w = true;
 721     int vector_len = AVX_128bit;
 722     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 723                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 724                                  false, no_mask_reg);
 725   }
 726 
 727   int  vex_prefix_0F38_and_encode_q_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 728     bool vex_w = true;
 729     int vector_len = AVX_128bit;
 730     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 731                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 732                                  true, no_mask_reg);
 733   }
 734 
 735   int  vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 736                              VexSimdPrefix pre, int vector_len = AVX_128bit,
 737                              VexOpcode opc = VEX_OPCODE_0F, bool legacy_mode = false,
 738                              bool no_mask_reg = false) {
 739     int src_enc = src->encoding();
 740     int dst_enc = dst->encoding();
 741     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 742     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector_len, legacy_mode, no_mask_reg);
 743   }
 744 
 745   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
 746                    VexSimdPrefix pre, bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F,
 747                    bool rex_w = false, int vector_len = AVX_128bit, bool legacy_mode = false);
 748 
 749   void simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre,
 750                    bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F) {
 751     simd_prefix(dst, xnoreg, src, pre, no_mask_reg, opc);
 752   }
 753 
 754   void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
 755     simd_prefix(src, dst, pre, no_mask_reg);
 756   }
 757   void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 758                      VexSimdPrefix pre, bool no_mask_reg = false) {
 759     bool rex_w = true;
 760     simd_prefix(dst, nds, src, pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
 761   }
 762 
 763   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 764                              VexSimdPrefix pre, bool no_mask_reg,
 765                              VexOpcode opc = VEX_OPCODE_0F,
 766                              bool rex_w = false, int vector_len = AVX_128bit,
 767                              bool legacy_mode = false);
 768 
 769   int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src,
 770                              VexSimdPrefix pre, bool no_mask_reg,
 771                              VexOpcode opc = VEX_OPCODE_0F,
 772                              bool rex_w = false, int vector_len = AVX_128bit);
 773 
 774   int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src,
 775                              VexSimdPrefix pre, bool no_mask_reg,
 776                              VexOpcode opc = VEX_OPCODE_0F,
 777                              bool rex_w = false, int vector_len = AVX_128bit);
 778 
 779   // Move/convert 32-bit integer value.
 780   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
 781                              VexSimdPrefix pre, bool no_mask_reg) {
 782     // It is OK to cast from Register to XMMRegister to pass argument here
 783     // since only encoding is used in simd_prefix_and_encode() and number of
 784     // Gen and Xmm registers are the same.
 785     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F);
 786   }
 787   int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
 788     return simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg);
 789   }
 790   int simd_prefix_and_encode(Register dst, XMMRegister src,
 791                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 792                              bool no_mask_reg = false) {
 793     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc);
 794   }
 795 
 796   // Move/convert 64-bit integer value.
 797   int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
 798                                VexSimdPrefix pre, bool no_mask_reg = false) {
 799     bool rex_w = true;
 800     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
 801   }
 802   int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
 803     return simd_prefix_and_encode_q(dst, xnoreg, src, pre, no_mask_reg);
 804   }
 805   int simd_prefix_and_encode_q(Register dst, XMMRegister src,
 806                                VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 807                                bool no_mask_reg = false) {
 808     bool rex_w = true;
 809     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc, rex_w);
 810   }
 811 
 812   // Helper functions for groups of instructions
 813   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 814 
 815   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 816   // Force generation of a 4 byte immediate value even if it fits into 8bit
 817   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 818   void emit_arith(int op1, int op2, Register dst, Register src);
 819 
 820   void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 821   void emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 822   void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 823   void emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
 824   void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 825   void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 826   void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 827   void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
 828   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 829                       Address src, VexSimdPrefix pre, int vector_len,
 830                       bool no_mask_reg = false, bool legacy_mode = false);
 831   void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
 832                         Address src, VexSimdPrefix pre, int vector_len,
 833                         bool no_mask_reg = false);
 834   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 835                       XMMRegister src, VexSimdPrefix pre, int vector_len,
 836                       bool no_mask_reg = false, bool legacy_mode = false);
 837   void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
 838                         XMMRegister src, VexSimdPrefix pre, int vector_len,
 839                         bool no_mask_reg = false);
 840 
 841   bool emit_compressed_disp_byte(int &disp);
 842 
 843   void emit_operand(Register reg,
 844                     Register base, Register index, Address::ScaleFactor scale,
 845                     int disp,
 846                     RelocationHolder const& rspec,
 847                     int rip_relative_correction = 0);
 848 
 849   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 850 
 851   // operands that only take the original 32bit registers
 852   void emit_operand32(Register reg, Address adr);
 853 
 854   void emit_operand(XMMRegister reg,
 855                     Register base, Register index, Address::ScaleFactor scale,
 856                     int disp,
 857                     RelocationHolder const& rspec);
 858 
 859   void emit_operand(XMMRegister reg, Address adr);
 860 
 861   void emit_operand(MMXRegister reg, Address adr);
 862 
 863   // workaround gcc (3.2.1-7) bug
 864   void emit_operand(Address adr, MMXRegister reg);
 865 
 866 
 867   // Immediate-to-memory forms
 868   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 869 
 870   void emit_farith(int b1, int b2, int i);
 871 
 872 
 873  protected:
 874   #ifdef ASSERT
 875   void check_relocation(RelocationHolder const& rspec, int format);
 876   #endif
 877 
 878   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 879   void emit_data(jint data, RelocationHolder const& rspec, int format);
 880   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 881   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 882 
 883   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 884 
 885   // These are all easily abused and hence protected
 886 
 887   // 32BIT ONLY SECTION
 888 #ifndef _LP64
 889   // Make these disappear in 64bit mode since they would never be correct
 890   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 891   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 892 
 893   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 894   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 895 
 896   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 897 #else
 898   // 64BIT ONLY SECTION
 899   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 900 
 901   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 902   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 903 
 904   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 905   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 906 #endif // _LP64
 907 
 908   // These are unique in that we are ensured by the caller that the 32bit
 909   // relative in these instructions will always be able to reach the potentially
 910   // 64bit address described by entry. Since they can take a 64bit address they
 911   // don't have the 32 suffix like the other instructions in this class.
 912 
 913   void call_literal(address entry, RelocationHolder const& rspec);
 914   void jmp_literal(address entry, RelocationHolder const& rspec);
 915 
 916   // Avoid using directly section
 917   // Instructions in this section are actually usable by anyone without danger
 918   // of failure but have performance issues that are addressed my enhanced
 919   // instructions which will do the proper thing base on the particular cpu.
 920   // We protect them because we don't trust you...
 921 
 922   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 923   // could cause a partial flag stall since they don't set CF flag.
 924   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 925   // which call inc() & dec() or add() & sub() in accordance with
 926   // the product flag UseIncDec value.
 927 
 928   void decl(Register dst);
 929   void decl(Address dst);
 930   void decq(Register dst);
 931   void decq(Address dst);
 932 
 933   void incl(Register dst);
 934   void incl(Address dst);
 935   void incq(Register dst);
 936   void incq(Address dst);
 937 
 938   // New cpus require use of movsd and movss to avoid partial register stall
 939   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 940   // The selection is done in MacroAssembler::movdbl() and movflt().
 941 
 942   // Move Scalar Single-Precision Floating-Point Values
 943   void movss(XMMRegister dst, Address src);
 944   void movss(XMMRegister dst, XMMRegister src);
 945   void movss(Address dst, XMMRegister src);
 946 
 947   // Move Scalar Double-Precision Floating-Point Values
 948   void movsd(XMMRegister dst, Address src);
 949   void movsd(XMMRegister dst, XMMRegister src);
 950   void movsd(Address dst, XMMRegister src);
 951   void movlpd(XMMRegister dst, Address src);
 952 
 953   // New cpus require use of movaps and movapd to avoid partial register stall
 954   // when moving between registers.
 955   void movaps(XMMRegister dst, XMMRegister src);
 956   void movapd(XMMRegister dst, XMMRegister src);
 957 
 958   // End avoid using directly
 959 
 960 
 961   // Instruction prefixes
 962   void prefix(Prefix p);
 963 
 964   public:
 965 
 966   // Creation
 967   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 968     init_attributes();
 969   }
 970 
 971   // Decoding
 972   static address locate_operand(address inst, WhichOperand which);
 973   static address locate_next_instruction(address inst);
 974 
 975   // Utilities
 976   static bool is_polling_page_far() NOT_LP64({ return false;});
 977   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 978                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 979 
 980   // Generic instructions
 981   // Does 32bit or 64bit as needed for the platform. In some sense these
 982   // belong in macro assembler but there is no need for both varieties to exist
 983 
 984   void init_attributes(void) {
 985     _evex_encoding = 0;
 986     _input_size_in_bits = 0;
 987     _avx_vector_len = AVX_NoVec;
 988     _tuple_type = EVEX_ETUP;
 989     _is_evex_instruction = false;
 990     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 991     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 992     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 993     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 994     _instruction_uses_vl = false;
 995   }
 996 
 997   void lea(Register dst, Address src);
 998 
 999   void mov(Register dst, Register src);
1000 
1001   void pusha();
1002   void popa();
1003 
1004   void pushf();
1005   void popf();
1006 
1007   void push(int32_t imm32);
1008 
1009   void push(Register src);
1010 
1011   void pop(Register dst);
1012 
1013   // These are dummies to prevent surprise implicit conversions to Register
1014   void push(void* v);
1015   void pop(void* v);
1016 
1017   // These do register sized moves/scans
1018   void rep_mov();
1019   void rep_stos();
1020   void rep_stosb();
1021   void repne_scan();
1022 #ifdef _LP64
1023   void repne_scanl();
1024 #endif
1025 
1026   // Vanilla instructions in lexical order
1027 
1028   void adcl(Address dst, int32_t imm32);
1029   void adcl(Address dst, Register src);
1030   void adcl(Register dst, int32_t imm32);
1031   void adcl(Register dst, Address src);
1032   void adcl(Register dst, Register src);
1033 
1034   void adcq(Register dst, int32_t imm32);
1035   void adcq(Register dst, Address src);
1036   void adcq(Register dst, Register src);
1037 
1038   void addl(Address dst, int32_t imm32);
1039   void addl(Address dst, Register src);
1040   void addl(Register dst, int32_t imm32);
1041   void addl(Register dst, Address src);
1042   void addl(Register dst, Register src);
1043 
1044   void addq(Address dst, int32_t imm32);
1045   void addq(Address dst, Register src);
1046   void addq(Register dst, int32_t imm32);
1047   void addq(Register dst, Address src);
1048   void addq(Register dst, Register src);
1049 
1050 #ifdef _LP64
1051  //Add Unsigned Integers with Carry Flag
1052   void adcxq(Register dst, Register src);
1053 
1054  //Add Unsigned Integers with Overflow Flag
1055   void adoxq(Register dst, Register src);
1056 #endif
1057 
1058   void addr_nop_4();
1059   void addr_nop_5();
1060   void addr_nop_7();
1061   void addr_nop_8();
1062 
1063   // Add Scalar Double-Precision Floating-Point Values
1064   void addsd(XMMRegister dst, Address src);
1065   void addsd(XMMRegister dst, XMMRegister src);
1066 
1067   // Add Scalar Single-Precision Floating-Point Values
1068   void addss(XMMRegister dst, Address src);
1069   void addss(XMMRegister dst, XMMRegister src);
1070 
1071   // AES instructions
1072   void aesdec(XMMRegister dst, Address src);
1073   void aesdec(XMMRegister dst, XMMRegister src);
1074   void aesdeclast(XMMRegister dst, Address src);
1075   void aesdeclast(XMMRegister dst, XMMRegister src);
1076   void aesenc(XMMRegister dst, Address src);
1077   void aesenc(XMMRegister dst, XMMRegister src);
1078   void aesenclast(XMMRegister dst, Address src);
1079   void aesenclast(XMMRegister dst, XMMRegister src);
1080 
1081 
1082   void andl(Address  dst, int32_t imm32);
1083   void andl(Register dst, int32_t imm32);
1084   void andl(Register dst, Address src);
1085   void andl(Register dst, Register src);
1086 
1087   void andq(Address  dst, int32_t imm32);
1088   void andq(Register dst, int32_t imm32);
1089   void andq(Register dst, Address src);
1090   void andq(Register dst, Register src);
1091 
1092   // BMI instructions
1093   void andnl(Register dst, Register src1, Register src2);
1094   void andnl(Register dst, Register src1, Address src2);
1095   void andnq(Register dst, Register src1, Register src2);
1096   void andnq(Register dst, Register src1, Address src2);
1097 
1098   void blsil(Register dst, Register src);
1099   void blsil(Register dst, Address src);
1100   void blsiq(Register dst, Register src);
1101   void blsiq(Register dst, Address src);
1102 
1103   void blsmskl(Register dst, Register src);
1104   void blsmskl(Register dst, Address src);
1105   void blsmskq(Register dst, Register src);
1106   void blsmskq(Register dst, Address src);
1107 
1108   void blsrl(Register dst, Register src);
1109   void blsrl(Register dst, Address src);
1110   void blsrq(Register dst, Register src);
1111   void blsrq(Register dst, Address src);
1112 
1113   void bsfl(Register dst, Register src);
1114   void bsrl(Register dst, Register src);
1115 
1116 #ifdef _LP64
1117   void bsfq(Register dst, Register src);
1118   void bsrq(Register dst, Register src);
1119 #endif
1120 
1121   void bswapl(Register reg);
1122 
1123   void bswapq(Register reg);
1124 
1125   void call(Label& L, relocInfo::relocType rtype);
1126   void call(Register reg);  // push pc; pc <- reg
1127   void call(Address adr);   // push pc; pc <- adr
1128 
1129   void cdql();
1130 
1131   void cdqq();
1132 
1133   void cld();
1134 
1135   void clflush(Address adr);
1136 
1137   void cmovl(Condition cc, Register dst, Register src);
1138   void cmovl(Condition cc, Register dst, Address src);
1139 
1140   void cmovq(Condition cc, Register dst, Register src);
1141   void cmovq(Condition cc, Register dst, Address src);
1142 
1143 
1144   void cmpb(Address dst, int imm8);
1145 
1146   void cmpl(Address dst, int32_t imm32);
1147 
1148   void cmpl(Register dst, int32_t imm32);
1149   void cmpl(Register dst, Register src);
1150   void cmpl(Register dst, Address src);
1151 
1152   void cmpq(Address dst, int32_t imm32);
1153   void cmpq(Address dst, Register src);
1154 
1155   void cmpq(Register dst, int32_t imm32);
1156   void cmpq(Register dst, Register src);
1157   void cmpq(Register dst, Address src);
1158 
1159   // these are dummies used to catch attempting to convert NULL to Register
1160   void cmpl(Register dst, void* junk); // dummy
1161   void cmpq(Register dst, void* junk); // dummy
1162 
1163   void cmpw(Address dst, int imm16);
1164 
1165   void cmpxchg8 (Address adr);
1166 
1167   void cmpxchgb(Register reg, Address adr);
1168   void cmpxchgl(Register reg, Address adr);
1169 
1170   void cmpxchgq(Register reg, Address adr);
1171 
1172   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1173   void comisd(XMMRegister dst, Address src);
1174   void comisd(XMMRegister dst, XMMRegister src);
1175 
1176   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1177   void comiss(XMMRegister dst, Address src);
1178   void comiss(XMMRegister dst, XMMRegister src);
1179 
1180   // Identify processor type and features
1181   void cpuid();
1182 
1183   // CRC32C
1184   void crc32(Register crc, Register v, int8_t sizeInBytes);
1185   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1186 
1187   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1188   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1189   void cvtsd2ss(XMMRegister dst, Address src);
1190 
1191   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1192   void cvtsi2sdl(XMMRegister dst, Register src);
1193   void cvtsi2sdl(XMMRegister dst, Address src);
1194   void cvtsi2sdq(XMMRegister dst, Register src);
1195   void cvtsi2sdq(XMMRegister dst, Address src);
1196 
1197   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1198   void cvtsi2ssl(XMMRegister dst, Register src);
1199   void cvtsi2ssl(XMMRegister dst, Address src);
1200   void cvtsi2ssq(XMMRegister dst, Register src);
1201   void cvtsi2ssq(XMMRegister dst, Address src);
1202 
1203   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1204   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1205 
1206   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1207   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1208 
1209   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1210   void cvtss2sd(XMMRegister dst, XMMRegister src);
1211   void cvtss2sd(XMMRegister dst, Address src);
1212 
1213   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1214   void cvttsd2sil(Register dst, Address src);
1215   void cvttsd2sil(Register dst, XMMRegister src);
1216   void cvttsd2siq(Register dst, XMMRegister src);
1217 
1218   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1219   void cvttss2sil(Register dst, XMMRegister src);
1220   void cvttss2siq(Register dst, XMMRegister src);
1221 
1222   // Divide Scalar Double-Precision Floating-Point Values
1223   void divsd(XMMRegister dst, Address src);
1224   void divsd(XMMRegister dst, XMMRegister src);
1225 
1226   // Divide Scalar Single-Precision Floating-Point Values
1227   void divss(XMMRegister dst, Address src);
1228   void divss(XMMRegister dst, XMMRegister src);
1229 
1230   void emms();
1231 
1232   void fabs();
1233 
1234   void fadd(int i);
1235 
1236   void fadd_d(Address src);
1237   void fadd_s(Address src);
1238 
1239   // "Alternate" versions of x87 instructions place result down in FPU
1240   // stack instead of on TOS
1241 
1242   void fadda(int i); // "alternate" fadd
1243   void faddp(int i = 1);
1244 
1245   void fchs();
1246 
1247   void fcom(int i);
1248 
1249   void fcomp(int i = 1);
1250   void fcomp_d(Address src);
1251   void fcomp_s(Address src);
1252 
1253   void fcompp();
1254 
1255   void fcos();
1256 
1257   void fdecstp();
1258 
1259   void fdiv(int i);
1260   void fdiv_d(Address src);
1261   void fdivr_s(Address src);
1262   void fdiva(int i);  // "alternate" fdiv
1263   void fdivp(int i = 1);
1264 
1265   void fdivr(int i);
1266   void fdivr_d(Address src);
1267   void fdiv_s(Address src);
1268 
1269   void fdivra(int i); // "alternate" reversed fdiv
1270 
1271   void fdivrp(int i = 1);
1272 
1273   void ffree(int i = 0);
1274 
1275   void fild_d(Address adr);
1276   void fild_s(Address adr);
1277 
1278   void fincstp();
1279 
1280   void finit();
1281 
1282   void fist_s (Address adr);
1283   void fistp_d(Address adr);
1284   void fistp_s(Address adr);
1285 
1286   void fld1();
1287 
1288   void fld_d(Address adr);
1289   void fld_s(Address adr);
1290   void fld_s(int index);
1291   void fld_x(Address adr);  // extended-precision (80-bit) format
1292 
1293   void fldcw(Address src);
1294 
1295   void fldenv(Address src);
1296 
1297   void fldlg2();
1298 
1299   void fldln2();
1300 
1301   void fldz();
1302 
1303   void flog();
1304   void flog10();
1305 
1306   void fmul(int i);
1307 
1308   void fmul_d(Address src);
1309   void fmul_s(Address src);
1310 
1311   void fmula(int i);  // "alternate" fmul
1312 
1313   void fmulp(int i = 1);
1314 
1315   void fnsave(Address dst);
1316 
1317   void fnstcw(Address src);
1318 
1319   void fnstsw_ax();
1320 
1321   void fprem();
1322   void fprem1();
1323 
1324   void frstor(Address src);
1325 
1326   void fsin();
1327 
1328   void fsqrt();
1329 
1330   void fst_d(Address adr);
1331   void fst_s(Address adr);
1332 
1333   void fstp_d(Address adr);
1334   void fstp_d(int index);
1335   void fstp_s(Address adr);
1336   void fstp_x(Address adr); // extended-precision (80-bit) format
1337 
1338   void fsub(int i);
1339   void fsub_d(Address src);
1340   void fsub_s(Address src);
1341 
1342   void fsuba(int i);  // "alternate" fsub
1343 
1344   void fsubp(int i = 1);
1345 
1346   void fsubr(int i);
1347   void fsubr_d(Address src);
1348   void fsubr_s(Address src);
1349 
1350   void fsubra(int i); // "alternate" reversed fsub
1351 
1352   void fsubrp(int i = 1);
1353 
1354   void ftan();
1355 
1356   void ftst();
1357 
1358   void fucomi(int i = 1);
1359   void fucomip(int i = 1);
1360 
1361   void fwait();
1362 
1363   void fxch(int i = 1);
1364 
1365   void fxrstor(Address src);
1366   void xrstor(Address src);
1367 
1368   void fxsave(Address dst);
1369   void xsave(Address dst);
1370 
1371   void fyl2x();
1372   void frndint();
1373   void f2xm1();
1374   void fldl2e();
1375 
1376   void hlt();
1377 
1378   void idivl(Register src);
1379   void divl(Register src); // Unsigned division
1380 
1381 #ifdef _LP64
1382   void idivq(Register src);
1383 #endif
1384 
1385   void imull(Register dst, Register src);
1386   void imull(Register dst, Register src, int value);
1387   void imull(Register dst, Address src);
1388 
1389 #ifdef _LP64
1390   void imulq(Register dst, Register src);
1391   void imulq(Register dst, Register src, int value);
1392   void imulq(Register dst, Address src);
1393 #endif
1394 
1395   // jcc is the generic conditional branch generator to run-
1396   // time routines, jcc is used for branches to labels. jcc
1397   // takes a branch opcode (cc) and a label (L) and generates
1398   // either a backward branch or a forward branch and links it
1399   // to the label fixup chain. Usage:
1400   //
1401   // Label L;      // unbound label
1402   // jcc(cc, L);   // forward branch to unbound label
1403   // bind(L);      // bind label to the current pc
1404   // jcc(cc, L);   // backward branch to bound label
1405   // bind(L);      // illegal: a label may be bound only once
1406   //
1407   // Note: The same Label can be used for forward and backward branches
1408   // but it may be bound only once.
1409 
1410   void jcc(Condition cc, Label& L, bool maybe_short = true);
1411 
1412   // Conditional jump to a 8-bit offset to L.
1413   // WARNING: be very careful using this for forward jumps.  If the label is
1414   // not bound within an 8-bit offset of this instruction, a run-time error
1415   // will occur.
1416   void jccb(Condition cc, Label& L);
1417 
1418   void jmp(Address entry);    // pc <- entry
1419 
1420   // Label operations & relative jumps (PPUM Appendix D)
1421   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1422 
1423   void jmp(Register entry); // pc <- entry
1424 
1425   // Unconditional 8-bit offset jump to L.
1426   // WARNING: be very careful using this for forward jumps.  If the label is
1427   // not bound within an 8-bit offset of this instruction, a run-time error
1428   // will occur.
1429   void jmpb(Label& L);
1430 
1431   void ldmxcsr( Address src );
1432 
1433   void leal(Register dst, Address src);
1434 
1435   void leaq(Register dst, Address src);
1436 
1437   void lfence();
1438 
1439   void lock();
1440 
1441   void lzcntl(Register dst, Register src);
1442 
1443 #ifdef _LP64
1444   void lzcntq(Register dst, Register src);
1445 #endif
1446 
1447   enum Membar_mask_bits {
1448     StoreStore = 1 << 3,
1449     LoadStore  = 1 << 2,
1450     StoreLoad  = 1 << 1,
1451     LoadLoad   = 1 << 0
1452   };
1453 
1454   // Serializes memory and blows flags
1455   void membar(Membar_mask_bits order_constraint) {
1456     if (os::is_MP()) {
1457       // We only have to handle StoreLoad
1458       if (order_constraint & StoreLoad) {
1459         // All usable chips support "locked" instructions which suffice
1460         // as barriers, and are much faster than the alternative of
1461         // using cpuid instruction. We use here a locked add [esp-C],0.
1462         // This is conveniently otherwise a no-op except for blowing
1463         // flags, and introducing a false dependency on target memory
1464         // location. We can't do anything with flags, but we can avoid
1465         // memory dependencies in the current method by locked-adding
1466         // somewhere else on the stack. Doing [esp+C] will collide with
1467         // something on stack in current method, hence we go for [esp-C].
1468         // It is convenient since it is almost always in data cache, for
1469         // any small C.  We need to step back from SP to avoid data
1470         // dependencies with other things on below SP (callee-saves, for
1471         // example). Without a clear way to figure out the minimal safe
1472         // distance from SP, it makes sense to step back the complete
1473         // cache line, as this will also avoid possible second-order effects
1474         // with locked ops against the cache line. Our choice of offset
1475         // is bounded by x86 operand encoding, which should stay within
1476         // [-128; +127] to have the 8-byte displacement encoding.
1477         //
1478         // Any change to this code may need to revisit other places in
1479         // the code where this idiom is used, in particular the
1480         // orderAccess code.
1481 
1482         int offset = -VM_Version::L1_line_size();
1483         if (offset < -128) {
1484           offset = -128;
1485         }
1486 
1487         lock();
1488         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1489       }
1490     }
1491   }
1492 
1493   void mfence();
1494 
1495   // Moves
1496 
1497   void mov64(Register dst, int64_t imm64);
1498 
1499   void movb(Address dst, Register src);
1500   void movb(Address dst, int imm8);
1501   void movb(Register dst, Address src);
1502 
1503   void kmovql(KRegister dst, KRegister src);
1504   void kmovql(KRegister dst, Register src);
1505   void kmovdl(KRegister dst, Register src);
1506   void kmovwl(KRegister dst, Register src);
1507   void kmovql(Address dst, KRegister src);
1508   void kmovql(KRegister dst, Address src);
1509 
1510   void movdl(XMMRegister dst, Register src);
1511   void movdl(Register dst, XMMRegister src);
1512   void movdl(XMMRegister dst, Address src);
1513   void movdl(Address dst, XMMRegister src);
1514 
1515   // Move Double Quadword
1516   void movdq(XMMRegister dst, Register src);
1517   void movdq(Register dst, XMMRegister src);
1518 
1519   // Move Aligned Double Quadword
1520   void movdqa(XMMRegister dst, XMMRegister src);
1521   void movdqa(XMMRegister dst, Address src);
1522 
1523   // Move Unaligned Double Quadword
1524   void movdqu(Address     dst, XMMRegister src);
1525   void movdqu(XMMRegister dst, Address src);
1526   void movdqu(XMMRegister dst, XMMRegister src);
1527 
1528   // Move Unaligned 256bit Vector
1529   void vmovdqu(Address dst, XMMRegister src);
1530   void vmovdqu(XMMRegister dst, Address src);
1531   void vmovdqu(XMMRegister dst, XMMRegister src);
1532 
1533    // Move Unaligned 512bit Vector
1534   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1535   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1536   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1537   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1538   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1539   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1540 
1541   // Move lower 64bit to high 64bit in 128bit register
1542   void movlhps(XMMRegister dst, XMMRegister src);
1543 
1544   void movl(Register dst, int32_t imm32);
1545   void movl(Address dst, int32_t imm32);
1546   void movl(Register dst, Register src);
1547   void movl(Register dst, Address src);
1548   void movl(Address dst, Register src);
1549 
1550   // These dummies prevent using movl from converting a zero (like NULL) into Register
1551   // by giving the compiler two choices it can't resolve
1552 
1553   void movl(Address  dst, void* junk);
1554   void movl(Register dst, void* junk);
1555 
1556 #ifdef _LP64
1557   void movq(Register dst, Register src);
1558   void movq(Register dst, Address src);
1559   void movq(Address  dst, Register src);
1560 #endif
1561 
1562   void movq(Address     dst, MMXRegister src );
1563   void movq(MMXRegister dst, Address src );
1564 
1565 #ifdef _LP64
1566   // These dummies prevent using movq from converting a zero (like NULL) into Register
1567   // by giving the compiler two choices it can't resolve
1568 
1569   void movq(Address  dst, void* dummy);
1570   void movq(Register dst, void* dummy);
1571 #endif
1572 
1573   // Move Quadword
1574   void movq(Address     dst, XMMRegister src);
1575   void movq(XMMRegister dst, Address src);
1576 
1577   void movsbl(Register dst, Address src);
1578   void movsbl(Register dst, Register src);
1579 
1580 #ifdef _LP64
1581   void movsbq(Register dst, Address src);
1582   void movsbq(Register dst, Register src);
1583 
1584   // Move signed 32bit immediate to 64bit extending sign
1585   void movslq(Address  dst, int32_t imm64);
1586   void movslq(Register dst, int32_t imm64);
1587 
1588   void movslq(Register dst, Address src);
1589   void movslq(Register dst, Register src);
1590   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1591 #endif
1592 
1593   void movswl(Register dst, Address src);
1594   void movswl(Register dst, Register src);
1595 
1596 #ifdef _LP64
1597   void movswq(Register dst, Address src);
1598   void movswq(Register dst, Register src);
1599 #endif
1600 
1601   void movw(Address dst, int imm16);
1602   void movw(Register dst, Address src);
1603   void movw(Address dst, Register src);
1604 
1605   void movzbl(Register dst, Address src);
1606   void movzbl(Register dst, Register src);
1607 
1608 #ifdef _LP64
1609   void movzbq(Register dst, Address src);
1610   void movzbq(Register dst, Register src);
1611 #endif
1612 
1613   void movzwl(Register dst, Address src);
1614   void movzwl(Register dst, Register src);
1615 
1616 #ifdef _LP64
1617   void movzwq(Register dst, Address src);
1618   void movzwq(Register dst, Register src);
1619 #endif
1620 
1621   // Unsigned multiply with RAX destination register
1622   void mull(Address src);
1623   void mull(Register src);
1624 
1625 #ifdef _LP64
1626   void mulq(Address src);
1627   void mulq(Register src);
1628   void mulxq(Register dst1, Register dst2, Register src);
1629 #endif
1630 
1631   // Multiply Scalar Double-Precision Floating-Point Values
1632   void mulsd(XMMRegister dst, Address src);
1633   void mulsd(XMMRegister dst, XMMRegister src);
1634 
1635   // Multiply Scalar Single-Precision Floating-Point Values
1636   void mulss(XMMRegister dst, Address src);
1637   void mulss(XMMRegister dst, XMMRegister src);
1638 
1639   void negl(Register dst);
1640 
1641 #ifdef _LP64
1642   void negq(Register dst);
1643 #endif
1644 
1645   void nop(int i = 1);
1646 
1647   void notl(Register dst);
1648 
1649 #ifdef _LP64
1650   void notq(Register dst);
1651 #endif
1652 
1653   void orl(Address dst, int32_t imm32);
1654   void orl(Register dst, int32_t imm32);
1655   void orl(Register dst, Address src);
1656   void orl(Register dst, Register src);
1657   void orl(Address dst, Register src);
1658 
1659   void orq(Address dst, int32_t imm32);
1660   void orq(Register dst, int32_t imm32);
1661   void orq(Register dst, Address src);
1662   void orq(Register dst, Register src);
1663 
1664   // Pack with unsigned saturation
1665   void packuswb(XMMRegister dst, XMMRegister src);
1666   void packuswb(XMMRegister dst, Address src);
1667   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1668 
1669   // Pemutation of 64bit words
1670   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1671   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1672 
1673   void pause();
1674 
1675   // SSE4.2 string instructions
1676   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1677   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1678 
1679   // SSE 4.1 extract
1680   void pextrd(Register dst, XMMRegister src, int imm8);
1681   void pextrq(Register dst, XMMRegister src, int imm8);
1682 
1683   // SSE 4.1 insert
1684   void pinsrd(XMMRegister dst, Register src, int imm8);
1685   void pinsrq(XMMRegister dst, Register src, int imm8);
1686 
1687   // SSE4.1 packed move
1688   void pmovzxbw(XMMRegister dst, XMMRegister src);
1689   void pmovzxbw(XMMRegister dst, Address src);
1690 
1691 #ifndef _LP64 // no 32bit push/pop on amd64
1692   void popl(Address dst);
1693 #endif
1694 
1695 #ifdef _LP64
1696   void popq(Address dst);
1697 #endif
1698 
1699   void popcntl(Register dst, Address src);
1700   void popcntl(Register dst, Register src);
1701 
1702 #ifdef _LP64
1703   void popcntq(Register dst, Address src);
1704   void popcntq(Register dst, Register src);
1705 #endif
1706 
1707   // Prefetches (SSE, SSE2, 3DNOW only)
1708 
1709   void prefetchnta(Address src);
1710   void prefetchr(Address src);
1711   void prefetcht0(Address src);
1712   void prefetcht1(Address src);
1713   void prefetcht2(Address src);
1714   void prefetchw(Address src);
1715 
1716   // Shuffle Bytes
1717   void pshufb(XMMRegister dst, XMMRegister src);
1718   void pshufb(XMMRegister dst, Address src);
1719 
1720   // Shuffle Packed Doublewords
1721   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1722   void pshufd(XMMRegister dst, Address src,     int mode);
1723 
1724   // Shuffle Packed Low Words
1725   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1726   void pshuflw(XMMRegister dst, Address src,     int mode);
1727 
1728   // Shift Right by bytes Logical DoubleQuadword Immediate
1729   void psrldq(XMMRegister dst, int shift);
1730   // Shift Left by bytes Logical DoubleQuadword Immediate
1731   void pslldq(XMMRegister dst, int shift);
1732 
1733   // Logical Compare 128bit
1734   void ptest(XMMRegister dst, XMMRegister src);
1735   void ptest(XMMRegister dst, Address src);
1736   // Logical Compare 256bit
1737   void vptest(XMMRegister dst, XMMRegister src);
1738   void vptest(XMMRegister dst, Address src);
1739 
1740   // Interleave Low Bytes
1741   void punpcklbw(XMMRegister dst, XMMRegister src);
1742   void punpcklbw(XMMRegister dst, Address src);
1743 
1744   // Interleave Low Doublewords
1745   void punpckldq(XMMRegister dst, XMMRegister src);
1746   void punpckldq(XMMRegister dst, Address src);
1747 
1748   // Interleave Low Quadwords
1749   void punpcklqdq(XMMRegister dst, XMMRegister src);
1750 
1751 #ifndef _LP64 // no 32bit push/pop on amd64
1752   void pushl(Address src);
1753 #endif
1754 
1755   void pushq(Address src);
1756 
1757   void rcll(Register dst, int imm8);
1758 
1759   void rclq(Register dst, int imm8);
1760 
1761   void rcrq(Register dst, int imm8);
1762 
1763   void rdtsc();
1764 
1765   void ret(int imm16);
1766 
1767 #ifdef _LP64
1768   void rorq(Register dst, int imm8);
1769   void rorxq(Register dst, Register src, int imm8);
1770 #endif
1771 
1772   void sahf();
1773 
1774   void sarl(Register dst, int imm8);
1775   void sarl(Register dst);
1776 
1777   void sarq(Register dst, int imm8);
1778   void sarq(Register dst);
1779 
1780   void sbbl(Address dst, int32_t imm32);
1781   void sbbl(Register dst, int32_t imm32);
1782   void sbbl(Register dst, Address src);
1783   void sbbl(Register dst, Register src);
1784 
1785   void sbbq(Address dst, int32_t imm32);
1786   void sbbq(Register dst, int32_t imm32);
1787   void sbbq(Register dst, Address src);
1788   void sbbq(Register dst, Register src);
1789 
1790   void setb(Condition cc, Register dst);
1791 
1792   void shldl(Register dst, Register src);
1793   void shldl(Register dst, Register src, int8_t imm8);
1794 
1795   void shll(Register dst, int imm8);
1796   void shll(Register dst);
1797 
1798   void shlq(Register dst, int imm8);
1799   void shlq(Register dst);
1800 
1801   void shrdl(Register dst, Register src);
1802 
1803   void shrl(Register dst, int imm8);
1804   void shrl(Register dst);
1805 
1806   void shrq(Register dst, int imm8);
1807   void shrq(Register dst);
1808 
1809   void smovl(); // QQQ generic?
1810 
1811   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1812   void sqrtsd(XMMRegister dst, Address src);
1813   void sqrtsd(XMMRegister dst, XMMRegister src);
1814 
1815   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1816   void sqrtss(XMMRegister dst, Address src);
1817   void sqrtss(XMMRegister dst, XMMRegister src);
1818 
1819   void std();
1820 
1821   void stmxcsr( Address dst );
1822 
1823   void subl(Address dst, int32_t imm32);
1824   void subl(Address dst, Register src);
1825   void subl(Register dst, int32_t imm32);
1826   void subl(Register dst, Address src);
1827   void subl(Register dst, Register src);
1828 
1829   void subq(Address dst, int32_t imm32);
1830   void subq(Address dst, Register src);
1831   void subq(Register dst, int32_t imm32);
1832   void subq(Register dst, Address src);
1833   void subq(Register dst, Register src);
1834 
1835   // Force generation of a 4 byte immediate value even if it fits into 8bit
1836   void subl_imm32(Register dst, int32_t imm32);
1837   void subq_imm32(Register dst, int32_t imm32);
1838 
1839   // Subtract Scalar Double-Precision Floating-Point Values
1840   void subsd(XMMRegister dst, Address src);
1841   void subsd(XMMRegister dst, XMMRegister src);
1842 
1843   // Subtract Scalar Single-Precision Floating-Point Values
1844   void subss(XMMRegister dst, Address src);
1845   void subss(XMMRegister dst, XMMRegister src);
1846 
1847   void testb(Register dst, int imm8);
1848 
1849   void testl(Register dst, int32_t imm32);
1850   void testl(Register dst, Register src);
1851   void testl(Register dst, Address src);
1852 
1853   void testq(Register dst, int32_t imm32);
1854   void testq(Register dst, Register src);
1855 
1856   // BMI - count trailing zeros
1857   void tzcntl(Register dst, Register src);
1858   void tzcntq(Register dst, Register src);
1859 
1860   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1861   void ucomisd(XMMRegister dst, Address src);
1862   void ucomisd(XMMRegister dst, XMMRegister src);
1863 
1864   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1865   void ucomiss(XMMRegister dst, Address src);
1866   void ucomiss(XMMRegister dst, XMMRegister src);
1867 
1868   void xabort(int8_t imm8);
1869 
1870   void xaddl(Address dst, Register src);
1871 
1872   void xaddq(Address dst, Register src);
1873 
1874   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1875 
1876   void xchgl(Register reg, Address adr);
1877   void xchgl(Register dst, Register src);
1878 
1879   void xchgq(Register reg, Address adr);
1880   void xchgq(Register dst, Register src);
1881 
1882   void xend();
1883 
1884   // Get Value of Extended Control Register
1885   void xgetbv();
1886 
1887   void xorl(Register dst, int32_t imm32);
1888   void xorl(Register dst, Address src);
1889   void xorl(Register dst, Register src);
1890 
1891   void xorq(Register dst, Address src);
1892   void xorq(Register dst, Register src);
1893 
1894   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1895 
1896   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1897 
1898   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1899   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1900   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1901   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1902   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1903   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1904   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1905   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1906   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1907   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1908   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1909   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1910   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1911   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1912   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1913   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1914 
1915 
1916   //====================VECTOR ARITHMETIC=====================================
1917 
1918   // Add Packed Floating-Point Values
1919   void addpd(XMMRegister dst, XMMRegister src);
1920   void addps(XMMRegister dst, XMMRegister src);
1921   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1922   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1923   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1924   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1925 
1926   // Subtract Packed Floating-Point Values
1927   void subpd(XMMRegister dst, XMMRegister src);
1928   void subps(XMMRegister dst, XMMRegister src);
1929   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1930   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1931   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1932   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1933 
1934   // Multiply Packed Floating-Point Values
1935   void mulpd(XMMRegister dst, XMMRegister src);
1936   void mulps(XMMRegister dst, XMMRegister src);
1937   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1938   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1939   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1940   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1941 
1942   // Divide Packed Floating-Point Values
1943   void divpd(XMMRegister dst, XMMRegister src);
1944   void divps(XMMRegister dst, XMMRegister src);
1945   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1946   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1947   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1948   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1949 
1950   // Sqrt Packed Floating-Point Values - Double precision only
1951   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1952   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1953 
1954   // Bitwise Logical AND of Packed Floating-Point Values
1955   void andpd(XMMRegister dst, XMMRegister src);
1956   void andps(XMMRegister dst, XMMRegister src);
1957   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1958   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1959   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1960   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1961 
1962   // Bitwise Logical XOR of Packed Floating-Point Values
1963   void xorpd(XMMRegister dst, XMMRegister src);
1964   void xorps(XMMRegister dst, XMMRegister src);
1965   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1966   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1967   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1968   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1969 
1970   // Add horizontal packed integers
1971   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1972   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1973   void phaddw(XMMRegister dst, XMMRegister src);
1974   void phaddd(XMMRegister dst, XMMRegister src);
1975 
1976   // Add packed integers
1977   void paddb(XMMRegister dst, XMMRegister src);
1978   void paddw(XMMRegister dst, XMMRegister src);
1979   void paddd(XMMRegister dst, XMMRegister src);
1980   void paddq(XMMRegister dst, XMMRegister src);
1981   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1982   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1983   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1984   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1985   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1986   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1987   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1988   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1989 
1990   // Sub packed integers
1991   void psubb(XMMRegister dst, XMMRegister src);
1992   void psubw(XMMRegister dst, XMMRegister src);
1993   void psubd(XMMRegister dst, XMMRegister src);
1994   void psubq(XMMRegister dst, XMMRegister src);
1995   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1996   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1997   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1998   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1999   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2000   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2001   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2002   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2003 
2004   // Multiply packed integers (only shorts and ints)
2005   void pmullw(XMMRegister dst, XMMRegister src);
2006   void pmulld(XMMRegister dst, XMMRegister src);
2007   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2008   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2009   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2010   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2011   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2012   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013 
2014   // Shift left packed integers
2015   void psllw(XMMRegister dst, int shift);
2016   void pslld(XMMRegister dst, int shift);
2017   void psllq(XMMRegister dst, int shift);
2018   void psllw(XMMRegister dst, XMMRegister shift);
2019   void pslld(XMMRegister dst, XMMRegister shift);
2020   void psllq(XMMRegister dst, XMMRegister shift);
2021   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2022   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2023   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2024   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2025   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2026   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2027 
2028   // Logical shift right packed integers
2029   void psrlw(XMMRegister dst, int shift);
2030   void psrld(XMMRegister dst, int shift);
2031   void psrlq(XMMRegister dst, int shift);
2032   void psrlw(XMMRegister dst, XMMRegister shift);
2033   void psrld(XMMRegister dst, XMMRegister shift);
2034   void psrlq(XMMRegister dst, XMMRegister shift);
2035   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2036   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2037   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2038   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2039   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2040   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2041 
2042   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2043   void psraw(XMMRegister dst, int shift);
2044   void psrad(XMMRegister dst, int shift);
2045   void psraw(XMMRegister dst, XMMRegister shift);
2046   void psrad(XMMRegister dst, XMMRegister shift);
2047   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2048   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2049   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2050   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2051 
2052   // And packed integers
2053   void pand(XMMRegister dst, XMMRegister src);
2054   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2055   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2056 
2057   // Or packed integers
2058   void por(XMMRegister dst, XMMRegister src);
2059   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2060   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2061 
2062   // Xor packed integers
2063   void pxor(XMMRegister dst, XMMRegister src);
2064   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2065   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2066 
2067   // Copy low 128bit into high 128bit of YMM registers.
2068   void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2069   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2070   void vextractf128h(XMMRegister dst, XMMRegister src);
2071   void vextracti128h(XMMRegister dst, XMMRegister src);
2072 
2073   // Load/store high 128bit of YMM registers which does not destroy other half.
2074   void vinsertf128h(XMMRegister dst, Address src);
2075   void vinserti128h(XMMRegister dst, Address src);
2076   void vextractf128h(Address dst, XMMRegister src);
2077   void vextracti128h(Address dst, XMMRegister src);
2078 
2079   // Copy low 256bit into high 256bit of ZMM registers.
2080   void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2081   void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2082   void vextracti64x4h(XMMRegister dst, XMMRegister src);
2083   void vextractf64x4h(XMMRegister dst, XMMRegister src);
2084   void vextractf64x4h(Address dst, XMMRegister src);
2085   void vinsertf64x4h(XMMRegister dst, Address src);
2086 
2087   // Copy targeted 128bit segments of the ZMM registers
2088   void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
2089   void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
2090   void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
2091   void vextractf32x4h(Address dst, XMMRegister src, int value);
2092   void vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
2093   void vinsertf32x4h(XMMRegister dst, Address src, int value);
2094 
2095   // duplicate 4-bytes integer data from src into 8 locations in dest
2096   void vpbroadcastd(XMMRegister dst, XMMRegister src);
2097 
2098   // duplicate n-bytes integer data from src into vector_len locations in dest
2099   void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2100   void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2101   void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2102   void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2103   void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2104   void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2105   void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2106   void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2107 
2108   void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2109   void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2110   void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2111   void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2112 
2113   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2114   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2115   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2116   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2117 
2118   // Carry-Less Multiplication Quadword
2119   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2120   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2121 
2122   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2123   // to avoid transaction penalty between AVX and SSE states. There is no
2124   // penalty if legacy SSE instructions are encoded using VEX prefix because
2125   // they always clear upper 128 bits. It should be used before calling
2126   // runtime code and native libraries.
2127   void vzeroupper();
2128 
2129  protected:
2130   // Next instructions require address alignment 16 bytes SSE mode.
2131   // They should be called only from corresponding MacroAssembler instructions.
2132   void andpd(XMMRegister dst, Address src);
2133   void andps(XMMRegister dst, Address src);
2134   void xorpd(XMMRegister dst, Address src);
2135   void xorps(XMMRegister dst, Address src);
2136 
2137 };
2138 
2139 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP
--- EOF ---