1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "memory/resourceArea.hpp" 29 #include "runtime/java.hpp" 30 #include "runtime/os.hpp" 31 #include "runtime/stubCodeGenerator.hpp" 32 #include "vm_version_x86.hpp" 33 34 35 int VM_Version::_cpu; 36 int VM_Version::_model; 37 int VM_Version::_stepping; 38 uint64_t VM_Version::_cpuFeatures; 39 const char* VM_Version::_features_str = ""; 40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 41 42 // Address of instruction which causes SEGV 43 address VM_Version::_cpuinfo_segv_addr = 0; 44 // Address of instruction after the one which causes SEGV 45 address VM_Version::_cpuinfo_cont_addr = 0; 46 47 static BufferBlob* stub_blob; 48 static const int stub_size = 1000; 49 50 extern "C" { 51 typedef void (*get_cpu_info_stub_t)(void*); 52 } 53 static get_cpu_info_stub_t get_cpu_info_stub = NULL; 54 55 56 class VM_Version_StubGenerator: public StubCodeGenerator { 57 public: 58 59 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 60 61 address generate_get_cpu_info() { 62 // Flags to test CPU type. 63 const uint32_t HS_EFL_AC = 0x40000; 64 const uint32_t HS_EFL_ID = 0x200000; 65 // Values for when we don't have a CPUID instruction. 66 const int CPU_FAMILY_SHIFT = 8; 67 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 68 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 69 70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; 71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup; 72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check; 73 74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); 75 # define __ _masm-> 76 77 address start = __ pc(); 78 79 // 80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); 81 // 82 // LP64: rcx and rdx are first and second argument registers on windows 83 84 __ push(rbp); 85 #ifdef _LP64 86 __ mov(rbp, c_rarg0); // cpuid_info address 87 #else 88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address 89 #endif 90 __ push(rbx); 91 __ push(rsi); 92 __ pushf(); // preserve rbx, and flags 93 __ pop(rax); 94 __ push(rax); 95 __ mov(rcx, rax); 96 // 97 // if we are unable to change the AC flag, we have a 386 98 // 99 __ xorl(rax, HS_EFL_AC); 100 __ push(rax); 101 __ popf(); 102 __ pushf(); 103 __ pop(rax); 104 __ cmpptr(rax, rcx); 105 __ jccb(Assembler::notEqual, detect_486); 106 107 __ movl(rax, CPU_FAMILY_386); 108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 109 __ jmp(done); 110 111 // 112 // If we are unable to change the ID flag, we have a 486 which does 113 // not support the "cpuid" instruction. 114 // 115 __ bind(detect_486); 116 __ mov(rax, rcx); 117 __ xorl(rax, HS_EFL_ID); 118 __ push(rax); 119 __ popf(); 120 __ pushf(); 121 __ pop(rax); 122 __ cmpptr(rcx, rax); 123 __ jccb(Assembler::notEqual, detect_586); 124 125 __ bind(cpu486); 126 __ movl(rax, CPU_FAMILY_486); 127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 128 __ jmp(done); 129 130 // 131 // At this point, we have a chip which supports the "cpuid" instruction 132 // 133 __ bind(detect_586); 134 __ xorl(rax, rax); 135 __ cpuid(); 136 __ orl(rax, rax); 137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input 138 // value of at least 1, we give up and 139 // assume a 486 140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); 141 __ movl(Address(rsi, 0), rax); 142 __ movl(Address(rsi, 4), rbx); 143 __ movl(Address(rsi, 8), rcx); 144 __ movl(Address(rsi,12), rdx); 145 146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? 147 __ jccb(Assembler::belowEqual, std_cpuid4); 148 149 // 150 // cpuid(0xB) Processor Topology 151 // 152 __ movl(rax, 0xb); 153 __ xorl(rcx, rcx); // Threads level 154 __ cpuid(); 155 156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); 157 __ movl(Address(rsi, 0), rax); 158 __ movl(Address(rsi, 4), rbx); 159 __ movl(Address(rsi, 8), rcx); 160 __ movl(Address(rsi,12), rdx); 161 162 __ movl(rax, 0xb); 163 __ movl(rcx, 1); // Cores level 164 __ cpuid(); 165 __ push(rax); 166 __ andl(rax, 0x1f); // Determine if valid topology level 167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 168 __ andl(rax, 0xffff); 169 __ pop(rax); 170 __ jccb(Assembler::equal, std_cpuid4); 171 172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); 173 __ movl(Address(rsi, 0), rax); 174 __ movl(Address(rsi, 4), rbx); 175 __ movl(Address(rsi, 8), rcx); 176 __ movl(Address(rsi,12), rdx); 177 178 __ movl(rax, 0xb); 179 __ movl(rcx, 2); // Packages level 180 __ cpuid(); 181 __ push(rax); 182 __ andl(rax, 0x1f); // Determine if valid topology level 183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 184 __ andl(rax, 0xffff); 185 __ pop(rax); 186 __ jccb(Assembler::equal, std_cpuid4); 187 188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); 189 __ movl(Address(rsi, 0), rax); 190 __ movl(Address(rsi, 4), rbx); 191 __ movl(Address(rsi, 8), rcx); 192 __ movl(Address(rsi,12), rdx); 193 194 // 195 // cpuid(0x4) Deterministic cache params 196 // 197 __ bind(std_cpuid4); 198 __ movl(rax, 4); 199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? 200 __ jccb(Assembler::greater, std_cpuid1); 201 202 __ xorl(rcx, rcx); // L1 cache 203 __ cpuid(); 204 __ push(rax); 205 __ andl(rax, 0x1f); // Determine if valid cache parameters used 206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache 207 __ pop(rax); 208 __ jccb(Assembler::equal, std_cpuid1); 209 210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); 211 __ movl(Address(rsi, 0), rax); 212 __ movl(Address(rsi, 4), rbx); 213 __ movl(Address(rsi, 8), rcx); 214 __ movl(Address(rsi,12), rdx); 215 216 // 217 // Standard cpuid(0x1) 218 // 219 __ bind(std_cpuid1); 220 __ movl(rax, 1); 221 __ cpuid(); 222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 223 __ movl(Address(rsi, 0), rax); 224 __ movl(Address(rsi, 4), rbx); 225 __ movl(Address(rsi, 8), rcx); 226 __ movl(Address(rsi,12), rdx); 227 228 // 229 // Check if OS has enabled XGETBV instruction to access XCR0 230 // (OSXSAVE feature flag) and CPU supports AVX 231 // 232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 233 __ cmpl(rcx, 0x18000000); 234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported 235 236 // 237 // XCR0, XFEATURE_ENABLED_MASK register 238 // 239 __ xorl(rcx, rcx); // zero for XCR0 register 240 __ xgetbv(); 241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); 242 __ movl(Address(rsi, 0), rax); 243 __ movl(Address(rsi, 4), rdx); 244 245 // 246 // cpuid(0x7) Structured Extended Features 247 // 248 __ bind(sef_cpuid); 249 __ movl(rax, 7); 250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? 251 __ jccb(Assembler::greater, ext_cpuid); 252 253 __ xorl(rcx, rcx); 254 __ cpuid(); 255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 256 __ movl(Address(rsi, 0), rax); 257 __ movl(Address(rsi, 4), rbx); 258 259 // 260 // Extended cpuid(0x80000000) 261 // 262 __ bind(ext_cpuid); 263 __ movl(rax, 0x80000000); 264 __ cpuid(); 265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? 266 __ jcc(Assembler::belowEqual, done); 267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? 268 __ jccb(Assembler::belowEqual, ext_cpuid1); 269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? 270 __ jccb(Assembler::belowEqual, ext_cpuid5); 271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? 272 __ jccb(Assembler::belowEqual, ext_cpuid7); 273 // 274 // Extended cpuid(0x80000008) 275 // 276 __ movl(rax, 0x80000008); 277 __ cpuid(); 278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); 279 __ movl(Address(rsi, 0), rax); 280 __ movl(Address(rsi, 4), rbx); 281 __ movl(Address(rsi, 8), rcx); 282 __ movl(Address(rsi,12), rdx); 283 284 // 285 // Extended cpuid(0x80000007) 286 // 287 __ bind(ext_cpuid7); 288 __ movl(rax, 0x80000007); 289 __ cpuid(); 290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); 291 __ movl(Address(rsi, 0), rax); 292 __ movl(Address(rsi, 4), rbx); 293 __ movl(Address(rsi, 8), rcx); 294 __ movl(Address(rsi,12), rdx); 295 296 // 297 // Extended cpuid(0x80000005) 298 // 299 __ bind(ext_cpuid5); 300 __ movl(rax, 0x80000005); 301 __ cpuid(); 302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); 303 __ movl(Address(rsi, 0), rax); 304 __ movl(Address(rsi, 4), rbx); 305 __ movl(Address(rsi, 8), rcx); 306 __ movl(Address(rsi,12), rdx); 307 308 // 309 // Extended cpuid(0x80000001) 310 // 311 __ bind(ext_cpuid1); 312 __ movl(rax, 0x80000001); 313 __ cpuid(); 314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); 315 __ movl(Address(rsi, 0), rax); 316 __ movl(Address(rsi, 4), rbx); 317 __ movl(Address(rsi, 8), rcx); 318 __ movl(Address(rsi,12), rdx); 319 320 // 321 // Check if OS has enabled XGETBV instruction to access XCR0 322 // (OSXSAVE feature flag) and CPU supports AVX 323 // 324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx 327 __ cmpl(rcx, 0x18000000); 328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported 329 330 __ movl(rax, 0x6); 331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 332 __ cmpl(rax, 0x6); 333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported 334 335 // we need to bridge farther than imm8, so we use this island as a thunk 336 __ bind(done); 337 __ jmp(wrapup); 338 339 __ bind(start_simd_check); 340 // 341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM 342 // registers are not restored after a signal processing. 343 // Generate SEGV here (reference through NULL) 344 // and check upper YMM/ZMM bits after it. 345 // 346 intx saved_useavx = UseAVX; 347 intx saved_usesse = UseSSE; 348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 350 __ movl(rax, 0x10000); 351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm 352 __ cmpl(rax, 0x10000); 353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 354 // check _cpuid_info.xem_xcr0_eax.bits.opmask 355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 357 __ movl(rax, 0xE0); 358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 359 __ cmpl(rax, 0xE0); 360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 361 362 // EVEX setup: run in lowest evex mode 363 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 364 UseAVX = 3; 365 UseSSE = 2; 366 // load value into all 64 bytes of zmm7 register 367 __ movl(rcx, VM_Version::ymm_test_value()); 368 __ movdl(xmm0, rcx); 369 __ movl(rcx, 0xffff); 370 __ kmovwl(k1, rcx); 371 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit); 372 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit); 373 #ifdef _LP64 374 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit); 375 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit); 376 #endif 377 VM_Version::clean_cpuFeatures(); 378 __ jmp(save_restore_except); 379 380 __ bind(legacy_setup); 381 // AVX setup 382 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 383 UseAVX = 1; 384 UseSSE = 2; 385 // load value into all 32 bytes of ymm7 register 386 __ movl(rcx, VM_Version::ymm_test_value()); 387 388 __ movdl(xmm0, rcx); 389 __ pshufd(xmm0, xmm0, 0x00); 390 __ vinsertf128h(xmm0, xmm0, xmm0); 391 __ vmovdqu(xmm7, xmm0); 392 #ifdef _LP64 393 __ vmovdqu(xmm8, xmm0); 394 __ vmovdqu(xmm15, xmm0); 395 #endif 396 VM_Version::clean_cpuFeatures(); 397 398 __ bind(save_restore_except); 399 __ xorl(rsi, rsi); 400 VM_Version::set_cpuinfo_segv_addr(__ pc()); 401 // Generate SEGV 402 __ movl(rax, Address(rsi, 0)); 403 404 VM_Version::set_cpuinfo_cont_addr(__ pc()); 405 // Returns here after signal. Save xmm0 to check it later. 406 407 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 408 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 409 __ movl(rax, 0x10000); 410 __ andl(rax, Address(rsi, 4)); 411 __ cmpl(rax, 0x10000); 412 __ jccb(Assembler::notEqual, legacy_save_restore); 413 // check _cpuid_info.xem_xcr0_eax.bits.opmask 414 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 415 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 416 __ movl(rax, 0xE0); 417 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 418 __ cmpl(rax, 0xE0); 419 __ jccb(Assembler::notEqual, legacy_save_restore); 420 421 // EVEX check: run in lowest evex mode 422 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 423 UseAVX = 3; 424 UseSSE = 2; 425 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset()))); 426 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit); 427 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit); 428 #ifdef _LP64 429 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit); 430 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit); 431 #endif 432 VM_Version::clean_cpuFeatures(); 433 UseAVX = saved_useavx; 434 UseSSE = saved_usesse; 435 __ jmp(wrapup); 436 437 __ bind(legacy_save_restore); 438 // AVX check 439 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 440 UseAVX = 1; 441 UseSSE = 2; 442 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); 443 __ vmovdqu(Address(rsi, 0), xmm0); 444 __ vmovdqu(Address(rsi, 32), xmm7); 445 #ifdef _LP64 446 __ vmovdqu(Address(rsi, 64), xmm8); 447 __ vmovdqu(Address(rsi, 96), xmm15); 448 #endif 449 VM_Version::clean_cpuFeatures(); 450 UseAVX = saved_useavx; 451 UseSSE = saved_usesse; 452 453 __ bind(wrapup); 454 __ popf(); 455 __ pop(rsi); 456 __ pop(rbx); 457 __ pop(rbp); 458 __ ret(0); 459 460 # undef __ 461 462 return start; 463 }; 464 }; 465 466 void VM_Version::get_processor_features() { 467 468 _cpu = 4; // 486 by default 469 _model = 0; 470 _stepping = 0; 471 _cpuFeatures = 0; 472 _logical_processors_per_package = 1; 473 // i486 internal cache is both I&D and has a 16-byte line size 474 _L1_data_cache_line_size = 16; 475 476 if (!Use486InstrsOnly) { 477 // Get raw processor info 478 479 get_cpu_info_stub(&_cpuid_info); 480 481 assert_is_initialized(); 482 _cpu = extended_cpu_family(); 483 _model = extended_cpu_model(); 484 _stepping = cpu_stepping(); 485 486 if (cpu_family() > 4) { // it supports CPUID 487 _cpuFeatures = feature_flags(); 488 // Logical processors are only available on P4s and above, 489 // and only if hyperthreading is available. 490 _logical_processors_per_package = logical_processor_count(); 491 _L1_data_cache_line_size = L1_line_size(); 492 } 493 } 494 495 _supports_cx8 = supports_cmpxchg8(); 496 // xchg and xadd instructions 497 _supports_atomic_getset4 = true; 498 _supports_atomic_getadd4 = true; 499 LP64_ONLY(_supports_atomic_getset8 = true); 500 LP64_ONLY(_supports_atomic_getadd8 = true); 501 502 #ifdef _LP64 503 // OS should support SSE for x64 and hardware should support at least SSE2. 504 if (!VM_Version::supports_sse2()) { 505 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); 506 } 507 // in 64 bit the use of SSE2 is the minimum 508 if (UseSSE < 2) UseSSE = 2; 509 #endif 510 511 #ifdef AMD64 512 // flush_icache_stub have to be generated first. 513 // That is why Icache line size is hard coded in ICache class, 514 // see icache_x86.hpp. It is also the reason why we can't use 515 // clflush instruction in 32-bit VM since it could be running 516 // on CPU which does not support it. 517 // 518 // The only thing we can do is to verify that flushed 519 // ICache::line_size has correct value. 520 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); 521 // clflush_size is size in quadwords (8 bytes). 522 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); 523 #endif 524 525 // If the OS doesn't support SSE, we can't use this feature even if the HW does 526 if (!os::supports_sse()) 527 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); 528 529 if (UseSSE < 4) { 530 _cpuFeatures &= ~CPU_SSE4_1; 531 _cpuFeatures &= ~CPU_SSE4_2; 532 } 533 534 if (UseSSE < 3) { 535 _cpuFeatures &= ~CPU_SSE3; 536 _cpuFeatures &= ~CPU_SSSE3; 537 _cpuFeatures &= ~CPU_SSE4A; 538 } 539 540 if (UseSSE < 2) 541 _cpuFeatures &= ~CPU_SSE2; 542 543 if (UseSSE < 1) 544 _cpuFeatures &= ~CPU_SSE; 545 546 // first try initial setting and detect what we can support 547 if (UseAVX > 0) { 548 if (UseAVX > 2 && supports_evex()) { 549 UseAVX = 3; 550 } else if (UseAVX > 1 && supports_avx2()) { 551 UseAVX = 2; 552 } else if (UseAVX > 0 && supports_avx()) { 553 UseAVX = 1; 554 } else { 555 UseAVX = 0; 556 } 557 } else if (UseAVX < 0) { 558 UseAVX = 0; 559 } 560 561 if (UseAVX < 3) { 562 _cpuFeatures &= ~CPU_AVX512F; 563 _cpuFeatures &= ~CPU_AVX512DQ; 564 _cpuFeatures &= ~CPU_AVX512CD; 565 _cpuFeatures &= ~CPU_AVX512BW; 566 _cpuFeatures &= ~CPU_AVX512VL; 567 } 568 569 if (UseAVX < 2) 570 _cpuFeatures &= ~CPU_AVX2; 571 572 if (UseAVX < 1) 573 _cpuFeatures &= ~CPU_AVX; 574 575 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) 576 _cpuFeatures &= ~CPU_AES; 577 578 if (logical_processors_per_package() == 1) { 579 // HT processor could be installed on a system which doesn't support HT. 580 _cpuFeatures &= ~CPU_HT; 581 } 582 583 char buf[256]; 584 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 585 cores_per_cpu(), threads_per_core(), 586 cpu_family(), _model, _stepping, 587 (supports_cmov() ? ", cmov" : ""), 588 (supports_cmpxchg8() ? ", cx8" : ""), 589 (supports_fxsr() ? ", fxsr" : ""), 590 (supports_mmx() ? ", mmx" : ""), 591 (supports_sse() ? ", sse" : ""), 592 (supports_sse2() ? ", sse2" : ""), 593 (supports_sse3() ? ", sse3" : ""), 594 (supports_ssse3()? ", ssse3": ""), 595 (supports_sse4_1() ? ", sse4.1" : ""), 596 (supports_sse4_2() ? ", sse4.2" : ""), 597 (supports_popcnt() ? ", popcnt" : ""), 598 (supports_avx() ? ", avx" : ""), 599 (supports_avx2() ? ", avx2" : ""), 600 (supports_aes() ? ", aes" : ""), 601 (supports_clmul() ? ", clmul" : ""), 602 (supports_erms() ? ", erms" : ""), 603 (supports_rtm() ? ", rtm" : ""), 604 (supports_mmx_ext() ? ", mmxext" : ""), 605 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), 606 (supports_lzcnt() ? ", lzcnt": ""), 607 (supports_sse4a() ? ", sse4a": ""), 608 (supports_ht() ? ", ht": ""), 609 (supports_tsc() ? ", tsc": ""), 610 (supports_tscinv_bit() ? ", tscinvbit": ""), 611 (supports_tscinv() ? ", tscinv": ""), 612 (supports_bmi1() ? ", bmi1" : ""), 613 (supports_bmi2() ? ", bmi2" : ""), 614 (supports_adx() ? ", adx" : ""), 615 (supports_evex() ? ", evex" : "")); 616 _features_str = os::strdup(buf); 617 618 // UseSSE is set to the smaller of what hardware supports and what 619 // the command line requires. I.e., you cannot set UseSSE to 2 on 620 // older Pentiums which do not support it. 621 if (UseSSE > 4) UseSSE=4; 622 if (UseSSE < 0) UseSSE=0; 623 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support 624 UseSSE = MIN2((intx)3,UseSSE); 625 if (!supports_sse3()) // Drop to 2 if no SSE3 support 626 UseSSE = MIN2((intx)2,UseSSE); 627 if (!supports_sse2()) // Drop to 1 if no SSE2 support 628 UseSSE = MIN2((intx)1,UseSSE); 629 if (!supports_sse ()) // Drop to 0 if no SSE support 630 UseSSE = 0; 631 632 // Use AES instructions if available. 633 if (supports_aes()) { 634 if (FLAG_IS_DEFAULT(UseAES)) { 635 UseAES = true; 636 } 637 } else if (UseAES) { 638 if (!FLAG_IS_DEFAULT(UseAES)) 639 warning("AES instructions are not available on this CPU"); 640 FLAG_SET_DEFAULT(UseAES, false); 641 } 642 643 // Use CLMUL instructions if available. 644 if (supports_clmul()) { 645 if (FLAG_IS_DEFAULT(UseCLMUL)) { 646 UseCLMUL = true; 647 } 648 } else if (UseCLMUL) { 649 if (!FLAG_IS_DEFAULT(UseCLMUL)) 650 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); 651 FLAG_SET_DEFAULT(UseCLMUL, false); 652 } 653 654 if (UseCLMUL && (UseSSE > 2)) { 655 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 656 UseCRC32Intrinsics = true; 657 } 658 } else if (UseCRC32Intrinsics) { 659 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 660 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); 661 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 662 } 663 664 if (supports_sse4_2()) { 665 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 666 UseCRC32CIntrinsics = true; 667 } 668 } 669 else if (UseCRC32CIntrinsics) { 670 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 671 warning("CRC32C intrinsics are not available on this CPU"); 672 } 673 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 674 } 675 676 // The AES intrinsic stubs require AES instruction support (of course) 677 // but also require sse3 mode for instructions it use. 678 if (UseAES && (UseSSE > 2)) { 679 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 680 UseAESIntrinsics = true; 681 } 682 } else if (UseAESIntrinsics) { 683 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 684 warning("AES intrinsics are not available on this CPU"); 685 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 686 } 687 688 // GHASH/GCM intrinsics 689 if (UseCLMUL && (UseSSE > 2)) { 690 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 691 UseGHASHIntrinsics = true; 692 } 693 } else if (UseGHASHIntrinsics) { 694 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 695 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU"); 696 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 697 } 698 699 if (UseSHA) { 700 warning("SHA instructions are not available on this CPU"); 701 FLAG_SET_DEFAULT(UseSHA, false); 702 } 703 704 if (UseSHA1Intrinsics) { 705 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 706 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 707 } 708 709 if (UseSHA256Intrinsics) { 710 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 711 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 712 } 713 714 if (UseSHA512Intrinsics) { 715 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 716 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 717 } 718 719 if (UseAdler32Intrinsics) { 720 warning("Adler32Intrinsics not available on this CPU."); 721 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 722 } 723 724 // Adjust RTM (Restricted Transactional Memory) flags 725 if (!supports_rtm() && UseRTMLocking) { 726 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 727 // setting during arguments processing. See use_biased_locking(). 728 // VM_Version_init() is executed after UseBiasedLocking is used 729 // in Thread::allocate(). 730 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 731 } 732 733 #if INCLUDE_RTM_OPT 734 if (UseRTMLocking) { 735 if (is_intel_family_core()) { 736 if ((_model == CPU_MODEL_HASWELL_E3) || 737 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || 738 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) { 739 // currently a collision between SKL and HSW_E3 740 if (!UnlockExperimentalVMOptions && UseAVX < 3) { 741 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 742 } else { 743 warning("UseRTMLocking is only available as experimental option on this platform."); 744 } 745 } 746 } 747 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 748 // RTM locking should be used only for applications with 749 // high lock contention. For now we do not use it by default. 750 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 751 } 752 if (!is_power_of_2(RTMTotalCountIncrRate)) { 753 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 754 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 755 } 756 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 757 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 758 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 759 } 760 } else { // !UseRTMLocking 761 if (UseRTMForStackLocks) { 762 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 763 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 764 } 765 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 766 } 767 if (UseRTMDeopt) { 768 FLAG_SET_DEFAULT(UseRTMDeopt, false); 769 } 770 if (PrintPreciseRTMLockingStatistics) { 771 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 772 } 773 } 774 #else 775 if (UseRTMLocking) { 776 // Only C2 does RTM locking optimization. 777 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 778 // setting during arguments processing. See use_biased_locking(). 779 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 780 } 781 #endif 782 783 #ifdef COMPILER2 784 if (UseFPUForSpilling) { 785 if (UseSSE < 2) { 786 // Only supported with SSE2+ 787 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 788 } 789 } 790 if (MaxVectorSize > 0) { 791 if (!is_power_of_2(MaxVectorSize)) { 792 warning("MaxVectorSize must be a power of 2"); 793 FLAG_SET_DEFAULT(MaxVectorSize, 64); 794 } 795 if (MaxVectorSize > 64) { 796 FLAG_SET_DEFAULT(MaxVectorSize, 64); 797 } 798 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { 799 // 32 bytes vectors (in YMM) are only supported with AVX+ 800 FLAG_SET_DEFAULT(MaxVectorSize, 16); 801 } 802 if (UseSSE < 2) { 803 // Vectors (in XMM) are only supported with SSE2+ 804 FLAG_SET_DEFAULT(MaxVectorSize, 0); 805 } 806 #ifdef ASSERT 807 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { 808 tty->print_cr("State of YMM registers after signal handle:"); 809 int nreg = 2 LP64_ONLY(+2); 810 const char* ymm_name[4] = {"0", "7", "8", "15"}; 811 for (int i = 0; i < nreg; i++) { 812 tty->print("YMM%s:", ymm_name[i]); 813 for (int j = 7; j >=0; j--) { 814 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); 815 } 816 tty->cr(); 817 } 818 } 819 #endif 820 } 821 822 #ifdef _LP64 823 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 824 UseMultiplyToLenIntrinsic = true; 825 } 826 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 827 UseSquareToLenIntrinsic = true; 828 } 829 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 830 UseMulAddIntrinsic = true; 831 } 832 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 833 UseMontgomeryMultiplyIntrinsic = true; 834 } 835 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 836 UseMontgomerySquareIntrinsic = true; 837 } 838 #else 839 if (UseMultiplyToLenIntrinsic) { 840 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 841 warning("multiplyToLen intrinsic is not available in 32-bit VM"); 842 } 843 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); 844 } 845 if (UseMontgomeryMultiplyIntrinsic) { 846 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 847 warning("montgomeryMultiply intrinsic is not available in 32-bit VM"); 848 } 849 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false); 850 } 851 if (UseMontgomerySquareIntrinsic) { 852 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 853 warning("montgomerySquare intrinsic is not available in 32-bit VM"); 854 } 855 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false); 856 } 857 if (UseSquareToLenIntrinsic) { 858 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 859 warning("squareToLen intrinsic is not available in 32-bit VM"); 860 } 861 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false); 862 } 863 if (UseMulAddIntrinsic) { 864 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 865 warning("mulAdd intrinsic is not available in 32-bit VM"); 866 } 867 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false); 868 } 869 #endif 870 #endif // COMPILER2 871 872 // On new cpus instructions which update whole XMM register should be used 873 // to prevent partial register stall due to dependencies on high half. 874 // 875 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) 876 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) 877 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). 878 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). 879 880 if( is_amd() ) { // AMD cpus specific settings 881 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { 882 // Use it on new AMD cpus starting from Opteron. 883 UseAddressNop = true; 884 } 885 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { 886 // Use it on new AMD cpus starting from Opteron. 887 UseNewLongLShift = true; 888 } 889 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 890 if( supports_sse4a() ) { 891 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron 892 } else { 893 UseXmmLoadAndClearUpper = false; 894 } 895 } 896 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 897 if( supports_sse4a() ) { 898 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' 899 } else { 900 UseXmmRegToRegMoveAll = false; 901 } 902 } 903 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { 904 if( supports_sse4a() ) { 905 UseXmmI2F = true; 906 } else { 907 UseXmmI2F = false; 908 } 909 } 910 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { 911 if( supports_sse4a() ) { 912 UseXmmI2D = true; 913 } else { 914 UseXmmI2D = false; 915 } 916 } 917 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { 918 if( supports_sse4_2() && UseSSE >= 4 ) { 919 UseSSE42Intrinsics = true; 920 } 921 } 922 923 // some defaults for AMD family 15h 924 if ( cpu_family() == 0x15 ) { 925 // On family 15h processors default is no sw prefetch 926 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 927 AllocatePrefetchStyle = 0; 928 } 929 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW 930 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 931 AllocatePrefetchInstr = 3; 932 } 933 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy 934 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 935 UseXMMForArrayCopy = true; 936 } 937 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 938 UseUnalignedLoadStores = true; 939 } 940 } 941 942 #ifdef COMPILER2 943 if (MaxVectorSize > 16) { 944 // Limit vectors size to 16 bytes on current AMD cpus. 945 FLAG_SET_DEFAULT(MaxVectorSize, 16); 946 } 947 #endif // COMPILER2 948 } 949 950 if( is_intel() ) { // Intel cpus specific settings 951 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { 952 UseStoreImmI16 = false; // don't use it on Intel cpus 953 } 954 if( cpu_family() == 6 || cpu_family() == 15 ) { 955 if( FLAG_IS_DEFAULT(UseAddressNop) ) { 956 // Use it on all Intel cpus starting from PentiumPro 957 UseAddressNop = true; 958 } 959 } 960 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 961 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus 962 } 963 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 964 if( supports_sse3() ) { 965 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus 966 } else { 967 UseXmmRegToRegMoveAll = false; 968 } 969 } 970 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus 971 #ifdef COMPILER2 972 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { 973 // For new Intel cpus do the next optimization: 974 // don't align the beginning of a loop if there are enough instructions 975 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) 976 // in current fetch line (OptoLoopAlignment) or the padding 977 // is big (> MaxLoopPad). 978 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of 979 // generated NOP instructions. 11 is the largest size of one 980 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 981 MaxLoopPad = 11; 982 } 983 #endif // COMPILER2 984 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 985 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus 986 } 987 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus 988 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 989 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 990 } 991 } 992 if (supports_sse4_2() && UseSSE >= 4) { 993 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 994 UseSSE42Intrinsics = true; 995 } 996 } 997 } 998 if ((cpu_family() == 0x06) && 999 ((extended_cpu_model() == 0x36) || // Centerton 1000 (extended_cpu_model() == 0x37) || // Silvermont 1001 (extended_cpu_model() == 0x4D))) { 1002 #ifdef COMPILER2 1003 if (FLAG_IS_DEFAULT(OptoScheduling)) { 1004 OptoScheduling = true; 1005 } 1006 #endif 1007 if (supports_sse4_2()) { // Silvermont 1008 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1009 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 1010 } 1011 } 1012 } 1013 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { 1014 AllocatePrefetchInstr = 3; 1015 } 1016 } 1017 1018 // Use count leading zeros count instruction if available. 1019 if (supports_lzcnt()) { 1020 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { 1021 UseCountLeadingZerosInstruction = true; 1022 } 1023 } else if (UseCountLeadingZerosInstruction) { 1024 warning("lzcnt instruction is not available on this CPU"); 1025 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); 1026 } 1027 1028 // Use count trailing zeros instruction if available 1029 if (supports_bmi1()) { 1030 // tzcnt does not require VEX prefix 1031 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { 1032 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1033 // Don't use tzcnt if BMI1 is switched off on command line. 1034 UseCountTrailingZerosInstruction = false; 1035 } else { 1036 UseCountTrailingZerosInstruction = true; 1037 } 1038 } 1039 } else if (UseCountTrailingZerosInstruction) { 1040 warning("tzcnt instruction is not available on this CPU"); 1041 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); 1042 } 1043 1044 // BMI instructions (except tzcnt) use an encoding with VEX prefix. 1045 // VEX prefix is generated only when AVX > 0. 1046 if (supports_bmi1() && supports_avx()) { 1047 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1048 UseBMI1Instructions = true; 1049 } 1050 } else if (UseBMI1Instructions) { 1051 warning("BMI1 instructions are not available on this CPU (AVX is also required)"); 1052 FLAG_SET_DEFAULT(UseBMI1Instructions, false); 1053 } 1054 1055 if (supports_bmi2() && supports_avx()) { 1056 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { 1057 UseBMI2Instructions = true; 1058 } 1059 } else if (UseBMI2Instructions) { 1060 warning("BMI2 instructions are not available on this CPU (AVX is also required)"); 1061 FLAG_SET_DEFAULT(UseBMI2Instructions, false); 1062 } 1063 1064 // Use population count instruction if available. 1065 if (supports_popcnt()) { 1066 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 1067 UsePopCountInstruction = true; 1068 } 1069 } else if (UsePopCountInstruction) { 1070 warning("POPCNT instruction is not available on this CPU"); 1071 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 1072 } 1073 1074 // Use fast-string operations if available. 1075 if (supports_erms()) { 1076 if (FLAG_IS_DEFAULT(UseFastStosb)) { 1077 UseFastStosb = true; 1078 } 1079 } else if (UseFastStosb) { 1080 warning("fast-string operations are not available on this CPU"); 1081 FLAG_SET_DEFAULT(UseFastStosb, false); 1082 } 1083 1084 #ifdef COMPILER2 1085 if (FLAG_IS_DEFAULT(AlignVector)) { 1086 // Modern processors allow misaligned memory operations for vectors. 1087 AlignVector = !UseUnalignedLoadStores; 1088 } 1089 #endif // COMPILER2 1090 1091 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); 1092 1093 // set valid Prefetch instruction 1094 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; 1095 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; 1096 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; 1097 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; 1098 1099 // Allocation prefetch settings 1100 intx cache_line_size = prefetch_data_size(); 1101 if( cache_line_size > AllocatePrefetchStepSize ) 1102 AllocatePrefetchStepSize = cache_line_size; 1103 1104 assert(AllocatePrefetchLines > 0, "invalid value"); 1105 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 1106 AllocatePrefetchLines = 3; 1107 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 1108 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 1109 AllocateInstancePrefetchLines = 1; 1110 1111 AllocatePrefetchDistance = allocate_prefetch_distance(); 1112 AllocatePrefetchStyle = allocate_prefetch_style(); 1113 1114 if (is_intel() && cpu_family() == 6 && supports_sse3()) { 1115 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core 1116 #ifdef _LP64 1117 AllocatePrefetchDistance = 384; 1118 #else 1119 AllocatePrefetchDistance = 320; 1120 #endif 1121 } 1122 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus 1123 AllocatePrefetchDistance = 192; 1124 AllocatePrefetchLines = 4; 1125 } 1126 #ifdef COMPILER2 1127 if (supports_sse4_2()) { 1128 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { 1129 FLAG_SET_DEFAULT(UseFPUForSpilling, true); 1130 } 1131 } 1132 #endif 1133 } 1134 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); 1135 1136 #ifdef _LP64 1137 // Prefetch settings 1138 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 1139 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 1140 PrefetchFieldsAhead = prefetch_fields_ahead(); 1141 #endif 1142 1143 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 1144 (cache_line_size > ContendedPaddingWidth)) 1145 ContendedPaddingWidth = cache_line_size; 1146 1147 // This machine allows unaligned memory accesses 1148 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 1149 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 1150 } 1151 1152 #ifndef PRODUCT 1153 if (PrintMiscellaneous && Verbose) { 1154 tty->print_cr("Logical CPUs per core: %u", 1155 logical_processors_per_package()); 1156 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 1157 tty->print("UseSSE=%d", (int) UseSSE); 1158 if (UseAVX > 0) { 1159 tty->print(" UseAVX=%d", (int) UseAVX); 1160 } 1161 if (UseAES) { 1162 tty->print(" UseAES=1"); 1163 } 1164 #ifdef COMPILER2 1165 if (MaxVectorSize > 0) { 1166 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize); 1167 } 1168 #endif 1169 tty->cr(); 1170 tty->print("Allocation"); 1171 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { 1172 tty->print_cr(": no prefetching"); 1173 } else { 1174 tty->print(" prefetching: "); 1175 if (UseSSE == 0 && supports_3dnow_prefetch()) { 1176 tty->print("PREFETCHW"); 1177 } else if (UseSSE >= 1) { 1178 if (AllocatePrefetchInstr == 0) { 1179 tty->print("PREFETCHNTA"); 1180 } else if (AllocatePrefetchInstr == 1) { 1181 tty->print("PREFETCHT0"); 1182 } else if (AllocatePrefetchInstr == 2) { 1183 tty->print("PREFETCHT2"); 1184 } else if (AllocatePrefetchInstr == 3) { 1185 tty->print("PREFETCHW"); 1186 } 1187 } 1188 if (AllocatePrefetchLines > 1) { 1189 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 1190 } else { 1191 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 1192 } 1193 } 1194 1195 if (PrefetchCopyIntervalInBytes > 0) { 1196 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 1197 } 1198 if (PrefetchScanIntervalInBytes > 0) { 1199 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 1200 } 1201 if (PrefetchFieldsAhead > 0) { 1202 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 1203 } 1204 if (ContendedPaddingWidth > 0) { 1205 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 1206 } 1207 } 1208 #endif // !PRODUCT 1209 } 1210 1211 bool VM_Version::use_biased_locking() { 1212 #if INCLUDE_RTM_OPT 1213 // RTM locking is most useful when there is high lock contention and 1214 // low data contention. With high lock contention the lock is usually 1215 // inflated and biased locking is not suitable for that case. 1216 // RTM locking code requires that biased locking is off. 1217 // Note: we can't switch off UseBiasedLocking in get_processor_features() 1218 // because it is used by Thread::allocate() which is called before 1219 // VM_Version::initialize(). 1220 if (UseRTMLocking && UseBiasedLocking) { 1221 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 1222 FLAG_SET_DEFAULT(UseBiasedLocking, false); 1223 } else { 1224 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 1225 UseBiasedLocking = false; 1226 } 1227 } 1228 #endif 1229 return UseBiasedLocking; 1230 } 1231 1232 void VM_Version::initialize() { 1233 ResourceMark rm; 1234 // Making this stub must be FIRST use of assembler 1235 1236 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); 1237 if (stub_blob == NULL) { 1238 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); 1239 } 1240 CodeBuffer c(stub_blob); 1241 VM_Version_StubGenerator g(&c); 1242 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, 1243 g.generate_get_cpu_info()); 1244 1245 get_processor_features(); 1246 }