1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "code/codeCache.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "nativeInst_sparc.hpp"
30 #include "oops/oop.inline.hpp"
31 #include "runtime/handles.hpp"
32 #include "runtime/sharedRuntime.hpp"
33 #include "runtime/stubRoutines.hpp"
34 #include "utilities/ostream.hpp"
35 #ifdef COMPILER1
36 #include "c1/c1_Runtime1.hpp"
37 #endif
38
39 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) {
40 ResourceMark rm;
41 CodeBuffer buf(instaddr, 10 * BytesPerInstWord );
42 MacroAssembler* _masm = new MacroAssembler(&buf);
43 Register destreg;
44
45 destreg = inv_rd(*(unsigned int *)instaddr);
46 // Generate a the new sequence
47 _masm->patchable_sethi(x, destreg);
48 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord);
49 }
50
51 void NativeInstruction::verify_data64_sethi(address instaddr, intptr_t x) {
52 ResourceMark rm;
53 unsigned char buffer[10 * BytesPerInstWord];
54 CodeBuffer buf(buffer, 10 * BytesPerInstWord);
55 MacroAssembler masm(&buf);
56
57 Register destreg = inv_rd(*(unsigned int *)instaddr);
58 // Generate the proper sequence into a temporary buffer and compare
59 // it with the original sequence.
60 masm.patchable_sethi(x, destreg);
61 int len = buffer - masm.pc();
62 for (int i = 0; i < len; i++) {
63 assert(instaddr[i] == buffer[i], "instructions must match");
64 }
65 }
66
67 void NativeInstruction::verify() {
68 // make sure code pattern is actually an instruction address
69 address addr = addr_at(0);
70 if (addr == 0 || ((intptr_t)addr & 3) != 0) {
71 fatal("not an instruction address");
72 }
73 }
74
75 void NativeInstruction::print() {
76 tty->print_cr(INTPTR_FORMAT ": 0x%x", p2i(addr_at(0)), long_at(0));
77 }
78
79 void NativeInstruction::set_long_at(int offset, int i) {
80 address addr = addr_at(offset);
81 *(int*)addr = i;
82 ICache::invalidate_word(addr);
83 }
84
85 void NativeInstruction::set_jlong_at(int offset, jlong i) {
86 address addr = addr_at(offset);
87 *(jlong*)addr = i;
88 // Don't need to invalidate 2 words here, because
89 // the flush instruction operates on doublewords.
90 ICache::invalidate_word(addr);
91 }
92
93 void NativeInstruction::set_addr_at(int offset, address x) {
94 address addr = addr_at(offset);
95 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment");
96 *(uintptr_t*)addr = (uintptr_t)x;
97 // Don't need to invalidate 2 words here in the 64-bit case,
98 // because the flush instruction operates on doublewords.
99 ICache::invalidate_word(addr);
100 // The Intel code has this assertion for NativeCall::set_destination,
101 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset,
102 // NativeJump::set_jump_destination, and NativePushImm32::set_data
103 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction")
104 }
105
106 bool NativeInstruction::is_zero_test(Register ®) {
107 int x = long_at(0);
108 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3);
109 if (is_op3(x, temp, Assembler::arith_op) &&
110 inv_immed(x) && inv_rd(x) == G0) {
111 if (inv_rs1(x) == G0) {
112 reg = inv_rs2(x);
113 return true;
114 } else if (inv_rs2(x) == G0) {
115 reg = inv_rs1(x);
116 return true;
117 }
118 }
119 return false;
120 }
121
122 bool NativeInstruction::is_load_store_with_small_offset(Register reg) {
123 int x = long_at(0);
124 if (is_op(x, Assembler::ldst_op) &&
125 inv_rs1(x) == reg && inv_immed(x)) {
126 return true;
127 }
128 return false;
129 }
130
131 void NativeCall::verify() {
132 NativeInstruction::verify();
133 // make sure code pattern is actually a call instruction
134 if (!is_op(long_at(0), Assembler::call_op)) {
135 fatal("not a call");
136 }
137 }
138
139 void NativeCall::print() {
140 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, p2i(instruction_address()), p2i(destination()));
141 }
142
143
144 // MT-safe patching of a call instruction (and following word).
145 // First patches the second word, and then atomicly replaces
146 // the first word with the first new instruction word.
147 // Other processors might briefly see the old first word
148 // followed by the new second word. This is OK if the old
149 // second word is harmless, and the new second word may be
150 // harmlessly executed in the delay slot of the call.
151 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
152 assert(Patching_lock->is_locked() ||
153 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
154 assert (instr_addr != NULL, "illegal address for code patching");
155 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
156 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
157 int i0 = ((int*)code_buffer)[0];
158 int i1 = ((int*)code_buffer)[1];
159 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
160 assert(inv_op(*contention_addr) == Assembler::arith_op ||
161 *contention_addr == nop_instruction(),
162 "must not interfere with original call");
163 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
164 n_call->set_long_at(1*BytesPerInstWord, i1);
165 n_call->set_long_at(0*BytesPerInstWord, i0);
166 // NOTE: It is possible that another thread T will execute
167 // only the second patched word.
168 // In other words, since the original instruction is this
169 // call patching_stub; nop (NativeCall)
170 // and the new sequence from the buffer is this:
171 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
172 // what T will execute is this:
173 // call patching_stub; add %r, %lo(K), %r
174 // thereby putting garbage into %r before calling the patching stub.
175 // This is OK, because the patching stub ignores the value of %r.
176
177 // Make sure the first-patched instruction, which may co-exist
178 // briefly with the call, will do something harmless.
179 assert(inv_op(*contention_addr) == Assembler::arith_op ||
180 *contention_addr == nop_instruction(),
181 "must not interfere with original call");
182 }
183
184 // Similar to replace_mt_safe, but just changes the destination. The
185 // important thing is that free-running threads are able to execute this
186 // call instruction at all times. Thus, the displacement field must be
187 // instruction-word-aligned. This is always true on SPARC.
188 //
189 // Used in the runtime linkage of calls; see class CompiledIC.
190 void NativeCall::set_destination_mt_safe(address dest) {
191 assert(Patching_lock->is_locked() ||
192 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
193 // set_destination uses set_long_at which does the ICache::invalidate
194 set_destination(dest);
195 }
196
197 // Code for unit testing implementation of NativeCall class
198 void NativeCall::test() {
199 #ifdef ASSERT
200 ResourceMark rm;
201 CodeBuffer cb("test", 100, 100);
202 MacroAssembler* a = new MacroAssembler(&cb);
203 NativeCall *nc;
204 uint idx;
205 int offsets[] = {
206 0x0,
207 0xfffffff0,
208 0x7ffffff0,
209 0x80000000,
210 0x20,
211 0x4000,
212 };
213
214 VM_Version::allow_all();
215
216 a->call( a->pc(), relocInfo::none );
217 a->delayed()->nop();
218 nc = nativeCall_at( cb.insts_begin() );
219 nc->print();
220
221 nc = nativeCall_overwriting_at( nc->next_instruction_address() );
222 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
223 nc->set_destination( cb.insts_begin() + offsets[idx] );
224 assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test");
225 nc->print();
226 }
227
228 nc = nativeCall_before( cb.insts_begin() + 8 );
229 nc->print();
230
231 VM_Version::revert();
232 #endif
233 }
234 // End code for unit testing implementation of NativeCall class
235
236 //-------------------------------------------------------------------
237
238 #ifdef _LP64
239
240 void NativeFarCall::set_destination(address dest) {
241 // Address materialized in the instruction stream, so nothing to do.
242 return;
243 #if 0 // What we'd do if we really did want to change the destination
244 if (destination() == dest) {
245 return;
246 }
247 ResourceMark rm;
248 CodeBuffer buf(addr_at(0), instruction_size + 1);
249 MacroAssembler* _masm = new MacroAssembler(&buf);
250 // Generate the new sequence
251 AddressLiteral(dest);
252 _masm->jumpl_to(dest, O7, O7);
253 ICache::invalidate_range(addr_at(0), instruction_size );
254 #endif
255 }
256
257 void NativeFarCall::verify() {
258 // make sure code pattern is actually a jumpl_to instruction
259 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to");
260 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
261 nativeJump_at(addr_at(0))->verify();
262 }
263
264 bool NativeFarCall::is_call_at(address instr) {
265 return nativeInstruction_at(instr)->is_sethi();
266 }
267
268 void NativeFarCall::print() {
269 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, p2i(instruction_address()), p2i(destination()));
270 }
271
272 bool NativeFarCall::destination_is_compiled_verified_entry_point() {
273 nmethod* callee = CodeCache::find_nmethod(destination());
274 if (callee == NULL) {
275 return false;
276 } else {
277 return destination() == callee->verified_entry_point();
278 }
279 }
280
281 // MT-safe patching of a far call.
282 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) {
283 Unimplemented();
284 }
285
286 // Code for unit testing implementation of NativeFarCall class
287 void NativeFarCall::test() {
288 Unimplemented();
289 }
290 // End code for unit testing implementation of NativeFarCall class
291
292 #endif // _LP64
293
294 //-------------------------------------------------------------------
295
296
297 void NativeMovConstReg::verify() {
298 NativeInstruction::verify();
299 // make sure code pattern is actually a "set_metadata" synthetic instruction
300 // see MacroAssembler::set_oop()
301 int i0 = long_at(sethi_offset);
302 int i1 = long_at(add_offset);
303
304 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg"
305 Register rd = inv_rd(i0);
306 #ifndef _LP64
307 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
308 is_op3(i1, Assembler::add_op3, Assembler::arith_op) &&
309 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
310 rd == inv_rs1(i1) && rd == inv_rd(i1))) {
311 fatal("not a set_metadata");
312 }
313 #else
314 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
315 fatal("not a set_metadata");
316 }
317 #endif
318 }
319
320
321 void NativeMovConstReg::print() {
322 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, p2i(instruction_address()), data());
323 }
324
325
326 #ifdef _LP64
327 intptr_t NativeMovConstReg::data() const {
328 return data64(addr_at(sethi_offset), long_at(add_offset));
329 }
330 #else
331 intptr_t NativeMovConstReg::data() const {
332 return data32(long_at(sethi_offset), long_at(add_offset));
333 }
334 #endif
335
336
337 void NativeMovConstReg::set_data(intptr_t x) {
338 #ifdef _LP64
339 set_data64_sethi(addr_at(sethi_offset), x);
340 #else
341 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x));
342 #endif
343 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x));
344
345 // also store the value into an oop_Relocation cell, if any
346 CodeBlob* cb = CodeCache::find_blob(instruction_address());
347 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL;
348 if (nm != NULL) {
349 RelocIterator iter(nm, instruction_address(), next_instruction_address());
350 oop* oop_addr = NULL;
351 Metadata** metadata_addr = NULL;
352 while (iter.next()) {
353 if (iter.type() == relocInfo::oop_type) {
354 oop_Relocation *r = iter.oop_reloc();
355 if (oop_addr == NULL) {
356 oop_addr = r->oop_addr();
357 *oop_addr = cast_to_oop(x);
358 } else {
359 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
360 }
361 }
362 if (iter.type() == relocInfo::metadata_type) {
363 metadata_Relocation *r = iter.metadata_reloc();
364 if (metadata_addr == NULL) {
365 metadata_addr = r->metadata_addr();
366 *metadata_addr = (Metadata*)x;
367 } else {
368 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here");
369 }
370 }
371 }
372 }
373 }
374
375
376 // Code for unit testing implementation of NativeMovConstReg class
377 void NativeMovConstReg::test() {
378 #ifdef ASSERT
379 ResourceMark rm;
380 CodeBuffer cb("test", 100, 100);
381 MacroAssembler* a = new MacroAssembler(&cb);
382 NativeMovConstReg* nm;
383 uint idx;
384 int offsets[] = {
385 0x0,
386 0x7fffffff,
387 0x80000000,
388 0xffffffff,
389 0x20,
390 4096,
391 4097,
392 };
393
394 VM_Version::allow_all();
395
396 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
397 a->sethi(al1, I3);
398 a->add(I3, al1.low10(), I3);
399 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
400 a->sethi(al2, O2);
401 a->add(O2, al2.low10(), O2);
402
403 nm = nativeMovConstReg_at( cb.insts_begin() );
404 nm->print();
405
406 nm = nativeMovConstReg_at( nm->next_instruction_address() );
407 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
408 nm->set_data( offsets[idx] );
409 assert(nm->data() == offsets[idx], "check unit test");
410 }
411 nm->print();
412
413 VM_Version::revert();
414 #endif
415 }
416 // End code for unit testing implementation of NativeMovConstReg class
417
418 //-------------------------------------------------------------------
419
420 void NativeMovConstReg32::verify() {
421 NativeInstruction::verify();
422 // make sure code pattern is actually a "set_metadata" synthetic instruction
423 // see MacroAssembler::set_oop()
424 int i0 = long_at(sethi_offset);
425 int i1 = long_at(add_offset);
426
427 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg"
428 Register rd = inv_rd(i0);
429 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
430 fatal("not a set_metadata");
431 }
432 }
433
434
435 void NativeMovConstReg32::print() {
436 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
437 }
438
439
440 intptr_t NativeMovConstReg32::data() const {
441 return data32(long_at(sethi_offset), long_at(add_offset));
442 }
443
444
445 void NativeMovConstReg32::set_data(intptr_t x) {
446 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x));
447 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x));
448
449 // also store the value into an oop_Relocation cell, if any
450 CodeBlob* cb = CodeCache::find_blob(instruction_address());
451 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL;
452 if (nm != NULL) {
453 RelocIterator iter(nm, instruction_address(), next_instruction_address());
454 oop* oop_addr = NULL;
455 Metadata** metadata_addr = NULL;
456 while (iter.next()) {
457 if (iter.type() == relocInfo::oop_type) {
458 oop_Relocation *r = iter.oop_reloc();
459 if (oop_addr == NULL) {
460 oop_addr = r->oop_addr();
461 *oop_addr = cast_to_oop(x);
462 } else {
463 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
464 }
465 }
466 if (iter.type() == relocInfo::metadata_type) {
467 metadata_Relocation *r = iter.metadata_reloc();
468 if (metadata_addr == NULL) {
469 metadata_addr = r->metadata_addr();
470 *metadata_addr = (Metadata*)x;
471 } else {
472 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here");
473 }
474 }
475 }
476 }
477 }
478
479 //-------------------------------------------------------------------
480
481 void NativeMovConstRegPatching::verify() {
482 NativeInstruction::verify();
483 // Make sure code pattern is sethi/nop/add.
484 int i0 = long_at(sethi_offset);
485 int i1 = long_at(nop_offset);
486 int i2 = long_at(add_offset);
487 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
488
489 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg"
490 // The casual reader should note that on Sparc a nop is a special case if sethi
491 // in which the destination register is %g0.
492 Register rd0 = inv_rd(i0);
493 Register rd1 = inv_rd(i1);
494 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 &&
495 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi
496 is_op3(i2, Assembler::add_op3, Assembler::arith_op) &&
497 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) &&
498 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) {
499 fatal("not a set_metadata");
500 }
501 }
502
503
504 void NativeMovConstRegPatching::print() {
505 tty->print_cr(INTPTR_FORMAT ": mov reg, 0x%x", p2i(instruction_address()), data());
506 }
507
508
509 int NativeMovConstRegPatching::data() const {
510 #ifdef _LP64
511 return data64(addr_at(sethi_offset), long_at(add_offset));
512 #else
513 return data32(long_at(sethi_offset), long_at(add_offset));
514 #endif
515 }
516
517
518 void NativeMovConstRegPatching::set_data(int x) {
519 #ifdef _LP64
520 set_data64_sethi(addr_at(sethi_offset), x);
521 #else
522 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x));
523 #endif
524 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x));
525
526 // also store the value into an oop_Relocation cell, if any
527 CodeBlob* cb = CodeCache::find_blob(instruction_address());
528 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL;
529 if (nm != NULL) {
530 RelocIterator iter(nm, instruction_address(), next_instruction_address());
531 oop* oop_addr = NULL;
532 Metadata** metadata_addr = NULL;
533 while (iter.next()) {
534 if (iter.type() == relocInfo::oop_type) {
535 oop_Relocation *r = iter.oop_reloc();
536 if (oop_addr == NULL) {
537 oop_addr = r->oop_addr();
538 *oop_addr = cast_to_oop(x);
539 } else {
540 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
541 }
542 }
543 if (iter.type() == relocInfo::metadata_type) {
544 metadata_Relocation *r = iter.metadata_reloc();
545 if (metadata_addr == NULL) {
546 metadata_addr = r->metadata_addr();
547 *metadata_addr = (Metadata*)x;
548 } else {
549 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here");
550 }
551 }
552 }
553 }
554 }
555
556
557 // Code for unit testing implementation of NativeMovConstRegPatching class
558 void NativeMovConstRegPatching::test() {
559 #ifdef ASSERT
560 ResourceMark rm;
561 CodeBuffer cb("test", 100, 100);
562 MacroAssembler* a = new MacroAssembler(&cb);
563 NativeMovConstRegPatching* nm;
564 uint idx;
565 int offsets[] = {
566 0x0,
567 0x7fffffff,
568 0x80000000,
569 0xffffffff,
570 0x20,
571 4096,
572 4097,
573 };
574
575 VM_Version::allow_all();
576
577 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
578 a->sethi(al1, I3);
579 a->nop();
580 a->add(I3, al1.low10(), I3);
581 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
582 a->sethi(al2, O2);
583 a->nop();
584 a->add(O2, al2.low10(), O2);
585
586 nm = nativeMovConstRegPatching_at( cb.insts_begin() );
587 nm->print();
588
589 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() );
590 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
591 nm->set_data( offsets[idx] );
592 assert(nm->data() == offsets[idx], "check unit test");
593 }
594 nm->print();
595
596 VM_Version::revert();
597 #endif // ASSERT
598 }
599 // End code for unit testing implementation of NativeMovConstRegPatching class
600
601
602 //-------------------------------------------------------------------
603
604
605 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
606 Untested("copy_instruction_to");
607 int instruction_size = next_instruction_address() - instruction_address();
608 for (int i = 0; i < instruction_size; i += BytesPerInstWord) {
609 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i);
610 }
611 }
612
613
614 void NativeMovRegMem::verify() {
615 NativeInstruction::verify();
616 // make sure code pattern is actually a "ld" or "st" of some sort.
617 int i0 = long_at(0);
618 int op3 = inv_op3(i0);
619
620 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok");
621
622 if (!(is_op(i0, Assembler::ldst_op) &&
623 inv_immed(i0) &&
624 0 != (op3 < op3_ldst_int_limit
625 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
626 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))))
627 {
628 int i1 = long_at(ldst_offset);
629 Register rd = inv_rd(i0);
630
631 op3 = inv_op3(i1);
632 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
633 0 != (op3 < op3_ldst_int_limit
634 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
635 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
636 fatal("not a ld* or st* op");
637 }
638 }
639 }
640
641
642 void NativeMovRegMem::print() {
643 if (is_immediate()) {
644 // offset is a signed 13-bit immediate, so casting it to int will not lose significant bits
645 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %d]", p2i(instruction_address()), (int)offset());
646 } else {
647 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", p2i(instruction_address()));
648 }
649 }
650
651
652 // Code for unit testing implementation of NativeMovRegMem class
653 void NativeMovRegMem::test() {
654 #ifdef ASSERT
655 ResourceMark rm;
656 CodeBuffer cb("test", 1000, 1000);
657 MacroAssembler* a = new MacroAssembler(&cb);
658 NativeMovRegMem* nm;
659 uint idx = 0;
660 uint idx1;
661 int offsets[] = {
662 0x0,
663 0xffffffff,
664 0x7fffffff,
665 0x80000000,
666 4096,
667 4097,
668 0x20,
669 0x4000,
670 };
671
672 VM_Version::allow_all();
673
674 AddressLiteral al1(0xffffffff, relocInfo::external_word_type);
675 AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type);
676 a->ldsw( G5, al1.low10(), G4 ); idx++;
677 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
678 a->ldsw( G5, I3, G4 ); idx++;
679 a->ldsb( G5, al1.low10(), G4 ); idx++;
680 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
681 a->ldsb( G5, I3, G4 ); idx++;
682 a->ldsh( G5, al1.low10(), G4 ); idx++;
683 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
684 a->ldsh( G5, I3, G4 ); idx++;
685 a->lduw( G5, al1.low10(), G4 ); idx++;
686 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
687 a->lduw( G5, I3, G4 ); idx++;
688 a->ldub( G5, al1.low10(), G4 ); idx++;
689 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
690 a->ldub( G5, I3, G4 ); idx++;
691 a->lduh( G5, al1.low10(), G4 ); idx++;
692 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
693 a->lduh( G5, I3, G4 ); idx++;
694 a->ldx( G5, al1.low10(), G4 ); idx++;
695 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
696 a->ldx( G5, I3, G4 ); idx++;
697 a->ldd( G5, al1.low10(), G4 ); idx++;
698 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
699 a->ldd( G5, I3, G4 ); idx++;
700 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
701 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
702 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
703
704 a->stw( G5, G4, al1.low10() ); idx++;
705 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
706 a->stw( G5, G4, I3 ); idx++;
707 a->stb( G5, G4, al1.low10() ); idx++;
708 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
709 a->stb( G5, G4, I3 ); idx++;
710 a->sth( G5, G4, al1.low10() ); idx++;
711 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
712 a->sth( G5, G4, I3 ); idx++;
713 a->stx( G5, G4, al1.low10() ); idx++;
714 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
715 a->stx( G5, G4, I3 ); idx++;
716 a->std( G5, G4, al1.low10() ); idx++;
717 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
718 a->std( G5, G4, I3 ); idx++;
719 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
720 a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
721 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
722
723 nm = nativeMovRegMem_at( cb.insts_begin() );
724 nm->print();
725 nm->set_offset( low10(0) );
726 nm->print();
727 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
728 nm->print();
729
730 while (--idx) {
731 nm = nativeMovRegMem_at( nm->next_instruction_address() );
732 nm->print();
733 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
734 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
735 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
736 "check unit test");
737 nm->print();
738 }
739 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
740 nm->print();
741 }
742
743 VM_Version::revert();
744 #endif // ASSERT
745 }
746
747 // End code for unit testing implementation of NativeMovRegMem class
748
749
750 //--------------------------------------------------------------------------------
751
752
753 void NativeJump::verify() {
754 NativeInstruction::verify();
755 int i0 = long_at(sethi_offset);
756 int i1 = long_at(jmpl_offset);
757 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
758 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg"
759 Register rd = inv_rd(i0);
760 #ifndef _LP64
761 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
762 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) ||
763 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) &&
764 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
765 rd == inv_rs1(i1))) {
766 fatal("not a jump_to instruction");
767 }
768 #else
769 // In LP64, the jump instruction location varies for non relocatable
770 // jumps, for example is could be sethi, xor, jmp instead of the
771 // 7 instructions for sethi. So let's check sethi only.
772 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
773 fatal("not a jump_to instruction");
774 }
775 #endif
776 }
777
778
779 void NativeJump::print() {
780 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, p2i(instruction_address()), p2i(jump_destination()));
781 }
782
783
784 // Code for unit testing implementation of NativeJump class
785 void NativeJump::test() {
786 #ifdef ASSERT
787 ResourceMark rm;
788 CodeBuffer cb("test", 100, 100);
789 MacroAssembler* a = new MacroAssembler(&cb);
790 NativeJump* nj;
791 uint idx;
792 int offsets[] = {
793 0x0,
794 0xffffffff,
795 0x7fffffff,
796 0x80000000,
797 4096,
798 4097,
799 0x20,
800 0x4000,
801 };
802
803 VM_Version::allow_all();
804
805 AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type);
806 a->sethi(al, I3);
807 a->jmpl(I3, al.low10(), G0, RelocationHolder::none);
808 a->delayed()->nop();
809 a->sethi(al, I3);
810 a->jmpl(I3, al.low10(), L3, RelocationHolder::none);
811 a->delayed()->nop();
812
813 nj = nativeJump_at( cb.insts_begin() );
814 nj->print();
815
816 nj = nativeJump_at( nj->next_instruction_address() );
817 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
818 nj->set_jump_destination( nj->instruction_address() + offsets[idx] );
819 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test");
820 nj->print();
821 }
822
823 VM_Version::revert();
824 #endif // ASSERT
825 }
826 // End code for unit testing implementation of NativeJump class
827
828
829 void NativeJump::insert(address code_pos, address entry) {
830 Unimplemented();
831 }
832
833 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
834 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
835 // Atomic write can be only with 1 word.
836 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
837 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere
838 // in the header of the nmethod, within a short branch's span of the patch point.
839 // Set up the jump sequence using NativeJump::insert, and then use an annulled
840 // unconditional branch at the target site (an atomic 1-word update).
841 // Limitations: You can only patch nmethods, with any given nmethod patched at
842 // most once, and the patch must be in the nmethod's header.
843 // It's messy, but you can ask the CodeCache for the nmethod containing the
844 // target address.
845
846 // %%%%% For now, do something MT-stupid:
847 ResourceMark rm;
848 int code_size = 1 * BytesPerInstWord;
849 CodeBuffer cb(verified_entry, code_size + 1);
850 MacroAssembler* a = new MacroAssembler(&cb);
851 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler
852 ICache::invalidate_range(verified_entry, code_size);
853 }
854
855
856 void NativeIllegalInstruction::insert(address code_pos) {
857 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
858 nii->set_long_at(0, illegal_instruction());
859 }
860
861 static int illegal_instruction_bits = 0;
862
863 int NativeInstruction::illegal_instruction() {
864 if (illegal_instruction_bits == 0) {
865 ResourceMark rm;
866 char buf[40];
867 CodeBuffer cbuf((address)&buf[0], 20);
868 MacroAssembler* a = new MacroAssembler(&cbuf);
869 address ia = a->pc();
870 a->trap(ST_RESERVED_FOR_USER_0 + 1);
871 int bits = *(int*)ia;
872 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
873 illegal_instruction_bits = bits;
874 assert(illegal_instruction_bits != 0, "oops");
875 }
876 return illegal_instruction_bits;
877 }
878
879 static int ic_miss_trap_bits = 0;
880
881 bool NativeInstruction::is_ic_miss_trap() {
882 if (ic_miss_trap_bits == 0) {
883 ResourceMark rm;
884 char buf[40];
885 CodeBuffer cbuf((address)&buf[0], 20);
886 MacroAssembler* a = new MacroAssembler(&cbuf);
887 address ia = a->pc();
888 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2);
889 int bits = *(int*)ia;
890 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
891 ic_miss_trap_bits = bits;
892 assert(ic_miss_trap_bits != 0, "oops");
893 }
894 return long_at(0) == ic_miss_trap_bits;
895 }
896
897
898 bool NativeInstruction::is_illegal() {
899 if (illegal_instruction_bits == 0) {
900 return false;
901 }
902 return long_at(0) == illegal_instruction_bits;
903 }
904
905
906 void NativeGeneralJump::verify() {
907 assert(((NativeInstruction *)this)->is_jump() ||
908 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
909 }
910
911
912 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
913 Assembler::Condition condition = Assembler::always;
914 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) |
915 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22);
916 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos);
917 ni->set_long_at(0, x);
918 }
919
920
921 // MT-safe patching of a jmp instruction (and following word).
922 // First patches the second word, and then atomicly replaces
923 // the first word with the first new instruction word.
924 // Other processors might briefly see the old first word
925 // followed by the new second word. This is OK if the old
926 // second word is harmless, and the new second word may be
927 // harmlessly executed in the delay slot of the call.
928 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
929 assert(Patching_lock->is_locked() ||
930 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
931 assert (instr_addr != NULL, "illegal address for code patching");
932 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call
933 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
934 int i0 = ((int*)code_buffer)[0];
935 int i1 = ((int*)code_buffer)[1];
936 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
937 assert(inv_op(*contention_addr) == Assembler::arith_op ||
938 *contention_addr == nop_instruction(),
939 "must not interfere with original call");
940 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
941 h_jump->set_long_at(1*BytesPerInstWord, i1);
942 h_jump->set_long_at(0*BytesPerInstWord, i0);
943 // NOTE: It is possible that another thread T will execute
944 // only the second patched word.
945 // In other words, since the original instruction is this
946 // jmp patching_stub; nop (NativeGeneralJump)
947 // and the new sequence from the buffer is this:
948 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
949 // what T will execute is this:
950 // jmp patching_stub; add %r, %lo(K), %r
951 // thereby putting garbage into %r before calling the patching stub.
952 // This is OK, because the patching stub ignores the value of %r.
953
954 // Make sure the first-patched instruction, which may co-exist
955 // briefly with the call, will do something harmless.
956 assert(inv_op(*contention_addr) == Assembler::arith_op ||
957 *contention_addr == nop_instruction(),
958 "must not interfere with original call");
959 }