1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 attributes.set_rex_vex_w_reverted();
1244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1245 emit_int8(0x58);
1246 emit_int8((unsigned char)(0xC0 | encode));
1247 }
1248
1249 void Assembler::addsd(XMMRegister dst, Address src) {
1250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1251 InstructionMark im(this);
1252 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1253 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1254 attributes.set_rex_vex_w_reverted();
1255 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1256 emit_int8(0x58);
1257 emit_operand(dst, src);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1264 emit_int8(0x58);
1265 emit_int8((unsigned char)(0xC0 | encode));
1266 }
1267
1268 void Assembler::addss(XMMRegister dst, Address src) {
1269 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1270 InstructionMark im(this);
1271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1272 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1273 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1274 emit_int8(0x58);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, Address src) {
1279 assert(VM_Version::supports_aes(), "");
1280 InstructionMark im(this);
1281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1282 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1283 emit_int8((unsigned char)0xDE);
1284 emit_operand(dst, src);
1285 }
1286
1287 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1288 assert(VM_Version::supports_aes(), "");
1289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1291 emit_int8((unsigned char)0xDE);
1292 emit_int8(0xC0 | encode);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1296 assert(VM_Version::supports_aes(), "");
1297 InstructionMark im(this);
1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1300 emit_int8((unsigned char)0xDF);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1308 emit_int8((unsigned char)0xDF);
1309 emit_int8((unsigned char)(0xC0 | encode));
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDC);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDC);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, Address src) {
1330 assert(VM_Version::supports_aes(), "");
1331 InstructionMark im(this);
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDD);
1335 emit_operand(dst, src);
1336 }
1337
1338 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1342 emit_int8((unsigned char)0xDD);
1343 emit_int8((unsigned char)(0xC0 | encode));
1344 }
1345
1346 void Assembler::andl(Address dst, int32_t imm32) {
1347 InstructionMark im(this);
1348 prefix(dst);
1349 emit_int8((unsigned char)0x81);
1350 emit_operand(rsp, dst, 4);
1351 emit_int32(imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, int32_t imm32) {
1355 prefix(dst);
1356 emit_arith(0x81, 0xE0, dst, imm32);
1357 }
1358
1359 void Assembler::andl(Register dst, Address src) {
1360 InstructionMark im(this);
1361 prefix(src, dst);
1362 emit_int8(0x23);
1363 emit_operand(dst, src);
1364 }
1365
1366 void Assembler::andl(Register dst, Register src) {
1367 (void) prefix_and_encode(dst->encoding(), src->encoding());
1368 emit_arith(0x23, 0xC0, dst, src);
1369 }
1370
1371 void Assembler::andnl(Register dst, Register src1, Register src2) {
1372 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1374 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1375 emit_int8((unsigned char)0xF2);
1376 emit_int8((unsigned char)(0xC0 | encode));
1377 }
1378
1379 void Assembler::andnl(Register dst, Register src1, Address src2) {
1380 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1381 InstructionMark im(this);
1382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1383 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1384 emit_int8((unsigned char)0xF2);
1385 emit_operand(dst, src2);
1386 }
1387
1388 void Assembler::bsfl(Register dst, Register src) {
1389 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1390 emit_int8(0x0F);
1391 emit_int8((unsigned char)0xBC);
1392 emit_int8((unsigned char)(0xC0 | encode));
1393 }
1394
1395 void Assembler::bsrl(Register dst, Register src) {
1396 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1397 emit_int8(0x0F);
1398 emit_int8((unsigned char)0xBD);
1399 emit_int8((unsigned char)(0xC0 | encode));
1400 }
1401
1402 void Assembler::bswapl(Register reg) { // bswap
1403 int encode = prefix_and_encode(reg->encoding());
1404 emit_int8(0x0F);
1405 emit_int8((unsigned char)(0xC8 | encode));
1406 }
1407
1408 void Assembler::blsil(Register dst, Register src) {
1409 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1410 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1411 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1412 emit_int8((unsigned char)0xF3);
1413 emit_int8((unsigned char)(0xC0 | encode));
1414 }
1415
1416 void Assembler::blsil(Register dst, Address src) {
1417 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1418 InstructionMark im(this);
1419 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1420 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1421 emit_int8((unsigned char)0xF3);
1422 emit_operand(rbx, src);
1423 }
1424
1425 void Assembler::blsmskl(Register dst, Register src) {
1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1428 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1429 emit_int8((unsigned char)0xF3);
1430 emit_int8((unsigned char)(0xC0 | encode));
1431 }
1432
1433 void Assembler::blsmskl(Register dst, Address src) {
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 InstructionMark im(this);
1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1437 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rdx, src);
1440 }
1441
1442 void Assembler::blsrl(Register dst, Register src) {
1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1445 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1446 emit_int8((unsigned char)0xF3);
1447 emit_int8((unsigned char)(0xC0 | encode));
1448 }
1449
1450 void Assembler::blsrl(Register dst, Address src) {
1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1452 InstructionMark im(this);
1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1454 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1455 emit_int8((unsigned char)0xF3);
1456 emit_operand(rcx, src);
1457 }
1458
1459 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1460 // suspect disp32 is always good
1461 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1462
1463 if (L.is_bound()) {
1464 const int long_size = 5;
1465 int offs = (int)( target(L) - pc() );
1466 assert(offs <= 0, "assembler error");
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 emit_int8((unsigned char)0xE8);
1470 emit_data(offs - long_size, rtype, operand);
1471 } else {
1472 InstructionMark im(this);
1473 // 1110 1000 #32-bit disp
1474 L.add_patch_at(code(), locator());
1475
1476 emit_int8((unsigned char)0xE8);
1477 emit_data(int(0), rtype, operand);
1478 }
1479 }
1480
1481 void Assembler::call(Register dst) {
1482 int encode = prefix_and_encode(dst->encoding());
1483 emit_int8((unsigned char)0xFF);
1484 emit_int8((unsigned char)(0xD0 | encode));
1485 }
1486
1487
1488 void Assembler::call(Address adr) {
1489 InstructionMark im(this);
1490 prefix(adr);
1491 emit_int8((unsigned char)0xFF);
1492 emit_operand(rdx, adr);
1493 }
1494
1495 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1496 assert(entry != NULL, "call most probably wrong");
1497 InstructionMark im(this);
1498 emit_int8((unsigned char)0xE8);
1499 intptr_t disp = entry - (pc() + sizeof(int32_t));
1500 assert(is_simm32(disp), "must be 32bit offset (call2)");
1501 // Technically, should use call32_operand, but this format is
1502 // implied by the fact that we're emitting a call instruction.
1503
1504 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1505 emit_data((int) disp, rspec, operand);
1506 }
1507
1508 void Assembler::cdql() {
1509 emit_int8((unsigned char)0x99);
1510 }
1511
1512 void Assembler::cld() {
1513 emit_int8((unsigned char)0xFC);
1514 }
1515
1516 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1517 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1518 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1519 emit_int8(0x0F);
1520 emit_int8(0x40 | cc);
1521 emit_int8((unsigned char)(0xC0 | encode));
1522 }
1523
1524
1525 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1526 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1527 prefix(src, dst);
1528 emit_int8(0x0F);
1529 emit_int8(0x40 | cc);
1530 emit_operand(dst, src);
1531 }
1532
1533 void Assembler::cmpb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_int8((unsigned char)0x80);
1537 emit_operand(rdi, dst, 1);
1538 emit_int8(imm8);
1539 }
1540
1541 void Assembler::cmpl(Address dst, int32_t imm32) {
1542 InstructionMark im(this);
1543 prefix(dst);
1544 emit_int8((unsigned char)0x81);
1545 emit_operand(rdi, dst, 4);
1546 emit_int32(imm32);
1547 }
1548
1549 void Assembler::cmpl(Register dst, int32_t imm32) {
1550 prefix(dst);
1551 emit_arith(0x81, 0xF8, dst, imm32);
1552 }
1553
1554 void Assembler::cmpl(Register dst, Register src) {
1555 (void) prefix_and_encode(dst->encoding(), src->encoding());
1556 emit_arith(0x3B, 0xC0, dst, src);
1557 }
1558
1559 void Assembler::cmpl(Register dst, Address src) {
1560 InstructionMark im(this);
1561 prefix(src, dst);
1562 emit_int8((unsigned char)0x3B);
1563 emit_operand(dst, src);
1564 }
1565
1566 void Assembler::cmpw(Address dst, int imm16) {
1567 InstructionMark im(this);
1568 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1569 emit_int8(0x66);
1570 emit_int8((unsigned char)0x81);
1571 emit_operand(rdi, dst, 2);
1572 emit_int16(imm16);
1573 }
1574
1575 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1576 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1577 // The ZF is set if the compared values were equal, and cleared otherwise.
1578 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1579 InstructionMark im(this);
1580 prefix(adr, reg);
1581 emit_int8(0x0F);
1582 emit_int8((unsigned char)0xB1);
1583 emit_operand(reg, adr);
1584 }
1585
1586 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1587 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1588 // The ZF is set if the compared values were equal, and cleared otherwise.
1589 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1590 InstructionMark im(this);
1591 prefix(adr, reg, true);
1592 emit_int8(0x0F);
1593 emit_int8((unsigned char)0xB0);
1594 emit_operand(reg, adr);
1595 }
1596
1597 void Assembler::comisd(XMMRegister dst, Address src) {
1598 // NOTE: dbx seems to decode this as comiss even though the
1599 // 0x66 is there. Strangly ucomisd comes out correct
1600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1601 InstructionMark im(this);
1602 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1604 attributes.set_rex_vex_w_reverted();
1605 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1606 emit_int8(0x2F);
1607 emit_operand(dst, src);
1608 }
1609
1610 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1613 attributes.set_rex_vex_w_reverted();
1614 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1615 emit_int8(0x2F);
1616 emit_int8((unsigned char)(0xC0 | encode));
1617 }
1618
1619 void Assembler::comiss(XMMRegister dst, Address src) {
1620 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1621 InstructionMark im(this);
1622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1623 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1624 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1625 emit_int8(0x2F);
1626 emit_operand(dst, src);
1627 }
1628
1629 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1632 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1633 emit_int8(0x2F);
1634 emit_int8((unsigned char)(0xC0 | encode));
1635 }
1636
1637 void Assembler::cpuid() {
1638 emit_int8(0x0F);
1639 emit_int8((unsigned char)0xA2);
1640 }
1641
1642 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1643 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1644 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1645 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1646 //
1647 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1648 //
1649 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1650 //
1651 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1652 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1653 assert(VM_Version::supports_sse4_2(), "");
1654 int8_t w = 0x01;
1655 Prefix p = Prefix_EMPTY;
1656
1657 emit_int8((int8_t)0xF2);
1658 switch (sizeInBytes) {
1659 case 1:
1660 w = 0;
1661 break;
1662 case 2:
1663 case 4:
1664 break;
1665 LP64_ONLY(case 8:)
1666 // This instruction is not valid in 32 bits
1667 // Note:
1668 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1669 //
1670 // Page B - 72 Vol. 2C says
1671 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1672 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1673 // F0!!!
1674 // while 3 - 208 Vol. 2A
1675 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1676 //
1677 // the 0 on a last bit is reserved for a different flavor of this instruction :
1678 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1679 p = REX_W;
1680 break;
1681 default:
1682 assert(0, "Unsupported value for a sizeInBytes argument");
1683 break;
1684 }
1685 LP64_ONLY(prefix(crc, v, p);)
1686 emit_int8((int8_t)0x0F);
1687 emit_int8(0x38);
1688 emit_int8((int8_t)(0xF0 | w));
1689 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1690 }
1691
1692 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1693 assert(VM_Version::supports_sse4_2(), "");
1694 InstructionMark im(this);
1695 int8_t w = 0x01;
1696 Prefix p = Prefix_EMPTY;
1697
1698 emit_int8((int8_t)0xF2);
1699 switch (sizeInBytes) {
1700 case 1:
1701 w = 0;
1702 break;
1703 case 2:
1704 case 4:
1705 break;
1706 LP64_ONLY(case 8:)
1707 // This instruction is not valid in 32 bits
1708 p = REX_W;
1709 break;
1710 default:
1711 assert(0, "Unsupported value for a sizeInBytes argument");
1712 break;
1713 }
1714 LP64_ONLY(prefix(crc, adr, p);)
1715 emit_int8((int8_t)0x0F);
1716 emit_int8(0x38);
1717 emit_int8((int8_t)(0xF0 | w));
1718 emit_operand(crc, adr);
1719 }
1720
1721 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1724 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1725 emit_int8((unsigned char)0xE6);
1726 emit_int8((unsigned char)(0xC0 | encode));
1727 }
1728
1729 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1731 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1732 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1733 emit_int8(0x5B);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1740 attributes.set_rex_vex_w_reverted();
1741 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1742 emit_int8(0x5A);
1743 emit_int8((unsigned char)(0xC0 | encode));
1744 }
1745
1746 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 InstructionMark im(this);
1749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1751 attributes.set_rex_vex_w_reverted();
1752 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x5A);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1761 emit_int8(0x2A);
1762 emit_int8((unsigned char)(0xC0 | encode));
1763 }
1764
1765 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 InstructionMark im(this);
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1770 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_operand(dst, src);
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1779 emit_int8(0x2A);
1780 emit_int8((unsigned char)(0xC0 | encode));
1781 }
1782
1783 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1784 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1785 InstructionMark im(this);
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1788 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_operand(dst, src);
1791 }
1792
1793 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x2A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_int8((unsigned char)(0xC0 | encode));
1807 }
1808
1809 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionMark im(this);
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1813 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1814 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x5A);
1816 emit_operand(dst, src);
1817 }
1818
1819
1820 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2C);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1839 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1840 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1841 emit_int8((unsigned char)0xE6);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::decl(Address dst) {
1846 // Don't use it directly. Use MacroAssembler::decrement() instead.
1847 InstructionMark im(this);
1848 prefix(dst);
1849 emit_int8((unsigned char)0xFF);
1850 emit_operand(rcx, dst);
1851 }
1852
1853 void Assembler::divsd(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1858 attributes.set_rex_vex_w_reverted();
1859 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 attributes.set_rex_vex_w_reverted();
1868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1869 emit_int8(0x5E);
1870 emit_int8((unsigned char)(0xC0 | encode));
1871 }
1872
1873 void Assembler::divss(XMMRegister dst, Address src) {
1874 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1875 InstructionMark im(this);
1876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1878 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879 emit_int8(0x5E);
1880 emit_operand(dst, src);
1881 }
1882
1883 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1884 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1886 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1887 emit_int8(0x5E);
1888 emit_int8((unsigned char)(0xC0 | encode));
1889 }
1890
1891 void Assembler::emms() {
1892 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1893 emit_int8(0x0F);
1894 emit_int8(0x77);
1895 }
1896
1897 void Assembler::hlt() {
1898 emit_int8((unsigned char)0xF4);
1899 }
1900
1901 void Assembler::idivl(Register src) {
1902 int encode = prefix_and_encode(src->encoding());
1903 emit_int8((unsigned char)0xF7);
1904 emit_int8((unsigned char)(0xF8 | encode));
1905 }
1906
1907 void Assembler::divl(Register src) { // Unsigned
1908 int encode = prefix_and_encode(src->encoding());
1909 emit_int8((unsigned char)0xF7);
1910 emit_int8((unsigned char)(0xF0 | encode));
1911 }
1912
1913 void Assembler::imull(Register src) {
1914 int encode = prefix_and_encode(src->encoding());
1915 emit_int8((unsigned char)0xF7);
1916 emit_int8((unsigned char)(0xE8 | encode));
1917 }
1918
1919 void Assembler::imull(Register dst, Register src) {
1920 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921 emit_int8(0x0F);
1922 emit_int8((unsigned char)0xAF);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926
1927 void Assembler::imull(Register dst, Register src, int value) {
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 if (is8bit(value)) {
1930 emit_int8(0x6B);
1931 emit_int8((unsigned char)(0xC0 | encode));
1932 emit_int8(value & 0xFF);
1933 } else {
1934 emit_int8(0x69);
1935 emit_int8((unsigned char)(0xC0 | encode));
1936 emit_int32(value);
1937 }
1938 }
1939
1940 void Assembler::imull(Register dst, Address src) {
1941 InstructionMark im(this);
1942 prefix(src, dst);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char) 0xAF);
1945 emit_operand(dst, src);
1946 }
1947
1948
1949 void Assembler::incl(Address dst) {
1950 // Don't use it directly. Use MacroAssembler::increment() instead.
1951 InstructionMark im(this);
1952 prefix(dst);
1953 emit_int8((unsigned char)0xFF);
1954 emit_operand(rax, dst);
1955 }
1956
1957 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1958 InstructionMark im(this);
1959 assert((0 <= cc) && (cc < 16), "illegal cc");
1960 if (L.is_bound()) {
1961 address dst = target(L);
1962 assert(dst != NULL, "jcc most probably wrong");
1963
1964 const int short_size = 2;
1965 const int long_size = 6;
1966 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1967 if (maybe_short && is8bit(offs - short_size)) {
1968 // 0111 tttn #8-bit disp
1969 emit_int8(0x70 | cc);
1970 emit_int8((offs - short_size) & 0xFF);
1971 } else {
1972 // 0000 1111 1000 tttn #32-bit disp
1973 assert(is_simm32(offs - long_size),
1974 "must be 32bit offset (call4)");
1975 emit_int8(0x0F);
1976 emit_int8((unsigned char)(0x80 | cc));
1977 emit_int32(offs - long_size);
1978 }
1979 } else {
1980 // Note: could eliminate cond. jumps to this jump if condition
1981 // is the same however, seems to be rather unlikely case.
1982 // Note: use jccb() if label to be bound is very close to get
1983 // an 8-bit displacement
1984 L.add_patch_at(code(), locator());
1985 emit_int8(0x0F);
1986 emit_int8((unsigned char)(0x80 | cc));
1987 emit_int32(0);
1988 }
1989 }
1990
1991 void Assembler::jccb(Condition cc, Label& L) {
1992 if (L.is_bound()) {
1993 const int short_size = 2;
1994 address entry = target(L);
1995 #ifdef ASSERT
1996 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1997 intptr_t delta = short_branch_delta();
1998 if (delta != 0) {
1999 dist += (dist < 0 ? (-delta) :delta);
2000 }
2001 assert(is8bit(dist), "Dispacement too large for a short jmp");
2002 #endif
2003 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2004 // 0111 tttn #8-bit disp
2005 emit_int8(0x70 | cc);
2006 emit_int8((offs - short_size) & 0xFF);
2007 } else {
2008 InstructionMark im(this);
2009 L.add_patch_at(code(), locator());
2010 emit_int8(0x70 | cc);
2011 emit_int8(0);
2012 }
2013 }
2014
2015 void Assembler::jmp(Address adr) {
2016 InstructionMark im(this);
2017 prefix(adr);
2018 emit_int8((unsigned char)0xFF);
2019 emit_operand(rsp, adr);
2020 }
2021
2022 void Assembler::jmp(Label& L, bool maybe_short) {
2023 if (L.is_bound()) {
2024 address entry = target(L);
2025 assert(entry != NULL, "jmp most probably wrong");
2026 InstructionMark im(this);
2027 const int short_size = 2;
2028 const int long_size = 5;
2029 intptr_t offs = entry - pc();
2030 if (maybe_short && is8bit(offs - short_size)) {
2031 emit_int8((unsigned char)0xEB);
2032 emit_int8((offs - short_size) & 0xFF);
2033 } else {
2034 emit_int8((unsigned char)0xE9);
2035 emit_int32(offs - long_size);
2036 }
2037 } else {
2038 // By default, forward jumps are always 32-bit displacements, since
2039 // we can't yet know where the label will be bound. If you're sure that
2040 // the forward jump will not run beyond 256 bytes, use jmpb to
2041 // force an 8-bit displacement.
2042 InstructionMark im(this);
2043 L.add_patch_at(code(), locator());
2044 emit_int8((unsigned char)0xE9);
2045 emit_int32(0);
2046 }
2047 }
2048
2049 void Assembler::jmp(Register entry) {
2050 int encode = prefix_and_encode(entry->encoding());
2051 emit_int8((unsigned char)0xFF);
2052 emit_int8((unsigned char)(0xE0 | encode));
2053 }
2054
2055 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2056 InstructionMark im(this);
2057 emit_int8((unsigned char)0xE9);
2058 assert(dest != NULL, "must have a target");
2059 intptr_t disp = dest - (pc() + sizeof(int32_t));
2060 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2061 emit_data(disp, rspec.reloc(), call32_operand);
2062 }
2063
2064 void Assembler::jmpb(Label& L) {
2065 if (L.is_bound()) {
2066 const int short_size = 2;
2067 address entry = target(L);
2068 assert(entry != NULL, "jmp most probably wrong");
2069 #ifdef ASSERT
2070 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2071 intptr_t delta = short_branch_delta();
2072 if (delta != 0) {
2073 dist += (dist < 0 ? (-delta) :delta);
2074 }
2075 assert(is8bit(dist), "Dispacement too large for a short jmp");
2076 #endif
2077 intptr_t offs = entry - pc();
2078 emit_int8((unsigned char)0xEB);
2079 emit_int8((offs - short_size) & 0xFF);
2080 } else {
2081 InstructionMark im(this);
2082 L.add_patch_at(code(), locator());
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8(0);
2085 }
2086 }
2087
2088 void Assembler::ldmxcsr( Address src) {
2089 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2090 InstructionMark im(this);
2091 prefix(src);
2092 emit_int8(0x0F);
2093 emit_int8((unsigned char)0xAE);
2094 emit_operand(as_Register(2), src);
2095 }
2096
2097 void Assembler::leal(Register dst, Address src) {
2098 InstructionMark im(this);
2099 #ifdef _LP64
2100 emit_int8(0x67); // addr32
2101 prefix(src, dst);
2102 #endif // LP64
2103 emit_int8((unsigned char)0x8D);
2104 emit_operand(dst, src);
2105 }
2106
2107 void Assembler::lfence() {
2108 emit_int8(0x0F);
2109 emit_int8((unsigned char)0xAE);
2110 emit_int8((unsigned char)0xE8);
2111 }
2112
2113 void Assembler::lock() {
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::lzcntl(Register dst, Register src) {
2118 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2119 emit_int8((unsigned char)0xF3);
2120 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2121 emit_int8(0x0F);
2122 emit_int8((unsigned char)0xBD);
2123 emit_int8((unsigned char)(0xC0 | encode));
2124 }
2125
2126 // Emit mfence instruction
2127 void Assembler::mfence() {
2128 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2129 emit_int8(0x0F);
2130 emit_int8((unsigned char)0xAE);
2131 emit_int8((unsigned char)0xF0);
2132 }
2133
2134 void Assembler::mov(Register dst, Register src) {
2135 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2136 }
2137
2138 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2140 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2141 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2142 attributes.set_rex_vex_w_reverted();
2143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2144 emit_int8(0x28);
2145 emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147
2148 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2151 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2152 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2153 emit_int8(0x28);
2154 emit_int8((unsigned char)(0xC0 | encode));
2155 }
2156
2157 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2158 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2160 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2161 emit_int8(0x16);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 void Assembler::movb(Register dst, Address src) {
2166 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2167 InstructionMark im(this);
2168 prefix(src, dst, true);
2169 emit_int8((unsigned char)0x8A);
2170 emit_operand(dst, src);
2171 }
2172
2173 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2174 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2175 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2176 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2177 attributes.set_rex_vex_w_reverted();
2178 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2179 emit_int8(0x12);
2180 emit_int8(0xC0 | encode);
2181 }
2182
2183 void Assembler::kmovbl(KRegister dst, Register src) {
2184 assert(VM_Version::supports_avx512dq(), "");
2185 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2186 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2187 emit_int8((unsigned char)0x92);
2188 emit_int8((unsigned char)(0xC0 | encode));
2189 }
2190
2191 void Assembler::kmovbl(Register dst, KRegister src) {
2192 assert(VM_Version::supports_avx512dq(), "");
2193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2194 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2195 emit_int8((unsigned char)0x93);
2196 emit_int8((unsigned char)(0xC0 | encode));
2197 }
2198
2199 void Assembler::kmovwl(KRegister dst, Register src) {
2200 assert(VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::kmovwl(Register dst, KRegister src) {
2208 assert(VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2211 emit_int8((unsigned char)0x93);
2212 emit_int8((unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::kmovwl(KRegister dst, Address src) {
2216 assert(VM_Version::supports_evex(), "");
2217 InstructionMark im(this);
2218 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2219 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2220 emit_int8((unsigned char)0x90);
2221 emit_operand((Register)dst, src);
2222 }
2223
2224 void Assembler::kmovdl(KRegister dst, Register src) {
2225 assert(VM_Version::supports_avx512bw(), "");
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x92);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::kmovdl(Register dst, KRegister src) {
2233 assert(VM_Version::supports_avx512bw(), "");
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2236 emit_int8((unsigned char)0x93);
2237 emit_int8((unsigned char)(0xC0 | encode));
2238 }
2239
2240 void Assembler::kmovql(KRegister dst, KRegister src) {
2241 assert(VM_Version::supports_avx512bw(), "");
2242 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2243 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int8((unsigned char)0x90);
2245 emit_int8((unsigned char)(0xC0 | encode));
2246 }
2247
2248 void Assembler::kmovql(KRegister dst, Address src) {
2249 assert(VM_Version::supports_avx512bw(), "");
2250 InstructionMark im(this);
2251 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2252 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2253 emit_int8((unsigned char)0x90);
2254 emit_operand((Register)dst, src);
2255 }
2256
2257 void Assembler::kmovql(Address dst, KRegister src) {
2258 assert(VM_Version::supports_avx512bw(), "");
2259 InstructionMark im(this);
2260 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2261 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2262 emit_int8((unsigned char)0x90);
2263 emit_operand((Register)src, dst);
2264 }
2265
2266 void Assembler::kmovql(KRegister dst, Register src) {
2267 assert(VM_Version::supports_avx512bw(), "");
2268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2269 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2270 emit_int8((unsigned char)0x92);
2271 emit_int8((unsigned char)(0xC0 | encode));
2272 }
2273
2274 void Assembler::kmovql(Register dst, KRegister src) {
2275 assert(VM_Version::supports_avx512bw(), "");
2276 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2277 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2278 emit_int8((unsigned char)0x93);
2279 emit_int8((unsigned char)(0xC0 | encode));
2280 }
2281
2282 void Assembler::knotwl(KRegister dst, KRegister src) {
2283 assert(VM_Version::supports_evex(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x44);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2292 assert(VM_Version::supports_avx512dq(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x98);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 // This instruction produces ZF or CF flags
2300 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2301 assert(VM_Version::supports_evex(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x98);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 void Assembler::movb(Address dst, int imm8) {
2327 InstructionMark im(this);
2328 prefix(dst);
2329 emit_int8((unsigned char)0xC6);
2330 emit_operand(rax, dst, 1);
2331 emit_int8(imm8);
2332 }
2333
2334
2335 void Assembler::movb(Address dst, Register src) {
2336 assert(src->has_byte_register(), "must have byte register");
2337 InstructionMark im(this);
2338 prefix(dst, src, true);
2339 emit_int8((unsigned char)0x88);
2340 emit_operand(src, dst);
2341 }
2342
2343 void Assembler::movdl(XMMRegister dst, Register src) {
2344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2346 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2347 emit_int8(0x6E);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 void Assembler::movdl(Register dst, XMMRegister src) {
2352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2354 // swap src/dst to get correct prefix
2355 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2356 emit_int8(0x7E);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 void Assembler::movdl(XMMRegister dst, Address src) {
2361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2362 InstructionMark im(this);
2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2364 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2365 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2366 emit_int8(0x6E);
2367 emit_operand(dst, src);
2368 }
2369
2370 void Assembler::movdl(Address dst, XMMRegister src) {
2371 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2372 InstructionMark im(this);
2373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2374 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2375 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2376 emit_int8(0x7E);
2377 emit_operand(src, dst);
2378 }
2379
2380 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2382 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2383 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2384 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2385 emit_int8(0x6F);
2386 emit_int8((unsigned char)(0xC0 | encode));
2387 }
2388
2389 void Assembler::movdqa(XMMRegister dst, Address src) {
2390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2391 InstructionMark im(this);
2392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2393 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2394 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2395 emit_int8(0x6F);
2396 emit_operand(dst, src);
2397 }
2398
2399 void Assembler::movdqu(XMMRegister dst, Address src) {
2400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2401 InstructionMark im(this);
2402 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2403 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2404 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2405 emit_int8(0x6F);
2406 emit_operand(dst, src);
2407 }
2408
2409 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2412 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2413 emit_int8(0x6F);
2414 emit_int8((unsigned char)(0xC0 | encode));
2415 }
2416
2417 void Assembler::movdqu(Address dst, XMMRegister src) {
2418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2419 InstructionMark im(this);
2420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2421 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2422 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2423 emit_int8(0x7F);
2424 emit_operand(src, dst);
2425 }
2426
2427 // Move Unaligned 256bit Vector
2428 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2429 assert(UseAVX > 0, "");
2430 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2431 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x6F);
2433 emit_int8((unsigned char)(0xC0 | encode));
2434 }
2435
2436 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2437 assert(UseAVX > 0, "");
2438 InstructionMark im(this);
2439 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2440 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2441 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2442 emit_int8(0x6F);
2443 emit_operand(dst, src);
2444 }
2445
2446 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2447 assert(UseAVX > 0, "");
2448 InstructionMark im(this);
2449 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2450 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2451 // swap src<->dst for encoding
2452 assert(src != xnoreg, "sanity");
2453 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2454 emit_int8(0x7F);
2455 emit_operand(src, dst);
2456 }
2457
2458 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2459 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2460 assert(VM_Version::supports_evex(), "");
2461 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2462 attributes.set_is_evex_instruction();
2463 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2464 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2465 emit_int8(0x6F);
2466 emit_int8((unsigned char)(0xC0 | encode));
2467 }
2468
2469 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2470 assert(VM_Version::supports_evex(), "");
2471 InstructionMark im(this);
2472 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2473 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2474 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2475 attributes.set_is_evex_instruction();
2476 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2477 emit_int8(0x6F);
2478 emit_operand(dst, src);
2479 }
2480
2481 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2482 assert(VM_Version::supports_evex(), "");
2483 assert(src != xnoreg, "sanity");
2484 InstructionMark im(this);
2485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2486 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2488 attributes.set_is_evex_instruction();
2489 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2490 emit_int8(0x7F);
2491 emit_operand(src, dst);
2492 }
2493
2494 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2495 assert(VM_Version::supports_evex(), "");
2496 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2497 attributes.set_is_evex_instruction();
2498 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2499 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2500 emit_int8(0x6F);
2501 emit_int8((unsigned char)(0xC0 | encode));
2502 }
2503
2504 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2505 assert(VM_Version::supports_evex(), "");
2506 InstructionMark im(this);
2507 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2508 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2509 attributes.set_is_evex_instruction();
2510 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2511 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2512 emit_int8(0x6F);
2513 emit_operand(dst, src);
2514 }
2515
2516 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2517 assert(VM_Version::supports_evex(), "");
2518 assert(src != xnoreg, "sanity");
2519 InstructionMark im(this);
2520 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2521 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2522 attributes.set_is_evex_instruction();
2523 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2524 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2525 emit_int8(0x7F);
2526 emit_operand(src, dst);
2527 }
2528
2529 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2530 assert(VM_Version::supports_evex(), "");
2531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2532 attributes.set_is_evex_instruction();
2533 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2534 emit_int8(0x6F);
2535 emit_int8((unsigned char)(0xC0 | encode));
2536 }
2537
2538 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2539 assert(VM_Version::supports_evex(), "");
2540 InstructionMark im(this);
2541 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2542 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2543 attributes.set_is_evex_instruction();
2544 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2545 emit_int8(0x6F);
2546 emit_operand(dst, src);
2547 }
2548
2549 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2550 assert(VM_Version::supports_evex(), "");
2551 assert(src != xnoreg, "sanity");
2552 InstructionMark im(this);
2553 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2554 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2555 attributes.set_is_evex_instruction();
2556 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2557 emit_int8(0x7F);
2558 emit_operand(src, dst);
2559 }
2560
2561 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2562 assert(VM_Version::supports_evex(), "");
2563 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2564 attributes.set_is_evex_instruction();
2565 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2566 emit_int8(0x6F);
2567 emit_int8((unsigned char)(0xC0 | encode));
2568 }
2569
2570 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2571 assert(VM_Version::supports_evex(), "");
2572 InstructionMark im(this);
2573 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2575 attributes.set_is_evex_instruction();
2576 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2577 emit_int8(0x6F);
2578 emit_operand(dst, src);
2579 }
2580
2581 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2582 assert(VM_Version::supports_evex(), "");
2583 assert(src != xnoreg, "sanity");
2584 InstructionMark im(this);
2585 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2586 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2587 attributes.set_is_evex_instruction();
2588 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2589 emit_int8(0x7F);
2590 emit_operand(src, dst);
2591 }
2592
2593 // Uses zero extension on 64bit
2594
2595 void Assembler::movl(Register dst, int32_t imm32) {
2596 int encode = prefix_and_encode(dst->encoding());
2597 emit_int8((unsigned char)(0xB8 | encode));
2598 emit_int32(imm32);
2599 }
2600
2601 void Assembler::movl(Register dst, Register src) {
2602 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2603 emit_int8((unsigned char)0x8B);
2604 emit_int8((unsigned char)(0xC0 | encode));
2605 }
2606
2607 void Assembler::movl(Register dst, Address src) {
2608 InstructionMark im(this);
2609 prefix(src, dst);
2610 emit_int8((unsigned char)0x8B);
2611 emit_operand(dst, src);
2612 }
2613
2614 void Assembler::movl(Address dst, int32_t imm32) {
2615 InstructionMark im(this);
2616 prefix(dst);
2617 emit_int8((unsigned char)0xC7);
2618 emit_operand(rax, dst, 4);
2619 emit_int32(imm32);
2620 }
2621
2622 void Assembler::movl(Address dst, Register src) {
2623 InstructionMark im(this);
2624 prefix(dst, src);
2625 emit_int8((unsigned char)0x89);
2626 emit_operand(src, dst);
2627 }
2628
2629 // New cpus require to use movsd and movss to avoid partial register stall
2630 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2631 // The selection is done in MacroAssembler::movdbl() and movflt().
2632 void Assembler::movlpd(XMMRegister dst, Address src) {
2633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2634 InstructionMark im(this);
2635 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2636 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2637 attributes.set_rex_vex_w_reverted();
2638 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x12);
2640 emit_operand(dst, src);
2641 }
2642
2643 void Assembler::movq( MMXRegister dst, Address src ) {
2644 assert( VM_Version::supports_mmx(), "" );
2645 emit_int8(0x0F);
2646 emit_int8(0x6F);
2647 emit_operand(dst, src);
2648 }
2649
2650 void Assembler::movq( Address dst, MMXRegister src ) {
2651 assert( VM_Version::supports_mmx(), "" );
2652 emit_int8(0x0F);
2653 emit_int8(0x7F);
2654 // workaround gcc (3.2.1-7a) bug
2655 // In that version of gcc with only an emit_operand(MMX, Address)
2656 // gcc will tail jump and try and reverse the parameters completely
2657 // obliterating dst in the process. By having a version available
2658 // that doesn't need to swap the args at the tail jump the bug is
2659 // avoided.
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::movq(XMMRegister dst, Address src) {
2664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2665 InstructionMark im(this);
2666 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2667 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2668 attributes.set_rex_vex_w_reverted();
2669 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2670 emit_int8(0x7E);
2671 emit_operand(dst, src);
2672 }
2673
2674 void Assembler::movq(Address dst, XMMRegister src) {
2675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2676 InstructionMark im(this);
2677 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2678 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2679 attributes.set_rex_vex_w_reverted();
2680 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2681 emit_int8((unsigned char)0xD6);
2682 emit_operand(src, dst);
2683 }
2684
2685 void Assembler::movsbl(Register dst, Address src) { // movsxb
2686 InstructionMark im(this);
2687 prefix(src, dst);
2688 emit_int8(0x0F);
2689 emit_int8((unsigned char)0xBE);
2690 emit_operand(dst, src);
2691 }
2692
2693 void Assembler::movsbl(Register dst, Register src) { // movsxb
2694 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2695 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2696 emit_int8(0x0F);
2697 emit_int8((unsigned char)0xBE);
2698 emit_int8((unsigned char)(0xC0 | encode));
2699 }
2700
2701 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2703 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2704 attributes.set_rex_vex_w_reverted();
2705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2706 emit_int8(0x10);
2707 emit_int8((unsigned char)(0xC0 | encode));
2708 }
2709
2710 void Assembler::movsd(XMMRegister dst, Address src) {
2711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2712 InstructionMark im(this);
2713 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2714 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2715 attributes.set_rex_vex_w_reverted();
2716 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2717 emit_int8(0x10);
2718 emit_operand(dst, src);
2719 }
2720
2721 void Assembler::movsd(Address dst, XMMRegister src) {
2722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2723 InstructionMark im(this);
2724 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2725 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2726 attributes.set_rex_vex_w_reverted();
2727 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2728 emit_int8(0x11);
2729 emit_operand(src, dst);
2730 }
2731
2732 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2733 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2734 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2735 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2736 emit_int8(0x10);
2737 emit_int8((unsigned char)(0xC0 | encode));
2738 }
2739
2740 void Assembler::movss(XMMRegister dst, Address src) {
2741 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2742 InstructionMark im(this);
2743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2744 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2745 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2746 emit_int8(0x10);
2747 emit_operand(dst, src);
2748 }
2749
2750 void Assembler::movss(Address dst, XMMRegister src) {
2751 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2752 InstructionMark im(this);
2753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2754 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2755 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2756 emit_int8(0x11);
2757 emit_operand(src, dst);
2758 }
2759
2760 void Assembler::movswl(Register dst, Address src) { // movsxw
2761 InstructionMark im(this);
2762 prefix(src, dst);
2763 emit_int8(0x0F);
2764 emit_int8((unsigned char)0xBF);
2765 emit_operand(dst, src);
2766 }
2767
2768 void Assembler::movswl(Register dst, Register src) { // movsxw
2769 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2770 emit_int8(0x0F);
2771 emit_int8((unsigned char)0xBF);
2772 emit_int8((unsigned char)(0xC0 | encode));
2773 }
2774
2775 void Assembler::movw(Address dst, int imm16) {
2776 InstructionMark im(this);
2777
2778 emit_int8(0x66); // switch to 16-bit mode
2779 prefix(dst);
2780 emit_int8((unsigned char)0xC7);
2781 emit_operand(rax, dst, 2);
2782 emit_int16(imm16);
2783 }
2784
2785 void Assembler::movw(Register dst, Address src) {
2786 InstructionMark im(this);
2787 emit_int8(0x66);
2788 prefix(src, dst);
2789 emit_int8((unsigned char)0x8B);
2790 emit_operand(dst, src);
2791 }
2792
2793 void Assembler::movw(Address dst, Register src) {
2794 InstructionMark im(this);
2795 emit_int8(0x66);
2796 prefix(dst, src);
2797 emit_int8((unsigned char)0x89);
2798 emit_operand(src, dst);
2799 }
2800
2801 void Assembler::movzbl(Register dst, Address src) { // movzxb
2802 InstructionMark im(this);
2803 prefix(src, dst);
2804 emit_int8(0x0F);
2805 emit_int8((unsigned char)0xB6);
2806 emit_operand(dst, src);
2807 }
2808
2809 void Assembler::movzbl(Register dst, Register src) { // movzxb
2810 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2811 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2812 emit_int8(0x0F);
2813 emit_int8((unsigned char)0xB6);
2814 emit_int8(0xC0 | encode);
2815 }
2816
2817 void Assembler::movzwl(Register dst, Address src) { // movzxw
2818 InstructionMark im(this);
2819 prefix(src, dst);
2820 emit_int8(0x0F);
2821 emit_int8((unsigned char)0xB7);
2822 emit_operand(dst, src);
2823 }
2824
2825 void Assembler::movzwl(Register dst, Register src) { // movzxw
2826 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2827 emit_int8(0x0F);
2828 emit_int8((unsigned char)0xB7);
2829 emit_int8(0xC0 | encode);
2830 }
2831
2832 void Assembler::mull(Address src) {
2833 InstructionMark im(this);
2834 prefix(src);
2835 emit_int8((unsigned char)0xF7);
2836 emit_operand(rsp, src);
2837 }
2838
2839 void Assembler::mull(Register src) {
2840 int encode = prefix_and_encode(src->encoding());
2841 emit_int8((unsigned char)0xF7);
2842 emit_int8((unsigned char)(0xE0 | encode));
2843 }
2844
2845 void Assembler::mulsd(XMMRegister dst, Address src) {
2846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2847 InstructionMark im(this);
2848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2849 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2850 attributes.set_rex_vex_w_reverted();
2851 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2852 emit_int8(0x59);
2853 emit_operand(dst, src);
2854 }
2855
2856 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2857 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2858 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2859 attributes.set_rex_vex_w_reverted();
2860 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2861 emit_int8(0x59);
2862 emit_int8((unsigned char)(0xC0 | encode));
2863 }
2864
2865 void Assembler::mulss(XMMRegister dst, Address src) {
2866 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2867 InstructionMark im(this);
2868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2869 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2870 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2871 emit_int8(0x59);
2872 emit_operand(dst, src);
2873 }
2874
2875 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2876 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2877 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2878 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2879 emit_int8(0x59);
2880 emit_int8((unsigned char)(0xC0 | encode));
2881 }
2882
2883 void Assembler::negl(Register dst) {
2884 int encode = prefix_and_encode(dst->encoding());
2885 emit_int8((unsigned char)0xF7);
2886 emit_int8((unsigned char)(0xD8 | encode));
2887 }
2888
2889 void Assembler::nop(int i) {
2890 #ifdef ASSERT
2891 assert(i > 0, " ");
2892 // The fancy nops aren't currently recognized by debuggers making it a
2893 // pain to disassemble code while debugging. If asserts are on clearly
2894 // speed is not an issue so simply use the single byte traditional nop
2895 // to do alignment.
2896
2897 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2898 return;
2899
2900 #endif // ASSERT
2901
2902 if (UseAddressNop && VM_Version::is_intel()) {
2903 //
2904 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2905 // 1: 0x90
2906 // 2: 0x66 0x90
2907 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2908 // 4: 0x0F 0x1F 0x40 0x00
2909 // 5: 0x0F 0x1F 0x44 0x00 0x00
2910 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2911 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2912 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2913 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2914 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2915 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2916
2917 // The rest coding is Intel specific - don't use consecutive address nops
2918
2919 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2920 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2921 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2922 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2923
2924 while(i >= 15) {
2925 // For Intel don't generate consecutive addess nops (mix with regular nops)
2926 i -= 15;
2927 emit_int8(0x66); // size prefix
2928 emit_int8(0x66); // size prefix
2929 emit_int8(0x66); // size prefix
2930 addr_nop_8();
2931 emit_int8(0x66); // size prefix
2932 emit_int8(0x66); // size prefix
2933 emit_int8(0x66); // size prefix
2934 emit_int8((unsigned char)0x90);
2935 // nop
2936 }
2937 switch (i) {
2938 case 14:
2939 emit_int8(0x66); // size prefix
2940 case 13:
2941 emit_int8(0x66); // size prefix
2942 case 12:
2943 addr_nop_8();
2944 emit_int8(0x66); // size prefix
2945 emit_int8(0x66); // size prefix
2946 emit_int8(0x66); // size prefix
2947 emit_int8((unsigned char)0x90);
2948 // nop
2949 break;
2950 case 11:
2951 emit_int8(0x66); // size prefix
2952 case 10:
2953 emit_int8(0x66); // size prefix
2954 case 9:
2955 emit_int8(0x66); // size prefix
2956 case 8:
2957 addr_nop_8();
2958 break;
2959 case 7:
2960 addr_nop_7();
2961 break;
2962 case 6:
2963 emit_int8(0x66); // size prefix
2964 case 5:
2965 addr_nop_5();
2966 break;
2967 case 4:
2968 addr_nop_4();
2969 break;
2970 case 3:
2971 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2972 emit_int8(0x66); // size prefix
2973 case 2:
2974 emit_int8(0x66); // size prefix
2975 case 1:
2976 emit_int8((unsigned char)0x90);
2977 // nop
2978 break;
2979 default:
2980 assert(i == 0, " ");
2981 }
2982 return;
2983 }
2984 if (UseAddressNop && VM_Version::is_amd()) {
2985 //
2986 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2987 // 1: 0x90
2988 // 2: 0x66 0x90
2989 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2990 // 4: 0x0F 0x1F 0x40 0x00
2991 // 5: 0x0F 0x1F 0x44 0x00 0x00
2992 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2993 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2994 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2995 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2996 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2997 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2998
2999 // The rest coding is AMD specific - use consecutive address nops
3000
3001 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3002 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3003 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3004 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3005 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3006 // Size prefixes (0x66) are added for larger sizes
3007
3008 while(i >= 22) {
3009 i -= 11;
3010 emit_int8(0x66); // size prefix
3011 emit_int8(0x66); // size prefix
3012 emit_int8(0x66); // size prefix
3013 addr_nop_8();
3014 }
3015 // Generate first nop for size between 21-12
3016 switch (i) {
3017 case 21:
3018 i -= 1;
3019 emit_int8(0x66); // size prefix
3020 case 20:
3021 case 19:
3022 i -= 1;
3023 emit_int8(0x66); // size prefix
3024 case 18:
3025 case 17:
3026 i -= 1;
3027 emit_int8(0x66); // size prefix
3028 case 16:
3029 case 15:
3030 i -= 8;
3031 addr_nop_8();
3032 break;
3033 case 14:
3034 case 13:
3035 i -= 7;
3036 addr_nop_7();
3037 break;
3038 case 12:
3039 i -= 6;
3040 emit_int8(0x66); // size prefix
3041 addr_nop_5();
3042 break;
3043 default:
3044 assert(i < 12, " ");
3045 }
3046
3047 // Generate second nop for size between 11-1
3048 switch (i) {
3049 case 11:
3050 emit_int8(0x66); // size prefix
3051 case 10:
3052 emit_int8(0x66); // size prefix
3053 case 9:
3054 emit_int8(0x66); // size prefix
3055 case 8:
3056 addr_nop_8();
3057 break;
3058 case 7:
3059 addr_nop_7();
3060 break;
3061 case 6:
3062 emit_int8(0x66); // size prefix
3063 case 5:
3064 addr_nop_5();
3065 break;
3066 case 4:
3067 addr_nop_4();
3068 break;
3069 case 3:
3070 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3071 emit_int8(0x66); // size prefix
3072 case 2:
3073 emit_int8(0x66); // size prefix
3074 case 1:
3075 emit_int8((unsigned char)0x90);
3076 // nop
3077 break;
3078 default:
3079 assert(i == 0, " ");
3080 }
3081 return;
3082 }
3083
3084 // Using nops with size prefixes "0x66 0x90".
3085 // From AMD Optimization Guide:
3086 // 1: 0x90
3087 // 2: 0x66 0x90
3088 // 3: 0x66 0x66 0x90
3089 // 4: 0x66 0x66 0x66 0x90
3090 // 5: 0x66 0x66 0x90 0x66 0x90
3091 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3092 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3093 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3094 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3095 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3096 //
3097 while(i > 12) {
3098 i -= 4;
3099 emit_int8(0x66); // size prefix
3100 emit_int8(0x66);
3101 emit_int8(0x66);
3102 emit_int8((unsigned char)0x90);
3103 // nop
3104 }
3105 // 1 - 12 nops
3106 if(i > 8) {
3107 if(i > 9) {
3108 i -= 1;
3109 emit_int8(0x66);
3110 }
3111 i -= 3;
3112 emit_int8(0x66);
3113 emit_int8(0x66);
3114 emit_int8((unsigned char)0x90);
3115 }
3116 // 1 - 8 nops
3117 if(i > 4) {
3118 if(i > 6) {
3119 i -= 1;
3120 emit_int8(0x66);
3121 }
3122 i -= 3;
3123 emit_int8(0x66);
3124 emit_int8(0x66);
3125 emit_int8((unsigned char)0x90);
3126 }
3127 switch (i) {
3128 case 4:
3129 emit_int8(0x66);
3130 case 3:
3131 emit_int8(0x66);
3132 case 2:
3133 emit_int8(0x66);
3134 case 1:
3135 emit_int8((unsigned char)0x90);
3136 break;
3137 default:
3138 assert(i == 0, " ");
3139 }
3140 }
3141
3142 void Assembler::notl(Register dst) {
3143 int encode = prefix_and_encode(dst->encoding());
3144 emit_int8((unsigned char)0xF7);
3145 emit_int8((unsigned char)(0xD0 | encode));
3146 }
3147
3148 void Assembler::orl(Address dst, int32_t imm32) {
3149 InstructionMark im(this);
3150 prefix(dst);
3151 emit_arith_operand(0x81, rcx, dst, imm32);
3152 }
3153
3154 void Assembler::orl(Register dst, int32_t imm32) {
3155 prefix(dst);
3156 emit_arith(0x81, 0xC8, dst, imm32);
3157 }
3158
3159 void Assembler::orl(Register dst, Address src) {
3160 InstructionMark im(this);
3161 prefix(src, dst);
3162 emit_int8(0x0B);
3163 emit_operand(dst, src);
3164 }
3165
3166 void Assembler::orl(Register dst, Register src) {
3167 (void) prefix_and_encode(dst->encoding(), src->encoding());
3168 emit_arith(0x0B, 0xC0, dst, src);
3169 }
3170
3171 void Assembler::orl(Address dst, Register src) {
3172 InstructionMark im(this);
3173 prefix(dst, src);
3174 emit_int8(0x09);
3175 emit_operand(src, dst);
3176 }
3177
3178 void Assembler::packuswb(XMMRegister dst, Address src) {
3179 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3180 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3181 InstructionMark im(this);
3182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3183 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3184 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3185 emit_int8(0x67);
3186 emit_operand(dst, src);
3187 }
3188
3189 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3192 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3193 emit_int8(0x67);
3194 emit_int8((unsigned char)(0xC0 | encode));
3195 }
3196
3197 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3198 assert(UseAVX > 0, "some form of AVX must be enabled");
3199 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3200 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3201 emit_int8(0x67);
3202 emit_int8((unsigned char)(0xC0 | encode));
3203 }
3204
3205 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3206 assert(VM_Version::supports_avx2(), "");
3207 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3208 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3209 emit_int8(0x00);
3210 emit_int8(0xC0 | encode);
3211 emit_int8(imm8);
3212 }
3213
3214 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3215 assert(VM_Version::supports_avx2(), "");
3216 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3217 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3218 emit_int8(0x46);
3219 emit_int8(0xC0 | encode);
3220 emit_int8(imm8);
3221 }
3222
3223
3224 void Assembler::pause() {
3225 emit_int8((unsigned char)0xF3);
3226 emit_int8((unsigned char)0x90);
3227 }
3228
3229 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3230 assert(VM_Version::supports_sse4_2(), "");
3231 InstructionMark im(this);
3232 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3233 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3234 emit_int8(0x61);
3235 emit_operand(dst, src);
3236 emit_int8(imm8);
3237 }
3238
3239 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3240 assert(VM_Version::supports_sse4_2(), "");
3241 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3242 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3243 emit_int8(0x61);
3244 emit_int8((unsigned char)(0xC0 | encode));
3245 emit_int8(imm8);
3246 }
3247
3248 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3249 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3250 assert(VM_Version::supports_sse2(), "");
3251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3253 emit_int8(0x74);
3254 emit_int8((unsigned char)(0xC0 | encode));
3255 }
3256
3257 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3258 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3259 assert(VM_Version::supports_avx(), "");
3260 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3261 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3262 emit_int8(0x74);
3263 emit_int8((unsigned char)(0xC0 | encode));
3264 }
3265
3266 // In this context, kdst is written the mask used to process the equal components
3267 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3268 assert(VM_Version::supports_avx512bw(), "");
3269 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3270 attributes.set_is_evex_instruction();
3271 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3272 emit_int8(0x74);
3273 emit_int8((unsigned char)(0xC0 | encode));
3274 }
3275
3276 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3277 assert(VM_Version::supports_avx512bw(), "");
3278 InstructionMark im(this);
3279 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3280 attributes.set_is_evex_instruction();
3281 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3282 int dst_enc = kdst->encoding();
3283 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3284 emit_int8(0x74);
3285 emit_operand(as_Register(dst_enc), src);
3286 }
3287
3288 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3289 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3290 assert(VM_Version::supports_sse2(), "");
3291 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3292 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3293 emit_int8(0x75);
3294 emit_int8((unsigned char)(0xC0 | encode));
3295 }
3296
3297 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3298 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3299 assert(VM_Version::supports_avx(), "");
3300 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3301 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3302 emit_int8(0x75);
3303 emit_int8((unsigned char)(0xC0 | encode));
3304 }
3305
3306 // In this context, kdst is written the mask used to process the equal components
3307 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3308 assert(VM_Version::supports_avx512bw(), "");
3309 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3310 attributes.set_is_evex_instruction();
3311 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3312 emit_int8(0x75);
3313 emit_int8((unsigned char)(0xC0 | encode));
3314 }
3315
3316 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3317 assert(VM_Version::supports_avx512bw(), "");
3318 InstructionMark im(this);
3319 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3320 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3321 attributes.set_is_evex_instruction();
3322 int dst_enc = kdst->encoding();
3323 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3324 emit_int8(0x75);
3325 emit_operand(as_Register(dst_enc), src);
3326 }
3327
3328 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3329 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3330 assert(VM_Version::supports_sse2(), "");
3331 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3332 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3333 emit_int8(0x76);
3334 emit_int8((unsigned char)(0xC0 | encode));
3335 }
3336
3337 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3338 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3339 assert(VM_Version::supports_avx(), "");
3340 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3341 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3342 emit_int8(0x76);
3343 emit_int8((unsigned char)(0xC0 | encode));
3344 }
3345
3346 // In this context, kdst is written the mask used to process the equal components
3347 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3348 assert(VM_Version::supports_evex(), "");
3349 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3350 attributes.set_is_evex_instruction();
3351 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3352 emit_int8(0x76);
3353 emit_int8((unsigned char)(0xC0 | encode));
3354 }
3355
3356 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3357 assert(VM_Version::supports_evex(), "");
3358 InstructionMark im(this);
3359 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3360 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3361 attributes.set_is_evex_instruction();
3362 int dst_enc = kdst->encoding();
3363 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3364 emit_int8(0x76);
3365 emit_operand(as_Register(dst_enc), src);
3366 }
3367
3368 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3369 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3370 assert(VM_Version::supports_sse4_1(), "");
3371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3372 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3373 emit_int8(0x29);
3374 emit_int8((unsigned char)(0xC0 | encode));
3375 }
3376
3377 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3378 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3379 assert(VM_Version::supports_avx(), "");
3380 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3381 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3382 emit_int8(0x29);
3383 emit_int8((unsigned char)(0xC0 | encode));
3384 }
3385
3386 // In this context, kdst is written the mask used to process the equal components
3387 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3388 assert(VM_Version::supports_evex(), "");
3389 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3390 attributes.set_is_evex_instruction();
3391 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3392 emit_int8(0x29);
3393 emit_int8((unsigned char)(0xC0 | encode));
3394 }
3395
3396 // In this context, kdst is written the mask used to process the equal components
3397 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3398 assert(VM_Version::supports_evex(), "");
3399 InstructionMark im(this);
3400 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3401 attributes.set_is_evex_instruction();
3402 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3403 int dst_enc = kdst->encoding();
3404 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3405 emit_int8(0x29);
3406 emit_operand(as_Register(dst_enc), src);
3407 }
3408
3409 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3410 assert(VM_Version::supports_sse2(), "");
3411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3412 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3413 emit_int8((unsigned char)0xD7);
3414 emit_int8((unsigned char)(0xC0 | encode));
3415 }
3416
3417 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3418 assert(VM_Version::supports_avx2(), "");
3419 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3420 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3421 emit_int8((unsigned char)0xD7);
3422 emit_int8((unsigned char)(0xC0 | encode));
3423 }
3424
3425 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3426 assert(VM_Version::supports_sse4_1(), "");
3427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3428 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3429 emit_int8(0x16);
3430 emit_int8((unsigned char)(0xC0 | encode));
3431 emit_int8(imm8);
3432 }
3433
3434 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3435 assert(VM_Version::supports_sse4_1(), "");
3436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3437 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3438 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3439 emit_int8(0x16);
3440 emit_operand(src, dst);
3441 emit_int8(imm8);
3442 }
3443
3444 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3445 assert(VM_Version::supports_sse4_1(), "");
3446 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3447 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3448 emit_int8(0x16);
3449 emit_int8((unsigned char)(0xC0 | encode));
3450 emit_int8(imm8);
3451 }
3452
3453 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3454 assert(VM_Version::supports_sse4_1(), "");
3455 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3456 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3457 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3458 emit_int8(0x16);
3459 emit_operand(src, dst);
3460 emit_int8(imm8);
3461 }
3462
3463 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3464 assert(VM_Version::supports_sse2(), "");
3465 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3466 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3467 emit_int8((unsigned char)0xC5);
3468 emit_int8((unsigned char)(0xC0 | encode));
3469 emit_int8(imm8);
3470 }
3471
3472 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3473 assert(VM_Version::supports_sse4_1(), "");
3474 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3475 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3476 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3477 emit_int8((unsigned char)0x15);
3478 emit_operand(src, dst);
3479 emit_int8(imm8);
3480 }
3481
3482 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3483 assert(VM_Version::supports_sse4_1(), "");
3484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3485 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3486 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3487 emit_int8(0x14);
3488 emit_operand(src, dst);
3489 emit_int8(imm8);
3490 }
3491
3492 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3493 assert(VM_Version::supports_sse4_1(), "");
3494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3495 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3496 emit_int8(0x22);
3497 emit_int8((unsigned char)(0xC0 | encode));
3498 emit_int8(imm8);
3499 }
3500
3501 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3502 assert(VM_Version::supports_sse4_1(), "");
3503 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3504 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3505 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3506 emit_int8(0x22);
3507 emit_operand(dst,src);
3508 emit_int8(imm8);
3509 }
3510
3511 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3512 assert(VM_Version::supports_sse4_1(), "");
3513 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3514 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3515 emit_int8(0x22);
3516 emit_int8((unsigned char)(0xC0 | encode));
3517 emit_int8(imm8);
3518 }
3519
3520 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3521 assert(VM_Version::supports_sse4_1(), "");
3522 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3523 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3524 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3525 emit_int8(0x22);
3526 emit_operand(dst, src);
3527 emit_int8(imm8);
3528 }
3529
3530 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3531 assert(VM_Version::supports_sse2(), "");
3532 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3533 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3534 emit_int8((unsigned char)0xC4);
3535 emit_int8((unsigned char)(0xC0 | encode));
3536 emit_int8(imm8);
3537 }
3538
3539 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3540 assert(VM_Version::supports_sse2(), "");
3541 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3542 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3543 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3544 emit_int8((unsigned char)0xC4);
3545 emit_operand(dst, src);
3546 emit_int8(imm8);
3547 }
3548
3549 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3550 assert(VM_Version::supports_sse4_1(), "");
3551 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3552 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3553 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3554 emit_int8(0x20);
3555 emit_operand(dst, src);
3556 emit_int8(imm8);
3557 }
3558
3559 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3560 assert(VM_Version::supports_sse4_1(), "");
3561 InstructionMark im(this);
3562 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3563 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3564 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3565 emit_int8(0x30);
3566 emit_operand(dst, src);
3567 }
3568
3569 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3570 assert(VM_Version::supports_sse4_1(), "");
3571 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3572 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3573 emit_int8(0x30);
3574 emit_int8((unsigned char)(0xC0 | encode));
3575 }
3576
3577 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3578 assert(VM_Version::supports_avx(), "");
3579 InstructionMark im(this);
3580 assert(dst != xnoreg, "sanity");
3581 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3582 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3583 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3584 emit_int8(0x30);
3585 emit_operand(dst, src);
3586 }
3587
3588 // generic
3589 void Assembler::pop(Register dst) {
3590 int encode = prefix_and_encode(dst->encoding());
3591 emit_int8(0x58 | encode);
3592 }
3593
3594 void Assembler::popcntl(Register dst, Address src) {
3595 assert(VM_Version::supports_popcnt(), "must support");
3596 InstructionMark im(this);
3597 emit_int8((unsigned char)0xF3);
3598 prefix(src, dst);
3599 emit_int8(0x0F);
3600 emit_int8((unsigned char)0xB8);
3601 emit_operand(dst, src);
3602 }
3603
3604 void Assembler::popcntl(Register dst, Register src) {
3605 assert(VM_Version::supports_popcnt(), "must support");
3606 emit_int8((unsigned char)0xF3);
3607 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3608 emit_int8(0x0F);
3609 emit_int8((unsigned char)0xB8);
3610 emit_int8((unsigned char)(0xC0 | encode));
3611 }
3612
3613 void Assembler::popf() {
3614 emit_int8((unsigned char)0x9D);
3615 }
3616
3617 #ifndef _LP64 // no 32bit push/pop on amd64
3618 void Assembler::popl(Address dst) {
3619 // NOTE: this will adjust stack by 8byte on 64bits
3620 InstructionMark im(this);
3621 prefix(dst);
3622 emit_int8((unsigned char)0x8F);
3623 emit_operand(rax, dst);
3624 }
3625 #endif
3626
3627 void Assembler::prefetch_prefix(Address src) {
3628 prefix(src);
3629 emit_int8(0x0F);
3630 }
3631
3632 void Assembler::prefetchnta(Address src) {
3633 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3634 InstructionMark im(this);
3635 prefetch_prefix(src);
3636 emit_int8(0x18);
3637 emit_operand(rax, src); // 0, src
3638 }
3639
3640 void Assembler::prefetchr(Address src) {
3641 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3642 InstructionMark im(this);
3643 prefetch_prefix(src);
3644 emit_int8(0x0D);
3645 emit_operand(rax, src); // 0, src
3646 }
3647
3648 void Assembler::prefetcht0(Address src) {
3649 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3650 InstructionMark im(this);
3651 prefetch_prefix(src);
3652 emit_int8(0x18);
3653 emit_operand(rcx, src); // 1, src
3654 }
3655
3656 void Assembler::prefetcht1(Address src) {
3657 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3658 InstructionMark im(this);
3659 prefetch_prefix(src);
3660 emit_int8(0x18);
3661 emit_operand(rdx, src); // 2, src
3662 }
3663
3664 void Assembler::prefetcht2(Address src) {
3665 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3666 InstructionMark im(this);
3667 prefetch_prefix(src);
3668 emit_int8(0x18);
3669 emit_operand(rbx, src); // 3, src
3670 }
3671
3672 void Assembler::prefetchw(Address src) {
3673 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3674 InstructionMark im(this);
3675 prefetch_prefix(src);
3676 emit_int8(0x0D);
3677 emit_operand(rcx, src); // 1, src
3678 }
3679
3680 void Assembler::prefix(Prefix p) {
3681 emit_int8(p);
3682 }
3683
3684 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3685 assert(VM_Version::supports_ssse3(), "");
3686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3687 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3688 emit_int8(0x00);
3689 emit_int8((unsigned char)(0xC0 | encode));
3690 }
3691
3692 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3693 assert(VM_Version::supports_ssse3(), "");
3694 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3695 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3696 emit_int8(0x00);
3697 emit_int8((unsigned char)(0xC0 | encode));
3698 }
3699
3700 void Assembler::pshufb(XMMRegister dst, Address src) {
3701 assert(VM_Version::supports_ssse3(), "");
3702 InstructionMark im(this);
3703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3704 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3705 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3706 emit_int8(0x00);
3707 emit_operand(dst, src);
3708 }
3709
3710 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3711 assert(isByte(mode), "invalid value");
3712 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3713 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3714 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3715 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3716 emit_int8(0x70);
3717 emit_int8((unsigned char)(0xC0 | encode));
3718 emit_int8(mode & 0xFF);
3719 }
3720
3721 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
3722 assert(isByte(mode), "invalid value");
3723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3724 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3725 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3726 emit_int8(0x70);
3727 emit_int8((unsigned char)(0xC0 | encode));
3728 emit_int8(mode & 0xFF);
3729 }
3730
3731 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3732 assert(isByte(mode), "invalid value");
3733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3734 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3735 InstructionMark im(this);
3736 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3737 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3738 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3739 emit_int8(0x70);
3740 emit_operand(dst, src);
3741 emit_int8(mode & 0xFF);
3742 }
3743
3744 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3745 assert(isByte(mode), "invalid value");
3746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3748 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3749 emit_int8(0x70);
3750 emit_int8((unsigned char)(0xC0 | encode));
3751 emit_int8(mode & 0xFF);
3752 }
3753
3754 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3755 assert(isByte(mode), "invalid value");
3756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3757 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3758 InstructionMark im(this);
3759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3760 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3761 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3762 emit_int8(0x70);
3763 emit_operand(dst, src);
3764 emit_int8(mode & 0xFF);
3765 }
3766
3767 void Assembler::psrldq(XMMRegister dst, int shift) {
3768 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3769 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3770 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3771 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3772 emit_int8(0x73);
3773 emit_int8((unsigned char)(0xC0 | encode));
3774 emit_int8(shift);
3775 }
3776
3777 void Assembler::pslldq(XMMRegister dst, int shift) {
3778 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3781 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3782 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3783 emit_int8(0x73);
3784 emit_int8((unsigned char)(0xC0 | encode));
3785 emit_int8(shift);
3786 }
3787
3788 void Assembler::ptest(XMMRegister dst, Address src) {
3789 assert(VM_Version::supports_sse4_1(), "");
3790 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3791 InstructionMark im(this);
3792 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3793 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3794 emit_int8(0x17);
3795 emit_operand(dst, src);
3796 }
3797
3798 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3799 assert(VM_Version::supports_sse4_1(), "");
3800 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3801 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3802 emit_int8(0x17);
3803 emit_int8((unsigned char)(0xC0 | encode));
3804 }
3805
3806 void Assembler::vptest(XMMRegister dst, Address src) {
3807 assert(VM_Version::supports_avx(), "");
3808 InstructionMark im(this);
3809 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3810 assert(dst != xnoreg, "sanity");
3811 // swap src<->dst for encoding
3812 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3813 emit_int8(0x17);
3814 emit_operand(dst, src);
3815 }
3816
3817 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3818 assert(VM_Version::supports_avx(), "");
3819 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3820 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3821 emit_int8(0x17);
3822 emit_int8((unsigned char)(0xC0 | encode));
3823 }
3824
3825 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3826 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3827 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3828 InstructionMark im(this);
3829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3830 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3831 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3832 emit_int8(0x60);
3833 emit_operand(dst, src);
3834 }
3835
3836 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3839 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3840 emit_int8(0x60);
3841 emit_int8((unsigned char)(0xC0 | encode));
3842 }
3843
3844 void Assembler::punpckldq(XMMRegister dst, Address src) {
3845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3846 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3847 InstructionMark im(this);
3848 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3849 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3850 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3851 emit_int8(0x62);
3852 emit_operand(dst, src);
3853 }
3854
3855 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3856 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3858 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3859 emit_int8(0x62);
3860 emit_int8((unsigned char)(0xC0 | encode));
3861 }
3862
3863 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3864 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3865 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3866 attributes.set_rex_vex_w_reverted();
3867 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3868 emit_int8(0x6C);
3869 emit_int8((unsigned char)(0xC0 | encode));
3870 }
3871
3872 void Assembler::push(int32_t imm32) {
3873 // in 64bits we push 64bits onto the stack but only
3874 // take a 32bit immediate
3875 emit_int8(0x68);
3876 emit_int32(imm32);
3877 }
3878
3879 void Assembler::push(Register src) {
3880 int encode = prefix_and_encode(src->encoding());
3881
3882 emit_int8(0x50 | encode);
3883 }
3884
3885 void Assembler::pushf() {
3886 emit_int8((unsigned char)0x9C);
3887 }
3888
3889 #ifndef _LP64 // no 32bit push/pop on amd64
3890 void Assembler::pushl(Address src) {
3891 // Note this will push 64bit on 64bit
3892 InstructionMark im(this);
3893 prefix(src);
3894 emit_int8((unsigned char)0xFF);
3895 emit_operand(rsi, src);
3896 }
3897 #endif
3898
3899 void Assembler::rcll(Register dst, int imm8) {
3900 assert(isShiftCount(imm8), "illegal shift count");
3901 int encode = prefix_and_encode(dst->encoding());
3902 if (imm8 == 1) {
3903 emit_int8((unsigned char)0xD1);
3904 emit_int8((unsigned char)(0xD0 | encode));
3905 } else {
3906 emit_int8((unsigned char)0xC1);
3907 emit_int8((unsigned char)0xD0 | encode);
3908 emit_int8(imm8);
3909 }
3910 }
3911
3912 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3913 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3915 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3916 emit_int8(0x53);
3917 emit_int8((unsigned char)(0xC0 | encode));
3918 }
3919
3920 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3923 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3924 emit_int8(0x53);
3925 emit_int8((unsigned char)(0xC0 | encode));
3926 }
3927
3928 void Assembler::rdtsc() {
3929 emit_int8((unsigned char)0x0F);
3930 emit_int8((unsigned char)0x31);
3931 }
3932
3933 // copies data from [esi] to [edi] using rcx pointer sized words
3934 // generic
3935 void Assembler::rep_mov() {
3936 emit_int8((unsigned char)0xF3);
3937 // MOVSQ
3938 LP64_ONLY(prefix(REX_W));
3939 emit_int8((unsigned char)0xA5);
3940 }
3941
3942 // sets rcx bytes with rax, value at [edi]
3943 void Assembler::rep_stosb() {
3944 emit_int8((unsigned char)0xF3); // REP
3945 LP64_ONLY(prefix(REX_W));
3946 emit_int8((unsigned char)0xAA); // STOSB
3947 }
3948
3949 // sets rcx pointer sized words with rax, value at [edi]
3950 // generic
3951 void Assembler::rep_stos() {
3952 emit_int8((unsigned char)0xF3); // REP
3953 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3954 emit_int8((unsigned char)0xAB);
3955 }
3956
3957 // scans rcx pointer sized words at [edi] for occurance of rax,
3958 // generic
3959 void Assembler::repne_scan() { // repne_scan
3960 emit_int8((unsigned char)0xF2);
3961 // SCASQ
3962 LP64_ONLY(prefix(REX_W));
3963 emit_int8((unsigned char)0xAF);
3964 }
3965
3966 #ifdef _LP64
3967 // scans rcx 4 byte words at [edi] for occurance of rax,
3968 // generic
3969 void Assembler::repne_scanl() { // repne_scan
3970 emit_int8((unsigned char)0xF2);
3971 // SCASL
3972 emit_int8((unsigned char)0xAF);
3973 }
3974 #endif
3975
3976 void Assembler::ret(int imm16) {
3977 if (imm16 == 0) {
3978 emit_int8((unsigned char)0xC3);
3979 } else {
3980 emit_int8((unsigned char)0xC2);
3981 emit_int16(imm16);
3982 }
3983 }
3984
3985 void Assembler::sahf() {
3986 #ifdef _LP64
3987 // Not supported in 64bit mode
3988 ShouldNotReachHere();
3989 #endif
3990 emit_int8((unsigned char)0x9E);
3991 }
3992
3993 void Assembler::sarl(Register dst, int imm8) {
3994 int encode = prefix_and_encode(dst->encoding());
3995 assert(isShiftCount(imm8), "illegal shift count");
3996 if (imm8 == 1) {
3997 emit_int8((unsigned char)0xD1);
3998 emit_int8((unsigned char)(0xF8 | encode));
3999 } else {
4000 emit_int8((unsigned char)0xC1);
4001 emit_int8((unsigned char)(0xF8 | encode));
4002 emit_int8(imm8);
4003 }
4004 }
4005
4006 void Assembler::sarl(Register dst) {
4007 int encode = prefix_and_encode(dst->encoding());
4008 emit_int8((unsigned char)0xD3);
4009 emit_int8((unsigned char)(0xF8 | encode));
4010 }
4011
4012 void Assembler::sbbl(Address dst, int32_t imm32) {
4013 InstructionMark im(this);
4014 prefix(dst);
4015 emit_arith_operand(0x81, rbx, dst, imm32);
4016 }
4017
4018 void Assembler::sbbl(Register dst, int32_t imm32) {
4019 prefix(dst);
4020 emit_arith(0x81, 0xD8, dst, imm32);
4021 }
4022
4023
4024 void Assembler::sbbl(Register dst, Address src) {
4025 InstructionMark im(this);
4026 prefix(src, dst);
4027 emit_int8(0x1B);
4028 emit_operand(dst, src);
4029 }
4030
4031 void Assembler::sbbl(Register dst, Register src) {
4032 (void) prefix_and_encode(dst->encoding(), src->encoding());
4033 emit_arith(0x1B, 0xC0, dst, src);
4034 }
4035
4036 void Assembler::setb(Condition cc, Register dst) {
4037 assert(0 <= cc && cc < 16, "illegal cc");
4038 int encode = prefix_and_encode(dst->encoding(), true);
4039 emit_int8(0x0F);
4040 emit_int8((unsigned char)0x90 | cc);
4041 emit_int8((unsigned char)(0xC0 | encode));
4042 }
4043
4044 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4045 assert(VM_Version::supports_ssse3(), "");
4046 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4047 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4048 emit_int8((unsigned char)0x0F);
4049 emit_int8((unsigned char)(0xC0 | encode));
4050 emit_int8(imm8);
4051 }
4052
4053 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4054 assert(VM_Version::supports_ssse3(), "");
4055 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4056 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4057 emit_int8((unsigned char)0x0F);
4058 emit_int8((unsigned char)(0xC0 | encode));
4059 emit_int8(imm8);
4060 }
4061
4062 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4063 assert(VM_Version::supports_sse4_1(), "");
4064 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4066 emit_int8((unsigned char)0x0E);
4067 emit_int8((unsigned char)(0xC0 | encode));
4068 emit_int8(imm8);
4069 }
4070
4071 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4072 assert(VM_Version::supports_sha(), "");
4073 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4074 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4075 emit_int8((unsigned char)0xCC);
4076 emit_int8((unsigned char)(0xC0 | encode));
4077 emit_int8((unsigned char)imm8);
4078 }
4079
4080 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4081 assert(VM_Version::supports_sha(), "");
4082 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4083 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4084 emit_int8((unsigned char)0xC8);
4085 emit_int8((unsigned char)(0xC0 | encode));
4086 }
4087
4088 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4089 assert(VM_Version::supports_sha(), "");
4090 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4091 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4092 emit_int8((unsigned char)0xC9);
4093 emit_int8((unsigned char)(0xC0 | encode));
4094 }
4095
4096 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4097 assert(VM_Version::supports_sha(), "");
4098 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4099 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4100 emit_int8((unsigned char)0xCA);
4101 emit_int8((unsigned char)(0xC0 | encode));
4102 }
4103
4104 // xmm0 is implicit additional source to this instruction.
4105 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4106 assert(VM_Version::supports_sha(), "");
4107 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4108 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4109 emit_int8((unsigned char)0xCB);
4110 emit_int8((unsigned char)(0xC0 | encode));
4111 }
4112
4113 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4114 assert(VM_Version::supports_sha(), "");
4115 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4117 emit_int8((unsigned char)0xCC);
4118 emit_int8((unsigned char)(0xC0 | encode));
4119 }
4120
4121 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4122 assert(VM_Version::supports_sha(), "");
4123 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4124 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4125 emit_int8((unsigned char)0xCD);
4126 emit_int8((unsigned char)(0xC0 | encode));
4127 }
4128
4129
4130 void Assembler::shll(Register dst, int imm8) {
4131 assert(isShiftCount(imm8), "illegal shift count");
4132 int encode = prefix_and_encode(dst->encoding());
4133 if (imm8 == 1 ) {
4134 emit_int8((unsigned char)0xD1);
4135 emit_int8((unsigned char)(0xE0 | encode));
4136 } else {
4137 emit_int8((unsigned char)0xC1);
4138 emit_int8((unsigned char)(0xE0 | encode));
4139 emit_int8(imm8);
4140 }
4141 }
4142
4143 void Assembler::shll(Register dst) {
4144 int encode = prefix_and_encode(dst->encoding());
4145 emit_int8((unsigned char)0xD3);
4146 emit_int8((unsigned char)(0xE0 | encode));
4147 }
4148
4149 void Assembler::shrl(Register dst, int imm8) {
4150 assert(isShiftCount(imm8), "illegal shift count");
4151 int encode = prefix_and_encode(dst->encoding());
4152 emit_int8((unsigned char)0xC1);
4153 emit_int8((unsigned char)(0xE8 | encode));
4154 emit_int8(imm8);
4155 }
4156
4157 void Assembler::shrl(Register dst) {
4158 int encode = prefix_and_encode(dst->encoding());
4159 emit_int8((unsigned char)0xD3);
4160 emit_int8((unsigned char)(0xE8 | encode));
4161 }
4162
4163 // copies a single word from [esi] to [edi]
4164 void Assembler::smovl() {
4165 emit_int8((unsigned char)0xA5);
4166 }
4167
4168 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4170 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4171 attributes.set_rex_vex_w_reverted();
4172 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4173 emit_int8(0x51);
4174 emit_int8((unsigned char)(0xC0 | encode));
4175 }
4176
4177 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4179 InstructionMark im(this);
4180 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4181 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4182 attributes.set_rex_vex_w_reverted();
4183 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4184 emit_int8(0x51);
4185 emit_operand(dst, src);
4186 }
4187
4188 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4189 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4190 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4191 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4192 emit_int8(0x51);
4193 emit_int8((unsigned char)(0xC0 | encode));
4194 }
4195
4196 void Assembler::std() {
4197 emit_int8((unsigned char)0xFD);
4198 }
4199
4200 void Assembler::sqrtss(XMMRegister dst, Address src) {
4201 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4202 InstructionMark im(this);
4203 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4204 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4205 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4206 emit_int8(0x51);
4207 emit_operand(dst, src);
4208 }
4209
4210 void Assembler::stmxcsr( Address dst) {
4211 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4212 InstructionMark im(this);
4213 prefix(dst);
4214 emit_int8(0x0F);
4215 emit_int8((unsigned char)0xAE);
4216 emit_operand(as_Register(3), dst);
4217 }
4218
4219 void Assembler::subl(Address dst, int32_t imm32) {
4220 InstructionMark im(this);
4221 prefix(dst);
4222 emit_arith_operand(0x81, rbp, dst, imm32);
4223 }
4224
4225 void Assembler::subl(Address dst, Register src) {
4226 InstructionMark im(this);
4227 prefix(dst, src);
4228 emit_int8(0x29);
4229 emit_operand(src, dst);
4230 }
4231
4232 void Assembler::subl(Register dst, int32_t imm32) {
4233 prefix(dst);
4234 emit_arith(0x81, 0xE8, dst, imm32);
4235 }
4236
4237 // Force generation of a 4 byte immediate value even if it fits into 8bit
4238 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4239 prefix(dst);
4240 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4241 }
4242
4243 void Assembler::subl(Register dst, Address src) {
4244 InstructionMark im(this);
4245 prefix(src, dst);
4246 emit_int8(0x2B);
4247 emit_operand(dst, src);
4248 }
4249
4250 void Assembler::subl(Register dst, Register src) {
4251 (void) prefix_and_encode(dst->encoding(), src->encoding());
4252 emit_arith(0x2B, 0xC0, dst, src);
4253 }
4254
4255 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4257 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4258 attributes.set_rex_vex_w_reverted();
4259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4260 emit_int8(0x5C);
4261 emit_int8((unsigned char)(0xC0 | encode));
4262 }
4263
4264 void Assembler::subsd(XMMRegister dst, Address src) {
4265 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4266 InstructionMark im(this);
4267 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4268 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4269 attributes.set_rex_vex_w_reverted();
4270 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4271 emit_int8(0x5C);
4272 emit_operand(dst, src);
4273 }
4274
4275 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4276 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4279 emit_int8(0x5C);
4280 emit_int8((unsigned char)(0xC0 | encode));
4281 }
4282
4283 void Assembler::subss(XMMRegister dst, Address src) {
4284 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4285 InstructionMark im(this);
4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4288 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4289 emit_int8(0x5C);
4290 emit_operand(dst, src);
4291 }
4292
4293 void Assembler::testb(Register dst, int imm8) {
4294 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4295 (void) prefix_and_encode(dst->encoding(), true);
4296 emit_arith_b(0xF6, 0xC0, dst, imm8);
4297 }
4298
4299 void Assembler::testb(Address dst, int imm8) {
4300 InstructionMark im(this);
4301 prefix(dst);
4302 emit_int8((unsigned char)0xF6);
4303 emit_operand(rax, dst, 1);
4304 emit_int8(imm8);
4305 }
4306
4307 void Assembler::testl(Register dst, int32_t imm32) {
4308 // not using emit_arith because test
4309 // doesn't support sign-extension of
4310 // 8bit operands
4311 int encode = dst->encoding();
4312 if (encode == 0) {
4313 emit_int8((unsigned char)0xA9);
4314 } else {
4315 encode = prefix_and_encode(encode);
4316 emit_int8((unsigned char)0xF7);
4317 emit_int8((unsigned char)(0xC0 | encode));
4318 }
4319 emit_int32(imm32);
4320 }
4321
4322 void Assembler::testl(Register dst, Register src) {
4323 (void) prefix_and_encode(dst->encoding(), src->encoding());
4324 emit_arith(0x85, 0xC0, dst, src);
4325 }
4326
4327 void Assembler::testl(Register dst, Address src) {
4328 InstructionMark im(this);
4329 prefix(src, dst);
4330 emit_int8((unsigned char)0x85);
4331 emit_operand(dst, src);
4332 }
4333
4334 void Assembler::tzcntl(Register dst, Register src) {
4335 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4336 emit_int8((unsigned char)0xF3);
4337 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4338 emit_int8(0x0F);
4339 emit_int8((unsigned char)0xBC);
4340 emit_int8((unsigned char)0xC0 | encode);
4341 }
4342
4343 void Assembler::tzcntq(Register dst, Register src) {
4344 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4345 emit_int8((unsigned char)0xF3);
4346 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4347 emit_int8(0x0F);
4348 emit_int8((unsigned char)0xBC);
4349 emit_int8((unsigned char)(0xC0 | encode));
4350 }
4351
4352 void Assembler::ucomisd(XMMRegister dst, Address src) {
4353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4354 InstructionMark im(this);
4355 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4356 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4357 attributes.set_rex_vex_w_reverted();
4358 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4359 emit_int8(0x2E);
4360 emit_operand(dst, src);
4361 }
4362
4363 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4365 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4366 attributes.set_rex_vex_w_reverted();
4367 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4368 emit_int8(0x2E);
4369 emit_int8((unsigned char)(0xC0 | encode));
4370 }
4371
4372 void Assembler::ucomiss(XMMRegister dst, Address src) {
4373 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4374 InstructionMark im(this);
4375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4376 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4377 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4378 emit_int8(0x2E);
4379 emit_operand(dst, src);
4380 }
4381
4382 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4383 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4385 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4386 emit_int8(0x2E);
4387 emit_int8((unsigned char)(0xC0 | encode));
4388 }
4389
4390 void Assembler::xabort(int8_t imm8) {
4391 emit_int8((unsigned char)0xC6);
4392 emit_int8((unsigned char)0xF8);
4393 emit_int8((unsigned char)(imm8 & 0xFF));
4394 }
4395
4396 void Assembler::xaddl(Address dst, Register src) {
4397 InstructionMark im(this);
4398 prefix(dst, src);
4399 emit_int8(0x0F);
4400 emit_int8((unsigned char)0xC1);
4401 emit_operand(src, dst);
4402 }
4403
4404 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4405 InstructionMark im(this);
4406 relocate(rtype);
4407 if (abort.is_bound()) {
4408 address entry = target(abort);
4409 assert(entry != NULL, "abort entry NULL");
4410 intptr_t offset = entry - pc();
4411 emit_int8((unsigned char)0xC7);
4412 emit_int8((unsigned char)0xF8);
4413 emit_int32(offset - 6); // 2 opcode + 4 address
4414 } else {
4415 abort.add_patch_at(code(), locator());
4416 emit_int8((unsigned char)0xC7);
4417 emit_int8((unsigned char)0xF8);
4418 emit_int32(0);
4419 }
4420 }
4421
4422 void Assembler::xchgl(Register dst, Address src) { // xchg
4423 InstructionMark im(this);
4424 prefix(src, dst);
4425 emit_int8((unsigned char)0x87);
4426 emit_operand(dst, src);
4427 }
4428
4429 void Assembler::xchgl(Register dst, Register src) {
4430 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4431 emit_int8((unsigned char)0x87);
4432 emit_int8((unsigned char)(0xC0 | encode));
4433 }
4434
4435 void Assembler::xend() {
4436 emit_int8((unsigned char)0x0F);
4437 emit_int8((unsigned char)0x01);
4438 emit_int8((unsigned char)0xD5);
4439 }
4440
4441 void Assembler::xgetbv() {
4442 emit_int8(0x0F);
4443 emit_int8(0x01);
4444 emit_int8((unsigned char)0xD0);
4445 }
4446
4447 void Assembler::xorl(Register dst, int32_t imm32) {
4448 prefix(dst);
4449 emit_arith(0x81, 0xF0, dst, imm32);
4450 }
4451
4452 void Assembler::xorl(Register dst, Address src) {
4453 InstructionMark im(this);
4454 prefix(src, dst);
4455 emit_int8(0x33);
4456 emit_operand(dst, src);
4457 }
4458
4459 void Assembler::xorl(Register dst, Register src) {
4460 (void) prefix_and_encode(dst->encoding(), src->encoding());
4461 emit_arith(0x33, 0xC0, dst, src);
4462 }
4463
4464 void Assembler::xorb(Register dst, Address src) {
4465 InstructionMark im(this);
4466 prefix(src, dst);
4467 emit_int8(0x32);
4468 emit_operand(dst, src);
4469 }
4470
4471 // AVX 3-operands scalar float-point arithmetic instructions
4472
4473 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4474 assert(VM_Version::supports_avx(), "");
4475 InstructionMark im(this);
4476 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4477 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4478 attributes.set_rex_vex_w_reverted();
4479 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4480 emit_int8(0x58);
4481 emit_operand(dst, src);
4482 }
4483
4484 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4485 assert(VM_Version::supports_avx(), "");
4486 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4487 attributes.set_rex_vex_w_reverted();
4488 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4489 emit_int8(0x58);
4490 emit_int8((unsigned char)(0xC0 | encode));
4491 }
4492
4493 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4494 assert(VM_Version::supports_avx(), "");
4495 InstructionMark im(this);
4496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4498 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4499 emit_int8(0x58);
4500 emit_operand(dst, src);
4501 }
4502
4503 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4504 assert(VM_Version::supports_avx(), "");
4505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4506 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4507 emit_int8(0x58);
4508 emit_int8((unsigned char)(0xC0 | encode));
4509 }
4510
4511 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4512 assert(VM_Version::supports_avx(), "");
4513 InstructionMark im(this);
4514 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4515 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4516 attributes.set_rex_vex_w_reverted();
4517 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4518 emit_int8(0x5E);
4519 emit_operand(dst, src);
4520 }
4521
4522 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4523 assert(VM_Version::supports_avx(), "");
4524 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4525 attributes.set_rex_vex_w_reverted();
4526 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4527 emit_int8(0x5E);
4528 emit_int8((unsigned char)(0xC0 | encode));
4529 }
4530
4531 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4532 assert(VM_Version::supports_avx(), "");
4533 InstructionMark im(this);
4534 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4535 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4536 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4537 emit_int8(0x5E);
4538 emit_operand(dst, src);
4539 }
4540
4541 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4542 assert(VM_Version::supports_avx(), "");
4543 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4544 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4545 emit_int8(0x5E);
4546 emit_int8((unsigned char)(0xC0 | encode));
4547 }
4548
4549 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4550 assert(VM_Version::supports_avx(), "");
4551 InstructionMark im(this);
4552 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4553 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4554 attributes.set_rex_vex_w_reverted();
4555 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4556 emit_int8(0x59);
4557 emit_operand(dst, src);
4558 }
4559
4560 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4561 assert(VM_Version::supports_avx(), "");
4562 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4563 attributes.set_rex_vex_w_reverted();
4564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4565 emit_int8(0x59);
4566 emit_int8((unsigned char)(0xC0 | encode));
4567 }
4568
4569 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4570 assert(VM_Version::supports_avx(), "");
4571 InstructionMark im(this);
4572 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4573 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4574 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4575 emit_int8(0x59);
4576 emit_operand(dst, src);
4577 }
4578
4579 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4580 assert(VM_Version::supports_avx(), "");
4581 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4582 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4583 emit_int8(0x59);
4584 emit_int8((unsigned char)(0xC0 | encode));
4585 }
4586
4587 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4588 assert(VM_Version::supports_avx(), "");
4589 InstructionMark im(this);
4590 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4591 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4592 attributes.set_rex_vex_w_reverted();
4593 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4594 emit_int8(0x5C);
4595 emit_operand(dst, src);
4596 }
4597
4598 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4599 assert(VM_Version::supports_avx(), "");
4600 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4601 attributes.set_rex_vex_w_reverted();
4602 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4603 emit_int8(0x5C);
4604 emit_int8((unsigned char)(0xC0 | encode));
4605 }
4606
4607 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4608 assert(VM_Version::supports_avx(), "");
4609 InstructionMark im(this);
4610 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4611 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4612 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4613 emit_int8(0x5C);
4614 emit_operand(dst, src);
4615 }
4616
4617 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4618 assert(VM_Version::supports_avx(), "");
4619 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4620 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4621 emit_int8(0x5C);
4622 emit_int8((unsigned char)(0xC0 | encode));
4623 }
4624
4625 //====================VECTOR ARITHMETIC=====================================
4626
4627 // Float-point vector arithmetic
4628
4629 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4631 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4632 attributes.set_rex_vex_w_reverted();
4633 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4634 emit_int8(0x58);
4635 emit_int8((unsigned char)(0xC0 | encode));
4636 }
4637
4638 void Assembler::addpd(XMMRegister dst, Address src) {
4639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4640 InstructionMark im(this);
4641 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4642 attributes.set_rex_vex_w_reverted();
4643 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4644 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4645 emit_int8(0x58);
4646 emit_operand(dst, src);
4647 }
4648
4649
4650 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4652 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4653 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4654 emit_int8(0x58);
4655 emit_int8((unsigned char)(0xC0 | encode));
4656 }
4657
4658 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4659 assert(VM_Version::supports_avx(), "");
4660 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4661 attributes.set_rex_vex_w_reverted();
4662 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4663 emit_int8(0x58);
4664 emit_int8((unsigned char)(0xC0 | encode));
4665 }
4666
4667 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4668 assert(VM_Version::supports_avx(), "");
4669 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4670 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4671 emit_int8(0x58);
4672 emit_int8((unsigned char)(0xC0 | encode));
4673 }
4674
4675 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4676 assert(VM_Version::supports_avx(), "");
4677 InstructionMark im(this);
4678 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4679 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4680 attributes.set_rex_vex_w_reverted();
4681 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4682 emit_int8(0x58);
4683 emit_operand(dst, src);
4684 }
4685
4686 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4687 assert(VM_Version::supports_avx(), "");
4688 InstructionMark im(this);
4689 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4690 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4691 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4692 emit_int8(0x58);
4693 emit_operand(dst, src);
4694 }
4695
4696 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4698 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4699 attributes.set_rex_vex_w_reverted();
4700 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4701 emit_int8(0x5C);
4702 emit_int8((unsigned char)(0xC0 | encode));
4703 }
4704
4705 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4707 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4708 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4709 emit_int8(0x5C);
4710 emit_int8((unsigned char)(0xC0 | encode));
4711 }
4712
4713 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4714 assert(VM_Version::supports_avx(), "");
4715 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4716 attributes.set_rex_vex_w_reverted();
4717 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4718 emit_int8(0x5C);
4719 emit_int8((unsigned char)(0xC0 | encode));
4720 }
4721
4722 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4723 assert(VM_Version::supports_avx(), "");
4724 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4725 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4726 emit_int8(0x5C);
4727 emit_int8((unsigned char)(0xC0 | encode));
4728 }
4729
4730 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4731 assert(VM_Version::supports_avx(), "");
4732 InstructionMark im(this);
4733 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4734 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4735 attributes.set_rex_vex_w_reverted();
4736 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4737 emit_int8(0x5C);
4738 emit_operand(dst, src);
4739 }
4740
4741 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4742 assert(VM_Version::supports_avx(), "");
4743 InstructionMark im(this);
4744 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4745 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4746 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4747 emit_int8(0x5C);
4748 emit_operand(dst, src);
4749 }
4750
4751 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4753 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4754 attributes.set_rex_vex_w_reverted();
4755 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4756 emit_int8(0x59);
4757 emit_int8((unsigned char)(0xC0 | encode));
4758 }
4759
4760 void Assembler::mulpd(XMMRegister dst, Address src) {
4761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4762 InstructionMark im(this);
4763 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4764 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4765 attributes.set_rex_vex_w_reverted();
4766 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4767 emit_int8(0x59);
4768 emit_operand(dst, src);
4769 }
4770
4771 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4772 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4773 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4774 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4775 emit_int8(0x59);
4776 emit_int8((unsigned char)(0xC0 | encode));
4777 }
4778
4779 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4780 assert(VM_Version::supports_avx(), "");
4781 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4782 attributes.set_rex_vex_w_reverted();
4783 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4784 emit_int8(0x59);
4785 emit_int8((unsigned char)(0xC0 | encode));
4786 }
4787
4788 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4789 assert(VM_Version::supports_avx(), "");
4790 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4791 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4792 emit_int8(0x59);
4793 emit_int8((unsigned char)(0xC0 | encode));
4794 }
4795
4796 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4797 assert(VM_Version::supports_avx(), "");
4798 InstructionMark im(this);
4799 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4800 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4801 attributes.set_rex_vex_w_reverted();
4802 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4803 emit_int8(0x59);
4804 emit_operand(dst, src);
4805 }
4806
4807 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4808 assert(VM_Version::supports_avx(), "");
4809 InstructionMark im(this);
4810 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4811 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4812 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4813 emit_int8(0x59);
4814 emit_operand(dst, src);
4815 }
4816
4817 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4819 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4820 attributes.set_rex_vex_w_reverted();
4821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4822 emit_int8(0x5E);
4823 emit_int8((unsigned char)(0xC0 | encode));
4824 }
4825
4826 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4828 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4829 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4830 emit_int8(0x5E);
4831 emit_int8((unsigned char)(0xC0 | encode));
4832 }
4833
4834 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4835 assert(VM_Version::supports_avx(), "");
4836 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4837 attributes.set_rex_vex_w_reverted();
4838 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4839 emit_int8(0x5E);
4840 emit_int8((unsigned char)(0xC0 | encode));
4841 }
4842
4843 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4844 assert(VM_Version::supports_avx(), "");
4845 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4846 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4847 emit_int8(0x5E);
4848 emit_int8((unsigned char)(0xC0 | encode));
4849 }
4850
4851 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4852 assert(VM_Version::supports_avx(), "");
4853 InstructionMark im(this);
4854 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4855 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4856 attributes.set_rex_vex_w_reverted();
4857 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4858 emit_int8(0x5E);
4859 emit_operand(dst, src);
4860 }
4861
4862 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4863 assert(VM_Version::supports_avx(), "");
4864 InstructionMark im(this);
4865 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4866 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4867 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4868 emit_int8(0x5E);
4869 emit_operand(dst, src);
4870 }
4871
4872 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4873 assert(VM_Version::supports_avx(), "");
4874 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4875 attributes.set_rex_vex_w_reverted();
4876 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4877 emit_int8(0x51);
4878 emit_int8((unsigned char)(0xC0 | encode));
4879 }
4880
4881 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4882 assert(VM_Version::supports_avx(), "");
4883 InstructionMark im(this);
4884 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4885 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4886 attributes.set_rex_vex_w_reverted();
4887 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4888 emit_int8(0x51);
4889 emit_operand(dst, src);
4890 }
4891
4892 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4894 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4895 attributes.set_rex_vex_w_reverted();
4896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4897 emit_int8(0x54);
4898 emit_int8((unsigned char)(0xC0 | encode));
4899 }
4900
4901 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4902 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4903 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4904 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4905 emit_int8(0x54);
4906 emit_int8((unsigned char)(0xC0 | encode));
4907 }
4908
4909 void Assembler::andps(XMMRegister dst, Address src) {
4910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4911 InstructionMark im(this);
4912 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4913 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4914 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4915 emit_int8(0x54);
4916 emit_operand(dst, src);
4917 }
4918
4919 void Assembler::andpd(XMMRegister dst, Address src) {
4920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4921 InstructionMark im(this);
4922 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4923 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4924 attributes.set_rex_vex_w_reverted();
4925 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4926 emit_int8(0x54);
4927 emit_operand(dst, src);
4928 }
4929
4930 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4931 assert(VM_Version::supports_avx(), "");
4932 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4933 attributes.set_rex_vex_w_reverted();
4934 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4935 emit_int8(0x54);
4936 emit_int8((unsigned char)(0xC0 | encode));
4937 }
4938
4939 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4940 assert(VM_Version::supports_avx(), "");
4941 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4942 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4943 emit_int8(0x54);
4944 emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946
4947 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4948 assert(VM_Version::supports_avx(), "");
4949 InstructionMark im(this);
4950 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4951 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4952 attributes.set_rex_vex_w_reverted();
4953 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4954 emit_int8(0x54);
4955 emit_operand(dst, src);
4956 }
4957
4958 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4959 assert(VM_Version::supports_avx(), "");
4960 InstructionMark im(this);
4961 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4962 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4963 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4964 emit_int8(0x54);
4965 emit_operand(dst, src);
4966 }
4967
4968 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4969 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4970 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4971 attributes.set_rex_vex_w_reverted();
4972 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4973 emit_int8(0x15);
4974 emit_int8((unsigned char)(0xC0 | encode));
4975 }
4976
4977 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4978 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4979 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4980 attributes.set_rex_vex_w_reverted();
4981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4982 emit_int8(0x14);
4983 emit_int8((unsigned char)(0xC0 | encode));
4984 }
4985
4986 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4988 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4989 attributes.set_rex_vex_w_reverted();
4990 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4991 emit_int8(0x57);
4992 emit_int8((unsigned char)(0xC0 | encode));
4993 }
4994
4995 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4996 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4997 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4998 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4999 emit_int8(0x57);
5000 emit_int8((unsigned char)(0xC0 | encode));
5001 }
5002
5003 void Assembler::xorpd(XMMRegister dst, Address src) {
5004 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5005 InstructionMark im(this);
5006 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5007 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5008 attributes.set_rex_vex_w_reverted();
5009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5010 emit_int8(0x57);
5011 emit_operand(dst, src);
5012 }
5013
5014 void Assembler::xorps(XMMRegister dst, Address src) {
5015 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5016 InstructionMark im(this);
5017 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5018 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5019 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5020 emit_int8(0x57);
5021 emit_operand(dst, src);
5022 }
5023
5024 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5025 assert(VM_Version::supports_avx(), "");
5026 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5027 attributes.set_rex_vex_w_reverted();
5028 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5029 emit_int8(0x57);
5030 emit_int8((unsigned char)(0xC0 | encode));
5031 }
5032
5033 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5034 assert(VM_Version::supports_avx(), "");
5035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5036 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5037 emit_int8(0x57);
5038 emit_int8((unsigned char)(0xC0 | encode));
5039 }
5040
5041 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5042 assert(VM_Version::supports_avx(), "");
5043 InstructionMark im(this);
5044 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5045 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5046 attributes.set_rex_vex_w_reverted();
5047 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5048 emit_int8(0x57);
5049 emit_operand(dst, src);
5050 }
5051
5052 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5053 assert(VM_Version::supports_avx(), "");
5054 InstructionMark im(this);
5055 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5056 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5057 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5058 emit_int8(0x57);
5059 emit_operand(dst, src);
5060 }
5061
5062 // Integer vector arithmetic
5063 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5064 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5065 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5067 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5068 emit_int8(0x01);
5069 emit_int8((unsigned char)(0xC0 | encode));
5070 }
5071
5072 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5073 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5074 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5075 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5077 emit_int8(0x02);
5078 emit_int8((unsigned char)(0xC0 | encode));
5079 }
5080
5081 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5084 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5085 emit_int8((unsigned char)0xFC);
5086 emit_int8((unsigned char)(0xC0 | encode));
5087 }
5088
5089 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5091 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5092 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5093 emit_int8((unsigned char)0xFD);
5094 emit_int8((unsigned char)(0xC0 | encode));
5095 }
5096
5097 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5100 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5101 emit_int8((unsigned char)0xFE);
5102 emit_int8((unsigned char)(0xC0 | encode));
5103 }
5104
5105 void Assembler::paddd(XMMRegister dst, Address src) {
5106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5107 InstructionMark im(this);
5108 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5109 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5110 emit_int8((unsigned char)0xFE);
5111 emit_operand(dst, src);
5112 }
5113
5114 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5115 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5116 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5117 attributes.set_rex_vex_w_reverted();
5118 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5119 emit_int8((unsigned char)0xD4);
5120 emit_int8((unsigned char)(0xC0 | encode));
5121 }
5122
5123 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5124 assert(VM_Version::supports_sse3(), "");
5125 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5126 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5127 emit_int8(0x01);
5128 emit_int8((unsigned char)(0xC0 | encode));
5129 }
5130
5131 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5132 assert(VM_Version::supports_sse3(), "");
5133 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5134 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5135 emit_int8(0x02);
5136 emit_int8((unsigned char)(0xC0 | encode));
5137 }
5138
5139 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5140 assert(UseAVX > 0, "requires some form of AVX");
5141 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5142 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5143 emit_int8((unsigned char)0xFC);
5144 emit_int8((unsigned char)(0xC0 | encode));
5145 }
5146
5147 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5148 assert(UseAVX > 0, "requires some form of AVX");
5149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5150 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5151 emit_int8((unsigned char)0xFD);
5152 emit_int8((unsigned char)(0xC0 | encode));
5153 }
5154
5155 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5156 assert(UseAVX > 0, "requires some form of AVX");
5157 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5158 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5159 emit_int8((unsigned char)0xFE);
5160 emit_int8((unsigned char)(0xC0 | encode));
5161 }
5162
5163 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5164 assert(UseAVX > 0, "requires some form of AVX");
5165 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5166 attributes.set_rex_vex_w_reverted();
5167 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5168 emit_int8((unsigned char)0xD4);
5169 emit_int8((unsigned char)(0xC0 | encode));
5170 }
5171
5172 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5173 assert(UseAVX > 0, "requires some form of AVX");
5174 InstructionMark im(this);
5175 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5176 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5177 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5178 emit_int8((unsigned char)0xFC);
5179 emit_operand(dst, src);
5180 }
5181
5182 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5183 assert(UseAVX > 0, "requires some form of AVX");
5184 InstructionMark im(this);
5185 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5186 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5187 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5188 emit_int8((unsigned char)0xFD);
5189 emit_operand(dst, src);
5190 }
5191
5192 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5193 assert(UseAVX > 0, "requires some form of AVX");
5194 InstructionMark im(this);
5195 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5196 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5197 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5198 emit_int8((unsigned char)0xFE);
5199 emit_operand(dst, src);
5200 }
5201
5202 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5203 assert(UseAVX > 0, "requires some form of AVX");
5204 InstructionMark im(this);
5205 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5206 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5207 attributes.set_rex_vex_w_reverted();
5208 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5209 emit_int8((unsigned char)0xD4);
5210 emit_operand(dst, src);
5211 }
5212
5213 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5215 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5216 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5217 emit_int8((unsigned char)0xF8);
5218 emit_int8((unsigned char)(0xC0 | encode));
5219 }
5220
5221 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5223 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5224 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5225 emit_int8((unsigned char)0xF9);
5226 emit_int8((unsigned char)(0xC0 | encode));
5227 }
5228
5229 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5230 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5231 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5232 emit_int8((unsigned char)0xFA);
5233 emit_int8((unsigned char)(0xC0 | encode));
5234 }
5235
5236 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5237 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5238 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5239 attributes.set_rex_vex_w_reverted();
5240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5241 emit_int8((unsigned char)0xFB);
5242 emit_int8((unsigned char)(0xC0 | encode));
5243 }
5244
5245 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5246 assert(UseAVX > 0, "requires some form of AVX");
5247 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5248 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5249 emit_int8((unsigned char)0xF8);
5250 emit_int8((unsigned char)(0xC0 | encode));
5251 }
5252
5253 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5254 assert(UseAVX > 0, "requires some form of AVX");
5255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5256 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5257 emit_int8((unsigned char)0xF9);
5258 emit_int8((unsigned char)(0xC0 | encode));
5259 }
5260
5261 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5262 assert(UseAVX > 0, "requires some form of AVX");
5263 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5264 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5265 emit_int8((unsigned char)0xFA);
5266 emit_int8((unsigned char)(0xC0 | encode));
5267 }
5268
5269 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5270 assert(UseAVX > 0, "requires some form of AVX");
5271 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5272 attributes.set_rex_vex_w_reverted();
5273 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5274 emit_int8((unsigned char)0xFB);
5275 emit_int8((unsigned char)(0xC0 | encode));
5276 }
5277
5278 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5279 assert(UseAVX > 0, "requires some form of AVX");
5280 InstructionMark im(this);
5281 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5282 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5283 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5284 emit_int8((unsigned char)0xF8);
5285 emit_operand(dst, src);
5286 }
5287
5288 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5289 assert(UseAVX > 0, "requires some form of AVX");
5290 InstructionMark im(this);
5291 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5292 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5293 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5294 emit_int8((unsigned char)0xF9);
5295 emit_operand(dst, src);
5296 }
5297
5298 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5299 assert(UseAVX > 0, "requires some form of AVX");
5300 InstructionMark im(this);
5301 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5302 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5303 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5304 emit_int8((unsigned char)0xFA);
5305 emit_operand(dst, src);
5306 }
5307
5308 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5309 assert(UseAVX > 0, "requires some form of AVX");
5310 InstructionMark im(this);
5311 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5312 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5313 attributes.set_rex_vex_w_reverted();
5314 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5315 emit_int8((unsigned char)0xFB);
5316 emit_operand(dst, src);
5317 }
5318
5319 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5323 emit_int8((unsigned char)0xD5);
5324 emit_int8((unsigned char)(0xC0 | encode));
5325 }
5326
5327 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5328 assert(VM_Version::supports_sse4_1(), "");
5329 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5330 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5331 emit_int8(0x40);
5332 emit_int8((unsigned char)(0xC0 | encode));
5333 }
5334
5335 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5336 assert(UseAVX > 0, "requires some form of AVX");
5337 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5338 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5339 emit_int8((unsigned char)0xD5);
5340 emit_int8((unsigned char)(0xC0 | encode));
5341 }
5342
5343 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5344 assert(UseAVX > 0, "requires some form of AVX");
5345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5346 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5347 emit_int8(0x40);
5348 emit_int8((unsigned char)(0xC0 | encode));
5349 }
5350
5351 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5352 assert(UseAVX > 2, "requires some form of EVEX");
5353 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5354 attributes.set_is_evex_instruction();
5355 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5356 emit_int8(0x40);
5357 emit_int8((unsigned char)(0xC0 | encode));
5358 }
5359
5360 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5361 assert(UseAVX > 0, "requires some form of AVX");
5362 InstructionMark im(this);
5363 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5365 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5366 emit_int8((unsigned char)0xD5);
5367 emit_operand(dst, src);
5368 }
5369
5370 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5371 assert(UseAVX > 0, "requires some form of AVX");
5372 InstructionMark im(this);
5373 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5374 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5375 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5376 emit_int8(0x40);
5377 emit_operand(dst, src);
5378 }
5379
5380 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5381 assert(UseAVX > 2, "requires some form of EVEX");
5382 InstructionMark im(this);
5383 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5384 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5385 attributes.set_is_evex_instruction();
5386 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5387 emit_int8(0x40);
5388 emit_operand(dst, src);
5389 }
5390
5391 // Shift packed integers left by specified number of bits.
5392 void Assembler::psllw(XMMRegister dst, int shift) {
5393 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5395 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5396 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5397 emit_int8(0x71);
5398 emit_int8((unsigned char)(0xC0 | encode));
5399 emit_int8(shift & 0xFF);
5400 }
5401
5402 void Assembler::pslld(XMMRegister dst, int shift) {
5403 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5404 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5405 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5406 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5407 emit_int8(0x72);
5408 emit_int8((unsigned char)(0xC0 | encode));
5409 emit_int8(shift & 0xFF);
5410 }
5411
5412 void Assembler::psllq(XMMRegister dst, int shift) {
5413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5414 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5415 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5416 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5417 emit_int8(0x73);
5418 emit_int8((unsigned char)(0xC0 | encode));
5419 emit_int8(shift & 0xFF);
5420 }
5421
5422 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5424 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5425 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5426 emit_int8((unsigned char)0xF1);
5427 emit_int8((unsigned char)(0xC0 | encode));
5428 }
5429
5430 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5431 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5432 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5433 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5434 emit_int8((unsigned char)0xF2);
5435 emit_int8((unsigned char)(0xC0 | encode));
5436 }
5437
5438 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5440 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5441 attributes.set_rex_vex_w_reverted();
5442 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5443 emit_int8((unsigned char)0xF3);
5444 emit_int8((unsigned char)(0xC0 | encode));
5445 }
5446
5447 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5448 assert(UseAVX > 0, "requires some form of AVX");
5449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5450 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5451 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5452 emit_int8(0x71);
5453 emit_int8((unsigned char)(0xC0 | encode));
5454 emit_int8(shift & 0xFF);
5455 }
5456
5457 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5458 assert(UseAVX > 0, "requires some form of AVX");
5459 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5460 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5461 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5462 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5463 emit_int8(0x72);
5464 emit_int8((unsigned char)(0xC0 | encode));
5465 emit_int8(shift & 0xFF);
5466 }
5467
5468 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5469 assert(UseAVX > 0, "requires some form of AVX");
5470 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5471 attributes.set_rex_vex_w_reverted();
5472 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5473 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5474 emit_int8(0x73);
5475 emit_int8((unsigned char)(0xC0 | encode));
5476 emit_int8(shift & 0xFF);
5477 }
5478
5479 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5480 assert(UseAVX > 0, "requires some form of AVX");
5481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5482 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5483 emit_int8((unsigned char)0xF1);
5484 emit_int8((unsigned char)(0xC0 | encode));
5485 }
5486
5487 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5488 assert(UseAVX > 0, "requires some form of AVX");
5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5490 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5491 emit_int8((unsigned char)0xF2);
5492 emit_int8((unsigned char)(0xC0 | encode));
5493 }
5494
5495 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5496 assert(UseAVX > 0, "requires some form of AVX");
5497 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5498 attributes.set_rex_vex_w_reverted();
5499 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5500 emit_int8((unsigned char)0xF3);
5501 emit_int8((unsigned char)(0xC0 | encode));
5502 }
5503
5504 // Shift packed integers logically right by specified number of bits.
5505 void Assembler::psrlw(XMMRegister dst, int shift) {
5506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5507 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5508 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5509 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5510 emit_int8(0x71);
5511 emit_int8((unsigned char)(0xC0 | encode));
5512 emit_int8(shift & 0xFF);
5513 }
5514
5515 void Assembler::psrld(XMMRegister dst, int shift) {
5516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5517 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5518 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5519 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5520 emit_int8(0x72);
5521 emit_int8((unsigned char)(0xC0 | encode));
5522 emit_int8(shift & 0xFF);
5523 }
5524
5525 void Assembler::psrlq(XMMRegister dst, int shift) {
5526 // Do not confuse it with psrldq SSE2 instruction which
5527 // shifts 128 bit value in xmm register by number of bytes.
5528 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5529 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5530 attributes.set_rex_vex_w_reverted();
5531 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5532 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5533 emit_int8(0x73);
5534 emit_int8((unsigned char)(0xC0 | encode));
5535 emit_int8(shift & 0xFF);
5536 }
5537
5538 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5539 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5540 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5541 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5542 emit_int8((unsigned char)0xD1);
5543 emit_int8((unsigned char)(0xC0 | encode));
5544 }
5545
5546 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5549 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5550 emit_int8((unsigned char)0xD2);
5551 emit_int8((unsigned char)(0xC0 | encode));
5552 }
5553
5554 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5555 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5556 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5557 attributes.set_rex_vex_w_reverted();
5558 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5559 emit_int8((unsigned char)0xD3);
5560 emit_int8((unsigned char)(0xC0 | encode));
5561 }
5562
5563 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5564 assert(UseAVX > 0, "requires some form of AVX");
5565 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5566 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5567 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5568 emit_int8(0x71);
5569 emit_int8((unsigned char)(0xC0 | encode));
5570 emit_int8(shift & 0xFF);
5571 }
5572
5573 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5574 assert(UseAVX > 0, "requires some form of AVX");
5575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5576 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5577 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5578 emit_int8(0x72);
5579 emit_int8((unsigned char)(0xC0 | encode));
5580 emit_int8(shift & 0xFF);
5581 }
5582
5583 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5584 assert(UseAVX > 0, "requires some form of AVX");
5585 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5586 attributes.set_rex_vex_w_reverted();
5587 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5588 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5589 emit_int8(0x73);
5590 emit_int8((unsigned char)(0xC0 | encode));
5591 emit_int8(shift & 0xFF);
5592 }
5593
5594 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5595 assert(UseAVX > 0, "requires some form of AVX");
5596 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5597 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5598 emit_int8((unsigned char)0xD1);
5599 emit_int8((unsigned char)(0xC0 | encode));
5600 }
5601
5602 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5603 assert(UseAVX > 0, "requires some form of AVX");
5604 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5605 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5606 emit_int8((unsigned char)0xD2);
5607 emit_int8((unsigned char)(0xC0 | encode));
5608 }
5609
5610 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5611 assert(UseAVX > 0, "requires some form of AVX");
5612 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5613 attributes.set_rex_vex_w_reverted();
5614 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5615 emit_int8((unsigned char)0xD3);
5616 emit_int8((unsigned char)(0xC0 | encode));
5617 }
5618
5619 // Shift packed integers arithmetically right by specified number of bits.
5620 void Assembler::psraw(XMMRegister dst, int shift) {
5621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5623 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5624 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5625 emit_int8(0x71);
5626 emit_int8((unsigned char)(0xC0 | encode));
5627 emit_int8(shift & 0xFF);
5628 }
5629
5630 void Assembler::psrad(XMMRegister dst, int shift) {
5631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5632 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5633 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5634 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5635 emit_int8(0x72);
5636 emit_int8((unsigned char)(0xC0 | encode));
5637 emit_int8(shift & 0xFF);
5638 }
5639
5640 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5641 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5643 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5644 emit_int8((unsigned char)0xE1);
5645 emit_int8((unsigned char)(0xC0 | encode));
5646 }
5647
5648 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5649 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5650 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5651 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5652 emit_int8((unsigned char)0xE2);
5653 emit_int8((unsigned char)(0xC0 | encode));
5654 }
5655
5656 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5657 assert(UseAVX > 0, "requires some form of AVX");
5658 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5659 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5660 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5661 emit_int8(0x71);
5662 emit_int8((unsigned char)(0xC0 | encode));
5663 emit_int8(shift & 0xFF);
5664 }
5665
5666 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5667 assert(UseAVX > 0, "requires some form of AVX");
5668 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5669 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5670 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5671 emit_int8(0x72);
5672 emit_int8((unsigned char)(0xC0 | encode));
5673 emit_int8(shift & 0xFF);
5674 }
5675
5676 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5677 assert(UseAVX > 0, "requires some form of AVX");
5678 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5679 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5680 emit_int8((unsigned char)0xE1);
5681 emit_int8((unsigned char)(0xC0 | encode));
5682 }
5683
5684 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5685 assert(UseAVX > 0, "requires some form of AVX");
5686 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5687 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5688 emit_int8((unsigned char)0xE2);
5689 emit_int8((unsigned char)(0xC0 | encode));
5690 }
5691
5692
5693 // logical operations packed integers
5694 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5697 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5698 emit_int8((unsigned char)0xDB);
5699 emit_int8((unsigned char)(0xC0 | encode));
5700 }
5701
5702 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5703 assert(UseAVX > 0, "requires some form of AVX");
5704 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5705 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706 emit_int8((unsigned char)0xDB);
5707 emit_int8((unsigned char)(0xC0 | encode));
5708 }
5709
5710 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5711 assert(UseAVX > 0, "requires some form of AVX");
5712 InstructionMark im(this);
5713 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5714 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5715 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5716 emit_int8((unsigned char)0xDB);
5717 emit_operand(dst, src);
5718 }
5719
5720 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5722 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5723 attributes.set_rex_vex_w_reverted();
5724 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5725 emit_int8((unsigned char)0xDF);
5726 emit_int8((unsigned char)(0xC0 | encode));
5727 }
5728
5729 void Assembler::por(XMMRegister dst, XMMRegister src) {
5730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5731 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5733 emit_int8((unsigned char)0xEB);
5734 emit_int8((unsigned char)(0xC0 | encode));
5735 }
5736
5737 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5738 assert(UseAVX > 0, "requires some form of AVX");
5739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5740 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5741 emit_int8((unsigned char)0xEB);
5742 emit_int8((unsigned char)(0xC0 | encode));
5743 }
5744
5745 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5746 assert(UseAVX > 0, "requires some form of AVX");
5747 InstructionMark im(this);
5748 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5749 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5750 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5751 emit_int8((unsigned char)0xEB);
5752 emit_operand(dst, src);
5753 }
5754
5755 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5757 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5759 emit_int8((unsigned char)0xEF);
5760 emit_int8((unsigned char)(0xC0 | encode));
5761 }
5762
5763 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5764 assert(UseAVX > 0, "requires some form of AVX");
5765 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5766 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5767 emit_int8((unsigned char)0xEF);
5768 emit_int8((unsigned char)(0xC0 | encode));
5769 }
5770
5771 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5772 assert(UseAVX > 0, "requires some form of AVX");
5773 InstructionMark im(this);
5774 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5775 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5776 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5777 emit_int8((unsigned char)0xEF);
5778 emit_operand(dst, src);
5779 }
5780
5781
5782 // vinserti forms
5783
5784 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5785 assert(VM_Version::supports_avx2(), "");
5786 assert(imm8 <= 0x01, "imm8: %u", imm8);
5787 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5788 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5789 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5790 emit_int8(0x38);
5791 emit_int8((unsigned char)(0xC0 | encode));
5792 // 0x00 - insert into lower 128 bits
5793 // 0x01 - insert into upper 128 bits
5794 emit_int8(imm8 & 0x01);
5795 }
5796
5797 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5798 assert(VM_Version::supports_avx2(), "");
5799 assert(dst != xnoreg, "sanity");
5800 assert(imm8 <= 0x01, "imm8: %u", imm8);
5801 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5802 InstructionMark im(this);
5803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5804 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5805 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5806 emit_int8(0x38);
5807 emit_operand(dst, src);
5808 // 0x00 - insert into lower 128 bits
5809 // 0x01 - insert into upper 128 bits
5810 emit_int8(imm8 & 0x01);
5811 }
5812
5813 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5814 assert(VM_Version::supports_evex(), "");
5815 assert(imm8 <= 0x03, "imm8: %u", imm8);
5816 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5818 emit_int8(0x38);
5819 emit_int8((unsigned char)(0xC0 | encode));
5820 // 0x00 - insert into q0 128 bits (0..127)
5821 // 0x01 - insert into q1 128 bits (128..255)
5822 // 0x02 - insert into q2 128 bits (256..383)
5823 // 0x03 - insert into q3 128 bits (384..511)
5824 emit_int8(imm8 & 0x03);
5825 }
5826
5827 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5828 assert(VM_Version::supports_avx(), "");
5829 assert(dst != xnoreg, "sanity");
5830 assert(imm8 <= 0x03, "imm8: %u", imm8);
5831 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5832 InstructionMark im(this);
5833 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5834 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5835 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5836 emit_int8(0x18);
5837 emit_operand(dst, src);
5838 // 0x00 - insert into q0 128 bits (0..127)
5839 // 0x01 - insert into q1 128 bits (128..255)
5840 // 0x02 - insert into q2 128 bits (256..383)
5841 // 0x03 - insert into q3 128 bits (384..511)
5842 emit_int8(imm8 & 0x03);
5843 }
5844
5845 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5846 assert(VM_Version::supports_evex(), "");
5847 assert(imm8 <= 0x01, "imm8: %u", imm8);
5848 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5849 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5850 emit_int8(0x38);
5851 emit_int8((unsigned char)(0xC0 | encode));
5852 // 0x00 - insert into lower 256 bits
5853 // 0x01 - insert into upper 256 bits
5854 emit_int8(imm8 & 0x01);
5855 }
5856
5857
5858 // vinsertf forms
5859
5860 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5861 assert(VM_Version::supports_avx(), "");
5862 assert(imm8 <= 0x01, "imm8: %u", imm8);
5863 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5864 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5865 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5866 emit_int8(0x18);
5867 emit_int8((unsigned char)(0xC0 | encode));
5868 // 0x00 - insert into lower 128 bits
5869 // 0x01 - insert into upper 128 bits
5870 emit_int8(imm8 & 0x01);
5871 }
5872
5873 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5874 assert(VM_Version::supports_avx(), "");
5875 assert(dst != xnoreg, "sanity");
5876 assert(imm8 <= 0x01, "imm8: %u", imm8);
5877 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5878 InstructionMark im(this);
5879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5880 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5881 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5882 emit_int8(0x18);
5883 emit_operand(dst, src);
5884 // 0x00 - insert into lower 128 bits
5885 // 0x01 - insert into upper 128 bits
5886 emit_int8(imm8 & 0x01);
5887 }
5888
5889 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5890 assert(VM_Version::supports_evex(), "");
5891 assert(imm8 <= 0x03, "imm8: %u", imm8);
5892 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5893 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5894 emit_int8(0x18);
5895 emit_int8((unsigned char)(0xC0 | encode));
5896 // 0x00 - insert into q0 128 bits (0..127)
5897 // 0x01 - insert into q1 128 bits (128..255)
5898 // 0x02 - insert into q2 128 bits (256..383)
5899 // 0x03 - insert into q3 128 bits (384..511)
5900 emit_int8(imm8 & 0x03);
5901 }
5902
5903 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5904 assert(VM_Version::supports_avx(), "");
5905 assert(dst != xnoreg, "sanity");
5906 assert(imm8 <= 0x03, "imm8: %u", imm8);
5907 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5908 InstructionMark im(this);
5909 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5910 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5911 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5912 emit_int8(0x18);
5913 emit_operand(dst, src);
5914 // 0x00 - insert into q0 128 bits (0..127)
5915 // 0x01 - insert into q1 128 bits (128..255)
5916 // 0x02 - insert into q2 128 bits (256..383)
5917 // 0x03 - insert into q3 128 bits (384..511)
5918 emit_int8(imm8 & 0x03);
5919 }
5920
5921 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5922 assert(VM_Version::supports_evex(), "");
5923 assert(imm8 <= 0x01, "imm8: %u", imm8);
5924 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5925 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5926 emit_int8(0x1A);
5927 emit_int8((unsigned char)(0xC0 | encode));
5928 // 0x00 - insert into lower 256 bits
5929 // 0x01 - insert into upper 256 bits
5930 emit_int8(imm8 & 0x01);
5931 }
5932
5933 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5934 assert(VM_Version::supports_evex(), "");
5935 assert(dst != xnoreg, "sanity");
5936 assert(imm8 <= 0x01, "imm8: %u", imm8);
5937 InstructionMark im(this);
5938 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5939 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5940 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5941 emit_int8(0x1A);
5942 emit_operand(dst, src);
5943 // 0x00 - insert into lower 256 bits
5944 // 0x01 - insert into upper 256 bits
5945 emit_int8(imm8 & 0x01);
5946 }
5947
5948
5949 // vextracti forms
5950
5951 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5952 assert(VM_Version::supports_avx(), "");
5953 assert(imm8 <= 0x01, "imm8: %u", imm8);
5954 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5956 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5957 emit_int8(0x39);
5958 emit_int8((unsigned char)(0xC0 | encode));
5959 // 0x00 - extract from lower 128 bits
5960 // 0x01 - extract from upper 128 bits
5961 emit_int8(imm8 & 0x01);
5962 }
5963
5964 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5965 assert(VM_Version::supports_avx2(), "");
5966 assert(src != xnoreg, "sanity");
5967 assert(imm8 <= 0x01, "imm8: %u", imm8);
5968 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5969 InstructionMark im(this);
5970 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5971 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5972 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5973 emit_int8(0x39);
5974 emit_operand(src, dst);
5975 // 0x00 - extract from lower 128 bits
5976 // 0x01 - extract from upper 128 bits
5977 emit_int8(imm8 & 0x01);
5978 }
5979
5980 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5981 assert(VM_Version::supports_avx(), "");
5982 assert(imm8 <= 0x03, "imm8: %u", imm8);
5983 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5984 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5985 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5986 emit_int8(0x39);
5987 emit_int8((unsigned char)(0xC0 | encode));
5988 // 0x00 - extract from bits 127:0
5989 // 0x01 - extract from bits 255:128
5990 // 0x02 - extract from bits 383:256
5991 // 0x03 - extract from bits 511:384
5992 emit_int8(imm8 & 0x03);
5993 }
5994
5995 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
5996 assert(VM_Version::supports_evex(), "");
5997 assert(src != xnoreg, "sanity");
5998 assert(imm8 <= 0x03, "imm8: %u", imm8);
5999 InstructionMark im(this);
6000 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6001 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6002 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6003 emit_int8(0x39);
6004 emit_operand(src, dst);
6005 // 0x00 - extract from bits 127:0
6006 // 0x01 - extract from bits 255:128
6007 // 0x02 - extract from bits 383:256
6008 // 0x03 - extract from bits 511:384
6009 emit_int8(imm8 & 0x03);
6010 }
6011
6012 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6013 assert(VM_Version::supports_avx512dq(), "");
6014 assert(imm8 <= 0x03, "imm8: %u", imm8);
6015 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6016 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6017 emit_int8(0x39);
6018 emit_int8((unsigned char)(0xC0 | encode));
6019 // 0x00 - extract from bits 127:0
6020 // 0x01 - extract from bits 255:128
6021 // 0x02 - extract from bits 383:256
6022 // 0x03 - extract from bits 511:384
6023 emit_int8(imm8 & 0x03);
6024 }
6025
6026 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6027 assert(VM_Version::supports_evex(), "");
6028 assert(imm8 <= 0x01, "imm8: %u", imm8);
6029 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6030 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6031 emit_int8(0x3B);
6032 emit_int8((unsigned char)(0xC0 | encode));
6033 // 0x00 - extract from lower 256 bits
6034 // 0x01 - extract from upper 256 bits
6035 emit_int8(imm8 & 0x01);
6036 }
6037
6038
6039 // vextractf forms
6040
6041 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6042 assert(VM_Version::supports_avx(), "");
6043 assert(imm8 <= 0x01, "imm8: %u", imm8);
6044 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6045 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6046 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6047 emit_int8(0x19);
6048 emit_int8((unsigned char)(0xC0 | encode));
6049 // 0x00 - extract from lower 128 bits
6050 // 0x01 - extract from upper 128 bits
6051 emit_int8(imm8 & 0x01);
6052 }
6053
6054 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6055 assert(VM_Version::supports_avx(), "");
6056 assert(src != xnoreg, "sanity");
6057 assert(imm8 <= 0x01, "imm8: %u", imm8);
6058 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6059 InstructionMark im(this);
6060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6061 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6062 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6063 emit_int8(0x19);
6064 emit_operand(src, dst);
6065 // 0x00 - extract from lower 128 bits
6066 // 0x01 - extract from upper 128 bits
6067 emit_int8(imm8 & 0x01);
6068 }
6069
6070 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6071 assert(VM_Version::supports_avx(), "");
6072 assert(imm8 <= 0x03, "imm8: %u", imm8);
6073 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6074 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6075 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6076 emit_int8(0x19);
6077 emit_int8((unsigned char)(0xC0 | encode));
6078 // 0x00 - extract from bits 127:0
6079 // 0x01 - extract from bits 255:128
6080 // 0x02 - extract from bits 383:256
6081 // 0x03 - extract from bits 511:384
6082 emit_int8(imm8 & 0x03);
6083 }
6084
6085 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6086 assert(VM_Version::supports_evex(), "");
6087 assert(src != xnoreg, "sanity");
6088 assert(imm8 <= 0x03, "imm8: %u", imm8);
6089 InstructionMark im(this);
6090 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6091 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6092 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6093 emit_int8(0x19);
6094 emit_operand(src, dst);
6095 // 0x00 - extract from bits 127:0
6096 // 0x01 - extract from bits 255:128
6097 // 0x02 - extract from bits 383:256
6098 // 0x03 - extract from bits 511:384
6099 emit_int8(imm8 & 0x03);
6100 }
6101
6102 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6103 assert(VM_Version::supports_avx512dq(), "");
6104 assert(imm8 <= 0x03, "imm8: %u", imm8);
6105 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6106 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6107 emit_int8(0x19);
6108 emit_int8((unsigned char)(0xC0 | encode));
6109 // 0x00 - extract from bits 127:0
6110 // 0x01 - extract from bits 255:128
6111 // 0x02 - extract from bits 383:256
6112 // 0x03 - extract from bits 511:384
6113 emit_int8(imm8 & 0x03);
6114 }
6115
6116 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6117 assert(VM_Version::supports_evex(), "");
6118 assert(imm8 <= 0x01, "imm8: %u", imm8);
6119 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6120 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6121 emit_int8(0x1B);
6122 emit_int8((unsigned char)(0xC0 | encode));
6123 // 0x00 - extract from lower 256 bits
6124 // 0x01 - extract from upper 256 bits
6125 emit_int8(imm8 & 0x01);
6126 }
6127
6128 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6129 assert(VM_Version::supports_evex(), "");
6130 assert(src != xnoreg, "sanity");
6131 assert(imm8 <= 0x01, "imm8: %u", imm8);
6132 InstructionMark im(this);
6133 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6134 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6135 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6136 emit_int8(0x1B);
6137 emit_operand(src, dst);
6138 // 0x00 - extract from lower 256 bits
6139 // 0x01 - extract from upper 256 bits
6140 emit_int8(imm8 & 0x01);
6141 }
6142
6143
6144 // legacy word/dword replicate
6145 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6146 assert(VM_Version::supports_avx2(), "");
6147 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6148 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6149 emit_int8(0x79);
6150 emit_int8((unsigned char)(0xC0 | encode));
6151 }
6152
6153 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6154 assert(VM_Version::supports_avx2(), "");
6155 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6156 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6157 emit_int8(0x58);
6158 emit_int8((unsigned char)(0xC0 | encode));
6159 }
6160
6161
6162 // xmm/mem sourced byte/word/dword/qword replicate
6163
6164 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6165 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6166 assert(VM_Version::supports_evex(), "");
6167 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6168 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6169 emit_int8(0x78);
6170 emit_int8((unsigned char)(0xC0 | encode));
6171 }
6172
6173 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6174 assert(VM_Version::supports_evex(), "");
6175 assert(dst != xnoreg, "sanity");
6176 InstructionMark im(this);
6177 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6178 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6179 // swap src<->dst for encoding
6180 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6181 emit_int8(0x78);
6182 emit_operand(dst, src);
6183 }
6184
6185 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6186 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6187 assert(VM_Version::supports_evex(), "");
6188 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6189 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6190 emit_int8(0x79);
6191 emit_int8((unsigned char)(0xC0 | encode));
6192 }
6193
6194 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6195 assert(VM_Version::supports_evex(), "");
6196 assert(dst != xnoreg, "sanity");
6197 InstructionMark im(this);
6198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6199 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6200 // swap src<->dst for encoding
6201 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6202 emit_int8(0x79);
6203 emit_operand(dst, src);
6204 }
6205
6206 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6207 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6208 assert(VM_Version::supports_evex(), "");
6209 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6211 emit_int8(0x58);
6212 emit_int8((unsigned char)(0xC0 | encode));
6213 }
6214
6215 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6216 assert(VM_Version::supports_evex(), "");
6217 assert(dst != xnoreg, "sanity");
6218 InstructionMark im(this);
6219 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6220 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6221 // swap src<->dst for encoding
6222 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6223 emit_int8(0x58);
6224 emit_operand(dst, src);
6225 }
6226
6227 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6228 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6229 assert(VM_Version::supports_evex(), "");
6230 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6231 attributes.set_rex_vex_w_reverted();
6232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6233 emit_int8(0x59);
6234 emit_int8((unsigned char)(0xC0 | encode));
6235 }
6236
6237 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6238 assert(VM_Version::supports_evex(), "");
6239 assert(dst != xnoreg, "sanity");
6240 InstructionMark im(this);
6241 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6242 attributes.set_rex_vex_w_reverted();
6243 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6244 // swap src<->dst for encoding
6245 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6246 emit_int8(0x59);
6247 emit_operand(dst, src);
6248 }
6249
6250
6251 // scalar single/double precision replicate
6252
6253 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6254 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6255 assert(VM_Version::supports_evex(), "");
6256 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6257 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6258 emit_int8(0x18);
6259 emit_int8((unsigned char)(0xC0 | encode));
6260 }
6261
6262 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6263 assert(VM_Version::supports_evex(), "");
6264 assert(dst != xnoreg, "sanity");
6265 InstructionMark im(this);
6266 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6268 // swap src<->dst for encoding
6269 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6270 emit_int8(0x18);
6271 emit_operand(dst, src);
6272 }
6273
6274 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6275 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6276 assert(VM_Version::supports_evex(), "");
6277 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6278 attributes.set_rex_vex_w_reverted();
6279 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6280 emit_int8(0x19);
6281 emit_int8((unsigned char)(0xC0 | encode));
6282 }
6283
6284 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6285 assert(VM_Version::supports_evex(), "");
6286 assert(dst != xnoreg, "sanity");
6287 InstructionMark im(this);
6288 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6289 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6290 attributes.set_rex_vex_w_reverted();
6291 // swap src<->dst for encoding
6292 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6293 emit_int8(0x19);
6294 emit_operand(dst, src);
6295 }
6296
6297
6298 // gpr source broadcast forms
6299
6300 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6301 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6302 assert(VM_Version::supports_evex(), "");
6303 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6304 attributes.set_is_evex_instruction();
6305 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6306 emit_int8(0x7A);
6307 emit_int8((unsigned char)(0xC0 | encode));
6308 }
6309
6310 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6311 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6312 assert(VM_Version::supports_evex(), "");
6313 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6314 attributes.set_is_evex_instruction();
6315 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6316 emit_int8(0x7B);
6317 emit_int8((unsigned char)(0xC0 | encode));
6318 }
6319
6320 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6321 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6322 assert(VM_Version::supports_evex(), "");
6323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6324 attributes.set_is_evex_instruction();
6325 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6326 emit_int8(0x7C);
6327 emit_int8((unsigned char)(0xC0 | encode));
6328 }
6329
6330 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6331 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6332 assert(VM_Version::supports_evex(), "");
6333 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6334 attributes.set_is_evex_instruction();
6335 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6336 emit_int8(0x7C);
6337 emit_int8((unsigned char)(0xC0 | encode));
6338 }
6339
6340
6341 // Carry-Less Multiplication Quadword
6342 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6343 assert(VM_Version::supports_clmul(), "");
6344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6345 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6346 emit_int8(0x44);
6347 emit_int8((unsigned char)(0xC0 | encode));
6348 emit_int8((unsigned char)mask);
6349 }
6350
6351 // Carry-Less Multiplication Quadword
6352 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6353 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6354 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6355 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6356 emit_int8(0x44);
6357 emit_int8((unsigned char)(0xC0 | encode));
6358 emit_int8((unsigned char)mask);
6359 }
6360
6361 void Assembler::vzeroupper() {
6362 assert(VM_Version::supports_avx(), "");
6363 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6364 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6365 emit_int8(0x77);
6366 }
6367
6368
6369 #ifndef _LP64
6370 // 32bit only pieces of the assembler
6371
6372 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6373 // NO PREFIX AS NEVER 64BIT
6374 InstructionMark im(this);
6375 emit_int8((unsigned char)0x81);
6376 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6377 emit_data(imm32, rspec, 0);
6378 }
6379
6380 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6381 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6382 InstructionMark im(this);
6383 emit_int8((unsigned char)0x81);
6384 emit_operand(rdi, src1);
6385 emit_data(imm32, rspec, 0);
6386 }
6387
6388 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6389 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6390 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6391 void Assembler::cmpxchg8(Address adr) {
6392 InstructionMark im(this);
6393 emit_int8(0x0F);
6394 emit_int8((unsigned char)0xC7);
6395 emit_operand(rcx, adr);
6396 }
6397
6398 void Assembler::decl(Register dst) {
6399 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6400 emit_int8(0x48 | dst->encoding());
6401 }
6402
6403 #endif // _LP64
6404
6405 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6406
6407 void Assembler::fabs() {
6408 emit_int8((unsigned char)0xD9);
6409 emit_int8((unsigned char)0xE1);
6410 }
6411
6412 void Assembler::fadd(int i) {
6413 emit_farith(0xD8, 0xC0, i);
6414 }
6415
6416 void Assembler::fadd_d(Address src) {
6417 InstructionMark im(this);
6418 emit_int8((unsigned char)0xDC);
6419 emit_operand32(rax, src);
6420 }
6421
6422 void Assembler::fadd_s(Address src) {
6423 InstructionMark im(this);
6424 emit_int8((unsigned char)0xD8);
6425 emit_operand32(rax, src);
6426 }
6427
6428 void Assembler::fadda(int i) {
6429 emit_farith(0xDC, 0xC0, i);
6430 }
6431
6432 void Assembler::faddp(int i) {
6433 emit_farith(0xDE, 0xC0, i);
6434 }
6435
6436 void Assembler::fchs() {
6437 emit_int8((unsigned char)0xD9);
6438 emit_int8((unsigned char)0xE0);
6439 }
6440
6441 void Assembler::fcom(int i) {
6442 emit_farith(0xD8, 0xD0, i);
6443 }
6444
6445 void Assembler::fcomp(int i) {
6446 emit_farith(0xD8, 0xD8, i);
6447 }
6448
6449 void Assembler::fcomp_d(Address src) {
6450 InstructionMark im(this);
6451 emit_int8((unsigned char)0xDC);
6452 emit_operand32(rbx, src);
6453 }
6454
6455 void Assembler::fcomp_s(Address src) {
6456 InstructionMark im(this);
6457 emit_int8((unsigned char)0xD8);
6458 emit_operand32(rbx, src);
6459 }
6460
6461 void Assembler::fcompp() {
6462 emit_int8((unsigned char)0xDE);
6463 emit_int8((unsigned char)0xD9);
6464 }
6465
6466 void Assembler::fcos() {
6467 emit_int8((unsigned char)0xD9);
6468 emit_int8((unsigned char)0xFF);
6469 }
6470
6471 void Assembler::fdecstp() {
6472 emit_int8((unsigned char)0xD9);
6473 emit_int8((unsigned char)0xF6);
6474 }
6475
6476 void Assembler::fdiv(int i) {
6477 emit_farith(0xD8, 0xF0, i);
6478 }
6479
6480 void Assembler::fdiv_d(Address src) {
6481 InstructionMark im(this);
6482 emit_int8((unsigned char)0xDC);
6483 emit_operand32(rsi, src);
6484 }
6485
6486 void Assembler::fdiv_s(Address src) {
6487 InstructionMark im(this);
6488 emit_int8((unsigned char)0xD8);
6489 emit_operand32(rsi, src);
6490 }
6491
6492 void Assembler::fdiva(int i) {
6493 emit_farith(0xDC, 0xF8, i);
6494 }
6495
6496 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6497 // is erroneous for some of the floating-point instructions below.
6498
6499 void Assembler::fdivp(int i) {
6500 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6501 }
6502
6503 void Assembler::fdivr(int i) {
6504 emit_farith(0xD8, 0xF8, i);
6505 }
6506
6507 void Assembler::fdivr_d(Address src) {
6508 InstructionMark im(this);
6509 emit_int8((unsigned char)0xDC);
6510 emit_operand32(rdi, src);
6511 }
6512
6513 void Assembler::fdivr_s(Address src) {
6514 InstructionMark im(this);
6515 emit_int8((unsigned char)0xD8);
6516 emit_operand32(rdi, src);
6517 }
6518
6519 void Assembler::fdivra(int i) {
6520 emit_farith(0xDC, 0xF0, i);
6521 }
6522
6523 void Assembler::fdivrp(int i) {
6524 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6525 }
6526
6527 void Assembler::ffree(int i) {
6528 emit_farith(0xDD, 0xC0, i);
6529 }
6530
6531 void Assembler::fild_d(Address adr) {
6532 InstructionMark im(this);
6533 emit_int8((unsigned char)0xDF);
6534 emit_operand32(rbp, adr);
6535 }
6536
6537 void Assembler::fild_s(Address adr) {
6538 InstructionMark im(this);
6539 emit_int8((unsigned char)0xDB);
6540 emit_operand32(rax, adr);
6541 }
6542
6543 void Assembler::fincstp() {
6544 emit_int8((unsigned char)0xD9);
6545 emit_int8((unsigned char)0xF7);
6546 }
6547
6548 void Assembler::finit() {
6549 emit_int8((unsigned char)0x9B);
6550 emit_int8((unsigned char)0xDB);
6551 emit_int8((unsigned char)0xE3);
6552 }
6553
6554 void Assembler::fist_s(Address adr) {
6555 InstructionMark im(this);
6556 emit_int8((unsigned char)0xDB);
6557 emit_operand32(rdx, adr);
6558 }
6559
6560 void Assembler::fistp_d(Address adr) {
6561 InstructionMark im(this);
6562 emit_int8((unsigned char)0xDF);
6563 emit_operand32(rdi, adr);
6564 }
6565
6566 void Assembler::fistp_s(Address adr) {
6567 InstructionMark im(this);
6568 emit_int8((unsigned char)0xDB);
6569 emit_operand32(rbx, adr);
6570 }
6571
6572 void Assembler::fld1() {
6573 emit_int8((unsigned char)0xD9);
6574 emit_int8((unsigned char)0xE8);
6575 }
6576
6577 void Assembler::fld_d(Address adr) {
6578 InstructionMark im(this);
6579 emit_int8((unsigned char)0xDD);
6580 emit_operand32(rax, adr);
6581 }
6582
6583 void Assembler::fld_s(Address adr) {
6584 InstructionMark im(this);
6585 emit_int8((unsigned char)0xD9);
6586 emit_operand32(rax, adr);
6587 }
6588
6589
6590 void Assembler::fld_s(int index) {
6591 emit_farith(0xD9, 0xC0, index);
6592 }
6593
6594 void Assembler::fld_x(Address adr) {
6595 InstructionMark im(this);
6596 emit_int8((unsigned char)0xDB);
6597 emit_operand32(rbp, adr);
6598 }
6599
6600 void Assembler::fldcw(Address src) {
6601 InstructionMark im(this);
6602 emit_int8((unsigned char)0xD9);
6603 emit_operand32(rbp, src);
6604 }
6605
6606 void Assembler::fldenv(Address src) {
6607 InstructionMark im(this);
6608 emit_int8((unsigned char)0xD9);
6609 emit_operand32(rsp, src);
6610 }
6611
6612 void Assembler::fldlg2() {
6613 emit_int8((unsigned char)0xD9);
6614 emit_int8((unsigned char)0xEC);
6615 }
6616
6617 void Assembler::fldln2() {
6618 emit_int8((unsigned char)0xD9);
6619 emit_int8((unsigned char)0xED);
6620 }
6621
6622 void Assembler::fldz() {
6623 emit_int8((unsigned char)0xD9);
6624 emit_int8((unsigned char)0xEE);
6625 }
6626
6627 void Assembler::flog() {
6628 fldln2();
6629 fxch();
6630 fyl2x();
6631 }
6632
6633 void Assembler::flog10() {
6634 fldlg2();
6635 fxch();
6636 fyl2x();
6637 }
6638
6639 void Assembler::fmul(int i) {
6640 emit_farith(0xD8, 0xC8, i);
6641 }
6642
6643 void Assembler::fmul_d(Address src) {
6644 InstructionMark im(this);
6645 emit_int8((unsigned char)0xDC);
6646 emit_operand32(rcx, src);
6647 }
6648
6649 void Assembler::fmul_s(Address src) {
6650 InstructionMark im(this);
6651 emit_int8((unsigned char)0xD8);
6652 emit_operand32(rcx, src);
6653 }
6654
6655 void Assembler::fmula(int i) {
6656 emit_farith(0xDC, 0xC8, i);
6657 }
6658
6659 void Assembler::fmulp(int i) {
6660 emit_farith(0xDE, 0xC8, i);
6661 }
6662
6663 void Assembler::fnsave(Address dst) {
6664 InstructionMark im(this);
6665 emit_int8((unsigned char)0xDD);
6666 emit_operand32(rsi, dst);
6667 }
6668
6669 void Assembler::fnstcw(Address src) {
6670 InstructionMark im(this);
6671 emit_int8((unsigned char)0x9B);
6672 emit_int8((unsigned char)0xD9);
6673 emit_operand32(rdi, src);
6674 }
6675
6676 void Assembler::fnstsw_ax() {
6677 emit_int8((unsigned char)0xDF);
6678 emit_int8((unsigned char)0xE0);
6679 }
6680
6681 void Assembler::fprem() {
6682 emit_int8((unsigned char)0xD9);
6683 emit_int8((unsigned char)0xF8);
6684 }
6685
6686 void Assembler::fprem1() {
6687 emit_int8((unsigned char)0xD9);
6688 emit_int8((unsigned char)0xF5);
6689 }
6690
6691 void Assembler::frstor(Address src) {
6692 InstructionMark im(this);
6693 emit_int8((unsigned char)0xDD);
6694 emit_operand32(rsp, src);
6695 }
6696
6697 void Assembler::fsin() {
6698 emit_int8((unsigned char)0xD9);
6699 emit_int8((unsigned char)0xFE);
6700 }
6701
6702 void Assembler::fsqrt() {
6703 emit_int8((unsigned char)0xD9);
6704 emit_int8((unsigned char)0xFA);
6705 }
6706
6707 void Assembler::fst_d(Address adr) {
6708 InstructionMark im(this);
6709 emit_int8((unsigned char)0xDD);
6710 emit_operand32(rdx, adr);
6711 }
6712
6713 void Assembler::fst_s(Address adr) {
6714 InstructionMark im(this);
6715 emit_int8((unsigned char)0xD9);
6716 emit_operand32(rdx, adr);
6717 }
6718
6719 void Assembler::fstp_d(Address adr) {
6720 InstructionMark im(this);
6721 emit_int8((unsigned char)0xDD);
6722 emit_operand32(rbx, adr);
6723 }
6724
6725 void Assembler::fstp_d(int index) {
6726 emit_farith(0xDD, 0xD8, index);
6727 }
6728
6729 void Assembler::fstp_s(Address adr) {
6730 InstructionMark im(this);
6731 emit_int8((unsigned char)0xD9);
6732 emit_operand32(rbx, adr);
6733 }
6734
6735 void Assembler::fstp_x(Address adr) {
6736 InstructionMark im(this);
6737 emit_int8((unsigned char)0xDB);
6738 emit_operand32(rdi, adr);
6739 }
6740
6741 void Assembler::fsub(int i) {
6742 emit_farith(0xD8, 0xE0, i);
6743 }
6744
6745 void Assembler::fsub_d(Address src) {
6746 InstructionMark im(this);
6747 emit_int8((unsigned char)0xDC);
6748 emit_operand32(rsp, src);
6749 }
6750
6751 void Assembler::fsub_s(Address src) {
6752 InstructionMark im(this);
6753 emit_int8((unsigned char)0xD8);
6754 emit_operand32(rsp, src);
6755 }
6756
6757 void Assembler::fsuba(int i) {
6758 emit_farith(0xDC, 0xE8, i);
6759 }
6760
6761 void Assembler::fsubp(int i) {
6762 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6763 }
6764
6765 void Assembler::fsubr(int i) {
6766 emit_farith(0xD8, 0xE8, i);
6767 }
6768
6769 void Assembler::fsubr_d(Address src) {
6770 InstructionMark im(this);
6771 emit_int8((unsigned char)0xDC);
6772 emit_operand32(rbp, src);
6773 }
6774
6775 void Assembler::fsubr_s(Address src) {
6776 InstructionMark im(this);
6777 emit_int8((unsigned char)0xD8);
6778 emit_operand32(rbp, src);
6779 }
6780
6781 void Assembler::fsubra(int i) {
6782 emit_farith(0xDC, 0xE0, i);
6783 }
6784
6785 void Assembler::fsubrp(int i) {
6786 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6787 }
6788
6789 void Assembler::ftan() {
6790 emit_int8((unsigned char)0xD9);
6791 emit_int8((unsigned char)0xF2);
6792 emit_int8((unsigned char)0xDD);
6793 emit_int8((unsigned char)0xD8);
6794 }
6795
6796 void Assembler::ftst() {
6797 emit_int8((unsigned char)0xD9);
6798 emit_int8((unsigned char)0xE4);
6799 }
6800
6801 void Assembler::fucomi(int i) {
6802 // make sure the instruction is supported (introduced for P6, together with cmov)
6803 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6804 emit_farith(0xDB, 0xE8, i);
6805 }
6806
6807 void Assembler::fucomip(int i) {
6808 // make sure the instruction is supported (introduced for P6, together with cmov)
6809 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6810 emit_farith(0xDF, 0xE8, i);
6811 }
6812
6813 void Assembler::fwait() {
6814 emit_int8((unsigned char)0x9B);
6815 }
6816
6817 void Assembler::fxch(int i) {
6818 emit_farith(0xD9, 0xC8, i);
6819 }
6820
6821 void Assembler::fyl2x() {
6822 emit_int8((unsigned char)0xD9);
6823 emit_int8((unsigned char)0xF1);
6824 }
6825
6826 void Assembler::frndint() {
6827 emit_int8((unsigned char)0xD9);
6828 emit_int8((unsigned char)0xFC);
6829 }
6830
6831 void Assembler::f2xm1() {
6832 emit_int8((unsigned char)0xD9);
6833 emit_int8((unsigned char)0xF0);
6834 }
6835
6836 void Assembler::fldl2e() {
6837 emit_int8((unsigned char)0xD9);
6838 emit_int8((unsigned char)0xEA);
6839 }
6840
6841 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6842 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6843 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6844 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6845
6846 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6847 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6848 if (pre > 0) {
6849 emit_int8(simd_pre[pre]);
6850 }
6851 if (rex_w) {
6852 prefixq(adr, xreg);
6853 } else {
6854 prefix(adr, xreg);
6855 }
6856 if (opc > 0) {
6857 emit_int8(0x0F);
6858 int opc2 = simd_opc[opc];
6859 if (opc2 > 0) {
6860 emit_int8(opc2);
6861 }
6862 }
6863 }
6864
6865 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6866 if (pre > 0) {
6867 emit_int8(simd_pre[pre]);
6868 }
6869 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6870 if (opc > 0) {
6871 emit_int8(0x0F);
6872 int opc2 = simd_opc[opc];
6873 if (opc2 > 0) {
6874 emit_int8(opc2);
6875 }
6876 }
6877 return encode;
6878 }
6879
6880
6881 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6882 int vector_len = _attributes->get_vector_len();
6883 bool vex_w = _attributes->is_rex_vex_w();
6884 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6885 prefix(VEX_3bytes);
6886
6887 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6888 byte1 = (~byte1) & 0xE0;
6889 byte1 |= opc;
6890 emit_int8(byte1);
6891
6892 int byte2 = ((~nds_enc) & 0xf) << 3;
6893 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6894 emit_int8(byte2);
6895 } else {
6896 prefix(VEX_2bytes);
6897
6898 int byte1 = vex_r ? VEX_R : 0;
6899 byte1 = (~byte1) & 0x80;
6900 byte1 |= ((~nds_enc) & 0xf) << 3;
6901 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6902 emit_int8(byte1);
6903 }
6904 }
6905
6906 // This is a 4 byte encoding
6907 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6908 // EVEX 0x62 prefix
6909 prefix(EVEX_4bytes);
6910 bool vex_w = _attributes->is_rex_vex_w();
6911 int evex_encoding = (vex_w ? VEX_W : 0);
6912 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6913 _attributes->set_evex_encoding(evex_encoding);
6914
6915 // P0: byte 2, initialized to RXBR`00mm
6916 // instead of not'd
6917 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6918 byte2 = (~byte2) & 0xF0;
6919 // confine opc opcode extensions in mm bits to lower two bits
6920 // of form {0F, 0F_38, 0F_3A}
6921 byte2 |= opc;
6922 emit_int8(byte2);
6923
6924 // P1: byte 3 as Wvvvv1pp
6925 int byte3 = ((~nds_enc) & 0xf) << 3;
6926 // p[10] is always 1
6927 byte3 |= EVEX_F;
6928 byte3 |= (vex_w & 1) << 7;
6929 // confine pre opcode extensions in pp bits to lower two bits
6930 // of form {66, F3, F2}
6931 byte3 |= pre;
6932 emit_int8(byte3);
6933
6934 // P2: byte 4 as zL'Lbv'aaa
6935 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6936 // EVEX.v` for extending EVEX.vvvv or VIDX
6937 byte4 |= (evex_v ? 0: EVEX_V);
6938 // third EXEC.b for broadcast actions
6939 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6940 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6941 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6942 // last is EVEX.z for zero/merge actions
6943 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6944 emit_int8(byte4);
6945 }
6946
6947 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6948 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6949 bool vex_b = adr.base_needs_rex();
6950 bool vex_x = adr.index_needs_rex();
6951 set_attributes(attributes);
6952 attributes->set_current_assembler(this);
6953
6954 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6955 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6956 switch (attributes->get_vector_len()) {
6957 case AVX_128bit:
6958 case AVX_256bit:
6959 attributes->set_is_legacy_mode();
6960 break;
6961 }
6962 }
6963
6964 // For pure EVEX check and see if this instruction
6965 // is allowed in legacy mode and has resources which will
6966 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6967 // else that field is set when we encode to EVEX
6968 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6969 !_is_managed && !attributes->is_evex_instruction()) {
6970 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6971 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6972 if (check_register_bank) {
6973 // check nds_enc and xreg_enc for upper bank usage
6974 if (nds_enc < 16 && xreg_enc < 16) {
6975 attributes->set_is_legacy_mode();
6976 }
6977 } else {
6978 attributes->set_is_legacy_mode();
6979 }
6980 }
6981 }
6982
6983 _is_managed = false;
6984 if (UseAVX > 2 && !attributes->is_legacy_mode())
6985 {
6986 bool evex_r = (xreg_enc >= 16);
6987 bool evex_v = (nds_enc >= 16);
6988 attributes->set_is_evex_instruction();
6989 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6990 } else {
6991 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
6992 attributes->set_rex_vex_w(false);
6993 }
6994 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6995 }
6996 }
6997
6998 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6999 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7000 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7001 bool vex_x = false;
7002 set_attributes(attributes);
7003 attributes->set_current_assembler(this);
7004 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7005
7006 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7007 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7008 switch (attributes->get_vector_len()) {
7009 case AVX_128bit:
7010 case AVX_256bit:
7011 if (check_register_bank) {
7012 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7013 // up propagate arithmetic instructions to meet RA requirements
7014 attributes->set_vector_len(AVX_512bit);
7015 } else {
7016 attributes->set_is_legacy_mode();
7017 }
7018 } else {
7019 attributes->set_is_legacy_mode();
7020 }
7021 break;
7022 }
7023 }
7024
7025 // For pure EVEX check and see if this instruction
7026 // is allowed in legacy mode and has resources which will
7027 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7028 // else that field is set when we encode to EVEX
7029 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7030 !_is_managed && !attributes->is_evex_instruction()) {
7031 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7032 if (check_register_bank) {
7033 // check dst_enc, nds_enc and src_enc for upper bank usage
7034 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7035 attributes->set_is_legacy_mode();
7036 }
7037 } else {
7038 attributes->set_is_legacy_mode();
7039 }
7040 }
7041 }
7042
7043 _is_managed = false;
7044 if (UseAVX > 2 && !attributes->is_legacy_mode())
7045 {
7046 bool evex_r = (dst_enc >= 16);
7047 bool evex_v = (nds_enc >= 16);
7048 // can use vex_x as bank extender on rm encoding
7049 vex_x = (src_enc >= 16);
7050 attributes->set_is_evex_instruction();
7051 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7052 } else {
7053 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7054 attributes->set_rex_vex_w(false);
7055 }
7056 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7057 }
7058
7059 // return modrm byte components for operands
7060 return (((dst_enc & 7) << 3) | (src_enc & 7));
7061 }
7062
7063
7064 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7065 VexOpcode opc, InstructionAttr *attributes) {
7066 if (UseAVX > 0) {
7067 int xreg_enc = xreg->encoding();
7068 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7069 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7070 } else {
7071 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7072 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7073 }
7074 }
7075
7076 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7077 VexOpcode opc, InstructionAttr *attributes) {
7078 int dst_enc = dst->encoding();
7079 int src_enc = src->encoding();
7080 if (UseAVX > 0) {
7081 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7082 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7083 } else {
7084 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7085 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7086 }
7087 }
7088
7089 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7090 assert(VM_Version::supports_avx(), "");
7091 assert(!VM_Version::supports_evex(), "");
7092 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7093 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7094 emit_int8((unsigned char)0xC2);
7095 emit_int8((unsigned char)(0xC0 | encode));
7096 emit_int8((unsigned char)(0xF & cop));
7097 }
7098
7099 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7100 assert(VM_Version::supports_avx(), "");
7101 assert(!VM_Version::supports_evex(), "");
7102 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7103 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7104 emit_int8((unsigned char)0x4B);
7105 emit_int8((unsigned char)(0xC0 | encode));
7106 int src2_enc = src2->encoding();
7107 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7108 }
7109
7110 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7111 assert(VM_Version::supports_bmi2(), "");
7112 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7113 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7114 emit_int8((unsigned char)0xF7);
7115 emit_int8((unsigned char)(0xC0 | encode));
7116 }
7117
7118 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7119 assert(VM_Version::supports_bmi2(), "");
7120 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7121 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7122 emit_int8((unsigned char)0xF7);
7123 emit_int8((unsigned char)(0xC0 | encode));
7124 }
7125
7126 #ifndef _LP64
7127
7128 void Assembler::incl(Register dst) {
7129 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7130 emit_int8(0x40 | dst->encoding());
7131 }
7132
7133 void Assembler::lea(Register dst, Address src) {
7134 leal(dst, src);
7135 }
7136
7137 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7138 InstructionMark im(this);
7139 emit_int8((unsigned char)0xC7);
7140 emit_operand(rax, dst);
7141 emit_data((int)imm32, rspec, 0);
7142 }
7143
7144 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7145 InstructionMark im(this);
7146 int encode = prefix_and_encode(dst->encoding());
7147 emit_int8((unsigned char)(0xB8 | encode));
7148 emit_data((int)imm32, rspec, 0);
7149 }
7150
7151 void Assembler::popa() { // 32bit
7152 emit_int8(0x61);
7153 }
7154
7155 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7156 InstructionMark im(this);
7157 emit_int8(0x68);
7158 emit_data(imm32, rspec, 0);
7159 }
7160
7161 void Assembler::pusha() { // 32bit
7162 emit_int8(0x60);
7163 }
7164
7165 void Assembler::set_byte_if_not_zero(Register dst) {
7166 emit_int8(0x0F);
7167 emit_int8((unsigned char)0x95);
7168 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7169 }
7170
7171 void Assembler::shldl(Register dst, Register src) {
7172 emit_int8(0x0F);
7173 emit_int8((unsigned char)0xA5);
7174 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7175 }
7176
7177 // 0F A4 / r ib
7178 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7179 emit_int8(0x0F);
7180 emit_int8((unsigned char)0xA4);
7181 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7182 emit_int8(imm8);
7183 }
7184
7185 void Assembler::shrdl(Register dst, Register src) {
7186 emit_int8(0x0F);
7187 emit_int8((unsigned char)0xAD);
7188 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7189 }
7190
7191 #else // LP64
7192
7193 void Assembler::set_byte_if_not_zero(Register dst) {
7194 int enc = prefix_and_encode(dst->encoding(), true);
7195 emit_int8(0x0F);
7196 emit_int8((unsigned char)0x95);
7197 emit_int8((unsigned char)(0xE0 | enc));
7198 }
7199
7200 // 64bit only pieces of the assembler
7201 // This should only be used by 64bit instructions that can use rip-relative
7202 // it cannot be used by instructions that want an immediate value.
7203
7204 bool Assembler::reachable(AddressLiteral adr) {
7205 int64_t disp;
7206 // None will force a 64bit literal to the code stream. Likely a placeholder
7207 // for something that will be patched later and we need to certain it will
7208 // always be reachable.
7209 if (adr.reloc() == relocInfo::none) {
7210 return false;
7211 }
7212 if (adr.reloc() == relocInfo::internal_word_type) {
7213 // This should be rip relative and easily reachable.
7214 return true;
7215 }
7216 if (adr.reloc() == relocInfo::virtual_call_type ||
7217 adr.reloc() == relocInfo::opt_virtual_call_type ||
7218 adr.reloc() == relocInfo::static_call_type ||
7219 adr.reloc() == relocInfo::static_stub_type ) {
7220 // This should be rip relative within the code cache and easily
7221 // reachable until we get huge code caches. (At which point
7222 // ic code is going to have issues).
7223 return true;
7224 }
7225 if (adr.reloc() != relocInfo::external_word_type &&
7226 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7227 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7228 adr.reloc() != relocInfo::runtime_call_type ) {
7229 return false;
7230 }
7231
7232 // Stress the correction code
7233 if (ForceUnreachable) {
7234 // Must be runtimecall reloc, see if it is in the codecache
7235 // Flipping stuff in the codecache to be unreachable causes issues
7236 // with things like inline caches where the additional instructions
7237 // are not handled.
7238 if (CodeCache::find_blob(adr._target) == NULL) {
7239 return false;
7240 }
7241 }
7242 // For external_word_type/runtime_call_type if it is reachable from where we
7243 // are now (possibly a temp buffer) and where we might end up
7244 // anywhere in the codeCache then we are always reachable.
7245 // This would have to change if we ever save/restore shared code
7246 // to be more pessimistic.
7247 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7248 if (!is_simm32(disp)) return false;
7249 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7250 if (!is_simm32(disp)) return false;
7251
7252 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7253
7254 // Because rip relative is a disp + address_of_next_instruction and we
7255 // don't know the value of address_of_next_instruction we apply a fudge factor
7256 // to make sure we will be ok no matter the size of the instruction we get placed into.
7257 // We don't have to fudge the checks above here because they are already worst case.
7258
7259 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7260 // + 4 because better safe than sorry.
7261 const int fudge = 12 + 4;
7262 if (disp < 0) {
7263 disp -= fudge;
7264 } else {
7265 disp += fudge;
7266 }
7267 return is_simm32(disp);
7268 }
7269
7270 // Check if the polling page is not reachable from the code cache using rip-relative
7271 // addressing.
7272 bool Assembler::is_polling_page_far() {
7273 intptr_t addr = (intptr_t)os::get_polling_page();
7274 return ForceUnreachable ||
7275 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7276 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7277 }
7278
7279 void Assembler::emit_data64(jlong data,
7280 relocInfo::relocType rtype,
7281 int format) {
7282 if (rtype == relocInfo::none) {
7283 emit_int64(data);
7284 } else {
7285 emit_data64(data, Relocation::spec_simple(rtype), format);
7286 }
7287 }
7288
7289 void Assembler::emit_data64(jlong data,
7290 RelocationHolder const& rspec,
7291 int format) {
7292 assert(imm_operand == 0, "default format must be immediate in this file");
7293 assert(imm_operand == format, "must be immediate");
7294 assert(inst_mark() != NULL, "must be inside InstructionMark");
7295 // Do not use AbstractAssembler::relocate, which is not intended for
7296 // embedded words. Instead, relocate to the enclosing instruction.
7297 code_section()->relocate(inst_mark(), rspec, format);
7298 #ifdef ASSERT
7299 check_relocation(rspec, format);
7300 #endif
7301 emit_int64(data);
7302 }
7303
7304 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7305 if (reg_enc >= 8) {
7306 prefix(REX_B);
7307 reg_enc -= 8;
7308 } else if (byteinst && reg_enc >= 4) {
7309 prefix(REX);
7310 }
7311 return reg_enc;
7312 }
7313
7314 int Assembler::prefixq_and_encode(int reg_enc) {
7315 if (reg_enc < 8) {
7316 prefix(REX_W);
7317 } else {
7318 prefix(REX_WB);
7319 reg_enc -= 8;
7320 }
7321 return reg_enc;
7322 }
7323
7324 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7325 if (dst_enc < 8) {
7326 if (src_enc >= 8) {
7327 prefix(REX_B);
7328 src_enc -= 8;
7329 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7330 prefix(REX);
7331 }
7332 } else {
7333 if (src_enc < 8) {
7334 prefix(REX_R);
7335 } else {
7336 prefix(REX_RB);
7337 src_enc -= 8;
7338 }
7339 dst_enc -= 8;
7340 }
7341 return dst_enc << 3 | src_enc;
7342 }
7343
7344 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7345 if (dst_enc < 8) {
7346 if (src_enc < 8) {
7347 prefix(REX_W);
7348 } else {
7349 prefix(REX_WB);
7350 src_enc -= 8;
7351 }
7352 } else {
7353 if (src_enc < 8) {
7354 prefix(REX_WR);
7355 } else {
7356 prefix(REX_WRB);
7357 src_enc -= 8;
7358 }
7359 dst_enc -= 8;
7360 }
7361 return dst_enc << 3 | src_enc;
7362 }
7363
7364 void Assembler::prefix(Register reg) {
7365 if (reg->encoding() >= 8) {
7366 prefix(REX_B);
7367 }
7368 }
7369
7370 void Assembler::prefix(Register dst, Register src, Prefix p) {
7371 if (src->encoding() >= 8) {
7372 p = (Prefix)(p | REX_B);
7373 }
7374 if (dst->encoding() >= 8) {
7375 p = (Prefix)( p | REX_R);
7376 }
7377 if (p != Prefix_EMPTY) {
7378 // do not generate an empty prefix
7379 prefix(p);
7380 }
7381 }
7382
7383 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7384 if (adr.base_needs_rex()) {
7385 if (adr.index_needs_rex()) {
7386 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7387 } else {
7388 prefix(REX_B);
7389 }
7390 } else {
7391 if (adr.index_needs_rex()) {
7392 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7393 }
7394 }
7395 if (dst->encoding() >= 8) {
7396 p = (Prefix)(p | REX_R);
7397 }
7398 if (p != Prefix_EMPTY) {
7399 // do not generate an empty prefix
7400 prefix(p);
7401 }
7402 }
7403
7404 void Assembler::prefix(Address adr) {
7405 if (adr.base_needs_rex()) {
7406 if (adr.index_needs_rex()) {
7407 prefix(REX_XB);
7408 } else {
7409 prefix(REX_B);
7410 }
7411 } else {
7412 if (adr.index_needs_rex()) {
7413 prefix(REX_X);
7414 }
7415 }
7416 }
7417
7418 void Assembler::prefixq(Address adr) {
7419 if (adr.base_needs_rex()) {
7420 if (adr.index_needs_rex()) {
7421 prefix(REX_WXB);
7422 } else {
7423 prefix(REX_WB);
7424 }
7425 } else {
7426 if (adr.index_needs_rex()) {
7427 prefix(REX_WX);
7428 } else {
7429 prefix(REX_W);
7430 }
7431 }
7432 }
7433
7434
7435 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7436 if (reg->encoding() < 8) {
7437 if (adr.base_needs_rex()) {
7438 if (adr.index_needs_rex()) {
7439 prefix(REX_XB);
7440 } else {
7441 prefix(REX_B);
7442 }
7443 } else {
7444 if (adr.index_needs_rex()) {
7445 prefix(REX_X);
7446 } else if (byteinst && reg->encoding() >= 4 ) {
7447 prefix(REX);
7448 }
7449 }
7450 } else {
7451 if (adr.base_needs_rex()) {
7452 if (adr.index_needs_rex()) {
7453 prefix(REX_RXB);
7454 } else {
7455 prefix(REX_RB);
7456 }
7457 } else {
7458 if (adr.index_needs_rex()) {
7459 prefix(REX_RX);
7460 } else {
7461 prefix(REX_R);
7462 }
7463 }
7464 }
7465 }
7466
7467 void Assembler::prefixq(Address adr, Register src) {
7468 if (src->encoding() < 8) {
7469 if (adr.base_needs_rex()) {
7470 if (adr.index_needs_rex()) {
7471 prefix(REX_WXB);
7472 } else {
7473 prefix(REX_WB);
7474 }
7475 } else {
7476 if (adr.index_needs_rex()) {
7477 prefix(REX_WX);
7478 } else {
7479 prefix(REX_W);
7480 }
7481 }
7482 } else {
7483 if (adr.base_needs_rex()) {
7484 if (adr.index_needs_rex()) {
7485 prefix(REX_WRXB);
7486 } else {
7487 prefix(REX_WRB);
7488 }
7489 } else {
7490 if (adr.index_needs_rex()) {
7491 prefix(REX_WRX);
7492 } else {
7493 prefix(REX_WR);
7494 }
7495 }
7496 }
7497 }
7498
7499 void Assembler::prefix(Address adr, XMMRegister reg) {
7500 if (reg->encoding() < 8) {
7501 if (adr.base_needs_rex()) {
7502 if (adr.index_needs_rex()) {
7503 prefix(REX_XB);
7504 } else {
7505 prefix(REX_B);
7506 }
7507 } else {
7508 if (adr.index_needs_rex()) {
7509 prefix(REX_X);
7510 }
7511 }
7512 } else {
7513 if (adr.base_needs_rex()) {
7514 if (adr.index_needs_rex()) {
7515 prefix(REX_RXB);
7516 } else {
7517 prefix(REX_RB);
7518 }
7519 } else {
7520 if (adr.index_needs_rex()) {
7521 prefix(REX_RX);
7522 } else {
7523 prefix(REX_R);
7524 }
7525 }
7526 }
7527 }
7528
7529 void Assembler::prefixq(Address adr, XMMRegister src) {
7530 if (src->encoding() < 8) {
7531 if (adr.base_needs_rex()) {
7532 if (adr.index_needs_rex()) {
7533 prefix(REX_WXB);
7534 } else {
7535 prefix(REX_WB);
7536 }
7537 } else {
7538 if (adr.index_needs_rex()) {
7539 prefix(REX_WX);
7540 } else {
7541 prefix(REX_W);
7542 }
7543 }
7544 } else {
7545 if (adr.base_needs_rex()) {
7546 if (adr.index_needs_rex()) {
7547 prefix(REX_WRXB);
7548 } else {
7549 prefix(REX_WRB);
7550 }
7551 } else {
7552 if (adr.index_needs_rex()) {
7553 prefix(REX_WRX);
7554 } else {
7555 prefix(REX_WR);
7556 }
7557 }
7558 }
7559 }
7560
7561 void Assembler::adcq(Register dst, int32_t imm32) {
7562 (void) prefixq_and_encode(dst->encoding());
7563 emit_arith(0x81, 0xD0, dst, imm32);
7564 }
7565
7566 void Assembler::adcq(Register dst, Address src) {
7567 InstructionMark im(this);
7568 prefixq(src, dst);
7569 emit_int8(0x13);
7570 emit_operand(dst, src);
7571 }
7572
7573 void Assembler::adcq(Register dst, Register src) {
7574 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7575 emit_arith(0x13, 0xC0, dst, src);
7576 }
7577
7578 void Assembler::addq(Address dst, int32_t imm32) {
7579 InstructionMark im(this);
7580 prefixq(dst);
7581 emit_arith_operand(0x81, rax, dst,imm32);
7582 }
7583
7584 void Assembler::addq(Address dst, Register src) {
7585 InstructionMark im(this);
7586 prefixq(dst, src);
7587 emit_int8(0x01);
7588 emit_operand(src, dst);
7589 }
7590
7591 void Assembler::addq(Register dst, int32_t imm32) {
7592 (void) prefixq_and_encode(dst->encoding());
7593 emit_arith(0x81, 0xC0, dst, imm32);
7594 }
7595
7596 void Assembler::addq(Register dst, Address src) {
7597 InstructionMark im(this);
7598 prefixq(src, dst);
7599 emit_int8(0x03);
7600 emit_operand(dst, src);
7601 }
7602
7603 void Assembler::addq(Register dst, Register src) {
7604 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7605 emit_arith(0x03, 0xC0, dst, src);
7606 }
7607
7608 void Assembler::adcxq(Register dst, Register src) {
7609 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7610 emit_int8((unsigned char)0x66);
7611 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7612 emit_int8(0x0F);
7613 emit_int8(0x38);
7614 emit_int8((unsigned char)0xF6);
7615 emit_int8((unsigned char)(0xC0 | encode));
7616 }
7617
7618 void Assembler::adoxq(Register dst, Register src) {
7619 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7620 emit_int8((unsigned char)0xF3);
7621 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7622 emit_int8(0x0F);
7623 emit_int8(0x38);
7624 emit_int8((unsigned char)0xF6);
7625 emit_int8((unsigned char)(0xC0 | encode));
7626 }
7627
7628 void Assembler::andq(Address dst, int32_t imm32) {
7629 InstructionMark im(this);
7630 prefixq(dst);
7631 emit_int8((unsigned char)0x81);
7632 emit_operand(rsp, dst, 4);
7633 emit_int32(imm32);
7634 }
7635
7636 void Assembler::andq(Register dst, int32_t imm32) {
7637 (void) prefixq_and_encode(dst->encoding());
7638 emit_arith(0x81, 0xE0, dst, imm32);
7639 }
7640
7641 void Assembler::andq(Register dst, Address src) {
7642 InstructionMark im(this);
7643 prefixq(src, dst);
7644 emit_int8(0x23);
7645 emit_operand(dst, src);
7646 }
7647
7648 void Assembler::andq(Register dst, Register src) {
7649 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7650 emit_arith(0x23, 0xC0, dst, src);
7651 }
7652
7653 void Assembler::andnq(Register dst, Register src1, Register src2) {
7654 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7655 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7656 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7657 emit_int8((unsigned char)0xF2);
7658 emit_int8((unsigned char)(0xC0 | encode));
7659 }
7660
7661 void Assembler::andnq(Register dst, Register src1, Address src2) {
7662 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7663 InstructionMark im(this);
7664 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7665 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7666 emit_int8((unsigned char)0xF2);
7667 emit_operand(dst, src2);
7668 }
7669
7670 void Assembler::bsfq(Register dst, Register src) {
7671 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7672 emit_int8(0x0F);
7673 emit_int8((unsigned char)0xBC);
7674 emit_int8((unsigned char)(0xC0 | encode));
7675 }
7676
7677 void Assembler::bsrq(Register dst, Register src) {
7678 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7679 emit_int8(0x0F);
7680 emit_int8((unsigned char)0xBD);
7681 emit_int8((unsigned char)(0xC0 | encode));
7682 }
7683
7684 void Assembler::bswapq(Register reg) {
7685 int encode = prefixq_and_encode(reg->encoding());
7686 emit_int8(0x0F);
7687 emit_int8((unsigned char)(0xC8 | encode));
7688 }
7689
7690 void Assembler::blsiq(Register dst, Register src) {
7691 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7692 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7693 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7694 emit_int8((unsigned char)0xF3);
7695 emit_int8((unsigned char)(0xC0 | encode));
7696 }
7697
7698 void Assembler::blsiq(Register dst, Address src) {
7699 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7700 InstructionMark im(this);
7701 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7702 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7703 emit_int8((unsigned char)0xF3);
7704 emit_operand(rbx, src);
7705 }
7706
7707 void Assembler::blsmskq(Register dst, Register src) {
7708 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7709 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7710 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7711 emit_int8((unsigned char)0xF3);
7712 emit_int8((unsigned char)(0xC0 | encode));
7713 }
7714
7715 void Assembler::blsmskq(Register dst, Address src) {
7716 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7717 InstructionMark im(this);
7718 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7719 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7720 emit_int8((unsigned char)0xF3);
7721 emit_operand(rdx, src);
7722 }
7723
7724 void Assembler::blsrq(Register dst, Register src) {
7725 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7726 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7727 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7728 emit_int8((unsigned char)0xF3);
7729 emit_int8((unsigned char)(0xC0 | encode));
7730 }
7731
7732 void Assembler::blsrq(Register dst, Address src) {
7733 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7734 InstructionMark im(this);
7735 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7736 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7737 emit_int8((unsigned char)0xF3);
7738 emit_operand(rcx, src);
7739 }
7740
7741 void Assembler::cdqq() {
7742 prefix(REX_W);
7743 emit_int8((unsigned char)0x99);
7744 }
7745
7746 void Assembler::clflush(Address adr) {
7747 prefix(adr);
7748 emit_int8(0x0F);
7749 emit_int8((unsigned char)0xAE);
7750 emit_operand(rdi, adr);
7751 }
7752
7753 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7754 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7755 emit_int8(0x0F);
7756 emit_int8(0x40 | cc);
7757 emit_int8((unsigned char)(0xC0 | encode));
7758 }
7759
7760 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7761 InstructionMark im(this);
7762 prefixq(src, dst);
7763 emit_int8(0x0F);
7764 emit_int8(0x40 | cc);
7765 emit_operand(dst, src);
7766 }
7767
7768 void Assembler::cmpq(Address dst, int32_t imm32) {
7769 InstructionMark im(this);
7770 prefixq(dst);
7771 emit_int8((unsigned char)0x81);
7772 emit_operand(rdi, dst, 4);
7773 emit_int32(imm32);
7774 }
7775
7776 void Assembler::cmpq(Register dst, int32_t imm32) {
7777 (void) prefixq_and_encode(dst->encoding());
7778 emit_arith(0x81, 0xF8, dst, imm32);
7779 }
7780
7781 void Assembler::cmpq(Address dst, Register src) {
7782 InstructionMark im(this);
7783 prefixq(dst, src);
7784 emit_int8(0x3B);
7785 emit_operand(src, dst);
7786 }
7787
7788 void Assembler::cmpq(Register dst, Register src) {
7789 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7790 emit_arith(0x3B, 0xC0, dst, src);
7791 }
7792
7793 void Assembler::cmpq(Register dst, Address src) {
7794 InstructionMark im(this);
7795 prefixq(src, dst);
7796 emit_int8(0x3B);
7797 emit_operand(dst, src);
7798 }
7799
7800 void Assembler::cmpxchgq(Register reg, Address adr) {
7801 InstructionMark im(this);
7802 prefixq(adr, reg);
7803 emit_int8(0x0F);
7804 emit_int8((unsigned char)0xB1);
7805 emit_operand(reg, adr);
7806 }
7807
7808 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7809 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7810 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7811 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7812 emit_int8(0x2A);
7813 emit_int8((unsigned char)(0xC0 | encode));
7814 }
7815
7816 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7818 InstructionMark im(this);
7819 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7820 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7821 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7822 emit_int8(0x2A);
7823 emit_operand(dst, src);
7824 }
7825
7826 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7828 InstructionMark im(this);
7829 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7832 emit_int8(0x2A);
7833 emit_operand(dst, src);
7834 }
7835
7836 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7838 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7839 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7840 emit_int8(0x2C);
7841 emit_int8((unsigned char)(0xC0 | encode));
7842 }
7843
7844 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7846 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7847 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7848 emit_int8(0x2C);
7849 emit_int8((unsigned char)(0xC0 | encode));
7850 }
7851
7852 void Assembler::decl(Register dst) {
7853 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7854 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7855 int encode = prefix_and_encode(dst->encoding());
7856 emit_int8((unsigned char)0xFF);
7857 emit_int8((unsigned char)(0xC8 | encode));
7858 }
7859
7860 void Assembler::decq(Register dst) {
7861 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7862 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7863 int encode = prefixq_and_encode(dst->encoding());
7864 emit_int8((unsigned char)0xFF);
7865 emit_int8(0xC8 | encode);
7866 }
7867
7868 void Assembler::decq(Address dst) {
7869 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7870 InstructionMark im(this);
7871 prefixq(dst);
7872 emit_int8((unsigned char)0xFF);
7873 emit_operand(rcx, dst);
7874 }
7875
7876 void Assembler::fxrstor(Address src) {
7877 prefixq(src);
7878 emit_int8(0x0F);
7879 emit_int8((unsigned char)0xAE);
7880 emit_operand(as_Register(1), src);
7881 }
7882
7883 void Assembler::xrstor(Address src) {
7884 prefixq(src);
7885 emit_int8(0x0F);
7886 emit_int8((unsigned char)0xAE);
7887 emit_operand(as_Register(5), src);
7888 }
7889
7890 void Assembler::fxsave(Address dst) {
7891 prefixq(dst);
7892 emit_int8(0x0F);
7893 emit_int8((unsigned char)0xAE);
7894 emit_operand(as_Register(0), dst);
7895 }
7896
7897 void Assembler::xsave(Address dst) {
7898 prefixq(dst);
7899 emit_int8(0x0F);
7900 emit_int8((unsigned char)0xAE);
7901 emit_operand(as_Register(4), dst);
7902 }
7903
7904 void Assembler::idivq(Register src) {
7905 int encode = prefixq_and_encode(src->encoding());
7906 emit_int8((unsigned char)0xF7);
7907 emit_int8((unsigned char)(0xF8 | encode));
7908 }
7909
7910 void Assembler::imulq(Register dst, Register src) {
7911 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7912 emit_int8(0x0F);
7913 emit_int8((unsigned char)0xAF);
7914 emit_int8((unsigned char)(0xC0 | encode));
7915 }
7916
7917 void Assembler::imulq(Register dst, Register src, int value) {
7918 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7919 if (is8bit(value)) {
7920 emit_int8(0x6B);
7921 emit_int8((unsigned char)(0xC0 | encode));
7922 emit_int8(value & 0xFF);
7923 } else {
7924 emit_int8(0x69);
7925 emit_int8((unsigned char)(0xC0 | encode));
7926 emit_int32(value);
7927 }
7928 }
7929
7930 void Assembler::imulq(Register dst, Address src) {
7931 InstructionMark im(this);
7932 prefixq(src, dst);
7933 emit_int8(0x0F);
7934 emit_int8((unsigned char) 0xAF);
7935 emit_operand(dst, src);
7936 }
7937
7938 void Assembler::incl(Register dst) {
7939 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7940 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7941 int encode = prefix_and_encode(dst->encoding());
7942 emit_int8((unsigned char)0xFF);
7943 emit_int8((unsigned char)(0xC0 | encode));
7944 }
7945
7946 void Assembler::incq(Register dst) {
7947 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7948 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7949 int encode = prefixq_and_encode(dst->encoding());
7950 emit_int8((unsigned char)0xFF);
7951 emit_int8((unsigned char)(0xC0 | encode));
7952 }
7953
7954 void Assembler::incq(Address dst) {
7955 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7956 InstructionMark im(this);
7957 prefixq(dst);
7958 emit_int8((unsigned char)0xFF);
7959 emit_operand(rax, dst);
7960 }
7961
7962 void Assembler::lea(Register dst, Address src) {
7963 leaq(dst, src);
7964 }
7965
7966 void Assembler::leaq(Register dst, Address src) {
7967 InstructionMark im(this);
7968 prefixq(src, dst);
7969 emit_int8((unsigned char)0x8D);
7970 emit_operand(dst, src);
7971 }
7972
7973 void Assembler::mov64(Register dst, int64_t imm64) {
7974 InstructionMark im(this);
7975 int encode = prefixq_and_encode(dst->encoding());
7976 emit_int8((unsigned char)(0xB8 | encode));
7977 emit_int64(imm64);
7978 }
7979
7980 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7981 InstructionMark im(this);
7982 int encode = prefixq_and_encode(dst->encoding());
7983 emit_int8(0xB8 | encode);
7984 emit_data64(imm64, rspec);
7985 }
7986
7987 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7988 InstructionMark im(this);
7989 int encode = prefix_and_encode(dst->encoding());
7990 emit_int8((unsigned char)(0xB8 | encode));
7991 emit_data((int)imm32, rspec, narrow_oop_operand);
7992 }
7993
7994 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7995 InstructionMark im(this);
7996 prefix(dst);
7997 emit_int8((unsigned char)0xC7);
7998 emit_operand(rax, dst, 4);
7999 emit_data((int)imm32, rspec, narrow_oop_operand);
8000 }
8001
8002 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8003 InstructionMark im(this);
8004 int encode = prefix_and_encode(src1->encoding());
8005 emit_int8((unsigned char)0x81);
8006 emit_int8((unsigned char)(0xF8 | encode));
8007 emit_data((int)imm32, rspec, narrow_oop_operand);
8008 }
8009
8010 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8011 InstructionMark im(this);
8012 prefix(src1);
8013 emit_int8((unsigned char)0x81);
8014 emit_operand(rax, src1, 4);
8015 emit_data((int)imm32, rspec, narrow_oop_operand);
8016 }
8017
8018 void Assembler::lzcntq(Register dst, Register src) {
8019 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8020 emit_int8((unsigned char)0xF3);
8021 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8022 emit_int8(0x0F);
8023 emit_int8((unsigned char)0xBD);
8024 emit_int8((unsigned char)(0xC0 | encode));
8025 }
8026
8027 void Assembler::movdq(XMMRegister dst, Register src) {
8028 // table D-1 says MMX/SSE2
8029 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8030 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8031 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8032 emit_int8(0x6E);
8033 emit_int8((unsigned char)(0xC0 | encode));
8034 }
8035
8036 void Assembler::movdq(Register dst, XMMRegister src) {
8037 // table D-1 says MMX/SSE2
8038 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8039 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8040 // swap src/dst to get correct prefix
8041 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8042 emit_int8(0x7E);
8043 emit_int8((unsigned char)(0xC0 | encode));
8044 }
8045
8046 void Assembler::movq(Register dst, Register src) {
8047 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8048 emit_int8((unsigned char)0x8B);
8049 emit_int8((unsigned char)(0xC0 | encode));
8050 }
8051
8052 void Assembler::movq(Register dst, Address src) {
8053 InstructionMark im(this);
8054 prefixq(src, dst);
8055 emit_int8((unsigned char)0x8B);
8056 emit_operand(dst, src);
8057 }
8058
8059 void Assembler::movq(Address dst, Register src) {
8060 InstructionMark im(this);
8061 prefixq(dst, src);
8062 emit_int8((unsigned char)0x89);
8063 emit_operand(src, dst);
8064 }
8065
8066 void Assembler::movsbq(Register dst, Address src) {
8067 InstructionMark im(this);
8068 prefixq(src, dst);
8069 emit_int8(0x0F);
8070 emit_int8((unsigned char)0xBE);
8071 emit_operand(dst, src);
8072 }
8073
8074 void Assembler::movsbq(Register dst, Register src) {
8075 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8076 emit_int8(0x0F);
8077 emit_int8((unsigned char)0xBE);
8078 emit_int8((unsigned char)(0xC0 | encode));
8079 }
8080
8081 void Assembler::movslq(Register dst, int32_t imm32) {
8082 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8083 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8084 // as a result we shouldn't use until tested at runtime...
8085 ShouldNotReachHere();
8086 InstructionMark im(this);
8087 int encode = prefixq_and_encode(dst->encoding());
8088 emit_int8((unsigned char)(0xC7 | encode));
8089 emit_int32(imm32);
8090 }
8091
8092 void Assembler::movslq(Address dst, int32_t imm32) {
8093 assert(is_simm32(imm32), "lost bits");
8094 InstructionMark im(this);
8095 prefixq(dst);
8096 emit_int8((unsigned char)0xC7);
8097 emit_operand(rax, dst, 4);
8098 emit_int32(imm32);
8099 }
8100
8101 void Assembler::movslq(Register dst, Address src) {
8102 InstructionMark im(this);
8103 prefixq(src, dst);
8104 emit_int8(0x63);
8105 emit_operand(dst, src);
8106 }
8107
8108 void Assembler::movslq(Register dst, Register src) {
8109 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8110 emit_int8(0x63);
8111 emit_int8((unsigned char)(0xC0 | encode));
8112 }
8113
8114 void Assembler::movswq(Register dst, Address src) {
8115 InstructionMark im(this);
8116 prefixq(src, dst);
8117 emit_int8(0x0F);
8118 emit_int8((unsigned char)0xBF);
8119 emit_operand(dst, src);
8120 }
8121
8122 void Assembler::movswq(Register dst, Register src) {
8123 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8124 emit_int8((unsigned char)0x0F);
8125 emit_int8((unsigned char)0xBF);
8126 emit_int8((unsigned char)(0xC0 | encode));
8127 }
8128
8129 void Assembler::movzbq(Register dst, Address src) {
8130 InstructionMark im(this);
8131 prefixq(src, dst);
8132 emit_int8((unsigned char)0x0F);
8133 emit_int8((unsigned char)0xB6);
8134 emit_operand(dst, src);
8135 }
8136
8137 void Assembler::movzbq(Register dst, Register src) {
8138 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8139 emit_int8(0x0F);
8140 emit_int8((unsigned char)0xB6);
8141 emit_int8(0xC0 | encode);
8142 }
8143
8144 void Assembler::movzwq(Register dst, Address src) {
8145 InstructionMark im(this);
8146 prefixq(src, dst);
8147 emit_int8((unsigned char)0x0F);
8148 emit_int8((unsigned char)0xB7);
8149 emit_operand(dst, src);
8150 }
8151
8152 void Assembler::movzwq(Register dst, Register src) {
8153 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8154 emit_int8((unsigned char)0x0F);
8155 emit_int8((unsigned char)0xB7);
8156 emit_int8((unsigned char)(0xC0 | encode));
8157 }
8158
8159 void Assembler::mulq(Address src) {
8160 InstructionMark im(this);
8161 prefixq(src);
8162 emit_int8((unsigned char)0xF7);
8163 emit_operand(rsp, src);
8164 }
8165
8166 void Assembler::mulq(Register src) {
8167 int encode = prefixq_and_encode(src->encoding());
8168 emit_int8((unsigned char)0xF7);
8169 emit_int8((unsigned char)(0xE0 | encode));
8170 }
8171
8172 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8173 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8174 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8175 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8176 emit_int8((unsigned char)0xF6);
8177 emit_int8((unsigned char)(0xC0 | encode));
8178 }
8179
8180 void Assembler::negq(Register dst) {
8181 int encode = prefixq_and_encode(dst->encoding());
8182 emit_int8((unsigned char)0xF7);
8183 emit_int8((unsigned char)(0xD8 | encode));
8184 }
8185
8186 void Assembler::notq(Register dst) {
8187 int encode = prefixq_and_encode(dst->encoding());
8188 emit_int8((unsigned char)0xF7);
8189 emit_int8((unsigned char)(0xD0 | encode));
8190 }
8191
8192 void Assembler::orq(Address dst, int32_t imm32) {
8193 InstructionMark im(this);
8194 prefixq(dst);
8195 emit_int8((unsigned char)0x81);
8196 emit_operand(rcx, dst, 4);
8197 emit_int32(imm32);
8198 }
8199
8200 void Assembler::orq(Register dst, int32_t imm32) {
8201 (void) prefixq_and_encode(dst->encoding());
8202 emit_arith(0x81, 0xC8, dst, imm32);
8203 }
8204
8205 void Assembler::orq(Register dst, Address src) {
8206 InstructionMark im(this);
8207 prefixq(src, dst);
8208 emit_int8(0x0B);
8209 emit_operand(dst, src);
8210 }
8211
8212 void Assembler::orq(Register dst, Register src) {
8213 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8214 emit_arith(0x0B, 0xC0, dst, src);
8215 }
8216
8217 void Assembler::popa() { // 64bit
8218 movq(r15, Address(rsp, 0));
8219 movq(r14, Address(rsp, wordSize));
8220 movq(r13, Address(rsp, 2 * wordSize));
8221 movq(r12, Address(rsp, 3 * wordSize));
8222 movq(r11, Address(rsp, 4 * wordSize));
8223 movq(r10, Address(rsp, 5 * wordSize));
8224 movq(r9, Address(rsp, 6 * wordSize));
8225 movq(r8, Address(rsp, 7 * wordSize));
8226 movq(rdi, Address(rsp, 8 * wordSize));
8227 movq(rsi, Address(rsp, 9 * wordSize));
8228 movq(rbp, Address(rsp, 10 * wordSize));
8229 // skip rsp
8230 movq(rbx, Address(rsp, 12 * wordSize));
8231 movq(rdx, Address(rsp, 13 * wordSize));
8232 movq(rcx, Address(rsp, 14 * wordSize));
8233 movq(rax, Address(rsp, 15 * wordSize));
8234
8235 addq(rsp, 16 * wordSize);
8236 }
8237
8238 void Assembler::popcntq(Register dst, Address src) {
8239 assert(VM_Version::supports_popcnt(), "must support");
8240 InstructionMark im(this);
8241 emit_int8((unsigned char)0xF3);
8242 prefixq(src, dst);
8243 emit_int8((unsigned char)0x0F);
8244 emit_int8((unsigned char)0xB8);
8245 emit_operand(dst, src);
8246 }
8247
8248 void Assembler::popcntq(Register dst, Register src) {
8249 assert(VM_Version::supports_popcnt(), "must support");
8250 emit_int8((unsigned char)0xF3);
8251 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8252 emit_int8((unsigned char)0x0F);
8253 emit_int8((unsigned char)0xB8);
8254 emit_int8((unsigned char)(0xC0 | encode));
8255 }
8256
8257 void Assembler::popq(Address dst) {
8258 InstructionMark im(this);
8259 prefixq(dst);
8260 emit_int8((unsigned char)0x8F);
8261 emit_operand(rax, dst);
8262 }
8263
8264 void Assembler::pusha() { // 64bit
8265 // we have to store original rsp. ABI says that 128 bytes
8266 // below rsp are local scratch.
8267 movq(Address(rsp, -5 * wordSize), rsp);
8268
8269 subq(rsp, 16 * wordSize);
8270
8271 movq(Address(rsp, 15 * wordSize), rax);
8272 movq(Address(rsp, 14 * wordSize), rcx);
8273 movq(Address(rsp, 13 * wordSize), rdx);
8274 movq(Address(rsp, 12 * wordSize), rbx);
8275 // skip rsp
8276 movq(Address(rsp, 10 * wordSize), rbp);
8277 movq(Address(rsp, 9 * wordSize), rsi);
8278 movq(Address(rsp, 8 * wordSize), rdi);
8279 movq(Address(rsp, 7 * wordSize), r8);
8280 movq(Address(rsp, 6 * wordSize), r9);
8281 movq(Address(rsp, 5 * wordSize), r10);
8282 movq(Address(rsp, 4 * wordSize), r11);
8283 movq(Address(rsp, 3 * wordSize), r12);
8284 movq(Address(rsp, 2 * wordSize), r13);
8285 movq(Address(rsp, wordSize), r14);
8286 movq(Address(rsp, 0), r15);
8287 }
8288
8289 void Assembler::pushq(Address src) {
8290 InstructionMark im(this);
8291 prefixq(src);
8292 emit_int8((unsigned char)0xFF);
8293 emit_operand(rsi, src);
8294 }
8295
8296 void Assembler::rclq(Register dst, int imm8) {
8297 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8298 int encode = prefixq_and_encode(dst->encoding());
8299 if (imm8 == 1) {
8300 emit_int8((unsigned char)0xD1);
8301 emit_int8((unsigned char)(0xD0 | encode));
8302 } else {
8303 emit_int8((unsigned char)0xC1);
8304 emit_int8((unsigned char)(0xD0 | encode));
8305 emit_int8(imm8);
8306 }
8307 }
8308
8309 void Assembler::rcrq(Register dst, int imm8) {
8310 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8311 int encode = prefixq_and_encode(dst->encoding());
8312 if (imm8 == 1) {
8313 emit_int8((unsigned char)0xD1);
8314 emit_int8((unsigned char)(0xD8 | encode));
8315 } else {
8316 emit_int8((unsigned char)0xC1);
8317 emit_int8((unsigned char)(0xD8 | encode));
8318 emit_int8(imm8);
8319 }
8320 }
8321
8322 void Assembler::rorq(Register dst, int imm8) {
8323 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8324 int encode = prefixq_and_encode(dst->encoding());
8325 if (imm8 == 1) {
8326 emit_int8((unsigned char)0xD1);
8327 emit_int8((unsigned char)(0xC8 | encode));
8328 } else {
8329 emit_int8((unsigned char)0xC1);
8330 emit_int8((unsigned char)(0xc8 | encode));
8331 emit_int8(imm8);
8332 }
8333 }
8334
8335 void Assembler::rorxq(Register dst, Register src, int imm8) {
8336 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8337 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8339 emit_int8((unsigned char)0xF0);
8340 emit_int8((unsigned char)(0xC0 | encode));
8341 emit_int8(imm8);
8342 }
8343
8344 void Assembler::rorxd(Register dst, Register src, int imm8) {
8345 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8346 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8347 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8348 emit_int8((unsigned char)0xF0);
8349 emit_int8((unsigned char)(0xC0 | encode));
8350 emit_int8(imm8);
8351 }
8352
8353 void Assembler::sarq(Register dst, int imm8) {
8354 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8355 int encode = prefixq_and_encode(dst->encoding());
8356 if (imm8 == 1) {
8357 emit_int8((unsigned char)0xD1);
8358 emit_int8((unsigned char)(0xF8 | encode));
8359 } else {
8360 emit_int8((unsigned char)0xC1);
8361 emit_int8((unsigned char)(0xF8 | encode));
8362 emit_int8(imm8);
8363 }
8364 }
8365
8366 void Assembler::sarq(Register dst) {
8367 int encode = prefixq_and_encode(dst->encoding());
8368 emit_int8((unsigned char)0xD3);
8369 emit_int8((unsigned char)(0xF8 | encode));
8370 }
8371
8372 void Assembler::sbbq(Address dst, int32_t imm32) {
8373 InstructionMark im(this);
8374 prefixq(dst);
8375 emit_arith_operand(0x81, rbx, dst, imm32);
8376 }
8377
8378 void Assembler::sbbq(Register dst, int32_t imm32) {
8379 (void) prefixq_and_encode(dst->encoding());
8380 emit_arith(0x81, 0xD8, dst, imm32);
8381 }
8382
8383 void Assembler::sbbq(Register dst, Address src) {
8384 InstructionMark im(this);
8385 prefixq(src, dst);
8386 emit_int8(0x1B);
8387 emit_operand(dst, src);
8388 }
8389
8390 void Assembler::sbbq(Register dst, Register src) {
8391 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8392 emit_arith(0x1B, 0xC0, dst, src);
8393 }
8394
8395 void Assembler::shlq(Register dst, int imm8) {
8396 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8397 int encode = prefixq_and_encode(dst->encoding());
8398 if (imm8 == 1) {
8399 emit_int8((unsigned char)0xD1);
8400 emit_int8((unsigned char)(0xE0 | encode));
8401 } else {
8402 emit_int8((unsigned char)0xC1);
8403 emit_int8((unsigned char)(0xE0 | encode));
8404 emit_int8(imm8);
8405 }
8406 }
8407
8408 void Assembler::shlq(Register dst) {
8409 int encode = prefixq_and_encode(dst->encoding());
8410 emit_int8((unsigned char)0xD3);
8411 emit_int8((unsigned char)(0xE0 | encode));
8412 }
8413
8414 void Assembler::shrq(Register dst, int imm8) {
8415 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8416 int encode = prefixq_and_encode(dst->encoding());
8417 emit_int8((unsigned char)0xC1);
8418 emit_int8((unsigned char)(0xE8 | encode));
8419 emit_int8(imm8);
8420 }
8421
8422 void Assembler::shrq(Register dst) {
8423 int encode = prefixq_and_encode(dst->encoding());
8424 emit_int8((unsigned char)0xD3);
8425 emit_int8(0xE8 | encode);
8426 }
8427
8428 void Assembler::subq(Address dst, int32_t imm32) {
8429 InstructionMark im(this);
8430 prefixq(dst);
8431 emit_arith_operand(0x81, rbp, dst, imm32);
8432 }
8433
8434 void Assembler::subq(Address dst, Register src) {
8435 InstructionMark im(this);
8436 prefixq(dst, src);
8437 emit_int8(0x29);
8438 emit_operand(src, dst);
8439 }
8440
8441 void Assembler::subq(Register dst, int32_t imm32) {
8442 (void) prefixq_and_encode(dst->encoding());
8443 emit_arith(0x81, 0xE8, dst, imm32);
8444 }
8445
8446 // Force generation of a 4 byte immediate value even if it fits into 8bit
8447 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8448 (void) prefixq_and_encode(dst->encoding());
8449 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8450 }
8451
8452 void Assembler::subq(Register dst, Address src) {
8453 InstructionMark im(this);
8454 prefixq(src, dst);
8455 emit_int8(0x2B);
8456 emit_operand(dst, src);
8457 }
8458
8459 void Assembler::subq(Register dst, Register src) {
8460 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8461 emit_arith(0x2B, 0xC0, dst, src);
8462 }
8463
8464 void Assembler::testq(Register dst, int32_t imm32) {
8465 // not using emit_arith because test
8466 // doesn't support sign-extension of
8467 // 8bit operands
8468 int encode = dst->encoding();
8469 if (encode == 0) {
8470 prefix(REX_W);
8471 emit_int8((unsigned char)0xA9);
8472 } else {
8473 encode = prefixq_and_encode(encode);
8474 emit_int8((unsigned char)0xF7);
8475 emit_int8((unsigned char)(0xC0 | encode));
8476 }
8477 emit_int32(imm32);
8478 }
8479
8480 void Assembler::testq(Register dst, Register src) {
8481 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8482 emit_arith(0x85, 0xC0, dst, src);
8483 }
8484
8485 void Assembler::xaddq(Address dst, Register src) {
8486 InstructionMark im(this);
8487 prefixq(dst, src);
8488 emit_int8(0x0F);
8489 emit_int8((unsigned char)0xC1);
8490 emit_operand(src, dst);
8491 }
8492
8493 void Assembler::xchgq(Register dst, Address src) {
8494 InstructionMark im(this);
8495 prefixq(src, dst);
8496 emit_int8((unsigned char)0x87);
8497 emit_operand(dst, src);
8498 }
8499
8500 void Assembler::xchgq(Register dst, Register src) {
8501 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8502 emit_int8((unsigned char)0x87);
8503 emit_int8((unsigned char)(0xc0 | encode));
8504 }
8505
8506 void Assembler::xorq(Register dst, Register src) {
8507 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8508 emit_arith(0x33, 0xC0, dst, src);
8509 }
8510
8511 void Assembler::xorq(Register dst, Address src) {
8512 InstructionMark im(this);
8513 prefixq(src, dst);
8514 emit_int8(0x33);
8515 emit_operand(dst, src);
8516 }
8517
8518 #endif // !LP64