src/cpu/x86/vm/assembler_x86.cpp

*** 3209,3218 ****
--- 3209,3228 ----
    emit_int8(0x00);
    emit_int8(0xC0 | encode);
    emit_int8(imm8);
  }
  
+ void Assembler::vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8) {
+   assert(VM_Version::supports_avx2(), "");
+   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
+   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+   emit_int8(0x46);
+   emit_int8(0xC0 | encode);
+   emit_int8(imm8);
+ }
+ 
+ 
  void Assembler::pause() {
    emit_int8((unsigned char)0xF3);
    emit_int8((unsigned char)0x90);
  }
  
*** 3677,3686 ****
--- 3687,3706 ----
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x00);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
+   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
+          vector_len == AVX_256bit? VM_Version::supports_avx2() :
+          0, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x00);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::pshufb(XMMRegister dst, Address src) {
    assert(VM_Version::supports_ssse3(), "");
    InstructionMark im(this);
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
    attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
*** 3698,3707 ****
--- 3718,3739 ----
    emit_int8(0x70);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(mode & 0xFF);
  }
  
+ void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
+   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
+          vector_len == AVX_256bit? VM_Version::supports_avx2() :
+          0, "");
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8(0x70);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(mode & 0xFF);
+ }
+ 
  void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
    assert(isByte(mode), "invalid value");
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
    InstructionMark im(this);
*** 3738,3748 ****
  
  void Assembler::psrldq(XMMRegister dst, int shift) {
    // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
-   // XMM3 is for /3 encoding: 66 0F 73 /3 ib
    int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
    emit_int8(0x73);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(shift);
  }
--- 3770,3779 ----
*** 4021,4030 ****
--- 4052,4072 ----
    emit_int8((unsigned char)0x0F);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(imm8);
  }
  
+ void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
+   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
+          vector_len == AVX_256bit? VM_Version::supports_avx2() :
+          0, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+   emit_int8((unsigned char)0x0F);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
+ 
  void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
    assert(VM_Version::supports_sse4_1(), "");
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
    emit_int8((unsigned char)0x0E);
*** 8302,8311 ****
--- 8344,8362 ----
    int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
    emit_int8((unsigned char)0xF0);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(imm8);
  }
+ 
+ void Assembler::rorxd(Register dst, Register src, int imm8) {
+   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
+   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
+   emit_int8((unsigned char)0xF0);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
  
  void Assembler::sarq(Register dst, int imm8) {
    assert(isShiftCount(imm8 >> 1), "illegal shift count");
    int encode = prefixq_and_encode(dst->encoding());
    if (imm8 == 1) {