1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
75 // The implementation is only non-empty for the InterpreterMacroAssembler,
76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
77 virtual void check_and_handle_popframe(Register java_thread);
78 virtual void check_and_handle_earlyret(Register java_thread);
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // helpers for FPU flag access
83 // tmp is a temporary register, if none is available use noreg
84 void save_rax (Register tmp);
85 void restore_rax(Register tmp);
86
87 public:
88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf(address entry_point,
263 int number_of_arguments = 0);
264 void call_VM_leaf(address entry_point,
265 Register arg_1);
266 void call_VM_leaf(address entry_point,
267 Register arg_1, Register arg_2);
268 void call_VM_leaf(address entry_point,
269 Register arg_1, Register arg_2, Register arg_3);
270
271 // These always tightly bind to MacroAssembler::call_VM_leaf_base
272 // bypassing the virtual implementation
273 void super_call_VM_leaf(address entry_point);
274 void super_call_VM_leaf(address entry_point, Register arg_1);
275 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
278
279 // last Java Frame (fills frame anchor)
280 void set_last_Java_frame(Register thread,
281 Register last_java_sp,
282 Register last_java_fp,
283 address last_java_pc);
284
285 // thread in the default location (r15_thread on 64bit)
286 void set_last_Java_frame(Register last_java_sp,
287 Register last_java_fp,
288 address last_java_pc);
289
290 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
291
292 // thread in the default location (r15_thread on 64bit)
293 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
294
295 // Stores
296 void store_check(Register obj); // store check for obj - register is destroyed afterwards
297 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
298
299 #if INCLUDE_ALL_GCS
300
301 void g1_write_barrier_pre(Register obj,
302 Register pre_val,
303 Register thread,
304 Register tmp,
305 bool tosca_live,
306 bool expand_call);
307
308 void g1_write_barrier_post(Register store_addr,
309 Register new_val,
310 Register thread,
311 Register tmp,
312 Register tmp2);
313
314 #endif // INCLUDE_ALL_GCS
315
316 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
317 void c2bool(Register x);
318
319 // C++ bool manipulation
320
321 void movbool(Register dst, Address src);
322 void movbool(Address dst, bool boolconst);
323 void movbool(Address dst, Register src);
324 void testbool(Register dst);
325
326 // oop manipulations
327 void load_klass(Register dst, Register src);
328 void store_klass(Register dst, Register src);
329
330 void load_heap_oop(Register dst, Address src);
331 void load_heap_oop_not_null(Register dst, Address src);
332 void store_heap_oop(Address dst, Register src);
333 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
334
335 // Used for storing NULL. All other oop constants should be
336 // stored using routines that take a jobject.
337 void store_heap_oop_null(Address dst);
338
339 void load_prototype_header(Register dst, Register src);
340
341 #ifdef _LP64
342 void store_klass_gap(Register dst, Register src);
343
344 // This dummy is to prevent a call to store_heap_oop from
345 // converting a zero (like NULL) into a Register by giving
346 // the compiler two choices it can't resolve
347
348 void store_heap_oop(Address dst, void* dummy);
349
350 void encode_heap_oop(Register r);
351 void decode_heap_oop(Register r);
352 void encode_heap_oop_not_null(Register r);
353 void decode_heap_oop_not_null(Register r);
354 void encode_heap_oop_not_null(Register dst, Register src);
355 void decode_heap_oop_not_null(Register dst, Register src);
356
357 void set_narrow_oop(Register dst, jobject obj);
358 void set_narrow_oop(Address dst, jobject obj);
359 void cmp_narrow_oop(Register dst, jobject obj);
360 void cmp_narrow_oop(Address dst, jobject obj);
361
362 void encode_klass_not_null(Register r);
363 void decode_klass_not_null(Register r);
364 void encode_klass_not_null(Register dst, Register src);
365 void decode_klass_not_null(Register dst, Register src);
366 void set_narrow_klass(Register dst, Klass* k);
367 void set_narrow_klass(Address dst, Klass* k);
368 void cmp_narrow_klass(Register dst, Klass* k);
369 void cmp_narrow_klass(Address dst, Klass* k);
370
371 // Returns the byte size of the instructions generated by decode_klass_not_null()
372 // when compressed klass pointers are being used.
373 static int instr_size_for_decode_klass_not_null();
374
375 // if heap base register is used - reinit it with the correct value
376 void reinit_heapbase();
377
378 DEBUG_ONLY(void verify_heapbase(const char* msg);)
379
380 #endif // _LP64
381
382 // Int division/remainder for Java
383 // (as idivl, but checks for special case as described in JVM spec.)
384 // returns idivl instruction offset for implicit exception handling
385 int corrected_idivl(Register reg);
386
387 // Long division/remainder for Java
388 // (as idivq, but checks for special case as described in JVM spec.)
389 // returns idivq instruction offset for implicit exception handling
390 int corrected_idivq(Register reg);
391
392 void int3();
393
394 // Long operation macros for a 32bit cpu
395 // Long negation for Java
396 void lneg(Register hi, Register lo);
397
398 // Long multiplication for Java
399 // (destroys contents of eax, ebx, ecx and edx)
400 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
401
402 // Long shifts for Java
403 // (semantics as described in JVM spec.)
404 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
405 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
406
407 // Long compare for Java
408 // (semantics as described in JVM spec.)
409 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
410
411
412 // misc
413
414 // Sign extension
415 void sign_extend_short(Register reg);
416 void sign_extend_byte(Register reg);
417
418 // Division by power of 2, rounding towards 0
419 void division_with_shift(Register reg, int shift_value);
420
421 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
422 //
423 // CF (corresponds to C0) if x < y
424 // PF (corresponds to C2) if unordered
425 // ZF (corresponds to C3) if x = y
426 //
427 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
428 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
429 void fcmp(Register tmp);
430 // Variant of the above which allows y to be further down the stack
431 // and which only pops x and y if specified. If pop_right is
432 // specified then pop_left must also be specified.
433 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
434
435 // Floating-point comparison for Java
436 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
437 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
438 // (semantics as described in JVM spec.)
439 void fcmp2int(Register dst, bool unordered_is_less);
440 // Variant of the above which allows y to be further down the stack
441 // and which only pops x and y if specified. If pop_right is
442 // specified then pop_left must also be specified.
443 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
444
445 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
446 // tmp is a temporary register, if none is available use noreg
447 void fremr(Register tmp);
448
449
450 // same as fcmp2int, but using SSE2
451 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
452 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
453
454 // Inlined sin/cos generator for Java; must not use CPU instruction
455 // directly on Intel as it does not have high enough precision
456 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
457 // number of FPU stack slots in use; all but the topmost will
458 // require saving if a slow case is necessary. Assumes argument is
459 // on FP TOS; result is on FP TOS. No cpu registers are changed by
460 // this code.
461 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
462
463 // branch to L if FPU flag C2 is set/not set
464 // tmp is a temporary register, if none is available use noreg
465 void jC2 (Register tmp, Label& L);
466 void jnC2(Register tmp, Label& L);
467
468 // Pop ST (ffree & fincstp combined)
469 void fpop();
470
471 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
472 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
473 void load_float(Address src);
474
475 // Store float value to 'address'. If UseSSE >= 1, the value is stored
476 // from register xmm0. Otherwise, the value is stored from the FPU stack.
477 void store_float(Address dst);
478
479 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
480 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
481 void load_double(Address src);
482
483 // Store double value to 'address'. If UseSSE >= 2, the value is stored
484 // from register xmm0. Otherwise, the value is stored from the FPU stack.
485 void store_double(Address dst);
486
487 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
488 void push_fTOS();
489
490 // pops double TOS element from CPU stack and pushes on FPU stack
491 void pop_fTOS();
492
493 void empty_FPU_stack();
494
495 void push_IU_state();
496 void pop_IU_state();
497
498 void push_FPU_state();
499 void pop_FPU_state();
500
501 void push_CPU_state();
502 void pop_CPU_state();
503
504 // Round up to a power of two
505 void round_to(Register reg, int modulus);
506
507 // Callee saved registers handling
508 void push_callee_saved_registers();
509 void pop_callee_saved_registers();
510
511 // allocation
512 void eden_allocate(
513 Register obj, // result: pointer to object after successful allocation
514 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
515 int con_size_in_bytes, // object size in bytes if known at compile time
516 Register t1, // temp register
517 Label& slow_case // continuation point if fast allocation fails
518 );
519 void tlab_allocate(
520 Register obj, // result: pointer to object after successful allocation
521 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
522 int con_size_in_bytes, // object size in bytes if known at compile time
523 Register t1, // temp register
524 Register t2, // temp register
525 Label& slow_case // continuation point if fast allocation fails
526 );
527 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
528 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
529
530 void incr_allocated_bytes(Register thread,
531 Register var_size_in_bytes, int con_size_in_bytes,
532 Register t1 = noreg);
533
534 // interface method calling
535 void lookup_interface_method(Register recv_klass,
536 Register intf_klass,
537 RegisterOrConstant itable_index,
538 Register method_result,
539 Register scan_temp,
540 Label& no_such_interface);
541
542 // virtual method calling
543 void lookup_virtual_method(Register recv_klass,
544 RegisterOrConstant vtable_index,
545 Register method_result);
546
547 // Test sub_klass against super_klass, with fast and slow paths.
548
549 // The fast path produces a tri-state answer: yes / no / maybe-slow.
550 // One of the three labels can be NULL, meaning take the fall-through.
551 // If super_check_offset is -1, the value is loaded up from super_klass.
552 // No registers are killed, except temp_reg.
553 void check_klass_subtype_fast_path(Register sub_klass,
554 Register super_klass,
555 Register temp_reg,
556 Label* L_success,
557 Label* L_failure,
558 Label* L_slow_path,
559 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
560
561 // The rest of the type check; must be wired to a corresponding fast path.
562 // It does not repeat the fast path logic, so don't use it standalone.
563 // The temp_reg and temp2_reg can be noreg, if no temps are available.
564 // Updates the sub's secondary super cache as necessary.
565 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
566 void check_klass_subtype_slow_path(Register sub_klass,
567 Register super_klass,
568 Register temp_reg,
569 Register temp2_reg,
570 Label* L_success,
571 Label* L_failure,
572 bool set_cond_codes = false);
573
574 // Simplified, combined version, good for typical uses.
575 // Falls through on failure.
576 void check_klass_subtype(Register sub_klass,
577 Register super_klass,
578 Register temp_reg,
579 Label& L_success);
580
581 // method handles (JSR 292)
582 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
583
584 //----
585 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
586
587 // Debugging
588
589 // only if +VerifyOops
590 // TODO: Make these macros with file and line like sparc version!
591 void verify_oop(Register reg, const char* s = "broken oop");
592 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
593
594 // TODO: verify method and klass metadata (compare against vptr?)
595 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
596 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
597
598 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
599 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
600
601 // only if +VerifyFPU
602 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
603
604 // Verify or restore cpu control state after JNI call
605 void restore_cpu_control_state_after_jni();
606
607 // prints msg, dumps registers and stops execution
608 void stop(const char* msg);
609
610 // prints msg and continues
611 void warn(const char* msg);
612
613 // dumps registers and other state
614 void print_state();
615
616 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
617 static void debug64(char* msg, int64_t pc, int64_t regs[]);
618 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
619 static void print_state64(int64_t pc, int64_t regs[]);
620
621 void os_breakpoint();
622
623 void untested() { stop("untested"); }
624
625 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
626
627 void should_not_reach_here() { stop("should not reach here"); }
628
629 void print_CPU_state();
630
631 // Stack overflow checking
632 void bang_stack_with_offset(int offset) {
633 // stack grows down, caller passes positive offset
634 assert(offset > 0, "must bang with negative offset");
635 movl(Address(rsp, (-offset)), rax);
636 }
637
638 // Writes to stack successive pages until offset reached to check for
639 // stack overflow + shadow pages. Also, clobbers tmp
640 void bang_stack_size(Register size, Register tmp);
641
642 // Check for reserved stack access in method being exited (for JIT)
643 void reserved_stack_check();
644
645 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
646 Register tmp,
647 int offset);
648
649 // Support for serializing memory accesses between threads
650 void serialize_memory(Register thread, Register tmp);
651
652 void verify_tlab();
653
654 // Biased locking support
655 // lock_reg and obj_reg must be loaded up with the appropriate values.
656 // swap_reg must be rax, and is killed.
657 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
658 // be killed; if not supplied, push/pop will be used internally to
659 // allocate a temporary (inefficient, avoid if possible).
660 // Optional slow case is for implementations (interpreter and C1) which branch to
661 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
662 // Returns offset of first potentially-faulting instruction for null
663 // check info (currently consumed only by C1). If
664 // swap_reg_contains_mark is true then returns -1 as it is assumed
665 // the calling code has already passed any potential faults.
666 int biased_locking_enter(Register lock_reg, Register obj_reg,
667 Register swap_reg, Register tmp_reg,
668 bool swap_reg_contains_mark,
669 Label& done, Label* slow_case = NULL,
670 BiasedLockingCounters* counters = NULL);
671 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
672 #ifdef COMPILER2
673 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
674 // See full desription in macroAssembler_x86.cpp.
675 void fast_lock(Register obj, Register box, Register tmp,
676 Register scr, Register cx1, Register cx2,
677 BiasedLockingCounters* counters,
678 RTMLockingCounters* rtm_counters,
679 RTMLockingCounters* stack_rtm_counters,
680 Metadata* method_data,
681 bool use_rtm, bool profile_rtm);
682 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
683 #if INCLUDE_RTM_OPT
684 void rtm_counters_update(Register abort_status, Register rtm_counters);
685 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
686 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
687 RTMLockingCounters* rtm_counters,
688 Metadata* method_data);
689 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
690 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
691 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
692 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
693 void rtm_stack_locking(Register obj, Register tmp, Register scr,
694 Register retry_on_abort_count,
695 RTMLockingCounters* stack_rtm_counters,
696 Metadata* method_data, bool profile_rtm,
697 Label& DONE_LABEL, Label& IsInflated);
698 void rtm_inflated_locking(Register obj, Register box, Register tmp,
699 Register scr, Register retry_on_busy_count,
700 Register retry_on_abort_count,
701 RTMLockingCounters* rtm_counters,
702 Metadata* method_data, bool profile_rtm,
703 Label& DONE_LABEL);
704 #endif
705 #endif
706
707 Condition negate_condition(Condition cond);
708
709 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
710 // operands. In general the names are modified to avoid hiding the instruction in Assembler
711 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
712 // here in MacroAssembler. The major exception to this rule is call
713
714 // Arithmetics
715
716
717 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
718 void addptr(Address dst, Register src);
719
720 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
721 void addptr(Register dst, int32_t src);
722 void addptr(Register dst, Register src);
723 void addptr(Register dst, RegisterOrConstant src) {
724 if (src.is_constant()) addptr(dst, (int) src.as_constant());
725 else addptr(dst, src.as_register());
726 }
727
728 void andptr(Register dst, int32_t src);
729 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
730
731 void cmp8(AddressLiteral src1, int imm);
732
733 // renamed to drag out the casting of address to int32_t/intptr_t
734 void cmp32(Register src1, int32_t imm);
735
736 void cmp32(AddressLiteral src1, int32_t imm);
737 // compare reg - mem, or reg - &mem
738 void cmp32(Register src1, AddressLiteral src2);
739
740 void cmp32(Register src1, Address src2);
741
742 #ifndef _LP64
743 void cmpklass(Address dst, Metadata* obj);
744 void cmpklass(Register dst, Metadata* obj);
745 void cmpoop(Address dst, jobject obj);
746 void cmpoop(Register dst, jobject obj);
747 #endif // _LP64
748
749 // NOTE src2 must be the lval. This is NOT an mem-mem compare
750 void cmpptr(Address src1, AddressLiteral src2);
751
752 void cmpptr(Register src1, AddressLiteral src2);
753
754 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
755 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
756 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757
758 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
759 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
760
761 // cmp64 to avoild hiding cmpq
762 void cmp64(Register src1, AddressLiteral src);
763
764 void cmpxchgptr(Register reg, Address adr);
765
766 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
767
768
769 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
770 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
771
772
773 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
774
775 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
776
777 void shlptr(Register dst, int32_t shift);
778 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
779
780 void shrptr(Register dst, int32_t shift);
781 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
782
783 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
784 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
785
786 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
787
788 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
789 void subptr(Register dst, int32_t src);
790 // Force generation of a 4 byte immediate value even if it fits into 8bit
791 void subptr_imm32(Register dst, int32_t src);
792 void subptr(Register dst, Register src);
793 void subptr(Register dst, RegisterOrConstant src) {
794 if (src.is_constant()) subptr(dst, (int) src.as_constant());
795 else subptr(dst, src.as_register());
796 }
797
798 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
799 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
800
801 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
802 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
803
804 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
805
806
807
808 // Helper functions for statistics gathering.
809 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
810 void cond_inc32(Condition cond, AddressLiteral counter_addr);
811 // Unconditional atomic increment.
812 void atomic_incl(Address counter_addr);
813 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
814 #ifdef _LP64
815 void atomic_incq(Address counter_addr);
816 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
817 #endif
818 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
819 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
820
821 void lea(Register dst, AddressLiteral adr);
822 void lea(Address dst, AddressLiteral adr);
823 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
824
825 void leal32(Register dst, Address src) { leal(dst, src); }
826
827 // Import other testl() methods from the parent class or else
828 // they will be hidden by the following overriding declaration.
829 using Assembler::testl;
830 void testl(Register dst, AddressLiteral src);
831
832 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
833 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
834 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
835 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
836
837 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
838 void testptr(Register src1, Register src2);
839
840 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
841 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
842
843 // Calls
844
845 void call(Label& L, relocInfo::relocType rtype);
846 void call(Register entry);
847
848 // NOTE: this call tranfers to the effective address of entry NOT
849 // the address contained by entry. This is because this is more natural
850 // for jumps/calls.
851 void call(AddressLiteral entry);
852
853 // Emit the CompiledIC call idiom
854 void ic_call(address entry, jint method_index = 0);
855
856 // Jumps
857
858 // NOTE: these jumps tranfer to the effective address of dst NOT
859 // the address contained by dst. This is because this is more natural
860 // for jumps/calls.
861 void jump(AddressLiteral dst);
862 void jump_cc(Condition cc, AddressLiteral dst);
863
864 // 32bit can do a case table jump in one instruction but we no longer allow the base
865 // to be installed in the Address class. This jump will tranfers to the address
866 // contained in the location described by entry (not the address of entry)
867 void jump(ArrayAddress entry);
868
869 // Floating
870
871 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
872 void andpd(XMMRegister dst, AddressLiteral src);
873 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
874
875 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
876 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
877 void andps(XMMRegister dst, AddressLiteral src);
878
879 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
880 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
881 void comiss(XMMRegister dst, AddressLiteral src);
882
883 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
884 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
885 void comisd(XMMRegister dst, AddressLiteral src);
886
887 void fadd_s(Address src) { Assembler::fadd_s(src); }
888 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
889
890 void fldcw(Address src) { Assembler::fldcw(src); }
891 void fldcw(AddressLiteral src);
892
893 void fld_s(int index) { Assembler::fld_s(index); }
894 void fld_s(Address src) { Assembler::fld_s(src); }
895 void fld_s(AddressLiteral src);
896
897 void fld_d(Address src) { Assembler::fld_d(src); }
898 void fld_d(AddressLiteral src);
899
900 void fld_x(Address src) { Assembler::fld_x(src); }
901 void fld_x(AddressLiteral src);
902
903 void fmul_s(Address src) { Assembler::fmul_s(src); }
904 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
905
906 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
907 void ldmxcsr(AddressLiteral src);
908
909 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
910 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
911 Register buf, Register state, Register ofs, Register limit, Register rsp,
912 bool multi_block);
913
914 #ifdef _LP64
915 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
916 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
917 Register buf, Register state, Register ofs, Register limit, Register rsp,
918 bool multi_block, XMMRegister shuf_mask);
919 #else
920 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
921 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
922 Register buf, Register state, Register ofs, Register limit, Register rsp,
923 bool multi_block);
924 #endif
925
926 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
927 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
928 Register rax, Register rcx, Register rdx, Register tmp);
929
930 #ifdef _LP64
931 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
932 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
933 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
934
935 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
936 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
937 Register rax, Register rcx, Register rdx, Register r11);
938
939 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
940 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
941 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
942
943 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
944 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
945 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
946 Register tmp3, Register tmp4);
947
948 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
949 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
950 Register rax, Register rcx, Register rdx, Register tmp1,
951 Register tmp2, Register tmp3, Register tmp4);
952 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
953 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
954 Register rax, Register rcx, Register rdx, Register tmp1,
955 Register tmp2, Register tmp3, Register tmp4);
956 #else
957 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
958 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
959 Register rax, Register rcx, Register rdx, Register tmp1);
960
961 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
962 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
963 Register rax, Register rcx, Register rdx, Register tmp);
964
965 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
966 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
967 Register rdx, Register tmp);
968
969 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
970 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
971 Register rax, Register rbx, Register rdx);
972
973 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
974 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
975 Register rax, Register rcx, Register rdx, Register tmp);
976
977 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
978 Register edx, Register ebx, Register esi, Register edi,
979 Register ebp, Register esp);
980
981 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
982 Register esi, Register edi, Register ebp, Register esp);
983
984 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
985 Register edx, Register ebx, Register esi, Register edi,
986 Register ebp, Register esp);
987
988 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
989 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
990 Register rax, Register rcx, Register rdx, Register tmp);
991 #endif
992
993 void increase_precision();
994 void restore_precision();
995
996 private:
997
998 // call runtime as a fallback for trig functions and pow/exp.
999 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
1000
1001 // these are private because users should be doing movflt/movdbl
1002
1003 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1004 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1005 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1006 void movss(XMMRegister dst, AddressLiteral src);
1007
1008 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1009 void movlpd(XMMRegister dst, AddressLiteral src);
1010
1011 public:
1012
1013 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1014 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1015 void addsd(XMMRegister dst, AddressLiteral src);
1016
1017 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1018 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1019 void addss(XMMRegister dst, AddressLiteral src);
1020
1021 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1022 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1023 void addpd(XMMRegister dst, AddressLiteral src);
1024
1025 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1026 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1027 void divsd(XMMRegister dst, AddressLiteral src);
1028
1029 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1030 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1031 void divss(XMMRegister dst, AddressLiteral src);
1032
1033 // Move Unaligned Double Quadword
1034 void movdqu(Address dst, XMMRegister src);
1035 void movdqu(XMMRegister dst, Address src);
1036 void movdqu(XMMRegister dst, XMMRegister src);
1037 void movdqu(XMMRegister dst, AddressLiteral src);
1038 // AVX Unaligned forms
1039 void vmovdqu(Address dst, XMMRegister src);
1040 void vmovdqu(XMMRegister dst, Address src);
1041 void vmovdqu(XMMRegister dst, XMMRegister src);
1042 void vmovdqu(XMMRegister dst, AddressLiteral src);
1043
1044 // Move Aligned Double Quadword
1045 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1046 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1047 void movdqa(XMMRegister dst, AddressLiteral src);
1048
1049 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1050 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1051 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1052 void movsd(XMMRegister dst, AddressLiteral src);
1053
1054 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1055 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1056 void mulpd(XMMRegister dst, AddressLiteral src);
1057
1058 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1059 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1060 void mulsd(XMMRegister dst, AddressLiteral src);
1061
1062 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1063 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1064 void mulss(XMMRegister dst, AddressLiteral src);
1065
1066 // Carry-Less Multiplication Quadword
1067 void pclmulldq(XMMRegister dst, XMMRegister src) {
1068 // 0x00 - multiply lower 64 bits [0:63]
1069 Assembler::pclmulqdq(dst, src, 0x00);
1070 }
1071 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1072 // 0x11 - multiply upper 64 bits [64:127]
1073 Assembler::pclmulqdq(dst, src, 0x11);
1074 }
1075
1076 void pcmpeqb(XMMRegister dst, XMMRegister src);
1077 void pcmpeqw(XMMRegister dst, XMMRegister src);
1078
1079 void pcmpestri(XMMRegister dst, Address src, int imm8);
1080 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1081
1082 void pmovzxbw(XMMRegister dst, XMMRegister src);
1083 void pmovzxbw(XMMRegister dst, Address src);
1084
1085 void pmovmskb(Register dst, XMMRegister src);
1086
1087 void ptest(XMMRegister dst, XMMRegister src);
1088
1089 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1090 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1091 void sqrtsd(XMMRegister dst, AddressLiteral src);
1092
1093 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1094 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1095 void sqrtss(XMMRegister dst, AddressLiteral src);
1096
1097 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1098 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1099 void subsd(XMMRegister dst, AddressLiteral src);
1100
1101 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1102 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1103 void subss(XMMRegister dst, AddressLiteral src);
1104
1105 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1106 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1107 void ucomiss(XMMRegister dst, AddressLiteral src);
1108
1109 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1110 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1111 void ucomisd(XMMRegister dst, AddressLiteral src);
1112
1113 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1114 void xorpd(XMMRegister dst, XMMRegister src);
1115 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1116 void xorpd(XMMRegister dst, AddressLiteral src);
1117
1118 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1119 void xorps(XMMRegister dst, XMMRegister src);
1120 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1121 void xorps(XMMRegister dst, AddressLiteral src);
1122
1123 // Shuffle Bytes
1124 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1125 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1126 void pshufb(XMMRegister dst, AddressLiteral src);
1127 // AVX 3-operands instructions
1128
1129 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1130 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1131 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1132
1133 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1134 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1135 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1136
1137 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1138 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1139
1140 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1141 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1142
1143 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1144 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1145
1146 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1147
1148 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1149 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1150
1151 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1152 void vpmovmskb(Register dst, XMMRegister src);
1153
1154 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1155 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1156
1157 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1158 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1159
1160 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1161 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1162
1163 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1164 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1165
1166 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1167 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1168
1169 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1170 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1171
1172 void vptest(XMMRegister dst, XMMRegister src);
1173
1174 void punpcklbw(XMMRegister dst, XMMRegister src);
1175 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1176
1177 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1178 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1179
1180 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1181 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1182 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1183
1184 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1185 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1186 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1187
1188 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1189 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1190 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1191
1192 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1193 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1194 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1195
1196 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1197 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1198 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1199
1200 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1201 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1202 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1203
1204 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1205 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1206 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1207
1208 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1209 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1210 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1211
1212 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1213 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1214
1215 // AVX Vector instructions
1216
1217 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1218 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1219 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1220
1221 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1222 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1223 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1224
1225 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1226 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1227 Assembler::vpxor(dst, nds, src, vector_len);
1228 else
1229 Assembler::vxorpd(dst, nds, src, vector_len);
1230 }
1231 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1232 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1233 Assembler::vpxor(dst, nds, src, vector_len);
1234 else
1235 Assembler::vxorpd(dst, nds, src, vector_len);
1236 }
1237
1238 // Simple version for AVX2 256bit vectors
1239 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1240 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1241
1242 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1243 if (UseAVX > 2) {
1244 Assembler::vinserti32x4(dst, dst, src, imm8);
1245 } else if (UseAVX > 1) {
1246 // vinserti128 is available only in AVX2
1247 Assembler::vinserti128(dst, nds, src, imm8);
1248 } else {
1249 Assembler::vinsertf128(dst, nds, src, imm8);
1250 }
1251 }
1252
1253 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1254 if (UseAVX > 2) {
1255 Assembler::vinserti32x4(dst, dst, src, imm8);
1256 } else if (UseAVX > 1) {
1257 // vinserti128 is available only in AVX2
1258 Assembler::vinserti128(dst, nds, src, imm8);
1259 } else {
1260 Assembler::vinsertf128(dst, nds, src, imm8);
1261 }
1262 }
1263
1264 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1265 if (UseAVX > 2) {
1266 Assembler::vextracti32x4(dst, src, imm8);
1267 } else if (UseAVX > 1) {
1268 // vextracti128 is available only in AVX2
1269 Assembler::vextracti128(dst, src, imm8);
1270 } else {
1271 Assembler::vextractf128(dst, src, imm8);
1272 }
1273 }
1274
1275 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1276 if (UseAVX > 2) {
1277 Assembler::vextracti32x4(dst, src, imm8);
1278 } else if (UseAVX > 1) {
1279 // vextracti128 is available only in AVX2
1280 Assembler::vextracti128(dst, src, imm8);
1281 } else {
1282 Assembler::vextractf128(dst, src, imm8);
1283 }
1284 }
1285
1286 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1287 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1288 vinserti128(dst, dst, src, 1);
1289 }
1290 void vinserti128_high(XMMRegister dst, Address src) {
1291 vinserti128(dst, dst, src, 1);
1292 }
1293 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1294 vextracti128(dst, src, 1);
1295 }
1296 void vextracti128_high(Address dst, XMMRegister src) {
1297 vextracti128(dst, src, 1);
1298 }
1299
1300 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1301 if (UseAVX > 2) {
1302 Assembler::vinsertf32x4(dst, dst, src, 1);
1303 } else {
1304 Assembler::vinsertf128(dst, dst, src, 1);
1305 }
1306 }
1307
1308 void vinsertf128_high(XMMRegister dst, Address src) {
1309 if (UseAVX > 2) {
1310 Assembler::vinsertf32x4(dst, dst, src, 1);
1311 } else {
1312 Assembler::vinsertf128(dst, dst, src, 1);
1313 }
1314 }
1315
1316 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1317 if (UseAVX > 2) {
1318 Assembler::vextractf32x4(dst, src, 1);
1319 } else {
1320 Assembler::vextractf128(dst, src, 1);
1321 }
1322 }
1323
1324 void vextractf128_high(Address dst, XMMRegister src) {
1325 if (UseAVX > 2) {
1326 Assembler::vextractf32x4(dst, src, 1);
1327 } else {
1328 Assembler::vextractf128(dst, src, 1);
1329 }
1330 }
1331
1332 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1333 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1334 Assembler::vinserti64x4(dst, dst, src, 1);
1335 }
1336 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1337 Assembler::vinsertf64x4(dst, dst, src, 1);
1338 }
1339 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1340 Assembler::vextracti64x4(dst, src, 1);
1341 }
1342 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1343 Assembler::vextractf64x4(dst, src, 1);
1344 }
1345 void vextractf64x4_high(Address dst, XMMRegister src) {
1346 Assembler::vextractf64x4(dst, src, 1);
1347 }
1348 void vinsertf64x4_high(XMMRegister dst, Address src) {
1349 Assembler::vinsertf64x4(dst, dst, src, 1);
1350 }
1351
1352 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1353 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1354 vinserti128(dst, dst, src, 0);
1355 }
1356 void vinserti128_low(XMMRegister dst, Address src) {
1357 vinserti128(dst, dst, src, 0);
1358 }
1359 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1360 vextracti128(dst, src, 0);
1361 }
1362 void vextracti128_low(Address dst, XMMRegister src) {
1363 vextracti128(dst, src, 0);
1364 }
1365
1366 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1367 if (UseAVX > 2) {
1368 Assembler::vinsertf32x4(dst, dst, src, 0);
1369 } else {
1370 Assembler::vinsertf128(dst, dst, src, 0);
1371 }
1372 }
1373
1374 void vinsertf128_low(XMMRegister dst, Address src) {
1375 if (UseAVX > 2) {
1376 Assembler::vinsertf32x4(dst, dst, src, 0);
1377 } else {
1378 Assembler::vinsertf128(dst, dst, src, 0);
1379 }
1380 }
1381
1382 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1383 if (UseAVX > 2) {
1384 Assembler::vextractf32x4(dst, src, 0);
1385 } else {
1386 Assembler::vextractf128(dst, src, 0);
1387 }
1388 }
1389
1390 void vextractf128_low(Address dst, XMMRegister src) {
1391 if (UseAVX > 2) {
1392 Assembler::vextractf32x4(dst, src, 0);
1393 } else {
1394 Assembler::vextractf128(dst, src, 0);
1395 }
1396 }
1397
1398 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1399 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1400 Assembler::vinserti64x4(dst, dst, src, 0);
1401 }
1402 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1403 Assembler::vinsertf64x4(dst, dst, src, 0);
1404 }
1405 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1406 Assembler::vextracti64x4(dst, src, 0);
1407 }
1408 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1409 Assembler::vextractf64x4(dst, src, 0);
1410 }
1411 void vextractf64x4_low(Address dst, XMMRegister src) {
1412 Assembler::vextractf64x4(dst, src, 0);
1413 }
1414 void vinsertf64x4_low(XMMRegister dst, Address src) {
1415 Assembler::vinsertf64x4(dst, dst, src, 0);
1416 }
1417
1418 // Carry-Less Multiplication Quadword
1419 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1420 // 0x00 - multiply lower 64 bits [0:63]
1421 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1422 }
1423 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1424 // 0x11 - multiply upper 64 bits [64:127]
1425 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1426 }
1427
1428 // Data
1429
1430 void cmov32( Condition cc, Register dst, Address src);
1431 void cmov32( Condition cc, Register dst, Register src);
1432
1433 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1434
1435 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1436 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1437
1438 void movoop(Register dst, jobject obj);
1439 void movoop(Address dst, jobject obj);
1440
1441 void mov_metadata(Register dst, Metadata* obj);
1442 void mov_metadata(Address dst, Metadata* obj);
1443
1444 void movptr(ArrayAddress dst, Register src);
1445 // can this do an lea?
1446 void movptr(Register dst, ArrayAddress src);
1447
1448 void movptr(Register dst, Address src);
1449
1450 #ifdef _LP64
1451 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1452 #else
1453 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1454 #endif
1455
1456 void movptr(Register dst, intptr_t src);
1457 void movptr(Register dst, Register src);
1458 void movptr(Address dst, intptr_t src);
1459
1460 void movptr(Address dst, Register src);
1461
1462 void movptr(Register dst, RegisterOrConstant src) {
1463 if (src.is_constant()) movptr(dst, src.as_constant());
1464 else movptr(dst, src.as_register());
1465 }
1466
1467 #ifdef _LP64
1468 // Generally the next two are only used for moving NULL
1469 // Although there are situations in initializing the mark word where
1470 // they could be used. They are dangerous.
1471
1472 // They only exist on LP64 so that int32_t and intptr_t are not the same
1473 // and we have ambiguous declarations.
1474
1475 void movptr(Address dst, int32_t imm32);
1476 void movptr(Register dst, int32_t imm32);
1477 #endif // _LP64
1478
1479 // to avoid hiding movl
1480 void mov32(AddressLiteral dst, Register src);
1481 void mov32(Register dst, AddressLiteral src);
1482
1483 // to avoid hiding movb
1484 void movbyte(ArrayAddress dst, int src);
1485
1486 // Import other mov() methods from the parent class or else
1487 // they will be hidden by the following overriding declaration.
1488 using Assembler::movdl;
1489 using Assembler::movq;
1490 void movdl(XMMRegister dst, AddressLiteral src);
1491 void movq(XMMRegister dst, AddressLiteral src);
1492
1493 // Can push value or effective address
1494 void pushptr(AddressLiteral src);
1495
1496 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1497 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1498
1499 void pushoop(jobject obj);
1500 void pushklass(Metadata* obj);
1501
1502 // sign extend as need a l to ptr sized element
1503 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1504 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1505
1506 // C2 compiled method's prolog code.
1507 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1508
1509 // clear memory of size 'cnt' qwords, starting at 'base';
1510 // if 'is_large' is set, do not try to produce short loop
1511 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1512
1513 #ifdef COMPILER2
1514 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1515 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1516
1517 // IndexOf strings.
1518 // Small strings are loaded through stack if they cross page boundary.
1519 void string_indexof(Register str1, Register str2,
1520 Register cnt1, Register cnt2,
1521 int int_cnt2, Register result,
1522 XMMRegister vec, Register tmp,
1523 int ae);
1524
1525 // IndexOf for constant substrings with size >= 8 elements
1526 // which don't need to be loaded through stack.
1527 void string_indexofC8(Register str1, Register str2,
1528 Register cnt1, Register cnt2,
1529 int int_cnt2, Register result,
1530 XMMRegister vec, Register tmp,
1531 int ae);
1532
1533 // Smallest code: we don't need to load through stack,
1534 // check string tail.
1535
1536 // helper function for string_compare
1537 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1538 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1539 Address::ScaleFactor scale2, Register index, int ae);
1540 // Compare strings.
1541 void string_compare(Register str1, Register str2,
1542 Register cnt1, Register cnt2, Register result,
1543 XMMRegister vec1, int ae);
1544
1545 // Search for Non-ASCII character (Negative byte value) in a byte array,
1546 // return true if it has any and false otherwise.
1547 void has_negatives(Register ary1, Register len,
1548 Register result, Register tmp1,
1549 XMMRegister vec1, XMMRegister vec2);
1550
1551 // Compare char[] or byte[] arrays.
1552 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1553 Register limit, Register result, Register chr,
1554 XMMRegister vec1, XMMRegister vec2, bool is_char);
1555
1556 #endif
1557
1558 // Fill primitive arrays
1559 void generate_fill(BasicType t, bool aligned,
1560 Register to, Register value, Register count,
1561 Register rtmp, XMMRegister xtmp);
1562
1563 void encode_iso_array(Register src, Register dst, Register len,
1564 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1565 XMMRegister tmp4, Register tmp5, Register result);
1566
1567 #ifdef _LP64
1568 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1569 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1570 Register y, Register y_idx, Register z,
1571 Register carry, Register product,
1572 Register idx, Register kdx);
1573 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1574 Register yz_idx, Register idx,
1575 Register carry, Register product, int offset);
1576 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1577 Register carry, Register carry2,
1578 Register idx, Register jdx,
1579 Register yz_idx1, Register yz_idx2,
1580 Register tmp, Register tmp3, Register tmp4);
1581 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1582 Register yz_idx, Register idx, Register jdx,
1583 Register carry, Register product,
1584 Register carry2);
1585 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1586 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1587 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1588 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1589 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1590 Register tmp2);
1591 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1592 Register rdxReg, Register raxReg);
1593 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1594 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1595 Register tmp3, Register tmp4);
1596 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1597 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1598
1599 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1600 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1601 Register raxReg);
1602 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1603 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1604 Register raxReg);
1605 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1606 Register result, Register tmp1, Register tmp2,
1607 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1608 #endif
1609
1610 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1611 void update_byte_crc32(Register crc, Register val, Register table);
1612 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1613 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1614 // Note on a naming convention:
1615 // Prefix w = register only used on a Westmere+ architecture
1616 // Prefix n = register only used on a Nehalem architecture
1617 #ifdef _LP64
1618 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1619 Register tmp1, Register tmp2, Register tmp3);
1620 #else
1621 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1622 Register tmp1, Register tmp2, Register tmp3,
1623 XMMRegister xtmp1, XMMRegister xtmp2);
1624 #endif
1625 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1626 Register in_out,
1627 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1628 XMMRegister w_xtmp2,
1629 Register tmp1,
1630 Register n_tmp2, Register n_tmp3);
1631 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1632 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1633 Register tmp1, Register tmp2,
1634 Register n_tmp3);
1635 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1636 Register in_out1, Register in_out2, Register in_out3,
1637 Register tmp1, Register tmp2, Register tmp3,
1638 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1639 Register tmp4, Register tmp5,
1640 Register n_tmp6);
1641 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1642 Register tmp1, Register tmp2, Register tmp3,
1643 Register tmp4, Register tmp5, Register tmp6,
1644 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1645 bool is_pclmulqdq_supported);
1646 // Fold 128-bit data chunk
1647 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1648 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1649 // Fold 8-bit data
1650 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1651 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1652
1653 // Compress char[] array to byte[].
1654 void char_array_compress(Register src, Register dst, Register len,
1655 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1656 XMMRegister tmp4, Register tmp5, Register result);
1657
1658 // Inflate byte[] array to char[].
1659 void byte_array_inflate(Register src, Register dst, Register len,
1660 XMMRegister tmp1, Register tmp2);
1661
1662 };
1663
1664 /**
1665 * class SkipIfEqual:
1666 *
1667 * Instantiating this class will result in assembly code being output that will
1668 * jump around any code emitted between the creation of the instance and it's
1669 * automatic destruction at the end of a scope block, depending on the value of
1670 * the flag passed to the constructor, which will be checked at run-time.
1671 */
1672 class SkipIfEqual {
1673 private:
1674 MacroAssembler* _masm;
1675 Label _label;
1676
1677 public:
1678 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1679 ~SkipIfEqual();
1680 };
1681
1682 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP