1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 756 bool clear_pc) { 757 // we must set sp to zero to clear frame 758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 759 // must clear fp, so that compiled frames are not confused; it is 760 // possible that we need it only for debugging 761 if (clear_fp) { 762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 763 } 764 765 if (clear_pc) { 766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 767 } 768 } 769 770 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 771 Register last_java_fp, 772 address last_java_pc) { 773 // determine last_java_sp register 774 if (!last_java_sp->is_valid()) { 775 last_java_sp = rsp; 776 } 777 778 // last_java_fp is optional 779 if (last_java_fp->is_valid()) { 780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 781 last_java_fp); 782 } 783 784 // last_java_pc is optional 785 if (last_java_pc != NULL) { 786 Address java_pc(r15_thread, 787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 788 lea(rscratch1, InternalAddress(last_java_pc)); 789 movptr(java_pc, rscratch1); 790 } 791 792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 793 } 794 795 static void pass_arg0(MacroAssembler* masm, Register arg) { 796 if (c_rarg0 != arg ) { 797 masm->mov(c_rarg0, arg); 798 } 799 } 800 801 static void pass_arg1(MacroAssembler* masm, Register arg) { 802 if (c_rarg1 != arg ) { 803 masm->mov(c_rarg1, arg); 804 } 805 } 806 807 static void pass_arg2(MacroAssembler* masm, Register arg) { 808 if (c_rarg2 != arg ) { 809 masm->mov(c_rarg2, arg); 810 } 811 } 812 813 static void pass_arg3(MacroAssembler* masm, Register arg) { 814 if (c_rarg3 != arg ) { 815 masm->mov(c_rarg3, arg); 816 } 817 } 818 819 void MacroAssembler::stop(const char* msg) { 820 address rip = pc(); 821 pusha(); // get regs on stack 822 lea(c_rarg0, ExternalAddress((address) msg)); 823 lea(c_rarg1, InternalAddress(rip)); 824 movq(c_rarg2, rsp); // pass pointer to regs array 825 andq(rsp, -16); // align stack as required by ABI 826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 827 hlt(); 828 } 829 830 void MacroAssembler::warn(const char* msg) { 831 push(rbp); 832 movq(rbp, rsp); 833 andq(rsp, -16); // align stack as required by push_CPU_state and call 834 push_CPU_state(); // keeps alignment at 16 bytes 835 lea(c_rarg0, ExternalAddress((address) msg)); 836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 837 pop_CPU_state(); 838 mov(rsp, rbp); 839 pop(rbp); 840 } 841 842 void MacroAssembler::print_state() { 843 address rip = pc(); 844 pusha(); // get regs on stack 845 push(rbp); 846 movq(rbp, rsp); 847 andq(rsp, -16); // align stack as required by push_CPU_state and call 848 push_CPU_state(); // keeps alignment at 16 bytes 849 850 lea(c_rarg0, InternalAddress(rip)); 851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 853 854 pop_CPU_state(); 855 mov(rsp, rbp); 856 pop(rbp); 857 popa(); 858 } 859 860 #ifndef PRODUCT 861 extern "C" void findpc(intptr_t x); 862 #endif 863 864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 865 // In order to get locks to work, we need to fake a in_VM state 866 if (ShowMessageBoxOnError) { 867 JavaThread* thread = JavaThread::current(); 868 JavaThreadState saved_state = thread->thread_state(); 869 thread->set_thread_state(_thread_in_vm); 870 #ifndef PRODUCT 871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 872 ttyLocker ttyl; 873 BytecodeCounter::print(); 874 } 875 #endif 876 // To see where a verify_oop failed, get $ebx+40/X for this frame. 877 // XXX correct this offset for amd64 878 // This is the value of eip which points to where verify_oop will return. 879 if (os::message_box(msg, "Execution stopped, print registers?")) { 880 print_state64(pc, regs); 881 BREAKPOINT; 882 assert(false, "start up GDB"); 883 } 884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 885 } else { 886 ttyLocker ttyl; 887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 888 msg); 889 assert(false, "DEBUG MESSAGE: %s", msg); 890 } 891 } 892 893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 894 ttyLocker ttyl; 895 FlagSetting fs(Debugging, true); 896 tty->print_cr("rip = 0x%016lx", pc); 897 #ifndef PRODUCT 898 tty->cr(); 899 findpc(pc); 900 tty->cr(); 901 #endif 902 #define PRINT_REG(rax, value) \ 903 { tty->print("%s = ", #rax); os::print_location(tty, value); } 904 PRINT_REG(rax, regs[15]); 905 PRINT_REG(rbx, regs[12]); 906 PRINT_REG(rcx, regs[14]); 907 PRINT_REG(rdx, regs[13]); 908 PRINT_REG(rdi, regs[8]); 909 PRINT_REG(rsi, regs[9]); 910 PRINT_REG(rbp, regs[10]); 911 PRINT_REG(rsp, regs[11]); 912 PRINT_REG(r8 , regs[7]); 913 PRINT_REG(r9 , regs[6]); 914 PRINT_REG(r10, regs[5]); 915 PRINT_REG(r11, regs[4]); 916 PRINT_REG(r12, regs[3]); 917 PRINT_REG(r13, regs[2]); 918 PRINT_REG(r14, regs[1]); 919 PRINT_REG(r15, regs[0]); 920 #undef PRINT_REG 921 // Print some words near top of staack. 922 int64_t* rsp = (int64_t*) regs[11]; 923 int64_t* dump_sp = rsp; 924 for (int col1 = 0; col1 < 8; col1++) { 925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 926 os::print_location(tty, *dump_sp++); 927 } 928 for (int row = 0; row < 25; row++) { 929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 930 for (int col = 0; col < 4; col++) { 931 tty->print(" 0x%016lx", *dump_sp++); 932 } 933 tty->cr(); 934 } 935 // Print some instructions around pc: 936 Disassembler::decode((address)pc-64, (address)pc); 937 tty->print_cr("--------"); 938 Disassembler::decode((address)pc, (address)pc+32); 939 } 940 941 #endif // _LP64 942 943 // Now versions that are common to 32/64 bit 944 945 void MacroAssembler::addptr(Register dst, int32_t imm32) { 946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 947 } 948 949 void MacroAssembler::addptr(Register dst, Register src) { 950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 951 } 952 953 void MacroAssembler::addptr(Address dst, Register src) { 954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 955 } 956 957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 958 if (reachable(src)) { 959 Assembler::addsd(dst, as_Address(src)); 960 } else { 961 lea(rscratch1, src); 962 Assembler::addsd(dst, Address(rscratch1, 0)); 963 } 964 } 965 966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 967 if (reachable(src)) { 968 addss(dst, as_Address(src)); 969 } else { 970 lea(rscratch1, src); 971 addss(dst, Address(rscratch1, 0)); 972 } 973 } 974 975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 976 if (reachable(src)) { 977 Assembler::addpd(dst, as_Address(src)); 978 } else { 979 lea(rscratch1, src); 980 Assembler::addpd(dst, Address(rscratch1, 0)); 981 } 982 } 983 984 void MacroAssembler::align(int modulus) { 985 align(modulus, offset()); 986 } 987 988 void MacroAssembler::align(int modulus, int target) { 989 if (target % modulus != 0) { 990 nop(modulus - (target % modulus)); 991 } 992 } 993 994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 995 // Used in sign-masking with aligned address. 996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 997 if (reachable(src)) { 998 Assembler::andpd(dst, as_Address(src)); 999 } else { 1000 lea(rscratch1, src); 1001 Assembler::andpd(dst, Address(rscratch1, 0)); 1002 } 1003 } 1004 1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1006 // Used in sign-masking with aligned address. 1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1008 if (reachable(src)) { 1009 Assembler::andps(dst, as_Address(src)); 1010 } else { 1011 lea(rscratch1, src); 1012 Assembler::andps(dst, Address(rscratch1, 0)); 1013 } 1014 } 1015 1016 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1018 } 1019 1020 void MacroAssembler::atomic_incl(Address counter_addr) { 1021 if (os::is_MP()) 1022 lock(); 1023 incrementl(counter_addr); 1024 } 1025 1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1027 if (reachable(counter_addr)) { 1028 atomic_incl(as_Address(counter_addr)); 1029 } else { 1030 lea(scr, counter_addr); 1031 atomic_incl(Address(scr, 0)); 1032 } 1033 } 1034 1035 #ifdef _LP64 1036 void MacroAssembler::atomic_incq(Address counter_addr) { 1037 if (os::is_MP()) 1038 lock(); 1039 incrementq(counter_addr); 1040 } 1041 1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1043 if (reachable(counter_addr)) { 1044 atomic_incq(as_Address(counter_addr)); 1045 } else { 1046 lea(scr, counter_addr); 1047 atomic_incq(Address(scr, 0)); 1048 } 1049 } 1050 #endif 1051 1052 // Writes to stack successive pages until offset reached to check for 1053 // stack overflow + shadow pages. This clobbers tmp. 1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1055 movptr(tmp, rsp); 1056 // Bang stack for total size given plus shadow page size. 1057 // Bang one page at a time because large size can bang beyond yellow and 1058 // red zones. 1059 Label loop; 1060 bind(loop); 1061 movl(Address(tmp, (-os::vm_page_size())), size ); 1062 subptr(tmp, os::vm_page_size()); 1063 subl(size, os::vm_page_size()); 1064 jcc(Assembler::greater, loop); 1065 1066 // Bang down shadow pages too. 1067 // At this point, (tmp-0) is the last address touched, so don't 1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1069 // was post-decremented.) Skip this address by starting at i=1, and 1070 // touch a few more pages below. N.B. It is important to touch all 1071 // the way down including all pages in the shadow zone. 1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1073 // this could be any sized move but this is can be a debugging crumb 1074 // so the bigger the better. 1075 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1076 } 1077 } 1078 1079 void MacroAssembler::reserved_stack_check() { 1080 // testing if reserved zone needs to be enabled 1081 Label no_reserved_zone_enabling; 1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1083 NOT_LP64(get_thread(rsi);) 1084 1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1086 jcc(Assembler::below, no_reserved_zone_enabling); 1087 1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1090 should_not_reach_here(); 1091 1092 bind(no_reserved_zone_enabling); 1093 } 1094 1095 int MacroAssembler::biased_locking_enter(Register lock_reg, 1096 Register obj_reg, 1097 Register swap_reg, 1098 Register tmp_reg, 1099 bool swap_reg_contains_mark, 1100 Label& done, 1101 Label* slow_case, 1102 BiasedLockingCounters* counters) { 1103 assert(UseBiasedLocking, "why call this otherwise?"); 1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1105 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1110 1111 if (PrintBiasedLockingStatistics && counters == NULL) { 1112 counters = BiasedLocking::counters(); 1113 } 1114 // Biased locking 1115 // See whether the lock is currently biased toward our thread and 1116 // whether the epoch is still valid 1117 // Note that the runtime guarantees sufficient alignment of JavaThread 1118 // pointers to allow age to be placed into low bits 1119 // First check to see whether biasing is even enabled for this object 1120 Label cas_label; 1121 int null_check_offset = -1; 1122 if (!swap_reg_contains_mark) { 1123 null_check_offset = offset(); 1124 movptr(swap_reg, mark_addr); 1125 } 1126 movptr(tmp_reg, swap_reg); 1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1129 jcc(Assembler::notEqual, cas_label); 1130 // The bias pattern is present in the object's header. Need to check 1131 // whether the bias owner and the epoch are both still current. 1132 #ifndef _LP64 1133 // Note that because there is no current thread register on x86_32 we 1134 // need to store off the mark word we read out of the object to 1135 // avoid reloading it and needing to recheck invariants below. This 1136 // store is unfortunate but it makes the overall code shorter and 1137 // simpler. 1138 movptr(saved_mark_addr, swap_reg); 1139 #endif 1140 if (swap_reg_contains_mark) { 1141 null_check_offset = offset(); 1142 } 1143 load_prototype_header(tmp_reg, obj_reg); 1144 #ifdef _LP64 1145 orptr(tmp_reg, r15_thread); 1146 xorptr(tmp_reg, swap_reg); 1147 Register header_reg = tmp_reg; 1148 #else 1149 xorptr(tmp_reg, swap_reg); 1150 get_thread(swap_reg); 1151 xorptr(swap_reg, tmp_reg); 1152 Register header_reg = swap_reg; 1153 #endif 1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1155 if (counters != NULL) { 1156 cond_inc32(Assembler::zero, 1157 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1158 } 1159 jcc(Assembler::equal, done); 1160 1161 Label try_revoke_bias; 1162 Label try_rebias; 1163 1164 // At this point we know that the header has the bias pattern and 1165 // that we are not the bias owner in the current epoch. We need to 1166 // figure out more details about the state of the header in order to 1167 // know what operations can be legally performed on the object's 1168 // header. 1169 1170 // If the low three bits in the xor result aren't clear, that means 1171 // the prototype header is no longer biased and we have to revoke 1172 // the bias on this object. 1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1174 jccb(Assembler::notZero, try_revoke_bias); 1175 1176 // Biasing is still enabled for this data type. See whether the 1177 // epoch of the current bias is still valid, meaning that the epoch 1178 // bits of the mark word are equal to the epoch bits of the 1179 // prototype header. (Note that the prototype header's epoch bits 1180 // only change at a safepoint.) If not, attempt to rebias the object 1181 // toward the current thread. Note that we must be absolutely sure 1182 // that the current epoch is invalid in order to do this because 1183 // otherwise the manipulations it performs on the mark word are 1184 // illegal. 1185 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1186 jccb(Assembler::notZero, try_rebias); 1187 1188 // The epoch of the current bias is still valid but we know nothing 1189 // about the owner; it might be set or it might be clear. Try to 1190 // acquire the bias of the object using an atomic operation. If this 1191 // fails we will go in to the runtime to revoke the object's bias. 1192 // Note that we first construct the presumed unbiased header so we 1193 // don't accidentally blow away another thread's valid bias. 1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1195 andptr(swap_reg, 1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1197 #ifdef _LP64 1198 movptr(tmp_reg, swap_reg); 1199 orptr(tmp_reg, r15_thread); 1200 #else 1201 get_thread(tmp_reg); 1202 orptr(tmp_reg, swap_reg); 1203 #endif 1204 if (os::is_MP()) { 1205 lock(); 1206 } 1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1208 // If the biasing toward our thread failed, this means that 1209 // another thread succeeded in biasing it toward itself and we 1210 // need to revoke that bias. The revocation will occur in the 1211 // interpreter runtime in the slow case. 1212 if (counters != NULL) { 1213 cond_inc32(Assembler::zero, 1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1215 } 1216 if (slow_case != NULL) { 1217 jcc(Assembler::notZero, *slow_case); 1218 } 1219 jmp(done); 1220 1221 bind(try_rebias); 1222 // At this point we know the epoch has expired, meaning that the 1223 // current "bias owner", if any, is actually invalid. Under these 1224 // circumstances _only_, we are allowed to use the current header's 1225 // value as the comparison value when doing the cas to acquire the 1226 // bias in the current epoch. In other words, we allow transfer of 1227 // the bias from one thread to another directly in this situation. 1228 // 1229 // FIXME: due to a lack of registers we currently blow away the age 1230 // bits in this situation. Should attempt to preserve them. 1231 load_prototype_header(tmp_reg, obj_reg); 1232 #ifdef _LP64 1233 orptr(tmp_reg, r15_thread); 1234 #else 1235 get_thread(swap_reg); 1236 orptr(tmp_reg, swap_reg); 1237 movptr(swap_reg, saved_mark_addr); 1238 #endif 1239 if (os::is_MP()) { 1240 lock(); 1241 } 1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1243 // If the biasing toward our thread failed, then another thread 1244 // succeeded in biasing it toward itself and we need to revoke that 1245 // bias. The revocation will occur in the runtime in the slow case. 1246 if (counters != NULL) { 1247 cond_inc32(Assembler::zero, 1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1249 } 1250 if (slow_case != NULL) { 1251 jcc(Assembler::notZero, *slow_case); 1252 } 1253 jmp(done); 1254 1255 bind(try_revoke_bias); 1256 // The prototype mark in the klass doesn't have the bias bit set any 1257 // more, indicating that objects of this data type are not supposed 1258 // to be biased any more. We are going to try to reset the mark of 1259 // this object to the prototype value and fall through to the 1260 // CAS-based locking scheme. Note that if our CAS fails, it means 1261 // that another thread raced us for the privilege of revoking the 1262 // bias of this particular object, so it's okay to continue in the 1263 // normal locking code. 1264 // 1265 // FIXME: due to a lack of registers we currently blow away the age 1266 // bits in this situation. Should attempt to preserve them. 1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1268 load_prototype_header(tmp_reg, obj_reg); 1269 if (os::is_MP()) { 1270 lock(); 1271 } 1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1273 // Fall through to the normal CAS-based lock, because no matter what 1274 // the result of the above CAS, some thread must have succeeded in 1275 // removing the bias bit from the object's header. 1276 if (counters != NULL) { 1277 cond_inc32(Assembler::zero, 1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1279 } 1280 1281 bind(cas_label); 1282 1283 return null_check_offset; 1284 } 1285 1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1287 assert(UseBiasedLocking, "why call this otherwise?"); 1288 1289 // Check for biased locking unlock case, which is a no-op 1290 // Note: we do not have to check the thread ID for two reasons. 1291 // First, the interpreter checks for IllegalMonitorStateException at 1292 // a higher level. Second, if the bias was revoked while we held the 1293 // lock, the object could not be rebiased toward another thread, so 1294 // the bias bit would be clear. 1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1298 jcc(Assembler::equal, done); 1299 } 1300 1301 #ifdef COMPILER2 1302 1303 #if INCLUDE_RTM_OPT 1304 1305 // Update rtm_counters based on abort status 1306 // input: abort_status 1307 // rtm_counters (RTMLockingCounters*) 1308 // flags are killed 1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1310 1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1312 if (PrintPreciseRTMLockingStatistics) { 1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1314 Label check_abort; 1315 testl(abort_status, (1<<i)); 1316 jccb(Assembler::equal, check_abort); 1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1318 bind(check_abort); 1319 } 1320 } 1321 } 1322 1323 // Branch if (random & (count-1) != 0), count is 2^n 1324 // tmp, scr and flags are killed 1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1326 assert(tmp == rax, ""); 1327 assert(scr == rdx, ""); 1328 rdtsc(); // modifies EDX:EAX 1329 andptr(tmp, count-1); 1330 jccb(Assembler::notZero, brLabel); 1331 } 1332 1333 // Perform abort ratio calculation, set no_rtm bit if high ratio 1334 // input: rtm_counters_Reg (RTMLockingCounters* address) 1335 // tmpReg, rtm_counters_Reg and flags are killed 1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1337 Register rtm_counters_Reg, 1338 RTMLockingCounters* rtm_counters, 1339 Metadata* method_data) { 1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1341 1342 if (RTMLockingCalculationDelay > 0) { 1343 // Delay calculation 1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1345 testptr(tmpReg, tmpReg); 1346 jccb(Assembler::equal, L_done); 1347 } 1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1349 // Aborted transactions = abort_count * 100 1350 // All transactions = total_count * RTMTotalCountIncrRate 1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1352 1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1354 cmpptr(tmpReg, RTMAbortThreshold); 1355 jccb(Assembler::below, L_check_always_rtm2); 1356 imulptr(tmpReg, tmpReg, 100); 1357 1358 Register scrReg = rtm_counters_Reg; 1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1361 imulptr(scrReg, scrReg, RTMAbortRatio); 1362 cmpptr(tmpReg, scrReg); 1363 jccb(Assembler::below, L_check_always_rtm1); 1364 if (method_data != NULL) { 1365 // set rtm_state to "no rtm" in MDO 1366 mov_metadata(tmpReg, method_data); 1367 if (os::is_MP()) { 1368 lock(); 1369 } 1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1371 } 1372 jmpb(L_done); 1373 bind(L_check_always_rtm1); 1374 // Reload RTMLockingCounters* address 1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1376 bind(L_check_always_rtm2); 1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1379 jccb(Assembler::below, L_done); 1380 if (method_data != NULL) { 1381 // set rtm_state to "always rtm" in MDO 1382 mov_metadata(tmpReg, method_data); 1383 if (os::is_MP()) { 1384 lock(); 1385 } 1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1387 } 1388 bind(L_done); 1389 } 1390 1391 // Update counters and perform abort ratio calculation 1392 // input: abort_status_Reg 1393 // rtm_counters_Reg, flags are killed 1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1395 Register rtm_counters_Reg, 1396 RTMLockingCounters* rtm_counters, 1397 Metadata* method_data, 1398 bool profile_rtm) { 1399 1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1401 // update rtm counters based on rax value at abort 1402 // reads abort_status_Reg, updates flags 1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1405 if (profile_rtm) { 1406 // Save abort status because abort_status_Reg is used by following code. 1407 if (RTMRetryCount > 0) { 1408 push(abort_status_Reg); 1409 } 1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1412 // restore abort status 1413 if (RTMRetryCount > 0) { 1414 pop(abort_status_Reg); 1415 } 1416 } 1417 } 1418 1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1420 // inputs: retry_count_Reg 1421 // : abort_status_Reg 1422 // output: retry_count_Reg decremented by 1 1423 // flags are killed 1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1425 Label doneRetry; 1426 assert(abort_status_Reg == rax, ""); 1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1429 // if reason is in 0x6 and retry count != 0 then retry 1430 andptr(abort_status_Reg, 0x6); 1431 jccb(Assembler::zero, doneRetry); 1432 testl(retry_count_Reg, retry_count_Reg); 1433 jccb(Assembler::zero, doneRetry); 1434 pause(); 1435 decrementl(retry_count_Reg); 1436 jmp(retryLabel); 1437 bind(doneRetry); 1438 } 1439 1440 // Spin and retry if lock is busy, 1441 // inputs: box_Reg (monitor address) 1442 // : retry_count_Reg 1443 // output: retry_count_Reg decremented by 1 1444 // : clear z flag if retry count exceeded 1445 // tmp_Reg, scr_Reg, flags are killed 1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1448 Label SpinLoop, SpinExit, doneRetry; 1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1450 1451 testl(retry_count_Reg, retry_count_Reg); 1452 jccb(Assembler::zero, doneRetry); 1453 decrementl(retry_count_Reg); 1454 movptr(scr_Reg, RTMSpinLoopCount); 1455 1456 bind(SpinLoop); 1457 pause(); 1458 decrementl(scr_Reg); 1459 jccb(Assembler::lessEqual, SpinExit); 1460 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1461 testptr(tmp_Reg, tmp_Reg); 1462 jccb(Assembler::notZero, SpinLoop); 1463 1464 bind(SpinExit); 1465 jmp(retryLabel); 1466 bind(doneRetry); 1467 incrementl(retry_count_Reg); // clear z flag 1468 } 1469 1470 // Use RTM for normal stack locks 1471 // Input: objReg (object to lock) 1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1473 Register retry_on_abort_count_Reg, 1474 RTMLockingCounters* stack_rtm_counters, 1475 Metadata* method_data, bool profile_rtm, 1476 Label& DONE_LABEL, Label& IsInflated) { 1477 assert(UseRTMForStackLocks, "why call this otherwise?"); 1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1479 assert(tmpReg == rax, ""); 1480 assert(scrReg == rdx, ""); 1481 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1482 1483 if (RTMRetryCount > 0) { 1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1485 bind(L_rtm_retry); 1486 } 1487 movptr(tmpReg, Address(objReg, 0)); 1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1489 jcc(Assembler::notZero, IsInflated); 1490 1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1492 Label L_noincrement; 1493 if (RTMTotalCountIncrRate > 1) { 1494 // tmpReg, scrReg and flags are killed 1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1496 } 1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1499 bind(L_noincrement); 1500 } 1501 xbegin(L_on_abort); 1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1506 1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1508 if (UseRTMXendForLockBusy) { 1509 xend(); 1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1511 jmp(L_decrement_retry); 1512 } 1513 else { 1514 xabort(0); 1515 } 1516 bind(L_on_abort); 1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1519 } 1520 bind(L_decrement_retry); 1521 if (RTMRetryCount > 0) { 1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1524 } 1525 } 1526 1527 // Use RTM for inflating locks 1528 // inputs: objReg (object to lock) 1529 // boxReg (on-stack box address (displaced header location) - KILLED) 1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1532 Register scrReg, Register retry_on_busy_count_Reg, 1533 Register retry_on_abort_count_Reg, 1534 RTMLockingCounters* rtm_counters, 1535 Metadata* method_data, bool profile_rtm, 1536 Label& DONE_LABEL) { 1537 assert(UseRTMLocking, "why call this otherwise?"); 1538 assert(tmpReg == rax, ""); 1539 assert(scrReg == rdx, ""); 1540 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1542 1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1546 1547 if (RTMRetryCount > 0) { 1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1550 bind(L_rtm_retry); 1551 } 1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1553 Label L_noincrement; 1554 if (RTMTotalCountIncrRate > 1) { 1555 // tmpReg, scrReg and flags are killed 1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1557 } 1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1560 bind(L_noincrement); 1561 } 1562 xbegin(L_on_abort); 1563 movptr(tmpReg, Address(objReg, 0)); 1564 movptr(tmpReg, Address(tmpReg, owner_offset)); 1565 testptr(tmpReg, tmpReg); 1566 jcc(Assembler::zero, DONE_LABEL); 1567 if (UseRTMXendForLockBusy) { 1568 xend(); 1569 jmp(L_decrement_retry); 1570 } 1571 else { 1572 xabort(0); 1573 } 1574 bind(L_on_abort); 1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1578 } 1579 if (RTMRetryCount > 0) { 1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1582 } 1583 1584 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1585 testptr(tmpReg, tmpReg) ; 1586 jccb(Assembler::notZero, L_decrement_retry) ; 1587 1588 // Appears unlocked - try to swing _owner from null to non-null. 1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1590 #ifdef _LP64 1591 Register threadReg = r15_thread; 1592 #else 1593 get_thread(scrReg); 1594 Register threadReg = scrReg; 1595 #endif 1596 if (os::is_MP()) { 1597 lock(); 1598 } 1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1600 1601 if (RTMRetryCount > 0) { 1602 // success done else retry 1603 jccb(Assembler::equal, DONE_LABEL) ; 1604 bind(L_decrement_retry); 1605 // Spin and retry if lock is busy. 1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1607 } 1608 else { 1609 bind(L_decrement_retry); 1610 } 1611 } 1612 1613 #endif // INCLUDE_RTM_OPT 1614 1615 // Fast_Lock and Fast_Unlock used by C2 1616 1617 // Because the transitions from emitted code to the runtime 1618 // monitorenter/exit helper stubs are so slow it's critical that 1619 // we inline both the stack-locking fast-path and the inflated fast path. 1620 // 1621 // See also: cmpFastLock and cmpFastUnlock. 1622 // 1623 // What follows is a specialized inline transliteration of the code 1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1625 // another option would be to emit TrySlowEnter and TrySlowExit methods 1626 // at startup-time. These methods would accept arguments as 1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1630 // In practice, however, the # of lock sites is bounded and is usually small. 1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1632 // if the processor uses simple bimodal branch predictors keyed by EIP 1633 // Since the helper routines would be called from multiple synchronization 1634 // sites. 1635 // 1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1638 // to those specialized methods. That'd give us a mostly platform-independent 1639 // implementation that the JITs could optimize and inline at their pleasure. 1640 // Done correctly, the only time we'd need to cross to native could would be 1641 // to park() or unpark() threads. We'd also need a few more unsafe operators 1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1643 // (b) explicit barriers or fence operations. 1644 // 1645 // TODO: 1646 // 1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1650 // the lock operators would typically be faster than reifying Self. 1651 // 1652 // * Ideally I'd define the primitives as: 1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1656 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1657 // Furthermore the register assignments are overconstrained, possibly resulting in 1658 // sub-optimal code near the synchronization site. 1659 // 1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1661 // Alternately, use a better sp-proximity test. 1662 // 1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1664 // Either one is sufficient to uniquely identify a thread. 1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1666 // 1667 // * Intrinsify notify() and notifyAll() for the common cases where the 1668 // object is locked by the calling thread but the waitlist is empty. 1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1670 // 1671 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1672 // But beware of excessive branch density on AMD Opterons. 1673 // 1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1675 // or failure of the fast-path. If the fast-path fails then we pass 1676 // control to the slow-path, typically in C. In Fast_Lock and 1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1678 // will emit a conditional branch immediately after the node. 1679 // So we have branches to branches and lots of ICC.ZF games. 1680 // Instead, it might be better to have C2 pass a "FailureLabel" 1681 // into Fast_Lock and Fast_Unlock. In the case of success, control 1682 // will drop through the node. ICC.ZF is undefined at exit. 1683 // In the case of failure, the node will branch directly to the 1684 // FailureLabel 1685 1686 1687 // obj: object to lock 1688 // box: on-stack box address (displaced header location) - KILLED 1689 // rax,: tmp -- KILLED 1690 // scr: tmp -- KILLED 1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1692 Register scrReg, Register cx1Reg, Register cx2Reg, 1693 BiasedLockingCounters* counters, 1694 RTMLockingCounters* rtm_counters, 1695 RTMLockingCounters* stack_rtm_counters, 1696 Metadata* method_data, 1697 bool use_rtm, bool profile_rtm) { 1698 // Ensure the register assignments are disjoint 1699 assert(tmpReg == rax, ""); 1700 1701 if (use_rtm) { 1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1703 } else { 1704 assert(cx1Reg == noreg, ""); 1705 assert(cx2Reg == noreg, ""); 1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1707 } 1708 1709 if (counters != NULL) { 1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1711 } 1712 if (EmitSync & 1) { 1713 // set box->dhw = markOopDesc::unused_mark() 1714 // Force all sync thru slow-path: slow_enter() and slow_exit() 1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1716 cmpptr (rsp, (int32_t)NULL_WORD); 1717 } else { 1718 // Possible cases that we'll encounter in fast_lock 1719 // ------------------------------------------------ 1720 // * Inflated 1721 // -- unlocked 1722 // -- Locked 1723 // = by self 1724 // = by other 1725 // * biased 1726 // -- by Self 1727 // -- by other 1728 // * neutral 1729 // * stack-locked 1730 // -- by self 1731 // = sp-proximity test hits 1732 // = sp-proximity test generates false-negative 1733 // -- by other 1734 // 1735 1736 Label IsInflated, DONE_LABEL; 1737 1738 // it's stack-locked, biased or neutral 1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1740 // order to reduce the number of conditional branches in the most common cases. 1741 // Beware -- there's a subtle invariant that fetch of the markword 1742 // at [FETCH], below, will never observe a biased encoding (*101b). 1743 // If this invariant is not held we risk exclusion (safety) failure. 1744 if (UseBiasedLocking && !UseOptoBiasInlining) { 1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1746 } 1747 1748 #if INCLUDE_RTM_OPT 1749 if (UseRTMForStackLocks && use_rtm) { 1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1751 stack_rtm_counters, method_data, profile_rtm, 1752 DONE_LABEL, IsInflated); 1753 } 1754 #endif // INCLUDE_RTM_OPT 1755 1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1758 jccb(Assembler::notZero, IsInflated); 1759 1760 // Attempt stack-locking ... 1761 orptr (tmpReg, markOopDesc::unlocked_value); 1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1763 if (os::is_MP()) { 1764 lock(); 1765 } 1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1767 if (counters != NULL) { 1768 cond_inc32(Assembler::equal, 1769 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1770 } 1771 jcc(Assembler::equal, DONE_LABEL); // Success 1772 1773 // Recursive locking. 1774 // The object is stack-locked: markword contains stack pointer to BasicLock. 1775 // Locked by current thread if difference with current SP is less than one page. 1776 subptr(tmpReg, rsp); 1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1779 movptr(Address(boxReg, 0), tmpReg); 1780 if (counters != NULL) { 1781 cond_inc32(Assembler::equal, 1782 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1783 } 1784 jmp(DONE_LABEL); 1785 1786 bind(IsInflated); 1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1788 1789 #if INCLUDE_RTM_OPT 1790 // Use the same RTM locking code in 32- and 64-bit VM. 1791 if (use_rtm) { 1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1793 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1794 } else { 1795 #endif // INCLUDE_RTM_OPT 1796 1797 #ifndef _LP64 1798 // The object is inflated. 1799 1800 // boxReg refers to the on-stack BasicLock in the current frame. 1801 // We'd like to write: 1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1804 // additional latency as we have another ST in the store buffer that must drain. 1805 1806 if (EmitSync & 8192) { 1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1808 get_thread (scrReg); 1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1811 if (os::is_MP()) { 1812 lock(); 1813 } 1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1815 } else 1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1817 // register juggle because we need tmpReg for cmpxchgptr below 1818 movptr(scrReg, boxReg); 1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1820 1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1823 // prefetchw [eax + Offset(_owner)-2] 1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1825 } 1826 1827 if ((EmitSync & 64) == 0) { 1828 // Optimistic form: consider XORL tmpReg,tmpReg 1829 movptr(tmpReg, NULL_WORD); 1830 } else { 1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1832 // Test-And-CAS instead of CAS 1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1834 testptr(tmpReg, tmpReg); // Locked ? 1835 jccb (Assembler::notZero, DONE_LABEL); 1836 } 1837 1838 // Appears unlocked - try to swing _owner from null to non-null. 1839 // Ideally, I'd manifest "Self" with get_thread and then attempt 1840 // to CAS the register containing Self into m->Owner. 1841 // But we don't have enough registers, so instead we can either try to CAS 1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1843 // we later store "Self" into m->Owner. Transiently storing a stack address 1844 // (rsp or the address of the box) into m->owner is harmless. 1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1846 if (os::is_MP()) { 1847 lock(); 1848 } 1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1851 // If we weren't able to swing _owner from NULL to the BasicLock 1852 // then take the slow path. 1853 jccb (Assembler::notZero, DONE_LABEL); 1854 // update _owner from BasicLock to thread 1855 get_thread (scrReg); // beware: clobbers ICCs 1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1858 1859 // If the CAS fails we can either retry or pass control to the slow-path. 1860 // We use the latter tactic. 1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1862 // If the CAS was successful ... 1863 // Self has acquired the lock 1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1865 // Intentional fall-through into DONE_LABEL ... 1866 } else { 1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1868 movptr(boxReg, tmpReg); 1869 1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1872 // prefetchw [eax + Offset(_owner)-2] 1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1874 } 1875 1876 if ((EmitSync & 64) == 0) { 1877 // Optimistic form 1878 xorptr (tmpReg, tmpReg); 1879 } else { 1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1882 testptr(tmpReg, tmpReg); // Locked ? 1883 jccb (Assembler::notZero, DONE_LABEL); 1884 } 1885 1886 // Appears unlocked - try to swing _owner from null to non-null. 1887 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1889 get_thread (scrReg); 1890 if (os::is_MP()) { 1891 lock(); 1892 } 1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1894 1895 // If the CAS fails we can either retry or pass control to the slow-path. 1896 // We use the latter tactic. 1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1898 // If the CAS was successful ... 1899 // Self has acquired the lock 1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1901 // Intentional fall-through into DONE_LABEL ... 1902 } 1903 #else // _LP64 1904 // It's inflated 1905 movq(scrReg, tmpReg); 1906 xorq(tmpReg, tmpReg); 1907 1908 if (os::is_MP()) { 1909 lock(); 1910 } 1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1913 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1915 // Intentional fall-through into DONE_LABEL ... 1916 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1917 #endif // _LP64 1918 #if INCLUDE_RTM_OPT 1919 } // use_rtm() 1920 #endif 1921 // DONE_LABEL is a hot target - we'd really like to place it at the 1922 // start of cache line by padding with NOPs. 1923 // See the AMD and Intel software optimization manuals for the 1924 // most efficient "long" NOP encodings. 1925 // Unfortunately none of our alignment mechanisms suffice. 1926 bind(DONE_LABEL); 1927 1928 // At DONE_LABEL the icc ZFlag is set as follows ... 1929 // Fast_Unlock uses the same protocol. 1930 // ZFlag == 1 -> Success 1931 // ZFlag == 0 -> Failure - force control through the slow-path 1932 } 1933 } 1934 1935 // obj: object to unlock 1936 // box: box address (displaced header location), killed. Must be EAX. 1937 // tmp: killed, cannot be obj nor box. 1938 // 1939 // Some commentary on balanced locking: 1940 // 1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1942 // Methods that don't have provably balanced locking are forced to run in the 1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1944 // The interpreter provides two properties: 1945 // I1: At return-time the interpreter automatically and quietly unlocks any 1946 // objects acquired the current activation (frame). Recall that the 1947 // interpreter maintains an on-stack list of locks currently held by 1948 // a frame. 1949 // I2: If a method attempts to unlock an object that is not held by the 1950 // the frame the interpreter throws IMSX. 1951 // 1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1953 // B() doesn't have provably balanced locking so it runs in the interpreter. 1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1955 // is still locked by A(). 1956 // 1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1961 // Arguably given that the spec legislates the JNI case as undefined our implementation 1962 // could reasonably *avoid* checking owner in Fast_Unlock(). 1963 // In the interest of performance we elide m->Owner==Self check in unlock. 1964 // A perfectly viable alternative is to elide the owner check except when 1965 // Xcheck:jni is enabled. 1966 1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1968 assert(boxReg == rax, ""); 1969 assert_different_registers(objReg, boxReg, tmpReg); 1970 1971 if (EmitSync & 4) { 1972 // Disable - inhibit all inlining. Force control through the slow-path 1973 cmpptr (rsp, 0); 1974 } else { 1975 Label DONE_LABEL, Stacked, CheckSucc; 1976 1977 // Critically, the biased locking test must have precedence over 1978 // and appear before the (box->dhw == 0) recursive stack-lock test. 1979 if (UseBiasedLocking && !UseOptoBiasInlining) { 1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1981 } 1982 1983 #if INCLUDE_RTM_OPT 1984 if (UseRTMForStackLocks && use_rtm) { 1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1986 Label L_regular_unlock; 1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1991 xend(); // otherwise end... 1992 jmp(DONE_LABEL); // ... and we're done 1993 bind(L_regular_unlock); 1994 } 1995 #endif 1996 1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 2001 jccb (Assembler::zero, Stacked); 2002 2003 // It's inflated. 2004 #if INCLUDE_RTM_OPT 2005 if (use_rtm) { 2006 Label L_regular_inflated_unlock; 2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2008 movptr(boxReg, Address(tmpReg, owner_offset)); 2009 testptr(boxReg, boxReg); 2010 jccb(Assembler::notZero, L_regular_inflated_unlock); 2011 xend(); 2012 jmpb(DONE_LABEL); 2013 bind(L_regular_inflated_unlock); 2014 } 2015 #endif 2016 2017 // Despite our balanced locking property we still check that m->_owner == Self 2018 // as java routines or native JNI code called by this thread might 2019 // have released the lock. 2020 // Refer to the comments in synchronizer.cpp for how we might encode extra 2021 // state in _succ so we can avoid fetching EntryList|cxq. 2022 // 2023 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2024 // such as recursive enter and exit -- but we have to be wary of 2025 // I$ bloat, T$ effects and BP$ effects. 2026 // 2027 // If there's no contention try a 1-0 exit. That is, exit without 2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2029 // we detect and recover from the race that the 1-0 exit admits. 2030 // 2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2032 // before it STs null into _owner, releasing the lock. Updates 2033 // to data protected by the critical section must be visible before 2034 // we drop the lock (and thus before any other thread could acquire 2035 // the lock and observe the fields protected by the lock). 2036 // IA32's memory-model is SPO, so STs are ordered with respect to 2037 // each other and there's no need for an explicit barrier (fence). 2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2039 #ifndef _LP64 2040 get_thread (boxReg); 2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2042 // prefetchw [ebx + Offset(_owner)-2] 2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2044 } 2045 2046 // Note that we could employ various encoding schemes to reduce 2047 // the number of loads below (currently 4) to just 2 or 3. 2048 // Refer to the comments in synchronizer.cpp. 2049 // In practice the chain of fetches doesn't seem to impact performance, however. 2050 xorptr(boxReg, boxReg); 2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2052 // Attempt to reduce branch density - AMD's branch predictor. 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2056 jccb (Assembler::notZero, DONE_LABEL); 2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2058 jmpb (DONE_LABEL); 2059 } else { 2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2061 jccb (Assembler::notZero, DONE_LABEL); 2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2064 jccb (Assembler::notZero, CheckSucc); 2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2066 jmpb (DONE_LABEL); 2067 } 2068 2069 // The Following code fragment (EmitSync & 65536) improves the performance of 2070 // contended applications and contended synchronization microbenchmarks. 2071 // Unfortunately the emission of the code - even though not executed - causes regressions 2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2073 // with an equal number of never-executed NOPs results in the same regression. 2074 // We leave it off by default. 2075 2076 if ((EmitSync & 65536) != 0) { 2077 Label LSuccess, LGoSlowPath ; 2078 2079 bind (CheckSucc); 2080 2081 // Optional pre-test ... it's safe to elide this 2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2083 jccb(Assembler::zero, LGoSlowPath); 2084 2085 // We have a classic Dekker-style idiom: 2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2087 // There are a number of ways to implement the barrier: 2088 // (1) lock:andl &m->_owner, 0 2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2092 // (2) If supported, an explicit MFENCE is appealing. 2093 // In older IA32 processors MFENCE is slower than lock:add or xchg 2094 // particularly if the write-buffer is full as might be the case if 2095 // if stores closely precede the fence or fence-equivalent instruction. 2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2097 // as the situation has changed with Nehalem and Shanghai. 2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2099 // The $lines underlying the top-of-stack should be in M-state. 2100 // The locked add instruction is serializing, of course. 2101 // (4) Use xchg, which is serializing 2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2104 // The integer condition codes will tell us if succ was 0. 2105 // Since _succ and _owner should reside in the same $line and 2106 // we just stored into _owner, it's likely that the $line 2107 // remains in M-state for the lock:orl. 2108 // 2109 // We currently use (3), although it's likely that switching to (2) 2110 // is correct for the future. 2111 2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2113 if (os::is_MP()) { 2114 lock(); addptr(Address(rsp, 0), 0); 2115 } 2116 // Ratify _succ remains non-null 2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2118 jccb (Assembler::notZero, LSuccess); 2119 2120 xorptr(boxReg, boxReg); // box is really EAX 2121 if (os::is_MP()) { lock(); } 2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2123 // There's no successor so we tried to regrab the lock with the 2124 // placeholder value. If that didn't work, then another thread 2125 // grabbed the lock so we're done (and exit was a success). 2126 jccb (Assembler::notEqual, LSuccess); 2127 // Since we're low on registers we installed rsp as a placeholding in _owner. 2128 // Now install Self over rsp. This is safe as we're transitioning from 2129 // non-null to non=null 2130 get_thread (boxReg); 2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2132 // Intentional fall-through into LGoSlowPath ... 2133 2134 bind (LGoSlowPath); 2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2136 jmpb (DONE_LABEL); 2137 2138 bind (LSuccess); 2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2140 jmpb (DONE_LABEL); 2141 } 2142 2143 bind (Stacked); 2144 // It's not inflated and it's not recursively stack-locked and it's not biased. 2145 // It must be stack-locked. 2146 // Try to reset the header to displaced header. 2147 // The "box" value on the stack is stable, so we can reload 2148 // and be assured we observe the same value as above. 2149 movptr(tmpReg, Address(boxReg, 0)); 2150 if (os::is_MP()) { 2151 lock(); 2152 } 2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2154 // Intention fall-thru into DONE_LABEL 2155 2156 // DONE_LABEL is a hot target - we'd really like to place it at the 2157 // start of cache line by padding with NOPs. 2158 // See the AMD and Intel software optimization manuals for the 2159 // most efficient "long" NOP encodings. 2160 // Unfortunately none of our alignment mechanisms suffice. 2161 if ((EmitSync & 65536) == 0) { 2162 bind (CheckSucc); 2163 } 2164 #else // _LP64 2165 // It's inflated 2166 if (EmitSync & 1024) { 2167 // Emit code to check that _owner == Self 2168 // We could fold the _owner test into subsequent code more efficiently 2169 // than using a stand-alone check, but since _owner checking is off by 2170 // default we don't bother. We also might consider predicating the 2171 // _owner==Self check on Xcheck:jni or running on a debug build. 2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2173 xorptr(boxReg, r15_thread); 2174 } else { 2175 xorptr(boxReg, boxReg); 2176 } 2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2178 jccb (Assembler::notZero, DONE_LABEL); 2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2181 jccb (Assembler::notZero, CheckSucc); 2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2183 jmpb (DONE_LABEL); 2184 2185 if ((EmitSync & 65536) == 0) { 2186 // Try to avoid passing control into the slow_path ... 2187 Label LSuccess, LGoSlowPath ; 2188 bind (CheckSucc); 2189 2190 // The following optional optimization can be elided if necessary 2191 // Effectively: if (succ == null) goto SlowPath 2192 // The code reduces the window for a race, however, 2193 // and thus benefits performance. 2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2195 jccb (Assembler::zero, LGoSlowPath); 2196 2197 xorptr(boxReg, boxReg); 2198 if ((EmitSync & 16) && os::is_MP()) { 2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2200 } else { 2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2202 if (os::is_MP()) { 2203 // Memory barrier/fence 2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2206 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2210 lock(); addl(Address(rsp, 0), 0); 2211 } 2212 } 2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2214 jccb (Assembler::notZero, LSuccess); 2215 2216 // Rare inopportune interleaving - race. 2217 // The successor vanished in the small window above. 2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2219 // We need to ensure progress and succession. 2220 // Try to reacquire the lock. 2221 // If that fails then the new owner is responsible for succession and this 2222 // thread needs to take no further action and can exit via the fast path (success). 2223 // If the re-acquire succeeds then pass control into the slow path. 2224 // As implemented, this latter mode is horrible because we generated more 2225 // coherence traffic on the lock *and* artifically extended the critical section 2226 // length while by virtue of passing control into the slow path. 2227 2228 // box is really RAX -- the following CMPXCHG depends on that binding 2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2230 if (os::is_MP()) { lock(); } 2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2232 // There's no successor so we tried to regrab the lock. 2233 // If that didn't work, then another thread grabbed the 2234 // lock so we're done (and exit was a success). 2235 jccb (Assembler::notEqual, LSuccess); 2236 // Intentional fall-through into slow-path 2237 2238 bind (LGoSlowPath); 2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2240 jmpb (DONE_LABEL); 2241 2242 bind (LSuccess); 2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2244 jmpb (DONE_LABEL); 2245 } 2246 2247 bind (Stacked); 2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2249 if (os::is_MP()) { lock(); } 2250 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2251 2252 if (EmitSync & 65536) { 2253 bind (CheckSucc); 2254 } 2255 #endif 2256 bind(DONE_LABEL); 2257 } 2258 } 2259 #endif // COMPILER2 2260 2261 void MacroAssembler::c2bool(Register x) { 2262 // implements x == 0 ? 0 : 1 2263 // note: must only look at least-significant byte of x 2264 // since C-style booleans are stored in one byte 2265 // only! (was bug) 2266 andl(x, 0xFF); 2267 setb(Assembler::notZero, x); 2268 } 2269 2270 // Wouldn't need if AddressLiteral version had new name 2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2272 Assembler::call(L, rtype); 2273 } 2274 2275 void MacroAssembler::call(Register entry) { 2276 Assembler::call(entry); 2277 } 2278 2279 void MacroAssembler::call(AddressLiteral entry) { 2280 if (reachable(entry)) { 2281 Assembler::call_literal(entry.target(), entry.rspec()); 2282 } else { 2283 lea(rscratch1, entry); 2284 Assembler::call(rscratch1); 2285 } 2286 } 2287 2288 void MacroAssembler::ic_call(address entry, jint method_index) { 2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2290 movptr(rax, (intptr_t)Universe::non_oop_word()); 2291 call(AddressLiteral(entry, rh)); 2292 } 2293 2294 // Implementation of call_VM versions 2295 2296 void MacroAssembler::call_VM(Register oop_result, 2297 address entry_point, 2298 bool check_exceptions) { 2299 Label C, E; 2300 call(C, relocInfo::none); 2301 jmp(E); 2302 2303 bind(C); 2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2305 ret(0); 2306 2307 bind(E); 2308 } 2309 2310 void MacroAssembler::call_VM(Register oop_result, 2311 address entry_point, 2312 Register arg_1, 2313 bool check_exceptions) { 2314 Label C, E; 2315 call(C, relocInfo::none); 2316 jmp(E); 2317 2318 bind(C); 2319 pass_arg1(this, arg_1); 2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2321 ret(0); 2322 2323 bind(E); 2324 } 2325 2326 void MacroAssembler::call_VM(Register oop_result, 2327 address entry_point, 2328 Register arg_1, 2329 Register arg_2, 2330 bool check_exceptions) { 2331 Label C, E; 2332 call(C, relocInfo::none); 2333 jmp(E); 2334 2335 bind(C); 2336 2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2338 2339 pass_arg2(this, arg_2); 2340 pass_arg1(this, arg_1); 2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2342 ret(0); 2343 2344 bind(E); 2345 } 2346 2347 void MacroAssembler::call_VM(Register oop_result, 2348 address entry_point, 2349 Register arg_1, 2350 Register arg_2, 2351 Register arg_3, 2352 bool check_exceptions) { 2353 Label C, E; 2354 call(C, relocInfo::none); 2355 jmp(E); 2356 2357 bind(C); 2358 2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2361 pass_arg3(this, arg_3); 2362 2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2364 pass_arg2(this, arg_2); 2365 2366 pass_arg1(this, arg_1); 2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2368 ret(0); 2369 2370 bind(E); 2371 } 2372 2373 void MacroAssembler::call_VM(Register oop_result, 2374 Register last_java_sp, 2375 address entry_point, 2376 int number_of_arguments, 2377 bool check_exceptions) { 2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2380 } 2381 2382 void MacroAssembler::call_VM(Register oop_result, 2383 Register last_java_sp, 2384 address entry_point, 2385 Register arg_1, 2386 bool check_exceptions) { 2387 pass_arg1(this, arg_1); 2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2389 } 2390 2391 void MacroAssembler::call_VM(Register oop_result, 2392 Register last_java_sp, 2393 address entry_point, 2394 Register arg_1, 2395 Register arg_2, 2396 bool check_exceptions) { 2397 2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2399 pass_arg2(this, arg_2); 2400 pass_arg1(this, arg_1); 2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2402 } 2403 2404 void MacroAssembler::call_VM(Register oop_result, 2405 Register last_java_sp, 2406 address entry_point, 2407 Register arg_1, 2408 Register arg_2, 2409 Register arg_3, 2410 bool check_exceptions) { 2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2413 pass_arg3(this, arg_3); 2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2415 pass_arg2(this, arg_2); 2416 pass_arg1(this, arg_1); 2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2418 } 2419 2420 void MacroAssembler::super_call_VM(Register oop_result, 2421 Register last_java_sp, 2422 address entry_point, 2423 int number_of_arguments, 2424 bool check_exceptions) { 2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2427 } 2428 2429 void MacroAssembler::super_call_VM(Register oop_result, 2430 Register last_java_sp, 2431 address entry_point, 2432 Register arg_1, 2433 bool check_exceptions) { 2434 pass_arg1(this, arg_1); 2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2436 } 2437 2438 void MacroAssembler::super_call_VM(Register oop_result, 2439 Register last_java_sp, 2440 address entry_point, 2441 Register arg_1, 2442 Register arg_2, 2443 bool check_exceptions) { 2444 2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2446 pass_arg2(this, arg_2); 2447 pass_arg1(this, arg_1); 2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2449 } 2450 2451 void MacroAssembler::super_call_VM(Register oop_result, 2452 Register last_java_sp, 2453 address entry_point, 2454 Register arg_1, 2455 Register arg_2, 2456 Register arg_3, 2457 bool check_exceptions) { 2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2460 pass_arg3(this, arg_3); 2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2462 pass_arg2(this, arg_2); 2463 pass_arg1(this, arg_1); 2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2465 } 2466 2467 void MacroAssembler::call_VM_base(Register oop_result, 2468 Register java_thread, 2469 Register last_java_sp, 2470 address entry_point, 2471 int number_of_arguments, 2472 bool check_exceptions) { 2473 // determine java_thread register 2474 if (!java_thread->is_valid()) { 2475 #ifdef _LP64 2476 java_thread = r15_thread; 2477 #else 2478 java_thread = rdi; 2479 get_thread(java_thread); 2480 #endif // LP64 2481 } 2482 // determine last_java_sp register 2483 if (!last_java_sp->is_valid()) { 2484 last_java_sp = rsp; 2485 } 2486 // debugging support 2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2489 #ifdef ASSERT 2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2491 // r12 is the heapbase. 2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2493 #endif // ASSERT 2494 2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2497 2498 // push java thread (becomes first argument of C function) 2499 2500 NOT_LP64(push(java_thread); number_of_arguments++); 2501 LP64_ONLY(mov(c_rarg0, r15_thread)); 2502 2503 // set last Java frame before call 2504 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2505 2506 // Only interpreter should have to set fp 2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2508 2509 // do the call, remove parameters 2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2511 2512 // restore the thread (cannot use the pushed argument since arguments 2513 // may be overwritten by C code generated by an optimizing compiler); 2514 // however can use the register value directly if it is callee saved. 2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2516 // rdi & rsi (also r15) are callee saved -> nothing to do 2517 #ifdef ASSERT 2518 guarantee(java_thread != rax, "change this code"); 2519 push(rax); 2520 { Label L; 2521 get_thread(rax); 2522 cmpptr(java_thread, rax); 2523 jcc(Assembler::equal, L); 2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2525 bind(L); 2526 } 2527 pop(rax); 2528 #endif 2529 } else { 2530 get_thread(java_thread); 2531 } 2532 // reset last Java frame 2533 // Only interpreter should have to clear fp 2534 reset_last_Java_frame(java_thread, true, false); 2535 2536 // C++ interp handles this in the interpreter 2537 check_and_handle_popframe(java_thread); 2538 check_and_handle_earlyret(java_thread); 2539 2540 if (check_exceptions) { 2541 // check for pending exceptions (java_thread is set upon return) 2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2543 #ifndef _LP64 2544 jump_cc(Assembler::notEqual, 2545 RuntimeAddress(StubRoutines::forward_exception_entry())); 2546 #else 2547 // This used to conditionally jump to forward_exception however it is 2548 // possible if we relocate that the branch will not reach. So we must jump 2549 // around so we can always reach 2550 2551 Label ok; 2552 jcc(Assembler::equal, ok); 2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2554 bind(ok); 2555 #endif // LP64 2556 } 2557 2558 // get oop result if there is one and reset the value in the thread 2559 if (oop_result->is_valid()) { 2560 get_vm_result(oop_result, java_thread); 2561 } 2562 } 2563 2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2565 2566 // Calculate the value for last_Java_sp 2567 // somewhat subtle. call_VM does an intermediate call 2568 // which places a return address on the stack just under the 2569 // stack pointer as the user finsihed with it. This allows 2570 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2571 // On 32bit we then have to push additional args on the stack to accomplish 2572 // the actual requested call. On 64bit call_VM only can use register args 2573 // so the only extra space is the return address that call_VM created. 2574 // This hopefully explains the calculations here. 2575 2576 #ifdef _LP64 2577 // We've pushed one address, correct last_Java_sp 2578 lea(rax, Address(rsp, wordSize)); 2579 #else 2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2581 #endif // LP64 2582 2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2584 2585 } 2586 2587 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2588 call_VM_leaf_base(entry_point, number_of_arguments); 2589 } 2590 2591 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2592 pass_arg0(this, arg_0); 2593 call_VM_leaf(entry_point, 1); 2594 } 2595 2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2597 2598 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2599 pass_arg1(this, arg_1); 2600 pass_arg0(this, arg_0); 2601 call_VM_leaf(entry_point, 2); 2602 } 2603 2604 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2605 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2606 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2607 pass_arg2(this, arg_2); 2608 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2609 pass_arg1(this, arg_1); 2610 pass_arg0(this, arg_0); 2611 call_VM_leaf(entry_point, 3); 2612 } 2613 2614 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2615 pass_arg0(this, arg_0); 2616 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2617 } 2618 2619 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2620 2621 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2622 pass_arg1(this, arg_1); 2623 pass_arg0(this, arg_0); 2624 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2625 } 2626 2627 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2628 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2629 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2630 pass_arg2(this, arg_2); 2631 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2632 pass_arg1(this, arg_1); 2633 pass_arg0(this, arg_0); 2634 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2635 } 2636 2637 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2638 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2639 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2640 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2641 pass_arg3(this, arg_3); 2642 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2644 pass_arg2(this, arg_2); 2645 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2646 pass_arg1(this, arg_1); 2647 pass_arg0(this, arg_0); 2648 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2649 } 2650 2651 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2652 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2653 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2654 verify_oop(oop_result, "broken oop in call_VM_base"); 2655 } 2656 2657 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2658 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2659 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2660 } 2661 2662 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2663 } 2664 2665 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2666 } 2667 2668 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2669 if (reachable(src1)) { 2670 cmpl(as_Address(src1), imm); 2671 } else { 2672 lea(rscratch1, src1); 2673 cmpl(Address(rscratch1, 0), imm); 2674 } 2675 } 2676 2677 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2678 assert(!src2.is_lval(), "use cmpptr"); 2679 if (reachable(src2)) { 2680 cmpl(src1, as_Address(src2)); 2681 } else { 2682 lea(rscratch1, src2); 2683 cmpl(src1, Address(rscratch1, 0)); 2684 } 2685 } 2686 2687 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2688 Assembler::cmpl(src1, imm); 2689 } 2690 2691 void MacroAssembler::cmp32(Register src1, Address src2) { 2692 Assembler::cmpl(src1, src2); 2693 } 2694 2695 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2696 ucomisd(opr1, opr2); 2697 2698 Label L; 2699 if (unordered_is_less) { 2700 movl(dst, -1); 2701 jcc(Assembler::parity, L); 2702 jcc(Assembler::below , L); 2703 movl(dst, 0); 2704 jcc(Assembler::equal , L); 2705 increment(dst); 2706 } else { // unordered is greater 2707 movl(dst, 1); 2708 jcc(Assembler::parity, L); 2709 jcc(Assembler::above , L); 2710 movl(dst, 0); 2711 jcc(Assembler::equal , L); 2712 decrementl(dst); 2713 } 2714 bind(L); 2715 } 2716 2717 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2718 ucomiss(opr1, opr2); 2719 2720 Label L; 2721 if (unordered_is_less) { 2722 movl(dst, -1); 2723 jcc(Assembler::parity, L); 2724 jcc(Assembler::below , L); 2725 movl(dst, 0); 2726 jcc(Assembler::equal , L); 2727 increment(dst); 2728 } else { // unordered is greater 2729 movl(dst, 1); 2730 jcc(Assembler::parity, L); 2731 jcc(Assembler::above , L); 2732 movl(dst, 0); 2733 jcc(Assembler::equal , L); 2734 decrementl(dst); 2735 } 2736 bind(L); 2737 } 2738 2739 2740 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2741 if (reachable(src1)) { 2742 cmpb(as_Address(src1), imm); 2743 } else { 2744 lea(rscratch1, src1); 2745 cmpb(Address(rscratch1, 0), imm); 2746 } 2747 } 2748 2749 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2750 #ifdef _LP64 2751 if (src2.is_lval()) { 2752 movptr(rscratch1, src2); 2753 Assembler::cmpq(src1, rscratch1); 2754 } else if (reachable(src2)) { 2755 cmpq(src1, as_Address(src2)); 2756 } else { 2757 lea(rscratch1, src2); 2758 Assembler::cmpq(src1, Address(rscratch1, 0)); 2759 } 2760 #else 2761 if (src2.is_lval()) { 2762 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2763 } else { 2764 cmpl(src1, as_Address(src2)); 2765 } 2766 #endif // _LP64 2767 } 2768 2769 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2770 assert(src2.is_lval(), "not a mem-mem compare"); 2771 #ifdef _LP64 2772 // moves src2's literal address 2773 movptr(rscratch1, src2); 2774 Assembler::cmpq(src1, rscratch1); 2775 #else 2776 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2777 #endif // _LP64 2778 } 2779 2780 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2781 if (reachable(adr)) { 2782 if (os::is_MP()) 2783 lock(); 2784 cmpxchgptr(reg, as_Address(adr)); 2785 } else { 2786 lea(rscratch1, adr); 2787 if (os::is_MP()) 2788 lock(); 2789 cmpxchgptr(reg, Address(rscratch1, 0)); 2790 } 2791 } 2792 2793 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2794 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2795 } 2796 2797 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2798 if (reachable(src)) { 2799 Assembler::comisd(dst, as_Address(src)); 2800 } else { 2801 lea(rscratch1, src); 2802 Assembler::comisd(dst, Address(rscratch1, 0)); 2803 } 2804 } 2805 2806 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2807 if (reachable(src)) { 2808 Assembler::comiss(dst, as_Address(src)); 2809 } else { 2810 lea(rscratch1, src); 2811 Assembler::comiss(dst, Address(rscratch1, 0)); 2812 } 2813 } 2814 2815 2816 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2817 Condition negated_cond = negate_condition(cond); 2818 Label L; 2819 jcc(negated_cond, L); 2820 pushf(); // Preserve flags 2821 atomic_incl(counter_addr); 2822 popf(); 2823 bind(L); 2824 } 2825 2826 int MacroAssembler::corrected_idivl(Register reg) { 2827 // Full implementation of Java idiv and irem; checks for 2828 // special case as described in JVM spec., p.243 & p.271. 2829 // The function returns the (pc) offset of the idivl 2830 // instruction - may be needed for implicit exceptions. 2831 // 2832 // normal case special case 2833 // 2834 // input : rax,: dividend min_int 2835 // reg: divisor (may not be rax,/rdx) -1 2836 // 2837 // output: rax,: quotient (= rax, idiv reg) min_int 2838 // rdx: remainder (= rax, irem reg) 0 2839 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2840 const int min_int = 0x80000000; 2841 Label normal_case, special_case; 2842 2843 // check for special case 2844 cmpl(rax, min_int); 2845 jcc(Assembler::notEqual, normal_case); 2846 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2847 cmpl(reg, -1); 2848 jcc(Assembler::equal, special_case); 2849 2850 // handle normal case 2851 bind(normal_case); 2852 cdql(); 2853 int idivl_offset = offset(); 2854 idivl(reg); 2855 2856 // normal and special case exit 2857 bind(special_case); 2858 2859 return idivl_offset; 2860 } 2861 2862 2863 2864 void MacroAssembler::decrementl(Register reg, int value) { 2865 if (value == min_jint) {subl(reg, value) ; return; } 2866 if (value < 0) { incrementl(reg, -value); return; } 2867 if (value == 0) { ; return; } 2868 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2869 /* else */ { subl(reg, value) ; return; } 2870 } 2871 2872 void MacroAssembler::decrementl(Address dst, int value) { 2873 if (value == min_jint) {subl(dst, value) ; return; } 2874 if (value < 0) { incrementl(dst, -value); return; } 2875 if (value == 0) { ; return; } 2876 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2877 /* else */ { subl(dst, value) ; return; } 2878 } 2879 2880 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2881 assert (shift_value > 0, "illegal shift value"); 2882 Label _is_positive; 2883 testl (reg, reg); 2884 jcc (Assembler::positive, _is_positive); 2885 int offset = (1 << shift_value) - 1 ; 2886 2887 if (offset == 1) { 2888 incrementl(reg); 2889 } else { 2890 addl(reg, offset); 2891 } 2892 2893 bind (_is_positive); 2894 sarl(reg, shift_value); 2895 } 2896 2897 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2898 if (reachable(src)) { 2899 Assembler::divsd(dst, as_Address(src)); 2900 } else { 2901 lea(rscratch1, src); 2902 Assembler::divsd(dst, Address(rscratch1, 0)); 2903 } 2904 } 2905 2906 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2907 if (reachable(src)) { 2908 Assembler::divss(dst, as_Address(src)); 2909 } else { 2910 lea(rscratch1, src); 2911 Assembler::divss(dst, Address(rscratch1, 0)); 2912 } 2913 } 2914 2915 // !defined(COMPILER2) is because of stupid core builds 2916 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2917 void MacroAssembler::empty_FPU_stack() { 2918 if (VM_Version::supports_mmx()) { 2919 emms(); 2920 } else { 2921 for (int i = 8; i-- > 0; ) ffree(i); 2922 } 2923 } 2924 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2925 2926 2927 // Defines obj, preserves var_size_in_bytes 2928 void MacroAssembler::eden_allocate(Register obj, 2929 Register var_size_in_bytes, 2930 int con_size_in_bytes, 2931 Register t1, 2932 Label& slow_case) { 2933 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2934 assert_different_registers(obj, var_size_in_bytes, t1); 2935 if (!Universe::heap()->supports_inline_contig_alloc()) { 2936 jmp(slow_case); 2937 } else { 2938 Register end = t1; 2939 Label retry; 2940 bind(retry); 2941 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2942 movptr(obj, heap_top); 2943 if (var_size_in_bytes == noreg) { 2944 lea(end, Address(obj, con_size_in_bytes)); 2945 } else { 2946 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2947 } 2948 // if end < obj then we wrapped around => object too long => slow case 2949 cmpptr(end, obj); 2950 jcc(Assembler::below, slow_case); 2951 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2952 jcc(Assembler::above, slow_case); 2953 // Compare obj with the top addr, and if still equal, store the new top addr in 2954 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2955 // it otherwise. Use lock prefix for atomicity on MPs. 2956 locked_cmpxchgptr(end, heap_top); 2957 jcc(Assembler::notEqual, retry); 2958 } 2959 } 2960 2961 void MacroAssembler::enter() { 2962 push(rbp); 2963 mov(rbp, rsp); 2964 } 2965 2966 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2967 void MacroAssembler::fat_nop() { 2968 if (UseAddressNop) { 2969 addr_nop_5(); 2970 } else { 2971 emit_int8(0x26); // es: 2972 emit_int8(0x2e); // cs: 2973 emit_int8(0x64); // fs: 2974 emit_int8(0x65); // gs: 2975 emit_int8((unsigned char)0x90); 2976 } 2977 } 2978 2979 void MacroAssembler::fcmp(Register tmp) { 2980 fcmp(tmp, 1, true, true); 2981 } 2982 2983 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2984 assert(!pop_right || pop_left, "usage error"); 2985 if (VM_Version::supports_cmov()) { 2986 assert(tmp == noreg, "unneeded temp"); 2987 if (pop_left) { 2988 fucomip(index); 2989 } else { 2990 fucomi(index); 2991 } 2992 if (pop_right) { 2993 fpop(); 2994 } 2995 } else { 2996 assert(tmp != noreg, "need temp"); 2997 if (pop_left) { 2998 if (pop_right) { 2999 fcompp(); 3000 } else { 3001 fcomp(index); 3002 } 3003 } else { 3004 fcom(index); 3005 } 3006 // convert FPU condition into eflags condition via rax, 3007 save_rax(tmp); 3008 fwait(); fnstsw_ax(); 3009 sahf(); 3010 restore_rax(tmp); 3011 } 3012 // condition codes set as follows: 3013 // 3014 // CF (corresponds to C0) if x < y 3015 // PF (corresponds to C2) if unordered 3016 // ZF (corresponds to C3) if x = y 3017 } 3018 3019 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3020 fcmp2int(dst, unordered_is_less, 1, true, true); 3021 } 3022 3023 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3024 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3025 Label L; 3026 if (unordered_is_less) { 3027 movl(dst, -1); 3028 jcc(Assembler::parity, L); 3029 jcc(Assembler::below , L); 3030 movl(dst, 0); 3031 jcc(Assembler::equal , L); 3032 increment(dst); 3033 } else { // unordered is greater 3034 movl(dst, 1); 3035 jcc(Assembler::parity, L); 3036 jcc(Assembler::above , L); 3037 movl(dst, 0); 3038 jcc(Assembler::equal , L); 3039 decrementl(dst); 3040 } 3041 bind(L); 3042 } 3043 3044 void MacroAssembler::fld_d(AddressLiteral src) { 3045 fld_d(as_Address(src)); 3046 } 3047 3048 void MacroAssembler::fld_s(AddressLiteral src) { 3049 fld_s(as_Address(src)); 3050 } 3051 3052 void MacroAssembler::fld_x(AddressLiteral src) { 3053 Assembler::fld_x(as_Address(src)); 3054 } 3055 3056 void MacroAssembler::fldcw(AddressLiteral src) { 3057 Assembler::fldcw(as_Address(src)); 3058 } 3059 3060 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3061 if (reachable(src)) { 3062 Assembler::mulpd(dst, as_Address(src)); 3063 } else { 3064 lea(rscratch1, src); 3065 Assembler::mulpd(dst, Address(rscratch1, 0)); 3066 } 3067 } 3068 3069 void MacroAssembler::increase_precision() { 3070 subptr(rsp, BytesPerWord); 3071 fnstcw(Address(rsp, 0)); 3072 movl(rax, Address(rsp, 0)); 3073 orl(rax, 0x300); 3074 push(rax); 3075 fldcw(Address(rsp, 0)); 3076 pop(rax); 3077 } 3078 3079 void MacroAssembler::restore_precision() { 3080 fldcw(Address(rsp, 0)); 3081 addptr(rsp, BytesPerWord); 3082 } 3083 3084 void MacroAssembler::fpop() { 3085 ffree(); 3086 fincstp(); 3087 } 3088 3089 void MacroAssembler::load_float(Address src) { 3090 if (UseSSE >= 1) { 3091 movflt(xmm0, src); 3092 } else { 3093 LP64_ONLY(ShouldNotReachHere()); 3094 NOT_LP64(fld_s(src)); 3095 } 3096 } 3097 3098 void MacroAssembler::store_float(Address dst) { 3099 if (UseSSE >= 1) { 3100 movflt(dst, xmm0); 3101 } else { 3102 LP64_ONLY(ShouldNotReachHere()); 3103 NOT_LP64(fstp_s(dst)); 3104 } 3105 } 3106 3107 void MacroAssembler::load_double(Address src) { 3108 if (UseSSE >= 2) { 3109 movdbl(xmm0, src); 3110 } else { 3111 LP64_ONLY(ShouldNotReachHere()); 3112 NOT_LP64(fld_d(src)); 3113 } 3114 } 3115 3116 void MacroAssembler::store_double(Address dst) { 3117 if (UseSSE >= 2) { 3118 movdbl(dst, xmm0); 3119 } else { 3120 LP64_ONLY(ShouldNotReachHere()); 3121 NOT_LP64(fstp_d(dst)); 3122 } 3123 } 3124 3125 void MacroAssembler::fremr(Register tmp) { 3126 save_rax(tmp); 3127 { Label L; 3128 bind(L); 3129 fprem(); 3130 fwait(); fnstsw_ax(); 3131 #ifdef _LP64 3132 testl(rax, 0x400); 3133 jcc(Assembler::notEqual, L); 3134 #else 3135 sahf(); 3136 jcc(Assembler::parity, L); 3137 #endif // _LP64 3138 } 3139 restore_rax(tmp); 3140 // Result is in ST0. 3141 // Note: fxch & fpop to get rid of ST1 3142 // (otherwise FPU stack could overflow eventually) 3143 fxch(1); 3144 fpop(); 3145 } 3146 3147 3148 void MacroAssembler::incrementl(AddressLiteral dst) { 3149 if (reachable(dst)) { 3150 incrementl(as_Address(dst)); 3151 } else { 3152 lea(rscratch1, dst); 3153 incrementl(Address(rscratch1, 0)); 3154 } 3155 } 3156 3157 void MacroAssembler::incrementl(ArrayAddress dst) { 3158 incrementl(as_Address(dst)); 3159 } 3160 3161 void MacroAssembler::incrementl(Register reg, int value) { 3162 if (value == min_jint) {addl(reg, value) ; return; } 3163 if (value < 0) { decrementl(reg, -value); return; } 3164 if (value == 0) { ; return; } 3165 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3166 /* else */ { addl(reg, value) ; return; } 3167 } 3168 3169 void MacroAssembler::incrementl(Address dst, int value) { 3170 if (value == min_jint) {addl(dst, value) ; return; } 3171 if (value < 0) { decrementl(dst, -value); return; } 3172 if (value == 0) { ; return; } 3173 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3174 /* else */ { addl(dst, value) ; return; } 3175 } 3176 3177 void MacroAssembler::jump(AddressLiteral dst) { 3178 if (reachable(dst)) { 3179 jmp_literal(dst.target(), dst.rspec()); 3180 } else { 3181 lea(rscratch1, dst); 3182 jmp(rscratch1); 3183 } 3184 } 3185 3186 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3187 if (reachable(dst)) { 3188 InstructionMark im(this); 3189 relocate(dst.reloc()); 3190 const int short_size = 2; 3191 const int long_size = 6; 3192 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3193 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3194 // 0111 tttn #8-bit disp 3195 emit_int8(0x70 | cc); 3196 emit_int8((offs - short_size) & 0xFF); 3197 } else { 3198 // 0000 1111 1000 tttn #32-bit disp 3199 emit_int8(0x0F); 3200 emit_int8((unsigned char)(0x80 | cc)); 3201 emit_int32(offs - long_size); 3202 } 3203 } else { 3204 #ifdef ASSERT 3205 warning("reversing conditional branch"); 3206 #endif /* ASSERT */ 3207 Label skip; 3208 jccb(reverse[cc], skip); 3209 lea(rscratch1, dst); 3210 Assembler::jmp(rscratch1); 3211 bind(skip); 3212 } 3213 } 3214 3215 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3216 if (reachable(src)) { 3217 Assembler::ldmxcsr(as_Address(src)); 3218 } else { 3219 lea(rscratch1, src); 3220 Assembler::ldmxcsr(Address(rscratch1, 0)); 3221 } 3222 } 3223 3224 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3225 int off; 3226 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3227 off = offset(); 3228 movsbl(dst, src); // movsxb 3229 } else { 3230 off = load_unsigned_byte(dst, src); 3231 shll(dst, 24); 3232 sarl(dst, 24); 3233 } 3234 return off; 3235 } 3236 3237 // Note: load_signed_short used to be called load_signed_word. 3238 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3239 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3240 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3241 int MacroAssembler::load_signed_short(Register dst, Address src) { 3242 int off; 3243 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3244 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3245 // version but this is what 64bit has always done. This seems to imply 3246 // that users are only using 32bits worth. 3247 off = offset(); 3248 movswl(dst, src); // movsxw 3249 } else { 3250 off = load_unsigned_short(dst, src); 3251 shll(dst, 16); 3252 sarl(dst, 16); 3253 } 3254 return off; 3255 } 3256 3257 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3258 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3259 // and "3.9 Partial Register Penalties", p. 22). 3260 int off; 3261 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3262 off = offset(); 3263 movzbl(dst, src); // movzxb 3264 } else { 3265 xorl(dst, dst); 3266 off = offset(); 3267 movb(dst, src); 3268 } 3269 return off; 3270 } 3271 3272 // Note: load_unsigned_short used to be called load_unsigned_word. 3273 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3274 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3275 // and "3.9 Partial Register Penalties", p. 22). 3276 int off; 3277 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3278 off = offset(); 3279 movzwl(dst, src); // movzxw 3280 } else { 3281 xorl(dst, dst); 3282 off = offset(); 3283 movw(dst, src); 3284 } 3285 return off; 3286 } 3287 3288 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3289 switch (size_in_bytes) { 3290 #ifndef _LP64 3291 case 8: 3292 assert(dst2 != noreg, "second dest register required"); 3293 movl(dst, src); 3294 movl(dst2, src.plus_disp(BytesPerInt)); 3295 break; 3296 #else 3297 case 8: movq(dst, src); break; 3298 #endif 3299 case 4: movl(dst, src); break; 3300 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3301 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3302 default: ShouldNotReachHere(); 3303 } 3304 } 3305 3306 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3307 switch (size_in_bytes) { 3308 #ifndef _LP64 3309 case 8: 3310 assert(src2 != noreg, "second source register required"); 3311 movl(dst, src); 3312 movl(dst.plus_disp(BytesPerInt), src2); 3313 break; 3314 #else 3315 case 8: movq(dst, src); break; 3316 #endif 3317 case 4: movl(dst, src); break; 3318 case 2: movw(dst, src); break; 3319 case 1: movb(dst, src); break; 3320 default: ShouldNotReachHere(); 3321 } 3322 } 3323 3324 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3325 if (reachable(dst)) { 3326 movl(as_Address(dst), src); 3327 } else { 3328 lea(rscratch1, dst); 3329 movl(Address(rscratch1, 0), src); 3330 } 3331 } 3332 3333 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3334 if (reachable(src)) { 3335 movl(dst, as_Address(src)); 3336 } else { 3337 lea(rscratch1, src); 3338 movl(dst, Address(rscratch1, 0)); 3339 } 3340 } 3341 3342 // C++ bool manipulation 3343 3344 void MacroAssembler::movbool(Register dst, Address src) { 3345 if(sizeof(bool) == 1) 3346 movb(dst, src); 3347 else if(sizeof(bool) == 2) 3348 movw(dst, src); 3349 else if(sizeof(bool) == 4) 3350 movl(dst, src); 3351 else 3352 // unsupported 3353 ShouldNotReachHere(); 3354 } 3355 3356 void MacroAssembler::movbool(Address dst, bool boolconst) { 3357 if(sizeof(bool) == 1) 3358 movb(dst, (int) boolconst); 3359 else if(sizeof(bool) == 2) 3360 movw(dst, (int) boolconst); 3361 else if(sizeof(bool) == 4) 3362 movl(dst, (int) boolconst); 3363 else 3364 // unsupported 3365 ShouldNotReachHere(); 3366 } 3367 3368 void MacroAssembler::movbool(Address dst, Register src) { 3369 if(sizeof(bool) == 1) 3370 movb(dst, src); 3371 else if(sizeof(bool) == 2) 3372 movw(dst, src); 3373 else if(sizeof(bool) == 4) 3374 movl(dst, src); 3375 else 3376 // unsupported 3377 ShouldNotReachHere(); 3378 } 3379 3380 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3381 movb(as_Address(dst), src); 3382 } 3383 3384 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3385 if (reachable(src)) { 3386 movdl(dst, as_Address(src)); 3387 } else { 3388 lea(rscratch1, src); 3389 movdl(dst, Address(rscratch1, 0)); 3390 } 3391 } 3392 3393 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3394 if (reachable(src)) { 3395 movq(dst, as_Address(src)); 3396 } else { 3397 lea(rscratch1, src); 3398 movq(dst, Address(rscratch1, 0)); 3399 } 3400 } 3401 3402 void MacroAssembler::setvectmask(Register dst, Register src) { 3403 Assembler::movl(dst, 1); 3404 Assembler::shlxl(dst, dst, src); 3405 Assembler::decl(dst); 3406 Assembler::kmovdl(k1, dst); 3407 Assembler::movl(dst, src); 3408 } 3409 3410 void MacroAssembler::restorevectmask() { 3411 Assembler::knotwl(k1, k0); 3412 } 3413 3414 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3415 if (reachable(src)) { 3416 if (UseXmmLoadAndClearUpper) { 3417 movsd (dst, as_Address(src)); 3418 } else { 3419 movlpd(dst, as_Address(src)); 3420 } 3421 } else { 3422 lea(rscratch1, src); 3423 if (UseXmmLoadAndClearUpper) { 3424 movsd (dst, Address(rscratch1, 0)); 3425 } else { 3426 movlpd(dst, Address(rscratch1, 0)); 3427 } 3428 } 3429 } 3430 3431 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3432 if (reachable(src)) { 3433 movss(dst, as_Address(src)); 3434 } else { 3435 lea(rscratch1, src); 3436 movss(dst, Address(rscratch1, 0)); 3437 } 3438 } 3439 3440 void MacroAssembler::movptr(Register dst, Register src) { 3441 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3442 } 3443 3444 void MacroAssembler::movptr(Register dst, Address src) { 3445 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3446 } 3447 3448 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3449 void MacroAssembler::movptr(Register dst, intptr_t src) { 3450 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3451 } 3452 3453 void MacroAssembler::movptr(Address dst, Register src) { 3454 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3455 } 3456 3457 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3458 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3459 Assembler::vextractf32x4(dst, src, 0); 3460 } else { 3461 Assembler::movdqu(dst, src); 3462 } 3463 } 3464 3465 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3466 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3467 Assembler::vinsertf32x4(dst, dst, src, 0); 3468 } else { 3469 Assembler::movdqu(dst, src); 3470 } 3471 } 3472 3473 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3474 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3475 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3476 } else { 3477 Assembler::movdqu(dst, src); 3478 } 3479 } 3480 3481 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3482 if (reachable(src)) { 3483 movdqu(dst, as_Address(src)); 3484 } else { 3485 lea(rscratch1, src); 3486 movdqu(dst, Address(rscratch1, 0)); 3487 } 3488 } 3489 3490 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3491 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3492 vextractf64x4_low(dst, src); 3493 } else { 3494 Assembler::vmovdqu(dst, src); 3495 } 3496 } 3497 3498 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3499 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3500 vinsertf64x4_low(dst, src); 3501 } else { 3502 Assembler::vmovdqu(dst, src); 3503 } 3504 } 3505 3506 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3507 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3508 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3509 } 3510 else { 3511 Assembler::vmovdqu(dst, src); 3512 } 3513 } 3514 3515 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3516 if (reachable(src)) { 3517 vmovdqu(dst, as_Address(src)); 3518 } 3519 else { 3520 lea(rscratch1, src); 3521 vmovdqu(dst, Address(rscratch1, 0)); 3522 } 3523 } 3524 3525 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3526 if (reachable(src)) { 3527 Assembler::movdqa(dst, as_Address(src)); 3528 } else { 3529 lea(rscratch1, src); 3530 Assembler::movdqa(dst, Address(rscratch1, 0)); 3531 } 3532 } 3533 3534 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3535 if (reachable(src)) { 3536 Assembler::movsd(dst, as_Address(src)); 3537 } else { 3538 lea(rscratch1, src); 3539 Assembler::movsd(dst, Address(rscratch1, 0)); 3540 } 3541 } 3542 3543 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3544 if (reachable(src)) { 3545 Assembler::movss(dst, as_Address(src)); 3546 } else { 3547 lea(rscratch1, src); 3548 Assembler::movss(dst, Address(rscratch1, 0)); 3549 } 3550 } 3551 3552 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3553 if (reachable(src)) { 3554 Assembler::mulsd(dst, as_Address(src)); 3555 } else { 3556 lea(rscratch1, src); 3557 Assembler::mulsd(dst, Address(rscratch1, 0)); 3558 } 3559 } 3560 3561 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3562 if (reachable(src)) { 3563 Assembler::mulss(dst, as_Address(src)); 3564 } else { 3565 lea(rscratch1, src); 3566 Assembler::mulss(dst, Address(rscratch1, 0)); 3567 } 3568 } 3569 3570 void MacroAssembler::null_check(Register reg, int offset) { 3571 if (needs_explicit_null_check(offset)) { 3572 // provoke OS NULL exception if reg = NULL by 3573 // accessing M[reg] w/o changing any (non-CC) registers 3574 // NOTE: cmpl is plenty here to provoke a segv 3575 cmpptr(rax, Address(reg, 0)); 3576 // Note: should probably use testl(rax, Address(reg, 0)); 3577 // may be shorter code (however, this version of 3578 // testl needs to be implemented first) 3579 } else { 3580 // nothing to do, (later) access of M[reg + offset] 3581 // will provoke OS NULL exception if reg = NULL 3582 } 3583 } 3584 3585 void MacroAssembler::os_breakpoint() { 3586 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3587 // (e.g., MSVC can't call ps() otherwise) 3588 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3589 } 3590 3591 #ifdef _LP64 3592 #define XSTATE_BV 0x200 3593 #endif 3594 3595 void MacroAssembler::pop_CPU_state() { 3596 pop_FPU_state(); 3597 pop_IU_state(); 3598 } 3599 3600 void MacroAssembler::pop_FPU_state() { 3601 #ifndef _LP64 3602 frstor(Address(rsp, 0)); 3603 #else 3604 fxrstor(Address(rsp, 0)); 3605 #endif 3606 addptr(rsp, FPUStateSizeInWords * wordSize); 3607 } 3608 3609 void MacroAssembler::pop_IU_state() { 3610 popa(); 3611 LP64_ONLY(addq(rsp, 8)); 3612 popf(); 3613 } 3614 3615 // Save Integer and Float state 3616 // Warning: Stack must be 16 byte aligned (64bit) 3617 void MacroAssembler::push_CPU_state() { 3618 push_IU_state(); 3619 push_FPU_state(); 3620 } 3621 3622 void MacroAssembler::push_FPU_state() { 3623 subptr(rsp, FPUStateSizeInWords * wordSize); 3624 #ifndef _LP64 3625 fnsave(Address(rsp, 0)); 3626 fwait(); 3627 #else 3628 fxsave(Address(rsp, 0)); 3629 #endif // LP64 3630 } 3631 3632 void MacroAssembler::push_IU_state() { 3633 // Push flags first because pusha kills them 3634 pushf(); 3635 // Make sure rsp stays 16-byte aligned 3636 LP64_ONLY(subq(rsp, 8)); 3637 pusha(); 3638 } 3639 3640 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 3641 // determine java_thread register 3642 if (!java_thread->is_valid()) { 3643 java_thread = rdi; 3644 get_thread(java_thread); 3645 } 3646 // we must set sp to zero to clear frame 3647 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3648 if (clear_fp) { 3649 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3650 } 3651 3652 if (clear_pc) 3653 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3654 3655 } 3656 3657 void MacroAssembler::restore_rax(Register tmp) { 3658 if (tmp == noreg) pop(rax); 3659 else if (tmp != rax) mov(rax, tmp); 3660 } 3661 3662 void MacroAssembler::round_to(Register reg, int modulus) { 3663 addptr(reg, modulus - 1); 3664 andptr(reg, -modulus); 3665 } 3666 3667 void MacroAssembler::save_rax(Register tmp) { 3668 if (tmp == noreg) push(rax); 3669 else if (tmp != rax) mov(tmp, rax); 3670 } 3671 3672 // Write serialization page so VM thread can do a pseudo remote membar. 3673 // We use the current thread pointer to calculate a thread specific 3674 // offset to write to within the page. This minimizes bus traffic 3675 // due to cache line collision. 3676 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3677 movl(tmp, thread); 3678 shrl(tmp, os::get_serialize_page_shift_count()); 3679 andl(tmp, (os::vm_page_size() - sizeof(int))); 3680 3681 Address index(noreg, tmp, Address::times_1); 3682 ExternalAddress page(os::get_memory_serialize_page()); 3683 3684 // Size of store must match masking code above 3685 movl(as_Address(ArrayAddress(page, index)), tmp); 3686 } 3687 3688 // Calls to C land 3689 // 3690 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3691 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3692 // has to be reset to 0. This is required to allow proper stack traversal. 3693 void MacroAssembler::set_last_Java_frame(Register java_thread, 3694 Register last_java_sp, 3695 Register last_java_fp, 3696 address last_java_pc) { 3697 // determine java_thread register 3698 if (!java_thread->is_valid()) { 3699 java_thread = rdi; 3700 get_thread(java_thread); 3701 } 3702 // determine last_java_sp register 3703 if (!last_java_sp->is_valid()) { 3704 last_java_sp = rsp; 3705 } 3706 3707 // last_java_fp is optional 3708 3709 if (last_java_fp->is_valid()) { 3710 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3711 } 3712 3713 // last_java_pc is optional 3714 3715 if (last_java_pc != NULL) { 3716 lea(Address(java_thread, 3717 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3718 InternalAddress(last_java_pc)); 3719 3720 } 3721 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3722 } 3723 3724 void MacroAssembler::shlptr(Register dst, int imm8) { 3725 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3726 } 3727 3728 void MacroAssembler::shrptr(Register dst, int imm8) { 3729 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3730 } 3731 3732 void MacroAssembler::sign_extend_byte(Register reg) { 3733 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3734 movsbl(reg, reg); // movsxb 3735 } else { 3736 shll(reg, 24); 3737 sarl(reg, 24); 3738 } 3739 } 3740 3741 void MacroAssembler::sign_extend_short(Register reg) { 3742 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3743 movswl(reg, reg); // movsxw 3744 } else { 3745 shll(reg, 16); 3746 sarl(reg, 16); 3747 } 3748 } 3749 3750 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3751 assert(reachable(src), "Address should be reachable"); 3752 testl(dst, as_Address(src)); 3753 } 3754 3755 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3756 int dst_enc = dst->encoding(); 3757 int src_enc = src->encoding(); 3758 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3759 Assembler::pcmpeqb(dst, src); 3760 } else if ((dst_enc < 16) && (src_enc < 16)) { 3761 Assembler::pcmpeqb(dst, src); 3762 } else if (src_enc < 16) { 3763 subptr(rsp, 64); 3764 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3765 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3766 Assembler::pcmpeqb(xmm0, src); 3767 movdqu(dst, xmm0); 3768 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3769 addptr(rsp, 64); 3770 } else if (dst_enc < 16) { 3771 subptr(rsp, 64); 3772 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3773 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3774 Assembler::pcmpeqb(dst, xmm0); 3775 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3776 addptr(rsp, 64); 3777 } else { 3778 subptr(rsp, 64); 3779 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3780 subptr(rsp, 64); 3781 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3782 movdqu(xmm0, src); 3783 movdqu(xmm1, dst); 3784 Assembler::pcmpeqb(xmm1, xmm0); 3785 movdqu(dst, xmm1); 3786 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3787 addptr(rsp, 64); 3788 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3789 addptr(rsp, 64); 3790 } 3791 } 3792 3793 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3794 int dst_enc = dst->encoding(); 3795 int src_enc = src->encoding(); 3796 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3797 Assembler::pcmpeqw(dst, src); 3798 } else if ((dst_enc < 16) && (src_enc < 16)) { 3799 Assembler::pcmpeqw(dst, src); 3800 } else if (src_enc < 16) { 3801 subptr(rsp, 64); 3802 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3803 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3804 Assembler::pcmpeqw(xmm0, src); 3805 movdqu(dst, xmm0); 3806 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3807 addptr(rsp, 64); 3808 } else if (dst_enc < 16) { 3809 subptr(rsp, 64); 3810 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3811 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3812 Assembler::pcmpeqw(dst, xmm0); 3813 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3814 addptr(rsp, 64); 3815 } else { 3816 subptr(rsp, 64); 3817 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3818 subptr(rsp, 64); 3819 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3820 movdqu(xmm0, src); 3821 movdqu(xmm1, dst); 3822 Assembler::pcmpeqw(xmm1, xmm0); 3823 movdqu(dst, xmm1); 3824 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3825 addptr(rsp, 64); 3826 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3827 addptr(rsp, 64); 3828 } 3829 } 3830 3831 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3832 int dst_enc = dst->encoding(); 3833 if (dst_enc < 16) { 3834 Assembler::pcmpestri(dst, src, imm8); 3835 } else { 3836 subptr(rsp, 64); 3837 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3838 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3839 Assembler::pcmpestri(xmm0, src, imm8); 3840 movdqu(dst, xmm0); 3841 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3842 addptr(rsp, 64); 3843 } 3844 } 3845 3846 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3847 int dst_enc = dst->encoding(); 3848 int src_enc = src->encoding(); 3849 if ((dst_enc < 16) && (src_enc < 16)) { 3850 Assembler::pcmpestri(dst, src, imm8); 3851 } else if (src_enc < 16) { 3852 subptr(rsp, 64); 3853 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3854 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3855 Assembler::pcmpestri(xmm0, src, imm8); 3856 movdqu(dst, xmm0); 3857 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3858 addptr(rsp, 64); 3859 } else if (dst_enc < 16) { 3860 subptr(rsp, 64); 3861 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3862 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3863 Assembler::pcmpestri(dst, xmm0, imm8); 3864 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3865 addptr(rsp, 64); 3866 } else { 3867 subptr(rsp, 64); 3868 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3869 subptr(rsp, 64); 3870 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3871 movdqu(xmm0, src); 3872 movdqu(xmm1, dst); 3873 Assembler::pcmpestri(xmm1, xmm0, imm8); 3874 movdqu(dst, xmm1); 3875 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3876 addptr(rsp, 64); 3877 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3878 addptr(rsp, 64); 3879 } 3880 } 3881 3882 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3883 int dst_enc = dst->encoding(); 3884 int src_enc = src->encoding(); 3885 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3886 Assembler::pmovzxbw(dst, src); 3887 } else if ((dst_enc < 16) && (src_enc < 16)) { 3888 Assembler::pmovzxbw(dst, src); 3889 } else if (src_enc < 16) { 3890 subptr(rsp, 64); 3891 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3892 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3893 Assembler::pmovzxbw(xmm0, src); 3894 movdqu(dst, xmm0); 3895 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3896 addptr(rsp, 64); 3897 } else if (dst_enc < 16) { 3898 subptr(rsp, 64); 3899 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3900 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3901 Assembler::pmovzxbw(dst, xmm0); 3902 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3903 addptr(rsp, 64); 3904 } else { 3905 subptr(rsp, 64); 3906 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3907 subptr(rsp, 64); 3908 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3909 movdqu(xmm0, src); 3910 movdqu(xmm1, dst); 3911 Assembler::pmovzxbw(xmm1, xmm0); 3912 movdqu(dst, xmm1); 3913 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3914 addptr(rsp, 64); 3915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3916 addptr(rsp, 64); 3917 } 3918 } 3919 3920 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3921 int dst_enc = dst->encoding(); 3922 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3923 Assembler::pmovzxbw(dst, src); 3924 } else if (dst_enc < 16) { 3925 Assembler::pmovzxbw(dst, src); 3926 } else { 3927 subptr(rsp, 64); 3928 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3929 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3930 Assembler::pmovzxbw(xmm0, src); 3931 movdqu(dst, xmm0); 3932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3933 addptr(rsp, 64); 3934 } 3935 } 3936 3937 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3938 int src_enc = src->encoding(); 3939 if (src_enc < 16) { 3940 Assembler::pmovmskb(dst, src); 3941 } else { 3942 subptr(rsp, 64); 3943 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3944 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3945 Assembler::pmovmskb(dst, xmm0); 3946 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3947 addptr(rsp, 64); 3948 } 3949 } 3950 3951 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3952 int dst_enc = dst->encoding(); 3953 int src_enc = src->encoding(); 3954 if ((dst_enc < 16) && (src_enc < 16)) { 3955 Assembler::ptest(dst, src); 3956 } else if (src_enc < 16) { 3957 subptr(rsp, 64); 3958 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3959 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3960 Assembler::ptest(xmm0, src); 3961 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3962 addptr(rsp, 64); 3963 } else if (dst_enc < 16) { 3964 subptr(rsp, 64); 3965 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3966 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3967 Assembler::ptest(dst, xmm0); 3968 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3969 addptr(rsp, 64); 3970 } else { 3971 subptr(rsp, 64); 3972 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3973 subptr(rsp, 64); 3974 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3975 movdqu(xmm0, src); 3976 movdqu(xmm1, dst); 3977 Assembler::ptest(xmm1, xmm0); 3978 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3979 addptr(rsp, 64); 3980 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3981 addptr(rsp, 64); 3982 } 3983 } 3984 3985 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 3986 if (reachable(src)) { 3987 Assembler::sqrtsd(dst, as_Address(src)); 3988 } else { 3989 lea(rscratch1, src); 3990 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 3991 } 3992 } 3993 3994 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 3995 if (reachable(src)) { 3996 Assembler::sqrtss(dst, as_Address(src)); 3997 } else { 3998 lea(rscratch1, src); 3999 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4000 } 4001 } 4002 4003 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4004 if (reachable(src)) { 4005 Assembler::subsd(dst, as_Address(src)); 4006 } else { 4007 lea(rscratch1, src); 4008 Assembler::subsd(dst, Address(rscratch1, 0)); 4009 } 4010 } 4011 4012 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4013 if (reachable(src)) { 4014 Assembler::subss(dst, as_Address(src)); 4015 } else { 4016 lea(rscratch1, src); 4017 Assembler::subss(dst, Address(rscratch1, 0)); 4018 } 4019 } 4020 4021 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4022 if (reachable(src)) { 4023 Assembler::ucomisd(dst, as_Address(src)); 4024 } else { 4025 lea(rscratch1, src); 4026 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4027 } 4028 } 4029 4030 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4031 if (reachable(src)) { 4032 Assembler::ucomiss(dst, as_Address(src)); 4033 } else { 4034 lea(rscratch1, src); 4035 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4036 } 4037 } 4038 4039 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4040 // Used in sign-bit flipping with aligned address. 4041 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4042 if (reachable(src)) { 4043 Assembler::xorpd(dst, as_Address(src)); 4044 } else { 4045 lea(rscratch1, src); 4046 Assembler::xorpd(dst, Address(rscratch1, 0)); 4047 } 4048 } 4049 4050 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4051 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4052 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4053 } 4054 else { 4055 Assembler::xorpd(dst, src); 4056 } 4057 } 4058 4059 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4060 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4061 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4062 } else { 4063 Assembler::xorps(dst, src); 4064 } 4065 } 4066 4067 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4068 // Used in sign-bit flipping with aligned address. 4069 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4070 if (reachable(src)) { 4071 Assembler::xorps(dst, as_Address(src)); 4072 } else { 4073 lea(rscratch1, src); 4074 Assembler::xorps(dst, Address(rscratch1, 0)); 4075 } 4076 } 4077 4078 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4079 // Used in sign-bit flipping with aligned address. 4080 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4081 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4082 if (reachable(src)) { 4083 Assembler::pshufb(dst, as_Address(src)); 4084 } else { 4085 lea(rscratch1, src); 4086 Assembler::pshufb(dst, Address(rscratch1, 0)); 4087 } 4088 } 4089 4090 // AVX 3-operands instructions 4091 4092 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4093 if (reachable(src)) { 4094 vaddsd(dst, nds, as_Address(src)); 4095 } else { 4096 lea(rscratch1, src); 4097 vaddsd(dst, nds, Address(rscratch1, 0)); 4098 } 4099 } 4100 4101 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4102 if (reachable(src)) { 4103 vaddss(dst, nds, as_Address(src)); 4104 } else { 4105 lea(rscratch1, src); 4106 vaddss(dst, nds, Address(rscratch1, 0)); 4107 } 4108 } 4109 4110 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4111 int dst_enc = dst->encoding(); 4112 int nds_enc = nds->encoding(); 4113 int src_enc = src->encoding(); 4114 if ((dst_enc < 16) && (nds_enc < 16)) { 4115 vandps(dst, nds, negate_field, vector_len); 4116 } else if ((src_enc < 16) && (dst_enc < 16)) { 4117 movss(src, nds); 4118 vandps(dst, src, negate_field, vector_len); 4119 } else if (src_enc < 16) { 4120 movss(src, nds); 4121 vandps(src, src, negate_field, vector_len); 4122 movss(dst, src); 4123 } else if (dst_enc < 16) { 4124 movdqu(src, xmm0); 4125 movss(xmm0, nds); 4126 vandps(dst, xmm0, negate_field, vector_len); 4127 movdqu(xmm0, src); 4128 } else if (nds_enc < 16) { 4129 movdqu(src, xmm0); 4130 vandps(xmm0, nds, negate_field, vector_len); 4131 movss(dst, xmm0); 4132 movdqu(xmm0, src); 4133 } else { 4134 movdqu(src, xmm0); 4135 movss(xmm0, nds); 4136 vandps(xmm0, xmm0, negate_field, vector_len); 4137 movss(dst, xmm0); 4138 movdqu(xmm0, src); 4139 } 4140 } 4141 4142 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4143 int dst_enc = dst->encoding(); 4144 int nds_enc = nds->encoding(); 4145 int src_enc = src->encoding(); 4146 if ((dst_enc < 16) && (nds_enc < 16)) { 4147 vandpd(dst, nds, negate_field, vector_len); 4148 } else if ((src_enc < 16) && (dst_enc < 16)) { 4149 movsd(src, nds); 4150 vandpd(dst, src, negate_field, vector_len); 4151 } else if (src_enc < 16) { 4152 movsd(src, nds); 4153 vandpd(src, src, negate_field, vector_len); 4154 movsd(dst, src); 4155 } else if (dst_enc < 16) { 4156 movdqu(src, xmm0); 4157 movsd(xmm0, nds); 4158 vandpd(dst, xmm0, negate_field, vector_len); 4159 movdqu(xmm0, src); 4160 } else if (nds_enc < 16) { 4161 movdqu(src, xmm0); 4162 vandpd(xmm0, nds, negate_field, vector_len); 4163 movsd(dst, xmm0); 4164 movdqu(xmm0, src); 4165 } else { 4166 movdqu(src, xmm0); 4167 movsd(xmm0, nds); 4168 vandpd(xmm0, xmm0, negate_field, vector_len); 4169 movsd(dst, xmm0); 4170 movdqu(xmm0, src); 4171 } 4172 } 4173 4174 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4175 int dst_enc = dst->encoding(); 4176 int nds_enc = nds->encoding(); 4177 int src_enc = src->encoding(); 4178 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4179 Assembler::vpaddb(dst, nds, src, vector_len); 4180 } else if ((dst_enc < 16) && (src_enc < 16)) { 4181 Assembler::vpaddb(dst, dst, src, vector_len); 4182 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4183 // use nds as scratch for src 4184 evmovdqul(nds, src, Assembler::AVX_512bit); 4185 Assembler::vpaddb(dst, dst, nds, vector_len); 4186 } else if ((src_enc < 16) && (nds_enc < 16)) { 4187 // use nds as scratch for dst 4188 evmovdqul(nds, dst, Assembler::AVX_512bit); 4189 Assembler::vpaddb(nds, nds, src, vector_len); 4190 evmovdqul(dst, nds, Assembler::AVX_512bit); 4191 } else if (dst_enc < 16) { 4192 // use nds as scatch for xmm0 to hold src 4193 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4194 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4195 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4196 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4197 } else { 4198 // worse case scenario, all regs are in the upper bank 4199 subptr(rsp, 64); 4200 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4201 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4202 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4203 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4204 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4205 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4206 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4207 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4208 addptr(rsp, 64); 4209 } 4210 } 4211 4212 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4213 int dst_enc = dst->encoding(); 4214 int nds_enc = nds->encoding(); 4215 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4216 Assembler::vpaddb(dst, nds, src, vector_len); 4217 } else if (dst_enc < 16) { 4218 Assembler::vpaddb(dst, dst, src, vector_len); 4219 } else if (nds_enc < 16) { 4220 // implies dst_enc in upper bank with src as scratch 4221 evmovdqul(nds, dst, Assembler::AVX_512bit); 4222 Assembler::vpaddb(nds, nds, src, vector_len); 4223 evmovdqul(dst, nds, Assembler::AVX_512bit); 4224 } else { 4225 // worse case scenario, all regs in upper bank 4226 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4227 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4228 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4229 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4230 } 4231 } 4232 4233 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4234 int dst_enc = dst->encoding(); 4235 int nds_enc = nds->encoding(); 4236 int src_enc = src->encoding(); 4237 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4238 Assembler::vpaddw(dst, nds, src, vector_len); 4239 } else if ((dst_enc < 16) && (src_enc < 16)) { 4240 Assembler::vpaddw(dst, dst, src, vector_len); 4241 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4242 // use nds as scratch for src 4243 evmovdqul(nds, src, Assembler::AVX_512bit); 4244 Assembler::vpaddw(dst, dst, nds, vector_len); 4245 } else if ((src_enc < 16) && (nds_enc < 16)) { 4246 // use nds as scratch for dst 4247 evmovdqul(nds, dst, Assembler::AVX_512bit); 4248 Assembler::vpaddw(nds, nds, src, vector_len); 4249 evmovdqul(dst, nds, Assembler::AVX_512bit); 4250 } else if (dst_enc < 16) { 4251 // use nds as scatch for xmm0 to hold src 4252 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4253 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4254 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4255 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4256 } else { 4257 // worse case scenario, all regs are in the upper bank 4258 subptr(rsp, 64); 4259 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4260 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4261 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4262 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4263 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4264 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4265 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4266 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4267 addptr(rsp, 64); 4268 } 4269 } 4270 4271 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4272 int dst_enc = dst->encoding(); 4273 int nds_enc = nds->encoding(); 4274 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4275 Assembler::vpaddw(dst, nds, src, vector_len); 4276 } else if (dst_enc < 16) { 4277 Assembler::vpaddw(dst, dst, src, vector_len); 4278 } else if (nds_enc < 16) { 4279 // implies dst_enc in upper bank with src as scratch 4280 evmovdqul(nds, dst, Assembler::AVX_512bit); 4281 Assembler::vpaddw(nds, nds, src, vector_len); 4282 evmovdqul(dst, nds, Assembler::AVX_512bit); 4283 } else { 4284 // worse case scenario, all regs in upper bank 4285 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4286 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4287 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4288 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4289 } 4290 } 4291 4292 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4293 int dst_enc = dst->encoding(); 4294 int src_enc = src->encoding(); 4295 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4296 Assembler::vpbroadcastw(dst, src); 4297 } else if ((dst_enc < 16) && (src_enc < 16)) { 4298 Assembler::vpbroadcastw(dst, src); 4299 } else if (src_enc < 16) { 4300 subptr(rsp, 64); 4301 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4302 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4303 Assembler::vpbroadcastw(xmm0, src); 4304 movdqu(dst, xmm0); 4305 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4306 addptr(rsp, 64); 4307 } else if (dst_enc < 16) { 4308 subptr(rsp, 64); 4309 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4310 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4311 Assembler::vpbroadcastw(dst, xmm0); 4312 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4313 addptr(rsp, 64); 4314 } else { 4315 subptr(rsp, 64); 4316 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4317 subptr(rsp, 64); 4318 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4319 movdqu(xmm0, src); 4320 movdqu(xmm1, dst); 4321 Assembler::vpbroadcastw(xmm1, xmm0); 4322 movdqu(dst, xmm1); 4323 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4324 addptr(rsp, 64); 4325 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4326 addptr(rsp, 64); 4327 } 4328 } 4329 4330 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4331 int dst_enc = dst->encoding(); 4332 int nds_enc = nds->encoding(); 4333 int src_enc = src->encoding(); 4334 assert(dst_enc == nds_enc, ""); 4335 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4336 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4337 } else if ((dst_enc < 16) && (src_enc < 16)) { 4338 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4339 } else if (src_enc < 16) { 4340 subptr(rsp, 64); 4341 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4342 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4343 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4344 movdqu(dst, xmm0); 4345 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4346 addptr(rsp, 64); 4347 } else if (dst_enc < 16) { 4348 subptr(rsp, 64); 4349 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4350 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4351 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4352 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4353 addptr(rsp, 64); 4354 } else { 4355 subptr(rsp, 64); 4356 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4357 subptr(rsp, 64); 4358 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4359 movdqu(xmm0, src); 4360 movdqu(xmm1, dst); 4361 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4362 movdqu(dst, xmm1); 4363 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4364 addptr(rsp, 64); 4365 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4366 addptr(rsp, 64); 4367 } 4368 } 4369 4370 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4371 int dst_enc = dst->encoding(); 4372 int nds_enc = nds->encoding(); 4373 int src_enc = src->encoding(); 4374 assert(dst_enc == nds_enc, ""); 4375 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4376 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4377 } else if ((dst_enc < 16) && (src_enc < 16)) { 4378 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4379 } else if (src_enc < 16) { 4380 subptr(rsp, 64); 4381 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4382 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4383 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4384 movdqu(dst, xmm0); 4385 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4386 addptr(rsp, 64); 4387 } else if (dst_enc < 16) { 4388 subptr(rsp, 64); 4389 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4390 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4391 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4392 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4393 addptr(rsp, 64); 4394 } else { 4395 subptr(rsp, 64); 4396 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4397 subptr(rsp, 64); 4398 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4399 movdqu(xmm0, src); 4400 movdqu(xmm1, dst); 4401 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4402 movdqu(dst, xmm1); 4403 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4404 addptr(rsp, 64); 4405 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4406 addptr(rsp, 64); 4407 } 4408 } 4409 4410 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4411 int dst_enc = dst->encoding(); 4412 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4413 Assembler::vpmovzxbw(dst, src, vector_len); 4414 } else if (dst_enc < 16) { 4415 Assembler::vpmovzxbw(dst, src, vector_len); 4416 } else { 4417 subptr(rsp, 64); 4418 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4419 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4420 Assembler::vpmovzxbw(xmm0, src, vector_len); 4421 movdqu(dst, xmm0); 4422 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4423 addptr(rsp, 64); 4424 } 4425 } 4426 4427 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4428 int src_enc = src->encoding(); 4429 if (src_enc < 16) { 4430 Assembler::vpmovmskb(dst, src); 4431 } else { 4432 subptr(rsp, 64); 4433 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4434 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4435 Assembler::vpmovmskb(dst, xmm0); 4436 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4437 addptr(rsp, 64); 4438 } 4439 } 4440 4441 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4442 int dst_enc = dst->encoding(); 4443 int nds_enc = nds->encoding(); 4444 int src_enc = src->encoding(); 4445 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4446 Assembler::vpmullw(dst, nds, src, vector_len); 4447 } else if ((dst_enc < 16) && (src_enc < 16)) { 4448 Assembler::vpmullw(dst, dst, src, vector_len); 4449 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4450 // use nds as scratch for src 4451 evmovdqul(nds, src, Assembler::AVX_512bit); 4452 Assembler::vpmullw(dst, dst, nds, vector_len); 4453 } else if ((src_enc < 16) && (nds_enc < 16)) { 4454 // use nds as scratch for dst 4455 evmovdqul(nds, dst, Assembler::AVX_512bit); 4456 Assembler::vpmullw(nds, nds, src, vector_len); 4457 evmovdqul(dst, nds, Assembler::AVX_512bit); 4458 } else if (dst_enc < 16) { 4459 // use nds as scatch for xmm0 to hold src 4460 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4461 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4462 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4463 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4464 } else { 4465 // worse case scenario, all regs are in the upper bank 4466 subptr(rsp, 64); 4467 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4468 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4469 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4470 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4471 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4472 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4473 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4474 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4475 addptr(rsp, 64); 4476 } 4477 } 4478 4479 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4480 int dst_enc = dst->encoding(); 4481 int nds_enc = nds->encoding(); 4482 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4483 Assembler::vpmullw(dst, nds, src, vector_len); 4484 } else if (dst_enc < 16) { 4485 Assembler::vpmullw(dst, dst, src, vector_len); 4486 } else if (nds_enc < 16) { 4487 // implies dst_enc in upper bank with src as scratch 4488 evmovdqul(nds, dst, Assembler::AVX_512bit); 4489 Assembler::vpmullw(nds, nds, src, vector_len); 4490 evmovdqul(dst, nds, Assembler::AVX_512bit); 4491 } else { 4492 // worse case scenario, all regs in upper bank 4493 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4494 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4495 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4496 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4497 } 4498 } 4499 4500 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4501 int dst_enc = dst->encoding(); 4502 int nds_enc = nds->encoding(); 4503 int src_enc = src->encoding(); 4504 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4505 Assembler::vpsubb(dst, nds, src, vector_len); 4506 } else if ((dst_enc < 16) && (src_enc < 16)) { 4507 Assembler::vpsubb(dst, dst, src, vector_len); 4508 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4509 // use nds as scratch for src 4510 evmovdqul(nds, src, Assembler::AVX_512bit); 4511 Assembler::vpsubb(dst, dst, nds, vector_len); 4512 } else if ((src_enc < 16) && (nds_enc < 16)) { 4513 // use nds as scratch for dst 4514 evmovdqul(nds, dst, Assembler::AVX_512bit); 4515 Assembler::vpsubb(nds, nds, src, vector_len); 4516 evmovdqul(dst, nds, Assembler::AVX_512bit); 4517 } else if (dst_enc < 16) { 4518 // use nds as scatch for xmm0 to hold src 4519 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4520 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4521 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4522 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4523 } else { 4524 // worse case scenario, all regs are in the upper bank 4525 subptr(rsp, 64); 4526 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4527 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4528 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4529 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4530 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4531 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4532 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4533 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4534 addptr(rsp, 64); 4535 } 4536 } 4537 4538 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4539 int dst_enc = dst->encoding(); 4540 int nds_enc = nds->encoding(); 4541 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4542 Assembler::vpsubb(dst, nds, src, vector_len); 4543 } else if (dst_enc < 16) { 4544 Assembler::vpsubb(dst, dst, src, vector_len); 4545 } else if (nds_enc < 16) { 4546 // implies dst_enc in upper bank with src as scratch 4547 evmovdqul(nds, dst, Assembler::AVX_512bit); 4548 Assembler::vpsubb(nds, nds, src, vector_len); 4549 evmovdqul(dst, nds, Assembler::AVX_512bit); 4550 } else { 4551 // worse case scenario, all regs in upper bank 4552 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4553 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4554 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4555 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4556 } 4557 } 4558 4559 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4560 int dst_enc = dst->encoding(); 4561 int nds_enc = nds->encoding(); 4562 int src_enc = src->encoding(); 4563 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4564 Assembler::vpsubw(dst, nds, src, vector_len); 4565 } else if ((dst_enc < 16) && (src_enc < 16)) { 4566 Assembler::vpsubw(dst, dst, src, vector_len); 4567 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4568 // use nds as scratch for src 4569 evmovdqul(nds, src, Assembler::AVX_512bit); 4570 Assembler::vpsubw(dst, dst, nds, vector_len); 4571 } else if ((src_enc < 16) && (nds_enc < 16)) { 4572 // use nds as scratch for dst 4573 evmovdqul(nds, dst, Assembler::AVX_512bit); 4574 Assembler::vpsubw(nds, nds, src, vector_len); 4575 evmovdqul(dst, nds, Assembler::AVX_512bit); 4576 } else if (dst_enc < 16) { 4577 // use nds as scatch for xmm0 to hold src 4578 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4579 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4580 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4581 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4582 } else { 4583 // worse case scenario, all regs are in the upper bank 4584 subptr(rsp, 64); 4585 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4586 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4587 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4588 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4589 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4590 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4591 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4592 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4593 addptr(rsp, 64); 4594 } 4595 } 4596 4597 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4598 int dst_enc = dst->encoding(); 4599 int nds_enc = nds->encoding(); 4600 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4601 Assembler::vpsubw(dst, nds, src, vector_len); 4602 } else if (dst_enc < 16) { 4603 Assembler::vpsubw(dst, dst, src, vector_len); 4604 } else if (nds_enc < 16) { 4605 // implies dst_enc in upper bank with src as scratch 4606 evmovdqul(nds, dst, Assembler::AVX_512bit); 4607 Assembler::vpsubw(nds, nds, src, vector_len); 4608 evmovdqul(dst, nds, Assembler::AVX_512bit); 4609 } else { 4610 // worse case scenario, all regs in upper bank 4611 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4612 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4613 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4614 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4615 } 4616 } 4617 4618 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4619 int dst_enc = dst->encoding(); 4620 int nds_enc = nds->encoding(); 4621 int shift_enc = shift->encoding(); 4622 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4623 Assembler::vpsraw(dst, nds, shift, vector_len); 4624 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4625 Assembler::vpsraw(dst, dst, shift, vector_len); 4626 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4627 // use nds_enc as scratch with shift 4628 evmovdqul(nds, shift, Assembler::AVX_512bit); 4629 Assembler::vpsraw(dst, dst, nds, vector_len); 4630 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4631 // use nds as scratch with dst 4632 evmovdqul(nds, dst, Assembler::AVX_512bit); 4633 Assembler::vpsraw(nds, nds, shift, vector_len); 4634 evmovdqul(dst, nds, Assembler::AVX_512bit); 4635 } else if (dst_enc < 16) { 4636 // use nds to save a copy of xmm0 and hold shift 4637 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4638 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4639 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4640 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4641 } else if (nds_enc < 16) { 4642 // use nds as dest as temps 4643 evmovdqul(nds, dst, Assembler::AVX_512bit); 4644 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4645 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4646 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4647 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4648 evmovdqul(dst, nds, Assembler::AVX_512bit); 4649 } else { 4650 // worse case scenario, all regs are in the upper bank 4651 subptr(rsp, 64); 4652 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4653 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4654 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4655 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4656 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4657 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4658 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4659 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4660 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4661 addptr(rsp, 64); 4662 } 4663 } 4664 4665 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4666 int dst_enc = dst->encoding(); 4667 int nds_enc = nds->encoding(); 4668 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4669 Assembler::vpsraw(dst, nds, shift, vector_len); 4670 } else if (dst_enc < 16) { 4671 Assembler::vpsraw(dst, dst, shift, vector_len); 4672 } else if (nds_enc < 16) { 4673 // use nds as scratch 4674 evmovdqul(nds, dst, Assembler::AVX_512bit); 4675 Assembler::vpsraw(nds, nds, shift, vector_len); 4676 evmovdqul(dst, nds, Assembler::AVX_512bit); 4677 } else { 4678 // use nds as scratch for xmm0 4679 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4680 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4681 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4682 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4683 } 4684 } 4685 4686 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4687 int dst_enc = dst->encoding(); 4688 int nds_enc = nds->encoding(); 4689 int shift_enc = shift->encoding(); 4690 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4691 Assembler::vpsrlw(dst, nds, shift, vector_len); 4692 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4693 Assembler::vpsrlw(dst, dst, shift, vector_len); 4694 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4695 // use nds_enc as scratch with shift 4696 evmovdqul(nds, shift, Assembler::AVX_512bit); 4697 Assembler::vpsrlw(dst, dst, nds, vector_len); 4698 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4699 // use nds as scratch with dst 4700 evmovdqul(nds, dst, Assembler::AVX_512bit); 4701 Assembler::vpsrlw(nds, nds, shift, vector_len); 4702 evmovdqul(dst, nds, Assembler::AVX_512bit); 4703 } else if (dst_enc < 16) { 4704 // use nds to save a copy of xmm0 and hold shift 4705 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4706 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4707 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4708 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4709 } else if (nds_enc < 16) { 4710 // use nds as dest as temps 4711 evmovdqul(nds, dst, Assembler::AVX_512bit); 4712 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4713 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4714 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4715 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4716 evmovdqul(dst, nds, Assembler::AVX_512bit); 4717 } else { 4718 // worse case scenario, all regs are in the upper bank 4719 subptr(rsp, 64); 4720 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4721 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4722 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4723 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4724 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4725 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4726 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4727 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4728 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4729 addptr(rsp, 64); 4730 } 4731 } 4732 4733 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4734 int dst_enc = dst->encoding(); 4735 int nds_enc = nds->encoding(); 4736 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4737 Assembler::vpsrlw(dst, nds, shift, vector_len); 4738 } else if (dst_enc < 16) { 4739 Assembler::vpsrlw(dst, dst, shift, vector_len); 4740 } else if (nds_enc < 16) { 4741 // use nds as scratch 4742 evmovdqul(nds, dst, Assembler::AVX_512bit); 4743 Assembler::vpsrlw(nds, nds, shift, vector_len); 4744 evmovdqul(dst, nds, Assembler::AVX_512bit); 4745 } else { 4746 // use nds as scratch for xmm0 4747 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4748 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4749 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4750 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4751 } 4752 } 4753 4754 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4755 int dst_enc = dst->encoding(); 4756 int nds_enc = nds->encoding(); 4757 int shift_enc = shift->encoding(); 4758 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4759 Assembler::vpsllw(dst, nds, shift, vector_len); 4760 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4761 Assembler::vpsllw(dst, dst, shift, vector_len); 4762 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4763 // use nds_enc as scratch with shift 4764 evmovdqul(nds, shift, Assembler::AVX_512bit); 4765 Assembler::vpsllw(dst, dst, nds, vector_len); 4766 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4767 // use nds as scratch with dst 4768 evmovdqul(nds, dst, Assembler::AVX_512bit); 4769 Assembler::vpsllw(nds, nds, shift, vector_len); 4770 evmovdqul(dst, nds, Assembler::AVX_512bit); 4771 } else if (dst_enc < 16) { 4772 // use nds to save a copy of xmm0 and hold shift 4773 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4774 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4775 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4776 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4777 } else if (nds_enc < 16) { 4778 // use nds as dest as temps 4779 evmovdqul(nds, dst, Assembler::AVX_512bit); 4780 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4781 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4782 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4783 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4784 evmovdqul(dst, nds, Assembler::AVX_512bit); 4785 } else { 4786 // worse case scenario, all regs are in the upper bank 4787 subptr(rsp, 64); 4788 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4789 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4790 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4791 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4792 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4793 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4794 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4795 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4796 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4797 addptr(rsp, 64); 4798 } 4799 } 4800 4801 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4802 int dst_enc = dst->encoding(); 4803 int nds_enc = nds->encoding(); 4804 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4805 Assembler::vpsllw(dst, nds, shift, vector_len); 4806 } else if (dst_enc < 16) { 4807 Assembler::vpsllw(dst, dst, shift, vector_len); 4808 } else if (nds_enc < 16) { 4809 // use nds as scratch 4810 evmovdqul(nds, dst, Assembler::AVX_512bit); 4811 Assembler::vpsllw(nds, nds, shift, vector_len); 4812 evmovdqul(dst, nds, Assembler::AVX_512bit); 4813 } else { 4814 // use nds as scratch for xmm0 4815 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4816 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4817 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4818 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4819 } 4820 } 4821 4822 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4823 int dst_enc = dst->encoding(); 4824 int src_enc = src->encoding(); 4825 if ((dst_enc < 16) && (src_enc < 16)) { 4826 Assembler::vptest(dst, src); 4827 } else if (src_enc < 16) { 4828 subptr(rsp, 64); 4829 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4830 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4831 Assembler::vptest(xmm0, src); 4832 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4833 addptr(rsp, 64); 4834 } else if (dst_enc < 16) { 4835 subptr(rsp, 64); 4836 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4837 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4838 Assembler::vptest(dst, xmm0); 4839 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4840 addptr(rsp, 64); 4841 } else { 4842 subptr(rsp, 64); 4843 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4844 subptr(rsp, 64); 4845 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4846 movdqu(xmm0, src); 4847 movdqu(xmm1, dst); 4848 Assembler::vptest(xmm1, xmm0); 4849 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4850 addptr(rsp, 64); 4851 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4852 addptr(rsp, 64); 4853 } 4854 } 4855 4856 // This instruction exists within macros, ergo we cannot control its input 4857 // when emitted through those patterns. 4858 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4859 if (VM_Version::supports_avx512nobw()) { 4860 int dst_enc = dst->encoding(); 4861 int src_enc = src->encoding(); 4862 if (dst_enc == src_enc) { 4863 if (dst_enc < 16) { 4864 Assembler::punpcklbw(dst, src); 4865 } else { 4866 subptr(rsp, 64); 4867 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4868 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4869 Assembler::punpcklbw(xmm0, xmm0); 4870 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4871 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4872 addptr(rsp, 64); 4873 } 4874 } else { 4875 if ((src_enc < 16) && (dst_enc < 16)) { 4876 Assembler::punpcklbw(dst, src); 4877 } else if (src_enc < 16) { 4878 subptr(rsp, 64); 4879 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4880 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4881 Assembler::punpcklbw(xmm0, src); 4882 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4883 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4884 addptr(rsp, 64); 4885 } else if (dst_enc < 16) { 4886 subptr(rsp, 64); 4887 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4888 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4889 Assembler::punpcklbw(dst, xmm0); 4890 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4891 addptr(rsp, 64); 4892 } else { 4893 subptr(rsp, 64); 4894 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4895 subptr(rsp, 64); 4896 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4897 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4898 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4899 Assembler::punpcklbw(xmm0, xmm1); 4900 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4901 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4902 addptr(rsp, 64); 4903 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4904 addptr(rsp, 64); 4905 } 4906 } 4907 } else { 4908 Assembler::punpcklbw(dst, src); 4909 } 4910 } 4911 4912 // This instruction exists within macros, ergo we cannot control its input 4913 // when emitted through those patterns. 4914 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4915 if (VM_Version::supports_avx512nobw()) { 4916 int dst_enc = dst->encoding(); 4917 int src_enc = src->encoding(); 4918 if (dst_enc == src_enc) { 4919 if (dst_enc < 16) { 4920 Assembler::pshuflw(dst, src, mode); 4921 } else { 4922 subptr(rsp, 64); 4923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4924 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4925 Assembler::pshuflw(xmm0, xmm0, mode); 4926 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4927 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4928 addptr(rsp, 64); 4929 } 4930 } else { 4931 if ((src_enc < 16) && (dst_enc < 16)) { 4932 Assembler::pshuflw(dst, src, mode); 4933 } else if (src_enc < 16) { 4934 subptr(rsp, 64); 4935 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4936 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4937 Assembler::pshuflw(xmm0, src, mode); 4938 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4939 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4940 addptr(rsp, 64); 4941 } else if (dst_enc < 16) { 4942 subptr(rsp, 64); 4943 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4944 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4945 Assembler::pshuflw(dst, xmm0, mode); 4946 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4947 addptr(rsp, 64); 4948 } else { 4949 subptr(rsp, 64); 4950 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4951 subptr(rsp, 64); 4952 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4953 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4954 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4955 Assembler::pshuflw(xmm0, xmm1, mode); 4956 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4957 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4958 addptr(rsp, 64); 4959 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4960 addptr(rsp, 64); 4961 } 4962 } 4963 } else { 4964 Assembler::pshuflw(dst, src, mode); 4965 } 4966 } 4967 4968 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4969 if (reachable(src)) { 4970 vandpd(dst, nds, as_Address(src), vector_len); 4971 } else { 4972 lea(rscratch1, src); 4973 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4974 } 4975 } 4976 4977 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4978 if (reachable(src)) { 4979 vandps(dst, nds, as_Address(src), vector_len); 4980 } else { 4981 lea(rscratch1, src); 4982 vandps(dst, nds, Address(rscratch1, 0), vector_len); 4983 } 4984 } 4985 4986 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4987 if (reachable(src)) { 4988 vdivsd(dst, nds, as_Address(src)); 4989 } else { 4990 lea(rscratch1, src); 4991 vdivsd(dst, nds, Address(rscratch1, 0)); 4992 } 4993 } 4994 4995 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4996 if (reachable(src)) { 4997 vdivss(dst, nds, as_Address(src)); 4998 } else { 4999 lea(rscratch1, src); 5000 vdivss(dst, nds, Address(rscratch1, 0)); 5001 } 5002 } 5003 5004 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5005 if (reachable(src)) { 5006 vmulsd(dst, nds, as_Address(src)); 5007 } else { 5008 lea(rscratch1, src); 5009 vmulsd(dst, nds, Address(rscratch1, 0)); 5010 } 5011 } 5012 5013 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5014 if (reachable(src)) { 5015 vmulss(dst, nds, as_Address(src)); 5016 } else { 5017 lea(rscratch1, src); 5018 vmulss(dst, nds, Address(rscratch1, 0)); 5019 } 5020 } 5021 5022 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5023 if (reachable(src)) { 5024 vsubsd(dst, nds, as_Address(src)); 5025 } else { 5026 lea(rscratch1, src); 5027 vsubsd(dst, nds, Address(rscratch1, 0)); 5028 } 5029 } 5030 5031 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5032 if (reachable(src)) { 5033 vsubss(dst, nds, as_Address(src)); 5034 } else { 5035 lea(rscratch1, src); 5036 vsubss(dst, nds, Address(rscratch1, 0)); 5037 } 5038 } 5039 5040 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5041 int nds_enc = nds->encoding(); 5042 int dst_enc = dst->encoding(); 5043 bool dst_upper_bank = (dst_enc > 15); 5044 bool nds_upper_bank = (nds_enc > 15); 5045 if (VM_Version::supports_avx512novl() && 5046 (nds_upper_bank || dst_upper_bank)) { 5047 if (dst_upper_bank) { 5048 subptr(rsp, 64); 5049 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5050 movflt(xmm0, nds); 5051 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5052 movflt(dst, xmm0); 5053 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5054 addptr(rsp, 64); 5055 } else { 5056 movflt(dst, nds); 5057 vxorps(dst, dst, src, Assembler::AVX_128bit); 5058 } 5059 } else { 5060 vxorps(dst, nds, src, Assembler::AVX_128bit); 5061 } 5062 } 5063 5064 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5065 int nds_enc = nds->encoding(); 5066 int dst_enc = dst->encoding(); 5067 bool dst_upper_bank = (dst_enc > 15); 5068 bool nds_upper_bank = (nds_enc > 15); 5069 if (VM_Version::supports_avx512novl() && 5070 (nds_upper_bank || dst_upper_bank)) { 5071 if (dst_upper_bank) { 5072 subptr(rsp, 64); 5073 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5074 movdbl(xmm0, nds); 5075 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5076 movdbl(dst, xmm0); 5077 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5078 addptr(rsp, 64); 5079 } else { 5080 movdbl(dst, nds); 5081 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5082 } 5083 } else { 5084 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5085 } 5086 } 5087 5088 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5089 if (reachable(src)) { 5090 vxorpd(dst, nds, as_Address(src), vector_len); 5091 } else { 5092 lea(rscratch1, src); 5093 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5094 } 5095 } 5096 5097 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5098 if (reachable(src)) { 5099 vxorps(dst, nds, as_Address(src), vector_len); 5100 } else { 5101 lea(rscratch1, src); 5102 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5103 } 5104 } 5105 5106 5107 ////////////////////////////////////////////////////////////////////////////////// 5108 #if INCLUDE_ALL_GCS 5109 5110 void MacroAssembler::g1_write_barrier_pre(Register obj, 5111 Register pre_val, 5112 Register thread, 5113 Register tmp, 5114 bool tosca_live, 5115 bool expand_call) { 5116 5117 // If expand_call is true then we expand the call_VM_leaf macro 5118 // directly to skip generating the check by 5119 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5120 5121 #ifdef _LP64 5122 assert(thread == r15_thread, "must be"); 5123 #endif // _LP64 5124 5125 Label done; 5126 Label runtime; 5127 5128 assert(pre_val != noreg, "check this code"); 5129 5130 if (obj != noreg) { 5131 assert_different_registers(obj, pre_val, tmp); 5132 assert(pre_val != rax, "check this code"); 5133 } 5134 5135 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5136 SATBMarkQueue::byte_offset_of_active())); 5137 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5138 SATBMarkQueue::byte_offset_of_index())); 5139 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5140 SATBMarkQueue::byte_offset_of_buf())); 5141 5142 5143 // Is marking active? 5144 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5145 cmpl(in_progress, 0); 5146 } else { 5147 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5148 cmpb(in_progress, 0); 5149 } 5150 jcc(Assembler::equal, done); 5151 5152 // Do we need to load the previous value? 5153 if (obj != noreg) { 5154 load_heap_oop(pre_val, Address(obj, 0)); 5155 } 5156 5157 // Is the previous value null? 5158 cmpptr(pre_val, (int32_t) NULL_WORD); 5159 jcc(Assembler::equal, done); 5160 5161 // Can we store original value in the thread's buffer? 5162 // Is index == 0? 5163 // (The index field is typed as size_t.) 5164 5165 movptr(tmp, index); // tmp := *index_adr 5166 cmpptr(tmp, 0); // tmp == 0? 5167 jcc(Assembler::equal, runtime); // If yes, goto runtime 5168 5169 subptr(tmp, wordSize); // tmp := tmp - wordSize 5170 movptr(index, tmp); // *index_adr := tmp 5171 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5172 5173 // Record the previous value 5174 movptr(Address(tmp, 0), pre_val); 5175 jmp(done); 5176 5177 bind(runtime); 5178 // save the live input values 5179 if(tosca_live) push(rax); 5180 5181 if (obj != noreg && obj != rax) 5182 push(obj); 5183 5184 if (pre_val != rax) 5185 push(pre_val); 5186 5187 // Calling the runtime using the regular call_VM_leaf mechanism generates 5188 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5189 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5190 // 5191 // If we care generating the pre-barrier without a frame (e.g. in the 5192 // intrinsified Reference.get() routine) then ebp might be pointing to 5193 // the caller frame and so this check will most likely fail at runtime. 5194 // 5195 // Expanding the call directly bypasses the generation of the check. 5196 // So when we do not have have a full interpreter frame on the stack 5197 // expand_call should be passed true. 5198 5199 NOT_LP64( push(thread); ) 5200 5201 if (expand_call) { 5202 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5203 pass_arg1(this, thread); 5204 pass_arg0(this, pre_val); 5205 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5206 } else { 5207 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5208 } 5209 5210 NOT_LP64( pop(thread); ) 5211 5212 // save the live input values 5213 if (pre_val != rax) 5214 pop(pre_val); 5215 5216 if (obj != noreg && obj != rax) 5217 pop(obj); 5218 5219 if(tosca_live) pop(rax); 5220 5221 bind(done); 5222 } 5223 5224 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5225 Register new_val, 5226 Register thread, 5227 Register tmp, 5228 Register tmp2) { 5229 #ifdef _LP64 5230 assert(thread == r15_thread, "must be"); 5231 #endif // _LP64 5232 5233 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5234 DirtyCardQueue::byte_offset_of_index())); 5235 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5236 DirtyCardQueue::byte_offset_of_buf())); 5237 5238 CardTableModRefBS* ct = 5239 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5240 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5241 5242 Label done; 5243 Label runtime; 5244 5245 // Does store cross heap regions? 5246 5247 movptr(tmp, store_addr); 5248 xorptr(tmp, new_val); 5249 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5250 jcc(Assembler::equal, done); 5251 5252 // crosses regions, storing NULL? 5253 5254 cmpptr(new_val, (int32_t) NULL_WORD); 5255 jcc(Assembler::equal, done); 5256 5257 // storing region crossing non-NULL, is card already dirty? 5258 5259 const Register card_addr = tmp; 5260 const Register cardtable = tmp2; 5261 5262 movptr(card_addr, store_addr); 5263 shrptr(card_addr, CardTableModRefBS::card_shift); 5264 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5265 // a valid address and therefore is not properly handled by the relocation code. 5266 movptr(cardtable, (intptr_t)ct->byte_map_base); 5267 addptr(card_addr, cardtable); 5268 5269 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5270 jcc(Assembler::equal, done); 5271 5272 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5273 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5274 jcc(Assembler::equal, done); 5275 5276 5277 // storing a region crossing, non-NULL oop, card is clean. 5278 // dirty card and log. 5279 5280 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5281 5282 cmpl(queue_index, 0); 5283 jcc(Assembler::equal, runtime); 5284 subl(queue_index, wordSize); 5285 movptr(tmp2, buffer); 5286 #ifdef _LP64 5287 movslq(rscratch1, queue_index); 5288 addq(tmp2, rscratch1); 5289 movq(Address(tmp2, 0), card_addr); 5290 #else 5291 addl(tmp2, queue_index); 5292 movl(Address(tmp2, 0), card_addr); 5293 #endif 5294 jmp(done); 5295 5296 bind(runtime); 5297 // save the live input values 5298 push(store_addr); 5299 push(new_val); 5300 #ifdef _LP64 5301 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5302 #else 5303 push(thread); 5304 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5305 pop(thread); 5306 #endif 5307 pop(new_val); 5308 pop(store_addr); 5309 5310 bind(done); 5311 } 5312 5313 #endif // INCLUDE_ALL_GCS 5314 ////////////////////////////////////////////////////////////////////////////////// 5315 5316 5317 void MacroAssembler::store_check(Register obj, Address dst) { 5318 store_check(obj); 5319 } 5320 5321 void MacroAssembler::store_check(Register obj) { 5322 // Does a store check for the oop in register obj. The content of 5323 // register obj is destroyed afterwards. 5324 BarrierSet* bs = Universe::heap()->barrier_set(); 5325 assert(bs->kind() == BarrierSet::CardTableForRS || 5326 bs->kind() == BarrierSet::CardTableExtension, 5327 "Wrong barrier set kind"); 5328 5329 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5330 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5331 5332 shrptr(obj, CardTableModRefBS::card_shift); 5333 5334 Address card_addr; 5335 5336 // The calculation for byte_map_base is as follows: 5337 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5338 // So this essentially converts an address to a displacement and it will 5339 // never need to be relocated. On 64bit however the value may be too 5340 // large for a 32bit displacement. 5341 intptr_t disp = (intptr_t) ct->byte_map_base; 5342 if (is_simm32(disp)) { 5343 card_addr = Address(noreg, obj, Address::times_1, disp); 5344 } else { 5345 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5346 // displacement and done in a single instruction given favorable mapping and a 5347 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5348 // entry and that entry is not properly handled by the relocation code. 5349 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5350 Address index(noreg, obj, Address::times_1); 5351 card_addr = as_Address(ArrayAddress(cardtable, index)); 5352 } 5353 5354 int dirty = CardTableModRefBS::dirty_card_val(); 5355 if (UseCondCardMark) { 5356 Label L_already_dirty; 5357 if (UseConcMarkSweepGC) { 5358 membar(Assembler::StoreLoad); 5359 } 5360 cmpb(card_addr, dirty); 5361 jcc(Assembler::equal, L_already_dirty); 5362 movb(card_addr, dirty); 5363 bind(L_already_dirty); 5364 } else { 5365 movb(card_addr, dirty); 5366 } 5367 } 5368 5369 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5370 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5371 } 5372 5373 // Force generation of a 4 byte immediate value even if it fits into 8bit 5374 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5375 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5376 } 5377 5378 void MacroAssembler::subptr(Register dst, Register src) { 5379 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5380 } 5381 5382 // C++ bool manipulation 5383 void MacroAssembler::testbool(Register dst) { 5384 if(sizeof(bool) == 1) 5385 testb(dst, 0xff); 5386 else if(sizeof(bool) == 2) { 5387 // testw implementation needed for two byte bools 5388 ShouldNotReachHere(); 5389 } else if(sizeof(bool) == 4) 5390 testl(dst, dst); 5391 else 5392 // unsupported 5393 ShouldNotReachHere(); 5394 } 5395 5396 void MacroAssembler::testptr(Register dst, Register src) { 5397 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5398 } 5399 5400 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5401 void MacroAssembler::tlab_allocate(Register obj, 5402 Register var_size_in_bytes, 5403 int con_size_in_bytes, 5404 Register t1, 5405 Register t2, 5406 Label& slow_case) { 5407 assert_different_registers(obj, t1, t2); 5408 assert_different_registers(obj, var_size_in_bytes, t1); 5409 Register end = t2; 5410 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5411 5412 verify_tlab(); 5413 5414 NOT_LP64(get_thread(thread)); 5415 5416 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5417 if (var_size_in_bytes == noreg) { 5418 lea(end, Address(obj, con_size_in_bytes)); 5419 } else { 5420 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5421 } 5422 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5423 jcc(Assembler::above, slow_case); 5424 5425 // update the tlab top pointer 5426 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5427 5428 // recover var_size_in_bytes if necessary 5429 if (var_size_in_bytes == end) { 5430 subptr(var_size_in_bytes, obj); 5431 } 5432 verify_tlab(); 5433 } 5434 5435 // Preserves rbx, and rdx. 5436 Register MacroAssembler::tlab_refill(Label& retry, 5437 Label& try_eden, 5438 Label& slow_case) { 5439 Register top = rax; 5440 Register t1 = rcx; // object size 5441 Register t2 = rsi; 5442 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5443 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5444 Label do_refill, discard_tlab; 5445 5446 if (!Universe::heap()->supports_inline_contig_alloc()) { 5447 // No allocation in the shared eden. 5448 jmp(slow_case); 5449 } 5450 5451 NOT_LP64(get_thread(thread_reg)); 5452 5453 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5454 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5455 5456 // calculate amount of free space 5457 subptr(t1, top); 5458 shrptr(t1, LogHeapWordSize); 5459 5460 // Retain tlab and allocate object in shared space if 5461 // the amount free in the tlab is too large to discard. 5462 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5463 jcc(Assembler::lessEqual, discard_tlab); 5464 5465 // Retain 5466 // %%% yuck as movptr... 5467 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5468 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5469 if (TLABStats) { 5470 // increment number of slow_allocations 5471 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5472 } 5473 jmp(try_eden); 5474 5475 bind(discard_tlab); 5476 if (TLABStats) { 5477 // increment number of refills 5478 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5479 // accumulate wastage -- t1 is amount free in tlab 5480 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5481 } 5482 5483 // if tlab is currently allocated (top or end != null) then 5484 // fill [top, end + alignment_reserve) with array object 5485 testptr(top, top); 5486 jcc(Assembler::zero, do_refill); 5487 5488 // set up the mark word 5489 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5490 // set the length to the remaining space 5491 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5492 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5493 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5494 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5495 // set klass to intArrayKlass 5496 // dubious reloc why not an oop reloc? 5497 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5498 // store klass last. concurrent gcs assumes klass length is valid if 5499 // klass field is not null. 5500 store_klass(top, t1); 5501 5502 movptr(t1, top); 5503 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5504 incr_allocated_bytes(thread_reg, t1, 0); 5505 5506 // refill the tlab with an eden allocation 5507 bind(do_refill); 5508 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5509 shlptr(t1, LogHeapWordSize); 5510 // allocate new tlab, address returned in top 5511 eden_allocate(top, t1, 0, t2, slow_case); 5512 5513 // Check that t1 was preserved in eden_allocate. 5514 #ifdef ASSERT 5515 if (UseTLAB) { 5516 Label ok; 5517 Register tsize = rsi; 5518 assert_different_registers(tsize, thread_reg, t1); 5519 push(tsize); 5520 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5521 shlptr(tsize, LogHeapWordSize); 5522 cmpptr(t1, tsize); 5523 jcc(Assembler::equal, ok); 5524 STOP("assert(t1 != tlab size)"); 5525 should_not_reach_here(); 5526 5527 bind(ok); 5528 pop(tsize); 5529 } 5530 #endif 5531 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5532 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5533 addptr(top, t1); 5534 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5535 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5536 5537 if (ZeroTLAB) { 5538 // This is a fast TLAB refill, therefore the GC is not notified of it. 5539 // So compiled code must fill the new TLAB with zeroes. 5540 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5541 zero_memory(top, t1, 0, t2); 5542 } 5543 5544 verify_tlab(); 5545 jmp(retry); 5546 5547 return thread_reg; // for use by caller 5548 } 5549 5550 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5551 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5552 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5553 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5554 Label done; 5555 5556 testptr(length_in_bytes, length_in_bytes); 5557 jcc(Assembler::zero, done); 5558 5559 // initialize topmost word, divide index by 2, check if odd and test if zero 5560 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5561 #ifdef ASSERT 5562 { 5563 Label L; 5564 testptr(length_in_bytes, BytesPerWord - 1); 5565 jcc(Assembler::zero, L); 5566 stop("length must be a multiple of BytesPerWord"); 5567 bind(L); 5568 } 5569 #endif 5570 Register index = length_in_bytes; 5571 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5572 if (UseIncDec) { 5573 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5574 } else { 5575 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5576 shrptr(index, 1); 5577 } 5578 #ifndef _LP64 5579 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5580 { 5581 Label even; 5582 // note: if index was a multiple of 8, then it cannot 5583 // be 0 now otherwise it must have been 0 before 5584 // => if it is even, we don't need to check for 0 again 5585 jcc(Assembler::carryClear, even); 5586 // clear topmost word (no jump would be needed if conditional assignment worked here) 5587 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5588 // index could be 0 now, must check again 5589 jcc(Assembler::zero, done); 5590 bind(even); 5591 } 5592 #endif // !_LP64 5593 // initialize remaining object fields: index is a multiple of 2 now 5594 { 5595 Label loop; 5596 bind(loop); 5597 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5598 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5599 decrement(index); 5600 jcc(Assembler::notZero, loop); 5601 } 5602 5603 bind(done); 5604 } 5605 5606 void MacroAssembler::incr_allocated_bytes(Register thread, 5607 Register var_size_in_bytes, 5608 int con_size_in_bytes, 5609 Register t1) { 5610 if (!thread->is_valid()) { 5611 #ifdef _LP64 5612 thread = r15_thread; 5613 #else 5614 assert(t1->is_valid(), "need temp reg"); 5615 thread = t1; 5616 get_thread(thread); 5617 #endif 5618 } 5619 5620 #ifdef _LP64 5621 if (var_size_in_bytes->is_valid()) { 5622 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5623 } else { 5624 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5625 } 5626 #else 5627 if (var_size_in_bytes->is_valid()) { 5628 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5629 } else { 5630 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5631 } 5632 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5633 #endif 5634 } 5635 5636 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { 5637 pusha(); 5638 5639 // if we are coming from c1, xmm registers may be live 5640 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8); 5641 if (UseAVX > 2) { 5642 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8); 5643 } 5644 5645 if (UseSSE == 1) { 5646 subptr(rsp, sizeof(jdouble)*8); 5647 for (int n = 0; n < 8; n++) { 5648 movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n)); 5649 } 5650 } else if (UseSSE >= 2) { 5651 if (UseAVX > 2) { 5652 push(rbx); 5653 movl(rbx, 0xffff); 5654 kmovwl(k1, rbx); 5655 pop(rbx); 5656 } 5657 #ifdef COMPILER2 5658 if (MaxVectorSize > 16) { 5659 if(UseAVX > 2) { 5660 // Save upper half of ZMM registers 5661 subptr(rsp, 32*num_xmm_regs); 5662 for (int n = 0; n < num_xmm_regs; n++) { 5663 vextractf64x4_high(Address(rsp, n*32), as_XMMRegister(n)); 5664 } 5665 } 5666 assert(UseAVX > 0, "256 bit vectors are supported only with AVX"); 5667 // Save upper half of YMM registers 5668 subptr(rsp, 16*num_xmm_regs); 5669 for (int n = 0; n < num_xmm_regs; n++) { 5670 vextractf128_high(Address(rsp, n*16), as_XMMRegister(n)); 5671 } 5672 } 5673 #endif 5674 // Save whole 128bit (16 bytes) XMM registers 5675 subptr(rsp, 16*num_xmm_regs); 5676 #ifdef _LP64 5677 if (VM_Version::supports_evex()) { 5678 for (int n = 0; n < num_xmm_regs; n++) { 5679 vextractf32x4(Address(rsp, n*16), as_XMMRegister(n), 0); 5680 } 5681 } else { 5682 for (int n = 0; n < num_xmm_regs; n++) { 5683 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 5684 } 5685 } 5686 #else 5687 for (int n = 0; n < num_xmm_regs; n++) { 5688 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 5689 } 5690 #endif 5691 } 5692 5693 // Preserve registers across runtime call 5694 int incoming_argument_and_return_value_offset = -1; 5695 if (num_fpu_regs_in_use > 1) { 5696 // Must preserve all other FPU regs (could alternatively convert 5697 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash 5698 // FPU state, but can not trust C compiler) 5699 NEEDS_CLEANUP; 5700 // NOTE that in this case we also push the incoming argument(s) to 5701 // the stack and restore it later; we also use this stack slot to 5702 // hold the return value from dsin, dcos etc. 5703 for (int i = 0; i < num_fpu_regs_in_use; i++) { 5704 subptr(rsp, sizeof(jdouble)); 5705 fstp_d(Address(rsp, 0)); 5706 } 5707 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 5708 for (int i = nb_args-1; i >= 0; i--) { 5709 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); 5710 } 5711 } 5712 5713 subptr(rsp, nb_args*sizeof(jdouble)); 5714 for (int i = 0; i < nb_args; i++) { 5715 fstp_d(Address(rsp, i*sizeof(jdouble))); 5716 } 5717 5718 #ifdef _LP64 5719 if (nb_args > 0) { 5720 movdbl(xmm0, Address(rsp, 0)); 5721 } 5722 if (nb_args > 1) { 5723 movdbl(xmm1, Address(rsp, sizeof(jdouble))); 5724 } 5725 assert(nb_args <= 2, "unsupported number of args"); 5726 #endif // _LP64 5727 5728 // NOTE: we must not use call_VM_leaf here because that requires a 5729 // complete interpreter frame in debug mode -- same bug as 4387334 5730 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 5731 // do proper 64bit abi 5732 5733 NEEDS_CLEANUP; 5734 // Need to add stack banging before this runtime call if it needs to 5735 // be taken; however, there is no generic stack banging routine at 5736 // the MacroAssembler level 5737 5738 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); 5739 5740 #ifdef _LP64 5741 movsd(Address(rsp, 0), xmm0); 5742 fld_d(Address(rsp, 0)); 5743 #endif // _LP64 5744 addptr(rsp, sizeof(jdouble)*nb_args); 5745 if (num_fpu_regs_in_use > 1) { 5746 // Must save return value to stack and then restore entire FPU 5747 // stack except incoming arguments 5748 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 5749 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { 5750 fld_d(Address(rsp, 0)); 5751 addptr(rsp, sizeof(jdouble)); 5752 } 5753 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); 5754 addptr(rsp, sizeof(jdouble)*nb_args); 5755 } 5756 5757 if (UseSSE == 1) { 5758 for (int n = 0; n < 8; n++) { 5759 movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble))); 5760 } 5761 addptr(rsp, sizeof(jdouble)*8); 5762 } else if (UseSSE >= 2) { 5763 // Restore whole 128bit (16 bytes) XMM registers 5764 #ifdef _LP64 5765 if (VM_Version::supports_evex()) { 5766 for (int n = 0; n < num_xmm_regs; n++) { 5767 vinsertf32x4(as_XMMRegister(n), as_XMMRegister(n), Address(rsp, n*16), 0); 5768 } 5769 } else { 5770 for (int n = 0; n < num_xmm_regs; n++) { 5771 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 5772 } 5773 } 5774 #else 5775 for (int n = 0; n < num_xmm_regs; n++) { 5776 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 5777 } 5778 #endif 5779 addptr(rsp, 16*num_xmm_regs); 5780 5781 #ifdef COMPILER2 5782 if (MaxVectorSize > 16) { 5783 // Restore upper half of YMM registers. 5784 for (int n = 0; n < num_xmm_regs; n++) { 5785 vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16)); 5786 } 5787 addptr(rsp, 16*num_xmm_regs); 5788 if(UseAVX > 2) { 5789 for (int n = 0; n < num_xmm_regs; n++) { 5790 vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32)); 5791 } 5792 addptr(rsp, 32*num_xmm_regs); 5793 } 5794 } 5795 #endif 5796 } 5797 popa(); 5798 } 5799 5800 static const double pi_4 = 0.7853981633974483; 5801 5802 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 5803 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 5804 // was attempted in this code; unfortunately it appears that the 5805 // switch to 80-bit precision and back causes this to be 5806 // unprofitable compared with simply performing a runtime call if 5807 // the argument is out of the (-pi/4, pi/4) range. 5808 5809 Register tmp = noreg; 5810 if (!VM_Version::supports_cmov()) { 5811 // fcmp needs a temporary so preserve rbx, 5812 tmp = rbx; 5813 push(tmp); 5814 } 5815 5816 Label slow_case, done; 5817 if (trig == 't') { 5818 ExternalAddress pi4_adr = (address)&pi_4; 5819 if (reachable(pi4_adr)) { 5820 // x ?<= pi/4 5821 fld_d(pi4_adr); 5822 fld_s(1); // Stack: X PI/4 X 5823 fabs(); // Stack: |X| PI/4 X 5824 fcmp(tmp); 5825 jcc(Assembler::above, slow_case); 5826 5827 // fastest case: -pi/4 <= x <= pi/4 5828 ftan(); 5829 5830 jmp(done); 5831 } 5832 } 5833 // slow case: runtime call 5834 bind(slow_case); 5835 5836 switch(trig) { 5837 case 's': 5838 { 5839 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); 5840 } 5841 break; 5842 case 'c': 5843 { 5844 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); 5845 } 5846 break; 5847 case 't': 5848 { 5849 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); 5850 } 5851 break; 5852 default: 5853 assert(false, "bad intrinsic"); 5854 break; 5855 } 5856 5857 // Come here with result in F-TOS 5858 bind(done); 5859 5860 if (tmp != noreg) { 5861 pop(tmp); 5862 } 5863 } 5864 5865 // Look up the method for a megamorphic invokeinterface call. 5866 // The target method is determined by <intf_klass, itable_index>. 5867 // The receiver klass is in recv_klass. 5868 // On success, the result will be in method_result, and execution falls through. 5869 // On failure, execution transfers to the given label. 5870 void MacroAssembler::lookup_interface_method(Register recv_klass, 5871 Register intf_klass, 5872 RegisterOrConstant itable_index, 5873 Register method_result, 5874 Register scan_temp, 5875 Label& L_no_such_interface) { 5876 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5877 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5878 "caller must use same register for non-constant itable index as for method"); 5879 5880 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5881 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5882 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5883 int scan_step = itableOffsetEntry::size() * wordSize; 5884 int vte_size = vtableEntry::size_in_bytes(); 5885 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5886 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5887 5888 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5889 5890 // %%% Could store the aligned, prescaled offset in the klassoop. 5891 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5892 5893 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5894 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5895 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5896 5897 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5898 // if (scan->interface() == intf) { 5899 // result = (klass + scan->offset() + itable_index); 5900 // } 5901 // } 5902 Label search, found_method; 5903 5904 for (int peel = 1; peel >= 0; peel--) { 5905 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5906 cmpptr(intf_klass, method_result); 5907 5908 if (peel) { 5909 jccb(Assembler::equal, found_method); 5910 } else { 5911 jccb(Assembler::notEqual, search); 5912 // (invert the test to fall through to found_method...) 5913 } 5914 5915 if (!peel) break; 5916 5917 bind(search); 5918 5919 // Check that the previous entry is non-null. A null entry means that 5920 // the receiver class doesn't implement the interface, and wasn't the 5921 // same as when the caller was compiled. 5922 testptr(method_result, method_result); 5923 jcc(Assembler::zero, L_no_such_interface); 5924 addptr(scan_temp, scan_step); 5925 } 5926 5927 bind(found_method); 5928 5929 // Got a hit. 5930 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5931 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5932 } 5933 5934 5935 // virtual method calling 5936 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5937 RegisterOrConstant vtable_index, 5938 Register method_result) { 5939 const int base = in_bytes(Klass::vtable_start_offset()); 5940 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5941 Address vtable_entry_addr(recv_klass, 5942 vtable_index, Address::times_ptr, 5943 base + vtableEntry::method_offset_in_bytes()); 5944 movptr(method_result, vtable_entry_addr); 5945 } 5946 5947 5948 void MacroAssembler::check_klass_subtype(Register sub_klass, 5949 Register super_klass, 5950 Register temp_reg, 5951 Label& L_success) { 5952 Label L_failure; 5953 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5954 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5955 bind(L_failure); 5956 } 5957 5958 5959 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5960 Register super_klass, 5961 Register temp_reg, 5962 Label* L_success, 5963 Label* L_failure, 5964 Label* L_slow_path, 5965 RegisterOrConstant super_check_offset) { 5966 assert_different_registers(sub_klass, super_klass, temp_reg); 5967 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5968 if (super_check_offset.is_register()) { 5969 assert_different_registers(sub_klass, super_klass, 5970 super_check_offset.as_register()); 5971 } else if (must_load_sco) { 5972 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5973 } 5974 5975 Label L_fallthrough; 5976 int label_nulls = 0; 5977 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5978 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5979 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5980 assert(label_nulls <= 1, "at most one NULL in the batch"); 5981 5982 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5983 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5984 Address super_check_offset_addr(super_klass, sco_offset); 5985 5986 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5987 // range of a jccb. If this routine grows larger, reconsider at 5988 // least some of these. 5989 #define local_jcc(assembler_cond, label) \ 5990 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5991 else jcc( assembler_cond, label) /*omit semi*/ 5992 5993 // Hacked jmp, which may only be used just before L_fallthrough. 5994 #define final_jmp(label) \ 5995 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5996 else jmp(label) /*omit semi*/ 5997 5998 // If the pointers are equal, we are done (e.g., String[] elements). 5999 // This self-check enables sharing of secondary supertype arrays among 6000 // non-primary types such as array-of-interface. Otherwise, each such 6001 // type would need its own customized SSA. 6002 // We move this check to the front of the fast path because many 6003 // type checks are in fact trivially successful in this manner, 6004 // so we get a nicely predicted branch right at the start of the check. 6005 cmpptr(sub_klass, super_klass); 6006 local_jcc(Assembler::equal, *L_success); 6007 6008 // Check the supertype display: 6009 if (must_load_sco) { 6010 // Positive movl does right thing on LP64. 6011 movl(temp_reg, super_check_offset_addr); 6012 super_check_offset = RegisterOrConstant(temp_reg); 6013 } 6014 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 6015 cmpptr(super_klass, super_check_addr); // load displayed supertype 6016 6017 // This check has worked decisively for primary supers. 6018 // Secondary supers are sought in the super_cache ('super_cache_addr'). 6019 // (Secondary supers are interfaces and very deeply nested subtypes.) 6020 // This works in the same check above because of a tricky aliasing 6021 // between the super_cache and the primary super display elements. 6022 // (The 'super_check_addr' can address either, as the case requires.) 6023 // Note that the cache is updated below if it does not help us find 6024 // what we need immediately. 6025 // So if it was a primary super, we can just fail immediately. 6026 // Otherwise, it's the slow path for us (no success at this point). 6027 6028 if (super_check_offset.is_register()) { 6029 local_jcc(Assembler::equal, *L_success); 6030 cmpl(super_check_offset.as_register(), sc_offset); 6031 if (L_failure == &L_fallthrough) { 6032 local_jcc(Assembler::equal, *L_slow_path); 6033 } else { 6034 local_jcc(Assembler::notEqual, *L_failure); 6035 final_jmp(*L_slow_path); 6036 } 6037 } else if (super_check_offset.as_constant() == sc_offset) { 6038 // Need a slow path; fast failure is impossible. 6039 if (L_slow_path == &L_fallthrough) { 6040 local_jcc(Assembler::equal, *L_success); 6041 } else { 6042 local_jcc(Assembler::notEqual, *L_slow_path); 6043 final_jmp(*L_success); 6044 } 6045 } else { 6046 // No slow path; it's a fast decision. 6047 if (L_failure == &L_fallthrough) { 6048 local_jcc(Assembler::equal, *L_success); 6049 } else { 6050 local_jcc(Assembler::notEqual, *L_failure); 6051 final_jmp(*L_success); 6052 } 6053 } 6054 6055 bind(L_fallthrough); 6056 6057 #undef local_jcc 6058 #undef final_jmp 6059 } 6060 6061 6062 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 6063 Register super_klass, 6064 Register temp_reg, 6065 Register temp2_reg, 6066 Label* L_success, 6067 Label* L_failure, 6068 bool set_cond_codes) { 6069 assert_different_registers(sub_klass, super_klass, temp_reg); 6070 if (temp2_reg != noreg) 6071 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 6072 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 6073 6074 Label L_fallthrough; 6075 int label_nulls = 0; 6076 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 6077 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 6078 assert(label_nulls <= 1, "at most one NULL in the batch"); 6079 6080 // a couple of useful fields in sub_klass: 6081 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 6082 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 6083 Address secondary_supers_addr(sub_klass, ss_offset); 6084 Address super_cache_addr( sub_klass, sc_offset); 6085 6086 // Do a linear scan of the secondary super-klass chain. 6087 // This code is rarely used, so simplicity is a virtue here. 6088 // The repne_scan instruction uses fixed registers, which we must spill. 6089 // Don't worry too much about pre-existing connections with the input regs. 6090 6091 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 6092 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 6093 6094 // Get super_klass value into rax (even if it was in rdi or rcx). 6095 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 6096 if (super_klass != rax || UseCompressedOops) { 6097 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 6098 mov(rax, super_klass); 6099 } 6100 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 6101 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 6102 6103 #ifndef PRODUCT 6104 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 6105 ExternalAddress pst_counter_addr((address) pst_counter); 6106 NOT_LP64( incrementl(pst_counter_addr) ); 6107 LP64_ONLY( lea(rcx, pst_counter_addr) ); 6108 LP64_ONLY( incrementl(Address(rcx, 0)) ); 6109 #endif //PRODUCT 6110 6111 // We will consult the secondary-super array. 6112 movptr(rdi, secondary_supers_addr); 6113 // Load the array length. (Positive movl does right thing on LP64.) 6114 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 6115 // Skip to start of data. 6116 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 6117 6118 // Scan RCX words at [RDI] for an occurrence of RAX. 6119 // Set NZ/Z based on last compare. 6120 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 6121 // not change flags (only scas instruction which is repeated sets flags). 6122 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 6123 6124 testptr(rax,rax); // Set Z = 0 6125 repne_scan(); 6126 6127 // Unspill the temp. registers: 6128 if (pushed_rdi) pop(rdi); 6129 if (pushed_rcx) pop(rcx); 6130 if (pushed_rax) pop(rax); 6131 6132 if (set_cond_codes) { 6133 // Special hack for the AD files: rdi is guaranteed non-zero. 6134 assert(!pushed_rdi, "rdi must be left non-NULL"); 6135 // Also, the condition codes are properly set Z/NZ on succeed/failure. 6136 } 6137 6138 if (L_failure == &L_fallthrough) 6139 jccb(Assembler::notEqual, *L_failure); 6140 else jcc(Assembler::notEqual, *L_failure); 6141 6142 // Success. Cache the super we found and proceed in triumph. 6143 movptr(super_cache_addr, super_klass); 6144 6145 if (L_success != &L_fallthrough) { 6146 jmp(*L_success); 6147 } 6148 6149 #undef IS_A_TEMP 6150 6151 bind(L_fallthrough); 6152 } 6153 6154 6155 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 6156 if (VM_Version::supports_cmov()) { 6157 cmovl(cc, dst, src); 6158 } else { 6159 Label L; 6160 jccb(negate_condition(cc), L); 6161 movl(dst, src); 6162 bind(L); 6163 } 6164 } 6165 6166 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 6167 if (VM_Version::supports_cmov()) { 6168 cmovl(cc, dst, src); 6169 } else { 6170 Label L; 6171 jccb(negate_condition(cc), L); 6172 movl(dst, src); 6173 bind(L); 6174 } 6175 } 6176 6177 void MacroAssembler::verify_oop(Register reg, const char* s) { 6178 if (!VerifyOops) return; 6179 6180 // Pass register number to verify_oop_subroutine 6181 const char* b = NULL; 6182 { 6183 ResourceMark rm; 6184 stringStream ss; 6185 ss.print("verify_oop: %s: %s", reg->name(), s); 6186 b = code_string(ss.as_string()); 6187 } 6188 BLOCK_COMMENT("verify_oop {"); 6189 #ifdef _LP64 6190 push(rscratch1); // save r10, trashed by movptr() 6191 #endif 6192 push(rax); // save rax, 6193 push(reg); // pass register argument 6194 ExternalAddress buffer((address) b); 6195 // avoid using pushptr, as it modifies scratch registers 6196 // and our contract is not to modify anything 6197 movptr(rax, buffer.addr()); 6198 push(rax); 6199 // call indirectly to solve generation ordering problem 6200 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6201 call(rax); 6202 // Caller pops the arguments (oop, message) and restores rax, r10 6203 BLOCK_COMMENT("} verify_oop"); 6204 } 6205 6206 6207 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6208 Register tmp, 6209 int offset) { 6210 intptr_t value = *delayed_value_addr; 6211 if (value != 0) 6212 return RegisterOrConstant(value + offset); 6213 6214 // load indirectly to solve generation ordering problem 6215 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6216 6217 #ifdef ASSERT 6218 { Label L; 6219 testptr(tmp, tmp); 6220 if (WizardMode) { 6221 const char* buf = NULL; 6222 { 6223 ResourceMark rm; 6224 stringStream ss; 6225 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6226 buf = code_string(ss.as_string()); 6227 } 6228 jcc(Assembler::notZero, L); 6229 STOP(buf); 6230 } else { 6231 jccb(Assembler::notZero, L); 6232 hlt(); 6233 } 6234 bind(L); 6235 } 6236 #endif 6237 6238 if (offset != 0) 6239 addptr(tmp, offset); 6240 6241 return RegisterOrConstant(tmp); 6242 } 6243 6244 6245 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6246 int extra_slot_offset) { 6247 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6248 int stackElementSize = Interpreter::stackElementSize; 6249 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6250 #ifdef ASSERT 6251 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6252 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6253 #endif 6254 Register scale_reg = noreg; 6255 Address::ScaleFactor scale_factor = Address::no_scale; 6256 if (arg_slot.is_constant()) { 6257 offset += arg_slot.as_constant() * stackElementSize; 6258 } else { 6259 scale_reg = arg_slot.as_register(); 6260 scale_factor = Address::times(stackElementSize); 6261 } 6262 offset += wordSize; // return PC is on stack 6263 return Address(rsp, scale_reg, scale_factor, offset); 6264 } 6265 6266 6267 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6268 if (!VerifyOops) return; 6269 6270 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6271 // Pass register number to verify_oop_subroutine 6272 const char* b = NULL; 6273 { 6274 ResourceMark rm; 6275 stringStream ss; 6276 ss.print("verify_oop_addr: %s", s); 6277 b = code_string(ss.as_string()); 6278 } 6279 #ifdef _LP64 6280 push(rscratch1); // save r10, trashed by movptr() 6281 #endif 6282 push(rax); // save rax, 6283 // addr may contain rsp so we will have to adjust it based on the push 6284 // we just did (and on 64 bit we do two pushes) 6285 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6286 // stores rax into addr which is backwards of what was intended. 6287 if (addr.uses(rsp)) { 6288 lea(rax, addr); 6289 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6290 } else { 6291 pushptr(addr); 6292 } 6293 6294 ExternalAddress buffer((address) b); 6295 // pass msg argument 6296 // avoid using pushptr, as it modifies scratch registers 6297 // and our contract is not to modify anything 6298 movptr(rax, buffer.addr()); 6299 push(rax); 6300 6301 // call indirectly to solve generation ordering problem 6302 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6303 call(rax); 6304 // Caller pops the arguments (addr, message) and restores rax, r10. 6305 } 6306 6307 void MacroAssembler::verify_tlab() { 6308 #ifdef ASSERT 6309 if (UseTLAB && VerifyOops) { 6310 Label next, ok; 6311 Register t1 = rsi; 6312 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6313 6314 push(t1); 6315 NOT_LP64(push(thread_reg)); 6316 NOT_LP64(get_thread(thread_reg)); 6317 6318 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6319 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6320 jcc(Assembler::aboveEqual, next); 6321 STOP("assert(top >= start)"); 6322 should_not_reach_here(); 6323 6324 bind(next); 6325 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6326 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6327 jcc(Assembler::aboveEqual, ok); 6328 STOP("assert(top <= end)"); 6329 should_not_reach_here(); 6330 6331 bind(ok); 6332 NOT_LP64(pop(thread_reg)); 6333 pop(t1); 6334 } 6335 #endif 6336 } 6337 6338 class ControlWord { 6339 public: 6340 int32_t _value; 6341 6342 int rounding_control() const { return (_value >> 10) & 3 ; } 6343 int precision_control() const { return (_value >> 8) & 3 ; } 6344 bool precision() const { return ((_value >> 5) & 1) != 0; } 6345 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6346 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6347 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6348 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6349 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6350 6351 void print() const { 6352 // rounding control 6353 const char* rc; 6354 switch (rounding_control()) { 6355 case 0: rc = "round near"; break; 6356 case 1: rc = "round down"; break; 6357 case 2: rc = "round up "; break; 6358 case 3: rc = "chop "; break; 6359 }; 6360 // precision control 6361 const char* pc; 6362 switch (precision_control()) { 6363 case 0: pc = "24 bits "; break; 6364 case 1: pc = "reserved"; break; 6365 case 2: pc = "53 bits "; break; 6366 case 3: pc = "64 bits "; break; 6367 }; 6368 // flags 6369 char f[9]; 6370 f[0] = ' '; 6371 f[1] = ' '; 6372 f[2] = (precision ()) ? 'P' : 'p'; 6373 f[3] = (underflow ()) ? 'U' : 'u'; 6374 f[4] = (overflow ()) ? 'O' : 'o'; 6375 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6376 f[6] = (denormalized()) ? 'D' : 'd'; 6377 f[7] = (invalid ()) ? 'I' : 'i'; 6378 f[8] = '\x0'; 6379 // output 6380 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6381 } 6382 6383 }; 6384 6385 class StatusWord { 6386 public: 6387 int32_t _value; 6388 6389 bool busy() const { return ((_value >> 15) & 1) != 0; } 6390 bool C3() const { return ((_value >> 14) & 1) != 0; } 6391 bool C2() const { return ((_value >> 10) & 1) != 0; } 6392 bool C1() const { return ((_value >> 9) & 1) != 0; } 6393 bool C0() const { return ((_value >> 8) & 1) != 0; } 6394 int top() const { return (_value >> 11) & 7 ; } 6395 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6396 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6397 bool precision() const { return ((_value >> 5) & 1) != 0; } 6398 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6399 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6400 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6401 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6402 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6403 6404 void print() const { 6405 // condition codes 6406 char c[5]; 6407 c[0] = (C3()) ? '3' : '-'; 6408 c[1] = (C2()) ? '2' : '-'; 6409 c[2] = (C1()) ? '1' : '-'; 6410 c[3] = (C0()) ? '0' : '-'; 6411 c[4] = '\x0'; 6412 // flags 6413 char f[9]; 6414 f[0] = (error_status()) ? 'E' : '-'; 6415 f[1] = (stack_fault ()) ? 'S' : '-'; 6416 f[2] = (precision ()) ? 'P' : '-'; 6417 f[3] = (underflow ()) ? 'U' : '-'; 6418 f[4] = (overflow ()) ? 'O' : '-'; 6419 f[5] = (zero_divide ()) ? 'Z' : '-'; 6420 f[6] = (denormalized()) ? 'D' : '-'; 6421 f[7] = (invalid ()) ? 'I' : '-'; 6422 f[8] = '\x0'; 6423 // output 6424 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6425 } 6426 6427 }; 6428 6429 class TagWord { 6430 public: 6431 int32_t _value; 6432 6433 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6434 6435 void print() const { 6436 printf("%04x", _value & 0xFFFF); 6437 } 6438 6439 }; 6440 6441 class FPU_Register { 6442 public: 6443 int32_t _m0; 6444 int32_t _m1; 6445 int16_t _ex; 6446 6447 bool is_indefinite() const { 6448 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6449 } 6450 6451 void print() const { 6452 char sign = (_ex < 0) ? '-' : '+'; 6453 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6454 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6455 }; 6456 6457 }; 6458 6459 class FPU_State { 6460 public: 6461 enum { 6462 register_size = 10, 6463 number_of_registers = 8, 6464 register_mask = 7 6465 }; 6466 6467 ControlWord _control_word; 6468 StatusWord _status_word; 6469 TagWord _tag_word; 6470 int32_t _error_offset; 6471 int32_t _error_selector; 6472 int32_t _data_offset; 6473 int32_t _data_selector; 6474 int8_t _register[register_size * number_of_registers]; 6475 6476 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6477 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6478 6479 const char* tag_as_string(int tag) const { 6480 switch (tag) { 6481 case 0: return "valid"; 6482 case 1: return "zero"; 6483 case 2: return "special"; 6484 case 3: return "empty"; 6485 } 6486 ShouldNotReachHere(); 6487 return NULL; 6488 } 6489 6490 void print() const { 6491 // print computation registers 6492 { int t = _status_word.top(); 6493 for (int i = 0; i < number_of_registers; i++) { 6494 int j = (i - t) & register_mask; 6495 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6496 st(j)->print(); 6497 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6498 } 6499 } 6500 printf("\n"); 6501 // print control registers 6502 printf("ctrl = "); _control_word.print(); printf("\n"); 6503 printf("stat = "); _status_word .print(); printf("\n"); 6504 printf("tags = "); _tag_word .print(); printf("\n"); 6505 } 6506 6507 }; 6508 6509 class Flag_Register { 6510 public: 6511 int32_t _value; 6512 6513 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6514 bool direction() const { return ((_value >> 10) & 1) != 0; } 6515 bool sign() const { return ((_value >> 7) & 1) != 0; } 6516 bool zero() const { return ((_value >> 6) & 1) != 0; } 6517 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6518 bool parity() const { return ((_value >> 2) & 1) != 0; } 6519 bool carry() const { return ((_value >> 0) & 1) != 0; } 6520 6521 void print() const { 6522 // flags 6523 char f[8]; 6524 f[0] = (overflow ()) ? 'O' : '-'; 6525 f[1] = (direction ()) ? 'D' : '-'; 6526 f[2] = (sign ()) ? 'S' : '-'; 6527 f[3] = (zero ()) ? 'Z' : '-'; 6528 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6529 f[5] = (parity ()) ? 'P' : '-'; 6530 f[6] = (carry ()) ? 'C' : '-'; 6531 f[7] = '\x0'; 6532 // output 6533 printf("%08x flags = %s", _value, f); 6534 } 6535 6536 }; 6537 6538 class IU_Register { 6539 public: 6540 int32_t _value; 6541 6542 void print() const { 6543 printf("%08x %11d", _value, _value); 6544 } 6545 6546 }; 6547 6548 class IU_State { 6549 public: 6550 Flag_Register _eflags; 6551 IU_Register _rdi; 6552 IU_Register _rsi; 6553 IU_Register _rbp; 6554 IU_Register _rsp; 6555 IU_Register _rbx; 6556 IU_Register _rdx; 6557 IU_Register _rcx; 6558 IU_Register _rax; 6559 6560 void print() const { 6561 // computation registers 6562 printf("rax, = "); _rax.print(); printf("\n"); 6563 printf("rbx, = "); _rbx.print(); printf("\n"); 6564 printf("rcx = "); _rcx.print(); printf("\n"); 6565 printf("rdx = "); _rdx.print(); printf("\n"); 6566 printf("rdi = "); _rdi.print(); printf("\n"); 6567 printf("rsi = "); _rsi.print(); printf("\n"); 6568 printf("rbp, = "); _rbp.print(); printf("\n"); 6569 printf("rsp = "); _rsp.print(); printf("\n"); 6570 printf("\n"); 6571 // control registers 6572 printf("flgs = "); _eflags.print(); printf("\n"); 6573 } 6574 }; 6575 6576 6577 class CPU_State { 6578 public: 6579 FPU_State _fpu_state; 6580 IU_State _iu_state; 6581 6582 void print() const { 6583 printf("--------------------------------------------------\n"); 6584 _iu_state .print(); 6585 printf("\n"); 6586 _fpu_state.print(); 6587 printf("--------------------------------------------------\n"); 6588 } 6589 6590 }; 6591 6592 6593 static void _print_CPU_state(CPU_State* state) { 6594 state->print(); 6595 }; 6596 6597 6598 void MacroAssembler::print_CPU_state() { 6599 push_CPU_state(); 6600 push(rsp); // pass CPU state 6601 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6602 addptr(rsp, wordSize); // discard argument 6603 pop_CPU_state(); 6604 } 6605 6606 6607 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6608 static int counter = 0; 6609 FPU_State* fs = &state->_fpu_state; 6610 counter++; 6611 // For leaf calls, only verify that the top few elements remain empty. 6612 // We only need 1 empty at the top for C2 code. 6613 if( stack_depth < 0 ) { 6614 if( fs->tag_for_st(7) != 3 ) { 6615 printf("FPR7 not empty\n"); 6616 state->print(); 6617 assert(false, "error"); 6618 return false; 6619 } 6620 return true; // All other stack states do not matter 6621 } 6622 6623 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6624 "bad FPU control word"); 6625 6626 // compute stack depth 6627 int i = 0; 6628 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6629 int d = i; 6630 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6631 // verify findings 6632 if (i != FPU_State::number_of_registers) { 6633 // stack not contiguous 6634 printf("%s: stack not contiguous at ST%d\n", s, i); 6635 state->print(); 6636 assert(false, "error"); 6637 return false; 6638 } 6639 // check if computed stack depth corresponds to expected stack depth 6640 if (stack_depth < 0) { 6641 // expected stack depth is -stack_depth or less 6642 if (d > -stack_depth) { 6643 // too many elements on the stack 6644 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6645 state->print(); 6646 assert(false, "error"); 6647 return false; 6648 } 6649 } else { 6650 // expected stack depth is stack_depth 6651 if (d != stack_depth) { 6652 // wrong stack depth 6653 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6654 state->print(); 6655 assert(false, "error"); 6656 return false; 6657 } 6658 } 6659 // everything is cool 6660 return true; 6661 } 6662 6663 6664 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6665 if (!VerifyFPU) return; 6666 push_CPU_state(); 6667 push(rsp); // pass CPU state 6668 ExternalAddress msg((address) s); 6669 // pass message string s 6670 pushptr(msg.addr()); 6671 push(stack_depth); // pass stack depth 6672 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6673 addptr(rsp, 3 * wordSize); // discard arguments 6674 // check for error 6675 { Label L; 6676 testl(rax, rax); 6677 jcc(Assembler::notZero, L); 6678 int3(); // break if error condition 6679 bind(L); 6680 } 6681 pop_CPU_state(); 6682 } 6683 6684 void MacroAssembler::restore_cpu_control_state_after_jni() { 6685 // Either restore the MXCSR register after returning from the JNI Call 6686 // or verify that it wasn't changed (with -Xcheck:jni flag). 6687 if (VM_Version::supports_sse()) { 6688 if (RestoreMXCSROnJNICalls) { 6689 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6690 } else if (CheckJNICalls) { 6691 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6692 } 6693 } 6694 if (VM_Version::supports_avx()) { 6695 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6696 vzeroupper(); 6697 } 6698 6699 #ifndef _LP64 6700 // Either restore the x87 floating pointer control word after returning 6701 // from the JNI call or verify that it wasn't changed. 6702 if (CheckJNICalls) { 6703 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6704 } 6705 #endif // _LP64 6706 } 6707 6708 6709 void MacroAssembler::load_klass(Register dst, Register src) { 6710 #ifdef _LP64 6711 if (UseCompressedClassPointers) { 6712 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6713 decode_klass_not_null(dst); 6714 } else 6715 #endif 6716 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6717 } 6718 6719 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6720 load_klass(dst, src); 6721 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6722 } 6723 6724 void MacroAssembler::store_klass(Register dst, Register src) { 6725 #ifdef _LP64 6726 if (UseCompressedClassPointers) { 6727 encode_klass_not_null(src); 6728 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6729 } else 6730 #endif 6731 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6732 } 6733 6734 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6735 #ifdef _LP64 6736 // FIXME: Must change all places where we try to load the klass. 6737 if (UseCompressedOops) { 6738 movl(dst, src); 6739 decode_heap_oop(dst); 6740 } else 6741 #endif 6742 movptr(dst, src); 6743 } 6744 6745 // Doesn't do verfication, generates fixed size code 6746 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6747 #ifdef _LP64 6748 if (UseCompressedOops) { 6749 movl(dst, src); 6750 decode_heap_oop_not_null(dst); 6751 } else 6752 #endif 6753 movptr(dst, src); 6754 } 6755 6756 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6757 #ifdef _LP64 6758 if (UseCompressedOops) { 6759 assert(!dst.uses(src), "not enough registers"); 6760 encode_heap_oop(src); 6761 movl(dst, src); 6762 } else 6763 #endif 6764 movptr(dst, src); 6765 } 6766 6767 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6768 assert_different_registers(src1, tmp); 6769 #ifdef _LP64 6770 if (UseCompressedOops) { 6771 bool did_push = false; 6772 if (tmp == noreg) { 6773 tmp = rax; 6774 push(tmp); 6775 did_push = true; 6776 assert(!src2.uses(rsp), "can't push"); 6777 } 6778 load_heap_oop(tmp, src2); 6779 cmpptr(src1, tmp); 6780 if (did_push) pop(tmp); 6781 } else 6782 #endif 6783 cmpptr(src1, src2); 6784 } 6785 6786 // Used for storing NULLs. 6787 void MacroAssembler::store_heap_oop_null(Address dst) { 6788 #ifdef _LP64 6789 if (UseCompressedOops) { 6790 movl(dst, (int32_t)NULL_WORD); 6791 } else { 6792 movslq(dst, (int32_t)NULL_WORD); 6793 } 6794 #else 6795 movl(dst, (int32_t)NULL_WORD); 6796 #endif 6797 } 6798 6799 #ifdef _LP64 6800 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6801 if (UseCompressedClassPointers) { 6802 // Store to klass gap in destination 6803 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6804 } 6805 } 6806 6807 #ifdef ASSERT 6808 void MacroAssembler::verify_heapbase(const char* msg) { 6809 assert (UseCompressedOops, "should be compressed"); 6810 assert (Universe::heap() != NULL, "java heap should be initialized"); 6811 if (CheckCompressedOops) { 6812 Label ok; 6813 push(rscratch1); // cmpptr trashes rscratch1 6814 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6815 jcc(Assembler::equal, ok); 6816 STOP(msg); 6817 bind(ok); 6818 pop(rscratch1); 6819 } 6820 } 6821 #endif 6822 6823 // Algorithm must match oop.inline.hpp encode_heap_oop. 6824 void MacroAssembler::encode_heap_oop(Register r) { 6825 #ifdef ASSERT 6826 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6827 #endif 6828 verify_oop(r, "broken oop in encode_heap_oop"); 6829 if (Universe::narrow_oop_base() == NULL) { 6830 if (Universe::narrow_oop_shift() != 0) { 6831 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6832 shrq(r, LogMinObjAlignmentInBytes); 6833 } 6834 return; 6835 } 6836 testq(r, r); 6837 cmovq(Assembler::equal, r, r12_heapbase); 6838 subq(r, r12_heapbase); 6839 shrq(r, LogMinObjAlignmentInBytes); 6840 } 6841 6842 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6843 #ifdef ASSERT 6844 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6845 if (CheckCompressedOops) { 6846 Label ok; 6847 testq(r, r); 6848 jcc(Assembler::notEqual, ok); 6849 STOP("null oop passed to encode_heap_oop_not_null"); 6850 bind(ok); 6851 } 6852 #endif 6853 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6854 if (Universe::narrow_oop_base() != NULL) { 6855 subq(r, r12_heapbase); 6856 } 6857 if (Universe::narrow_oop_shift() != 0) { 6858 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6859 shrq(r, LogMinObjAlignmentInBytes); 6860 } 6861 } 6862 6863 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6864 #ifdef ASSERT 6865 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6866 if (CheckCompressedOops) { 6867 Label ok; 6868 testq(src, src); 6869 jcc(Assembler::notEqual, ok); 6870 STOP("null oop passed to encode_heap_oop_not_null2"); 6871 bind(ok); 6872 } 6873 #endif 6874 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6875 if (dst != src) { 6876 movq(dst, src); 6877 } 6878 if (Universe::narrow_oop_base() != NULL) { 6879 subq(dst, r12_heapbase); 6880 } 6881 if (Universe::narrow_oop_shift() != 0) { 6882 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6883 shrq(dst, LogMinObjAlignmentInBytes); 6884 } 6885 } 6886 6887 void MacroAssembler::decode_heap_oop(Register r) { 6888 #ifdef ASSERT 6889 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6890 #endif 6891 if (Universe::narrow_oop_base() == NULL) { 6892 if (Universe::narrow_oop_shift() != 0) { 6893 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6894 shlq(r, LogMinObjAlignmentInBytes); 6895 } 6896 } else { 6897 Label done; 6898 shlq(r, LogMinObjAlignmentInBytes); 6899 jccb(Assembler::equal, done); 6900 addq(r, r12_heapbase); 6901 bind(done); 6902 } 6903 verify_oop(r, "broken oop in decode_heap_oop"); 6904 } 6905 6906 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6907 // Note: it will change flags 6908 assert (UseCompressedOops, "should only be used for compressed headers"); 6909 assert (Universe::heap() != NULL, "java heap should be initialized"); 6910 // Cannot assert, unverified entry point counts instructions (see .ad file) 6911 // vtableStubs also counts instructions in pd_code_size_limit. 6912 // Also do not verify_oop as this is called by verify_oop. 6913 if (Universe::narrow_oop_shift() != 0) { 6914 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6915 shlq(r, LogMinObjAlignmentInBytes); 6916 if (Universe::narrow_oop_base() != NULL) { 6917 addq(r, r12_heapbase); 6918 } 6919 } else { 6920 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6921 } 6922 } 6923 6924 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6925 // Note: it will change flags 6926 assert (UseCompressedOops, "should only be used for compressed headers"); 6927 assert (Universe::heap() != NULL, "java heap should be initialized"); 6928 // Cannot assert, unverified entry point counts instructions (see .ad file) 6929 // vtableStubs also counts instructions in pd_code_size_limit. 6930 // Also do not verify_oop as this is called by verify_oop. 6931 if (Universe::narrow_oop_shift() != 0) { 6932 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6933 if (LogMinObjAlignmentInBytes == Address::times_8) { 6934 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6935 } else { 6936 if (dst != src) { 6937 movq(dst, src); 6938 } 6939 shlq(dst, LogMinObjAlignmentInBytes); 6940 if (Universe::narrow_oop_base() != NULL) { 6941 addq(dst, r12_heapbase); 6942 } 6943 } 6944 } else { 6945 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6946 if (dst != src) { 6947 movq(dst, src); 6948 } 6949 } 6950 } 6951 6952 void MacroAssembler::encode_klass_not_null(Register r) { 6953 if (Universe::narrow_klass_base() != NULL) { 6954 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6955 assert(r != r12_heapbase, "Encoding a klass in r12"); 6956 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6957 subq(r, r12_heapbase); 6958 } 6959 if (Universe::narrow_klass_shift() != 0) { 6960 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6961 shrq(r, LogKlassAlignmentInBytes); 6962 } 6963 if (Universe::narrow_klass_base() != NULL) { 6964 reinit_heapbase(); 6965 } 6966 } 6967 6968 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6969 if (dst == src) { 6970 encode_klass_not_null(src); 6971 } else { 6972 if (Universe::narrow_klass_base() != NULL) { 6973 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6974 negq(dst); 6975 addq(dst, src); 6976 } else { 6977 movptr(dst, src); 6978 } 6979 if (Universe::narrow_klass_shift() != 0) { 6980 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6981 shrq(dst, LogKlassAlignmentInBytes); 6982 } 6983 } 6984 } 6985 6986 // Function instr_size_for_decode_klass_not_null() counts the instructions 6987 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6988 // when (Universe::heap() != NULL). Hence, if the instructions they 6989 // generate change, then this method needs to be updated. 6990 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6991 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6992 if (Universe::narrow_klass_base() != NULL) { 6993 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6994 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6995 } else { 6996 // longest load decode klass function, mov64, leaq 6997 return 16; 6998 } 6999 } 7000 7001 // !!! If the instructions that get generated here change then function 7002 // instr_size_for_decode_klass_not_null() needs to get updated. 7003 void MacroAssembler::decode_klass_not_null(Register r) { 7004 // Note: it will change flags 7005 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7006 assert(r != r12_heapbase, "Decoding a klass in r12"); 7007 // Cannot assert, unverified entry point counts instructions (see .ad file) 7008 // vtableStubs also counts instructions in pd_code_size_limit. 7009 // Also do not verify_oop as this is called by verify_oop. 7010 if (Universe::narrow_klass_shift() != 0) { 7011 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 7012 shlq(r, LogKlassAlignmentInBytes); 7013 } 7014 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 7015 if (Universe::narrow_klass_base() != NULL) { 7016 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 7017 addq(r, r12_heapbase); 7018 reinit_heapbase(); 7019 } 7020 } 7021 7022 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 7023 // Note: it will change flags 7024 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7025 if (dst == src) { 7026 decode_klass_not_null(dst); 7027 } else { 7028 // Cannot assert, unverified entry point counts instructions (see .ad file) 7029 // vtableStubs also counts instructions in pd_code_size_limit. 7030 // Also do not verify_oop as this is called by verify_oop. 7031 mov64(dst, (int64_t)Universe::narrow_klass_base()); 7032 if (Universe::narrow_klass_shift() != 0) { 7033 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 7034 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 7035 leaq(dst, Address(dst, src, Address::times_8, 0)); 7036 } else { 7037 addq(dst, src); 7038 } 7039 } 7040 } 7041 7042 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 7043 assert (UseCompressedOops, "should only be used for compressed headers"); 7044 assert (Universe::heap() != NULL, "java heap should be initialized"); 7045 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7046 int oop_index = oop_recorder()->find_index(obj); 7047 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7048 mov_narrow_oop(dst, oop_index, rspec); 7049 } 7050 7051 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 7052 assert (UseCompressedOops, "should only be used for compressed headers"); 7053 assert (Universe::heap() != NULL, "java heap should be initialized"); 7054 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7055 int oop_index = oop_recorder()->find_index(obj); 7056 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7057 mov_narrow_oop(dst, oop_index, rspec); 7058 } 7059 7060 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 7061 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7062 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7063 int klass_index = oop_recorder()->find_index(k); 7064 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7065 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7066 } 7067 7068 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 7069 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7070 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7071 int klass_index = oop_recorder()->find_index(k); 7072 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7073 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7074 } 7075 7076 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 7077 assert (UseCompressedOops, "should only be used for compressed headers"); 7078 assert (Universe::heap() != NULL, "java heap should be initialized"); 7079 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7080 int oop_index = oop_recorder()->find_index(obj); 7081 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7082 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7083 } 7084 7085 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 7086 assert (UseCompressedOops, "should only be used for compressed headers"); 7087 assert (Universe::heap() != NULL, "java heap should be initialized"); 7088 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7089 int oop_index = oop_recorder()->find_index(obj); 7090 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7091 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7092 } 7093 7094 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 7095 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7096 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7097 int klass_index = oop_recorder()->find_index(k); 7098 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7099 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7100 } 7101 7102 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 7103 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7104 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7105 int klass_index = oop_recorder()->find_index(k); 7106 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7107 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7108 } 7109 7110 void MacroAssembler::reinit_heapbase() { 7111 if (UseCompressedOops || UseCompressedClassPointers) { 7112 if (Universe::heap() != NULL) { 7113 if (Universe::narrow_oop_base() == NULL) { 7114 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 7115 } else { 7116 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 7117 } 7118 } else { 7119 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 7120 } 7121 } 7122 } 7123 7124 #endif // _LP64 7125 7126 7127 // C2 compiled method's prolog code. 7128 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 7129 7130 // WARNING: Initial instruction MUST be 5 bytes or longer so that 7131 // NativeJump::patch_verified_entry will be able to patch out the entry 7132 // code safely. The push to verify stack depth is ok at 5 bytes, 7133 // the frame allocation can be either 3 or 6 bytes. So if we don't do 7134 // stack bang then we must use the 6 byte frame allocation even if 7135 // we have no frame. :-( 7136 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 7137 7138 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 7139 // Remove word for return addr 7140 framesize -= wordSize; 7141 stack_bang_size -= wordSize; 7142 7143 // Calls to C2R adapters often do not accept exceptional returns. 7144 // We require that their callers must bang for them. But be careful, because 7145 // some VM calls (such as call site linkage) can use several kilobytes of 7146 // stack. But the stack safety zone should account for that. 7147 // See bugs 4446381, 4468289, 4497237. 7148 if (stack_bang_size > 0) { 7149 generate_stack_overflow_check(stack_bang_size); 7150 7151 // We always push rbp, so that on return to interpreter rbp, will be 7152 // restored correctly and we can correct the stack. 7153 push(rbp); 7154 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7155 if (PreserveFramePointer) { 7156 mov(rbp, rsp); 7157 } 7158 // Remove word for ebp 7159 framesize -= wordSize; 7160 7161 // Create frame 7162 if (framesize) { 7163 subptr(rsp, framesize); 7164 } 7165 } else { 7166 // Create frame (force generation of a 4 byte immediate value) 7167 subptr_imm32(rsp, framesize); 7168 7169 // Save RBP register now. 7170 framesize -= wordSize; 7171 movptr(Address(rsp, framesize), rbp); 7172 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7173 if (PreserveFramePointer) { 7174 movptr(rbp, rsp); 7175 if (framesize > 0) { 7176 addptr(rbp, framesize); 7177 } 7178 } 7179 } 7180 7181 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 7182 framesize -= wordSize; 7183 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 7184 } 7185 7186 #ifndef _LP64 7187 // If method sets FPU control word do it now 7188 if (fp_mode_24b) { 7189 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 7190 } 7191 if (UseSSE >= 2 && VerifyFPU) { 7192 verify_FPU(0, "FPU stack must be clean on entry"); 7193 } 7194 #endif 7195 7196 #ifdef ASSERT 7197 if (VerifyStackAtCalls) { 7198 Label L; 7199 push(rax); 7200 mov(rax, rsp); 7201 andptr(rax, StackAlignmentInBytes-1); 7202 cmpptr(rax, StackAlignmentInBytes-wordSize); 7203 pop(rax); 7204 jcc(Assembler::equal, L); 7205 STOP("Stack is not properly aligned!"); 7206 bind(L); 7207 } 7208 #endif 7209 7210 } 7211 7212 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7213 // cnt - number of qwords (8-byte words). 7214 // base - start address, qword aligned. 7215 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7216 assert(base==rdi, "base register must be edi for rep stos"); 7217 assert(tmp==rax, "tmp register must be eax for rep stos"); 7218 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7219 assert(InitArrayShortSize % BytesPerLong == 0, 7220 "InitArrayShortSize should be the multiple of BytesPerLong"); 7221 7222 Label DONE; 7223 7224 xorptr(tmp, tmp); 7225 7226 if (!is_large) { 7227 Label LOOP, LONG; 7228 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7229 jccb(Assembler::greater, LONG); 7230 7231 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7232 7233 decrement(cnt); 7234 jccb(Assembler::negative, DONE); // Zero length 7235 7236 // Use individual pointer-sized stores for small counts: 7237 BIND(LOOP); 7238 movptr(Address(base, cnt, Address::times_ptr), tmp); 7239 decrement(cnt); 7240 jccb(Assembler::greaterEqual, LOOP); 7241 jmpb(DONE); 7242 7243 BIND(LONG); 7244 } 7245 7246 // Use longer rep-prefixed ops for non-small counts: 7247 if (UseFastStosb) { 7248 shlptr(cnt, 3); // convert to number of bytes 7249 rep_stosb(); 7250 } else { 7251 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7252 rep_stos(); 7253 } 7254 7255 BIND(DONE); 7256 } 7257 7258 #ifdef COMPILER2 7259 7260 // IndexOf for constant substrings with size >= 8 chars 7261 // which don't need to be loaded through stack. 7262 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7263 Register cnt1, Register cnt2, 7264 int int_cnt2, Register result, 7265 XMMRegister vec, Register tmp, 7266 int ae) { 7267 ShortBranchVerifier sbv(this); 7268 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7269 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7270 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7271 7272 // This method uses the pcmpestri instruction with bound registers 7273 // inputs: 7274 // xmm - substring 7275 // rax - substring length (elements count) 7276 // mem - scanned string 7277 // rdx - string length (elements count) 7278 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7279 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7280 // outputs: 7281 // rcx - matched index in string 7282 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7283 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7284 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7285 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7286 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7287 7288 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7289 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7290 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7291 7292 // Note, inline_string_indexOf() generates checks: 7293 // if (substr.count > string.count) return -1; 7294 // if (substr.count == 0) return 0; 7295 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7296 7297 // Load substring. 7298 if (ae == StrIntrinsicNode::UL) { 7299 pmovzxbw(vec, Address(str2, 0)); 7300 } else { 7301 movdqu(vec, Address(str2, 0)); 7302 } 7303 movl(cnt2, int_cnt2); 7304 movptr(result, str1); // string addr 7305 7306 if (int_cnt2 > stride) { 7307 jmpb(SCAN_TO_SUBSTR); 7308 7309 // Reload substr for rescan, this code 7310 // is executed only for large substrings (> 8 chars) 7311 bind(RELOAD_SUBSTR); 7312 if (ae == StrIntrinsicNode::UL) { 7313 pmovzxbw(vec, Address(str2, 0)); 7314 } else { 7315 movdqu(vec, Address(str2, 0)); 7316 } 7317 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7318 7319 bind(RELOAD_STR); 7320 // We came here after the beginning of the substring was 7321 // matched but the rest of it was not so we need to search 7322 // again. Start from the next element after the previous match. 7323 7324 // cnt2 is number of substring reminding elements and 7325 // cnt1 is number of string reminding elements when cmp failed. 7326 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7327 subl(cnt1, cnt2); 7328 addl(cnt1, int_cnt2); 7329 movl(cnt2, int_cnt2); // Now restore cnt2 7330 7331 decrementl(cnt1); // Shift to next element 7332 cmpl(cnt1, cnt2); 7333 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7334 7335 addptr(result, (1<<scale1)); 7336 7337 } // (int_cnt2 > 8) 7338 7339 // Scan string for start of substr in 16-byte vectors 7340 bind(SCAN_TO_SUBSTR); 7341 pcmpestri(vec, Address(result, 0), mode); 7342 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7343 subl(cnt1, stride); 7344 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7345 cmpl(cnt1, cnt2); 7346 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7347 addptr(result, 16); 7348 jmpb(SCAN_TO_SUBSTR); 7349 7350 // Found a potential substr 7351 bind(FOUND_CANDIDATE); 7352 // Matched whole vector if first element matched (tmp(rcx) == 0). 7353 if (int_cnt2 == stride) { 7354 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7355 } else { // int_cnt2 > 8 7356 jccb(Assembler::overflow, FOUND_SUBSTR); 7357 } 7358 // After pcmpestri tmp(rcx) contains matched element index 7359 // Compute start addr of substr 7360 lea(result, Address(result, tmp, scale1)); 7361 7362 // Make sure string is still long enough 7363 subl(cnt1, tmp); 7364 cmpl(cnt1, cnt2); 7365 if (int_cnt2 == stride) { 7366 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7367 } else { // int_cnt2 > 8 7368 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7369 } 7370 // Left less then substring. 7371 7372 bind(RET_NOT_FOUND); 7373 movl(result, -1); 7374 jmpb(EXIT); 7375 7376 if (int_cnt2 > stride) { 7377 // This code is optimized for the case when whole substring 7378 // is matched if its head is matched. 7379 bind(MATCH_SUBSTR_HEAD); 7380 pcmpestri(vec, Address(result, 0), mode); 7381 // Reload only string if does not match 7382 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 7383 7384 Label CONT_SCAN_SUBSTR; 7385 // Compare the rest of substring (> 8 chars). 7386 bind(FOUND_SUBSTR); 7387 // First 8 chars are already matched. 7388 negptr(cnt2); 7389 addptr(cnt2, stride); 7390 7391 bind(SCAN_SUBSTR); 7392 subl(cnt1, stride); 7393 cmpl(cnt2, -stride); // Do not read beyond substring 7394 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7395 // Back-up strings to avoid reading beyond substring: 7396 // cnt1 = cnt1 - cnt2 + 8 7397 addl(cnt1, cnt2); // cnt2 is negative 7398 addl(cnt1, stride); 7399 movl(cnt2, stride); negptr(cnt2); 7400 bind(CONT_SCAN_SUBSTR); 7401 if (int_cnt2 < (int)G) { 7402 int tail_off1 = int_cnt2<<scale1; 7403 int tail_off2 = int_cnt2<<scale2; 7404 if (ae == StrIntrinsicNode::UL) { 7405 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7406 } else { 7407 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7408 } 7409 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7410 } else { 7411 // calculate index in register to avoid integer overflow (int_cnt2*2) 7412 movl(tmp, int_cnt2); 7413 addptr(tmp, cnt2); 7414 if (ae == StrIntrinsicNode::UL) { 7415 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7416 } else { 7417 movdqu(vec, Address(str2, tmp, scale2, 0)); 7418 } 7419 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7420 } 7421 // Need to reload strings pointers if not matched whole vector 7422 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7423 addptr(cnt2, stride); 7424 jcc(Assembler::negative, SCAN_SUBSTR); 7425 // Fall through if found full substring 7426 7427 } // (int_cnt2 > 8) 7428 7429 bind(RET_FOUND); 7430 // Found result if we matched full small substring. 7431 // Compute substr offset 7432 subptr(result, str1); 7433 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7434 shrl(result, 1); // index 7435 } 7436 bind(EXIT); 7437 7438 } // string_indexofC8 7439 7440 // Small strings are loaded through stack if they cross page boundary. 7441 void MacroAssembler::string_indexof(Register str1, Register str2, 7442 Register cnt1, Register cnt2, 7443 int int_cnt2, Register result, 7444 XMMRegister vec, Register tmp, 7445 int ae) { 7446 ShortBranchVerifier sbv(this); 7447 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7448 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7449 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7450 7451 // 7452 // int_cnt2 is length of small (< 8 chars) constant substring 7453 // or (-1) for non constant substring in which case its length 7454 // is in cnt2 register. 7455 // 7456 // Note, inline_string_indexOf() generates checks: 7457 // if (substr.count > string.count) return -1; 7458 // if (substr.count == 0) return 0; 7459 // 7460 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7461 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7462 // This method uses the pcmpestri instruction with bound registers 7463 // inputs: 7464 // xmm - substring 7465 // rax - substring length (elements count) 7466 // mem - scanned string 7467 // rdx - string length (elements count) 7468 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7469 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7470 // outputs: 7471 // rcx - matched index in string 7472 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7473 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7474 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7475 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7476 7477 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7478 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7479 FOUND_CANDIDATE; 7480 7481 { //======================================================== 7482 // We don't know where these strings are located 7483 // and we can't read beyond them. Load them through stack. 7484 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7485 7486 movptr(tmp, rsp); // save old SP 7487 7488 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7489 if (int_cnt2 == (1>>scale2)) { // One byte 7490 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7491 load_unsigned_byte(result, Address(str2, 0)); 7492 movdl(vec, result); // move 32 bits 7493 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7494 // Not enough header space in 32-bit VM: 12+3 = 15. 7495 movl(result, Address(str2, -1)); 7496 shrl(result, 8); 7497 movdl(vec, result); // move 32 bits 7498 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7499 load_unsigned_short(result, Address(str2, 0)); 7500 movdl(vec, result); // move 32 bits 7501 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7502 movdl(vec, Address(str2, 0)); // move 32 bits 7503 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7504 movq(vec, Address(str2, 0)); // move 64 bits 7505 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7506 // Array header size is 12 bytes in 32-bit VM 7507 // + 6 bytes for 3 chars == 18 bytes, 7508 // enough space to load vec and shift. 7509 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7510 if (ae == StrIntrinsicNode::UL) { 7511 int tail_off = int_cnt2-8; 7512 pmovzxbw(vec, Address(str2, tail_off)); 7513 psrldq(vec, -2*tail_off); 7514 } 7515 else { 7516 int tail_off = int_cnt2*(1<<scale2); 7517 movdqu(vec, Address(str2, tail_off-16)); 7518 psrldq(vec, 16-tail_off); 7519 } 7520 } 7521 } else { // not constant substring 7522 cmpl(cnt2, stride); 7523 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7524 7525 // We can read beyond string if srt+16 does not cross page boundary 7526 // since heaps are aligned and mapped by pages. 7527 assert(os::vm_page_size() < (int)G, "default page should be small"); 7528 movl(result, str2); // We need only low 32 bits 7529 andl(result, (os::vm_page_size()-1)); 7530 cmpl(result, (os::vm_page_size()-16)); 7531 jccb(Assembler::belowEqual, CHECK_STR); 7532 7533 // Move small strings to stack to allow load 16 bytes into vec. 7534 subptr(rsp, 16); 7535 int stk_offset = wordSize-(1<<scale2); 7536 push(cnt2); 7537 7538 bind(COPY_SUBSTR); 7539 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7540 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7541 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7542 } else if (ae == StrIntrinsicNode::UU) { 7543 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7544 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7545 } 7546 decrement(cnt2); 7547 jccb(Assembler::notZero, COPY_SUBSTR); 7548 7549 pop(cnt2); 7550 movptr(str2, rsp); // New substring address 7551 } // non constant 7552 7553 bind(CHECK_STR); 7554 cmpl(cnt1, stride); 7555 jccb(Assembler::aboveEqual, BIG_STRINGS); 7556 7557 // Check cross page boundary. 7558 movl(result, str1); // We need only low 32 bits 7559 andl(result, (os::vm_page_size()-1)); 7560 cmpl(result, (os::vm_page_size()-16)); 7561 jccb(Assembler::belowEqual, BIG_STRINGS); 7562 7563 subptr(rsp, 16); 7564 int stk_offset = -(1<<scale1); 7565 if (int_cnt2 < 0) { // not constant 7566 push(cnt2); 7567 stk_offset += wordSize; 7568 } 7569 movl(cnt2, cnt1); 7570 7571 bind(COPY_STR); 7572 if (ae == StrIntrinsicNode::LL) { 7573 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7574 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7575 } else { 7576 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7577 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7578 } 7579 decrement(cnt2); 7580 jccb(Assembler::notZero, COPY_STR); 7581 7582 if (int_cnt2 < 0) { // not constant 7583 pop(cnt2); 7584 } 7585 movptr(str1, rsp); // New string address 7586 7587 bind(BIG_STRINGS); 7588 // Load substring. 7589 if (int_cnt2 < 0) { // -1 7590 if (ae == StrIntrinsicNode::UL) { 7591 pmovzxbw(vec, Address(str2, 0)); 7592 } else { 7593 movdqu(vec, Address(str2, 0)); 7594 } 7595 push(cnt2); // substr count 7596 push(str2); // substr addr 7597 push(str1); // string addr 7598 } else { 7599 // Small (< 8 chars) constant substrings are loaded already. 7600 movl(cnt2, int_cnt2); 7601 } 7602 push(tmp); // original SP 7603 7604 } // Finished loading 7605 7606 //======================================================== 7607 // Start search 7608 // 7609 7610 movptr(result, str1); // string addr 7611 7612 if (int_cnt2 < 0) { // Only for non constant substring 7613 jmpb(SCAN_TO_SUBSTR); 7614 7615 // SP saved at sp+0 7616 // String saved at sp+1*wordSize 7617 // Substr saved at sp+2*wordSize 7618 // Substr count saved at sp+3*wordSize 7619 7620 // Reload substr for rescan, this code 7621 // is executed only for large substrings (> 8 chars) 7622 bind(RELOAD_SUBSTR); 7623 movptr(str2, Address(rsp, 2*wordSize)); 7624 movl(cnt2, Address(rsp, 3*wordSize)); 7625 if (ae == StrIntrinsicNode::UL) { 7626 pmovzxbw(vec, Address(str2, 0)); 7627 } else { 7628 movdqu(vec, Address(str2, 0)); 7629 } 7630 // We came here after the beginning of the substring was 7631 // matched but the rest of it was not so we need to search 7632 // again. Start from the next element after the previous match. 7633 subptr(str1, result); // Restore counter 7634 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7635 shrl(str1, 1); 7636 } 7637 addl(cnt1, str1); 7638 decrementl(cnt1); // Shift to next element 7639 cmpl(cnt1, cnt2); 7640 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7641 7642 addptr(result, (1<<scale1)); 7643 } // non constant 7644 7645 // Scan string for start of substr in 16-byte vectors 7646 bind(SCAN_TO_SUBSTR); 7647 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7648 pcmpestri(vec, Address(result, 0), mode); 7649 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7650 subl(cnt1, stride); 7651 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7652 cmpl(cnt1, cnt2); 7653 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7654 addptr(result, 16); 7655 7656 bind(ADJUST_STR); 7657 cmpl(cnt1, stride); // Do not read beyond string 7658 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7659 // Back-up string to avoid reading beyond string. 7660 lea(result, Address(result, cnt1, scale1, -16)); 7661 movl(cnt1, stride); 7662 jmpb(SCAN_TO_SUBSTR); 7663 7664 // Found a potential substr 7665 bind(FOUND_CANDIDATE); 7666 // After pcmpestri tmp(rcx) contains matched element index 7667 7668 // Make sure string is still long enough 7669 subl(cnt1, tmp); 7670 cmpl(cnt1, cnt2); 7671 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7672 // Left less then substring. 7673 7674 bind(RET_NOT_FOUND); 7675 movl(result, -1); 7676 jmpb(CLEANUP); 7677 7678 bind(FOUND_SUBSTR); 7679 // Compute start addr of substr 7680 lea(result, Address(result, tmp, scale1)); 7681 if (int_cnt2 > 0) { // Constant substring 7682 // Repeat search for small substring (< 8 chars) 7683 // from new point without reloading substring. 7684 // Have to check that we don't read beyond string. 7685 cmpl(tmp, stride-int_cnt2); 7686 jccb(Assembler::greater, ADJUST_STR); 7687 // Fall through if matched whole substring. 7688 } else { // non constant 7689 assert(int_cnt2 == -1, "should be != 0"); 7690 7691 addl(tmp, cnt2); 7692 // Found result if we matched whole substring. 7693 cmpl(tmp, stride); 7694 jccb(Assembler::lessEqual, RET_FOUND); 7695 7696 // Repeat search for small substring (<= 8 chars) 7697 // from new point 'str1' without reloading substring. 7698 cmpl(cnt2, stride); 7699 // Have to check that we don't read beyond string. 7700 jccb(Assembler::lessEqual, ADJUST_STR); 7701 7702 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7703 // Compare the rest of substring (> 8 chars). 7704 movptr(str1, result); 7705 7706 cmpl(tmp, cnt2); 7707 // First 8 chars are already matched. 7708 jccb(Assembler::equal, CHECK_NEXT); 7709 7710 bind(SCAN_SUBSTR); 7711 pcmpestri(vec, Address(str1, 0), mode); 7712 // Need to reload strings pointers if not matched whole vector 7713 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7714 7715 bind(CHECK_NEXT); 7716 subl(cnt2, stride); 7717 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7718 addptr(str1, 16); 7719 if (ae == StrIntrinsicNode::UL) { 7720 addptr(str2, 8); 7721 } else { 7722 addptr(str2, 16); 7723 } 7724 subl(cnt1, stride); 7725 cmpl(cnt2, stride); // Do not read beyond substring 7726 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7727 // Back-up strings to avoid reading beyond substring. 7728 7729 if (ae == StrIntrinsicNode::UL) { 7730 lea(str2, Address(str2, cnt2, scale2, -8)); 7731 lea(str1, Address(str1, cnt2, scale1, -16)); 7732 } else { 7733 lea(str2, Address(str2, cnt2, scale2, -16)); 7734 lea(str1, Address(str1, cnt2, scale1, -16)); 7735 } 7736 subl(cnt1, cnt2); 7737 movl(cnt2, stride); 7738 addl(cnt1, stride); 7739 bind(CONT_SCAN_SUBSTR); 7740 if (ae == StrIntrinsicNode::UL) { 7741 pmovzxbw(vec, Address(str2, 0)); 7742 } else { 7743 movdqu(vec, Address(str2, 0)); 7744 } 7745 jmpb(SCAN_SUBSTR); 7746 7747 bind(RET_FOUND_LONG); 7748 movptr(str1, Address(rsp, wordSize)); 7749 } // non constant 7750 7751 bind(RET_FOUND); 7752 // Compute substr offset 7753 subptr(result, str1); 7754 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7755 shrl(result, 1); // index 7756 } 7757 bind(CLEANUP); 7758 pop(rsp); // restore SP 7759 7760 } // string_indexof 7761 7762 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7763 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7764 ShortBranchVerifier sbv(this); 7765 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7766 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7767 7768 int stride = 8; 7769 7770 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7771 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7772 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7773 FOUND_SEQ_CHAR, DONE_LABEL; 7774 7775 movptr(result, str1); 7776 if (UseAVX >= 2) { 7777 cmpl(cnt1, stride); 7778 jccb(Assembler::less, SCAN_TO_CHAR_LOOP); 7779 cmpl(cnt1, 2*stride); 7780 jccb(Assembler::less, SCAN_TO_8_CHAR_INIT); 7781 movdl(vec1, ch); 7782 vpbroadcastw(vec1, vec1); 7783 vpxor(vec2, vec2); 7784 movl(tmp, cnt1); 7785 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7786 andl(cnt1,0x0000000F); //tail count (in chars) 7787 7788 bind(SCAN_TO_16_CHAR_LOOP); 7789 vmovdqu(vec3, Address(result, 0)); 7790 vpcmpeqw(vec3, vec3, vec1, 1); 7791 vptest(vec2, vec3); 7792 jcc(Assembler::carryClear, FOUND_CHAR); 7793 addptr(result, 32); 7794 subl(tmp, 2*stride); 7795 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7796 jmp(SCAN_TO_8_CHAR); 7797 bind(SCAN_TO_8_CHAR_INIT); 7798 movdl(vec1, ch); 7799 pshuflw(vec1, vec1, 0x00); 7800 pshufd(vec1, vec1, 0); 7801 pxor(vec2, vec2); 7802 } 7803 bind(SCAN_TO_8_CHAR); 7804 cmpl(cnt1, stride); 7805 if (UseAVX >= 2) { 7806 jccb(Assembler::less, SCAN_TO_CHAR); 7807 } else { 7808 jccb(Assembler::less, SCAN_TO_CHAR_LOOP); 7809 movdl(vec1, ch); 7810 pshuflw(vec1, vec1, 0x00); 7811 pshufd(vec1, vec1, 0); 7812 pxor(vec2, vec2); 7813 } 7814 movl(tmp, cnt1); 7815 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7816 andl(cnt1,0x00000007); //tail count (in chars) 7817 7818 bind(SCAN_TO_8_CHAR_LOOP); 7819 movdqu(vec3, Address(result, 0)); 7820 pcmpeqw(vec3, vec1); 7821 ptest(vec2, vec3); 7822 jcc(Assembler::carryClear, FOUND_CHAR); 7823 addptr(result, 16); 7824 subl(tmp, stride); 7825 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7826 bind(SCAN_TO_CHAR); 7827 testl(cnt1, cnt1); 7828 jcc(Assembler::zero, RET_NOT_FOUND); 7829 bind(SCAN_TO_CHAR_LOOP); 7830 load_unsigned_short(tmp, Address(result, 0)); 7831 cmpl(ch, tmp); 7832 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7833 addptr(result, 2); 7834 subl(cnt1, 1); 7835 jccb(Assembler::zero, RET_NOT_FOUND); 7836 jmp(SCAN_TO_CHAR_LOOP); 7837 7838 bind(RET_NOT_FOUND); 7839 movl(result, -1); 7840 jmpb(DONE_LABEL); 7841 7842 bind(FOUND_CHAR); 7843 if (UseAVX >= 2) { 7844 vpmovmskb(tmp, vec3); 7845 } else { 7846 pmovmskb(tmp, vec3); 7847 } 7848 bsfl(ch, tmp); 7849 addl(result, ch); 7850 7851 bind(FOUND_SEQ_CHAR); 7852 subptr(result, str1); 7853 shrl(result, 1); 7854 7855 bind(DONE_LABEL); 7856 } // string_indexof_char 7857 7858 // helper function for string_compare 7859 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7860 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7861 Address::ScaleFactor scale2, Register index, int ae) { 7862 if (ae == StrIntrinsicNode::LL) { 7863 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7864 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7865 } else if (ae == StrIntrinsicNode::UU) { 7866 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7867 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7868 } else { 7869 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7870 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7871 } 7872 } 7873 7874 // Compare strings, used for char[] and byte[]. 7875 void MacroAssembler::string_compare(Register str1, Register str2, 7876 Register cnt1, Register cnt2, Register result, 7877 XMMRegister vec1, int ae) { 7878 ShortBranchVerifier sbv(this); 7879 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7880 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7881 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7882 int stride2x2 = 0x40; 7883 Address::ScaleFactor scale = Address::no_scale; 7884 Address::ScaleFactor scale1 = Address::no_scale; 7885 Address::ScaleFactor scale2 = Address::no_scale; 7886 7887 if (ae != StrIntrinsicNode::LL) { 7888 stride2x2 = 0x20; 7889 } 7890 7891 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7892 shrl(cnt2, 1); 7893 } 7894 // Compute the minimum of the string lengths and the 7895 // difference of the string lengths (stack). 7896 // Do the conditional move stuff 7897 movl(result, cnt1); 7898 subl(cnt1, cnt2); 7899 push(cnt1); 7900 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7901 7902 // Is the minimum length zero? 7903 testl(cnt2, cnt2); 7904 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7905 if (ae == StrIntrinsicNode::LL) { 7906 // Load first bytes 7907 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7908 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7909 } else if (ae == StrIntrinsicNode::UU) { 7910 // Load first characters 7911 load_unsigned_short(result, Address(str1, 0)); 7912 load_unsigned_short(cnt1, Address(str2, 0)); 7913 } else { 7914 load_unsigned_byte(result, Address(str1, 0)); 7915 load_unsigned_short(cnt1, Address(str2, 0)); 7916 } 7917 subl(result, cnt1); 7918 jcc(Assembler::notZero, POP_LABEL); 7919 7920 if (ae == StrIntrinsicNode::UU) { 7921 // Divide length by 2 to get number of chars 7922 shrl(cnt2, 1); 7923 } 7924 cmpl(cnt2, 1); 7925 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7926 7927 // Check if the strings start at the same location and setup scale and stride 7928 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7929 cmpptr(str1, str2); 7930 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7931 if (ae == StrIntrinsicNode::LL) { 7932 scale = Address::times_1; 7933 stride = 16; 7934 } else { 7935 scale = Address::times_2; 7936 stride = 8; 7937 } 7938 } else { 7939 scale1 = Address::times_1; 7940 scale2 = Address::times_2; 7941 // scale not used 7942 stride = 8; 7943 } 7944 7945 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7946 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7947 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7948 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7949 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7950 Label COMPARE_TAIL_LONG; 7951 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7952 7953 int pcmpmask = 0x19; 7954 if (ae == StrIntrinsicNode::LL) { 7955 pcmpmask &= ~0x01; 7956 } 7957 7958 // Setup to compare 16-chars (32-bytes) vectors, 7959 // start from first character again because it has aligned address. 7960 if (ae == StrIntrinsicNode::LL) { 7961 stride2 = 32; 7962 } else { 7963 stride2 = 16; 7964 } 7965 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7966 adr_stride = stride << scale; 7967 } else { 7968 adr_stride1 = 8; //stride << scale1; 7969 adr_stride2 = 16; //stride << scale2; 7970 } 7971 7972 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7973 // rax and rdx are used by pcmpestri as elements counters 7974 movl(result, cnt2); 7975 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7976 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7977 7978 // fast path : compare first 2 8-char vectors. 7979 bind(COMPARE_16_CHARS); 7980 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7981 movdqu(vec1, Address(str1, 0)); 7982 } else { 7983 pmovzxbw(vec1, Address(str1, 0)); 7984 } 7985 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7986 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7987 7988 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7989 movdqu(vec1, Address(str1, adr_stride)); 7990 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7991 } else { 7992 pmovzxbw(vec1, Address(str1, adr_stride1)); 7993 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7994 } 7995 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7996 addl(cnt1, stride); 7997 7998 // Compare the characters at index in cnt1 7999 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 8000 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8001 subl(result, cnt2); 8002 jmp(POP_LABEL); 8003 8004 // Setup the registers to start vector comparison loop 8005 bind(COMPARE_WIDE_VECTORS); 8006 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8007 lea(str1, Address(str1, result, scale)); 8008 lea(str2, Address(str2, result, scale)); 8009 } else { 8010 lea(str1, Address(str1, result, scale1)); 8011 lea(str2, Address(str2, result, scale2)); 8012 } 8013 subl(result, stride2); 8014 subl(cnt2, stride2); 8015 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 8016 negptr(result); 8017 8018 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 8019 bind(COMPARE_WIDE_VECTORS_LOOP); 8020 8021 #ifdef _LP64 8022 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8023 cmpl(cnt2, stride2x2); 8024 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8025 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 8026 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 8027 8028 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8029 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8030 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 8031 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 8032 } else { 8033 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 8034 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 8035 } 8036 kortestql(k7, k7); 8037 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 8038 addptr(result, stride2x2); // update since we already compared at this addr 8039 subl(cnt2, stride2x2); // and sub the size too 8040 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8041 8042 vpxor(vec1, vec1); 8043 jmpb(COMPARE_WIDE_TAIL); 8044 }//if (VM_Version::supports_avx512vlbw()) 8045 #endif // _LP64 8046 8047 8048 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8049 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8050 vmovdqu(vec1, Address(str1, result, scale)); 8051 vpxor(vec1, Address(str2, result, scale)); 8052 } else { 8053 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 8054 vpxor(vec1, Address(str2, result, scale2)); 8055 } 8056 vptest(vec1, vec1); 8057 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 8058 addptr(result, stride2); 8059 subl(cnt2, stride2); 8060 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 8061 // clean upper bits of YMM registers 8062 vpxor(vec1, vec1); 8063 8064 // compare wide vectors tail 8065 bind(COMPARE_WIDE_TAIL); 8066 testptr(result, result); 8067 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8068 8069 movl(result, stride2); 8070 movl(cnt2, result); 8071 negptr(result); 8072 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8073 8074 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 8075 bind(VECTOR_NOT_EQUAL); 8076 // clean upper bits of YMM registers 8077 vpxor(vec1, vec1); 8078 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8079 lea(str1, Address(str1, result, scale)); 8080 lea(str2, Address(str2, result, scale)); 8081 } else { 8082 lea(str1, Address(str1, result, scale1)); 8083 lea(str2, Address(str2, result, scale2)); 8084 } 8085 jmp(COMPARE_16_CHARS); 8086 8087 // Compare tail chars, length between 1 to 15 chars 8088 bind(COMPARE_TAIL_LONG); 8089 movl(cnt2, result); 8090 cmpl(cnt2, stride); 8091 jccb(Assembler::less, COMPARE_SMALL_STR); 8092 8093 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8094 movdqu(vec1, Address(str1, 0)); 8095 } else { 8096 pmovzxbw(vec1, Address(str1, 0)); 8097 } 8098 pcmpestri(vec1, Address(str2, 0), pcmpmask); 8099 jcc(Assembler::below, COMPARE_INDEX_CHAR); 8100 subptr(cnt2, stride); 8101 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8102 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8103 lea(str1, Address(str1, result, scale)); 8104 lea(str2, Address(str2, result, scale)); 8105 } else { 8106 lea(str1, Address(str1, result, scale1)); 8107 lea(str2, Address(str2, result, scale2)); 8108 } 8109 negptr(cnt2); 8110 jmpb(WHILE_HEAD_LABEL); 8111 8112 bind(COMPARE_SMALL_STR); 8113 } else if (UseSSE42Intrinsics) { 8114 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8115 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 8116 int pcmpmask = 0x19; 8117 // Setup to compare 8-char (16-byte) vectors, 8118 // start from first character again because it has aligned address. 8119 movl(result, cnt2); 8120 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 8121 if (ae == StrIntrinsicNode::LL) { 8122 pcmpmask &= ~0x01; 8123 } 8124 jccb(Assembler::zero, COMPARE_TAIL); 8125 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8126 lea(str1, Address(str1, result, scale)); 8127 lea(str2, Address(str2, result, scale)); 8128 } else { 8129 lea(str1, Address(str1, result, scale1)); 8130 lea(str2, Address(str2, result, scale2)); 8131 } 8132 negptr(result); 8133 8134 // pcmpestri 8135 // inputs: 8136 // vec1- substring 8137 // rax - negative string length (elements count) 8138 // mem - scanned string 8139 // rdx - string length (elements count) 8140 // pcmpmask - cmp mode: 11000 (string compare with negated result) 8141 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 8142 // outputs: 8143 // rcx - first mismatched element index 8144 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 8145 8146 bind(COMPARE_WIDE_VECTORS); 8147 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8148 movdqu(vec1, Address(str1, result, scale)); 8149 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8150 } else { 8151 pmovzxbw(vec1, Address(str1, result, scale1)); 8152 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8153 } 8154 // After pcmpestri cnt1(rcx) contains mismatched element index 8155 8156 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 8157 addptr(result, stride); 8158 subptr(cnt2, stride); 8159 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 8160 8161 // compare wide vectors tail 8162 testptr(result, result); 8163 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8164 8165 movl(cnt2, stride); 8166 movl(result, stride); 8167 negptr(result); 8168 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8169 movdqu(vec1, Address(str1, result, scale)); 8170 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8171 } else { 8172 pmovzxbw(vec1, Address(str1, result, scale1)); 8173 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8174 } 8175 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 8176 8177 // Mismatched characters in the vectors 8178 bind(VECTOR_NOT_EQUAL); 8179 addptr(cnt1, result); 8180 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8181 subl(result, cnt2); 8182 jmpb(POP_LABEL); 8183 8184 bind(COMPARE_TAIL); // limit is zero 8185 movl(cnt2, result); 8186 // Fallthru to tail compare 8187 } 8188 // Shift str2 and str1 to the end of the arrays, negate min 8189 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8190 lea(str1, Address(str1, cnt2, scale)); 8191 lea(str2, Address(str2, cnt2, scale)); 8192 } else { 8193 lea(str1, Address(str1, cnt2, scale1)); 8194 lea(str2, Address(str2, cnt2, scale2)); 8195 } 8196 decrementl(cnt2); // first character was compared already 8197 negptr(cnt2); 8198 8199 // Compare the rest of the elements 8200 bind(WHILE_HEAD_LABEL); 8201 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8202 subl(result, cnt1); 8203 jccb(Assembler::notZero, POP_LABEL); 8204 increment(cnt2); 8205 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8206 8207 // Strings are equal up to min length. Return the length difference. 8208 bind(LENGTH_DIFF_LABEL); 8209 pop(result); 8210 if (ae == StrIntrinsicNode::UU) { 8211 // Divide diff by 2 to get number of chars 8212 sarl(result, 1); 8213 } 8214 jmpb(DONE_LABEL); 8215 8216 #ifdef _LP64 8217 if (VM_Version::supports_avx512vlbw()) { 8218 8219 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8220 8221 kmovql(cnt1, k7); 8222 notq(cnt1); 8223 bsfq(cnt2, cnt1); 8224 if (ae != StrIntrinsicNode::LL) { 8225 // Divide diff by 2 to get number of chars 8226 sarl(cnt2, 1); 8227 } 8228 addq(result, cnt2); 8229 if (ae == StrIntrinsicNode::LL) { 8230 load_unsigned_byte(cnt1, Address(str2, result)); 8231 load_unsigned_byte(result, Address(str1, result)); 8232 } else if (ae == StrIntrinsicNode::UU) { 8233 load_unsigned_short(cnt1, Address(str2, result, scale)); 8234 load_unsigned_short(result, Address(str1, result, scale)); 8235 } else { 8236 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8237 load_unsigned_byte(result, Address(str1, result, scale1)); 8238 } 8239 subl(result, cnt1); 8240 jmpb(POP_LABEL); 8241 }//if (VM_Version::supports_avx512vlbw()) 8242 #endif // _LP64 8243 8244 // Discard the stored length difference 8245 bind(POP_LABEL); 8246 pop(cnt1); 8247 8248 // That's it 8249 bind(DONE_LABEL); 8250 if(ae == StrIntrinsicNode::UL) { 8251 negl(result); 8252 } 8253 8254 } 8255 8256 // Search for Non-ASCII character (Negative byte value) in a byte array, 8257 // return true if it has any and false otherwise. 8258 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8259 // @HotSpotIntrinsicCandidate 8260 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8261 // for (int i = off; i < off + len; i++) { 8262 // if (ba[i] < 0) { 8263 // return true; 8264 // } 8265 // } 8266 // return false; 8267 // } 8268 void MacroAssembler::has_negatives(Register ary1, Register len, 8269 Register result, Register tmp1, 8270 XMMRegister vec1, XMMRegister vec2) { 8271 // rsi: byte array 8272 // rcx: len 8273 // rax: result 8274 ShortBranchVerifier sbv(this); 8275 assert_different_registers(ary1, len, result, tmp1); 8276 assert_different_registers(vec1, vec2); 8277 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8278 8279 // len == 0 8280 testl(len, len); 8281 jcc(Assembler::zero, FALSE_LABEL); 8282 8283 if ((UseAVX > 2) && // AVX512 8284 VM_Version::supports_avx512vlbw() && 8285 VM_Version::supports_bmi2()) { 8286 8287 set_vector_masking(); // opening of the stub context for programming mask registers 8288 8289 Label test_64_loop, test_tail; 8290 Register tmp3_aliased = len; 8291 8292 movl(tmp1, len); 8293 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8294 8295 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8296 andl(len, ~(64 - 1)); // vector count (in chars) 8297 jccb(Assembler::zero, test_tail); 8298 8299 lea(ary1, Address(ary1, len, Address::times_1)); 8300 negptr(len); 8301 8302 bind(test_64_loop); 8303 // Check whether our 64 elements of size byte contain negatives 8304 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8305 kortestql(k2, k2); 8306 jcc(Assembler::notZero, TRUE_LABEL); 8307 8308 addptr(len, 64); 8309 jccb(Assembler::notZero, test_64_loop); 8310 8311 8312 bind(test_tail); 8313 // bail out when there is nothing to be done 8314 testl(tmp1, -1); 8315 jcc(Assembler::zero, FALSE_LABEL); 8316 8317 // Save k1 8318 kmovql(k3, k1); 8319 8320 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8321 #ifdef _LP64 8322 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8323 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8324 notq(tmp3_aliased); 8325 kmovql(k1, tmp3_aliased); 8326 #else 8327 Label k_init; 8328 jmp(k_init); 8329 8330 // We could not read 64-bits from a general purpose register thus we move 8331 // data required to compose 64 1's to the instruction stream 8332 // We emit 64 byte wide series of elements from 0..63 which later on would 8333 // be used as a compare targets with tail count contained in tmp1 register. 8334 // Result would be a k1 register having tmp1 consecutive number or 1 8335 // counting from least significant bit. 8336 address tmp = pc(); 8337 emit_int64(0x0706050403020100); 8338 emit_int64(0x0F0E0D0C0B0A0908); 8339 emit_int64(0x1716151413121110); 8340 emit_int64(0x1F1E1D1C1B1A1918); 8341 emit_int64(0x2726252423222120); 8342 emit_int64(0x2F2E2D2C2B2A2928); 8343 emit_int64(0x3736353433323130); 8344 emit_int64(0x3F3E3D3C3B3A3938); 8345 8346 bind(k_init); 8347 lea(len, InternalAddress(tmp)); 8348 // create mask to test for negative byte inside a vector 8349 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8350 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8351 8352 #endif 8353 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8354 ktestq(k2, k1); 8355 // Restore k1 8356 kmovql(k1, k3); 8357 jcc(Assembler::notZero, TRUE_LABEL); 8358 8359 jmp(FALSE_LABEL); 8360 8361 clear_vector_masking(); // closing of the stub context for programming mask registers 8362 } else { 8363 movl(result, len); // copy 8364 8365 if (UseAVX == 2 && UseSSE >= 2) { 8366 // With AVX2, use 32-byte vector compare 8367 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8368 8369 // Compare 32-byte vectors 8370 andl(result, 0x0000001f); // tail count (in bytes) 8371 andl(len, 0xffffffe0); // vector count (in bytes) 8372 jccb(Assembler::zero, COMPARE_TAIL); 8373 8374 lea(ary1, Address(ary1, len, Address::times_1)); 8375 negptr(len); 8376 8377 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8378 movdl(vec2, tmp1); 8379 vpbroadcastd(vec2, vec2); 8380 8381 bind(COMPARE_WIDE_VECTORS); 8382 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8383 vptest(vec1, vec2); 8384 jccb(Assembler::notZero, TRUE_LABEL); 8385 addptr(len, 32); 8386 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8387 8388 testl(result, result); 8389 jccb(Assembler::zero, FALSE_LABEL); 8390 8391 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8392 vptest(vec1, vec2); 8393 jccb(Assembler::notZero, TRUE_LABEL); 8394 jmpb(FALSE_LABEL); 8395 8396 bind(COMPARE_TAIL); // len is zero 8397 movl(len, result); 8398 // Fallthru to tail compare 8399 } else if (UseSSE42Intrinsics) { 8400 assert(UseSSE >= 4, "SSE4 must be for SSE4.2 intrinsics to be available"); 8401 // With SSE4.2, use double quad vector compare 8402 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8403 8404 // Compare 16-byte vectors 8405 andl(result, 0x0000000f); // tail count (in bytes) 8406 andl(len, 0xfffffff0); // vector count (in bytes) 8407 jccb(Assembler::zero, COMPARE_TAIL); 8408 8409 lea(ary1, Address(ary1, len, Address::times_1)); 8410 negptr(len); 8411 8412 movl(tmp1, 0x80808080); 8413 movdl(vec2, tmp1); 8414 pshufd(vec2, vec2, 0); 8415 8416 bind(COMPARE_WIDE_VECTORS); 8417 movdqu(vec1, Address(ary1, len, Address::times_1)); 8418 ptest(vec1, vec2); 8419 jccb(Assembler::notZero, TRUE_LABEL); 8420 addptr(len, 16); 8421 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8422 8423 testl(result, result); 8424 jccb(Assembler::zero, FALSE_LABEL); 8425 8426 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8427 ptest(vec1, vec2); 8428 jccb(Assembler::notZero, TRUE_LABEL); 8429 jmpb(FALSE_LABEL); 8430 8431 bind(COMPARE_TAIL); // len is zero 8432 movl(len, result); 8433 // Fallthru to tail compare 8434 } 8435 } 8436 // Compare 4-byte vectors 8437 andl(len, 0xfffffffc); // vector count (in bytes) 8438 jccb(Assembler::zero, COMPARE_CHAR); 8439 8440 lea(ary1, Address(ary1, len, Address::times_1)); 8441 negptr(len); 8442 8443 bind(COMPARE_VECTORS); 8444 movl(tmp1, Address(ary1, len, Address::times_1)); 8445 andl(tmp1, 0x80808080); 8446 jccb(Assembler::notZero, TRUE_LABEL); 8447 addptr(len, 4); 8448 jcc(Assembler::notZero, COMPARE_VECTORS); 8449 8450 // Compare trailing char (final 2 bytes), if any 8451 bind(COMPARE_CHAR); 8452 testl(result, 0x2); // tail char 8453 jccb(Assembler::zero, COMPARE_BYTE); 8454 load_unsigned_short(tmp1, Address(ary1, 0)); 8455 andl(tmp1, 0x00008080); 8456 jccb(Assembler::notZero, TRUE_LABEL); 8457 subptr(result, 2); 8458 lea(ary1, Address(ary1, 2)); 8459 8460 bind(COMPARE_BYTE); 8461 testl(result, 0x1); // tail byte 8462 jccb(Assembler::zero, FALSE_LABEL); 8463 load_unsigned_byte(tmp1, Address(ary1, 0)); 8464 andl(tmp1, 0x00000080); 8465 jccb(Assembler::notEqual, TRUE_LABEL); 8466 jmpb(FALSE_LABEL); 8467 8468 bind(TRUE_LABEL); 8469 movl(result, 1); // return true 8470 jmpb(DONE); 8471 8472 bind(FALSE_LABEL); 8473 xorl(result, result); // return false 8474 8475 // That's it 8476 bind(DONE); 8477 if (UseAVX >= 2 && UseSSE >= 2) { 8478 // clean upper bits of YMM registers 8479 vpxor(vec1, vec1); 8480 vpxor(vec2, vec2); 8481 } 8482 } 8483 8484 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8485 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8486 Register limit, Register result, Register chr, 8487 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8488 ShortBranchVerifier sbv(this); 8489 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8490 8491 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8492 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8493 8494 if (is_array_equ) { 8495 // Check the input args 8496 cmpptr(ary1, ary2); 8497 jcc(Assembler::equal, TRUE_LABEL); 8498 8499 // Need additional checks for arrays_equals. 8500 testptr(ary1, ary1); 8501 jcc(Assembler::zero, FALSE_LABEL); 8502 testptr(ary2, ary2); 8503 jcc(Assembler::zero, FALSE_LABEL); 8504 8505 // Check the lengths 8506 movl(limit, Address(ary1, length_offset)); 8507 cmpl(limit, Address(ary2, length_offset)); 8508 jcc(Assembler::notEqual, FALSE_LABEL); 8509 } 8510 8511 // count == 0 8512 testl(limit, limit); 8513 jcc(Assembler::zero, TRUE_LABEL); 8514 8515 if (is_array_equ) { 8516 // Load array address 8517 lea(ary1, Address(ary1, base_offset)); 8518 lea(ary2, Address(ary2, base_offset)); 8519 } 8520 8521 if (is_array_equ && is_char) { 8522 // arrays_equals when used for char[]. 8523 shll(limit, 1); // byte count != 0 8524 } 8525 movl(result, limit); // copy 8526 8527 if (UseAVX >= 2) { 8528 // With AVX2, use 32-byte vector compare 8529 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8530 8531 // Compare 32-byte vectors 8532 andl(result, 0x0000001f); // tail count (in bytes) 8533 andl(limit, 0xffffffe0); // vector count (in bytes) 8534 jcc(Assembler::zero, COMPARE_TAIL); 8535 8536 lea(ary1, Address(ary1, limit, Address::times_1)); 8537 lea(ary2, Address(ary2, limit, Address::times_1)); 8538 negptr(limit); 8539 8540 bind(COMPARE_WIDE_VECTORS); 8541 8542 #ifdef _LP64 8543 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8544 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8545 8546 cmpl(limit, -64); 8547 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8548 8549 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8550 8551 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8552 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8553 kortestql(k7, k7); 8554 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8555 addptr(limit, 64); // update since we already compared at this addr 8556 cmpl(limit, -64); 8557 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8558 8559 // At this point we may still need to compare -limit+result bytes. 8560 // We could execute the next two instruction and just continue via non-wide path: 8561 // cmpl(limit, 0); 8562 // jcc(Assembler::equal, COMPARE_TAIL); // true 8563 // But since we stopped at the points ary{1,2}+limit which are 8564 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8565 // (|limit| <= 32 and result < 32), 8566 // we may just compare the last 64 bytes. 8567 // 8568 addptr(result, -64); // it is safe, bc we just came from this area 8569 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8570 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8571 kortestql(k7, k7); 8572 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8573 8574 jmp(TRUE_LABEL); 8575 8576 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8577 8578 }//if (VM_Version::supports_avx512vlbw()) 8579 #endif //_LP64 8580 8581 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8582 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8583 vpxor(vec1, vec2); 8584 8585 vptest(vec1, vec1); 8586 jccb(Assembler::notZero, FALSE_LABEL); 8587 addptr(limit, 32); 8588 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8589 8590 testl(result, result); 8591 jccb(Assembler::zero, TRUE_LABEL); 8592 8593 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8594 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8595 vpxor(vec1, vec2); 8596 8597 vptest(vec1, vec1); 8598 jccb(Assembler::notZero, FALSE_LABEL); 8599 jmpb(TRUE_LABEL); 8600 8601 bind(COMPARE_TAIL); // limit is zero 8602 movl(limit, result); 8603 // Fallthru to tail compare 8604 } else if (UseSSE42Intrinsics) { 8605 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8606 // With SSE4.2, use double quad vector compare 8607 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8608 8609 // Compare 16-byte vectors 8610 andl(result, 0x0000000f); // tail count (in bytes) 8611 andl(limit, 0xfffffff0); // vector count (in bytes) 8612 jccb(Assembler::zero, COMPARE_TAIL); 8613 8614 lea(ary1, Address(ary1, limit, Address::times_1)); 8615 lea(ary2, Address(ary2, limit, Address::times_1)); 8616 negptr(limit); 8617 8618 bind(COMPARE_WIDE_VECTORS); 8619 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8620 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8621 pxor(vec1, vec2); 8622 8623 ptest(vec1, vec1); 8624 jccb(Assembler::notZero, FALSE_LABEL); 8625 addptr(limit, 16); 8626 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8627 8628 testl(result, result); 8629 jccb(Assembler::zero, TRUE_LABEL); 8630 8631 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8632 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8633 pxor(vec1, vec2); 8634 8635 ptest(vec1, vec1); 8636 jccb(Assembler::notZero, FALSE_LABEL); 8637 jmpb(TRUE_LABEL); 8638 8639 bind(COMPARE_TAIL); // limit is zero 8640 movl(limit, result); 8641 // Fallthru to tail compare 8642 } 8643 8644 // Compare 4-byte vectors 8645 andl(limit, 0xfffffffc); // vector count (in bytes) 8646 jccb(Assembler::zero, COMPARE_CHAR); 8647 8648 lea(ary1, Address(ary1, limit, Address::times_1)); 8649 lea(ary2, Address(ary2, limit, Address::times_1)); 8650 negptr(limit); 8651 8652 bind(COMPARE_VECTORS); 8653 movl(chr, Address(ary1, limit, Address::times_1)); 8654 cmpl(chr, Address(ary2, limit, Address::times_1)); 8655 jccb(Assembler::notEqual, FALSE_LABEL); 8656 addptr(limit, 4); 8657 jcc(Assembler::notZero, COMPARE_VECTORS); 8658 8659 // Compare trailing char (final 2 bytes), if any 8660 bind(COMPARE_CHAR); 8661 testl(result, 0x2); // tail char 8662 jccb(Assembler::zero, COMPARE_BYTE); 8663 load_unsigned_short(chr, Address(ary1, 0)); 8664 load_unsigned_short(limit, Address(ary2, 0)); 8665 cmpl(chr, limit); 8666 jccb(Assembler::notEqual, FALSE_LABEL); 8667 8668 if (is_array_equ && is_char) { 8669 bind(COMPARE_BYTE); 8670 } else { 8671 lea(ary1, Address(ary1, 2)); 8672 lea(ary2, Address(ary2, 2)); 8673 8674 bind(COMPARE_BYTE); 8675 testl(result, 0x1); // tail byte 8676 jccb(Assembler::zero, TRUE_LABEL); 8677 load_unsigned_byte(chr, Address(ary1, 0)); 8678 load_unsigned_byte(limit, Address(ary2, 0)); 8679 cmpl(chr, limit); 8680 jccb(Assembler::notEqual, FALSE_LABEL); 8681 } 8682 bind(TRUE_LABEL); 8683 movl(result, 1); // return true 8684 jmpb(DONE); 8685 8686 bind(FALSE_LABEL); 8687 xorl(result, result); // return false 8688 8689 // That's it 8690 bind(DONE); 8691 if (UseAVX >= 2) { 8692 // clean upper bits of YMM registers 8693 vpxor(vec1, vec1); 8694 vpxor(vec2, vec2); 8695 } 8696 } 8697 8698 #endif 8699 8700 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8701 Register to, Register value, Register count, 8702 Register rtmp, XMMRegister xtmp) { 8703 ShortBranchVerifier sbv(this); 8704 assert_different_registers(to, value, count, rtmp); 8705 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8706 Label L_fill_2_bytes, L_fill_4_bytes; 8707 8708 int shift = -1; 8709 switch (t) { 8710 case T_BYTE: 8711 shift = 2; 8712 break; 8713 case T_SHORT: 8714 shift = 1; 8715 break; 8716 case T_INT: 8717 shift = 0; 8718 break; 8719 default: ShouldNotReachHere(); 8720 } 8721 8722 if (t == T_BYTE) { 8723 andl(value, 0xff); 8724 movl(rtmp, value); 8725 shll(rtmp, 8); 8726 orl(value, rtmp); 8727 } 8728 if (t == T_SHORT) { 8729 andl(value, 0xffff); 8730 } 8731 if (t == T_BYTE || t == T_SHORT) { 8732 movl(rtmp, value); 8733 shll(rtmp, 16); 8734 orl(value, rtmp); 8735 } 8736 8737 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8738 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8739 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8740 // align source address at 4 bytes address boundary 8741 if (t == T_BYTE) { 8742 // One byte misalignment happens only for byte arrays 8743 testptr(to, 1); 8744 jccb(Assembler::zero, L_skip_align1); 8745 movb(Address(to, 0), value); 8746 increment(to); 8747 decrement(count); 8748 BIND(L_skip_align1); 8749 } 8750 // Two bytes misalignment happens only for byte and short (char) arrays 8751 testptr(to, 2); 8752 jccb(Assembler::zero, L_skip_align2); 8753 movw(Address(to, 0), value); 8754 addptr(to, 2); 8755 subl(count, 1<<(shift-1)); 8756 BIND(L_skip_align2); 8757 } 8758 if (UseSSE < 2) { 8759 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8760 // Fill 32-byte chunks 8761 subl(count, 8 << shift); 8762 jcc(Assembler::less, L_check_fill_8_bytes); 8763 align(16); 8764 8765 BIND(L_fill_32_bytes_loop); 8766 8767 for (int i = 0; i < 32; i += 4) { 8768 movl(Address(to, i), value); 8769 } 8770 8771 addptr(to, 32); 8772 subl(count, 8 << shift); 8773 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8774 BIND(L_check_fill_8_bytes); 8775 addl(count, 8 << shift); 8776 jccb(Assembler::zero, L_exit); 8777 jmpb(L_fill_8_bytes); 8778 8779 // 8780 // length is too short, just fill qwords 8781 // 8782 BIND(L_fill_8_bytes_loop); 8783 movl(Address(to, 0), value); 8784 movl(Address(to, 4), value); 8785 addptr(to, 8); 8786 BIND(L_fill_8_bytes); 8787 subl(count, 1 << (shift + 1)); 8788 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8789 // fall through to fill 4 bytes 8790 } else { 8791 Label L_fill_32_bytes; 8792 if (!UseUnalignedLoadStores) { 8793 // align to 8 bytes, we know we are 4 byte aligned to start 8794 testptr(to, 4); 8795 jccb(Assembler::zero, L_fill_32_bytes); 8796 movl(Address(to, 0), value); 8797 addptr(to, 4); 8798 subl(count, 1<<shift); 8799 } 8800 BIND(L_fill_32_bytes); 8801 { 8802 assert( UseSSE >= 2, "supported cpu only" ); 8803 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8804 if (UseAVX > 2) { 8805 movl(rtmp, 0xffff); 8806 kmovwl(k1, rtmp); 8807 } 8808 movdl(xtmp, value); 8809 if (UseAVX > 2 && UseUnalignedLoadStores) { 8810 // Fill 64-byte chunks 8811 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8812 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8813 8814 subl(count, 16 << shift); 8815 jcc(Assembler::less, L_check_fill_32_bytes); 8816 align(16); 8817 8818 BIND(L_fill_64_bytes_loop); 8819 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8820 addptr(to, 64); 8821 subl(count, 16 << shift); 8822 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8823 8824 BIND(L_check_fill_32_bytes); 8825 addl(count, 8 << shift); 8826 jccb(Assembler::less, L_check_fill_8_bytes); 8827 vmovdqu(Address(to, 0), xtmp); 8828 addptr(to, 32); 8829 subl(count, 8 << shift); 8830 8831 BIND(L_check_fill_8_bytes); 8832 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8833 // Fill 64-byte chunks 8834 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8835 vpbroadcastd(xtmp, xtmp); 8836 8837 subl(count, 16 << shift); 8838 jcc(Assembler::less, L_check_fill_32_bytes); 8839 align(16); 8840 8841 BIND(L_fill_64_bytes_loop); 8842 vmovdqu(Address(to, 0), xtmp); 8843 vmovdqu(Address(to, 32), xtmp); 8844 addptr(to, 64); 8845 subl(count, 16 << shift); 8846 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8847 8848 BIND(L_check_fill_32_bytes); 8849 addl(count, 8 << shift); 8850 jccb(Assembler::less, L_check_fill_8_bytes); 8851 vmovdqu(Address(to, 0), xtmp); 8852 addptr(to, 32); 8853 subl(count, 8 << shift); 8854 8855 BIND(L_check_fill_8_bytes); 8856 // clean upper bits of YMM registers 8857 movdl(xtmp, value); 8858 pshufd(xtmp, xtmp, 0); 8859 } else { 8860 // Fill 32-byte chunks 8861 pshufd(xtmp, xtmp, 0); 8862 8863 subl(count, 8 << shift); 8864 jcc(Assembler::less, L_check_fill_8_bytes); 8865 align(16); 8866 8867 BIND(L_fill_32_bytes_loop); 8868 8869 if (UseUnalignedLoadStores) { 8870 movdqu(Address(to, 0), xtmp); 8871 movdqu(Address(to, 16), xtmp); 8872 } else { 8873 movq(Address(to, 0), xtmp); 8874 movq(Address(to, 8), xtmp); 8875 movq(Address(to, 16), xtmp); 8876 movq(Address(to, 24), xtmp); 8877 } 8878 8879 addptr(to, 32); 8880 subl(count, 8 << shift); 8881 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8882 8883 BIND(L_check_fill_8_bytes); 8884 } 8885 addl(count, 8 << shift); 8886 jccb(Assembler::zero, L_exit); 8887 jmpb(L_fill_8_bytes); 8888 8889 // 8890 // length is too short, just fill qwords 8891 // 8892 BIND(L_fill_8_bytes_loop); 8893 movq(Address(to, 0), xtmp); 8894 addptr(to, 8); 8895 BIND(L_fill_8_bytes); 8896 subl(count, 1 << (shift + 1)); 8897 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8898 } 8899 } 8900 // fill trailing 4 bytes 8901 BIND(L_fill_4_bytes); 8902 testl(count, 1<<shift); 8903 jccb(Assembler::zero, L_fill_2_bytes); 8904 movl(Address(to, 0), value); 8905 if (t == T_BYTE || t == T_SHORT) { 8906 addptr(to, 4); 8907 BIND(L_fill_2_bytes); 8908 // fill trailing 2 bytes 8909 testl(count, 1<<(shift-1)); 8910 jccb(Assembler::zero, L_fill_byte); 8911 movw(Address(to, 0), value); 8912 if (t == T_BYTE) { 8913 addptr(to, 2); 8914 BIND(L_fill_byte); 8915 // fill trailing byte 8916 testl(count, 1); 8917 jccb(Assembler::zero, L_exit); 8918 movb(Address(to, 0), value); 8919 } else { 8920 BIND(L_fill_byte); 8921 } 8922 } else { 8923 BIND(L_fill_2_bytes); 8924 } 8925 BIND(L_exit); 8926 } 8927 8928 // encode char[] to byte[] in ISO_8859_1 8929 //@HotSpotIntrinsicCandidate 8930 //private static int implEncodeISOArray(byte[] sa, int sp, 8931 //byte[] da, int dp, int len) { 8932 // int i = 0; 8933 // for (; i < len; i++) { 8934 // char c = StringUTF16.getChar(sa, sp++); 8935 // if (c > '\u00FF') 8936 // break; 8937 // da[dp++] = (byte)c; 8938 // } 8939 // return i; 8940 //} 8941 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8942 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8943 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8944 Register tmp5, Register result) { 8945 8946 // rsi: src 8947 // rdi: dst 8948 // rdx: len 8949 // rcx: tmp5 8950 // rax: result 8951 ShortBranchVerifier sbv(this); 8952 assert_different_registers(src, dst, len, tmp5, result); 8953 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8954 8955 // set result 8956 xorl(result, result); 8957 // check for zero length 8958 testl(len, len); 8959 jcc(Assembler::zero, L_done); 8960 8961 movl(result, len); 8962 8963 // Setup pointers 8964 lea(src, Address(src, len, Address::times_2)); // char[] 8965 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8966 negptr(len); 8967 8968 if (UseSSE42Intrinsics || UseAVX >= 2) { 8969 assert(UseSSE42Intrinsics ? UseSSE >= 4 : true, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8970 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8971 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8972 8973 if (UseAVX >= 2) { 8974 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8975 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8976 movdl(tmp1Reg, tmp5); 8977 vpbroadcastd(tmp1Reg, tmp1Reg); 8978 jmpb(L_chars_32_check); 8979 8980 bind(L_copy_32_chars); 8981 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8982 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8983 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8984 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8985 jccb(Assembler::notZero, L_copy_32_chars_exit); 8986 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8987 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8988 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8989 8990 bind(L_chars_32_check); 8991 addptr(len, 32); 8992 jccb(Assembler::lessEqual, L_copy_32_chars); 8993 8994 bind(L_copy_32_chars_exit); 8995 subptr(len, 16); 8996 jccb(Assembler::greater, L_copy_16_chars_exit); 8997 8998 } else if (UseSSE42Intrinsics) { 8999 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 9000 movdl(tmp1Reg, tmp5); 9001 pshufd(tmp1Reg, tmp1Reg, 0); 9002 jmpb(L_chars_16_check); 9003 } 9004 9005 bind(L_copy_16_chars); 9006 if (UseAVX >= 2) { 9007 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 9008 vptest(tmp2Reg, tmp1Reg); 9009 jccb(Assembler::notZero, L_copy_16_chars_exit); 9010 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 9011 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 9012 } else { 9013 if (UseAVX > 0) { 9014 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 9015 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 9016 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 9017 } else { 9018 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 9019 por(tmp2Reg, tmp3Reg); 9020 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 9021 por(tmp2Reg, tmp4Reg); 9022 } 9023 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 9024 jccb(Assembler::notZero, L_copy_16_chars_exit); 9025 packuswb(tmp3Reg, tmp4Reg); 9026 } 9027 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 9028 9029 bind(L_chars_16_check); 9030 addptr(len, 16); 9031 jccb(Assembler::lessEqual, L_copy_16_chars); 9032 9033 bind(L_copy_16_chars_exit); 9034 if (UseAVX >= 2) { 9035 // clean upper bits of YMM registers 9036 vpxor(tmp2Reg, tmp2Reg); 9037 vpxor(tmp3Reg, tmp3Reg); 9038 vpxor(tmp4Reg, tmp4Reg); 9039 movdl(tmp1Reg, tmp5); 9040 pshufd(tmp1Reg, tmp1Reg, 0); 9041 } 9042 subptr(len, 8); 9043 jccb(Assembler::greater, L_copy_8_chars_exit); 9044 9045 bind(L_copy_8_chars); 9046 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 9047 ptest(tmp3Reg, tmp1Reg); 9048 jccb(Assembler::notZero, L_copy_8_chars_exit); 9049 packuswb(tmp3Reg, tmp1Reg); 9050 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 9051 addptr(len, 8); 9052 jccb(Assembler::lessEqual, L_copy_8_chars); 9053 9054 bind(L_copy_8_chars_exit); 9055 subptr(len, 8); 9056 jccb(Assembler::zero, L_done); 9057 } 9058 9059 bind(L_copy_1_char); 9060 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 9061 testl(tmp5, 0xff00); // check if Unicode char 9062 jccb(Assembler::notZero, L_copy_1_char_exit); 9063 movb(Address(dst, len, Address::times_1, 0), tmp5); 9064 addptr(len, 1); 9065 jccb(Assembler::less, L_copy_1_char); 9066 9067 bind(L_copy_1_char_exit); 9068 addptr(result, len); // len is negative count of not processed elements 9069 9070 bind(L_done); 9071 } 9072 9073 #ifdef _LP64 9074 /** 9075 * Helper for multiply_to_len(). 9076 */ 9077 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 9078 addq(dest_lo, src1); 9079 adcq(dest_hi, 0); 9080 addq(dest_lo, src2); 9081 adcq(dest_hi, 0); 9082 } 9083 9084 /** 9085 * Multiply 64 bit by 64 bit first loop. 9086 */ 9087 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 9088 Register y, Register y_idx, Register z, 9089 Register carry, Register product, 9090 Register idx, Register kdx) { 9091 // 9092 // jlong carry, x[], y[], z[]; 9093 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9094 // huge_128 product = y[idx] * x[xstart] + carry; 9095 // z[kdx] = (jlong)product; 9096 // carry = (jlong)(product >>> 64); 9097 // } 9098 // z[xstart] = carry; 9099 // 9100 9101 Label L_first_loop, L_first_loop_exit; 9102 Label L_one_x, L_one_y, L_multiply; 9103 9104 decrementl(xstart); 9105 jcc(Assembler::negative, L_one_x); 9106 9107 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9108 rorq(x_xstart, 32); // convert big-endian to little-endian 9109 9110 bind(L_first_loop); 9111 decrementl(idx); 9112 jcc(Assembler::negative, L_first_loop_exit); 9113 decrementl(idx); 9114 jcc(Assembler::negative, L_one_y); 9115 movq(y_idx, Address(y, idx, Address::times_4, 0)); 9116 rorq(y_idx, 32); // convert big-endian to little-endian 9117 bind(L_multiply); 9118 movq(product, x_xstart); 9119 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 9120 addq(product, carry); 9121 adcq(rdx, 0); 9122 subl(kdx, 2); 9123 movl(Address(z, kdx, Address::times_4, 4), product); 9124 shrq(product, 32); 9125 movl(Address(z, kdx, Address::times_4, 0), product); 9126 movq(carry, rdx); 9127 jmp(L_first_loop); 9128 9129 bind(L_one_y); 9130 movl(y_idx, Address(y, 0)); 9131 jmp(L_multiply); 9132 9133 bind(L_one_x); 9134 movl(x_xstart, Address(x, 0)); 9135 jmp(L_first_loop); 9136 9137 bind(L_first_loop_exit); 9138 } 9139 9140 /** 9141 * Multiply 64 bit by 64 bit and add 128 bit. 9142 */ 9143 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 9144 Register yz_idx, Register idx, 9145 Register carry, Register product, int offset) { 9146 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 9147 // z[kdx] = (jlong)product; 9148 9149 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 9150 rorq(yz_idx, 32); // convert big-endian to little-endian 9151 movq(product, x_xstart); 9152 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9153 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 9154 rorq(yz_idx, 32); // convert big-endian to little-endian 9155 9156 add2_with_carry(rdx, product, carry, yz_idx); 9157 9158 movl(Address(z, idx, Address::times_4, offset+4), product); 9159 shrq(product, 32); 9160 movl(Address(z, idx, Address::times_4, offset), product); 9161 9162 } 9163 9164 /** 9165 * Multiply 128 bit by 128 bit. Unrolled inner loop. 9166 */ 9167 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 9168 Register yz_idx, Register idx, Register jdx, 9169 Register carry, Register product, 9170 Register carry2) { 9171 // jlong carry, x[], y[], z[]; 9172 // int kdx = ystart+1; 9173 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9174 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 9175 // z[kdx+idx+1] = (jlong)product; 9176 // jlong carry2 = (jlong)(product >>> 64); 9177 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 9178 // z[kdx+idx] = (jlong)product; 9179 // carry = (jlong)(product >>> 64); 9180 // } 9181 // idx += 2; 9182 // if (idx > 0) { 9183 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 9184 // z[kdx+idx] = (jlong)product; 9185 // carry = (jlong)(product >>> 64); 9186 // } 9187 // 9188 9189 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9190 9191 movl(jdx, idx); 9192 andl(jdx, 0xFFFFFFFC); 9193 shrl(jdx, 2); 9194 9195 bind(L_third_loop); 9196 subl(jdx, 1); 9197 jcc(Assembler::negative, L_third_loop_exit); 9198 subl(idx, 4); 9199 9200 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 9201 movq(carry2, rdx); 9202 9203 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9204 movq(carry, rdx); 9205 jmp(L_third_loop); 9206 9207 bind (L_third_loop_exit); 9208 9209 andl (idx, 0x3); 9210 jcc(Assembler::zero, L_post_third_loop_done); 9211 9212 Label L_check_1; 9213 subl(idx, 2); 9214 jcc(Assembler::negative, L_check_1); 9215 9216 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9217 movq(carry, rdx); 9218 9219 bind (L_check_1); 9220 addl (idx, 0x2); 9221 andl (idx, 0x1); 9222 subl(idx, 1); 9223 jcc(Assembler::negative, L_post_third_loop_done); 9224 9225 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9226 movq(product, x_xstart); 9227 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9228 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9229 9230 add2_with_carry(rdx, product, yz_idx, carry); 9231 9232 movl(Address(z, idx, Address::times_4, 0), product); 9233 shrq(product, 32); 9234 9235 shlq(rdx, 32); 9236 orq(product, rdx); 9237 movq(carry, product); 9238 9239 bind(L_post_third_loop_done); 9240 } 9241 9242 /** 9243 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9244 * 9245 */ 9246 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9247 Register carry, Register carry2, 9248 Register idx, Register jdx, 9249 Register yz_idx1, Register yz_idx2, 9250 Register tmp, Register tmp3, Register tmp4) { 9251 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9252 9253 // jlong carry, x[], y[], z[]; 9254 // int kdx = ystart+1; 9255 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9256 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9257 // jlong carry2 = (jlong)(tmp3 >>> 64); 9258 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9259 // carry = (jlong)(tmp4 >>> 64); 9260 // z[kdx+idx+1] = (jlong)tmp3; 9261 // z[kdx+idx] = (jlong)tmp4; 9262 // } 9263 // idx += 2; 9264 // if (idx > 0) { 9265 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9266 // z[kdx+idx] = (jlong)yz_idx1; 9267 // carry = (jlong)(yz_idx1 >>> 64); 9268 // } 9269 // 9270 9271 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9272 9273 movl(jdx, idx); 9274 andl(jdx, 0xFFFFFFFC); 9275 shrl(jdx, 2); 9276 9277 bind(L_third_loop); 9278 subl(jdx, 1); 9279 jcc(Assembler::negative, L_third_loop_exit); 9280 subl(idx, 4); 9281 9282 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9283 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9284 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9285 rorxq(yz_idx2, yz_idx2, 32); 9286 9287 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9288 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9289 9290 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9291 rorxq(yz_idx1, yz_idx1, 32); 9292 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9293 rorxq(yz_idx2, yz_idx2, 32); 9294 9295 if (VM_Version::supports_adx()) { 9296 adcxq(tmp3, carry); 9297 adoxq(tmp3, yz_idx1); 9298 9299 adcxq(tmp4, tmp); 9300 adoxq(tmp4, yz_idx2); 9301 9302 movl(carry, 0); // does not affect flags 9303 adcxq(carry2, carry); 9304 adoxq(carry2, carry); 9305 } else { 9306 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9307 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9308 } 9309 movq(carry, carry2); 9310 9311 movl(Address(z, idx, Address::times_4, 12), tmp3); 9312 shrq(tmp3, 32); 9313 movl(Address(z, idx, Address::times_4, 8), tmp3); 9314 9315 movl(Address(z, idx, Address::times_4, 4), tmp4); 9316 shrq(tmp4, 32); 9317 movl(Address(z, idx, Address::times_4, 0), tmp4); 9318 9319 jmp(L_third_loop); 9320 9321 bind (L_third_loop_exit); 9322 9323 andl (idx, 0x3); 9324 jcc(Assembler::zero, L_post_third_loop_done); 9325 9326 Label L_check_1; 9327 subl(idx, 2); 9328 jcc(Assembler::negative, L_check_1); 9329 9330 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9331 rorxq(yz_idx1, yz_idx1, 32); 9332 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9333 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9334 rorxq(yz_idx2, yz_idx2, 32); 9335 9336 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9337 9338 movl(Address(z, idx, Address::times_4, 4), tmp3); 9339 shrq(tmp3, 32); 9340 movl(Address(z, idx, Address::times_4, 0), tmp3); 9341 movq(carry, tmp4); 9342 9343 bind (L_check_1); 9344 addl (idx, 0x2); 9345 andl (idx, 0x1); 9346 subl(idx, 1); 9347 jcc(Assembler::negative, L_post_third_loop_done); 9348 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9349 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9350 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9351 9352 add2_with_carry(carry2, tmp3, tmp4, carry); 9353 9354 movl(Address(z, idx, Address::times_4, 0), tmp3); 9355 shrq(tmp3, 32); 9356 9357 shlq(carry2, 32); 9358 orq(tmp3, carry2); 9359 movq(carry, tmp3); 9360 9361 bind(L_post_third_loop_done); 9362 } 9363 9364 /** 9365 * Code for BigInteger::multiplyToLen() instrinsic. 9366 * 9367 * rdi: x 9368 * rax: xlen 9369 * rsi: y 9370 * rcx: ylen 9371 * r8: z 9372 * r11: zlen 9373 * r12: tmp1 9374 * r13: tmp2 9375 * r14: tmp3 9376 * r15: tmp4 9377 * rbx: tmp5 9378 * 9379 */ 9380 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9381 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9382 ShortBranchVerifier sbv(this); 9383 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9384 9385 push(tmp1); 9386 push(tmp2); 9387 push(tmp3); 9388 push(tmp4); 9389 push(tmp5); 9390 9391 push(xlen); 9392 push(zlen); 9393 9394 const Register idx = tmp1; 9395 const Register kdx = tmp2; 9396 const Register xstart = tmp3; 9397 9398 const Register y_idx = tmp4; 9399 const Register carry = tmp5; 9400 const Register product = xlen; 9401 const Register x_xstart = zlen; // reuse register 9402 9403 // First Loop. 9404 // 9405 // final static long LONG_MASK = 0xffffffffL; 9406 // int xstart = xlen - 1; 9407 // int ystart = ylen - 1; 9408 // long carry = 0; 9409 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9410 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9411 // z[kdx] = (int)product; 9412 // carry = product >>> 32; 9413 // } 9414 // z[xstart] = (int)carry; 9415 // 9416 9417 movl(idx, ylen); // idx = ylen; 9418 movl(kdx, zlen); // kdx = xlen+ylen; 9419 xorq(carry, carry); // carry = 0; 9420 9421 Label L_done; 9422 9423 movl(xstart, xlen); 9424 decrementl(xstart); 9425 jcc(Assembler::negative, L_done); 9426 9427 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9428 9429 Label L_second_loop; 9430 testl(kdx, kdx); 9431 jcc(Assembler::zero, L_second_loop); 9432 9433 Label L_carry; 9434 subl(kdx, 1); 9435 jcc(Assembler::zero, L_carry); 9436 9437 movl(Address(z, kdx, Address::times_4, 0), carry); 9438 shrq(carry, 32); 9439 subl(kdx, 1); 9440 9441 bind(L_carry); 9442 movl(Address(z, kdx, Address::times_4, 0), carry); 9443 9444 // Second and third (nested) loops. 9445 // 9446 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9447 // carry = 0; 9448 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9449 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9450 // (z[k] & LONG_MASK) + carry; 9451 // z[k] = (int)product; 9452 // carry = product >>> 32; 9453 // } 9454 // z[i] = (int)carry; 9455 // } 9456 // 9457 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9458 9459 const Register jdx = tmp1; 9460 9461 bind(L_second_loop); 9462 xorl(carry, carry); // carry = 0; 9463 movl(jdx, ylen); // j = ystart+1 9464 9465 subl(xstart, 1); // i = xstart-1; 9466 jcc(Assembler::negative, L_done); 9467 9468 push (z); 9469 9470 Label L_last_x; 9471 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9472 subl(xstart, 1); // i = xstart-1; 9473 jcc(Assembler::negative, L_last_x); 9474 9475 if (UseBMI2Instructions) { 9476 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9477 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9478 } else { 9479 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9480 rorq(x_xstart, 32); // convert big-endian to little-endian 9481 } 9482 9483 Label L_third_loop_prologue; 9484 bind(L_third_loop_prologue); 9485 9486 push (x); 9487 push (xstart); 9488 push (ylen); 9489 9490 9491 if (UseBMI2Instructions) { 9492 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9493 } else { // !UseBMI2Instructions 9494 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9495 } 9496 9497 pop(ylen); 9498 pop(xlen); 9499 pop(x); 9500 pop(z); 9501 9502 movl(tmp3, xlen); 9503 addl(tmp3, 1); 9504 movl(Address(z, tmp3, Address::times_4, 0), carry); 9505 subl(tmp3, 1); 9506 jccb(Assembler::negative, L_done); 9507 9508 shrq(carry, 32); 9509 movl(Address(z, tmp3, Address::times_4, 0), carry); 9510 jmp(L_second_loop); 9511 9512 // Next infrequent code is moved outside loops. 9513 bind(L_last_x); 9514 if (UseBMI2Instructions) { 9515 movl(rdx, Address(x, 0)); 9516 } else { 9517 movl(x_xstart, Address(x, 0)); 9518 } 9519 jmp(L_third_loop_prologue); 9520 9521 bind(L_done); 9522 9523 pop(zlen); 9524 pop(xlen); 9525 9526 pop(tmp5); 9527 pop(tmp4); 9528 pop(tmp3); 9529 pop(tmp2); 9530 pop(tmp1); 9531 } 9532 9533 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9534 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9535 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9536 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9537 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9538 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9539 Label SAME_TILL_END, DONE; 9540 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9541 9542 //scale is in rcx in both Win64 and Unix 9543 ShortBranchVerifier sbv(this); 9544 9545 shlq(length); 9546 xorq(result, result); 9547 9548 cmpq(length, 8); 9549 jcc(Assembler::equal, VECTOR8_LOOP); 9550 jcc(Assembler::less, VECTOR4_TAIL); 9551 9552 if (UseAVX >= 2){ 9553 9554 cmpq(length, 16); 9555 jcc(Assembler::equal, VECTOR16_LOOP); 9556 jcc(Assembler::less, VECTOR8_LOOP); 9557 9558 cmpq(length, 32); 9559 jccb(Assembler::less, VECTOR16_TAIL); 9560 9561 subq(length, 32); 9562 bind(VECTOR32_LOOP); 9563 vmovdqu(rymm0, Address(obja, result)); 9564 vmovdqu(rymm1, Address(objb, result)); 9565 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9566 vptest(rymm2, rymm2); 9567 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9568 addq(result, 32); 9569 subq(length, 32); 9570 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9571 addq(length, 32); 9572 jcc(Assembler::equal, SAME_TILL_END); 9573 //falling through if less than 32 bytes left //close the branch here. 9574 9575 bind(VECTOR16_TAIL); 9576 cmpq(length, 16); 9577 jccb(Assembler::less, VECTOR8_TAIL); 9578 bind(VECTOR16_LOOP); 9579 movdqu(rymm0, Address(obja, result)); 9580 movdqu(rymm1, Address(objb, result)); 9581 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9582 ptest(rymm2, rymm2); 9583 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9584 addq(result, 16); 9585 subq(length, 16); 9586 jcc(Assembler::equal, SAME_TILL_END); 9587 //falling through if less than 16 bytes left 9588 } else {//regular intrinsics 9589 9590 cmpq(length, 16); 9591 jccb(Assembler::less, VECTOR8_TAIL); 9592 9593 subq(length, 16); 9594 bind(VECTOR16_LOOP); 9595 movdqu(rymm0, Address(obja, result)); 9596 movdqu(rymm1, Address(objb, result)); 9597 pxor(rymm0, rymm1); 9598 ptest(rymm0, rymm0); 9599 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9600 addq(result, 16); 9601 subq(length, 16); 9602 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9603 addq(length, 16); 9604 jcc(Assembler::equal, SAME_TILL_END); 9605 //falling through if less than 16 bytes left 9606 } 9607 9608 bind(VECTOR8_TAIL); 9609 cmpq(length, 8); 9610 jccb(Assembler::less, VECTOR4_TAIL); 9611 bind(VECTOR8_LOOP); 9612 movq(tmp1, Address(obja, result)); 9613 movq(tmp2, Address(objb, result)); 9614 xorq(tmp1, tmp2); 9615 testq(tmp1, tmp1); 9616 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9617 addq(result, 8); 9618 subq(length, 8); 9619 jcc(Assembler::equal, SAME_TILL_END); 9620 //falling through if less than 8 bytes left 9621 9622 bind(VECTOR4_TAIL); 9623 cmpq(length, 4); 9624 jccb(Assembler::less, BYTES_TAIL); 9625 bind(VECTOR4_LOOP); 9626 movl(tmp1, Address(obja, result)); 9627 xorl(tmp1, Address(objb, result)); 9628 testl(tmp1, tmp1); 9629 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9630 addq(result, 4); 9631 subq(length, 4); 9632 jcc(Assembler::equal, SAME_TILL_END); 9633 //falling through if less than 4 bytes left 9634 9635 bind(BYTES_TAIL); 9636 bind(BYTES_LOOP); 9637 load_unsigned_byte(tmp1, Address(obja, result)); 9638 load_unsigned_byte(tmp2, Address(objb, result)); 9639 xorl(tmp1, tmp2); 9640 testl(tmp1, tmp1); 9641 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9642 decq(length); 9643 jccb(Assembler::zero, SAME_TILL_END); 9644 incq(result); 9645 load_unsigned_byte(tmp1, Address(obja, result)); 9646 load_unsigned_byte(tmp2, Address(objb, result)); 9647 xorl(tmp1, tmp2); 9648 testl(tmp1, tmp1); 9649 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9650 decq(length); 9651 jccb(Assembler::zero, SAME_TILL_END); 9652 incq(result); 9653 load_unsigned_byte(tmp1, Address(obja, result)); 9654 load_unsigned_byte(tmp2, Address(objb, result)); 9655 xorl(tmp1, tmp2); 9656 testl(tmp1, tmp1); 9657 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9658 jmpb(SAME_TILL_END); 9659 9660 if (UseAVX >= 2){ 9661 bind(VECTOR32_NOT_EQUAL); 9662 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9663 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9664 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9665 vpmovmskb(tmp1, rymm0); 9666 bsfq(tmp1, tmp1); 9667 addq(result, tmp1); 9668 shrq(result); 9669 jmpb(DONE); 9670 } 9671 9672 bind(VECTOR16_NOT_EQUAL); 9673 if (UseAVX >= 2){ 9674 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9675 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9676 pxor(rymm0, rymm2); 9677 } else { 9678 pcmpeqb(rymm2, rymm2); 9679 pxor(rymm0, rymm1); 9680 pcmpeqb(rymm0, rymm1); 9681 pxor(rymm0, rymm2); 9682 } 9683 pmovmskb(tmp1, rymm0); 9684 bsfq(tmp1, tmp1); 9685 addq(result, tmp1); 9686 shrq(result); 9687 jmpb(DONE); 9688 9689 bind(VECTOR8_NOT_EQUAL); 9690 bind(VECTOR4_NOT_EQUAL); 9691 bsfq(tmp1, tmp1); 9692 shrq(tmp1, 3); 9693 addq(result, tmp1); 9694 bind(BYTES_NOT_EQUAL); 9695 shrq(result); 9696 jmpb(DONE); 9697 9698 bind(SAME_TILL_END); 9699 mov64(result, -1); 9700 9701 bind(DONE); 9702 } 9703 9704 9705 //Helper functions for square_to_len() 9706 9707 /** 9708 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9709 * Preserves x and z and modifies rest of the registers. 9710 */ 9711 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9712 // Perform square and right shift by 1 9713 // Handle odd xlen case first, then for even xlen do the following 9714 // jlong carry = 0; 9715 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9716 // huge_128 product = x[j:j+1] * x[j:j+1]; 9717 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9718 // z[i+2:i+3] = (jlong)(product >>> 1); 9719 // carry = (jlong)product; 9720 // } 9721 9722 xorq(tmp5, tmp5); // carry 9723 xorq(rdxReg, rdxReg); 9724 xorl(tmp1, tmp1); // index for x 9725 xorl(tmp4, tmp4); // index for z 9726 9727 Label L_first_loop, L_first_loop_exit; 9728 9729 testl(xlen, 1); 9730 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9731 9732 // Square and right shift by 1 the odd element using 32 bit multiply 9733 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9734 imulq(raxReg, raxReg); 9735 shrq(raxReg, 1); 9736 adcq(tmp5, 0); 9737 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9738 incrementl(tmp1); 9739 addl(tmp4, 2); 9740 9741 // Square and right shift by 1 the rest using 64 bit multiply 9742 bind(L_first_loop); 9743 cmpptr(tmp1, xlen); 9744 jccb(Assembler::equal, L_first_loop_exit); 9745 9746 // Square 9747 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9748 rorq(raxReg, 32); // convert big-endian to little-endian 9749 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9750 9751 // Right shift by 1 and save carry 9752 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9753 rcrq(rdxReg, 1); 9754 rcrq(raxReg, 1); 9755 adcq(tmp5, 0); 9756 9757 // Store result in z 9758 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9759 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9760 9761 // Update indices for x and z 9762 addl(tmp1, 2); 9763 addl(tmp4, 4); 9764 jmp(L_first_loop); 9765 9766 bind(L_first_loop_exit); 9767 } 9768 9769 9770 /** 9771 * Perform the following multiply add operation using BMI2 instructions 9772 * carry:sum = sum + op1*op2 + carry 9773 * op2 should be in rdx 9774 * op2 is preserved, all other registers are modified 9775 */ 9776 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9777 // assert op2 is rdx 9778 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9779 addq(sum, carry); 9780 adcq(tmp2, 0); 9781 addq(sum, op1); 9782 adcq(tmp2, 0); 9783 movq(carry, tmp2); 9784 } 9785 9786 /** 9787 * Perform the following multiply add operation: 9788 * carry:sum = sum + op1*op2 + carry 9789 * Preserves op1, op2 and modifies rest of registers 9790 */ 9791 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9792 // rdx:rax = op1 * op2 9793 movq(raxReg, op2); 9794 mulq(op1); 9795 9796 // rdx:rax = sum + carry + rdx:rax 9797 addq(sum, carry); 9798 adcq(rdxReg, 0); 9799 addq(sum, raxReg); 9800 adcq(rdxReg, 0); 9801 9802 // carry:sum = rdx:sum 9803 movq(carry, rdxReg); 9804 } 9805 9806 /** 9807 * Add 64 bit long carry into z[] with carry propogation. 9808 * Preserves z and carry register values and modifies rest of registers. 9809 * 9810 */ 9811 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9812 Label L_fourth_loop, L_fourth_loop_exit; 9813 9814 movl(tmp1, 1); 9815 subl(zlen, 2); 9816 addq(Address(z, zlen, Address::times_4, 0), carry); 9817 9818 bind(L_fourth_loop); 9819 jccb(Assembler::carryClear, L_fourth_loop_exit); 9820 subl(zlen, 2); 9821 jccb(Assembler::negative, L_fourth_loop_exit); 9822 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9823 jmp(L_fourth_loop); 9824 bind(L_fourth_loop_exit); 9825 } 9826 9827 /** 9828 * Shift z[] left by 1 bit. 9829 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9830 * 9831 */ 9832 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9833 9834 Label L_fifth_loop, L_fifth_loop_exit; 9835 9836 // Fifth loop 9837 // Perform primitiveLeftShift(z, zlen, 1) 9838 9839 const Register prev_carry = tmp1; 9840 const Register new_carry = tmp4; 9841 const Register value = tmp2; 9842 const Register zidx = tmp3; 9843 9844 // int zidx, carry; 9845 // long value; 9846 // carry = 0; 9847 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9848 // (carry:value) = (z[i] << 1) | carry ; 9849 // z[i] = value; 9850 // } 9851 9852 movl(zidx, zlen); 9853 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9854 9855 bind(L_fifth_loop); 9856 decl(zidx); // Use decl to preserve carry flag 9857 decl(zidx); 9858 jccb(Assembler::negative, L_fifth_loop_exit); 9859 9860 if (UseBMI2Instructions) { 9861 movq(value, Address(z, zidx, Address::times_4, 0)); 9862 rclq(value, 1); 9863 rorxq(value, value, 32); 9864 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9865 } 9866 else { 9867 // clear new_carry 9868 xorl(new_carry, new_carry); 9869 9870 // Shift z[i] by 1, or in previous carry and save new carry 9871 movq(value, Address(z, zidx, Address::times_4, 0)); 9872 shlq(value, 1); 9873 adcl(new_carry, 0); 9874 9875 orq(value, prev_carry); 9876 rorq(value, 0x20); 9877 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9878 9879 // Set previous carry = new carry 9880 movl(prev_carry, new_carry); 9881 } 9882 jmp(L_fifth_loop); 9883 9884 bind(L_fifth_loop_exit); 9885 } 9886 9887 9888 /** 9889 * Code for BigInteger::squareToLen() intrinsic 9890 * 9891 * rdi: x 9892 * rsi: len 9893 * r8: z 9894 * rcx: zlen 9895 * r12: tmp1 9896 * r13: tmp2 9897 * r14: tmp3 9898 * r15: tmp4 9899 * rbx: tmp5 9900 * 9901 */ 9902 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9903 9904 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9905 push(tmp1); 9906 push(tmp2); 9907 push(tmp3); 9908 push(tmp4); 9909 push(tmp5); 9910 9911 // First loop 9912 // Store the squares, right shifted one bit (i.e., divided by 2). 9913 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9914 9915 // Add in off-diagonal sums. 9916 // 9917 // Second, third (nested) and fourth loops. 9918 // zlen +=2; 9919 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9920 // carry = 0; 9921 // long op2 = x[xidx:xidx+1]; 9922 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9923 // k -= 2; 9924 // long op1 = x[j:j+1]; 9925 // long sum = z[k:k+1]; 9926 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9927 // z[k:k+1] = sum; 9928 // } 9929 // add_one_64(z, k, carry, tmp_regs); 9930 // } 9931 9932 const Register carry = tmp5; 9933 const Register sum = tmp3; 9934 const Register op1 = tmp4; 9935 Register op2 = tmp2; 9936 9937 push(zlen); 9938 push(len); 9939 addl(zlen,2); 9940 bind(L_second_loop); 9941 xorq(carry, carry); 9942 subl(zlen, 4); 9943 subl(len, 2); 9944 push(zlen); 9945 push(len); 9946 cmpl(len, 0); 9947 jccb(Assembler::lessEqual, L_second_loop_exit); 9948 9949 // Multiply an array by one 64 bit long. 9950 if (UseBMI2Instructions) { 9951 op2 = rdxReg; 9952 movq(op2, Address(x, len, Address::times_4, 0)); 9953 rorxq(op2, op2, 32); 9954 } 9955 else { 9956 movq(op2, Address(x, len, Address::times_4, 0)); 9957 rorq(op2, 32); 9958 } 9959 9960 bind(L_third_loop); 9961 decrementl(len); 9962 jccb(Assembler::negative, L_third_loop_exit); 9963 decrementl(len); 9964 jccb(Assembler::negative, L_last_x); 9965 9966 movq(op1, Address(x, len, Address::times_4, 0)); 9967 rorq(op1, 32); 9968 9969 bind(L_multiply); 9970 subl(zlen, 2); 9971 movq(sum, Address(z, zlen, Address::times_4, 0)); 9972 9973 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9974 if (UseBMI2Instructions) { 9975 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9976 } 9977 else { 9978 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9979 } 9980 9981 movq(Address(z, zlen, Address::times_4, 0), sum); 9982 9983 jmp(L_third_loop); 9984 bind(L_third_loop_exit); 9985 9986 // Fourth loop 9987 // Add 64 bit long carry into z with carry propogation. 9988 // Uses offsetted zlen. 9989 add_one_64(z, zlen, carry, tmp1); 9990 9991 pop(len); 9992 pop(zlen); 9993 jmp(L_second_loop); 9994 9995 // Next infrequent code is moved outside loops. 9996 bind(L_last_x); 9997 movl(op1, Address(x, 0)); 9998 jmp(L_multiply); 9999 10000 bind(L_second_loop_exit); 10001 pop(len); 10002 pop(zlen); 10003 pop(len); 10004 pop(zlen); 10005 10006 // Fifth loop 10007 // Shift z left 1 bit. 10008 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 10009 10010 // z[zlen-1] |= x[len-1] & 1; 10011 movl(tmp3, Address(x, len, Address::times_4, -4)); 10012 andl(tmp3, 1); 10013 orl(Address(z, zlen, Address::times_4, -4), tmp3); 10014 10015 pop(tmp5); 10016 pop(tmp4); 10017 pop(tmp3); 10018 pop(tmp2); 10019 pop(tmp1); 10020 } 10021 10022 /** 10023 * Helper function for mul_add() 10024 * Multiply the in[] by int k and add to out[] starting at offset offs using 10025 * 128 bit by 32 bit multiply and return the carry in tmp5. 10026 * Only quad int aligned length of in[] is operated on in this function. 10027 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 10028 * This function preserves out, in and k registers. 10029 * len and offset point to the appropriate index in "in" & "out" correspondingly 10030 * tmp5 has the carry. 10031 * other registers are temporary and are modified. 10032 * 10033 */ 10034 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 10035 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 10036 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 10037 10038 Label L_first_loop, L_first_loop_exit; 10039 10040 movl(tmp1, len); 10041 shrl(tmp1, 2); 10042 10043 bind(L_first_loop); 10044 subl(tmp1, 1); 10045 jccb(Assembler::negative, L_first_loop_exit); 10046 10047 subl(len, 4); 10048 subl(offset, 4); 10049 10050 Register op2 = tmp2; 10051 const Register sum = tmp3; 10052 const Register op1 = tmp4; 10053 const Register carry = tmp5; 10054 10055 if (UseBMI2Instructions) { 10056 op2 = rdxReg; 10057 } 10058 10059 movq(op1, Address(in, len, Address::times_4, 8)); 10060 rorq(op1, 32); 10061 movq(sum, Address(out, offset, Address::times_4, 8)); 10062 rorq(sum, 32); 10063 if (UseBMI2Instructions) { 10064 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10065 } 10066 else { 10067 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10068 } 10069 // Store back in big endian from little endian 10070 rorq(sum, 0x20); 10071 movq(Address(out, offset, Address::times_4, 8), sum); 10072 10073 movq(op1, Address(in, len, Address::times_4, 0)); 10074 rorq(op1, 32); 10075 movq(sum, Address(out, offset, Address::times_4, 0)); 10076 rorq(sum, 32); 10077 if (UseBMI2Instructions) { 10078 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10079 } 10080 else { 10081 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10082 } 10083 // Store back in big endian from little endian 10084 rorq(sum, 0x20); 10085 movq(Address(out, offset, Address::times_4, 0), sum); 10086 10087 jmp(L_first_loop); 10088 bind(L_first_loop_exit); 10089 } 10090 10091 /** 10092 * Code for BigInteger::mulAdd() intrinsic 10093 * 10094 * rdi: out 10095 * rsi: in 10096 * r11: offs (out.length - offset) 10097 * rcx: len 10098 * r8: k 10099 * r12: tmp1 10100 * r13: tmp2 10101 * r14: tmp3 10102 * r15: tmp4 10103 * rbx: tmp5 10104 * Multiply the in[] by word k and add to out[], return the carry in rax 10105 */ 10106 void MacroAssembler::mul_add(Register out, Register in, Register offs, 10107 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 10108 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 10109 10110 Label L_carry, L_last_in, L_done; 10111 10112 // carry = 0; 10113 // for (int j=len-1; j >= 0; j--) { 10114 // long product = (in[j] & LONG_MASK) * kLong + 10115 // (out[offs] & LONG_MASK) + carry; 10116 // out[offs--] = (int)product; 10117 // carry = product >>> 32; 10118 // } 10119 // 10120 push(tmp1); 10121 push(tmp2); 10122 push(tmp3); 10123 push(tmp4); 10124 push(tmp5); 10125 10126 Register op2 = tmp2; 10127 const Register sum = tmp3; 10128 const Register op1 = tmp4; 10129 const Register carry = tmp5; 10130 10131 if (UseBMI2Instructions) { 10132 op2 = rdxReg; 10133 movl(op2, k); 10134 } 10135 else { 10136 movl(op2, k); 10137 } 10138 10139 xorq(carry, carry); 10140 10141 //First loop 10142 10143 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 10144 //The carry is in tmp5 10145 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 10146 10147 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 10148 decrementl(len); 10149 jccb(Assembler::negative, L_carry); 10150 decrementl(len); 10151 jccb(Assembler::negative, L_last_in); 10152 10153 movq(op1, Address(in, len, Address::times_4, 0)); 10154 rorq(op1, 32); 10155 10156 subl(offs, 2); 10157 movq(sum, Address(out, offs, Address::times_4, 0)); 10158 rorq(sum, 32); 10159 10160 if (UseBMI2Instructions) { 10161 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10162 } 10163 else { 10164 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10165 } 10166 10167 // Store back in big endian from little endian 10168 rorq(sum, 0x20); 10169 movq(Address(out, offs, Address::times_4, 0), sum); 10170 10171 testl(len, len); 10172 jccb(Assembler::zero, L_carry); 10173 10174 //Multiply the last in[] entry, if any 10175 bind(L_last_in); 10176 movl(op1, Address(in, 0)); 10177 movl(sum, Address(out, offs, Address::times_4, -4)); 10178 10179 movl(raxReg, k); 10180 mull(op1); //tmp4 * eax -> edx:eax 10181 addl(sum, carry); 10182 adcl(rdxReg, 0); 10183 addl(sum, raxReg); 10184 adcl(rdxReg, 0); 10185 movl(carry, rdxReg); 10186 10187 movl(Address(out, offs, Address::times_4, -4), sum); 10188 10189 bind(L_carry); 10190 //return tmp5/carry as carry in rax 10191 movl(rax, carry); 10192 10193 bind(L_done); 10194 pop(tmp5); 10195 pop(tmp4); 10196 pop(tmp3); 10197 pop(tmp2); 10198 pop(tmp1); 10199 } 10200 #endif 10201 10202 /** 10203 * Emits code to update CRC-32 with a byte value according to constants in table 10204 * 10205 * @param [in,out]crc Register containing the crc. 10206 * @param [in]val Register containing the byte to fold into the CRC. 10207 * @param [in]table Register containing the table of crc constants. 10208 * 10209 * uint32_t crc; 10210 * val = crc_table[(val ^ crc) & 0xFF]; 10211 * crc = val ^ (crc >> 8); 10212 * 10213 */ 10214 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10215 xorl(val, crc); 10216 andl(val, 0xFF); 10217 shrl(crc, 8); // unsigned shift 10218 xorl(crc, Address(table, val, Address::times_4, 0)); 10219 } 10220 10221 /** 10222 * Fold 128-bit data chunk 10223 */ 10224 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10225 if (UseAVX > 0) { 10226 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10227 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10228 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10229 pxor(xcrc, xtmp); 10230 } else { 10231 movdqa(xtmp, xcrc); 10232 pclmulhdq(xtmp, xK); // [123:64] 10233 pclmulldq(xcrc, xK); // [63:0] 10234 pxor(xcrc, xtmp); 10235 movdqu(xtmp, Address(buf, offset)); 10236 pxor(xcrc, xtmp); 10237 } 10238 } 10239 10240 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10241 if (UseAVX > 0) { 10242 vpclmulhdq(xtmp, xK, xcrc); 10243 vpclmulldq(xcrc, xK, xcrc); 10244 pxor(xcrc, xbuf); 10245 pxor(xcrc, xtmp); 10246 } else { 10247 movdqa(xtmp, xcrc); 10248 pclmulhdq(xtmp, xK); 10249 pclmulldq(xcrc, xK); 10250 pxor(xcrc, xbuf); 10251 pxor(xcrc, xtmp); 10252 } 10253 } 10254 10255 /** 10256 * 8-bit folds to compute 32-bit CRC 10257 * 10258 * uint64_t xcrc; 10259 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10260 */ 10261 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10262 movdl(tmp, xcrc); 10263 andl(tmp, 0xFF); 10264 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10265 psrldq(xcrc, 1); // unsigned shift one byte 10266 pxor(xcrc, xtmp); 10267 } 10268 10269 /** 10270 * uint32_t crc; 10271 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10272 */ 10273 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10274 movl(tmp, crc); 10275 andl(tmp, 0xFF); 10276 shrl(crc, 8); 10277 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10278 } 10279 10280 /** 10281 * @param crc register containing existing CRC (32-bit) 10282 * @param buf register pointing to input byte buffer (byte*) 10283 * @param len register containing number of bytes 10284 * @param table register that will contain address of CRC table 10285 * @param tmp scratch register 10286 */ 10287 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10288 assert_different_registers(crc, buf, len, table, tmp, rax); 10289 10290 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10291 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10292 10293 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10294 // context for the registers used, where all instructions below are using 128-bit mode 10295 // On EVEX without VL and BW, these instructions will all be AVX. 10296 if (VM_Version::supports_avx512vlbw()) { 10297 movl(tmp, 0xffff); 10298 kmovwl(k1, tmp); 10299 } 10300 10301 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10302 notl(crc); // ~crc 10303 cmpl(len, 16); 10304 jcc(Assembler::less, L_tail); 10305 10306 // Align buffer to 16 bytes 10307 movl(tmp, buf); 10308 andl(tmp, 0xF); 10309 jccb(Assembler::zero, L_aligned); 10310 subl(tmp, 16); 10311 addl(len, tmp); 10312 10313 align(4); 10314 BIND(L_align_loop); 10315 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10316 update_byte_crc32(crc, rax, table); 10317 increment(buf); 10318 incrementl(tmp); 10319 jccb(Assembler::less, L_align_loop); 10320 10321 BIND(L_aligned); 10322 movl(tmp, len); // save 10323 shrl(len, 4); 10324 jcc(Assembler::zero, L_tail_restore); 10325 10326 // Fold crc into first bytes of vector 10327 movdqa(xmm1, Address(buf, 0)); 10328 movdl(rax, xmm1); 10329 xorl(crc, rax); 10330 pinsrd(xmm1, crc, 0); 10331 addptr(buf, 16); 10332 subl(len, 4); // len > 0 10333 jcc(Assembler::less, L_fold_tail); 10334 10335 movdqa(xmm2, Address(buf, 0)); 10336 movdqa(xmm3, Address(buf, 16)); 10337 movdqa(xmm4, Address(buf, 32)); 10338 addptr(buf, 48); 10339 subl(len, 3); 10340 jcc(Assembler::lessEqual, L_fold_512b); 10341 10342 // Fold total 512 bits of polynomial on each iteration, 10343 // 128 bits per each of 4 parallel streams. 10344 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10345 10346 align(32); 10347 BIND(L_fold_512b_loop); 10348 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10349 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10350 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10351 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10352 addptr(buf, 64); 10353 subl(len, 4); 10354 jcc(Assembler::greater, L_fold_512b_loop); 10355 10356 // Fold 512 bits to 128 bits. 10357 BIND(L_fold_512b); 10358 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10359 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10360 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10361 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10362 10363 // Fold the rest of 128 bits data chunks 10364 BIND(L_fold_tail); 10365 addl(len, 3); 10366 jccb(Assembler::lessEqual, L_fold_128b); 10367 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10368 10369 BIND(L_fold_tail_loop); 10370 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10371 addptr(buf, 16); 10372 decrementl(len); 10373 jccb(Assembler::greater, L_fold_tail_loop); 10374 10375 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10376 BIND(L_fold_128b); 10377 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10378 if (UseAVX > 0) { 10379 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10380 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10381 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10382 } else { 10383 movdqa(xmm2, xmm0); 10384 pclmulqdq(xmm2, xmm1, 0x1); 10385 movdqa(xmm3, xmm0); 10386 pand(xmm3, xmm2); 10387 pclmulqdq(xmm0, xmm3, 0x1); 10388 } 10389 psrldq(xmm1, 8); 10390 psrldq(xmm2, 4); 10391 pxor(xmm0, xmm1); 10392 pxor(xmm0, xmm2); 10393 10394 // 8 8-bit folds to compute 32-bit CRC. 10395 for (int j = 0; j < 4; j++) { 10396 fold_8bit_crc32(xmm0, table, xmm1, rax); 10397 } 10398 movdl(crc, xmm0); // mov 32 bits to general register 10399 for (int j = 0; j < 4; j++) { 10400 fold_8bit_crc32(crc, table, rax); 10401 } 10402 10403 BIND(L_tail_restore); 10404 movl(len, tmp); // restore 10405 BIND(L_tail); 10406 andl(len, 0xf); 10407 jccb(Assembler::zero, L_exit); 10408 10409 // Fold the rest of bytes 10410 align(4); 10411 BIND(L_tail_loop); 10412 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10413 update_byte_crc32(crc, rax, table); 10414 increment(buf); 10415 decrementl(len); 10416 jccb(Assembler::greater, L_tail_loop); 10417 10418 BIND(L_exit); 10419 notl(crc); // ~c 10420 } 10421 10422 #ifdef _LP64 10423 // S. Gueron / Information Processing Letters 112 (2012) 184 10424 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10425 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10426 // Output: the 64-bit carry-less product of B * CONST 10427 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10428 Register tmp1, Register tmp2, Register tmp3) { 10429 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10430 if (n > 0) { 10431 addq(tmp3, n * 256 * 8); 10432 } 10433 // Q1 = TABLEExt[n][B & 0xFF]; 10434 movl(tmp1, in); 10435 andl(tmp1, 0x000000FF); 10436 shll(tmp1, 3); 10437 addq(tmp1, tmp3); 10438 movq(tmp1, Address(tmp1, 0)); 10439 10440 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10441 movl(tmp2, in); 10442 shrl(tmp2, 8); 10443 andl(tmp2, 0x000000FF); 10444 shll(tmp2, 3); 10445 addq(tmp2, tmp3); 10446 movq(tmp2, Address(tmp2, 0)); 10447 10448 shlq(tmp2, 8); 10449 xorq(tmp1, tmp2); 10450 10451 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10452 movl(tmp2, in); 10453 shrl(tmp2, 16); 10454 andl(tmp2, 0x000000FF); 10455 shll(tmp2, 3); 10456 addq(tmp2, tmp3); 10457 movq(tmp2, Address(tmp2, 0)); 10458 10459 shlq(tmp2, 16); 10460 xorq(tmp1, tmp2); 10461 10462 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10463 shrl(in, 24); 10464 andl(in, 0x000000FF); 10465 shll(in, 3); 10466 addq(in, tmp3); 10467 movq(in, Address(in, 0)); 10468 10469 shlq(in, 24); 10470 xorq(in, tmp1); 10471 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10472 } 10473 10474 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10475 Register in_out, 10476 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10477 XMMRegister w_xtmp2, 10478 Register tmp1, 10479 Register n_tmp2, Register n_tmp3) { 10480 if (is_pclmulqdq_supported) { 10481 movdl(w_xtmp1, in_out); // modified blindly 10482 10483 movl(tmp1, const_or_pre_comp_const_index); 10484 movdl(w_xtmp2, tmp1); 10485 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10486 10487 movdq(in_out, w_xtmp1); 10488 } else { 10489 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10490 } 10491 } 10492 10493 // Recombination Alternative 2: No bit-reflections 10494 // T1 = (CRC_A * U1) << 1 10495 // T2 = (CRC_B * U2) << 1 10496 // C1 = T1 >> 32 10497 // C2 = T2 >> 32 10498 // T1 = T1 & 0xFFFFFFFF 10499 // T2 = T2 & 0xFFFFFFFF 10500 // T1 = CRC32(0, T1) 10501 // T2 = CRC32(0, T2) 10502 // C1 = C1 ^ T1 10503 // C2 = C2 ^ T2 10504 // CRC = C1 ^ C2 ^ CRC_C 10505 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10506 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10507 Register tmp1, Register tmp2, 10508 Register n_tmp3) { 10509 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10510 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10511 shlq(in_out, 1); 10512 movl(tmp1, in_out); 10513 shrq(in_out, 32); 10514 xorl(tmp2, tmp2); 10515 crc32(tmp2, tmp1, 4); 10516 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10517 shlq(in1, 1); 10518 movl(tmp1, in1); 10519 shrq(in1, 32); 10520 xorl(tmp2, tmp2); 10521 crc32(tmp2, tmp1, 4); 10522 xorl(in1, tmp2); 10523 xorl(in_out, in1); 10524 xorl(in_out, in2); 10525 } 10526 10527 // Set N to predefined value 10528 // Subtract from a lenght of a buffer 10529 // execute in a loop: 10530 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10531 // for i = 1 to N do 10532 // CRC_A = CRC32(CRC_A, A[i]) 10533 // CRC_B = CRC32(CRC_B, B[i]) 10534 // CRC_C = CRC32(CRC_C, C[i]) 10535 // end for 10536 // Recombine 10537 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10538 Register in_out1, Register in_out2, Register in_out3, 10539 Register tmp1, Register tmp2, Register tmp3, 10540 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10541 Register tmp4, Register tmp5, 10542 Register n_tmp6) { 10543 Label L_processPartitions; 10544 Label L_processPartition; 10545 Label L_exit; 10546 10547 bind(L_processPartitions); 10548 cmpl(in_out1, 3 * size); 10549 jcc(Assembler::less, L_exit); 10550 xorl(tmp1, tmp1); 10551 xorl(tmp2, tmp2); 10552 movq(tmp3, in_out2); 10553 addq(tmp3, size); 10554 10555 bind(L_processPartition); 10556 crc32(in_out3, Address(in_out2, 0), 8); 10557 crc32(tmp1, Address(in_out2, size), 8); 10558 crc32(tmp2, Address(in_out2, size * 2), 8); 10559 addq(in_out2, 8); 10560 cmpq(in_out2, tmp3); 10561 jcc(Assembler::less, L_processPartition); 10562 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10563 w_xtmp1, w_xtmp2, w_xtmp3, 10564 tmp4, tmp5, 10565 n_tmp6); 10566 addq(in_out2, 2 * size); 10567 subl(in_out1, 3 * size); 10568 jmp(L_processPartitions); 10569 10570 bind(L_exit); 10571 } 10572 #else 10573 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10574 Register tmp1, Register tmp2, Register tmp3, 10575 XMMRegister xtmp1, XMMRegister xtmp2) { 10576 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10577 if (n > 0) { 10578 addl(tmp3, n * 256 * 8); 10579 } 10580 // Q1 = TABLEExt[n][B & 0xFF]; 10581 movl(tmp1, in_out); 10582 andl(tmp1, 0x000000FF); 10583 shll(tmp1, 3); 10584 addl(tmp1, tmp3); 10585 movq(xtmp1, Address(tmp1, 0)); 10586 10587 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10588 movl(tmp2, in_out); 10589 shrl(tmp2, 8); 10590 andl(tmp2, 0x000000FF); 10591 shll(tmp2, 3); 10592 addl(tmp2, tmp3); 10593 movq(xtmp2, Address(tmp2, 0)); 10594 10595 psllq(xtmp2, 8); 10596 pxor(xtmp1, xtmp2); 10597 10598 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10599 movl(tmp2, in_out); 10600 shrl(tmp2, 16); 10601 andl(tmp2, 0x000000FF); 10602 shll(tmp2, 3); 10603 addl(tmp2, tmp3); 10604 movq(xtmp2, Address(tmp2, 0)); 10605 10606 psllq(xtmp2, 16); 10607 pxor(xtmp1, xtmp2); 10608 10609 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10610 shrl(in_out, 24); 10611 andl(in_out, 0x000000FF); 10612 shll(in_out, 3); 10613 addl(in_out, tmp3); 10614 movq(xtmp2, Address(in_out, 0)); 10615 10616 psllq(xtmp2, 24); 10617 pxor(xtmp1, xtmp2); // Result in CXMM 10618 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10619 } 10620 10621 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10622 Register in_out, 10623 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10624 XMMRegister w_xtmp2, 10625 Register tmp1, 10626 Register n_tmp2, Register n_tmp3) { 10627 if (is_pclmulqdq_supported) { 10628 movdl(w_xtmp1, in_out); 10629 10630 movl(tmp1, const_or_pre_comp_const_index); 10631 movdl(w_xtmp2, tmp1); 10632 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10633 // Keep result in XMM since GPR is 32 bit in length 10634 } else { 10635 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10636 } 10637 } 10638 10639 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10640 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10641 Register tmp1, Register tmp2, 10642 Register n_tmp3) { 10643 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10644 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10645 10646 psllq(w_xtmp1, 1); 10647 movdl(tmp1, w_xtmp1); 10648 psrlq(w_xtmp1, 32); 10649 movdl(in_out, w_xtmp1); 10650 10651 xorl(tmp2, tmp2); 10652 crc32(tmp2, tmp1, 4); 10653 xorl(in_out, tmp2); 10654 10655 psllq(w_xtmp2, 1); 10656 movdl(tmp1, w_xtmp2); 10657 psrlq(w_xtmp2, 32); 10658 movdl(in1, w_xtmp2); 10659 10660 xorl(tmp2, tmp2); 10661 crc32(tmp2, tmp1, 4); 10662 xorl(in1, tmp2); 10663 xorl(in_out, in1); 10664 xorl(in_out, in2); 10665 } 10666 10667 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10668 Register in_out1, Register in_out2, Register in_out3, 10669 Register tmp1, Register tmp2, Register tmp3, 10670 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10671 Register tmp4, Register tmp5, 10672 Register n_tmp6) { 10673 Label L_processPartitions; 10674 Label L_processPartition; 10675 Label L_exit; 10676 10677 bind(L_processPartitions); 10678 cmpl(in_out1, 3 * size); 10679 jcc(Assembler::less, L_exit); 10680 xorl(tmp1, tmp1); 10681 xorl(tmp2, tmp2); 10682 movl(tmp3, in_out2); 10683 addl(tmp3, size); 10684 10685 bind(L_processPartition); 10686 crc32(in_out3, Address(in_out2, 0), 4); 10687 crc32(tmp1, Address(in_out2, size), 4); 10688 crc32(tmp2, Address(in_out2, size*2), 4); 10689 crc32(in_out3, Address(in_out2, 0+4), 4); 10690 crc32(tmp1, Address(in_out2, size+4), 4); 10691 crc32(tmp2, Address(in_out2, size*2+4), 4); 10692 addl(in_out2, 8); 10693 cmpl(in_out2, tmp3); 10694 jcc(Assembler::less, L_processPartition); 10695 10696 push(tmp3); 10697 push(in_out1); 10698 push(in_out2); 10699 tmp4 = tmp3; 10700 tmp5 = in_out1; 10701 n_tmp6 = in_out2; 10702 10703 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10704 w_xtmp1, w_xtmp2, w_xtmp3, 10705 tmp4, tmp5, 10706 n_tmp6); 10707 10708 pop(in_out2); 10709 pop(in_out1); 10710 pop(tmp3); 10711 10712 addl(in_out2, 2 * size); 10713 subl(in_out1, 3 * size); 10714 jmp(L_processPartitions); 10715 10716 bind(L_exit); 10717 } 10718 #endif //LP64 10719 10720 #ifdef _LP64 10721 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10722 // Input: A buffer I of L bytes. 10723 // Output: the CRC32C value of the buffer. 10724 // Notations: 10725 // Write L = 24N + r, with N = floor (L/24). 10726 // r = L mod 24 (0 <= r < 24). 10727 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10728 // N quadwords, and R consists of r bytes. 10729 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10730 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10731 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10732 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10733 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10734 Register tmp1, Register tmp2, Register tmp3, 10735 Register tmp4, Register tmp5, Register tmp6, 10736 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10737 bool is_pclmulqdq_supported) { 10738 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10739 Label L_wordByWord; 10740 Label L_byteByByteProlog; 10741 Label L_byteByByte; 10742 Label L_exit; 10743 10744 if (is_pclmulqdq_supported ) { 10745 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10746 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10747 10748 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10749 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10750 10751 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10752 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10753 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10754 } else { 10755 const_or_pre_comp_const_index[0] = 1; 10756 const_or_pre_comp_const_index[1] = 0; 10757 10758 const_or_pre_comp_const_index[2] = 3; 10759 const_or_pre_comp_const_index[3] = 2; 10760 10761 const_or_pre_comp_const_index[4] = 5; 10762 const_or_pre_comp_const_index[5] = 4; 10763 } 10764 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10765 in2, in1, in_out, 10766 tmp1, tmp2, tmp3, 10767 w_xtmp1, w_xtmp2, w_xtmp3, 10768 tmp4, tmp5, 10769 tmp6); 10770 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10771 in2, in1, in_out, 10772 tmp1, tmp2, tmp3, 10773 w_xtmp1, w_xtmp2, w_xtmp3, 10774 tmp4, tmp5, 10775 tmp6); 10776 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10777 in2, in1, in_out, 10778 tmp1, tmp2, tmp3, 10779 w_xtmp1, w_xtmp2, w_xtmp3, 10780 tmp4, tmp5, 10781 tmp6); 10782 movl(tmp1, in2); 10783 andl(tmp1, 0x00000007); 10784 negl(tmp1); 10785 addl(tmp1, in2); 10786 addq(tmp1, in1); 10787 10788 BIND(L_wordByWord); 10789 cmpq(in1, tmp1); 10790 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10791 crc32(in_out, Address(in1, 0), 4); 10792 addq(in1, 4); 10793 jmp(L_wordByWord); 10794 10795 BIND(L_byteByByteProlog); 10796 andl(in2, 0x00000007); 10797 movl(tmp2, 1); 10798 10799 BIND(L_byteByByte); 10800 cmpl(tmp2, in2); 10801 jccb(Assembler::greater, L_exit); 10802 crc32(in_out, Address(in1, 0), 1); 10803 incq(in1); 10804 incl(tmp2); 10805 jmp(L_byteByByte); 10806 10807 BIND(L_exit); 10808 } 10809 #else 10810 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10811 Register tmp1, Register tmp2, Register tmp3, 10812 Register tmp4, Register tmp5, Register tmp6, 10813 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10814 bool is_pclmulqdq_supported) { 10815 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10816 Label L_wordByWord; 10817 Label L_byteByByteProlog; 10818 Label L_byteByByte; 10819 Label L_exit; 10820 10821 if (is_pclmulqdq_supported) { 10822 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10823 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10824 10825 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10826 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10827 10828 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10829 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10830 } else { 10831 const_or_pre_comp_const_index[0] = 1; 10832 const_or_pre_comp_const_index[1] = 0; 10833 10834 const_or_pre_comp_const_index[2] = 3; 10835 const_or_pre_comp_const_index[3] = 2; 10836 10837 const_or_pre_comp_const_index[4] = 5; 10838 const_or_pre_comp_const_index[5] = 4; 10839 } 10840 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10841 in2, in1, in_out, 10842 tmp1, tmp2, tmp3, 10843 w_xtmp1, w_xtmp2, w_xtmp3, 10844 tmp4, tmp5, 10845 tmp6); 10846 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10847 in2, in1, in_out, 10848 tmp1, tmp2, tmp3, 10849 w_xtmp1, w_xtmp2, w_xtmp3, 10850 tmp4, tmp5, 10851 tmp6); 10852 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10853 in2, in1, in_out, 10854 tmp1, tmp2, tmp3, 10855 w_xtmp1, w_xtmp2, w_xtmp3, 10856 tmp4, tmp5, 10857 tmp6); 10858 movl(tmp1, in2); 10859 andl(tmp1, 0x00000007); 10860 negl(tmp1); 10861 addl(tmp1, in2); 10862 addl(tmp1, in1); 10863 10864 BIND(L_wordByWord); 10865 cmpl(in1, tmp1); 10866 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10867 crc32(in_out, Address(in1,0), 4); 10868 addl(in1, 4); 10869 jmp(L_wordByWord); 10870 10871 BIND(L_byteByByteProlog); 10872 andl(in2, 0x00000007); 10873 movl(tmp2, 1); 10874 10875 BIND(L_byteByByte); 10876 cmpl(tmp2, in2); 10877 jccb(Assembler::greater, L_exit); 10878 movb(tmp1, Address(in1, 0)); 10879 crc32(in_out, tmp1, 1); 10880 incl(in1); 10881 incl(tmp2); 10882 jmp(L_byteByByte); 10883 10884 BIND(L_exit); 10885 } 10886 #endif // LP64 10887 #undef BIND 10888 #undef BLOCK_COMMENT 10889 10890 // Compress char[] array to byte[]. 10891 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10892 // @HotSpotIntrinsicCandidate 10893 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10894 // for (int i = 0; i < len; i++) { 10895 // int c = src[srcOff++]; 10896 // if (c >>> 8 != 0) { 10897 // return 0; 10898 // } 10899 // dst[dstOff++] = (byte)c; 10900 // } 10901 // return len; 10902 // } 10903 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10904 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10905 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10906 Register tmp5, Register result) { 10907 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10908 10909 // rsi: src 10910 // rdi: dst 10911 // rdx: len 10912 // rcx: tmp5 10913 // rax: result 10914 10915 // rsi holds start addr of source char[] to be compressed 10916 // rdi holds start addr of destination byte[] 10917 // rdx holds length 10918 10919 assert(len != result, ""); 10920 10921 // save length for return 10922 push(len); 10923 10924 if ((UseAVX > 2) && // AVX512 10925 VM_Version::supports_avx512vlbw() && 10926 VM_Version::supports_bmi2()) { 10927 10928 set_vector_masking(); // opening of the stub context for programming mask registers 10929 10930 Label copy_32_loop, copy_loop_tail, copy_just_portion_of_candidates; 10931 10932 // alignement 10933 Label post_alignement; 10934 10935 // if length of the string is less than 16, handle it in an old fashioned 10936 // way 10937 testl(len, -32); 10938 jcc(Assembler::zero, below_threshold); 10939 10940 // First check whether a character is compressable ( <= 0xFF). 10941 // Create mask to test for Unicode chars inside zmm vector 10942 movl(result, 0x00FF); 10943 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10944 10945 testl(len, -64); 10946 jcc(Assembler::zero, post_alignement); 10947 10948 // Save k1 10949 kmovql(k3, k1); 10950 10951 movl(tmp5, dst); 10952 andl(tmp5, (64 - 1)); 10953 negl(tmp5); 10954 andl(tmp5, (64 - 1)); 10955 10956 // bail out when there is nothing to be done 10957 testl(tmp5, 0xFFFFFFFF); 10958 jcc(Assembler::zero, post_alignement); 10959 10960 // ~(~0 << len), where len is the # of remaining elements to process 10961 movl(result, 0xFFFFFFFF); 10962 shlxl(result, result, tmp5); 10963 notl(result); 10964 10965 kmovdl(k1, result); 10966 10967 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10968 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, ComparisonPredicate::le, Assembler::AVX_512bit); 10969 ktestd(k2, k1); 10970 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10971 10972 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10973 10974 addptr(src, tmp5); 10975 addptr(src, tmp5); 10976 addptr(dst, tmp5); 10977 subl(len, tmp5); 10978 10979 bind(post_alignement); 10980 // end of alignement 10981 10982 movl(tmp5, len); 10983 andl(tmp5, (32 - 1)); // tail count (in chars) 10984 andl(len, ~(32 - 1)); // vector count (in chars) 10985 jcc(Assembler::zero, copy_loop_tail); 10986 10987 lea(src, Address(src, len, Address::times_2)); 10988 lea(dst, Address(dst, len, Address::times_1)); 10989 negptr(len); 10990 10991 bind(copy_32_loop); 10992 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10993 evpcmpuw(k2, tmp1Reg, tmp2Reg, ComparisonPredicate::le, Assembler::AVX_512bit); 10994 kortestdl(k2, k2); 10995 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10996 10997 // All elements in current processed chunk are valid candidates for 10998 // compression. Write a truncated byte elements to the memory. 10999 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 11000 addptr(len, 32); 11001 jcc(Assembler::notZero, copy_32_loop); 11002 11003 bind(copy_loop_tail); 11004 // bail out when there is nothing to be done 11005 testl(tmp5, 0xFFFFFFFF); 11006 jcc(Assembler::zero, return_length); 11007 11008 // Save k1 11009 kmovql(k3, k1); 11010 11011 movl(len, tmp5); 11012 11013 // ~(~0 << len), where len is the # of remaining elements to process 11014 movl(result, 0xFFFFFFFF); 11015 shlxl(result, result, len); 11016 notl(result); 11017 11018 kmovdl(k1, result); 11019 11020 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 11021 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, ComparisonPredicate::le, Assembler::AVX_512bit); 11022 ktestd(k2, k1); 11023 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 11024 11025 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 11026 // Restore k1 11027 kmovql(k1, k3); 11028 11029 jmp(return_length); 11030 11031 bind(copy_just_portion_of_candidates); 11032 kmovdl(tmp5, k2); 11033 tzcntl(tmp5, tmp5); 11034 11035 // ~(~0 << tmp5), where tmp5 is a number of elements in an array from the 11036 // result to the first element larger than 0xFF 11037 movl(result, 0xFFFFFFFF); 11038 shlxl(result, result, tmp5); 11039 notl(result); 11040 11041 kmovdl(k1, result); 11042 11043 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 11044 // Restore k1 11045 kmovql(k1, k3); 11046 11047 jmp(return_zero); 11048 11049 clear_vector_masking(); // closing of the stub context for programming mask registers 11050 } 11051 if (UseSSE42Intrinsics) { 11052 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 11053 Label copy_32_loop, copy_16, copy_tail; 11054 11055 bind(below_threshold); 11056 11057 movl(result, len); 11058 11059 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 11060 11061 // vectored compression 11062 andl(len, 0xfffffff0); // vector count (in chars) 11063 andl(result, 0x0000000f); // tail count (in chars) 11064 testl(len, len); 11065 jccb(Assembler::zero, copy_16); 11066 11067 // compress 16 chars per iter 11068 movdl(tmp1Reg, tmp5); 11069 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11070 pxor(tmp4Reg, tmp4Reg); 11071 11072 lea(src, Address(src, len, Address::times_2)); 11073 lea(dst, Address(dst, len, Address::times_1)); 11074 negptr(len); 11075 11076 bind(copy_32_loop); 11077 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 11078 por(tmp4Reg, tmp2Reg); 11079 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 11080 por(tmp4Reg, tmp3Reg); 11081 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 11082 jcc(Assembler::notZero, return_zero); 11083 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 11084 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 11085 addptr(len, 16); 11086 jcc(Assembler::notZero, copy_32_loop); 11087 11088 // compress next vector of 8 chars (if any) 11089 bind(copy_16); 11090 movl(len, result); 11091 andl(len, 0xfffffff8); // vector count (in chars) 11092 andl(result, 0x00000007); // tail count (in chars) 11093 testl(len, len); 11094 jccb(Assembler::zero, copy_tail); 11095 11096 movdl(tmp1Reg, tmp5); 11097 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11098 pxor(tmp3Reg, tmp3Reg); 11099 11100 movdqu(tmp2Reg, Address(src, 0)); 11101 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 11102 jccb(Assembler::notZero, return_zero); 11103 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 11104 movq(Address(dst, 0), tmp2Reg); 11105 addptr(src, 16); 11106 addptr(dst, 8); 11107 11108 bind(copy_tail); 11109 movl(len, result); 11110 } 11111 // compress 1 char per iter 11112 testl(len, len); 11113 jccb(Assembler::zero, return_length); 11114 lea(src, Address(src, len, Address::times_2)); 11115 lea(dst, Address(dst, len, Address::times_1)); 11116 negptr(len); 11117 11118 bind(copy_chars_loop); 11119 load_unsigned_short(result, Address(src, len, Address::times_2)); 11120 testl(result, 0xff00); // check if Unicode char 11121 jccb(Assembler::notZero, return_zero); 11122 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 11123 increment(len); 11124 jcc(Assembler::notZero, copy_chars_loop); 11125 11126 // if compression succeeded, return length 11127 bind(return_length); 11128 pop(result); 11129 jmpb(done); 11130 11131 // if compression failed, return 0 11132 bind(return_zero); 11133 xorl(result, result); 11134 addptr(rsp, wordSize); 11135 11136 bind(done); 11137 } 11138 11139 // Inflate byte[] array to char[]. 11140 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 11141 // @HotSpotIntrinsicCandidate 11142 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 11143 // for (int i = 0; i < len; i++) { 11144 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 11145 // } 11146 // } 11147 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 11148 XMMRegister tmp1, Register tmp2) { 11149 Label copy_chars_loop, done, below_threshold; 11150 // rsi: src 11151 // rdi: dst 11152 // rdx: len 11153 // rcx: tmp2 11154 11155 // rsi holds start addr of source byte[] to be inflated 11156 // rdi holds start addr of destination char[] 11157 // rdx holds length 11158 assert_different_registers(src, dst, len, tmp2); 11159 11160 if ((UseAVX > 2) && // AVX512 11161 VM_Version::supports_avx512vlbw() && 11162 VM_Version::supports_bmi2()) { 11163 11164 set_vector_masking(); // opening of the stub context for programming mask registers 11165 11166 Label copy_32_loop, copy_tail; 11167 Register tmp3_aliased = len; 11168 11169 // if length of the string is less than 16, handle it in an old fashioned 11170 // way 11171 testl(len, -16); 11172 jcc(Assembler::zero, below_threshold); 11173 11174 // In order to use only one arithmetic operation for the main loop we use 11175 // this pre-calculation 11176 movl(tmp2, len); 11177 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11178 andl(len, -32); // vector count 11179 jccb(Assembler::zero, copy_tail); 11180 11181 lea(src, Address(src, len, Address::times_1)); 11182 lea(dst, Address(dst, len, Address::times_2)); 11183 negptr(len); 11184 11185 11186 // inflate 32 chars per iter 11187 bind(copy_32_loop); 11188 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11189 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11190 addptr(len, 32); 11191 jcc(Assembler::notZero, copy_32_loop); 11192 11193 bind(copy_tail); 11194 // bail out when there is nothing to be done 11195 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11196 jcc(Assembler::zero, done); 11197 11198 // Save k1 11199 kmovql(k2, k1); 11200 11201 // ~(~0 << length), where length is the # of remaining elements to process 11202 movl(tmp3_aliased, -1); 11203 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11204 notl(tmp3_aliased); 11205 kmovdl(k1, tmp3_aliased); 11206 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11207 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11208 11209 // Restore k1 11210 kmovql(k1, k2); 11211 jmp(done); 11212 11213 clear_vector_masking(); // closing of the stub context for programming mask registers 11214 } 11215 if (UseSSE42Intrinsics) { 11216 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 11217 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11218 11219 movl(tmp2, len); 11220 11221 if (UseAVX > 1) { 11222 andl(tmp2, (16 - 1)); 11223 andl(len, -16); 11224 jccb(Assembler::zero, copy_new_tail); 11225 } else { 11226 andl(tmp2, 0x00000007); // tail count (in chars) 11227 andl(len, 0xfffffff8); // vector count (in chars) 11228 jccb(Assembler::zero, copy_tail); 11229 } 11230 11231 // vectored inflation 11232 lea(src, Address(src, len, Address::times_1)); 11233 lea(dst, Address(dst, len, Address::times_2)); 11234 negptr(len); 11235 11236 if (UseAVX > 1) { 11237 bind(copy_16_loop); 11238 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11239 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11240 addptr(len, 16); 11241 jcc(Assembler::notZero, copy_16_loop); 11242 11243 bind(below_threshold); 11244 bind(copy_new_tail); 11245 if (UseAVX > 2) { 11246 movl(tmp2, len); 11247 } 11248 else { 11249 movl(len, tmp2); 11250 } 11251 andl(tmp2, 0x00000007); 11252 andl(len, 0xFFFFFFF8); 11253 jccb(Assembler::zero, copy_tail); 11254 11255 pmovzxbw(tmp1, Address(src, 0)); 11256 movdqu(Address(dst, 0), tmp1); 11257 addptr(src, 8); 11258 addptr(dst, 2 * 8); 11259 11260 jmp(copy_tail, true); 11261 } 11262 11263 // inflate 8 chars per iter 11264 bind(copy_8_loop); 11265 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11266 movdqu(Address(dst, len, Address::times_2), tmp1); 11267 addptr(len, 8); 11268 jcc(Assembler::notZero, copy_8_loop); 11269 11270 bind(copy_tail); 11271 movl(len, tmp2); 11272 11273 cmpl(len, 4); 11274 jccb(Assembler::less, copy_bytes); 11275 11276 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11277 pmovzxbw(tmp1, tmp1); 11278 movq(Address(dst, 0), tmp1); 11279 subptr(len, 4); 11280 addptr(src, 4); 11281 addptr(dst, 8); 11282 11283 bind(copy_bytes); 11284 } 11285 testl(len, len); 11286 jccb(Assembler::zero, done); 11287 lea(src, Address(src, len, Address::times_1)); 11288 lea(dst, Address(dst, len, Address::times_2)); 11289 negptr(len); 11290 11291 // inflate 1 char per iter 11292 bind(copy_chars_loop); 11293 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11294 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11295 increment(len); 11296 jcc(Assembler::notZero, copy_chars_loop); 11297 11298 bind(done); 11299 } 11300 11301 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11302 switch (cond) { 11303 // Note some conditions are synonyms for others 11304 case Assembler::zero: return Assembler::notZero; 11305 case Assembler::notZero: return Assembler::zero; 11306 case Assembler::less: return Assembler::greaterEqual; 11307 case Assembler::lessEqual: return Assembler::greater; 11308 case Assembler::greater: return Assembler::lessEqual; 11309 case Assembler::greaterEqual: return Assembler::less; 11310 case Assembler::below: return Assembler::aboveEqual; 11311 case Assembler::belowEqual: return Assembler::above; 11312 case Assembler::above: return Assembler::belowEqual; 11313 case Assembler::aboveEqual: return Assembler::below; 11314 case Assembler::overflow: return Assembler::noOverflow; 11315 case Assembler::noOverflow: return Assembler::overflow; 11316 case Assembler::negative: return Assembler::positive; 11317 case Assembler::positive: return Assembler::negative; 11318 case Assembler::parity: return Assembler::noParity; 11319 case Assembler::noParity: return Assembler::parity; 11320 } 11321 ShouldNotReachHere(); return Assembler::overflow; 11322 } 11323 11324 SkipIfEqual::SkipIfEqual( 11325 MacroAssembler* masm, const bool* flag_addr, bool value) { 11326 _masm = masm; 11327 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11328 _masm->jcc(Assembler::equal, _label); 11329 } 11330 11331 SkipIfEqual::~SkipIfEqual() { 11332 _masm->bind(_label); 11333 } 11334 11335 // 32-bit Windows has its own fast-path implementation 11336 // of get_thread 11337 #if !defined(WIN32) || defined(_LP64) 11338 11339 // This is simply a call to Thread::current() 11340 void MacroAssembler::get_thread(Register thread) { 11341 if (thread != rax) { 11342 push(rax); 11343 } 11344 LP64_ONLY(push(rdi);) 11345 LP64_ONLY(push(rsi);) 11346 push(rdx); 11347 push(rcx); 11348 #ifdef _LP64 11349 push(r8); 11350 push(r9); 11351 push(r10); 11352 push(r11); 11353 #endif 11354 11355 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11356 11357 #ifdef _LP64 11358 pop(r11); 11359 pop(r10); 11360 pop(r9); 11361 pop(r8); 11362 #endif 11363 pop(rcx); 11364 pop(rdx); 11365 LP64_ONLY(pop(rsi);) 11366 LP64_ONLY(pop(rdi);) 11367 if (thread != rax) { 11368 mov(thread, rax); 11369 pop(rax); 11370 } 11371 } 11372 11373 #endif