1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 attributes.set_rex_vex_w_reverted();
1244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1245 emit_int8(0x58);
1246 emit_int8((unsigned char)(0xC0 | encode));
1247 }
1248
1249 void Assembler::addsd(XMMRegister dst, Address src) {
1250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1251 InstructionMark im(this);
1252 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1253 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1254 attributes.set_rex_vex_w_reverted();
1255 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1256 emit_int8(0x58);
1257 emit_operand(dst, src);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1264 emit_int8(0x58);
1265 emit_int8((unsigned char)(0xC0 | encode));
1266 }
1267
1268 void Assembler::addss(XMMRegister dst, Address src) {
1269 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1270 InstructionMark im(this);
1271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1272 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1273 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1274 emit_int8(0x58);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, Address src) {
1279 assert(VM_Version::supports_aes(), "");
1280 InstructionMark im(this);
1281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1282 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1283 emit_int8((unsigned char)0xDE);
1284 emit_operand(dst, src);
1285 }
1286
1287 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1288 assert(VM_Version::supports_aes(), "");
1289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1291 emit_int8((unsigned char)0xDE);
1292 emit_int8(0xC0 | encode);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1296 assert(VM_Version::supports_aes(), "");
1297 InstructionMark im(this);
1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1300 emit_int8((unsigned char)0xDF);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1308 emit_int8((unsigned char)0xDF);
1309 emit_int8((unsigned char)(0xC0 | encode));
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDC);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDC);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, Address src) {
1330 assert(VM_Version::supports_aes(), "");
1331 InstructionMark im(this);
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDD);
1335 emit_operand(dst, src);
1336 }
1337
1338 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1342 emit_int8((unsigned char)0xDD);
1343 emit_int8((unsigned char)(0xC0 | encode));
1344 }
1345
1346 void Assembler::andl(Address dst, int32_t imm32) {
1347 InstructionMark im(this);
1348 prefix(dst);
1349 emit_int8((unsigned char)0x81);
1350 emit_operand(rsp, dst, 4);
1351 emit_int32(imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, int32_t imm32) {
1355 prefix(dst);
1356 emit_arith(0x81, 0xE0, dst, imm32);
1357 }
1358
1359 void Assembler::andl(Register dst, Address src) {
1360 InstructionMark im(this);
1361 prefix(src, dst);
1362 emit_int8(0x23);
1363 emit_operand(dst, src);
1364 }
1365
1366 void Assembler::andl(Register dst, Register src) {
1367 (void) prefix_and_encode(dst->encoding(), src->encoding());
1368 emit_arith(0x23, 0xC0, dst, src);
1369 }
1370
1371 void Assembler::andnl(Register dst, Register src1, Register src2) {
1372 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1374 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1375 emit_int8((unsigned char)0xF2);
1376 emit_int8((unsigned char)(0xC0 | encode));
1377 }
1378
1379 void Assembler::andnl(Register dst, Register src1, Address src2) {
1380 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1381 InstructionMark im(this);
1382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1383 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1384 emit_int8((unsigned char)0xF2);
1385 emit_operand(dst, src2);
1386 }
1387
1388 void Assembler::bsfl(Register dst, Register src) {
1389 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1390 emit_int8(0x0F);
1391 emit_int8((unsigned char)0xBC);
1392 emit_int8((unsigned char)(0xC0 | encode));
1393 }
1394
1395 void Assembler::bsrl(Register dst, Register src) {
1396 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1397 emit_int8(0x0F);
1398 emit_int8((unsigned char)0xBD);
1399 emit_int8((unsigned char)(0xC0 | encode));
1400 }
1401
1402 void Assembler::bswapl(Register reg) { // bswap
1403 int encode = prefix_and_encode(reg->encoding());
1404 emit_int8(0x0F);
1405 emit_int8((unsigned char)(0xC8 | encode));
1406 }
1407
1408 void Assembler::blsil(Register dst, Register src) {
1409 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1410 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1411 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1412 emit_int8((unsigned char)0xF3);
1413 emit_int8((unsigned char)(0xC0 | encode));
1414 }
1415
1416 void Assembler::blsil(Register dst, Address src) {
1417 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1418 InstructionMark im(this);
1419 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1420 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1421 emit_int8((unsigned char)0xF3);
1422 emit_operand(rbx, src);
1423 }
1424
1425 void Assembler::blsmskl(Register dst, Register src) {
1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1428 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1429 emit_int8((unsigned char)0xF3);
1430 emit_int8((unsigned char)(0xC0 | encode));
1431 }
1432
1433 void Assembler::blsmskl(Register dst, Address src) {
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 InstructionMark im(this);
1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1437 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rdx, src);
1440 }
1441
1442 void Assembler::blsrl(Register dst, Register src) {
1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1445 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1446 emit_int8((unsigned char)0xF3);
1447 emit_int8((unsigned char)(0xC0 | encode));
1448 }
1449
1450 void Assembler::blsrl(Register dst, Address src) {
1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1452 InstructionMark im(this);
1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1454 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1455 emit_int8((unsigned char)0xF3);
1456 emit_operand(rcx, src);
1457 }
1458
1459 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1460 // suspect disp32 is always good
1461 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1462
1463 if (L.is_bound()) {
1464 const int long_size = 5;
1465 int offs = (int)( target(L) - pc() );
1466 assert(offs <= 0, "assembler error");
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 emit_int8((unsigned char)0xE8);
1470 emit_data(offs - long_size, rtype, operand);
1471 } else {
1472 InstructionMark im(this);
1473 // 1110 1000 #32-bit disp
1474 L.add_patch_at(code(), locator());
1475
1476 emit_int8((unsigned char)0xE8);
1477 emit_data(int(0), rtype, operand);
1478 }
1479 }
1480
1481 void Assembler::call(Register dst) {
1482 int encode = prefix_and_encode(dst->encoding());
1483 emit_int8((unsigned char)0xFF);
1484 emit_int8((unsigned char)(0xD0 | encode));
1485 }
1486
1487
1488 void Assembler::call(Address adr) {
1489 InstructionMark im(this);
1490 prefix(adr);
1491 emit_int8((unsigned char)0xFF);
1492 emit_operand(rdx, adr);
1493 }
1494
1495 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1496 assert(entry != NULL, "call most probably wrong");
1497 InstructionMark im(this);
1498 emit_int8((unsigned char)0xE8);
1499 intptr_t disp = entry - (pc() + sizeof(int32_t));
1500 assert(is_simm32(disp), "must be 32bit offset (call2)");
1501 // Technically, should use call32_operand, but this format is
1502 // implied by the fact that we're emitting a call instruction.
1503
1504 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1505 emit_data((int) disp, rspec, operand);
1506 }
1507
1508 void Assembler::cdql() {
1509 emit_int8((unsigned char)0x99);
1510 }
1511
1512 void Assembler::cld() {
1513 emit_int8((unsigned char)0xFC);
1514 }
1515
1516 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1517 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1518 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1519 emit_int8(0x0F);
1520 emit_int8(0x40 | cc);
1521 emit_int8((unsigned char)(0xC0 | encode));
1522 }
1523
1524
1525 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1526 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1527 prefix(src, dst);
1528 emit_int8(0x0F);
1529 emit_int8(0x40 | cc);
1530 emit_operand(dst, src);
1531 }
1532
1533 void Assembler::cmpb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_int8((unsigned char)0x80);
1537 emit_operand(rdi, dst, 1);
1538 emit_int8(imm8);
1539 }
1540
1541 void Assembler::cmpl(Address dst, int32_t imm32) {
1542 InstructionMark im(this);
1543 prefix(dst);
1544 emit_int8((unsigned char)0x81);
1545 emit_operand(rdi, dst, 4);
1546 emit_int32(imm32);
1547 }
1548
1549 void Assembler::cmpl(Register dst, int32_t imm32) {
1550 prefix(dst);
1551 emit_arith(0x81, 0xF8, dst, imm32);
1552 }
1553
1554 void Assembler::cmpl(Register dst, Register src) {
1555 (void) prefix_and_encode(dst->encoding(), src->encoding());
1556 emit_arith(0x3B, 0xC0, dst, src);
1557 }
1558
1559 void Assembler::cmpl(Register dst, Address src) {
1560 InstructionMark im(this);
1561 prefix(src, dst);
1562 emit_int8((unsigned char)0x3B);
1563 emit_operand(dst, src);
1564 }
1565
1566 void Assembler::cmpw(Address dst, int imm16) {
1567 InstructionMark im(this);
1568 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1569 emit_int8(0x66);
1570 emit_int8((unsigned char)0x81);
1571 emit_operand(rdi, dst, 2);
1572 emit_int16(imm16);
1573 }
1574
1575 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1576 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1577 // The ZF is set if the compared values were equal, and cleared otherwise.
1578 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1579 InstructionMark im(this);
1580 prefix(adr, reg);
1581 emit_int8(0x0F);
1582 emit_int8((unsigned char)0xB1);
1583 emit_operand(reg, adr);
1584 }
1585
1586 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1587 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1588 // The ZF is set if the compared values were equal, and cleared otherwise.
1589 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1590 InstructionMark im(this);
1591 prefix(adr, reg, true);
1592 emit_int8(0x0F);
1593 emit_int8((unsigned char)0xB0);
1594 emit_operand(reg, adr);
1595 }
1596
1597 void Assembler::comisd(XMMRegister dst, Address src) {
1598 // NOTE: dbx seems to decode this as comiss even though the
1599 // 0x66 is there. Strangly ucomisd comes out correct
1600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1601 InstructionMark im(this);
1602 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1604 attributes.set_rex_vex_w_reverted();
1605 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1606 emit_int8(0x2F);
1607 emit_operand(dst, src);
1608 }
1609
1610 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1613 attributes.set_rex_vex_w_reverted();
1614 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1615 emit_int8(0x2F);
1616 emit_int8((unsigned char)(0xC0 | encode));
1617 }
1618
1619 void Assembler::comiss(XMMRegister dst, Address src) {
1620 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1621 InstructionMark im(this);
1622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1623 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1624 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1625 emit_int8(0x2F);
1626 emit_operand(dst, src);
1627 }
1628
1629 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1632 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1633 emit_int8(0x2F);
1634 emit_int8((unsigned char)(0xC0 | encode));
1635 }
1636
1637 void Assembler::cpuid() {
1638 emit_int8(0x0F);
1639 emit_int8((unsigned char)0xA2);
1640 }
1641
1642 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1643 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1644 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1645 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1646 //
1647 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1648 //
1649 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1650 //
1651 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1652 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1653 assert(VM_Version::supports_sse4_2(), "");
1654 int8_t w = 0x01;
1655 Prefix p = Prefix_EMPTY;
1656
1657 emit_int8((int8_t)0xF2);
1658 switch (sizeInBytes) {
1659 case 1:
1660 w = 0;
1661 break;
1662 case 2:
1663 case 4:
1664 break;
1665 LP64_ONLY(case 8:)
1666 // This instruction is not valid in 32 bits
1667 // Note:
1668 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1669 //
1670 // Page B - 72 Vol. 2C says
1671 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1672 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1673 // F0!!!
1674 // while 3 - 208 Vol. 2A
1675 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1676 //
1677 // the 0 on a last bit is reserved for a different flavor of this instruction :
1678 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1679 p = REX_W;
1680 break;
1681 default:
1682 assert(0, "Unsupported value for a sizeInBytes argument");
1683 break;
1684 }
1685 LP64_ONLY(prefix(crc, v, p);)
1686 emit_int8((int8_t)0x0F);
1687 emit_int8(0x38);
1688 emit_int8((int8_t)(0xF0 | w));
1689 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1690 }
1691
1692 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1693 assert(VM_Version::supports_sse4_2(), "");
1694 InstructionMark im(this);
1695 int8_t w = 0x01;
1696 Prefix p = Prefix_EMPTY;
1697
1698 emit_int8((int8_t)0xF2);
1699 switch (sizeInBytes) {
1700 case 1:
1701 w = 0;
1702 break;
1703 case 2:
1704 case 4:
1705 break;
1706 LP64_ONLY(case 8:)
1707 // This instruction is not valid in 32 bits
1708 p = REX_W;
1709 break;
1710 default:
1711 assert(0, "Unsupported value for a sizeInBytes argument");
1712 break;
1713 }
1714 LP64_ONLY(prefix(crc, adr, p);)
1715 emit_int8((int8_t)0x0F);
1716 emit_int8(0x38);
1717 emit_int8((int8_t)(0xF0 | w));
1718 emit_operand(crc, adr);
1719 }
1720
1721 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1724 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1725 emit_int8((unsigned char)0xE6);
1726 emit_int8((unsigned char)(0xC0 | encode));
1727 }
1728
1729 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1731 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1732 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1733 emit_int8(0x5B);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1740 attributes.set_rex_vex_w_reverted();
1741 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1742 emit_int8(0x5A);
1743 emit_int8((unsigned char)(0xC0 | encode));
1744 }
1745
1746 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 InstructionMark im(this);
1749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1751 attributes.set_rex_vex_w_reverted();
1752 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x5A);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1761 emit_int8(0x2A);
1762 emit_int8((unsigned char)(0xC0 | encode));
1763 }
1764
1765 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 InstructionMark im(this);
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1770 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_operand(dst, src);
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1779 emit_int8(0x2A);
1780 emit_int8((unsigned char)(0xC0 | encode));
1781 }
1782
1783 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1784 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1785 InstructionMark im(this);
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1788 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_operand(dst, src);
1791 }
1792
1793 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x2A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_int8((unsigned char)(0xC0 | encode));
1807 }
1808
1809 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionMark im(this);
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1813 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1814 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x5A);
1816 emit_operand(dst, src);
1817 }
1818
1819
1820 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2C);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1839 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1840 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1841 emit_int8((unsigned char)0xE6);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::decl(Address dst) {
1846 // Don't use it directly. Use MacroAssembler::decrement() instead.
1847 InstructionMark im(this);
1848 prefix(dst);
1849 emit_int8((unsigned char)0xFF);
1850 emit_operand(rcx, dst);
1851 }
1852
1853 void Assembler::divsd(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1858 attributes.set_rex_vex_w_reverted();
1859 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 attributes.set_rex_vex_w_reverted();
1868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1869 emit_int8(0x5E);
1870 emit_int8((unsigned char)(0xC0 | encode));
1871 }
1872
1873 void Assembler::divss(XMMRegister dst, Address src) {
1874 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1875 InstructionMark im(this);
1876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1878 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879 emit_int8(0x5E);
1880 emit_operand(dst, src);
1881 }
1882
1883 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1884 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1886 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1887 emit_int8(0x5E);
1888 emit_int8((unsigned char)(0xC0 | encode));
1889 }
1890
1891 void Assembler::emms() {
1892 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1893 emit_int8(0x0F);
1894 emit_int8(0x77);
1895 }
1896
1897 void Assembler::hlt() {
1898 emit_int8((unsigned char)0xF4);
1899 }
1900
1901 void Assembler::idivl(Register src) {
1902 int encode = prefix_and_encode(src->encoding());
1903 emit_int8((unsigned char)0xF7);
1904 emit_int8((unsigned char)(0xF8 | encode));
1905 }
1906
1907 void Assembler::divl(Register src) { // Unsigned
1908 int encode = prefix_and_encode(src->encoding());
1909 emit_int8((unsigned char)0xF7);
1910 emit_int8((unsigned char)(0xF0 | encode));
1911 }
1912
1913 void Assembler::imull(Register src) {
1914 int encode = prefix_and_encode(src->encoding());
1915 emit_int8((unsigned char)0xF7);
1916 emit_int8((unsigned char)(0xE8 | encode));
1917 }
1918
1919 void Assembler::imull(Register dst, Register src) {
1920 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921 emit_int8(0x0F);
1922 emit_int8((unsigned char)0xAF);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926
1927 void Assembler::imull(Register dst, Register src, int value) {
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 if (is8bit(value)) {
1930 emit_int8(0x6B);
1931 emit_int8((unsigned char)(0xC0 | encode));
1932 emit_int8(value & 0xFF);
1933 } else {
1934 emit_int8(0x69);
1935 emit_int8((unsigned char)(0xC0 | encode));
1936 emit_int32(value);
1937 }
1938 }
1939
1940 void Assembler::imull(Register dst, Address src) {
1941 InstructionMark im(this);
1942 prefix(src, dst);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char) 0xAF);
1945 emit_operand(dst, src);
1946 }
1947
1948
1949 void Assembler::incl(Address dst) {
1950 // Don't use it directly. Use MacroAssembler::increment() instead.
1951 InstructionMark im(this);
1952 prefix(dst);
1953 emit_int8((unsigned char)0xFF);
1954 emit_operand(rax, dst);
1955 }
1956
1957 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1958 InstructionMark im(this);
1959 assert((0 <= cc) && (cc < 16), "illegal cc");
1960 if (L.is_bound()) {
1961 address dst = target(L);
1962 assert(dst != NULL, "jcc most probably wrong");
1963
1964 const int short_size = 2;
1965 const int long_size = 6;
1966 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1967 if (maybe_short && is8bit(offs - short_size)) {
1968 // 0111 tttn #8-bit disp
1969 emit_int8(0x70 | cc);
1970 emit_int8((offs - short_size) & 0xFF);
1971 } else {
1972 // 0000 1111 1000 tttn #32-bit disp
1973 assert(is_simm32(offs - long_size),
1974 "must be 32bit offset (call4)");
1975 emit_int8(0x0F);
1976 emit_int8((unsigned char)(0x80 | cc));
1977 emit_int32(offs - long_size);
1978 }
1979 } else {
1980 // Note: could eliminate cond. jumps to this jump if condition
1981 // is the same however, seems to be rather unlikely case.
1982 // Note: use jccb() if label to be bound is very close to get
1983 // an 8-bit displacement
1984 L.add_patch_at(code(), locator());
1985 emit_int8(0x0F);
1986 emit_int8((unsigned char)(0x80 | cc));
1987 emit_int32(0);
1988 }
1989 }
1990
1991 void Assembler::jccb(Condition cc, Label& L) {
1992 if (L.is_bound()) {
1993 const int short_size = 2;
1994 address entry = target(L);
1995 #ifdef ASSERT
1996 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1997 intptr_t delta = short_branch_delta();
1998 if (delta != 0) {
1999 dist += (dist < 0 ? (-delta) :delta);
2000 }
2001 assert(is8bit(dist), "Dispacement too large for a short jmp");
2002 #endif
2003 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2004 // 0111 tttn #8-bit disp
2005 emit_int8(0x70 | cc);
2006 emit_int8((offs - short_size) & 0xFF);
2007 } else {
2008 InstructionMark im(this);
2009 L.add_patch_at(code(), locator());
2010 emit_int8(0x70 | cc);
2011 emit_int8(0);
2012 }
2013 }
2014
2015 void Assembler::jmp(Address adr) {
2016 InstructionMark im(this);
2017 prefix(adr);
2018 emit_int8((unsigned char)0xFF);
2019 emit_operand(rsp, adr);
2020 }
2021
2022 void Assembler::jmp(Label& L, bool maybe_short) {
2023 if (L.is_bound()) {
2024 address entry = target(L);
2025 assert(entry != NULL, "jmp most probably wrong");
2026 InstructionMark im(this);
2027 const int short_size = 2;
2028 const int long_size = 5;
2029 intptr_t offs = entry - pc();
2030 if (maybe_short && is8bit(offs - short_size)) {
2031 emit_int8((unsigned char)0xEB);
2032 emit_int8((offs - short_size) & 0xFF);
2033 } else {
2034 emit_int8((unsigned char)0xE9);
2035 emit_int32(offs - long_size);
2036 }
2037 } else {
2038 // By default, forward jumps are always 32-bit displacements, since
2039 // we can't yet know where the label will be bound. If you're sure that
2040 // the forward jump will not run beyond 256 bytes, use jmpb to
2041 // force an 8-bit displacement.
2042 InstructionMark im(this);
2043 L.add_patch_at(code(), locator());
2044 emit_int8((unsigned char)0xE9);
2045 emit_int32(0);
2046 }
2047 }
2048
2049 void Assembler::jmp(Register entry) {
2050 int encode = prefix_and_encode(entry->encoding());
2051 emit_int8((unsigned char)0xFF);
2052 emit_int8((unsigned char)(0xE0 | encode));
2053 }
2054
2055 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2056 InstructionMark im(this);
2057 emit_int8((unsigned char)0xE9);
2058 assert(dest != NULL, "must have a target");
2059 intptr_t disp = dest - (pc() + sizeof(int32_t));
2060 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2061 emit_data(disp, rspec.reloc(), call32_operand);
2062 }
2063
2064 void Assembler::jmpb(Label& L) {
2065 if (L.is_bound()) {
2066 const int short_size = 2;
2067 address entry = target(L);
2068 assert(entry != NULL, "jmp most probably wrong");
2069 #ifdef ASSERT
2070 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2071 intptr_t delta = short_branch_delta();
2072 if (delta != 0) {
2073 dist += (dist < 0 ? (-delta) :delta);
2074 }
2075 assert(is8bit(dist), "Dispacement too large for a short jmp");
2076 #endif
2077 intptr_t offs = entry - pc();
2078 emit_int8((unsigned char)0xEB);
2079 emit_int8((offs - short_size) & 0xFF);
2080 } else {
2081 InstructionMark im(this);
2082 L.add_patch_at(code(), locator());
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8(0);
2085 }
2086 }
2087
2088 void Assembler::ldmxcsr( Address src) {
2089 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2090 InstructionMark im(this);
2091 prefix(src);
2092 emit_int8(0x0F);
2093 emit_int8((unsigned char)0xAE);
2094 emit_operand(as_Register(2), src);
2095 }
2096
2097 void Assembler::leal(Register dst, Address src) {
2098 InstructionMark im(this);
2099 #ifdef _LP64
2100 emit_int8(0x67); // addr32
2101 prefix(src, dst);
2102 #endif // LP64
2103 emit_int8((unsigned char)0x8D);
2104 emit_operand(dst, src);
2105 }
2106
2107 void Assembler::lfence() {
2108 emit_int8(0x0F);
2109 emit_int8((unsigned char)0xAE);
2110 emit_int8((unsigned char)0xE8);
2111 }
2112
2113 void Assembler::lock() {
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::lzcntl(Register dst, Register src) {
2118 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2119 emit_int8((unsigned char)0xF3);
2120 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2121 emit_int8(0x0F);
2122 emit_int8((unsigned char)0xBD);
2123 emit_int8((unsigned char)(0xC0 | encode));
2124 }
2125
2126 // Emit mfence instruction
2127 void Assembler::mfence() {
2128 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2129 emit_int8(0x0F);
2130 emit_int8((unsigned char)0xAE);
2131 emit_int8((unsigned char)0xF0);
2132 }
2133
2134 void Assembler::mov(Register dst, Register src) {
2135 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2136 }
2137
2138 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2140 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2141 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2142 attributes.set_rex_vex_w_reverted();
2143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2144 emit_int8(0x28);
2145 emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147
2148 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2151 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2152 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2153 emit_int8(0x28);
2154 emit_int8((unsigned char)(0xC0 | encode));
2155 }
2156
2157 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2158 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2160 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2161 emit_int8(0x16);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 void Assembler::movb(Register dst, Address src) {
2166 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2167 InstructionMark im(this);
2168 prefix(src, dst, true);
2169 emit_int8((unsigned char)0x8A);
2170 emit_operand(dst, src);
2171 }
2172
2173 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2174 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2175 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2176 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2177 attributes.set_rex_vex_w_reverted();
2178 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2179 emit_int8(0x12);
2180 emit_int8(0xC0 | encode);
2181 }
2182
2183 void Assembler::kmovbl(KRegister dst, Register src) {
2184 assert(VM_Version::supports_avx512dq(), "");
2185 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2186 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2187 emit_int8((unsigned char)0x92);
2188 emit_int8((unsigned char)(0xC0 | encode));
2189 }
2190
2191 void Assembler::kmovbl(Register dst, KRegister src) {
2192 assert(VM_Version::supports_avx512dq(), "");
2193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2194 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2195 emit_int8((unsigned char)0x93);
2196 emit_int8((unsigned char)(0xC0 | encode));
2197 }
2198
2199 void Assembler::kmovwl(KRegister dst, Register src) {
2200 assert(VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::kmovwl(Register dst, KRegister src) {
2208 assert(VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2211 emit_int8((unsigned char)0x93);
2212 emit_int8((unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::kmovwl(KRegister dst, Address src) {
2216 assert(VM_Version::supports_evex(), "");
2217 InstructionMark im(this);
2218 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2219 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2220 emit_int8((unsigned char)0x90);
2221 emit_operand((Register)dst, src);
2222 }
2223
2224 void Assembler::kmovdl(KRegister dst, Register src) {
2225 assert(VM_Version::supports_avx512bw(), "");
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x92);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::kmovdl(Register dst, KRegister src) {
2233 assert(VM_Version::supports_avx512bw(), "");
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2236 emit_int8((unsigned char)0x93);
2237 emit_int8((unsigned char)(0xC0 | encode));
2238 }
2239
2240 void Assembler::kmovql(KRegister dst, KRegister src) {
2241 assert(VM_Version::supports_avx512bw(), "");
2242 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2243 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int8((unsigned char)0x90);
2245 emit_int8((unsigned char)(0xC0 | encode));
2246 }
2247
2248 void Assembler::kmovql(KRegister dst, Address src) {
2249 assert(VM_Version::supports_avx512bw(), "");
2250 InstructionMark im(this);
2251 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2252 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2253 emit_int8((unsigned char)0x90);
2254 emit_operand((Register)dst, src);
2255 }
2256
2257 void Assembler::kmovql(Address dst, KRegister src) {
2258 assert(VM_Version::supports_avx512bw(), "");
2259 InstructionMark im(this);
2260 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2261 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2262 emit_int8((unsigned char)0x90);
2263 emit_operand((Register)src, dst);
2264 }
2265
2266 void Assembler::kmovql(KRegister dst, Register src) {
2267 assert(VM_Version::supports_avx512bw(), "");
2268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2269 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2270 emit_int8((unsigned char)0x92);
2271 emit_int8((unsigned char)(0xC0 | encode));
2272 }
2273
2274 void Assembler::kmovql(Register dst, KRegister src) {
2275 assert(VM_Version::supports_avx512bw(), "");
2276 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2277 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2278 emit_int8((unsigned char)0x93);
2279 emit_int8((unsigned char)(0xC0 | encode));
2280 }
2281
2282 void Assembler::knotwl(KRegister dst, KRegister src) {
2283 assert(VM_Version::supports_evex(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x44);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2292 assert(VM_Version::supports_avx512dq(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x98);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 // This instruction produces ZF or CF flags
2300 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2301 assert(VM_Version::supports_evex(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x98);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 // This instruction produces ZF or CF flags
2327 void Assembler::ktestql(KRegister src1, KRegister src2) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x99);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::ktestq(KRegister src1, KRegister src2) {
2336 assert(VM_Version::supports_avx512bw(), "");
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2338 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2339 emit_int8((unsigned char)0x99);
2340 emit_int8((unsigned char)(0xC0 | encode));
2341 }
2342
2343 void Assembler::ktestd(KRegister src1, KRegister src2) {
2344 assert(VM_Version::supports_avx512bw(), "");
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2346 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2347 emit_int8((unsigned char)0x99);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 void Assembler::movb(Address dst, int imm8) {
2352 InstructionMark im(this);
2353 prefix(dst);
2354 emit_int8((unsigned char)0xC6);
2355 emit_operand(rax, dst, 1);
2356 emit_int8(imm8);
2357 }
2358
2359
2360 void Assembler::movb(Address dst, Register src) {
2361 assert(src->has_byte_register(), "must have byte register");
2362 InstructionMark im(this);
2363 prefix(dst, src, true);
2364 emit_int8((unsigned char)0x88);
2365 emit_operand(src, dst);
2366 }
2367
2368 void Assembler::movdl(XMMRegister dst, Register src) {
2369 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2370 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2371 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2372 emit_int8(0x6E);
2373 emit_int8((unsigned char)(0xC0 | encode));
2374 }
2375
2376 void Assembler::movdl(Register dst, XMMRegister src) {
2377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2378 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2379 // swap src/dst to get correct prefix
2380 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2381 emit_int8(0x7E);
2382 emit_int8((unsigned char)(0xC0 | encode));
2383 }
2384
2385 void Assembler::movdl(XMMRegister dst, Address src) {
2386 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2387 InstructionMark im(this);
2388 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2389 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2390 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2391 emit_int8(0x6E);
2392 emit_operand(dst, src);
2393 }
2394
2395 void Assembler::movdl(Address dst, XMMRegister src) {
2396 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2397 InstructionMark im(this);
2398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2399 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2400 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2401 emit_int8(0x7E);
2402 emit_operand(src, dst);
2403 }
2404
2405 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2406 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2407 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2408 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2409 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2410 emit_int8(0x6F);
2411 emit_int8((unsigned char)(0xC0 | encode));
2412 }
2413
2414 void Assembler::movdqa(XMMRegister dst, Address src) {
2415 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2416 InstructionMark im(this);
2417 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2418 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2419 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2420 emit_int8(0x6F);
2421 emit_operand(dst, src);
2422 }
2423
2424 void Assembler::movdqu(XMMRegister dst, Address src) {
2425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2426 InstructionMark im(this);
2427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2428 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2429 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2430 emit_int8(0x6F);
2431 emit_operand(dst, src);
2432 }
2433
2434 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2437 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2438 emit_int8(0x6F);
2439 emit_int8((unsigned char)(0xC0 | encode));
2440 }
2441
2442 void Assembler::movdqu(Address dst, XMMRegister src) {
2443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2444 InstructionMark im(this);
2445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2446 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2447 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2448 emit_int8(0x7F);
2449 emit_operand(src, dst);
2450 }
2451
2452 // Move Unaligned 256bit Vector
2453 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2454 assert(UseAVX > 0, "");
2455 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2456 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2457 emit_int8(0x6F);
2458 emit_int8((unsigned char)(0xC0 | encode));
2459 }
2460
2461 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2462 assert(UseAVX > 0, "");
2463 InstructionMark im(this);
2464 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2465 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2466 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2467 emit_int8(0x6F);
2468 emit_operand(dst, src);
2469 }
2470
2471 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2472 assert(UseAVX > 0, "");
2473 InstructionMark im(this);
2474 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2475 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2476 // swap src<->dst for encoding
2477 assert(src != xnoreg, "sanity");
2478 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2479 emit_int8(0x7F);
2480 emit_operand(src, dst);
2481 }
2482
2483 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2484 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2485 assert(VM_Version::supports_evex(), "");
2486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2487 attributes.set_is_evex_instruction();
2488 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2489 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2490 emit_int8(0x6F);
2491 emit_int8((unsigned char)(0xC0 | encode));
2492 }
2493
2494 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2495 assert(VM_Version::supports_evex(), "");
2496 InstructionMark im(this);
2497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2498 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2499 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2500 attributes.set_is_evex_instruction();
2501 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2502 emit_int8(0x6F);
2503 emit_operand(dst, src);
2504 }
2505
2506 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2507 assert(VM_Version::supports_evex(), "");
2508 assert(src != xnoreg, "sanity");
2509 InstructionMark im(this);
2510 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2511 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2512 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2513 attributes.set_is_evex_instruction();
2514 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2515 emit_int8(0x7F);
2516 emit_operand(src, dst);
2517 }
2518
2519 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2520 assert(VM_Version::supports_avx512vlbw(), "");
2521 assert(is_vector_masking(), ""); // For stub code use only
2522 InstructionMark im(this);
2523 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2524 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2525 attributes.set_embedded_opmask_register_specifier(mask);
2526 attributes.set_is_evex_instruction();
2527 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2528 emit_int8(0x6F);
2529 emit_operand(dst, src);
2530 }
2531
2532 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2533 assert(VM_Version::supports_evex(), "");
2534 InstructionMark im(this);
2535 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2536 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2537 attributes.set_is_evex_instruction();
2538 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2539 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2540 emit_int8(0x6F);
2541 emit_operand(dst, src);
2542 }
2543
2544 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2545 assert(is_vector_masking(), "");
2546 assert(VM_Version::supports_avx512vlbw(), "");
2547 InstructionMark im(this);
2548 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2549 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2550 attributes.set_embedded_opmask_register_specifier(mask);
2551 attributes.set_is_evex_instruction();
2552 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2553 emit_int8(0x6F);
2554 emit_operand(dst, src);
2555 }
2556
2557 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2558 assert(VM_Version::supports_evex(), "");
2559 assert(src != xnoreg, "sanity");
2560 InstructionMark im(this);
2561 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2562 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2563 attributes.set_is_evex_instruction();
2564 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2565 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2566 emit_int8(0x7F);
2567 emit_operand(src, dst);
2568 }
2569
2570 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2571 assert(VM_Version::supports_avx512vlbw(), "");
2572 assert(src != xnoreg, "sanity");
2573 InstructionMark im(this);
2574 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2575 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2576 attributes.set_embedded_opmask_register_specifier(mask);
2577 attributes.set_is_evex_instruction();
2578 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2579 emit_int8(0x7F);
2580 emit_operand(src, dst);
2581 }
2582
2583 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2584 assert(VM_Version::supports_evex(), "");
2585 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2586 attributes.set_is_evex_instruction();
2587 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_int8((unsigned char)(0xC0 | encode));
2590 }
2591
2592 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2593 assert(VM_Version::supports_evex(), "");
2594 InstructionMark im(this);
2595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.set_is_evex_instruction();
2598 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2599 emit_int8(0x6F);
2600 emit_operand(dst, src);
2601 }
2602
2603 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2604 assert(VM_Version::supports_evex(), "");
2605 assert(src != xnoreg, "sanity");
2606 InstructionMark im(this);
2607 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2609 attributes.set_is_evex_instruction();
2610 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2611 emit_int8(0x7F);
2612 emit_operand(src, dst);
2613 }
2614
2615 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2616 assert(VM_Version::supports_evex(), "");
2617 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2618 attributes.set_is_evex_instruction();
2619 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2620 emit_int8(0x6F);
2621 emit_int8((unsigned char)(0xC0 | encode));
2622 }
2623
2624 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2625 assert(VM_Version::supports_evex(), "");
2626 InstructionMark im(this);
2627 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2628 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2629 attributes.set_is_evex_instruction();
2630 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2631 emit_int8(0x6F);
2632 emit_operand(dst, src);
2633 }
2634
2635 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2636 assert(VM_Version::supports_evex(), "");
2637 assert(src != xnoreg, "sanity");
2638 InstructionMark im(this);
2639 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2640 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2641 attributes.set_is_evex_instruction();
2642 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2643 emit_int8(0x7F);
2644 emit_operand(src, dst);
2645 }
2646
2647 // Uses zero extension on 64bit
2648
2649 void Assembler::movl(Register dst, int32_t imm32) {
2650 int encode = prefix_and_encode(dst->encoding());
2651 emit_int8((unsigned char)(0xB8 | encode));
2652 emit_int32(imm32);
2653 }
2654
2655 void Assembler::movl(Register dst, Register src) {
2656 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2657 emit_int8((unsigned char)0x8B);
2658 emit_int8((unsigned char)(0xC0 | encode));
2659 }
2660
2661 void Assembler::movl(Register dst, Address src) {
2662 InstructionMark im(this);
2663 prefix(src, dst);
2664 emit_int8((unsigned char)0x8B);
2665 emit_operand(dst, src);
2666 }
2667
2668 void Assembler::movl(Address dst, int32_t imm32) {
2669 InstructionMark im(this);
2670 prefix(dst);
2671 emit_int8((unsigned char)0xC7);
2672 emit_operand(rax, dst, 4);
2673 emit_int32(imm32);
2674 }
2675
2676 void Assembler::movl(Address dst, Register src) {
2677 InstructionMark im(this);
2678 prefix(dst, src);
2679 emit_int8((unsigned char)0x89);
2680 emit_operand(src, dst);
2681 }
2682
2683 // New cpus require to use movsd and movss to avoid partial register stall
2684 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2685 // The selection is done in MacroAssembler::movdbl() and movflt().
2686 void Assembler::movlpd(XMMRegister dst, Address src) {
2687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2688 InstructionMark im(this);
2689 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2690 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2691 attributes.set_rex_vex_w_reverted();
2692 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2693 emit_int8(0x12);
2694 emit_operand(dst, src);
2695 }
2696
2697 void Assembler::movq( MMXRegister dst, Address src ) {
2698 assert( VM_Version::supports_mmx(), "" );
2699 emit_int8(0x0F);
2700 emit_int8(0x6F);
2701 emit_operand(dst, src);
2702 }
2703
2704 void Assembler::movq( Address dst, MMXRegister src ) {
2705 assert( VM_Version::supports_mmx(), "" );
2706 emit_int8(0x0F);
2707 emit_int8(0x7F);
2708 // workaround gcc (3.2.1-7a) bug
2709 // In that version of gcc with only an emit_operand(MMX, Address)
2710 // gcc will tail jump and try and reverse the parameters completely
2711 // obliterating dst in the process. By having a version available
2712 // that doesn't need to swap the args at the tail jump the bug is
2713 // avoided.
2714 emit_operand(dst, src);
2715 }
2716
2717 void Assembler::movq(XMMRegister dst, Address src) {
2718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2719 InstructionMark im(this);
2720 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2721 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2722 attributes.set_rex_vex_w_reverted();
2723 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2724 emit_int8(0x7E);
2725 emit_operand(dst, src);
2726 }
2727
2728 void Assembler::movq(Address dst, XMMRegister src) {
2729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2730 InstructionMark im(this);
2731 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2732 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2733 attributes.set_rex_vex_w_reverted();
2734 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2735 emit_int8((unsigned char)0xD6);
2736 emit_operand(src, dst);
2737 }
2738
2739 void Assembler::movsbl(Register dst, Address src) { // movsxb
2740 InstructionMark im(this);
2741 prefix(src, dst);
2742 emit_int8(0x0F);
2743 emit_int8((unsigned char)0xBE);
2744 emit_operand(dst, src);
2745 }
2746
2747 void Assembler::movsbl(Register dst, Register src) { // movsxb
2748 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2749 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2750 emit_int8(0x0F);
2751 emit_int8((unsigned char)0xBE);
2752 emit_int8((unsigned char)(0xC0 | encode));
2753 }
2754
2755 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2757 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2758 attributes.set_rex_vex_w_reverted();
2759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2760 emit_int8(0x10);
2761 emit_int8((unsigned char)(0xC0 | encode));
2762 }
2763
2764 void Assembler::movsd(XMMRegister dst, Address src) {
2765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2766 InstructionMark im(this);
2767 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2768 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2769 attributes.set_rex_vex_w_reverted();
2770 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2771 emit_int8(0x10);
2772 emit_operand(dst, src);
2773 }
2774
2775 void Assembler::movsd(Address dst, XMMRegister src) {
2776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2777 InstructionMark im(this);
2778 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2779 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2780 attributes.set_rex_vex_w_reverted();
2781 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2782 emit_int8(0x11);
2783 emit_operand(src, dst);
2784 }
2785
2786 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2788 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2789 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2790 emit_int8(0x10);
2791 emit_int8((unsigned char)(0xC0 | encode));
2792 }
2793
2794 void Assembler::movss(XMMRegister dst, Address src) {
2795 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2796 InstructionMark im(this);
2797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2799 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2800 emit_int8(0x10);
2801 emit_operand(dst, src);
2802 }
2803
2804 void Assembler::movss(Address dst, XMMRegister src) {
2805 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2806 InstructionMark im(this);
2807 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2808 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2809 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2810 emit_int8(0x11);
2811 emit_operand(src, dst);
2812 }
2813
2814 void Assembler::movswl(Register dst, Address src) { // movsxw
2815 InstructionMark im(this);
2816 prefix(src, dst);
2817 emit_int8(0x0F);
2818 emit_int8((unsigned char)0xBF);
2819 emit_operand(dst, src);
2820 }
2821
2822 void Assembler::movswl(Register dst, Register src) { // movsxw
2823 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2824 emit_int8(0x0F);
2825 emit_int8((unsigned char)0xBF);
2826 emit_int8((unsigned char)(0xC0 | encode));
2827 }
2828
2829 void Assembler::movw(Address dst, int imm16) {
2830 InstructionMark im(this);
2831
2832 emit_int8(0x66); // switch to 16-bit mode
2833 prefix(dst);
2834 emit_int8((unsigned char)0xC7);
2835 emit_operand(rax, dst, 2);
2836 emit_int16(imm16);
2837 }
2838
2839 void Assembler::movw(Register dst, Address src) {
2840 InstructionMark im(this);
2841 emit_int8(0x66);
2842 prefix(src, dst);
2843 emit_int8((unsigned char)0x8B);
2844 emit_operand(dst, src);
2845 }
2846
2847 void Assembler::movw(Address dst, Register src) {
2848 InstructionMark im(this);
2849 emit_int8(0x66);
2850 prefix(dst, src);
2851 emit_int8((unsigned char)0x89);
2852 emit_operand(src, dst);
2853 }
2854
2855 void Assembler::movzbl(Register dst, Address src) { // movzxb
2856 InstructionMark im(this);
2857 prefix(src, dst);
2858 emit_int8(0x0F);
2859 emit_int8((unsigned char)0xB6);
2860 emit_operand(dst, src);
2861 }
2862
2863 void Assembler::movzbl(Register dst, Register src) { // movzxb
2864 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2865 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2866 emit_int8(0x0F);
2867 emit_int8((unsigned char)0xB6);
2868 emit_int8(0xC0 | encode);
2869 }
2870
2871 void Assembler::movzwl(Register dst, Address src) { // movzxw
2872 InstructionMark im(this);
2873 prefix(src, dst);
2874 emit_int8(0x0F);
2875 emit_int8((unsigned char)0xB7);
2876 emit_operand(dst, src);
2877 }
2878
2879 void Assembler::movzwl(Register dst, Register src) { // movzxw
2880 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2881 emit_int8(0x0F);
2882 emit_int8((unsigned char)0xB7);
2883 emit_int8(0xC0 | encode);
2884 }
2885
2886 void Assembler::mull(Address src) {
2887 InstructionMark im(this);
2888 prefix(src);
2889 emit_int8((unsigned char)0xF7);
2890 emit_operand(rsp, src);
2891 }
2892
2893 void Assembler::mull(Register src) {
2894 int encode = prefix_and_encode(src->encoding());
2895 emit_int8((unsigned char)0xF7);
2896 emit_int8((unsigned char)(0xE0 | encode));
2897 }
2898
2899 void Assembler::mulsd(XMMRegister dst, Address src) {
2900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2901 InstructionMark im(this);
2902 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2903 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2904 attributes.set_rex_vex_w_reverted();
2905 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2906 emit_int8(0x59);
2907 emit_operand(dst, src);
2908 }
2909
2910 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2911 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2912 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2913 attributes.set_rex_vex_w_reverted();
2914 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2915 emit_int8(0x59);
2916 emit_int8((unsigned char)(0xC0 | encode));
2917 }
2918
2919 void Assembler::mulss(XMMRegister dst, Address src) {
2920 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2921 InstructionMark im(this);
2922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2923 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2924 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2925 emit_int8(0x59);
2926 emit_operand(dst, src);
2927 }
2928
2929 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2930 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2931 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2932 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2933 emit_int8(0x59);
2934 emit_int8((unsigned char)(0xC0 | encode));
2935 }
2936
2937 void Assembler::negl(Register dst) {
2938 int encode = prefix_and_encode(dst->encoding());
2939 emit_int8((unsigned char)0xF7);
2940 emit_int8((unsigned char)(0xD8 | encode));
2941 }
2942
2943 void Assembler::nop(int i) {
2944 #ifdef ASSERT
2945 assert(i > 0, " ");
2946 // The fancy nops aren't currently recognized by debuggers making it a
2947 // pain to disassemble code while debugging. If asserts are on clearly
2948 // speed is not an issue so simply use the single byte traditional nop
2949 // to do alignment.
2950
2951 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2952 return;
2953
2954 #endif // ASSERT
2955
2956 if (UseAddressNop && VM_Version::is_intel()) {
2957 //
2958 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2959 // 1: 0x90
2960 // 2: 0x66 0x90
2961 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2962 // 4: 0x0F 0x1F 0x40 0x00
2963 // 5: 0x0F 0x1F 0x44 0x00 0x00
2964 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2965 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2966 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2967 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2968 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2969 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2970
2971 // The rest coding is Intel specific - don't use consecutive address nops
2972
2973 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2974 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2975 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2976 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2977
2978 while(i >= 15) {
2979 // For Intel don't generate consecutive addess nops (mix with regular nops)
2980 i -= 15;
2981 emit_int8(0x66); // size prefix
2982 emit_int8(0x66); // size prefix
2983 emit_int8(0x66); // size prefix
2984 addr_nop_8();
2985 emit_int8(0x66); // size prefix
2986 emit_int8(0x66); // size prefix
2987 emit_int8(0x66); // size prefix
2988 emit_int8((unsigned char)0x90);
2989 // nop
2990 }
2991 switch (i) {
2992 case 14:
2993 emit_int8(0x66); // size prefix
2994 case 13:
2995 emit_int8(0x66); // size prefix
2996 case 12:
2997 addr_nop_8();
2998 emit_int8(0x66); // size prefix
2999 emit_int8(0x66); // size prefix
3000 emit_int8(0x66); // size prefix
3001 emit_int8((unsigned char)0x90);
3002 // nop
3003 break;
3004 case 11:
3005 emit_int8(0x66); // size prefix
3006 case 10:
3007 emit_int8(0x66); // size prefix
3008 case 9:
3009 emit_int8(0x66); // size prefix
3010 case 8:
3011 addr_nop_8();
3012 break;
3013 case 7:
3014 addr_nop_7();
3015 break;
3016 case 6:
3017 emit_int8(0x66); // size prefix
3018 case 5:
3019 addr_nop_5();
3020 break;
3021 case 4:
3022 addr_nop_4();
3023 break;
3024 case 3:
3025 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3026 emit_int8(0x66); // size prefix
3027 case 2:
3028 emit_int8(0x66); // size prefix
3029 case 1:
3030 emit_int8((unsigned char)0x90);
3031 // nop
3032 break;
3033 default:
3034 assert(i == 0, " ");
3035 }
3036 return;
3037 }
3038 if (UseAddressNop && VM_Version::is_amd()) {
3039 //
3040 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3041 // 1: 0x90
3042 // 2: 0x66 0x90
3043 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3044 // 4: 0x0F 0x1F 0x40 0x00
3045 // 5: 0x0F 0x1F 0x44 0x00 0x00
3046 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3047 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3048 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3049 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3050 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3051 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3052
3053 // The rest coding is AMD specific - use consecutive address nops
3054
3055 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3056 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3057 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3058 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3059 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3060 // Size prefixes (0x66) are added for larger sizes
3061
3062 while(i >= 22) {
3063 i -= 11;
3064 emit_int8(0x66); // size prefix
3065 emit_int8(0x66); // size prefix
3066 emit_int8(0x66); // size prefix
3067 addr_nop_8();
3068 }
3069 // Generate first nop for size between 21-12
3070 switch (i) {
3071 case 21:
3072 i -= 1;
3073 emit_int8(0x66); // size prefix
3074 case 20:
3075 case 19:
3076 i -= 1;
3077 emit_int8(0x66); // size prefix
3078 case 18:
3079 case 17:
3080 i -= 1;
3081 emit_int8(0x66); // size prefix
3082 case 16:
3083 case 15:
3084 i -= 8;
3085 addr_nop_8();
3086 break;
3087 case 14:
3088 case 13:
3089 i -= 7;
3090 addr_nop_7();
3091 break;
3092 case 12:
3093 i -= 6;
3094 emit_int8(0x66); // size prefix
3095 addr_nop_5();
3096 break;
3097 default:
3098 assert(i < 12, " ");
3099 }
3100
3101 // Generate second nop for size between 11-1
3102 switch (i) {
3103 case 11:
3104 emit_int8(0x66); // size prefix
3105 case 10:
3106 emit_int8(0x66); // size prefix
3107 case 9:
3108 emit_int8(0x66); // size prefix
3109 case 8:
3110 addr_nop_8();
3111 break;
3112 case 7:
3113 addr_nop_7();
3114 break;
3115 case 6:
3116 emit_int8(0x66); // size prefix
3117 case 5:
3118 addr_nop_5();
3119 break;
3120 case 4:
3121 addr_nop_4();
3122 break;
3123 case 3:
3124 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3125 emit_int8(0x66); // size prefix
3126 case 2:
3127 emit_int8(0x66); // size prefix
3128 case 1:
3129 emit_int8((unsigned char)0x90);
3130 // nop
3131 break;
3132 default:
3133 assert(i == 0, " ");
3134 }
3135 return;
3136 }
3137
3138 // Using nops with size prefixes "0x66 0x90".
3139 // From AMD Optimization Guide:
3140 // 1: 0x90
3141 // 2: 0x66 0x90
3142 // 3: 0x66 0x66 0x90
3143 // 4: 0x66 0x66 0x66 0x90
3144 // 5: 0x66 0x66 0x90 0x66 0x90
3145 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3146 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3147 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3148 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3149 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3150 //
3151 while(i > 12) {
3152 i -= 4;
3153 emit_int8(0x66); // size prefix
3154 emit_int8(0x66);
3155 emit_int8(0x66);
3156 emit_int8((unsigned char)0x90);
3157 // nop
3158 }
3159 // 1 - 12 nops
3160 if(i > 8) {
3161 if(i > 9) {
3162 i -= 1;
3163 emit_int8(0x66);
3164 }
3165 i -= 3;
3166 emit_int8(0x66);
3167 emit_int8(0x66);
3168 emit_int8((unsigned char)0x90);
3169 }
3170 // 1 - 8 nops
3171 if(i > 4) {
3172 if(i > 6) {
3173 i -= 1;
3174 emit_int8(0x66);
3175 }
3176 i -= 3;
3177 emit_int8(0x66);
3178 emit_int8(0x66);
3179 emit_int8((unsigned char)0x90);
3180 }
3181 switch (i) {
3182 case 4:
3183 emit_int8(0x66);
3184 case 3:
3185 emit_int8(0x66);
3186 case 2:
3187 emit_int8(0x66);
3188 case 1:
3189 emit_int8((unsigned char)0x90);
3190 break;
3191 default:
3192 assert(i == 0, " ");
3193 }
3194 }
3195
3196 void Assembler::notl(Register dst) {
3197 int encode = prefix_and_encode(dst->encoding());
3198 emit_int8((unsigned char)0xF7);
3199 emit_int8((unsigned char)(0xD0 | encode));
3200 }
3201
3202 void Assembler::orl(Address dst, int32_t imm32) {
3203 InstructionMark im(this);
3204 prefix(dst);
3205 emit_arith_operand(0x81, rcx, dst, imm32);
3206 }
3207
3208 void Assembler::orl(Register dst, int32_t imm32) {
3209 prefix(dst);
3210 emit_arith(0x81, 0xC8, dst, imm32);
3211 }
3212
3213 void Assembler::orl(Register dst, Address src) {
3214 InstructionMark im(this);
3215 prefix(src, dst);
3216 emit_int8(0x0B);
3217 emit_operand(dst, src);
3218 }
3219
3220 void Assembler::orl(Register dst, Register src) {
3221 (void) prefix_and_encode(dst->encoding(), src->encoding());
3222 emit_arith(0x0B, 0xC0, dst, src);
3223 }
3224
3225 void Assembler::orl(Address dst, Register src) {
3226 InstructionMark im(this);
3227 prefix(dst, src);
3228 emit_int8(0x09);
3229 emit_operand(src, dst);
3230 }
3231
3232 void Assembler::packuswb(XMMRegister dst, Address src) {
3233 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3234 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3235 InstructionMark im(this);
3236 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3237 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3238 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3239 emit_int8(0x67);
3240 emit_operand(dst, src);
3241 }
3242
3243 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3245 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3246 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3247 emit_int8(0x67);
3248 emit_int8((unsigned char)(0xC0 | encode));
3249 }
3250
3251 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3252 assert(UseAVX > 0, "some form of AVX must be enabled");
3253 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3254 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3255 emit_int8(0x67);
3256 emit_int8((unsigned char)(0xC0 | encode));
3257 }
3258
3259 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3260 assert(VM_Version::supports_avx2(), "");
3261 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3262 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3263 emit_int8(0x00);
3264 emit_int8(0xC0 | encode);
3265 emit_int8(imm8);
3266 }
3267
3268 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3269 assert(VM_Version::supports_avx2(), "");
3270 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3272 emit_int8(0x46);
3273 emit_int8(0xC0 | encode);
3274 emit_int8(imm8);
3275 }
3276
3277
3278 void Assembler::pause() {
3279 emit_int8((unsigned char)0xF3);
3280 emit_int8((unsigned char)0x90);
3281 }
3282
3283 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3284 assert(VM_Version::supports_sse4_2(), "");
3285 InstructionMark im(this);
3286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3287 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3288 emit_int8(0x61);
3289 emit_operand(dst, src);
3290 emit_int8(imm8);
3291 }
3292
3293 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3294 assert(VM_Version::supports_sse4_2(), "");
3295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3296 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3297 emit_int8(0x61);
3298 emit_int8((unsigned char)(0xC0 | encode));
3299 emit_int8(imm8);
3300 }
3301
3302 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3303 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3304 assert(VM_Version::supports_sse2(), "");
3305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3306 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3307 emit_int8(0x74);
3308 emit_int8((unsigned char)(0xC0 | encode));
3309 }
3310
3311 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3312 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3313 assert(VM_Version::supports_avx(), "");
3314 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3315 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3316 emit_int8(0x74);
3317 emit_int8((unsigned char)(0xC0 | encode));
3318 }
3319
3320 // In this context, kdst is written the mask used to process the equal components
3321 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3322 assert(VM_Version::supports_avx512bw(), "");
3323 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3324 attributes.set_is_evex_instruction();
3325 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3326 emit_int8(0x74);
3327 emit_int8((unsigned char)(0xC0 | encode));
3328 }
3329
3330 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3331 assert(VM_Version::supports_avx512vlbw(), "");
3332 InstructionMark im(this);
3333 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3334 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3335 attributes.set_is_evex_instruction();
3336 int dst_enc = kdst->encoding();
3337 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3338 emit_int8(0x64);
3339 emit_operand(as_Register(dst_enc), src);
3340 }
3341
3342 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3343 assert(is_vector_masking(), "");
3344 assert(VM_Version::supports_avx512vlbw(), "");
3345 InstructionMark im(this);
3346 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3347 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3348 attributes.set_embedded_opmask_register_specifier(mask);
3349 attributes.set_is_evex_instruction();
3350 int dst_enc = kdst->encoding();
3351 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3352 emit_int8(0x64);
3353 emit_operand(as_Register(dst_enc), src);
3354 }
3355
3356 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3357 assert(VM_Version::supports_avx512vlbw(), "");
3358 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3359 attributes.set_is_evex_instruction();
3360 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3361 emit_int8(0x3E);
3362 emit_int8((unsigned char)(0xC0 | encode));
3363 emit_int8(vcc);
3364 }
3365
3366 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3367 assert(is_vector_masking(), "");
3368 assert(VM_Version::supports_avx512vlbw(), "");
3369 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3370 attributes.set_embedded_opmask_register_specifier(mask);
3371 attributes.set_is_evex_instruction();
3372 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3373 emit_int8(0x3E);
3374 emit_int8((unsigned char)(0xC0 | encode));
3375 emit_int8(vcc);
3376 }
3377
3378 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3379 assert(VM_Version::supports_avx512vlbw(), "");
3380 InstructionMark im(this);
3381 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3382 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3383 attributes.set_is_evex_instruction();
3384 int dst_enc = kdst->encoding();
3385 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3386 emit_int8(0x3E);
3387 emit_operand(as_Register(dst_enc), src);
3388 emit_int8(vcc);
3389 }
3390
3391 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3392 assert(VM_Version::supports_avx512bw(), "");
3393 InstructionMark im(this);
3394 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3395 attributes.set_is_evex_instruction();
3396 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3397 int dst_enc = kdst->encoding();
3398 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3399 emit_int8(0x74);
3400 emit_operand(as_Register(dst_enc), src);
3401 }
3402
3403 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3404 assert(VM_Version::supports_avx512vlbw(), "");
3405 assert(is_vector_masking(), ""); // For stub code use only
3406 InstructionMark im(this);
3407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3408 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3409 attributes.set_embedded_opmask_register_specifier(mask);
3410 attributes.set_is_evex_instruction();
3411 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3412 emit_int8(0x74);
3413 emit_operand(as_Register(kdst->encoding()), src);
3414 }
3415
3416 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3417 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3418 assert(VM_Version::supports_sse2(), "");
3419 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3420 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3421 emit_int8(0x75);
3422 emit_int8((unsigned char)(0xC0 | encode));
3423 }
3424
3425 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3426 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3427 assert(VM_Version::supports_avx(), "");
3428 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3429 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3430 emit_int8(0x75);
3431 emit_int8((unsigned char)(0xC0 | encode));
3432 }
3433
3434 // In this context, kdst is written the mask used to process the equal components
3435 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3436 assert(VM_Version::supports_avx512bw(), "");
3437 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3438 attributes.set_is_evex_instruction();
3439 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3440 emit_int8(0x75);
3441 emit_int8((unsigned char)(0xC0 | encode));
3442 }
3443
3444 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3445 assert(VM_Version::supports_avx512bw(), "");
3446 InstructionMark im(this);
3447 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3448 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3449 attributes.set_is_evex_instruction();
3450 int dst_enc = kdst->encoding();
3451 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3452 emit_int8(0x75);
3453 emit_operand(as_Register(dst_enc), src);
3454 }
3455
3456 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3457 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3458 assert(VM_Version::supports_sse2(), "");
3459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3460 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3461 emit_int8(0x76);
3462 emit_int8((unsigned char)(0xC0 | encode));
3463 }
3464
3465 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3466 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3467 assert(VM_Version::supports_avx(), "");
3468 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3469 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3470 emit_int8(0x76);
3471 emit_int8((unsigned char)(0xC0 | encode));
3472 }
3473
3474 // In this context, kdst is written the mask used to process the equal components
3475 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3476 assert(VM_Version::supports_evex(), "");
3477 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3478 attributes.set_is_evex_instruction();
3479 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3480 emit_int8(0x76);
3481 emit_int8((unsigned char)(0xC0 | encode));
3482 }
3483
3484 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3485 assert(VM_Version::supports_evex(), "");
3486 InstructionMark im(this);
3487 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3488 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3489 attributes.set_is_evex_instruction();
3490 int dst_enc = kdst->encoding();
3491 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3492 emit_int8(0x76);
3493 emit_operand(as_Register(dst_enc), src);
3494 }
3495
3496 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3497 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3498 assert(VM_Version::supports_sse4_1(), "");
3499 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3501 emit_int8(0x29);
3502 emit_int8((unsigned char)(0xC0 | encode));
3503 }
3504
3505 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3506 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3507 assert(VM_Version::supports_avx(), "");
3508 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3509 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3510 emit_int8(0x29);
3511 emit_int8((unsigned char)(0xC0 | encode));
3512 }
3513
3514 // In this context, kdst is written the mask used to process the equal components
3515 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3516 assert(VM_Version::supports_evex(), "");
3517 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3518 attributes.set_is_evex_instruction();
3519 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3520 emit_int8(0x29);
3521 emit_int8((unsigned char)(0xC0 | encode));
3522 }
3523
3524 // In this context, kdst is written the mask used to process the equal components
3525 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3526 assert(VM_Version::supports_evex(), "");
3527 InstructionMark im(this);
3528 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3529 attributes.set_is_evex_instruction();
3530 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3531 int dst_enc = kdst->encoding();
3532 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3533 emit_int8(0x29);
3534 emit_operand(as_Register(dst_enc), src);
3535 }
3536
3537 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3538 assert(VM_Version::supports_sse2(), "");
3539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3540 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3541 emit_int8((unsigned char)0xD7);
3542 emit_int8((unsigned char)(0xC0 | encode));
3543 }
3544
3545 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3546 assert(VM_Version::supports_avx2(), "");
3547 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3548 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3549 emit_int8((unsigned char)0xD7);
3550 emit_int8((unsigned char)(0xC0 | encode));
3551 }
3552
3553 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3554 assert(VM_Version::supports_sse4_1(), "");
3555 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3556 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3557 emit_int8(0x16);
3558 emit_int8((unsigned char)(0xC0 | encode));
3559 emit_int8(imm8);
3560 }
3561
3562 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3563 assert(VM_Version::supports_sse4_1(), "");
3564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3565 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3566 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3567 emit_int8(0x16);
3568 emit_operand(src, dst);
3569 emit_int8(imm8);
3570 }
3571
3572 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3573 assert(VM_Version::supports_sse4_1(), "");
3574 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3575 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3576 emit_int8(0x16);
3577 emit_int8((unsigned char)(0xC0 | encode));
3578 emit_int8(imm8);
3579 }
3580
3581 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3582 assert(VM_Version::supports_sse4_1(), "");
3583 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3584 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3585 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3586 emit_int8(0x16);
3587 emit_operand(src, dst);
3588 emit_int8(imm8);
3589 }
3590
3591 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3592 assert(VM_Version::supports_sse2(), "");
3593 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3594 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3595 emit_int8((unsigned char)0xC5);
3596 emit_int8((unsigned char)(0xC0 | encode));
3597 emit_int8(imm8);
3598 }
3599
3600 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3601 assert(VM_Version::supports_sse4_1(), "");
3602 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3604 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3605 emit_int8((unsigned char)0x15);
3606 emit_operand(src, dst);
3607 emit_int8(imm8);
3608 }
3609
3610 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3611 assert(VM_Version::supports_sse4_1(), "");
3612 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3613 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3614 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3615 emit_int8(0x14);
3616 emit_operand(src, dst);
3617 emit_int8(imm8);
3618 }
3619
3620 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3621 assert(VM_Version::supports_sse4_1(), "");
3622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3623 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3624 emit_int8(0x22);
3625 emit_int8((unsigned char)(0xC0 | encode));
3626 emit_int8(imm8);
3627 }
3628
3629 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3630 assert(VM_Version::supports_sse4_1(), "");
3631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3632 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3633 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3634 emit_int8(0x22);
3635 emit_operand(dst,src);
3636 emit_int8(imm8);
3637 }
3638
3639 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3640 assert(VM_Version::supports_sse4_1(), "");
3641 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3642 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3643 emit_int8(0x22);
3644 emit_int8((unsigned char)(0xC0 | encode));
3645 emit_int8(imm8);
3646 }
3647
3648 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3649 assert(VM_Version::supports_sse4_1(), "");
3650 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3651 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3652 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3653 emit_int8(0x22);
3654 emit_operand(dst, src);
3655 emit_int8(imm8);
3656 }
3657
3658 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3659 assert(VM_Version::supports_sse2(), "");
3660 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3661 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3662 emit_int8((unsigned char)0xC4);
3663 emit_int8((unsigned char)(0xC0 | encode));
3664 emit_int8(imm8);
3665 }
3666
3667 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3668 assert(VM_Version::supports_sse2(), "");
3669 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3670 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3671 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3672 emit_int8((unsigned char)0xC4);
3673 emit_operand(dst, src);
3674 emit_int8(imm8);
3675 }
3676
3677 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3678 assert(VM_Version::supports_sse4_1(), "");
3679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3680 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3681 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3682 emit_int8(0x20);
3683 emit_operand(dst, src);
3684 emit_int8(imm8);
3685 }
3686
3687 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3688 assert(VM_Version::supports_sse4_1(), "");
3689 InstructionMark im(this);
3690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3691 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3692 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3693 emit_int8(0x30);
3694 emit_operand(dst, src);
3695 }
3696
3697 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3698 assert(VM_Version::supports_sse4_1(), "");
3699 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3700 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3701 emit_int8(0x30);
3702 emit_int8((unsigned char)(0xC0 | encode));
3703 }
3704
3705 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3706 assert(VM_Version::supports_avx(), "");
3707 InstructionMark im(this);
3708 assert(dst != xnoreg, "sanity");
3709 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3710 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3711 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3712 emit_int8(0x30);
3713 emit_operand(dst, src);
3714 }
3715
3716 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3717 assert(is_vector_masking(), "");
3718 assert(VM_Version::supports_avx512vlbw(), "");
3719 assert(dst != xnoreg, "sanity");
3720 InstructionMark im(this);
3721 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3722 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3723 attributes.set_embedded_opmask_register_specifier(mask);
3724 attributes.set_is_evex_instruction();
3725 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3726 emit_int8(0x30);
3727 emit_operand(dst, src);
3728 }
3729
3730 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3731 assert(VM_Version::supports_avx512vlbw(), "");
3732 assert(src != xnoreg, "sanity");
3733 InstructionMark im(this);
3734 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3735 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3736 attributes.set_is_evex_instruction();
3737 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3738 emit_int8(0x30);
3739 emit_operand(src, dst);
3740 }
3741
3742 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3743 assert(is_vector_masking(), "");
3744 assert(VM_Version::supports_avx512vlbw(), "");
3745 assert(src != xnoreg, "sanity");
3746 InstructionMark im(this);
3747 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3748 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3749 attributes.set_embedded_opmask_register_specifier(mask);
3750 attributes.set_is_evex_instruction();
3751 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3752 emit_int8(0x30);
3753 emit_operand(src, dst);
3754 }
3755
3756 // generic
3757 void Assembler::pop(Register dst) {
3758 int encode = prefix_and_encode(dst->encoding());
3759 emit_int8(0x58 | encode);
3760 }
3761
3762 void Assembler::popcntl(Register dst, Address src) {
3763 assert(VM_Version::supports_popcnt(), "must support");
3764 InstructionMark im(this);
3765 emit_int8((unsigned char)0xF3);
3766 prefix(src, dst);
3767 emit_int8(0x0F);
3768 emit_int8((unsigned char)0xB8);
3769 emit_operand(dst, src);
3770 }
3771
3772 void Assembler::popcntl(Register dst, Register src) {
3773 assert(VM_Version::supports_popcnt(), "must support");
3774 emit_int8((unsigned char)0xF3);
3775 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3776 emit_int8(0x0F);
3777 emit_int8((unsigned char)0xB8);
3778 emit_int8((unsigned char)(0xC0 | encode));
3779 }
3780
3781 void Assembler::popf() {
3782 emit_int8((unsigned char)0x9D);
3783 }
3784
3785 #ifndef _LP64 // no 32bit push/pop on amd64
3786 void Assembler::popl(Address dst) {
3787 // NOTE: this will adjust stack by 8byte on 64bits
3788 InstructionMark im(this);
3789 prefix(dst);
3790 emit_int8((unsigned char)0x8F);
3791 emit_operand(rax, dst);
3792 }
3793 #endif
3794
3795 void Assembler::prefetch_prefix(Address src) {
3796 prefix(src);
3797 emit_int8(0x0F);
3798 }
3799
3800 void Assembler::prefetchnta(Address src) {
3801 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3802 InstructionMark im(this);
3803 prefetch_prefix(src);
3804 emit_int8(0x18);
3805 emit_operand(rax, src); // 0, src
3806 }
3807
3808 void Assembler::prefetchr(Address src) {
3809 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3810 InstructionMark im(this);
3811 prefetch_prefix(src);
3812 emit_int8(0x0D);
3813 emit_operand(rax, src); // 0, src
3814 }
3815
3816 void Assembler::prefetcht0(Address src) {
3817 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3818 InstructionMark im(this);
3819 prefetch_prefix(src);
3820 emit_int8(0x18);
3821 emit_operand(rcx, src); // 1, src
3822 }
3823
3824 void Assembler::prefetcht1(Address src) {
3825 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3826 InstructionMark im(this);
3827 prefetch_prefix(src);
3828 emit_int8(0x18);
3829 emit_operand(rdx, src); // 2, src
3830 }
3831
3832 void Assembler::prefetcht2(Address src) {
3833 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3834 InstructionMark im(this);
3835 prefetch_prefix(src);
3836 emit_int8(0x18);
3837 emit_operand(rbx, src); // 3, src
3838 }
3839
3840 void Assembler::prefetchw(Address src) {
3841 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3842 InstructionMark im(this);
3843 prefetch_prefix(src);
3844 emit_int8(0x0D);
3845 emit_operand(rcx, src); // 1, src
3846 }
3847
3848 void Assembler::prefix(Prefix p) {
3849 emit_int8(p);
3850 }
3851
3852 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3853 assert(VM_Version::supports_ssse3(), "");
3854 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3855 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3856 emit_int8(0x00);
3857 emit_int8((unsigned char)(0xC0 | encode));
3858 }
3859
3860 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3861 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3862 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3863 0, "");
3864 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3865 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3866 emit_int8(0x00);
3867 emit_int8((unsigned char)(0xC0 | encode));
3868 }
3869
3870 void Assembler::pshufb(XMMRegister dst, Address src) {
3871 assert(VM_Version::supports_ssse3(), "");
3872 InstructionMark im(this);
3873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3874 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3875 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3876 emit_int8(0x00);
3877 emit_operand(dst, src);
3878 }
3879
3880 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3881 assert(isByte(mode), "invalid value");
3882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3883 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3884 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3885 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3886 emit_int8(0x70);
3887 emit_int8((unsigned char)(0xC0 | encode));
3888 emit_int8(mode & 0xFF);
3889 }
3890
3891 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
3892 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3893 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3894 0, "");
3895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3896 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3897 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3898 emit_int8(0x70);
3899 emit_int8((unsigned char)(0xC0 | encode));
3900 emit_int8(mode & 0xFF);
3901 }
3902
3903 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3904 assert(isByte(mode), "invalid value");
3905 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3906 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3907 InstructionMark im(this);
3908 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3909 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3910 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3911 emit_int8(0x70);
3912 emit_operand(dst, src);
3913 emit_int8(mode & 0xFF);
3914 }
3915
3916 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3917 assert(isByte(mode), "invalid value");
3918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3919 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3920 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3921 emit_int8(0x70);
3922 emit_int8((unsigned char)(0xC0 | encode));
3923 emit_int8(mode & 0xFF);
3924 }
3925
3926 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3927 assert(isByte(mode), "invalid value");
3928 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3929 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3930 InstructionMark im(this);
3931 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3932 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3933 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3934 emit_int8(0x70);
3935 emit_operand(dst, src);
3936 emit_int8(mode & 0xFF);
3937 }
3938
3939 void Assembler::psrldq(XMMRegister dst, int shift) {
3940 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3941 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3943 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3944 emit_int8(0x73);
3945 emit_int8((unsigned char)(0xC0 | encode));
3946 emit_int8(shift);
3947 }
3948
3949 void Assembler::pslldq(XMMRegister dst, int shift) {
3950 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3951 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3952 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3953 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3954 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3955 emit_int8(0x73);
3956 emit_int8((unsigned char)(0xC0 | encode));
3957 emit_int8(shift);
3958 }
3959
3960 void Assembler::ptest(XMMRegister dst, Address src) {
3961 assert(VM_Version::supports_sse4_1(), "");
3962 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3963 InstructionMark im(this);
3964 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3965 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3966 emit_int8(0x17);
3967 emit_operand(dst, src);
3968 }
3969
3970 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3971 assert(VM_Version::supports_sse4_1(), "");
3972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3973 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3974 emit_int8(0x17);
3975 emit_int8((unsigned char)(0xC0 | encode));
3976 }
3977
3978 void Assembler::vptest(XMMRegister dst, Address src) {
3979 assert(VM_Version::supports_avx(), "");
3980 InstructionMark im(this);
3981 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3982 assert(dst != xnoreg, "sanity");
3983 // swap src<->dst for encoding
3984 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3985 emit_int8(0x17);
3986 emit_operand(dst, src);
3987 }
3988
3989 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3990 assert(VM_Version::supports_avx(), "");
3991 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3992 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3993 emit_int8(0x17);
3994 emit_int8((unsigned char)(0xC0 | encode));
3995 }
3996
3997 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3998 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3999 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4000 InstructionMark im(this);
4001 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4002 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4003 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4004 emit_int8(0x60);
4005 emit_operand(dst, src);
4006 }
4007
4008 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4009 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4010 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4011 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4012 emit_int8(0x60);
4013 emit_int8((unsigned char)(0xC0 | encode));
4014 }
4015
4016 void Assembler::punpckldq(XMMRegister dst, Address src) {
4017 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4018 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4019 InstructionMark im(this);
4020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4021 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4022 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4023 emit_int8(0x62);
4024 emit_operand(dst, src);
4025 }
4026
4027 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4028 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4029 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4031 emit_int8(0x62);
4032 emit_int8((unsigned char)(0xC0 | encode));
4033 }
4034
4035 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4036 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4037 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4038 attributes.set_rex_vex_w_reverted();
4039 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4040 emit_int8(0x6C);
4041 emit_int8((unsigned char)(0xC0 | encode));
4042 }
4043
4044 void Assembler::push(int32_t imm32) {
4045 // in 64bits we push 64bits onto the stack but only
4046 // take a 32bit immediate
4047 emit_int8(0x68);
4048 emit_int32(imm32);
4049 }
4050
4051 void Assembler::push(Register src) {
4052 int encode = prefix_and_encode(src->encoding());
4053
4054 emit_int8(0x50 | encode);
4055 }
4056
4057 void Assembler::pushf() {
4058 emit_int8((unsigned char)0x9C);
4059 }
4060
4061 #ifndef _LP64 // no 32bit push/pop on amd64
4062 void Assembler::pushl(Address src) {
4063 // Note this will push 64bit on 64bit
4064 InstructionMark im(this);
4065 prefix(src);
4066 emit_int8((unsigned char)0xFF);
4067 emit_operand(rsi, src);
4068 }
4069 #endif
4070
4071 void Assembler::rcll(Register dst, int imm8) {
4072 assert(isShiftCount(imm8), "illegal shift count");
4073 int encode = prefix_and_encode(dst->encoding());
4074 if (imm8 == 1) {
4075 emit_int8((unsigned char)0xD1);
4076 emit_int8((unsigned char)(0xD0 | encode));
4077 } else {
4078 emit_int8((unsigned char)0xC1);
4079 emit_int8((unsigned char)0xD0 | encode);
4080 emit_int8(imm8);
4081 }
4082 }
4083
4084 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4085 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4087 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4088 emit_int8(0x53);
4089 emit_int8((unsigned char)(0xC0 | encode));
4090 }
4091
4092 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4093 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4094 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4095 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4096 emit_int8(0x53);
4097 emit_int8((unsigned char)(0xC0 | encode));
4098 }
4099
4100 void Assembler::rdtsc() {
4101 emit_int8((unsigned char)0x0F);
4102 emit_int8((unsigned char)0x31);
4103 }
4104
4105 // copies data from [esi] to [edi] using rcx pointer sized words
4106 // generic
4107 void Assembler::rep_mov() {
4108 emit_int8((unsigned char)0xF3);
4109 // MOVSQ
4110 LP64_ONLY(prefix(REX_W));
4111 emit_int8((unsigned char)0xA5);
4112 }
4113
4114 // sets rcx bytes with rax, value at [edi]
4115 void Assembler::rep_stosb() {
4116 emit_int8((unsigned char)0xF3); // REP
4117 LP64_ONLY(prefix(REX_W));
4118 emit_int8((unsigned char)0xAA); // STOSB
4119 }
4120
4121 // sets rcx pointer sized words with rax, value at [edi]
4122 // generic
4123 void Assembler::rep_stos() {
4124 emit_int8((unsigned char)0xF3); // REP
4125 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4126 emit_int8((unsigned char)0xAB);
4127 }
4128
4129 // scans rcx pointer sized words at [edi] for occurance of rax,
4130 // generic
4131 void Assembler::repne_scan() { // repne_scan
4132 emit_int8((unsigned char)0xF2);
4133 // SCASQ
4134 LP64_ONLY(prefix(REX_W));
4135 emit_int8((unsigned char)0xAF);
4136 }
4137
4138 #ifdef _LP64
4139 // scans rcx 4 byte words at [edi] for occurance of rax,
4140 // generic
4141 void Assembler::repne_scanl() { // repne_scan
4142 emit_int8((unsigned char)0xF2);
4143 // SCASL
4144 emit_int8((unsigned char)0xAF);
4145 }
4146 #endif
4147
4148 void Assembler::ret(int imm16) {
4149 if (imm16 == 0) {
4150 emit_int8((unsigned char)0xC3);
4151 } else {
4152 emit_int8((unsigned char)0xC2);
4153 emit_int16(imm16);
4154 }
4155 }
4156
4157 void Assembler::sahf() {
4158 #ifdef _LP64
4159 // Not supported in 64bit mode
4160 ShouldNotReachHere();
4161 #endif
4162 emit_int8((unsigned char)0x9E);
4163 }
4164
4165 void Assembler::sarl(Register dst, int imm8) {
4166 int encode = prefix_and_encode(dst->encoding());
4167 assert(isShiftCount(imm8), "illegal shift count");
4168 if (imm8 == 1) {
4169 emit_int8((unsigned char)0xD1);
4170 emit_int8((unsigned char)(0xF8 | encode));
4171 } else {
4172 emit_int8((unsigned char)0xC1);
4173 emit_int8((unsigned char)(0xF8 | encode));
4174 emit_int8(imm8);
4175 }
4176 }
4177
4178 void Assembler::sarl(Register dst) {
4179 int encode = prefix_and_encode(dst->encoding());
4180 emit_int8((unsigned char)0xD3);
4181 emit_int8((unsigned char)(0xF8 | encode));
4182 }
4183
4184 void Assembler::sbbl(Address dst, int32_t imm32) {
4185 InstructionMark im(this);
4186 prefix(dst);
4187 emit_arith_operand(0x81, rbx, dst, imm32);
4188 }
4189
4190 void Assembler::sbbl(Register dst, int32_t imm32) {
4191 prefix(dst);
4192 emit_arith(0x81, 0xD8, dst, imm32);
4193 }
4194
4195
4196 void Assembler::sbbl(Register dst, Address src) {
4197 InstructionMark im(this);
4198 prefix(src, dst);
4199 emit_int8(0x1B);
4200 emit_operand(dst, src);
4201 }
4202
4203 void Assembler::sbbl(Register dst, Register src) {
4204 (void) prefix_and_encode(dst->encoding(), src->encoding());
4205 emit_arith(0x1B, 0xC0, dst, src);
4206 }
4207
4208 void Assembler::setb(Condition cc, Register dst) {
4209 assert(0 <= cc && cc < 16, "illegal cc");
4210 int encode = prefix_and_encode(dst->encoding(), true);
4211 emit_int8(0x0F);
4212 emit_int8((unsigned char)0x90 | cc);
4213 emit_int8((unsigned char)(0xC0 | encode));
4214 }
4215
4216 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4217 assert(VM_Version::supports_ssse3(), "");
4218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4219 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4220 emit_int8((unsigned char)0x0F);
4221 emit_int8((unsigned char)(0xC0 | encode));
4222 emit_int8(imm8);
4223 }
4224
4225 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4226 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4227 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4228 0, "");
4229 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4230 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4231 emit_int8((unsigned char)0x0F);
4232 emit_int8((unsigned char)(0xC0 | encode));
4233 emit_int8(imm8);
4234 }
4235
4236 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4237 assert(VM_Version::supports_sse4_1(), "");
4238 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4239 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4240 emit_int8((unsigned char)0x0E);
4241 emit_int8((unsigned char)(0xC0 | encode));
4242 emit_int8(imm8);
4243 }
4244
4245 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4246 assert(VM_Version::supports_sha(), "");
4247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4248 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4249 emit_int8((unsigned char)0xCC);
4250 emit_int8((unsigned char)(0xC0 | encode));
4251 emit_int8((unsigned char)imm8);
4252 }
4253
4254 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4255 assert(VM_Version::supports_sha(), "");
4256 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4257 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4258 emit_int8((unsigned char)0xC8);
4259 emit_int8((unsigned char)(0xC0 | encode));
4260 }
4261
4262 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4263 assert(VM_Version::supports_sha(), "");
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4266 emit_int8((unsigned char)0xC9);
4267 emit_int8((unsigned char)(0xC0 | encode));
4268 }
4269
4270 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4271 assert(VM_Version::supports_sha(), "");
4272 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4273 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4274 emit_int8((unsigned char)0xCA);
4275 emit_int8((unsigned char)(0xC0 | encode));
4276 }
4277
4278 // xmm0 is implicit additional source to this instruction.
4279 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4280 assert(VM_Version::supports_sha(), "");
4281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4282 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4283 emit_int8((unsigned char)0xCB);
4284 emit_int8((unsigned char)(0xC0 | encode));
4285 }
4286
4287 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4288 assert(VM_Version::supports_sha(), "");
4289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4290 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4291 emit_int8((unsigned char)0xCC);
4292 emit_int8((unsigned char)(0xC0 | encode));
4293 }
4294
4295 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4296 assert(VM_Version::supports_sha(), "");
4297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4298 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4299 emit_int8((unsigned char)0xCD);
4300 emit_int8((unsigned char)(0xC0 | encode));
4301 }
4302
4303
4304 void Assembler::shll(Register dst, int imm8) {
4305 assert(isShiftCount(imm8), "illegal shift count");
4306 int encode = prefix_and_encode(dst->encoding());
4307 if (imm8 == 1 ) {
4308 emit_int8((unsigned char)0xD1);
4309 emit_int8((unsigned char)(0xE0 | encode));
4310 } else {
4311 emit_int8((unsigned char)0xC1);
4312 emit_int8((unsigned char)(0xE0 | encode));
4313 emit_int8(imm8);
4314 }
4315 }
4316
4317 void Assembler::shll(Register dst) {
4318 int encode = prefix_and_encode(dst->encoding());
4319 emit_int8((unsigned char)0xD3);
4320 emit_int8((unsigned char)(0xE0 | encode));
4321 }
4322
4323 void Assembler::shrl(Register dst, int imm8) {
4324 assert(isShiftCount(imm8), "illegal shift count");
4325 int encode = prefix_and_encode(dst->encoding());
4326 emit_int8((unsigned char)0xC1);
4327 emit_int8((unsigned char)(0xE8 | encode));
4328 emit_int8(imm8);
4329 }
4330
4331 void Assembler::shrl(Register dst) {
4332 int encode = prefix_and_encode(dst->encoding());
4333 emit_int8((unsigned char)0xD3);
4334 emit_int8((unsigned char)(0xE8 | encode));
4335 }
4336
4337 // copies a single word from [esi] to [edi]
4338 void Assembler::smovl() {
4339 emit_int8((unsigned char)0xA5);
4340 }
4341
4342 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4344 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4345 attributes.set_rex_vex_w_reverted();
4346 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4347 emit_int8(0x51);
4348 emit_int8((unsigned char)(0xC0 | encode));
4349 }
4350
4351 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4353 InstructionMark im(this);
4354 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4355 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4356 attributes.set_rex_vex_w_reverted();
4357 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4358 emit_int8(0x51);
4359 emit_operand(dst, src);
4360 }
4361
4362 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4363 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4365 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4366 emit_int8(0x51);
4367 emit_int8((unsigned char)(0xC0 | encode));
4368 }
4369
4370 void Assembler::std() {
4371 emit_int8((unsigned char)0xFD);
4372 }
4373
4374 void Assembler::sqrtss(XMMRegister dst, Address src) {
4375 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4376 InstructionMark im(this);
4377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4378 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4379 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4380 emit_int8(0x51);
4381 emit_operand(dst, src);
4382 }
4383
4384 void Assembler::stmxcsr( Address dst) {
4385 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4386 InstructionMark im(this);
4387 prefix(dst);
4388 emit_int8(0x0F);
4389 emit_int8((unsigned char)0xAE);
4390 emit_operand(as_Register(3), dst);
4391 }
4392
4393 void Assembler::subl(Address dst, int32_t imm32) {
4394 InstructionMark im(this);
4395 prefix(dst);
4396 emit_arith_operand(0x81, rbp, dst, imm32);
4397 }
4398
4399 void Assembler::subl(Address dst, Register src) {
4400 InstructionMark im(this);
4401 prefix(dst, src);
4402 emit_int8(0x29);
4403 emit_operand(src, dst);
4404 }
4405
4406 void Assembler::subl(Register dst, int32_t imm32) {
4407 prefix(dst);
4408 emit_arith(0x81, 0xE8, dst, imm32);
4409 }
4410
4411 // Force generation of a 4 byte immediate value even if it fits into 8bit
4412 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4413 prefix(dst);
4414 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4415 }
4416
4417 void Assembler::subl(Register dst, Address src) {
4418 InstructionMark im(this);
4419 prefix(src, dst);
4420 emit_int8(0x2B);
4421 emit_operand(dst, src);
4422 }
4423
4424 void Assembler::subl(Register dst, Register src) {
4425 (void) prefix_and_encode(dst->encoding(), src->encoding());
4426 emit_arith(0x2B, 0xC0, dst, src);
4427 }
4428
4429 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4431 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4432 attributes.set_rex_vex_w_reverted();
4433 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4434 emit_int8(0x5C);
4435 emit_int8((unsigned char)(0xC0 | encode));
4436 }
4437
4438 void Assembler::subsd(XMMRegister dst, Address src) {
4439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4440 InstructionMark im(this);
4441 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4442 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4443 attributes.set_rex_vex_w_reverted();
4444 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4445 emit_int8(0x5C);
4446 emit_operand(dst, src);
4447 }
4448
4449 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4450 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4451 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4452 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4453 emit_int8(0x5C);
4454 emit_int8((unsigned char)(0xC0 | encode));
4455 }
4456
4457 void Assembler::subss(XMMRegister dst, Address src) {
4458 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4459 InstructionMark im(this);
4460 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4461 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4462 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4463 emit_int8(0x5C);
4464 emit_operand(dst, src);
4465 }
4466
4467 void Assembler::testb(Register dst, int imm8) {
4468 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4469 (void) prefix_and_encode(dst->encoding(), true);
4470 emit_arith_b(0xF6, 0xC0, dst, imm8);
4471 }
4472
4473 void Assembler::testb(Address dst, int imm8) {
4474 InstructionMark im(this);
4475 prefix(dst);
4476 emit_int8((unsigned char)0xF6);
4477 emit_operand(rax, dst, 1);
4478 emit_int8(imm8);
4479 }
4480
4481 void Assembler::testl(Register dst, int32_t imm32) {
4482 // not using emit_arith because test
4483 // doesn't support sign-extension of
4484 // 8bit operands
4485 int encode = dst->encoding();
4486 if (encode == 0) {
4487 emit_int8((unsigned char)0xA9);
4488 } else {
4489 encode = prefix_and_encode(encode);
4490 emit_int8((unsigned char)0xF7);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 }
4493 emit_int32(imm32);
4494 }
4495
4496 void Assembler::testl(Register dst, Register src) {
4497 (void) prefix_and_encode(dst->encoding(), src->encoding());
4498 emit_arith(0x85, 0xC0, dst, src);
4499 }
4500
4501 void Assembler::testl(Register dst, Address src) {
4502 InstructionMark im(this);
4503 prefix(src, dst);
4504 emit_int8((unsigned char)0x85);
4505 emit_operand(dst, src);
4506 }
4507
4508 void Assembler::tzcntl(Register dst, Register src) {
4509 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4510 emit_int8((unsigned char)0xF3);
4511 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4512 emit_int8(0x0F);
4513 emit_int8((unsigned char)0xBC);
4514 emit_int8((unsigned char)0xC0 | encode);
4515 }
4516
4517 void Assembler::tzcntq(Register dst, Register src) {
4518 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4519 emit_int8((unsigned char)0xF3);
4520 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4521 emit_int8(0x0F);
4522 emit_int8((unsigned char)0xBC);
4523 emit_int8((unsigned char)(0xC0 | encode));
4524 }
4525
4526 void Assembler::ucomisd(XMMRegister dst, Address src) {
4527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4528 InstructionMark im(this);
4529 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4530 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4531 attributes.set_rex_vex_w_reverted();
4532 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4533 emit_int8(0x2E);
4534 emit_operand(dst, src);
4535 }
4536
4537 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4539 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4540 attributes.set_rex_vex_w_reverted();
4541 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4542 emit_int8(0x2E);
4543 emit_int8((unsigned char)(0xC0 | encode));
4544 }
4545
4546 void Assembler::ucomiss(XMMRegister dst, Address src) {
4547 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4548 InstructionMark im(this);
4549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4550 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4551 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4552 emit_int8(0x2E);
4553 emit_operand(dst, src);
4554 }
4555
4556 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4557 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4558 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4559 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4560 emit_int8(0x2E);
4561 emit_int8((unsigned char)(0xC0 | encode));
4562 }
4563
4564 void Assembler::xabort(int8_t imm8) {
4565 emit_int8((unsigned char)0xC6);
4566 emit_int8((unsigned char)0xF8);
4567 emit_int8((unsigned char)(imm8 & 0xFF));
4568 }
4569
4570 void Assembler::xaddl(Address dst, Register src) {
4571 InstructionMark im(this);
4572 prefix(dst, src);
4573 emit_int8(0x0F);
4574 emit_int8((unsigned char)0xC1);
4575 emit_operand(src, dst);
4576 }
4577
4578 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4579 InstructionMark im(this);
4580 relocate(rtype);
4581 if (abort.is_bound()) {
4582 address entry = target(abort);
4583 assert(entry != NULL, "abort entry NULL");
4584 intptr_t offset = entry - pc();
4585 emit_int8((unsigned char)0xC7);
4586 emit_int8((unsigned char)0xF8);
4587 emit_int32(offset - 6); // 2 opcode + 4 address
4588 } else {
4589 abort.add_patch_at(code(), locator());
4590 emit_int8((unsigned char)0xC7);
4591 emit_int8((unsigned char)0xF8);
4592 emit_int32(0);
4593 }
4594 }
4595
4596 void Assembler::xchgl(Register dst, Address src) { // xchg
4597 InstructionMark im(this);
4598 prefix(src, dst);
4599 emit_int8((unsigned char)0x87);
4600 emit_operand(dst, src);
4601 }
4602
4603 void Assembler::xchgl(Register dst, Register src) {
4604 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4605 emit_int8((unsigned char)0x87);
4606 emit_int8((unsigned char)(0xC0 | encode));
4607 }
4608
4609 void Assembler::xend() {
4610 emit_int8((unsigned char)0x0F);
4611 emit_int8((unsigned char)0x01);
4612 emit_int8((unsigned char)0xD5);
4613 }
4614
4615 void Assembler::xgetbv() {
4616 emit_int8(0x0F);
4617 emit_int8(0x01);
4618 emit_int8((unsigned char)0xD0);
4619 }
4620
4621 void Assembler::xorl(Register dst, int32_t imm32) {
4622 prefix(dst);
4623 emit_arith(0x81, 0xF0, dst, imm32);
4624 }
4625
4626 void Assembler::xorl(Register dst, Address src) {
4627 InstructionMark im(this);
4628 prefix(src, dst);
4629 emit_int8(0x33);
4630 emit_operand(dst, src);
4631 }
4632
4633 void Assembler::xorl(Register dst, Register src) {
4634 (void) prefix_and_encode(dst->encoding(), src->encoding());
4635 emit_arith(0x33, 0xC0, dst, src);
4636 }
4637
4638 void Assembler::xorb(Register dst, Address src) {
4639 InstructionMark im(this);
4640 prefix(src, dst);
4641 emit_int8(0x32);
4642 emit_operand(dst, src);
4643 }
4644
4645 // AVX 3-operands scalar float-point arithmetic instructions
4646
4647 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4648 assert(VM_Version::supports_avx(), "");
4649 InstructionMark im(this);
4650 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4651 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4652 attributes.set_rex_vex_w_reverted();
4653 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4654 emit_int8(0x58);
4655 emit_operand(dst, src);
4656 }
4657
4658 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4659 assert(VM_Version::supports_avx(), "");
4660 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4661 attributes.set_rex_vex_w_reverted();
4662 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4663 emit_int8(0x58);
4664 emit_int8((unsigned char)(0xC0 | encode));
4665 }
4666
4667 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4668 assert(VM_Version::supports_avx(), "");
4669 InstructionMark im(this);
4670 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4671 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4672 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4673 emit_int8(0x58);
4674 emit_operand(dst, src);
4675 }
4676
4677 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4678 assert(VM_Version::supports_avx(), "");
4679 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4680 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4681 emit_int8(0x58);
4682 emit_int8((unsigned char)(0xC0 | encode));
4683 }
4684
4685 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4686 assert(VM_Version::supports_avx(), "");
4687 InstructionMark im(this);
4688 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4689 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4690 attributes.set_rex_vex_w_reverted();
4691 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4692 emit_int8(0x5E);
4693 emit_operand(dst, src);
4694 }
4695
4696 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4697 assert(VM_Version::supports_avx(), "");
4698 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4699 attributes.set_rex_vex_w_reverted();
4700 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4701 emit_int8(0x5E);
4702 emit_int8((unsigned char)(0xC0 | encode));
4703 }
4704
4705 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4706 assert(VM_Version::supports_avx(), "");
4707 InstructionMark im(this);
4708 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4709 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4710 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4711 emit_int8(0x5E);
4712 emit_operand(dst, src);
4713 }
4714
4715 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4716 assert(VM_Version::supports_avx(), "");
4717 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4718 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4719 emit_int8(0x5E);
4720 emit_int8((unsigned char)(0xC0 | encode));
4721 }
4722
4723 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4724 assert(VM_Version::supports_avx(), "");
4725 InstructionMark im(this);
4726 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4727 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4728 attributes.set_rex_vex_w_reverted();
4729 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4730 emit_int8(0x59);
4731 emit_operand(dst, src);
4732 }
4733
4734 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4735 assert(VM_Version::supports_avx(), "");
4736 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4737 attributes.set_rex_vex_w_reverted();
4738 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4739 emit_int8(0x59);
4740 emit_int8((unsigned char)(0xC0 | encode));
4741 }
4742
4743 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4744 assert(VM_Version::supports_avx(), "");
4745 InstructionMark im(this);
4746 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4747 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4748 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4749 emit_int8(0x59);
4750 emit_operand(dst, src);
4751 }
4752
4753 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4754 assert(VM_Version::supports_avx(), "");
4755 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4756 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4757 emit_int8(0x59);
4758 emit_int8((unsigned char)(0xC0 | encode));
4759 }
4760
4761 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4762 assert(VM_Version::supports_avx(), "");
4763 InstructionMark im(this);
4764 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4765 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4766 attributes.set_rex_vex_w_reverted();
4767 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4768 emit_int8(0x5C);
4769 emit_operand(dst, src);
4770 }
4771
4772 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4773 assert(VM_Version::supports_avx(), "");
4774 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4775 attributes.set_rex_vex_w_reverted();
4776 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4777 emit_int8(0x5C);
4778 emit_int8((unsigned char)(0xC0 | encode));
4779 }
4780
4781 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4782 assert(VM_Version::supports_avx(), "");
4783 InstructionMark im(this);
4784 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4786 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4787 emit_int8(0x5C);
4788 emit_operand(dst, src);
4789 }
4790
4791 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4792 assert(VM_Version::supports_avx(), "");
4793 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4794 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4795 emit_int8(0x5C);
4796 emit_int8((unsigned char)(0xC0 | encode));
4797 }
4798
4799 //====================VECTOR ARITHMETIC=====================================
4800
4801 // Float-point vector arithmetic
4802
4803 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4805 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4806 attributes.set_rex_vex_w_reverted();
4807 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4808 emit_int8(0x58);
4809 emit_int8((unsigned char)(0xC0 | encode));
4810 }
4811
4812 void Assembler::addpd(XMMRegister dst, Address src) {
4813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4814 InstructionMark im(this);
4815 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4816 attributes.set_rex_vex_w_reverted();
4817 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4818 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4819 emit_int8(0x58);
4820 emit_operand(dst, src);
4821 }
4822
4823
4824 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4825 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4826 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4827 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4828 emit_int8(0x58);
4829 emit_int8((unsigned char)(0xC0 | encode));
4830 }
4831
4832 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4833 assert(VM_Version::supports_avx(), "");
4834 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4835 attributes.set_rex_vex_w_reverted();
4836 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4837 emit_int8(0x58);
4838 emit_int8((unsigned char)(0xC0 | encode));
4839 }
4840
4841 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4842 assert(VM_Version::supports_avx(), "");
4843 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4844 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4845 emit_int8(0x58);
4846 emit_int8((unsigned char)(0xC0 | encode));
4847 }
4848
4849 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4850 assert(VM_Version::supports_avx(), "");
4851 InstructionMark im(this);
4852 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4853 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4854 attributes.set_rex_vex_w_reverted();
4855 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4856 emit_int8(0x58);
4857 emit_operand(dst, src);
4858 }
4859
4860 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4861 assert(VM_Version::supports_avx(), "");
4862 InstructionMark im(this);
4863 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4864 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4865 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4866 emit_int8(0x58);
4867 emit_operand(dst, src);
4868 }
4869
4870 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4871 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4872 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4873 attributes.set_rex_vex_w_reverted();
4874 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4875 emit_int8(0x5C);
4876 emit_int8((unsigned char)(0xC0 | encode));
4877 }
4878
4879 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4880 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4881 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4882 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4883 emit_int8(0x5C);
4884 emit_int8((unsigned char)(0xC0 | encode));
4885 }
4886
4887 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4888 assert(VM_Version::supports_avx(), "");
4889 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4890 attributes.set_rex_vex_w_reverted();
4891 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4892 emit_int8(0x5C);
4893 emit_int8((unsigned char)(0xC0 | encode));
4894 }
4895
4896 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4897 assert(VM_Version::supports_avx(), "");
4898 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4899 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4900 emit_int8(0x5C);
4901 emit_int8((unsigned char)(0xC0 | encode));
4902 }
4903
4904 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4905 assert(VM_Version::supports_avx(), "");
4906 InstructionMark im(this);
4907 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4908 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4909 attributes.set_rex_vex_w_reverted();
4910 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4911 emit_int8(0x5C);
4912 emit_operand(dst, src);
4913 }
4914
4915 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4916 assert(VM_Version::supports_avx(), "");
4917 InstructionMark im(this);
4918 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4919 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4920 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4921 emit_int8(0x5C);
4922 emit_operand(dst, src);
4923 }
4924
4925 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4926 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4927 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4928 attributes.set_rex_vex_w_reverted();
4929 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4930 emit_int8(0x59);
4931 emit_int8((unsigned char)(0xC0 | encode));
4932 }
4933
4934 void Assembler::mulpd(XMMRegister dst, Address src) {
4935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4936 InstructionMark im(this);
4937 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4938 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4939 attributes.set_rex_vex_w_reverted();
4940 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4941 emit_int8(0x59);
4942 emit_operand(dst, src);
4943 }
4944
4945 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4948 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4949 emit_int8(0x59);
4950 emit_int8((unsigned char)(0xC0 | encode));
4951 }
4952
4953 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4954 assert(VM_Version::supports_avx(), "");
4955 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4956 attributes.set_rex_vex_w_reverted();
4957 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4958 emit_int8(0x59);
4959 emit_int8((unsigned char)(0xC0 | encode));
4960 }
4961
4962 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4963 assert(VM_Version::supports_avx(), "");
4964 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4965 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4966 emit_int8(0x59);
4967 emit_int8((unsigned char)(0xC0 | encode));
4968 }
4969
4970 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4971 assert(VM_Version::supports_avx(), "");
4972 InstructionMark im(this);
4973 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4974 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4975 attributes.set_rex_vex_w_reverted();
4976 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x59);
4978 emit_operand(dst, src);
4979 }
4980
4981 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4982 assert(VM_Version::supports_avx(), "");
4983 InstructionMark im(this);
4984 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4985 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4986 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4987 emit_int8(0x59);
4988 emit_operand(dst, src);
4989 }
4990
4991 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4993 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4994 attributes.set_rex_vex_w_reverted();
4995 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4996 emit_int8(0x5E);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5001 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5002 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5003 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5004 emit_int8(0x5E);
5005 emit_int8((unsigned char)(0xC0 | encode));
5006 }
5007
5008 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5009 assert(VM_Version::supports_avx(), "");
5010 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5011 attributes.set_rex_vex_w_reverted();
5012 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5013 emit_int8(0x5E);
5014 emit_int8((unsigned char)(0xC0 | encode));
5015 }
5016
5017 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5018 assert(VM_Version::supports_avx(), "");
5019 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5020 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5021 emit_int8(0x5E);
5022 emit_int8((unsigned char)(0xC0 | encode));
5023 }
5024
5025 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5026 assert(VM_Version::supports_avx(), "");
5027 InstructionMark im(this);
5028 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5029 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5030 attributes.set_rex_vex_w_reverted();
5031 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5032 emit_int8(0x5E);
5033 emit_operand(dst, src);
5034 }
5035
5036 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5037 assert(VM_Version::supports_avx(), "");
5038 InstructionMark im(this);
5039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5040 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5041 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5042 emit_int8(0x5E);
5043 emit_operand(dst, src);
5044 }
5045
5046 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5047 assert(VM_Version::supports_avx(), "");
5048 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5049 attributes.set_rex_vex_w_reverted();
5050 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5051 emit_int8(0x51);
5052 emit_int8((unsigned char)(0xC0 | encode));
5053 }
5054
5055 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5056 assert(VM_Version::supports_avx(), "");
5057 InstructionMark im(this);
5058 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5059 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5060 attributes.set_rex_vex_w_reverted();
5061 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5062 emit_int8(0x51);
5063 emit_operand(dst, src);
5064 }
5065
5066 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5068 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5069 attributes.set_rex_vex_w_reverted();
5070 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5071 emit_int8(0x54);
5072 emit_int8((unsigned char)(0xC0 | encode));
5073 }
5074
5075 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5076 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5078 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5079 emit_int8(0x54);
5080 emit_int8((unsigned char)(0xC0 | encode));
5081 }
5082
5083 void Assembler::andps(XMMRegister dst, Address src) {
5084 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5085 InstructionMark im(this);
5086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5087 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5088 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5089 emit_int8(0x54);
5090 emit_operand(dst, src);
5091 }
5092
5093 void Assembler::andpd(XMMRegister dst, Address src) {
5094 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5095 InstructionMark im(this);
5096 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5097 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5098 attributes.set_rex_vex_w_reverted();
5099 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8(0x54);
5101 emit_operand(dst, src);
5102 }
5103
5104 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5105 assert(VM_Version::supports_avx(), "");
5106 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5107 attributes.set_rex_vex_w_reverted();
5108 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5109 emit_int8(0x54);
5110 emit_int8((unsigned char)(0xC0 | encode));
5111 }
5112
5113 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5114 assert(VM_Version::supports_avx(), "");
5115 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5116 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5117 emit_int8(0x54);
5118 emit_int8((unsigned char)(0xC0 | encode));
5119 }
5120
5121 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5122 assert(VM_Version::supports_avx(), "");
5123 InstructionMark im(this);
5124 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5125 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5126 attributes.set_rex_vex_w_reverted();
5127 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5128 emit_int8(0x54);
5129 emit_operand(dst, src);
5130 }
5131
5132 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5133 assert(VM_Version::supports_avx(), "");
5134 InstructionMark im(this);
5135 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5136 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5137 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5138 emit_int8(0x54);
5139 emit_operand(dst, src);
5140 }
5141
5142 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5144 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5145 attributes.set_rex_vex_w_reverted();
5146 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5147 emit_int8(0x15);
5148 emit_int8((unsigned char)(0xC0 | encode));
5149 }
5150
5151 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5152 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5153 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5154 attributes.set_rex_vex_w_reverted();
5155 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5156 emit_int8(0x14);
5157 emit_int8((unsigned char)(0xC0 | encode));
5158 }
5159
5160 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5162 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5163 attributes.set_rex_vex_w_reverted();
5164 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5165 emit_int8(0x57);
5166 emit_int8((unsigned char)(0xC0 | encode));
5167 }
5168
5169 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5170 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5171 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5172 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5173 emit_int8(0x57);
5174 emit_int8((unsigned char)(0xC0 | encode));
5175 }
5176
5177 void Assembler::xorpd(XMMRegister dst, Address src) {
5178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5179 InstructionMark im(this);
5180 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5181 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5182 attributes.set_rex_vex_w_reverted();
5183 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5184 emit_int8(0x57);
5185 emit_operand(dst, src);
5186 }
5187
5188 void Assembler::xorps(XMMRegister dst, Address src) {
5189 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5190 InstructionMark im(this);
5191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5192 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5193 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5194 emit_int8(0x57);
5195 emit_operand(dst, src);
5196 }
5197
5198 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5199 assert(VM_Version::supports_avx(), "");
5200 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5201 attributes.set_rex_vex_w_reverted();
5202 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5203 emit_int8(0x57);
5204 emit_int8((unsigned char)(0xC0 | encode));
5205 }
5206
5207 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5208 assert(VM_Version::supports_avx(), "");
5209 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5210 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5211 emit_int8(0x57);
5212 emit_int8((unsigned char)(0xC0 | encode));
5213 }
5214
5215 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5216 assert(VM_Version::supports_avx(), "");
5217 InstructionMark im(this);
5218 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5220 attributes.set_rex_vex_w_reverted();
5221 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5222 emit_int8(0x57);
5223 emit_operand(dst, src);
5224 }
5225
5226 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5227 assert(VM_Version::supports_avx(), "");
5228 InstructionMark im(this);
5229 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5230 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5231 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5232 emit_int8(0x57);
5233 emit_operand(dst, src);
5234 }
5235
5236 // Integer vector arithmetic
5237 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5238 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5239 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5240 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5242 emit_int8(0x01);
5243 emit_int8((unsigned char)(0xC0 | encode));
5244 }
5245
5246 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5247 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5248 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5249 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5250 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5251 emit_int8(0x02);
5252 emit_int8((unsigned char)(0xC0 | encode));
5253 }
5254
5255 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5258 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5259 emit_int8((unsigned char)0xFC);
5260 emit_int8((unsigned char)(0xC0 | encode));
5261 }
5262
5263 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5265 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5266 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5267 emit_int8((unsigned char)0xFD);
5268 emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270
5271 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5274 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5275 emit_int8((unsigned char)0xFE);
5276 emit_int8((unsigned char)(0xC0 | encode));
5277 }
5278
5279 void Assembler::paddd(XMMRegister dst, Address src) {
5280 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5281 InstructionMark im(this);
5282 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5283 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5284 emit_int8((unsigned char)0xFE);
5285 emit_operand(dst, src);
5286 }
5287
5288 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5289 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5290 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5291 attributes.set_rex_vex_w_reverted();
5292 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5293 emit_int8((unsigned char)0xD4);
5294 emit_int8((unsigned char)(0xC0 | encode));
5295 }
5296
5297 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5298 assert(VM_Version::supports_sse3(), "");
5299 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5300 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5301 emit_int8(0x01);
5302 emit_int8((unsigned char)(0xC0 | encode));
5303 }
5304
5305 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5306 assert(VM_Version::supports_sse3(), "");
5307 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5308 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5309 emit_int8(0x02);
5310 emit_int8((unsigned char)(0xC0 | encode));
5311 }
5312
5313 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5314 assert(UseAVX > 0, "requires some form of AVX");
5315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5316 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5317 emit_int8((unsigned char)0xFC);
5318 emit_int8((unsigned char)(0xC0 | encode));
5319 }
5320
5321 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5322 assert(UseAVX > 0, "requires some form of AVX");
5323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5324 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5325 emit_int8((unsigned char)0xFD);
5326 emit_int8((unsigned char)(0xC0 | encode));
5327 }
5328
5329 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5330 assert(UseAVX > 0, "requires some form of AVX");
5331 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5333 emit_int8((unsigned char)0xFE);
5334 emit_int8((unsigned char)(0xC0 | encode));
5335 }
5336
5337 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5338 assert(UseAVX > 0, "requires some form of AVX");
5339 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5340 attributes.set_rex_vex_w_reverted();
5341 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5342 emit_int8((unsigned char)0xD4);
5343 emit_int8((unsigned char)(0xC0 | encode));
5344 }
5345
5346 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5347 assert(UseAVX > 0, "requires some form of AVX");
5348 InstructionMark im(this);
5349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5350 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5351 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5352 emit_int8((unsigned char)0xFC);
5353 emit_operand(dst, src);
5354 }
5355
5356 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5357 assert(UseAVX > 0, "requires some form of AVX");
5358 InstructionMark im(this);
5359 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5360 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5361 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5362 emit_int8((unsigned char)0xFD);
5363 emit_operand(dst, src);
5364 }
5365
5366 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5367 assert(UseAVX > 0, "requires some form of AVX");
5368 InstructionMark im(this);
5369 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5370 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5371 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5372 emit_int8((unsigned char)0xFE);
5373 emit_operand(dst, src);
5374 }
5375
5376 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5377 assert(UseAVX > 0, "requires some form of AVX");
5378 InstructionMark im(this);
5379 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5380 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5381 attributes.set_rex_vex_w_reverted();
5382 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5383 emit_int8((unsigned char)0xD4);
5384 emit_operand(dst, src);
5385 }
5386
5387 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5389 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5390 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5391 emit_int8((unsigned char)0xF8);
5392 emit_int8((unsigned char)(0xC0 | encode));
5393 }
5394
5395 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5396 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5397 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5399 emit_int8((unsigned char)0xF9);
5400 emit_int8((unsigned char)(0xC0 | encode));
5401 }
5402
5403 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5404 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5405 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5406 emit_int8((unsigned char)0xFA);
5407 emit_int8((unsigned char)(0xC0 | encode));
5408 }
5409
5410 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5412 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5413 attributes.set_rex_vex_w_reverted();
5414 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5415 emit_int8((unsigned char)0xFB);
5416 emit_int8((unsigned char)(0xC0 | encode));
5417 }
5418
5419 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5420 assert(UseAVX > 0, "requires some form of AVX");
5421 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5422 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5423 emit_int8((unsigned char)0xF8);
5424 emit_int8((unsigned char)(0xC0 | encode));
5425 }
5426
5427 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5428 assert(UseAVX > 0, "requires some form of AVX");
5429 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5430 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5431 emit_int8((unsigned char)0xF9);
5432 emit_int8((unsigned char)(0xC0 | encode));
5433 }
5434
5435 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5436 assert(UseAVX > 0, "requires some form of AVX");
5437 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5438 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5439 emit_int8((unsigned char)0xFA);
5440 emit_int8((unsigned char)(0xC0 | encode));
5441 }
5442
5443 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5444 assert(UseAVX > 0, "requires some form of AVX");
5445 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5446 attributes.set_rex_vex_w_reverted();
5447 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5448 emit_int8((unsigned char)0xFB);
5449 emit_int8((unsigned char)(0xC0 | encode));
5450 }
5451
5452 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5453 assert(UseAVX > 0, "requires some form of AVX");
5454 InstructionMark im(this);
5455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5456 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5457 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5458 emit_int8((unsigned char)0xF8);
5459 emit_operand(dst, src);
5460 }
5461
5462 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5463 assert(UseAVX > 0, "requires some form of AVX");
5464 InstructionMark im(this);
5465 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5466 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5467 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5468 emit_int8((unsigned char)0xF9);
5469 emit_operand(dst, src);
5470 }
5471
5472 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5473 assert(UseAVX > 0, "requires some form of AVX");
5474 InstructionMark im(this);
5475 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5476 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5477 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5478 emit_int8((unsigned char)0xFA);
5479 emit_operand(dst, src);
5480 }
5481
5482 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5483 assert(UseAVX > 0, "requires some form of AVX");
5484 InstructionMark im(this);
5485 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5486 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5487 attributes.set_rex_vex_w_reverted();
5488 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5489 emit_int8((unsigned char)0xFB);
5490 emit_operand(dst, src);
5491 }
5492
5493 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5496 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5497 emit_int8((unsigned char)0xD5);
5498 emit_int8((unsigned char)(0xC0 | encode));
5499 }
5500
5501 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5502 assert(VM_Version::supports_sse4_1(), "");
5503 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5504 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5505 emit_int8(0x40);
5506 emit_int8((unsigned char)(0xC0 | encode));
5507 }
5508
5509 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5510 assert(UseAVX > 0, "requires some form of AVX");
5511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5512 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5513 emit_int8((unsigned char)0xD5);
5514 emit_int8((unsigned char)(0xC0 | encode));
5515 }
5516
5517 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5518 assert(UseAVX > 0, "requires some form of AVX");
5519 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5520 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5521 emit_int8(0x40);
5522 emit_int8((unsigned char)(0xC0 | encode));
5523 }
5524
5525 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5526 assert(UseAVX > 2, "requires some form of EVEX");
5527 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5528 attributes.set_is_evex_instruction();
5529 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5530 emit_int8(0x40);
5531 emit_int8((unsigned char)(0xC0 | encode));
5532 }
5533
5534 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5535 assert(UseAVX > 0, "requires some form of AVX");
5536 InstructionMark im(this);
5537 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5538 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5539 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5540 emit_int8((unsigned char)0xD5);
5541 emit_operand(dst, src);
5542 }
5543
5544 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5545 assert(UseAVX > 0, "requires some form of AVX");
5546 InstructionMark im(this);
5547 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5548 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5549 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5550 emit_int8(0x40);
5551 emit_operand(dst, src);
5552 }
5553
5554 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5555 assert(UseAVX > 2, "requires some form of EVEX");
5556 InstructionMark im(this);
5557 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5558 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5559 attributes.set_is_evex_instruction();
5560 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5561 emit_int8(0x40);
5562 emit_operand(dst, src);
5563 }
5564
5565 // Shift packed integers left by specified number of bits.
5566 void Assembler::psllw(XMMRegister dst, int shift) {
5567 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5568 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5569 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5570 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5571 emit_int8(0x71);
5572 emit_int8((unsigned char)(0xC0 | encode));
5573 emit_int8(shift & 0xFF);
5574 }
5575
5576 void Assembler::pslld(XMMRegister dst, int shift) {
5577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5578 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5579 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5580 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5581 emit_int8(0x72);
5582 emit_int8((unsigned char)(0xC0 | encode));
5583 emit_int8(shift & 0xFF);
5584 }
5585
5586 void Assembler::psllq(XMMRegister dst, int shift) {
5587 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5588 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5589 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5590 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5591 emit_int8(0x73);
5592 emit_int8((unsigned char)(0xC0 | encode));
5593 emit_int8(shift & 0xFF);
5594 }
5595
5596 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5597 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5598 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5599 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5600 emit_int8((unsigned char)0xF1);
5601 emit_int8((unsigned char)(0xC0 | encode));
5602 }
5603
5604 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5606 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5607 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5608 emit_int8((unsigned char)0xF2);
5609 emit_int8((unsigned char)(0xC0 | encode));
5610 }
5611
5612 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5614 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5615 attributes.set_rex_vex_w_reverted();
5616 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5617 emit_int8((unsigned char)0xF3);
5618 emit_int8((unsigned char)(0xC0 | encode));
5619 }
5620
5621 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5622 assert(UseAVX > 0, "requires some form of AVX");
5623 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5624 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5625 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5626 emit_int8(0x71);
5627 emit_int8((unsigned char)(0xC0 | encode));
5628 emit_int8(shift & 0xFF);
5629 }
5630
5631 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5632 assert(UseAVX > 0, "requires some form of AVX");
5633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5634 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5635 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5636 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5637 emit_int8(0x72);
5638 emit_int8((unsigned char)(0xC0 | encode));
5639 emit_int8(shift & 0xFF);
5640 }
5641
5642 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5643 assert(UseAVX > 0, "requires some form of AVX");
5644 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5645 attributes.set_rex_vex_w_reverted();
5646 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5647 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5648 emit_int8(0x73);
5649 emit_int8((unsigned char)(0xC0 | encode));
5650 emit_int8(shift & 0xFF);
5651 }
5652
5653 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5654 assert(UseAVX > 0, "requires some form of AVX");
5655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5656 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5657 emit_int8((unsigned char)0xF1);
5658 emit_int8((unsigned char)(0xC0 | encode));
5659 }
5660
5661 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5662 assert(UseAVX > 0, "requires some form of AVX");
5663 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5664 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5665 emit_int8((unsigned char)0xF2);
5666 emit_int8((unsigned char)(0xC0 | encode));
5667 }
5668
5669 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5670 assert(UseAVX > 0, "requires some form of AVX");
5671 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5672 attributes.set_rex_vex_w_reverted();
5673 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5674 emit_int8((unsigned char)0xF3);
5675 emit_int8((unsigned char)(0xC0 | encode));
5676 }
5677
5678 // Shift packed integers logically right by specified number of bits.
5679 void Assembler::psrlw(XMMRegister dst, int shift) {
5680 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5681 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5682 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5683 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5684 emit_int8(0x71);
5685 emit_int8((unsigned char)(0xC0 | encode));
5686 emit_int8(shift & 0xFF);
5687 }
5688
5689 void Assembler::psrld(XMMRegister dst, int shift) {
5690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5691 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5692 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5693 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5694 emit_int8(0x72);
5695 emit_int8((unsigned char)(0xC0 | encode));
5696 emit_int8(shift & 0xFF);
5697 }
5698
5699 void Assembler::psrlq(XMMRegister dst, int shift) {
5700 // Do not confuse it with psrldq SSE2 instruction which
5701 // shifts 128 bit value in xmm register by number of bytes.
5702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5703 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5704 attributes.set_rex_vex_w_reverted();
5705 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5706 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5707 emit_int8(0x73);
5708 emit_int8((unsigned char)(0xC0 | encode));
5709 emit_int8(shift & 0xFF);
5710 }
5711
5712 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5714 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5715 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5716 emit_int8((unsigned char)0xD1);
5717 emit_int8((unsigned char)(0xC0 | encode));
5718 }
5719
5720 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5722 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5723 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5724 emit_int8((unsigned char)0xD2);
5725 emit_int8((unsigned char)(0xC0 | encode));
5726 }
5727
5728 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5730 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5731 attributes.set_rex_vex_w_reverted();
5732 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5733 emit_int8((unsigned char)0xD3);
5734 emit_int8((unsigned char)(0xC0 | encode));
5735 }
5736
5737 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5738 assert(UseAVX > 0, "requires some form of AVX");
5739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5740 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5741 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5742 emit_int8(0x71);
5743 emit_int8((unsigned char)(0xC0 | encode));
5744 emit_int8(shift & 0xFF);
5745 }
5746
5747 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5748 assert(UseAVX > 0, "requires some form of AVX");
5749 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5750 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5751 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5752 emit_int8(0x72);
5753 emit_int8((unsigned char)(0xC0 | encode));
5754 emit_int8(shift & 0xFF);
5755 }
5756
5757 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5758 assert(UseAVX > 0, "requires some form of AVX");
5759 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5760 attributes.set_rex_vex_w_reverted();
5761 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5762 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5763 emit_int8(0x73);
5764 emit_int8((unsigned char)(0xC0 | encode));
5765 emit_int8(shift & 0xFF);
5766 }
5767
5768 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5769 assert(UseAVX > 0, "requires some form of AVX");
5770 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5771 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5772 emit_int8((unsigned char)0xD1);
5773 emit_int8((unsigned char)(0xC0 | encode));
5774 }
5775
5776 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5777 assert(UseAVX > 0, "requires some form of AVX");
5778 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5779 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5780 emit_int8((unsigned char)0xD2);
5781 emit_int8((unsigned char)(0xC0 | encode));
5782 }
5783
5784 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5785 assert(UseAVX > 0, "requires some form of AVX");
5786 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5787 attributes.set_rex_vex_w_reverted();
5788 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5789 emit_int8((unsigned char)0xD3);
5790 emit_int8((unsigned char)(0xC0 | encode));
5791 }
5792
5793 // Shift packed integers arithmetically right by specified number of bits.
5794 void Assembler::psraw(XMMRegister dst, int shift) {
5795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5796 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5797 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5798 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5799 emit_int8(0x71);
5800 emit_int8((unsigned char)(0xC0 | encode));
5801 emit_int8(shift & 0xFF);
5802 }
5803
5804 void Assembler::psrad(XMMRegister dst, int shift) {
5805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5807 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5808 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5809 emit_int8(0x72);
5810 emit_int8((unsigned char)(0xC0 | encode));
5811 emit_int8(shift & 0xFF);
5812 }
5813
5814 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5817 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5818 emit_int8((unsigned char)0xE1);
5819 emit_int8((unsigned char)(0xC0 | encode));
5820 }
5821
5822 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5823 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5825 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5826 emit_int8((unsigned char)0xE2);
5827 emit_int8((unsigned char)(0xC0 | encode));
5828 }
5829
5830 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5831 assert(UseAVX > 0, "requires some form of AVX");
5832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5833 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5834 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5835 emit_int8(0x71);
5836 emit_int8((unsigned char)(0xC0 | encode));
5837 emit_int8(shift & 0xFF);
5838 }
5839
5840 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5841 assert(UseAVX > 0, "requires some form of AVX");
5842 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5843 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5844 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5845 emit_int8(0x72);
5846 emit_int8((unsigned char)(0xC0 | encode));
5847 emit_int8(shift & 0xFF);
5848 }
5849
5850 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5851 assert(UseAVX > 0, "requires some form of AVX");
5852 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5853 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5854 emit_int8((unsigned char)0xE1);
5855 emit_int8((unsigned char)(0xC0 | encode));
5856 }
5857
5858 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5859 assert(UseAVX > 0, "requires some form of AVX");
5860 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5861 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5862 emit_int8((unsigned char)0xE2);
5863 emit_int8((unsigned char)(0xC0 | encode));
5864 }
5865
5866
5867 // logical operations packed integers
5868 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5870 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5871 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5872 emit_int8((unsigned char)0xDB);
5873 emit_int8((unsigned char)(0xC0 | encode));
5874 }
5875
5876 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5877 assert(UseAVX > 0, "requires some form of AVX");
5878 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5879 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5880 emit_int8((unsigned char)0xDB);
5881 emit_int8((unsigned char)(0xC0 | encode));
5882 }
5883
5884 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5885 assert(UseAVX > 0, "requires some form of AVX");
5886 InstructionMark im(this);
5887 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5888 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5889 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5890 emit_int8((unsigned char)0xDB);
5891 emit_operand(dst, src);
5892 }
5893
5894 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5896 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5897 attributes.set_rex_vex_w_reverted();
5898 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5899 emit_int8((unsigned char)0xDF);
5900 emit_int8((unsigned char)(0xC0 | encode));
5901 }
5902
5903 void Assembler::por(XMMRegister dst, XMMRegister src) {
5904 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5905 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5906 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5907 emit_int8((unsigned char)0xEB);
5908 emit_int8((unsigned char)(0xC0 | encode));
5909 }
5910
5911 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5912 assert(UseAVX > 0, "requires some form of AVX");
5913 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5914 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5915 emit_int8((unsigned char)0xEB);
5916 emit_int8((unsigned char)(0xC0 | encode));
5917 }
5918
5919 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5920 assert(UseAVX > 0, "requires some form of AVX");
5921 InstructionMark im(this);
5922 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5923 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5924 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5925 emit_int8((unsigned char)0xEB);
5926 emit_operand(dst, src);
5927 }
5928
5929 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5931 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5932 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5933 emit_int8((unsigned char)0xEF);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 }
5936
5937 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5938 assert(UseAVX > 0, "requires some form of AVX");
5939 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5940 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5941 emit_int8((unsigned char)0xEF);
5942 emit_int8((unsigned char)(0xC0 | encode));
5943 }
5944
5945 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5946 assert(UseAVX > 0, "requires some form of AVX");
5947 InstructionMark im(this);
5948 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5949 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5950 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5951 emit_int8((unsigned char)0xEF);
5952 emit_operand(dst, src);
5953 }
5954
5955
5956 // vinserti forms
5957
5958 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5959 assert(VM_Version::supports_avx2(), "");
5960 assert(imm8 <= 0x01, "imm8: %u", imm8);
5961 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5962 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5963 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5964 emit_int8(0x38);
5965 emit_int8((unsigned char)(0xC0 | encode));
5966 // 0x00 - insert into lower 128 bits
5967 // 0x01 - insert into upper 128 bits
5968 emit_int8(imm8 & 0x01);
5969 }
5970
5971 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5972 assert(VM_Version::supports_avx2(), "");
5973 assert(dst != xnoreg, "sanity");
5974 assert(imm8 <= 0x01, "imm8: %u", imm8);
5975 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5976 InstructionMark im(this);
5977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5978 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5979 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5980 emit_int8(0x38);
5981 emit_operand(dst, src);
5982 // 0x00 - insert into lower 128 bits
5983 // 0x01 - insert into upper 128 bits
5984 emit_int8(imm8 & 0x01);
5985 }
5986
5987 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5988 assert(VM_Version::supports_evex(), "");
5989 assert(imm8 <= 0x03, "imm8: %u", imm8);
5990 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5991 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5992 emit_int8(0x38);
5993 emit_int8((unsigned char)(0xC0 | encode));
5994 // 0x00 - insert into q0 128 bits (0..127)
5995 // 0x01 - insert into q1 128 bits (128..255)
5996 // 0x02 - insert into q2 128 bits (256..383)
5997 // 0x03 - insert into q3 128 bits (384..511)
5998 emit_int8(imm8 & 0x03);
5999 }
6000
6001 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6002 assert(VM_Version::supports_avx(), "");
6003 assert(dst != xnoreg, "sanity");
6004 assert(imm8 <= 0x03, "imm8: %u", imm8);
6005 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6006 InstructionMark im(this);
6007 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6008 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6009 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6010 emit_int8(0x18);
6011 emit_operand(dst, src);
6012 // 0x00 - insert into q0 128 bits (0..127)
6013 // 0x01 - insert into q1 128 bits (128..255)
6014 // 0x02 - insert into q2 128 bits (256..383)
6015 // 0x03 - insert into q3 128 bits (384..511)
6016 emit_int8(imm8 & 0x03);
6017 }
6018
6019 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6020 assert(VM_Version::supports_evex(), "");
6021 assert(imm8 <= 0x01, "imm8: %u", imm8);
6022 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6023 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6024 emit_int8(0x38);
6025 emit_int8((unsigned char)(0xC0 | encode));
6026 // 0x00 - insert into lower 256 bits
6027 // 0x01 - insert into upper 256 bits
6028 emit_int8(imm8 & 0x01);
6029 }
6030
6031
6032 // vinsertf forms
6033
6034 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6035 assert(VM_Version::supports_avx(), "");
6036 assert(imm8 <= 0x01, "imm8: %u", imm8);
6037 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6038 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6039 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6040 emit_int8(0x18);
6041 emit_int8((unsigned char)(0xC0 | encode));
6042 // 0x00 - insert into lower 128 bits
6043 // 0x01 - insert into upper 128 bits
6044 emit_int8(imm8 & 0x01);
6045 }
6046
6047 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6048 assert(VM_Version::supports_avx(), "");
6049 assert(dst != xnoreg, "sanity");
6050 assert(imm8 <= 0x01, "imm8: %u", imm8);
6051 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6052 InstructionMark im(this);
6053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6054 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6055 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6056 emit_int8(0x18);
6057 emit_operand(dst, src);
6058 // 0x00 - insert into lower 128 bits
6059 // 0x01 - insert into upper 128 bits
6060 emit_int8(imm8 & 0x01);
6061 }
6062
6063 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6064 assert(VM_Version::supports_evex(), "");
6065 assert(imm8 <= 0x03, "imm8: %u", imm8);
6066 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6067 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6068 emit_int8(0x18);
6069 emit_int8((unsigned char)(0xC0 | encode));
6070 // 0x00 - insert into q0 128 bits (0..127)
6071 // 0x01 - insert into q1 128 bits (128..255)
6072 // 0x02 - insert into q2 128 bits (256..383)
6073 // 0x03 - insert into q3 128 bits (384..511)
6074 emit_int8(imm8 & 0x03);
6075 }
6076
6077 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6078 assert(VM_Version::supports_avx(), "");
6079 assert(dst != xnoreg, "sanity");
6080 assert(imm8 <= 0x03, "imm8: %u", imm8);
6081 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6082 InstructionMark im(this);
6083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6084 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6085 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6086 emit_int8(0x18);
6087 emit_operand(dst, src);
6088 // 0x00 - insert into q0 128 bits (0..127)
6089 // 0x01 - insert into q1 128 bits (128..255)
6090 // 0x02 - insert into q2 128 bits (256..383)
6091 // 0x03 - insert into q3 128 bits (384..511)
6092 emit_int8(imm8 & 0x03);
6093 }
6094
6095 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6096 assert(VM_Version::supports_evex(), "");
6097 assert(imm8 <= 0x01, "imm8: %u", imm8);
6098 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6099 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6100 emit_int8(0x1A);
6101 emit_int8((unsigned char)(0xC0 | encode));
6102 // 0x00 - insert into lower 256 bits
6103 // 0x01 - insert into upper 256 bits
6104 emit_int8(imm8 & 0x01);
6105 }
6106
6107 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6108 assert(VM_Version::supports_evex(), "");
6109 assert(dst != xnoreg, "sanity");
6110 assert(imm8 <= 0x01, "imm8: %u", imm8);
6111 InstructionMark im(this);
6112 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6113 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6114 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6115 emit_int8(0x1A);
6116 emit_operand(dst, src);
6117 // 0x00 - insert into lower 256 bits
6118 // 0x01 - insert into upper 256 bits
6119 emit_int8(imm8 & 0x01);
6120 }
6121
6122
6123 // vextracti forms
6124
6125 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6126 assert(VM_Version::supports_avx(), "");
6127 assert(imm8 <= 0x01, "imm8: %u", imm8);
6128 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6129 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6130 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6131 emit_int8(0x39);
6132 emit_int8((unsigned char)(0xC0 | encode));
6133 // 0x00 - extract from lower 128 bits
6134 // 0x01 - extract from upper 128 bits
6135 emit_int8(imm8 & 0x01);
6136 }
6137
6138 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6139 assert(VM_Version::supports_avx2(), "");
6140 assert(src != xnoreg, "sanity");
6141 assert(imm8 <= 0x01, "imm8: %u", imm8);
6142 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6143 InstructionMark im(this);
6144 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6145 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6146 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6147 emit_int8(0x39);
6148 emit_operand(src, dst);
6149 // 0x00 - extract from lower 128 bits
6150 // 0x01 - extract from upper 128 bits
6151 emit_int8(imm8 & 0x01);
6152 }
6153
6154 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6155 assert(VM_Version::supports_avx(), "");
6156 assert(imm8 <= 0x03, "imm8: %u", imm8);
6157 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6158 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6159 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6160 emit_int8(0x39);
6161 emit_int8((unsigned char)(0xC0 | encode));
6162 // 0x00 - extract from bits 127:0
6163 // 0x01 - extract from bits 255:128
6164 // 0x02 - extract from bits 383:256
6165 // 0x03 - extract from bits 511:384
6166 emit_int8(imm8 & 0x03);
6167 }
6168
6169 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6170 assert(VM_Version::supports_evex(), "");
6171 assert(src != xnoreg, "sanity");
6172 assert(imm8 <= 0x03, "imm8: %u", imm8);
6173 InstructionMark im(this);
6174 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6175 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6176 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6177 emit_int8(0x39);
6178 emit_operand(src, dst);
6179 // 0x00 - extract from bits 127:0
6180 // 0x01 - extract from bits 255:128
6181 // 0x02 - extract from bits 383:256
6182 // 0x03 - extract from bits 511:384
6183 emit_int8(imm8 & 0x03);
6184 }
6185
6186 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6187 assert(VM_Version::supports_avx512dq(), "");
6188 assert(imm8 <= 0x03, "imm8: %u", imm8);
6189 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6190 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6191 emit_int8(0x39);
6192 emit_int8((unsigned char)(0xC0 | encode));
6193 // 0x00 - extract from bits 127:0
6194 // 0x01 - extract from bits 255:128
6195 // 0x02 - extract from bits 383:256
6196 // 0x03 - extract from bits 511:384
6197 emit_int8(imm8 & 0x03);
6198 }
6199
6200 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6201 assert(VM_Version::supports_evex(), "");
6202 assert(imm8 <= 0x01, "imm8: %u", imm8);
6203 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6204 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6205 emit_int8(0x3B);
6206 emit_int8((unsigned char)(0xC0 | encode));
6207 // 0x00 - extract from lower 256 bits
6208 // 0x01 - extract from upper 256 bits
6209 emit_int8(imm8 & 0x01);
6210 }
6211
6212
6213 // vextractf forms
6214
6215 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6216 assert(VM_Version::supports_avx(), "");
6217 assert(imm8 <= 0x01, "imm8: %u", imm8);
6218 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6219 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6220 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6221 emit_int8(0x19);
6222 emit_int8((unsigned char)(0xC0 | encode));
6223 // 0x00 - extract from lower 128 bits
6224 // 0x01 - extract from upper 128 bits
6225 emit_int8(imm8 & 0x01);
6226 }
6227
6228 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6229 assert(VM_Version::supports_avx(), "");
6230 assert(src != xnoreg, "sanity");
6231 assert(imm8 <= 0x01, "imm8: %u", imm8);
6232 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6233 InstructionMark im(this);
6234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6235 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6236 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6237 emit_int8(0x19);
6238 emit_operand(src, dst);
6239 // 0x00 - extract from lower 128 bits
6240 // 0x01 - extract from upper 128 bits
6241 emit_int8(imm8 & 0x01);
6242 }
6243
6244 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6245 assert(VM_Version::supports_avx(), "");
6246 assert(imm8 <= 0x03, "imm8: %u", imm8);
6247 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6248 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6249 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6250 emit_int8(0x19);
6251 emit_int8((unsigned char)(0xC0 | encode));
6252 // 0x00 - extract from bits 127:0
6253 // 0x01 - extract from bits 255:128
6254 // 0x02 - extract from bits 383:256
6255 // 0x03 - extract from bits 511:384
6256 emit_int8(imm8 & 0x03);
6257 }
6258
6259 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6260 assert(VM_Version::supports_evex(), "");
6261 assert(src != xnoreg, "sanity");
6262 assert(imm8 <= 0x03, "imm8: %u", imm8);
6263 InstructionMark im(this);
6264 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6265 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6266 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6267 emit_int8(0x19);
6268 emit_operand(src, dst);
6269 // 0x00 - extract from bits 127:0
6270 // 0x01 - extract from bits 255:128
6271 // 0x02 - extract from bits 383:256
6272 // 0x03 - extract from bits 511:384
6273 emit_int8(imm8 & 0x03);
6274 }
6275
6276 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6277 assert(VM_Version::supports_avx512dq(), "");
6278 assert(imm8 <= 0x03, "imm8: %u", imm8);
6279 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6280 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6281 emit_int8(0x19);
6282 emit_int8((unsigned char)(0xC0 | encode));
6283 // 0x00 - extract from bits 127:0
6284 // 0x01 - extract from bits 255:128
6285 // 0x02 - extract from bits 383:256
6286 // 0x03 - extract from bits 511:384
6287 emit_int8(imm8 & 0x03);
6288 }
6289
6290 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6291 assert(VM_Version::supports_evex(), "");
6292 assert(imm8 <= 0x01, "imm8: %u", imm8);
6293 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6294 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6295 emit_int8(0x1B);
6296 emit_int8((unsigned char)(0xC0 | encode));
6297 // 0x00 - extract from lower 256 bits
6298 // 0x01 - extract from upper 256 bits
6299 emit_int8(imm8 & 0x01);
6300 }
6301
6302 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6303 assert(VM_Version::supports_evex(), "");
6304 assert(src != xnoreg, "sanity");
6305 assert(imm8 <= 0x01, "imm8: %u", imm8);
6306 InstructionMark im(this);
6307 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6308 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6309 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6310 emit_int8(0x1B);
6311 emit_operand(src, dst);
6312 // 0x00 - extract from lower 256 bits
6313 // 0x01 - extract from upper 256 bits
6314 emit_int8(imm8 & 0x01);
6315 }
6316
6317
6318 // legacy word/dword replicate
6319 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6320 assert(VM_Version::supports_avx2(), "");
6321 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6322 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6323 emit_int8(0x79);
6324 emit_int8((unsigned char)(0xC0 | encode));
6325 }
6326
6327 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6328 assert(VM_Version::supports_avx2(), "");
6329 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6330 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6331 emit_int8(0x58);
6332 emit_int8((unsigned char)(0xC0 | encode));
6333 }
6334
6335
6336 // xmm/mem sourced byte/word/dword/qword replicate
6337
6338 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6339 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6340 assert(VM_Version::supports_evex(), "");
6341 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6342 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6343 emit_int8(0x78);
6344 emit_int8((unsigned char)(0xC0 | encode));
6345 }
6346
6347 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6348 assert(VM_Version::supports_evex(), "");
6349 assert(dst != xnoreg, "sanity");
6350 InstructionMark im(this);
6351 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6352 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6353 // swap src<->dst for encoding
6354 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6355 emit_int8(0x78);
6356 emit_operand(dst, src);
6357 }
6358
6359 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6360 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6361 assert(VM_Version::supports_evex(), "");
6362 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6363 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6364 emit_int8(0x79);
6365 emit_int8((unsigned char)(0xC0 | encode));
6366 }
6367
6368 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6369 assert(VM_Version::supports_evex(), "");
6370 assert(dst != xnoreg, "sanity");
6371 InstructionMark im(this);
6372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6373 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6374 // swap src<->dst for encoding
6375 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6376 emit_int8(0x79);
6377 emit_operand(dst, src);
6378 }
6379
6380 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6381 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6382 assert(VM_Version::supports_evex(), "");
6383 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6384 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6385 emit_int8(0x58);
6386 emit_int8((unsigned char)(0xC0 | encode));
6387 }
6388
6389 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6390 assert(VM_Version::supports_evex(), "");
6391 assert(dst != xnoreg, "sanity");
6392 InstructionMark im(this);
6393 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6394 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6395 // swap src<->dst for encoding
6396 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6397 emit_int8(0x58);
6398 emit_operand(dst, src);
6399 }
6400
6401 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6402 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6403 assert(VM_Version::supports_evex(), "");
6404 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6405 attributes.set_rex_vex_w_reverted();
6406 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6407 emit_int8(0x59);
6408 emit_int8((unsigned char)(0xC0 | encode));
6409 }
6410
6411 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6412 assert(VM_Version::supports_evex(), "");
6413 assert(dst != xnoreg, "sanity");
6414 InstructionMark im(this);
6415 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6416 attributes.set_rex_vex_w_reverted();
6417 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6418 // swap src<->dst for encoding
6419 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6420 emit_int8(0x59);
6421 emit_operand(dst, src);
6422 }
6423
6424
6425 // scalar single/double precision replicate
6426
6427 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6428 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6429 assert(VM_Version::supports_evex(), "");
6430 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6431 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6432 emit_int8(0x18);
6433 emit_int8((unsigned char)(0xC0 | encode));
6434 }
6435
6436 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6437 assert(VM_Version::supports_evex(), "");
6438 assert(dst != xnoreg, "sanity");
6439 InstructionMark im(this);
6440 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6441 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6442 // swap src<->dst for encoding
6443 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6444 emit_int8(0x18);
6445 emit_operand(dst, src);
6446 }
6447
6448 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6449 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6450 assert(VM_Version::supports_evex(), "");
6451 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6452 attributes.set_rex_vex_w_reverted();
6453 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6454 emit_int8(0x19);
6455 emit_int8((unsigned char)(0xC0 | encode));
6456 }
6457
6458 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6459 assert(VM_Version::supports_evex(), "");
6460 assert(dst != xnoreg, "sanity");
6461 InstructionMark im(this);
6462 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6463 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6464 attributes.set_rex_vex_w_reverted();
6465 // swap src<->dst for encoding
6466 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6467 emit_int8(0x19);
6468 emit_operand(dst, src);
6469 }
6470
6471
6472 // gpr source broadcast forms
6473
6474 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6475 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6476 assert(VM_Version::supports_evex(), "");
6477 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6478 attributes.set_is_evex_instruction();
6479 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6480 emit_int8(0x7A);
6481 emit_int8((unsigned char)(0xC0 | encode));
6482 }
6483
6484 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6485 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6486 assert(VM_Version::supports_evex(), "");
6487 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6488 attributes.set_is_evex_instruction();
6489 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6490 emit_int8(0x7B);
6491 emit_int8((unsigned char)(0xC0 | encode));
6492 }
6493
6494 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6495 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6496 assert(VM_Version::supports_evex(), "");
6497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6498 attributes.set_is_evex_instruction();
6499 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6500 emit_int8(0x7C);
6501 emit_int8((unsigned char)(0xC0 | encode));
6502 }
6503
6504 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6505 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6506 assert(VM_Version::supports_evex(), "");
6507 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6508 attributes.set_is_evex_instruction();
6509 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6510 emit_int8(0x7C);
6511 emit_int8((unsigned char)(0xC0 | encode));
6512 }
6513
6514
6515 // Carry-Less Multiplication Quadword
6516 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6517 assert(VM_Version::supports_clmul(), "");
6518 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6519 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6520 emit_int8(0x44);
6521 emit_int8((unsigned char)(0xC0 | encode));
6522 emit_int8((unsigned char)mask);
6523 }
6524
6525 // Carry-Less Multiplication Quadword
6526 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6527 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6528 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6529 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6530 emit_int8(0x44);
6531 emit_int8((unsigned char)(0xC0 | encode));
6532 emit_int8((unsigned char)mask);
6533 }
6534
6535 void Assembler::vzeroupper() {
6536 assert(VM_Version::supports_avx(), "");
6537 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6538 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6539 emit_int8(0x77);
6540 }
6541
6542 #ifndef _LP64
6543 // 32bit only pieces of the assembler
6544
6545 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6546 // NO PREFIX AS NEVER 64BIT
6547 InstructionMark im(this);
6548 emit_int8((unsigned char)0x81);
6549 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6550 emit_data(imm32, rspec, 0);
6551 }
6552
6553 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6554 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6555 InstructionMark im(this);
6556 emit_int8((unsigned char)0x81);
6557 emit_operand(rdi, src1);
6558 emit_data(imm32, rspec, 0);
6559 }
6560
6561 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6562 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6563 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6564 void Assembler::cmpxchg8(Address adr) {
6565 InstructionMark im(this);
6566 emit_int8(0x0F);
6567 emit_int8((unsigned char)0xC7);
6568 emit_operand(rcx, adr);
6569 }
6570
6571 void Assembler::decl(Register dst) {
6572 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6573 emit_int8(0x48 | dst->encoding());
6574 }
6575
6576 #endif // _LP64
6577
6578 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6579
6580 void Assembler::fabs() {
6581 emit_int8((unsigned char)0xD9);
6582 emit_int8((unsigned char)0xE1);
6583 }
6584
6585 void Assembler::fadd(int i) {
6586 emit_farith(0xD8, 0xC0, i);
6587 }
6588
6589 void Assembler::fadd_d(Address src) {
6590 InstructionMark im(this);
6591 emit_int8((unsigned char)0xDC);
6592 emit_operand32(rax, src);
6593 }
6594
6595 void Assembler::fadd_s(Address src) {
6596 InstructionMark im(this);
6597 emit_int8((unsigned char)0xD8);
6598 emit_operand32(rax, src);
6599 }
6600
6601 void Assembler::fadda(int i) {
6602 emit_farith(0xDC, 0xC0, i);
6603 }
6604
6605 void Assembler::faddp(int i) {
6606 emit_farith(0xDE, 0xC0, i);
6607 }
6608
6609 void Assembler::fchs() {
6610 emit_int8((unsigned char)0xD9);
6611 emit_int8((unsigned char)0xE0);
6612 }
6613
6614 void Assembler::fcom(int i) {
6615 emit_farith(0xD8, 0xD0, i);
6616 }
6617
6618 void Assembler::fcomp(int i) {
6619 emit_farith(0xD8, 0xD8, i);
6620 }
6621
6622 void Assembler::fcomp_d(Address src) {
6623 InstructionMark im(this);
6624 emit_int8((unsigned char)0xDC);
6625 emit_operand32(rbx, src);
6626 }
6627
6628 void Assembler::fcomp_s(Address src) {
6629 InstructionMark im(this);
6630 emit_int8((unsigned char)0xD8);
6631 emit_operand32(rbx, src);
6632 }
6633
6634 void Assembler::fcompp() {
6635 emit_int8((unsigned char)0xDE);
6636 emit_int8((unsigned char)0xD9);
6637 }
6638
6639 void Assembler::fcos() {
6640 emit_int8((unsigned char)0xD9);
6641 emit_int8((unsigned char)0xFF);
6642 }
6643
6644 void Assembler::fdecstp() {
6645 emit_int8((unsigned char)0xD9);
6646 emit_int8((unsigned char)0xF6);
6647 }
6648
6649 void Assembler::fdiv(int i) {
6650 emit_farith(0xD8, 0xF0, i);
6651 }
6652
6653 void Assembler::fdiv_d(Address src) {
6654 InstructionMark im(this);
6655 emit_int8((unsigned char)0xDC);
6656 emit_operand32(rsi, src);
6657 }
6658
6659 void Assembler::fdiv_s(Address src) {
6660 InstructionMark im(this);
6661 emit_int8((unsigned char)0xD8);
6662 emit_operand32(rsi, src);
6663 }
6664
6665 void Assembler::fdiva(int i) {
6666 emit_farith(0xDC, 0xF8, i);
6667 }
6668
6669 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6670 // is erroneous for some of the floating-point instructions below.
6671
6672 void Assembler::fdivp(int i) {
6673 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6674 }
6675
6676 void Assembler::fdivr(int i) {
6677 emit_farith(0xD8, 0xF8, i);
6678 }
6679
6680 void Assembler::fdivr_d(Address src) {
6681 InstructionMark im(this);
6682 emit_int8((unsigned char)0xDC);
6683 emit_operand32(rdi, src);
6684 }
6685
6686 void Assembler::fdivr_s(Address src) {
6687 InstructionMark im(this);
6688 emit_int8((unsigned char)0xD8);
6689 emit_operand32(rdi, src);
6690 }
6691
6692 void Assembler::fdivra(int i) {
6693 emit_farith(0xDC, 0xF0, i);
6694 }
6695
6696 void Assembler::fdivrp(int i) {
6697 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6698 }
6699
6700 void Assembler::ffree(int i) {
6701 emit_farith(0xDD, 0xC0, i);
6702 }
6703
6704 void Assembler::fild_d(Address adr) {
6705 InstructionMark im(this);
6706 emit_int8((unsigned char)0xDF);
6707 emit_operand32(rbp, adr);
6708 }
6709
6710 void Assembler::fild_s(Address adr) {
6711 InstructionMark im(this);
6712 emit_int8((unsigned char)0xDB);
6713 emit_operand32(rax, adr);
6714 }
6715
6716 void Assembler::fincstp() {
6717 emit_int8((unsigned char)0xD9);
6718 emit_int8((unsigned char)0xF7);
6719 }
6720
6721 void Assembler::finit() {
6722 emit_int8((unsigned char)0x9B);
6723 emit_int8((unsigned char)0xDB);
6724 emit_int8((unsigned char)0xE3);
6725 }
6726
6727 void Assembler::fist_s(Address adr) {
6728 InstructionMark im(this);
6729 emit_int8((unsigned char)0xDB);
6730 emit_operand32(rdx, adr);
6731 }
6732
6733 void Assembler::fistp_d(Address adr) {
6734 InstructionMark im(this);
6735 emit_int8((unsigned char)0xDF);
6736 emit_operand32(rdi, adr);
6737 }
6738
6739 void Assembler::fistp_s(Address adr) {
6740 InstructionMark im(this);
6741 emit_int8((unsigned char)0xDB);
6742 emit_operand32(rbx, adr);
6743 }
6744
6745 void Assembler::fld1() {
6746 emit_int8((unsigned char)0xD9);
6747 emit_int8((unsigned char)0xE8);
6748 }
6749
6750 void Assembler::fld_d(Address adr) {
6751 InstructionMark im(this);
6752 emit_int8((unsigned char)0xDD);
6753 emit_operand32(rax, adr);
6754 }
6755
6756 void Assembler::fld_s(Address adr) {
6757 InstructionMark im(this);
6758 emit_int8((unsigned char)0xD9);
6759 emit_operand32(rax, adr);
6760 }
6761
6762
6763 void Assembler::fld_s(int index) {
6764 emit_farith(0xD9, 0xC0, index);
6765 }
6766
6767 void Assembler::fld_x(Address adr) {
6768 InstructionMark im(this);
6769 emit_int8((unsigned char)0xDB);
6770 emit_operand32(rbp, adr);
6771 }
6772
6773 void Assembler::fldcw(Address src) {
6774 InstructionMark im(this);
6775 emit_int8((unsigned char)0xD9);
6776 emit_operand32(rbp, src);
6777 }
6778
6779 void Assembler::fldenv(Address src) {
6780 InstructionMark im(this);
6781 emit_int8((unsigned char)0xD9);
6782 emit_operand32(rsp, src);
6783 }
6784
6785 void Assembler::fldlg2() {
6786 emit_int8((unsigned char)0xD9);
6787 emit_int8((unsigned char)0xEC);
6788 }
6789
6790 void Assembler::fldln2() {
6791 emit_int8((unsigned char)0xD9);
6792 emit_int8((unsigned char)0xED);
6793 }
6794
6795 void Assembler::fldz() {
6796 emit_int8((unsigned char)0xD9);
6797 emit_int8((unsigned char)0xEE);
6798 }
6799
6800 void Assembler::flog() {
6801 fldln2();
6802 fxch();
6803 fyl2x();
6804 }
6805
6806 void Assembler::flog10() {
6807 fldlg2();
6808 fxch();
6809 fyl2x();
6810 }
6811
6812 void Assembler::fmul(int i) {
6813 emit_farith(0xD8, 0xC8, i);
6814 }
6815
6816 void Assembler::fmul_d(Address src) {
6817 InstructionMark im(this);
6818 emit_int8((unsigned char)0xDC);
6819 emit_operand32(rcx, src);
6820 }
6821
6822 void Assembler::fmul_s(Address src) {
6823 InstructionMark im(this);
6824 emit_int8((unsigned char)0xD8);
6825 emit_operand32(rcx, src);
6826 }
6827
6828 void Assembler::fmula(int i) {
6829 emit_farith(0xDC, 0xC8, i);
6830 }
6831
6832 void Assembler::fmulp(int i) {
6833 emit_farith(0xDE, 0xC8, i);
6834 }
6835
6836 void Assembler::fnsave(Address dst) {
6837 InstructionMark im(this);
6838 emit_int8((unsigned char)0xDD);
6839 emit_operand32(rsi, dst);
6840 }
6841
6842 void Assembler::fnstcw(Address src) {
6843 InstructionMark im(this);
6844 emit_int8((unsigned char)0x9B);
6845 emit_int8((unsigned char)0xD9);
6846 emit_operand32(rdi, src);
6847 }
6848
6849 void Assembler::fnstsw_ax() {
6850 emit_int8((unsigned char)0xDF);
6851 emit_int8((unsigned char)0xE0);
6852 }
6853
6854 void Assembler::fprem() {
6855 emit_int8((unsigned char)0xD9);
6856 emit_int8((unsigned char)0xF8);
6857 }
6858
6859 void Assembler::fprem1() {
6860 emit_int8((unsigned char)0xD9);
6861 emit_int8((unsigned char)0xF5);
6862 }
6863
6864 void Assembler::frstor(Address src) {
6865 InstructionMark im(this);
6866 emit_int8((unsigned char)0xDD);
6867 emit_operand32(rsp, src);
6868 }
6869
6870 void Assembler::fsin() {
6871 emit_int8((unsigned char)0xD9);
6872 emit_int8((unsigned char)0xFE);
6873 }
6874
6875 void Assembler::fsqrt() {
6876 emit_int8((unsigned char)0xD9);
6877 emit_int8((unsigned char)0xFA);
6878 }
6879
6880 void Assembler::fst_d(Address adr) {
6881 InstructionMark im(this);
6882 emit_int8((unsigned char)0xDD);
6883 emit_operand32(rdx, adr);
6884 }
6885
6886 void Assembler::fst_s(Address adr) {
6887 InstructionMark im(this);
6888 emit_int8((unsigned char)0xD9);
6889 emit_operand32(rdx, adr);
6890 }
6891
6892 void Assembler::fstp_d(Address adr) {
6893 InstructionMark im(this);
6894 emit_int8((unsigned char)0xDD);
6895 emit_operand32(rbx, adr);
6896 }
6897
6898 void Assembler::fstp_d(int index) {
6899 emit_farith(0xDD, 0xD8, index);
6900 }
6901
6902 void Assembler::fstp_s(Address adr) {
6903 InstructionMark im(this);
6904 emit_int8((unsigned char)0xD9);
6905 emit_operand32(rbx, adr);
6906 }
6907
6908 void Assembler::fstp_x(Address adr) {
6909 InstructionMark im(this);
6910 emit_int8((unsigned char)0xDB);
6911 emit_operand32(rdi, adr);
6912 }
6913
6914 void Assembler::fsub(int i) {
6915 emit_farith(0xD8, 0xE0, i);
6916 }
6917
6918 void Assembler::fsub_d(Address src) {
6919 InstructionMark im(this);
6920 emit_int8((unsigned char)0xDC);
6921 emit_operand32(rsp, src);
6922 }
6923
6924 void Assembler::fsub_s(Address src) {
6925 InstructionMark im(this);
6926 emit_int8((unsigned char)0xD8);
6927 emit_operand32(rsp, src);
6928 }
6929
6930 void Assembler::fsuba(int i) {
6931 emit_farith(0xDC, 0xE8, i);
6932 }
6933
6934 void Assembler::fsubp(int i) {
6935 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6936 }
6937
6938 void Assembler::fsubr(int i) {
6939 emit_farith(0xD8, 0xE8, i);
6940 }
6941
6942 void Assembler::fsubr_d(Address src) {
6943 InstructionMark im(this);
6944 emit_int8((unsigned char)0xDC);
6945 emit_operand32(rbp, src);
6946 }
6947
6948 void Assembler::fsubr_s(Address src) {
6949 InstructionMark im(this);
6950 emit_int8((unsigned char)0xD8);
6951 emit_operand32(rbp, src);
6952 }
6953
6954 void Assembler::fsubra(int i) {
6955 emit_farith(0xDC, 0xE0, i);
6956 }
6957
6958 void Assembler::fsubrp(int i) {
6959 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6960 }
6961
6962 void Assembler::ftan() {
6963 emit_int8((unsigned char)0xD9);
6964 emit_int8((unsigned char)0xF2);
6965 emit_int8((unsigned char)0xDD);
6966 emit_int8((unsigned char)0xD8);
6967 }
6968
6969 void Assembler::ftst() {
6970 emit_int8((unsigned char)0xD9);
6971 emit_int8((unsigned char)0xE4);
6972 }
6973
6974 void Assembler::fucomi(int i) {
6975 // make sure the instruction is supported (introduced for P6, together with cmov)
6976 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6977 emit_farith(0xDB, 0xE8, i);
6978 }
6979
6980 void Assembler::fucomip(int i) {
6981 // make sure the instruction is supported (introduced for P6, together with cmov)
6982 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6983 emit_farith(0xDF, 0xE8, i);
6984 }
6985
6986 void Assembler::fwait() {
6987 emit_int8((unsigned char)0x9B);
6988 }
6989
6990 void Assembler::fxch(int i) {
6991 emit_farith(0xD9, 0xC8, i);
6992 }
6993
6994 void Assembler::fyl2x() {
6995 emit_int8((unsigned char)0xD9);
6996 emit_int8((unsigned char)0xF1);
6997 }
6998
6999 void Assembler::frndint() {
7000 emit_int8((unsigned char)0xD9);
7001 emit_int8((unsigned char)0xFC);
7002 }
7003
7004 void Assembler::f2xm1() {
7005 emit_int8((unsigned char)0xD9);
7006 emit_int8((unsigned char)0xF0);
7007 }
7008
7009 void Assembler::fldl2e() {
7010 emit_int8((unsigned char)0xD9);
7011 emit_int8((unsigned char)0xEA);
7012 }
7013
7014 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7015 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7016 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7017 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7018
7019 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7020 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7021 if (pre > 0) {
7022 emit_int8(simd_pre[pre]);
7023 }
7024 if (rex_w) {
7025 prefixq(adr, xreg);
7026 } else {
7027 prefix(adr, xreg);
7028 }
7029 if (opc > 0) {
7030 emit_int8(0x0F);
7031 int opc2 = simd_opc[opc];
7032 if (opc2 > 0) {
7033 emit_int8(opc2);
7034 }
7035 }
7036 }
7037
7038 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7039 if (pre > 0) {
7040 emit_int8(simd_pre[pre]);
7041 }
7042 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7043 if (opc > 0) {
7044 emit_int8(0x0F);
7045 int opc2 = simd_opc[opc];
7046 if (opc2 > 0) {
7047 emit_int8(opc2);
7048 }
7049 }
7050 return encode;
7051 }
7052
7053
7054 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7055 int vector_len = _attributes->get_vector_len();
7056 bool vex_w = _attributes->is_rex_vex_w();
7057 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7058 prefix(VEX_3bytes);
7059
7060 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7061 byte1 = (~byte1) & 0xE0;
7062 byte1 |= opc;
7063 emit_int8(byte1);
7064
7065 int byte2 = ((~nds_enc) & 0xf) << 3;
7066 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7067 emit_int8(byte2);
7068 } else {
7069 prefix(VEX_2bytes);
7070
7071 int byte1 = vex_r ? VEX_R : 0;
7072 byte1 = (~byte1) & 0x80;
7073 byte1 |= ((~nds_enc) & 0xf) << 3;
7074 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7075 emit_int8(byte1);
7076 }
7077 }
7078
7079 // This is a 4 byte encoding
7080 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7081 // EVEX 0x62 prefix
7082 prefix(EVEX_4bytes);
7083 bool vex_w = _attributes->is_rex_vex_w();
7084 int evex_encoding = (vex_w ? VEX_W : 0);
7085 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7086 _attributes->set_evex_encoding(evex_encoding);
7087
7088 // P0: byte 2, initialized to RXBR`00mm
7089 // instead of not'd
7090 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7091 byte2 = (~byte2) & 0xF0;
7092 // confine opc opcode extensions in mm bits to lower two bits
7093 // of form {0F, 0F_38, 0F_3A}
7094 byte2 |= opc;
7095 emit_int8(byte2);
7096
7097 // P1: byte 3 as Wvvvv1pp
7098 int byte3 = ((~nds_enc) & 0xf) << 3;
7099 // p[10] is always 1
7100 byte3 |= EVEX_F;
7101 byte3 |= (vex_w & 1) << 7;
7102 // confine pre opcode extensions in pp bits to lower two bits
7103 // of form {66, F3, F2}
7104 byte3 |= pre;
7105 emit_int8(byte3);
7106
7107 // P2: byte 4 as zL'Lbv'aaa
7108 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7109 int byte4 = (_attributes->is_no_reg_mask()) ?
7110 0 :
7111 _attributes->get_embedded_opmask_register_specifier();
7112 // EVEX.v` for extending EVEX.vvvv or VIDX
7113 byte4 |= (evex_v ? 0: EVEX_V);
7114 // third EXEC.b for broadcast actions
7115 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7116 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7117 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7118 // last is EVEX.z for zero/merge actions
7119 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7120 emit_int8(byte4);
7121 }
7122
7123 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7124 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7125 bool vex_b = adr.base_needs_rex();
7126 bool vex_x = adr.index_needs_rex();
7127 set_attributes(attributes);
7128 attributes->set_current_assembler(this);
7129
7130 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7131 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7132 switch (attributes->get_vector_len()) {
7133 case AVX_128bit:
7134 case AVX_256bit:
7135 attributes->set_is_legacy_mode();
7136 break;
7137 }
7138 }
7139
7140 // For pure EVEX check and see if this instruction
7141 // is allowed in legacy mode and has resources which will
7142 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7143 // else that field is set when we encode to EVEX
7144 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7145 !_is_managed && !attributes->is_evex_instruction()) {
7146 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7147 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7148 if (check_register_bank) {
7149 // check nds_enc and xreg_enc for upper bank usage
7150 if (nds_enc < 16 && xreg_enc < 16) {
7151 attributes->set_is_legacy_mode();
7152 }
7153 } else {
7154 attributes->set_is_legacy_mode();
7155 }
7156 }
7157 }
7158
7159 _is_managed = false;
7160 if (UseAVX > 2 && !attributes->is_legacy_mode())
7161 {
7162 bool evex_r = (xreg_enc >= 16);
7163 bool evex_v = (nds_enc >= 16);
7164 attributes->set_is_evex_instruction();
7165 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7166 } else {
7167 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7168 attributes->set_rex_vex_w(false);
7169 }
7170 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7171 }
7172 }
7173
7174 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7175 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7176 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7177 bool vex_x = false;
7178 set_attributes(attributes);
7179 attributes->set_current_assembler(this);
7180 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7181
7182 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7183 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7184 switch (attributes->get_vector_len()) {
7185 case AVX_128bit:
7186 case AVX_256bit:
7187 if (check_register_bank) {
7188 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7189 // up propagate arithmetic instructions to meet RA requirements
7190 attributes->set_vector_len(AVX_512bit);
7191 } else {
7192 attributes->set_is_legacy_mode();
7193 }
7194 } else {
7195 attributes->set_is_legacy_mode();
7196 }
7197 break;
7198 }
7199 }
7200
7201 // For pure EVEX check and see if this instruction
7202 // is allowed in legacy mode and has resources which will
7203 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7204 // else that field is set when we encode to EVEX
7205 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7206 !_is_managed && !attributes->is_evex_instruction()) {
7207 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7208 if (check_register_bank) {
7209 // check dst_enc, nds_enc and src_enc for upper bank usage
7210 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7211 attributes->set_is_legacy_mode();
7212 }
7213 } else {
7214 attributes->set_is_legacy_mode();
7215 }
7216 }
7217 }
7218
7219 _is_managed = false;
7220 if (UseAVX > 2 && !attributes->is_legacy_mode())
7221 {
7222 bool evex_r = (dst_enc >= 16);
7223 bool evex_v = (nds_enc >= 16);
7224 // can use vex_x as bank extender on rm encoding
7225 vex_x = (src_enc >= 16);
7226 attributes->set_is_evex_instruction();
7227 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7228 } else {
7229 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7230 attributes->set_rex_vex_w(false);
7231 }
7232 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7233 }
7234
7235 // return modrm byte components for operands
7236 return (((dst_enc & 7) << 3) | (src_enc & 7));
7237 }
7238
7239
7240 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7241 VexOpcode opc, InstructionAttr *attributes) {
7242 if (UseAVX > 0) {
7243 int xreg_enc = xreg->encoding();
7244 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7245 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7246 } else {
7247 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7248 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7249 }
7250 }
7251
7252 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7253 VexOpcode opc, InstructionAttr *attributes) {
7254 int dst_enc = dst->encoding();
7255 int src_enc = src->encoding();
7256 if (UseAVX > 0) {
7257 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7258 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7259 } else {
7260 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7261 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7262 }
7263 }
7264
7265 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7266 assert(VM_Version::supports_avx(), "");
7267 assert(!VM_Version::supports_evex(), "");
7268 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7269 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7270 emit_int8((unsigned char)0xC2);
7271 emit_int8((unsigned char)(0xC0 | encode));
7272 emit_int8((unsigned char)(0xF & cop));
7273 }
7274
7275 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7276 assert(VM_Version::supports_avx(), "");
7277 assert(!VM_Version::supports_evex(), "");
7278 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7279 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7280 emit_int8((unsigned char)0x4B);
7281 emit_int8((unsigned char)(0xC0 | encode));
7282 int src2_enc = src2->encoding();
7283 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7284 }
7285
7286 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7287 assert(VM_Version::supports_bmi2(), "");
7288 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7289 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7290 emit_int8((unsigned char)0xF7);
7291 emit_int8((unsigned char)(0xC0 | encode));
7292 }
7293
7294 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7295 assert(VM_Version::supports_bmi2(), "");
7296 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7297 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7298 emit_int8((unsigned char)0xF7);
7299 emit_int8((unsigned char)(0xC0 | encode));
7300 }
7301
7302 #ifndef _LP64
7303
7304 void Assembler::incl(Register dst) {
7305 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7306 emit_int8(0x40 | dst->encoding());
7307 }
7308
7309 void Assembler::lea(Register dst, Address src) {
7310 leal(dst, src);
7311 }
7312
7313 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7314 InstructionMark im(this);
7315 emit_int8((unsigned char)0xC7);
7316 emit_operand(rax, dst);
7317 emit_data((int)imm32, rspec, 0);
7318 }
7319
7320 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7321 InstructionMark im(this);
7322 int encode = prefix_and_encode(dst->encoding());
7323 emit_int8((unsigned char)(0xB8 | encode));
7324 emit_data((int)imm32, rspec, 0);
7325 }
7326
7327 void Assembler::popa() { // 32bit
7328 emit_int8(0x61);
7329 }
7330
7331 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7332 InstructionMark im(this);
7333 emit_int8(0x68);
7334 emit_data(imm32, rspec, 0);
7335 }
7336
7337 void Assembler::pusha() { // 32bit
7338 emit_int8(0x60);
7339 }
7340
7341 void Assembler::set_byte_if_not_zero(Register dst) {
7342 emit_int8(0x0F);
7343 emit_int8((unsigned char)0x95);
7344 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7345 }
7346
7347 void Assembler::shldl(Register dst, Register src) {
7348 emit_int8(0x0F);
7349 emit_int8((unsigned char)0xA5);
7350 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7351 }
7352
7353 // 0F A4 / r ib
7354 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7355 emit_int8(0x0F);
7356 emit_int8((unsigned char)0xA4);
7357 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7358 emit_int8(imm8);
7359 }
7360
7361 void Assembler::shrdl(Register dst, Register src) {
7362 emit_int8(0x0F);
7363 emit_int8((unsigned char)0xAD);
7364 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7365 }
7366
7367 #else // LP64
7368
7369 void Assembler::set_byte_if_not_zero(Register dst) {
7370 int enc = prefix_and_encode(dst->encoding(), true);
7371 emit_int8(0x0F);
7372 emit_int8((unsigned char)0x95);
7373 emit_int8((unsigned char)(0xE0 | enc));
7374 }
7375
7376 // 64bit only pieces of the assembler
7377 // This should only be used by 64bit instructions that can use rip-relative
7378 // it cannot be used by instructions that want an immediate value.
7379
7380 bool Assembler::reachable(AddressLiteral adr) {
7381 int64_t disp;
7382 // None will force a 64bit literal to the code stream. Likely a placeholder
7383 // for something that will be patched later and we need to certain it will
7384 // always be reachable.
7385 if (adr.reloc() == relocInfo::none) {
7386 return false;
7387 }
7388 if (adr.reloc() == relocInfo::internal_word_type) {
7389 // This should be rip relative and easily reachable.
7390 return true;
7391 }
7392 if (adr.reloc() == relocInfo::virtual_call_type ||
7393 adr.reloc() == relocInfo::opt_virtual_call_type ||
7394 adr.reloc() == relocInfo::static_call_type ||
7395 adr.reloc() == relocInfo::static_stub_type ) {
7396 // This should be rip relative within the code cache and easily
7397 // reachable until we get huge code caches. (At which point
7398 // ic code is going to have issues).
7399 return true;
7400 }
7401 if (adr.reloc() != relocInfo::external_word_type &&
7402 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7403 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7404 adr.reloc() != relocInfo::runtime_call_type ) {
7405 return false;
7406 }
7407
7408 // Stress the correction code
7409 if (ForceUnreachable) {
7410 // Must be runtimecall reloc, see if it is in the codecache
7411 // Flipping stuff in the codecache to be unreachable causes issues
7412 // with things like inline caches where the additional instructions
7413 // are not handled.
7414 if (CodeCache::find_blob(adr._target) == NULL) {
7415 return false;
7416 }
7417 }
7418 // For external_word_type/runtime_call_type if it is reachable from where we
7419 // are now (possibly a temp buffer) and where we might end up
7420 // anywhere in the codeCache then we are always reachable.
7421 // This would have to change if we ever save/restore shared code
7422 // to be more pessimistic.
7423 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7424 if (!is_simm32(disp)) return false;
7425 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7426 if (!is_simm32(disp)) return false;
7427
7428 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7429
7430 // Because rip relative is a disp + address_of_next_instruction and we
7431 // don't know the value of address_of_next_instruction we apply a fudge factor
7432 // to make sure we will be ok no matter the size of the instruction we get placed into.
7433 // We don't have to fudge the checks above here because they are already worst case.
7434
7435 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7436 // + 4 because better safe than sorry.
7437 const int fudge = 12 + 4;
7438 if (disp < 0) {
7439 disp -= fudge;
7440 } else {
7441 disp += fudge;
7442 }
7443 return is_simm32(disp);
7444 }
7445
7446 // Check if the polling page is not reachable from the code cache using rip-relative
7447 // addressing.
7448 bool Assembler::is_polling_page_far() {
7449 intptr_t addr = (intptr_t)os::get_polling_page();
7450 return ForceUnreachable ||
7451 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7452 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7453 }
7454
7455 void Assembler::emit_data64(jlong data,
7456 relocInfo::relocType rtype,
7457 int format) {
7458 if (rtype == relocInfo::none) {
7459 emit_int64(data);
7460 } else {
7461 emit_data64(data, Relocation::spec_simple(rtype), format);
7462 }
7463 }
7464
7465 void Assembler::emit_data64(jlong data,
7466 RelocationHolder const& rspec,
7467 int format) {
7468 assert(imm_operand == 0, "default format must be immediate in this file");
7469 assert(imm_operand == format, "must be immediate");
7470 assert(inst_mark() != NULL, "must be inside InstructionMark");
7471 // Do not use AbstractAssembler::relocate, which is not intended for
7472 // embedded words. Instead, relocate to the enclosing instruction.
7473 code_section()->relocate(inst_mark(), rspec, format);
7474 #ifdef ASSERT
7475 check_relocation(rspec, format);
7476 #endif
7477 emit_int64(data);
7478 }
7479
7480 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7481 if (reg_enc >= 8) {
7482 prefix(REX_B);
7483 reg_enc -= 8;
7484 } else if (byteinst && reg_enc >= 4) {
7485 prefix(REX);
7486 }
7487 return reg_enc;
7488 }
7489
7490 int Assembler::prefixq_and_encode(int reg_enc) {
7491 if (reg_enc < 8) {
7492 prefix(REX_W);
7493 } else {
7494 prefix(REX_WB);
7495 reg_enc -= 8;
7496 }
7497 return reg_enc;
7498 }
7499
7500 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7501 if (dst_enc < 8) {
7502 if (src_enc >= 8) {
7503 prefix(REX_B);
7504 src_enc -= 8;
7505 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7506 prefix(REX);
7507 }
7508 } else {
7509 if (src_enc < 8) {
7510 prefix(REX_R);
7511 } else {
7512 prefix(REX_RB);
7513 src_enc -= 8;
7514 }
7515 dst_enc -= 8;
7516 }
7517 return dst_enc << 3 | src_enc;
7518 }
7519
7520 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7521 if (dst_enc < 8) {
7522 if (src_enc < 8) {
7523 prefix(REX_W);
7524 } else {
7525 prefix(REX_WB);
7526 src_enc -= 8;
7527 }
7528 } else {
7529 if (src_enc < 8) {
7530 prefix(REX_WR);
7531 } else {
7532 prefix(REX_WRB);
7533 src_enc -= 8;
7534 }
7535 dst_enc -= 8;
7536 }
7537 return dst_enc << 3 | src_enc;
7538 }
7539
7540 void Assembler::prefix(Register reg) {
7541 if (reg->encoding() >= 8) {
7542 prefix(REX_B);
7543 }
7544 }
7545
7546 void Assembler::prefix(Register dst, Register src, Prefix p) {
7547 if (src->encoding() >= 8) {
7548 p = (Prefix)(p | REX_B);
7549 }
7550 if (dst->encoding() >= 8) {
7551 p = (Prefix)( p | REX_R);
7552 }
7553 if (p != Prefix_EMPTY) {
7554 // do not generate an empty prefix
7555 prefix(p);
7556 }
7557 }
7558
7559 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7560 if (adr.base_needs_rex()) {
7561 if (adr.index_needs_rex()) {
7562 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7563 } else {
7564 prefix(REX_B);
7565 }
7566 } else {
7567 if (adr.index_needs_rex()) {
7568 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7569 }
7570 }
7571 if (dst->encoding() >= 8) {
7572 p = (Prefix)(p | REX_R);
7573 }
7574 if (p != Prefix_EMPTY) {
7575 // do not generate an empty prefix
7576 prefix(p);
7577 }
7578 }
7579
7580 void Assembler::prefix(Address adr) {
7581 if (adr.base_needs_rex()) {
7582 if (adr.index_needs_rex()) {
7583 prefix(REX_XB);
7584 } else {
7585 prefix(REX_B);
7586 }
7587 } else {
7588 if (adr.index_needs_rex()) {
7589 prefix(REX_X);
7590 }
7591 }
7592 }
7593
7594 void Assembler::prefixq(Address adr) {
7595 if (adr.base_needs_rex()) {
7596 if (adr.index_needs_rex()) {
7597 prefix(REX_WXB);
7598 } else {
7599 prefix(REX_WB);
7600 }
7601 } else {
7602 if (adr.index_needs_rex()) {
7603 prefix(REX_WX);
7604 } else {
7605 prefix(REX_W);
7606 }
7607 }
7608 }
7609
7610
7611 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7612 if (reg->encoding() < 8) {
7613 if (adr.base_needs_rex()) {
7614 if (adr.index_needs_rex()) {
7615 prefix(REX_XB);
7616 } else {
7617 prefix(REX_B);
7618 }
7619 } else {
7620 if (adr.index_needs_rex()) {
7621 prefix(REX_X);
7622 } else if (byteinst && reg->encoding() >= 4 ) {
7623 prefix(REX);
7624 }
7625 }
7626 } else {
7627 if (adr.base_needs_rex()) {
7628 if (adr.index_needs_rex()) {
7629 prefix(REX_RXB);
7630 } else {
7631 prefix(REX_RB);
7632 }
7633 } else {
7634 if (adr.index_needs_rex()) {
7635 prefix(REX_RX);
7636 } else {
7637 prefix(REX_R);
7638 }
7639 }
7640 }
7641 }
7642
7643 void Assembler::prefixq(Address adr, Register src) {
7644 if (src->encoding() < 8) {
7645 if (adr.base_needs_rex()) {
7646 if (adr.index_needs_rex()) {
7647 prefix(REX_WXB);
7648 } else {
7649 prefix(REX_WB);
7650 }
7651 } else {
7652 if (adr.index_needs_rex()) {
7653 prefix(REX_WX);
7654 } else {
7655 prefix(REX_W);
7656 }
7657 }
7658 } else {
7659 if (adr.base_needs_rex()) {
7660 if (adr.index_needs_rex()) {
7661 prefix(REX_WRXB);
7662 } else {
7663 prefix(REX_WRB);
7664 }
7665 } else {
7666 if (adr.index_needs_rex()) {
7667 prefix(REX_WRX);
7668 } else {
7669 prefix(REX_WR);
7670 }
7671 }
7672 }
7673 }
7674
7675 void Assembler::prefix(Address adr, XMMRegister reg) {
7676 if (reg->encoding() < 8) {
7677 if (adr.base_needs_rex()) {
7678 if (adr.index_needs_rex()) {
7679 prefix(REX_XB);
7680 } else {
7681 prefix(REX_B);
7682 }
7683 } else {
7684 if (adr.index_needs_rex()) {
7685 prefix(REX_X);
7686 }
7687 }
7688 } else {
7689 if (adr.base_needs_rex()) {
7690 if (adr.index_needs_rex()) {
7691 prefix(REX_RXB);
7692 } else {
7693 prefix(REX_RB);
7694 }
7695 } else {
7696 if (adr.index_needs_rex()) {
7697 prefix(REX_RX);
7698 } else {
7699 prefix(REX_R);
7700 }
7701 }
7702 }
7703 }
7704
7705 void Assembler::prefixq(Address adr, XMMRegister src) {
7706 if (src->encoding() < 8) {
7707 if (adr.base_needs_rex()) {
7708 if (adr.index_needs_rex()) {
7709 prefix(REX_WXB);
7710 } else {
7711 prefix(REX_WB);
7712 }
7713 } else {
7714 if (adr.index_needs_rex()) {
7715 prefix(REX_WX);
7716 } else {
7717 prefix(REX_W);
7718 }
7719 }
7720 } else {
7721 if (adr.base_needs_rex()) {
7722 if (adr.index_needs_rex()) {
7723 prefix(REX_WRXB);
7724 } else {
7725 prefix(REX_WRB);
7726 }
7727 } else {
7728 if (adr.index_needs_rex()) {
7729 prefix(REX_WRX);
7730 } else {
7731 prefix(REX_WR);
7732 }
7733 }
7734 }
7735 }
7736
7737 void Assembler::adcq(Register dst, int32_t imm32) {
7738 (void) prefixq_and_encode(dst->encoding());
7739 emit_arith(0x81, 0xD0, dst, imm32);
7740 }
7741
7742 void Assembler::adcq(Register dst, Address src) {
7743 InstructionMark im(this);
7744 prefixq(src, dst);
7745 emit_int8(0x13);
7746 emit_operand(dst, src);
7747 }
7748
7749 void Assembler::adcq(Register dst, Register src) {
7750 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7751 emit_arith(0x13, 0xC0, dst, src);
7752 }
7753
7754 void Assembler::addq(Address dst, int32_t imm32) {
7755 InstructionMark im(this);
7756 prefixq(dst);
7757 emit_arith_operand(0x81, rax, dst,imm32);
7758 }
7759
7760 void Assembler::addq(Address dst, Register src) {
7761 InstructionMark im(this);
7762 prefixq(dst, src);
7763 emit_int8(0x01);
7764 emit_operand(src, dst);
7765 }
7766
7767 void Assembler::addq(Register dst, int32_t imm32) {
7768 (void) prefixq_and_encode(dst->encoding());
7769 emit_arith(0x81, 0xC0, dst, imm32);
7770 }
7771
7772 void Assembler::addq(Register dst, Address src) {
7773 InstructionMark im(this);
7774 prefixq(src, dst);
7775 emit_int8(0x03);
7776 emit_operand(dst, src);
7777 }
7778
7779 void Assembler::addq(Register dst, Register src) {
7780 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7781 emit_arith(0x03, 0xC0, dst, src);
7782 }
7783
7784 void Assembler::adcxq(Register dst, Register src) {
7785 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7786 emit_int8((unsigned char)0x66);
7787 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7788 emit_int8(0x0F);
7789 emit_int8(0x38);
7790 emit_int8((unsigned char)0xF6);
7791 emit_int8((unsigned char)(0xC0 | encode));
7792 }
7793
7794 void Assembler::adoxq(Register dst, Register src) {
7795 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7796 emit_int8((unsigned char)0xF3);
7797 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7798 emit_int8(0x0F);
7799 emit_int8(0x38);
7800 emit_int8((unsigned char)0xF6);
7801 emit_int8((unsigned char)(0xC0 | encode));
7802 }
7803
7804 void Assembler::andq(Address dst, int32_t imm32) {
7805 InstructionMark im(this);
7806 prefixq(dst);
7807 emit_int8((unsigned char)0x81);
7808 emit_operand(rsp, dst, 4);
7809 emit_int32(imm32);
7810 }
7811
7812 void Assembler::andq(Register dst, int32_t imm32) {
7813 (void) prefixq_and_encode(dst->encoding());
7814 emit_arith(0x81, 0xE0, dst, imm32);
7815 }
7816
7817 void Assembler::andq(Register dst, Address src) {
7818 InstructionMark im(this);
7819 prefixq(src, dst);
7820 emit_int8(0x23);
7821 emit_operand(dst, src);
7822 }
7823
7824 void Assembler::andq(Register dst, Register src) {
7825 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7826 emit_arith(0x23, 0xC0, dst, src);
7827 }
7828
7829 void Assembler::andnq(Register dst, Register src1, Register src2) {
7830 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7831 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7832 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7833 emit_int8((unsigned char)0xF2);
7834 emit_int8((unsigned char)(0xC0 | encode));
7835 }
7836
7837 void Assembler::andnq(Register dst, Register src1, Address src2) {
7838 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7839 InstructionMark im(this);
7840 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7841 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7842 emit_int8((unsigned char)0xF2);
7843 emit_operand(dst, src2);
7844 }
7845
7846 void Assembler::bsfq(Register dst, Register src) {
7847 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7848 emit_int8(0x0F);
7849 emit_int8((unsigned char)0xBC);
7850 emit_int8((unsigned char)(0xC0 | encode));
7851 }
7852
7853 void Assembler::bsrq(Register dst, Register src) {
7854 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7855 emit_int8(0x0F);
7856 emit_int8((unsigned char)0xBD);
7857 emit_int8((unsigned char)(0xC0 | encode));
7858 }
7859
7860 void Assembler::bswapq(Register reg) {
7861 int encode = prefixq_and_encode(reg->encoding());
7862 emit_int8(0x0F);
7863 emit_int8((unsigned char)(0xC8 | encode));
7864 }
7865
7866 void Assembler::blsiq(Register dst, Register src) {
7867 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7868 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7869 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7870 emit_int8((unsigned char)0xF3);
7871 emit_int8((unsigned char)(0xC0 | encode));
7872 }
7873
7874 void Assembler::blsiq(Register dst, Address src) {
7875 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7876 InstructionMark im(this);
7877 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7878 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7879 emit_int8((unsigned char)0xF3);
7880 emit_operand(rbx, src);
7881 }
7882
7883 void Assembler::blsmskq(Register dst, Register src) {
7884 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7885 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7886 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7887 emit_int8((unsigned char)0xF3);
7888 emit_int8((unsigned char)(0xC0 | encode));
7889 }
7890
7891 void Assembler::blsmskq(Register dst, Address src) {
7892 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7893 InstructionMark im(this);
7894 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7895 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7896 emit_int8((unsigned char)0xF3);
7897 emit_operand(rdx, src);
7898 }
7899
7900 void Assembler::blsrq(Register dst, Register src) {
7901 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7902 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7903 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7904 emit_int8((unsigned char)0xF3);
7905 emit_int8((unsigned char)(0xC0 | encode));
7906 }
7907
7908 void Assembler::blsrq(Register dst, Address src) {
7909 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7910 InstructionMark im(this);
7911 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7912 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7913 emit_int8((unsigned char)0xF3);
7914 emit_operand(rcx, src);
7915 }
7916
7917 void Assembler::cdqq() {
7918 prefix(REX_W);
7919 emit_int8((unsigned char)0x99);
7920 }
7921
7922 void Assembler::clflush(Address adr) {
7923 prefix(adr);
7924 emit_int8(0x0F);
7925 emit_int8((unsigned char)0xAE);
7926 emit_operand(rdi, adr);
7927 }
7928
7929 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7930 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7931 emit_int8(0x0F);
7932 emit_int8(0x40 | cc);
7933 emit_int8((unsigned char)(0xC0 | encode));
7934 }
7935
7936 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7937 InstructionMark im(this);
7938 prefixq(src, dst);
7939 emit_int8(0x0F);
7940 emit_int8(0x40 | cc);
7941 emit_operand(dst, src);
7942 }
7943
7944 void Assembler::cmpq(Address dst, int32_t imm32) {
7945 InstructionMark im(this);
7946 prefixq(dst);
7947 emit_int8((unsigned char)0x81);
7948 emit_operand(rdi, dst, 4);
7949 emit_int32(imm32);
7950 }
7951
7952 void Assembler::cmpq(Register dst, int32_t imm32) {
7953 (void) prefixq_and_encode(dst->encoding());
7954 emit_arith(0x81, 0xF8, dst, imm32);
7955 }
7956
7957 void Assembler::cmpq(Address dst, Register src) {
7958 InstructionMark im(this);
7959 prefixq(dst, src);
7960 emit_int8(0x3B);
7961 emit_operand(src, dst);
7962 }
7963
7964 void Assembler::cmpq(Register dst, Register src) {
7965 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7966 emit_arith(0x3B, 0xC0, dst, src);
7967 }
7968
7969 void Assembler::cmpq(Register dst, Address src) {
7970 InstructionMark im(this);
7971 prefixq(src, dst);
7972 emit_int8(0x3B);
7973 emit_operand(dst, src);
7974 }
7975
7976 void Assembler::cmpxchgq(Register reg, Address adr) {
7977 InstructionMark im(this);
7978 prefixq(adr, reg);
7979 emit_int8(0x0F);
7980 emit_int8((unsigned char)0xB1);
7981 emit_operand(reg, adr);
7982 }
7983
7984 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7985 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7986 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7987 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7988 emit_int8(0x2A);
7989 emit_int8((unsigned char)(0xC0 | encode));
7990 }
7991
7992 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7993 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7994 InstructionMark im(this);
7995 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7996 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7997 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7998 emit_int8(0x2A);
7999 emit_operand(dst, src);
8000 }
8001
8002 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8003 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8004 InstructionMark im(this);
8005 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8006 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8007 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8008 emit_int8(0x2A);
8009 emit_operand(dst, src);
8010 }
8011
8012 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8013 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8014 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8015 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8016 emit_int8(0x2C);
8017 emit_int8((unsigned char)(0xC0 | encode));
8018 }
8019
8020 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8021 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8022 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8023 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8024 emit_int8(0x2C);
8025 emit_int8((unsigned char)(0xC0 | encode));
8026 }
8027
8028 void Assembler::decl(Register dst) {
8029 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8030 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8031 int encode = prefix_and_encode(dst->encoding());
8032 emit_int8((unsigned char)0xFF);
8033 emit_int8((unsigned char)(0xC8 | encode));
8034 }
8035
8036 void Assembler::decq(Register dst) {
8037 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8038 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8039 int encode = prefixq_and_encode(dst->encoding());
8040 emit_int8((unsigned char)0xFF);
8041 emit_int8(0xC8 | encode);
8042 }
8043
8044 void Assembler::decq(Address dst) {
8045 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8046 InstructionMark im(this);
8047 prefixq(dst);
8048 emit_int8((unsigned char)0xFF);
8049 emit_operand(rcx, dst);
8050 }
8051
8052 void Assembler::fxrstor(Address src) {
8053 prefixq(src);
8054 emit_int8(0x0F);
8055 emit_int8((unsigned char)0xAE);
8056 emit_operand(as_Register(1), src);
8057 }
8058
8059 void Assembler::xrstor(Address src) {
8060 prefixq(src);
8061 emit_int8(0x0F);
8062 emit_int8((unsigned char)0xAE);
8063 emit_operand(as_Register(5), src);
8064 }
8065
8066 void Assembler::fxsave(Address dst) {
8067 prefixq(dst);
8068 emit_int8(0x0F);
8069 emit_int8((unsigned char)0xAE);
8070 emit_operand(as_Register(0), dst);
8071 }
8072
8073 void Assembler::xsave(Address dst) {
8074 prefixq(dst);
8075 emit_int8(0x0F);
8076 emit_int8((unsigned char)0xAE);
8077 emit_operand(as_Register(4), dst);
8078 }
8079
8080 void Assembler::idivq(Register src) {
8081 int encode = prefixq_and_encode(src->encoding());
8082 emit_int8((unsigned char)0xF7);
8083 emit_int8((unsigned char)(0xF8 | encode));
8084 }
8085
8086 void Assembler::imulq(Register dst, Register src) {
8087 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8088 emit_int8(0x0F);
8089 emit_int8((unsigned char)0xAF);
8090 emit_int8((unsigned char)(0xC0 | encode));
8091 }
8092
8093 void Assembler::imulq(Register dst, Register src, int value) {
8094 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8095 if (is8bit(value)) {
8096 emit_int8(0x6B);
8097 emit_int8((unsigned char)(0xC0 | encode));
8098 emit_int8(value & 0xFF);
8099 } else {
8100 emit_int8(0x69);
8101 emit_int8((unsigned char)(0xC0 | encode));
8102 emit_int32(value);
8103 }
8104 }
8105
8106 void Assembler::imulq(Register dst, Address src) {
8107 InstructionMark im(this);
8108 prefixq(src, dst);
8109 emit_int8(0x0F);
8110 emit_int8((unsigned char) 0xAF);
8111 emit_operand(dst, src);
8112 }
8113
8114 void Assembler::incl(Register dst) {
8115 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8116 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8117 int encode = prefix_and_encode(dst->encoding());
8118 emit_int8((unsigned char)0xFF);
8119 emit_int8((unsigned char)(0xC0 | encode));
8120 }
8121
8122 void Assembler::incq(Register dst) {
8123 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8124 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8125 int encode = prefixq_and_encode(dst->encoding());
8126 emit_int8((unsigned char)0xFF);
8127 emit_int8((unsigned char)(0xC0 | encode));
8128 }
8129
8130 void Assembler::incq(Address dst) {
8131 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8132 InstructionMark im(this);
8133 prefixq(dst);
8134 emit_int8((unsigned char)0xFF);
8135 emit_operand(rax, dst);
8136 }
8137
8138 void Assembler::lea(Register dst, Address src) {
8139 leaq(dst, src);
8140 }
8141
8142 void Assembler::leaq(Register dst, Address src) {
8143 InstructionMark im(this);
8144 prefixq(src, dst);
8145 emit_int8((unsigned char)0x8D);
8146 emit_operand(dst, src);
8147 }
8148
8149 void Assembler::mov64(Register dst, int64_t imm64) {
8150 InstructionMark im(this);
8151 int encode = prefixq_and_encode(dst->encoding());
8152 emit_int8((unsigned char)(0xB8 | encode));
8153 emit_int64(imm64);
8154 }
8155
8156 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8157 InstructionMark im(this);
8158 int encode = prefixq_and_encode(dst->encoding());
8159 emit_int8(0xB8 | encode);
8160 emit_data64(imm64, rspec);
8161 }
8162
8163 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8164 InstructionMark im(this);
8165 int encode = prefix_and_encode(dst->encoding());
8166 emit_int8((unsigned char)(0xB8 | encode));
8167 emit_data((int)imm32, rspec, narrow_oop_operand);
8168 }
8169
8170 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8171 InstructionMark im(this);
8172 prefix(dst);
8173 emit_int8((unsigned char)0xC7);
8174 emit_operand(rax, dst, 4);
8175 emit_data((int)imm32, rspec, narrow_oop_operand);
8176 }
8177
8178 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8179 InstructionMark im(this);
8180 int encode = prefix_and_encode(src1->encoding());
8181 emit_int8((unsigned char)0x81);
8182 emit_int8((unsigned char)(0xF8 | encode));
8183 emit_data((int)imm32, rspec, narrow_oop_operand);
8184 }
8185
8186 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8187 InstructionMark im(this);
8188 prefix(src1);
8189 emit_int8((unsigned char)0x81);
8190 emit_operand(rax, src1, 4);
8191 emit_data((int)imm32, rspec, narrow_oop_operand);
8192 }
8193
8194 void Assembler::lzcntq(Register dst, Register src) {
8195 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8196 emit_int8((unsigned char)0xF3);
8197 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8198 emit_int8(0x0F);
8199 emit_int8((unsigned char)0xBD);
8200 emit_int8((unsigned char)(0xC0 | encode));
8201 }
8202
8203 void Assembler::movdq(XMMRegister dst, Register src) {
8204 // table D-1 says MMX/SSE2
8205 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8206 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8207 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8208 emit_int8(0x6E);
8209 emit_int8((unsigned char)(0xC0 | encode));
8210 }
8211
8212 void Assembler::movdq(Register dst, XMMRegister src) {
8213 // table D-1 says MMX/SSE2
8214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8215 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8216 // swap src/dst to get correct prefix
8217 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8218 emit_int8(0x7E);
8219 emit_int8((unsigned char)(0xC0 | encode));
8220 }
8221
8222 void Assembler::movq(Register dst, Register src) {
8223 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8224 emit_int8((unsigned char)0x8B);
8225 emit_int8((unsigned char)(0xC0 | encode));
8226 }
8227
8228 void Assembler::movq(Register dst, Address src) {
8229 InstructionMark im(this);
8230 prefixq(src, dst);
8231 emit_int8((unsigned char)0x8B);
8232 emit_operand(dst, src);
8233 }
8234
8235 void Assembler::movq(Address dst, Register src) {
8236 InstructionMark im(this);
8237 prefixq(dst, src);
8238 emit_int8((unsigned char)0x89);
8239 emit_operand(src, dst);
8240 }
8241
8242 void Assembler::movsbq(Register dst, Address src) {
8243 InstructionMark im(this);
8244 prefixq(src, dst);
8245 emit_int8(0x0F);
8246 emit_int8((unsigned char)0xBE);
8247 emit_operand(dst, src);
8248 }
8249
8250 void Assembler::movsbq(Register dst, Register src) {
8251 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8252 emit_int8(0x0F);
8253 emit_int8((unsigned char)0xBE);
8254 emit_int8((unsigned char)(0xC0 | encode));
8255 }
8256
8257 void Assembler::movslq(Register dst, int32_t imm32) {
8258 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8259 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8260 // as a result we shouldn't use until tested at runtime...
8261 ShouldNotReachHere();
8262 InstructionMark im(this);
8263 int encode = prefixq_and_encode(dst->encoding());
8264 emit_int8((unsigned char)(0xC7 | encode));
8265 emit_int32(imm32);
8266 }
8267
8268 void Assembler::movslq(Address dst, int32_t imm32) {
8269 assert(is_simm32(imm32), "lost bits");
8270 InstructionMark im(this);
8271 prefixq(dst);
8272 emit_int8((unsigned char)0xC7);
8273 emit_operand(rax, dst, 4);
8274 emit_int32(imm32);
8275 }
8276
8277 void Assembler::movslq(Register dst, Address src) {
8278 InstructionMark im(this);
8279 prefixq(src, dst);
8280 emit_int8(0x63);
8281 emit_operand(dst, src);
8282 }
8283
8284 void Assembler::movslq(Register dst, Register src) {
8285 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8286 emit_int8(0x63);
8287 emit_int8((unsigned char)(0xC0 | encode));
8288 }
8289
8290 void Assembler::movswq(Register dst, Address src) {
8291 InstructionMark im(this);
8292 prefixq(src, dst);
8293 emit_int8(0x0F);
8294 emit_int8((unsigned char)0xBF);
8295 emit_operand(dst, src);
8296 }
8297
8298 void Assembler::movswq(Register dst, Register src) {
8299 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8300 emit_int8((unsigned char)0x0F);
8301 emit_int8((unsigned char)0xBF);
8302 emit_int8((unsigned char)(0xC0 | encode));
8303 }
8304
8305 void Assembler::movzbq(Register dst, Address src) {
8306 InstructionMark im(this);
8307 prefixq(src, dst);
8308 emit_int8((unsigned char)0x0F);
8309 emit_int8((unsigned char)0xB6);
8310 emit_operand(dst, src);
8311 }
8312
8313 void Assembler::movzbq(Register dst, Register src) {
8314 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8315 emit_int8(0x0F);
8316 emit_int8((unsigned char)0xB6);
8317 emit_int8(0xC0 | encode);
8318 }
8319
8320 void Assembler::movzwq(Register dst, Address src) {
8321 InstructionMark im(this);
8322 prefixq(src, dst);
8323 emit_int8((unsigned char)0x0F);
8324 emit_int8((unsigned char)0xB7);
8325 emit_operand(dst, src);
8326 }
8327
8328 void Assembler::movzwq(Register dst, Register src) {
8329 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8330 emit_int8((unsigned char)0x0F);
8331 emit_int8((unsigned char)0xB7);
8332 emit_int8((unsigned char)(0xC0 | encode));
8333 }
8334
8335 void Assembler::mulq(Address src) {
8336 InstructionMark im(this);
8337 prefixq(src);
8338 emit_int8((unsigned char)0xF7);
8339 emit_operand(rsp, src);
8340 }
8341
8342 void Assembler::mulq(Register src) {
8343 int encode = prefixq_and_encode(src->encoding());
8344 emit_int8((unsigned char)0xF7);
8345 emit_int8((unsigned char)(0xE0 | encode));
8346 }
8347
8348 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8349 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8350 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8351 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8352 emit_int8((unsigned char)0xF6);
8353 emit_int8((unsigned char)(0xC0 | encode));
8354 }
8355
8356 void Assembler::negq(Register dst) {
8357 int encode = prefixq_and_encode(dst->encoding());
8358 emit_int8((unsigned char)0xF7);
8359 emit_int8((unsigned char)(0xD8 | encode));
8360 }
8361
8362 void Assembler::notq(Register dst) {
8363 int encode = prefixq_and_encode(dst->encoding());
8364 emit_int8((unsigned char)0xF7);
8365 emit_int8((unsigned char)(0xD0 | encode));
8366 }
8367
8368 void Assembler::orq(Address dst, int32_t imm32) {
8369 InstructionMark im(this);
8370 prefixq(dst);
8371 emit_int8((unsigned char)0x81);
8372 emit_operand(rcx, dst, 4);
8373 emit_int32(imm32);
8374 }
8375
8376 void Assembler::orq(Register dst, int32_t imm32) {
8377 (void) prefixq_and_encode(dst->encoding());
8378 emit_arith(0x81, 0xC8, dst, imm32);
8379 }
8380
8381 void Assembler::orq(Register dst, Address src) {
8382 InstructionMark im(this);
8383 prefixq(src, dst);
8384 emit_int8(0x0B);
8385 emit_operand(dst, src);
8386 }
8387
8388 void Assembler::orq(Register dst, Register src) {
8389 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8390 emit_arith(0x0B, 0xC0, dst, src);
8391 }
8392
8393 void Assembler::popa() { // 64bit
8394 movq(r15, Address(rsp, 0));
8395 movq(r14, Address(rsp, wordSize));
8396 movq(r13, Address(rsp, 2 * wordSize));
8397 movq(r12, Address(rsp, 3 * wordSize));
8398 movq(r11, Address(rsp, 4 * wordSize));
8399 movq(r10, Address(rsp, 5 * wordSize));
8400 movq(r9, Address(rsp, 6 * wordSize));
8401 movq(r8, Address(rsp, 7 * wordSize));
8402 movq(rdi, Address(rsp, 8 * wordSize));
8403 movq(rsi, Address(rsp, 9 * wordSize));
8404 movq(rbp, Address(rsp, 10 * wordSize));
8405 // skip rsp
8406 movq(rbx, Address(rsp, 12 * wordSize));
8407 movq(rdx, Address(rsp, 13 * wordSize));
8408 movq(rcx, Address(rsp, 14 * wordSize));
8409 movq(rax, Address(rsp, 15 * wordSize));
8410
8411 addq(rsp, 16 * wordSize);
8412 }
8413
8414 void Assembler::popcntq(Register dst, Address src) {
8415 assert(VM_Version::supports_popcnt(), "must support");
8416 InstructionMark im(this);
8417 emit_int8((unsigned char)0xF3);
8418 prefixq(src, dst);
8419 emit_int8((unsigned char)0x0F);
8420 emit_int8((unsigned char)0xB8);
8421 emit_operand(dst, src);
8422 }
8423
8424 void Assembler::popcntq(Register dst, Register src) {
8425 assert(VM_Version::supports_popcnt(), "must support");
8426 emit_int8((unsigned char)0xF3);
8427 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8428 emit_int8((unsigned char)0x0F);
8429 emit_int8((unsigned char)0xB8);
8430 emit_int8((unsigned char)(0xC0 | encode));
8431 }
8432
8433 void Assembler::popq(Address dst) {
8434 InstructionMark im(this);
8435 prefixq(dst);
8436 emit_int8((unsigned char)0x8F);
8437 emit_operand(rax, dst);
8438 }
8439
8440 void Assembler::pusha() { // 64bit
8441 // we have to store original rsp. ABI says that 128 bytes
8442 // below rsp are local scratch.
8443 movq(Address(rsp, -5 * wordSize), rsp);
8444
8445 subq(rsp, 16 * wordSize);
8446
8447 movq(Address(rsp, 15 * wordSize), rax);
8448 movq(Address(rsp, 14 * wordSize), rcx);
8449 movq(Address(rsp, 13 * wordSize), rdx);
8450 movq(Address(rsp, 12 * wordSize), rbx);
8451 // skip rsp
8452 movq(Address(rsp, 10 * wordSize), rbp);
8453 movq(Address(rsp, 9 * wordSize), rsi);
8454 movq(Address(rsp, 8 * wordSize), rdi);
8455 movq(Address(rsp, 7 * wordSize), r8);
8456 movq(Address(rsp, 6 * wordSize), r9);
8457 movq(Address(rsp, 5 * wordSize), r10);
8458 movq(Address(rsp, 4 * wordSize), r11);
8459 movq(Address(rsp, 3 * wordSize), r12);
8460 movq(Address(rsp, 2 * wordSize), r13);
8461 movq(Address(rsp, wordSize), r14);
8462 movq(Address(rsp, 0), r15);
8463 }
8464
8465 void Assembler::pushq(Address src) {
8466 InstructionMark im(this);
8467 prefixq(src);
8468 emit_int8((unsigned char)0xFF);
8469 emit_operand(rsi, src);
8470 }
8471
8472 void Assembler::rclq(Register dst, int imm8) {
8473 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8474 int encode = prefixq_and_encode(dst->encoding());
8475 if (imm8 == 1) {
8476 emit_int8((unsigned char)0xD1);
8477 emit_int8((unsigned char)(0xD0 | encode));
8478 } else {
8479 emit_int8((unsigned char)0xC1);
8480 emit_int8((unsigned char)(0xD0 | encode));
8481 emit_int8(imm8);
8482 }
8483 }
8484
8485 void Assembler::rcrq(Register dst, int imm8) {
8486 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8487 int encode = prefixq_and_encode(dst->encoding());
8488 if (imm8 == 1) {
8489 emit_int8((unsigned char)0xD1);
8490 emit_int8((unsigned char)(0xD8 | encode));
8491 } else {
8492 emit_int8((unsigned char)0xC1);
8493 emit_int8((unsigned char)(0xD8 | encode));
8494 emit_int8(imm8);
8495 }
8496 }
8497
8498 void Assembler::rorq(Register dst, int imm8) {
8499 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8500 int encode = prefixq_and_encode(dst->encoding());
8501 if (imm8 == 1) {
8502 emit_int8((unsigned char)0xD1);
8503 emit_int8((unsigned char)(0xC8 | encode));
8504 } else {
8505 emit_int8((unsigned char)0xC1);
8506 emit_int8((unsigned char)(0xc8 | encode));
8507 emit_int8(imm8);
8508 }
8509 }
8510
8511 void Assembler::rorxq(Register dst, Register src, int imm8) {
8512 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8513 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8514 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8515 emit_int8((unsigned char)0xF0);
8516 emit_int8((unsigned char)(0xC0 | encode));
8517 emit_int8(imm8);
8518 }
8519
8520 void Assembler::rorxd(Register dst, Register src, int imm8) {
8521 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8522 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8523 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8524 emit_int8((unsigned char)0xF0);
8525 emit_int8((unsigned char)(0xC0 | encode));
8526 emit_int8(imm8);
8527 }
8528
8529 void Assembler::sarq(Register dst, int imm8) {
8530 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8531 int encode = prefixq_and_encode(dst->encoding());
8532 if (imm8 == 1) {
8533 emit_int8((unsigned char)0xD1);
8534 emit_int8((unsigned char)(0xF8 | encode));
8535 } else {
8536 emit_int8((unsigned char)0xC1);
8537 emit_int8((unsigned char)(0xF8 | encode));
8538 emit_int8(imm8);
8539 }
8540 }
8541
8542 void Assembler::sarq(Register dst) {
8543 int encode = prefixq_and_encode(dst->encoding());
8544 emit_int8((unsigned char)0xD3);
8545 emit_int8((unsigned char)(0xF8 | encode));
8546 }
8547
8548 void Assembler::sbbq(Address dst, int32_t imm32) {
8549 InstructionMark im(this);
8550 prefixq(dst);
8551 emit_arith_operand(0x81, rbx, dst, imm32);
8552 }
8553
8554 void Assembler::sbbq(Register dst, int32_t imm32) {
8555 (void) prefixq_and_encode(dst->encoding());
8556 emit_arith(0x81, 0xD8, dst, imm32);
8557 }
8558
8559 void Assembler::sbbq(Register dst, Address src) {
8560 InstructionMark im(this);
8561 prefixq(src, dst);
8562 emit_int8(0x1B);
8563 emit_operand(dst, src);
8564 }
8565
8566 void Assembler::sbbq(Register dst, Register src) {
8567 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8568 emit_arith(0x1B, 0xC0, dst, src);
8569 }
8570
8571 void Assembler::shlq(Register dst, int imm8) {
8572 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8573 int encode = prefixq_and_encode(dst->encoding());
8574 if (imm8 == 1) {
8575 emit_int8((unsigned char)0xD1);
8576 emit_int8((unsigned char)(0xE0 | encode));
8577 } else {
8578 emit_int8((unsigned char)0xC1);
8579 emit_int8((unsigned char)(0xE0 | encode));
8580 emit_int8(imm8);
8581 }
8582 }
8583
8584 void Assembler::shlq(Register dst) {
8585 int encode = prefixq_and_encode(dst->encoding());
8586 emit_int8((unsigned char)0xD3);
8587 emit_int8((unsigned char)(0xE0 | encode));
8588 }
8589
8590 void Assembler::shrq(Register dst, int imm8) {
8591 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8592 int encode = prefixq_and_encode(dst->encoding());
8593 emit_int8((unsigned char)0xC1);
8594 emit_int8((unsigned char)(0xE8 | encode));
8595 emit_int8(imm8);
8596 }
8597
8598 void Assembler::shrq(Register dst) {
8599 int encode = prefixq_and_encode(dst->encoding());
8600 emit_int8((unsigned char)0xD3);
8601 emit_int8(0xE8 | encode);
8602 }
8603
8604 void Assembler::subq(Address dst, int32_t imm32) {
8605 InstructionMark im(this);
8606 prefixq(dst);
8607 emit_arith_operand(0x81, rbp, dst, imm32);
8608 }
8609
8610 void Assembler::subq(Address dst, Register src) {
8611 InstructionMark im(this);
8612 prefixq(dst, src);
8613 emit_int8(0x29);
8614 emit_operand(src, dst);
8615 }
8616
8617 void Assembler::subq(Register dst, int32_t imm32) {
8618 (void) prefixq_and_encode(dst->encoding());
8619 emit_arith(0x81, 0xE8, dst, imm32);
8620 }
8621
8622 // Force generation of a 4 byte immediate value even if it fits into 8bit
8623 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8624 (void) prefixq_and_encode(dst->encoding());
8625 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8626 }
8627
8628 void Assembler::subq(Register dst, Address src) {
8629 InstructionMark im(this);
8630 prefixq(src, dst);
8631 emit_int8(0x2B);
8632 emit_operand(dst, src);
8633 }
8634
8635 void Assembler::subq(Register dst, Register src) {
8636 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8637 emit_arith(0x2B, 0xC0, dst, src);
8638 }
8639
8640 void Assembler::testq(Register dst, int32_t imm32) {
8641 // not using emit_arith because test
8642 // doesn't support sign-extension of
8643 // 8bit operands
8644 int encode = dst->encoding();
8645 if (encode == 0) {
8646 prefix(REX_W);
8647 emit_int8((unsigned char)0xA9);
8648 } else {
8649 encode = prefixq_and_encode(encode);
8650 emit_int8((unsigned char)0xF7);
8651 emit_int8((unsigned char)(0xC0 | encode));
8652 }
8653 emit_int32(imm32);
8654 }
8655
8656 void Assembler::testq(Register dst, Register src) {
8657 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8658 emit_arith(0x85, 0xC0, dst, src);
8659 }
8660
8661 void Assembler::xaddq(Address dst, Register src) {
8662 InstructionMark im(this);
8663 prefixq(dst, src);
8664 emit_int8(0x0F);
8665 emit_int8((unsigned char)0xC1);
8666 emit_operand(src, dst);
8667 }
8668
8669 void Assembler::xchgq(Register dst, Address src) {
8670 InstructionMark im(this);
8671 prefixq(src, dst);
8672 emit_int8((unsigned char)0x87);
8673 emit_operand(dst, src);
8674 }
8675
8676 void Assembler::xchgq(Register dst, Register src) {
8677 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8678 emit_int8((unsigned char)0x87);
8679 emit_int8((unsigned char)(0xc0 | encode));
8680 }
8681
8682 void Assembler::xorq(Register dst, Register src) {
8683 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8684 emit_arith(0x33, 0xC0, dst, src);
8685 }
8686
8687 void Assembler::xorq(Register dst, Address src) {
8688 InstructionMark im(this);
8689 prefixq(src, dst);
8690 emit_int8(0x33);
8691 emit_operand(dst, src);
8692 }
8693
8694 #endif // !LP64