1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 attributes.set_rex_vex_w_reverted();
1244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1245 emit_int8(0x58);
1246 emit_int8((unsigned char)(0xC0 | encode));
1247 }
1248
1249 void Assembler::addsd(XMMRegister dst, Address src) {
1250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1251 InstructionMark im(this);
1252 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1253 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1254 attributes.set_rex_vex_w_reverted();
1255 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1256 emit_int8(0x58);
1257 emit_operand(dst, src);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1264 emit_int8(0x58);
1265 emit_int8((unsigned char)(0xC0 | encode));
1266 }
1267
1268 void Assembler::addss(XMMRegister dst, Address src) {
1269 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1270 InstructionMark im(this);
1271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1272 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1273 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1274 emit_int8(0x58);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, Address src) {
1279 assert(VM_Version::supports_aes(), "");
1280 InstructionMark im(this);
1281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1282 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1283 emit_int8((unsigned char)0xDE);
1284 emit_operand(dst, src);
1285 }
1286
1287 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1288 assert(VM_Version::supports_aes(), "");
1289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1291 emit_int8((unsigned char)0xDE);
1292 emit_int8(0xC0 | encode);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1296 assert(VM_Version::supports_aes(), "");
1297 InstructionMark im(this);
1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1300 emit_int8((unsigned char)0xDF);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1308 emit_int8((unsigned char)0xDF);
1309 emit_int8((unsigned char)(0xC0 | encode));
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDC);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDC);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, Address src) {
1330 assert(VM_Version::supports_aes(), "");
1331 InstructionMark im(this);
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDD);
1335 emit_operand(dst, src);
1336 }
1337
1338 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1342 emit_int8((unsigned char)0xDD);
1343 emit_int8((unsigned char)(0xC0 | encode));
1344 }
1345
1346 void Assembler::andl(Address dst, int32_t imm32) {
1347 InstructionMark im(this);
1348 prefix(dst);
1349 emit_int8((unsigned char)0x81);
1350 emit_operand(rsp, dst, 4);
1351 emit_int32(imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, int32_t imm32) {
1355 prefix(dst);
1356 emit_arith(0x81, 0xE0, dst, imm32);
1357 }
1358
1359 void Assembler::andl(Register dst, Address src) {
1360 InstructionMark im(this);
1361 prefix(src, dst);
1362 emit_int8(0x23);
1363 emit_operand(dst, src);
1364 }
1365
1366 void Assembler::andl(Register dst, Register src) {
1367 (void) prefix_and_encode(dst->encoding(), src->encoding());
1368 emit_arith(0x23, 0xC0, dst, src);
1369 }
1370
1371 void Assembler::andnl(Register dst, Register src1, Register src2) {
1372 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1374 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1375 emit_int8((unsigned char)0xF2);
1376 emit_int8((unsigned char)(0xC0 | encode));
1377 }
1378
1379 void Assembler::andnl(Register dst, Register src1, Address src2) {
1380 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1381 InstructionMark im(this);
1382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1383 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1384 emit_int8((unsigned char)0xF2);
1385 emit_operand(dst, src2);
1386 }
1387
1388 void Assembler::bsfl(Register dst, Register src) {
1389 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1390 emit_int8(0x0F);
1391 emit_int8((unsigned char)0xBC);
1392 emit_int8((unsigned char)(0xC0 | encode));
1393 }
1394
1395 void Assembler::bsrl(Register dst, Register src) {
1396 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1397 emit_int8(0x0F);
1398 emit_int8((unsigned char)0xBD);
1399 emit_int8((unsigned char)(0xC0 | encode));
1400 }
1401
1402 void Assembler::bswapl(Register reg) { // bswap
1403 int encode = prefix_and_encode(reg->encoding());
1404 emit_int8(0x0F);
1405 emit_int8((unsigned char)(0xC8 | encode));
1406 }
1407
1408 void Assembler::blsil(Register dst, Register src) {
1409 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1410 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1411 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1412 emit_int8((unsigned char)0xF3);
1413 emit_int8((unsigned char)(0xC0 | encode));
1414 }
1415
1416 void Assembler::blsil(Register dst, Address src) {
1417 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1418 InstructionMark im(this);
1419 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1420 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1421 emit_int8((unsigned char)0xF3);
1422 emit_operand(rbx, src);
1423 }
1424
1425 void Assembler::blsmskl(Register dst, Register src) {
1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1428 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1429 emit_int8((unsigned char)0xF3);
1430 emit_int8((unsigned char)(0xC0 | encode));
1431 }
1432
1433 void Assembler::blsmskl(Register dst, Address src) {
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 InstructionMark im(this);
1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1437 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rdx, src);
1440 }
1441
1442 void Assembler::blsrl(Register dst, Register src) {
1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1445 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1446 emit_int8((unsigned char)0xF3);
1447 emit_int8((unsigned char)(0xC0 | encode));
1448 }
1449
1450 void Assembler::blsrl(Register dst, Address src) {
1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1452 InstructionMark im(this);
1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1454 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1455 emit_int8((unsigned char)0xF3);
1456 emit_operand(rcx, src);
1457 }
1458
1459 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1460 // suspect disp32 is always good
1461 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1462
1463 if (L.is_bound()) {
1464 const int long_size = 5;
1465 int offs = (int)( target(L) - pc() );
1466 assert(offs <= 0, "assembler error");
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 emit_int8((unsigned char)0xE8);
1470 emit_data(offs - long_size, rtype, operand);
1471 } else {
1472 InstructionMark im(this);
1473 // 1110 1000 #32-bit disp
1474 L.add_patch_at(code(), locator());
1475
1476 emit_int8((unsigned char)0xE8);
1477 emit_data(int(0), rtype, operand);
1478 }
1479 }
1480
1481 void Assembler::call(Register dst) {
1482 int encode = prefix_and_encode(dst->encoding());
1483 emit_int8((unsigned char)0xFF);
1484 emit_int8((unsigned char)(0xD0 | encode));
1485 }
1486
1487
1488 void Assembler::call(Address adr) {
1489 InstructionMark im(this);
1490 prefix(adr);
1491 emit_int8((unsigned char)0xFF);
1492 emit_operand(rdx, adr);
1493 }
1494
1495 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1496 assert(entry != NULL, "call most probably wrong");
1497 InstructionMark im(this);
1498 emit_int8((unsigned char)0xE8);
1499 intptr_t disp = entry - (pc() + sizeof(int32_t));
1500 assert(is_simm32(disp), "must be 32bit offset (call2)");
1501 // Technically, should use call32_operand, but this format is
1502 // implied by the fact that we're emitting a call instruction.
1503
1504 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1505 emit_data((int) disp, rspec, operand);
1506 }
1507
1508 void Assembler::cdql() {
1509 emit_int8((unsigned char)0x99);
1510 }
1511
1512 void Assembler::cld() {
1513 emit_int8((unsigned char)0xFC);
1514 }
1515
1516 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1517 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1518 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1519 emit_int8(0x0F);
1520 emit_int8(0x40 | cc);
1521 emit_int8((unsigned char)(0xC0 | encode));
1522 }
1523
1524
1525 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1526 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1527 prefix(src, dst);
1528 emit_int8(0x0F);
1529 emit_int8(0x40 | cc);
1530 emit_operand(dst, src);
1531 }
1532
1533 void Assembler::cmpb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_int8((unsigned char)0x80);
1537 emit_operand(rdi, dst, 1);
1538 emit_int8(imm8);
1539 }
1540
1541 void Assembler::cmpl(Address dst, int32_t imm32) {
1542 InstructionMark im(this);
1543 prefix(dst);
1544 emit_int8((unsigned char)0x81);
1545 emit_operand(rdi, dst, 4);
1546 emit_int32(imm32);
1547 }
1548
1549 void Assembler::cmpl(Register dst, int32_t imm32) {
1550 prefix(dst);
1551 emit_arith(0x81, 0xF8, dst, imm32);
1552 }
1553
1554 void Assembler::cmpl(Register dst, Register src) {
1555 (void) prefix_and_encode(dst->encoding(), src->encoding());
1556 emit_arith(0x3B, 0xC0, dst, src);
1557 }
1558
1559 void Assembler::cmpl(Register dst, Address src) {
1560 InstructionMark im(this);
1561 prefix(src, dst);
1562 emit_int8((unsigned char)0x3B);
1563 emit_operand(dst, src);
1564 }
1565
1566 void Assembler::cmpw(Address dst, int imm16) {
1567 InstructionMark im(this);
1568 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1569 emit_int8(0x66);
1570 emit_int8((unsigned char)0x81);
1571 emit_operand(rdi, dst, 2);
1572 emit_int16(imm16);
1573 }
1574
1575 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1576 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1577 // The ZF is set if the compared values were equal, and cleared otherwise.
1578 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1579 InstructionMark im(this);
1580 prefix(adr, reg);
1581 emit_int8(0x0F);
1582 emit_int8((unsigned char)0xB1);
1583 emit_operand(reg, adr);
1584 }
1585
1586 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1587 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1588 // The ZF is set if the compared values were equal, and cleared otherwise.
1589 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1590 InstructionMark im(this);
1591 prefix(adr, reg, true);
1592 emit_int8(0x0F);
1593 emit_int8((unsigned char)0xB0);
1594 emit_operand(reg, adr);
1595 }
1596
1597 void Assembler::comisd(XMMRegister dst, Address src) {
1598 // NOTE: dbx seems to decode this as comiss even though the
1599 // 0x66 is there. Strangly ucomisd comes out correct
1600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1601 InstructionMark im(this);
1602 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1604 attributes.set_rex_vex_w_reverted();
1605 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1606 emit_int8(0x2F);
1607 emit_operand(dst, src);
1608 }
1609
1610 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1613 attributes.set_rex_vex_w_reverted();
1614 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1615 emit_int8(0x2F);
1616 emit_int8((unsigned char)(0xC0 | encode));
1617 }
1618
1619 void Assembler::comiss(XMMRegister dst, Address src) {
1620 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1621 InstructionMark im(this);
1622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1623 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1624 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1625 emit_int8(0x2F);
1626 emit_operand(dst, src);
1627 }
1628
1629 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1632 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1633 emit_int8(0x2F);
1634 emit_int8((unsigned char)(0xC0 | encode));
1635 }
1636
1637 void Assembler::cpuid() {
1638 emit_int8(0x0F);
1639 emit_int8((unsigned char)0xA2);
1640 }
1641
1642 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1643 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1644 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1645 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1646 //
1647 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1648 //
1649 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1650 //
1651 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1652 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1653 assert(VM_Version::supports_sse4_2(), "");
1654 int8_t w = 0x01;
1655 Prefix p = Prefix_EMPTY;
1656
1657 emit_int8((int8_t)0xF2);
1658 switch (sizeInBytes) {
1659 case 1:
1660 w = 0;
1661 break;
1662 case 2:
1663 case 4:
1664 break;
1665 LP64_ONLY(case 8:)
1666 // This instruction is not valid in 32 bits
1667 // Note:
1668 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1669 //
1670 // Page B - 72 Vol. 2C says
1671 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1672 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1673 // F0!!!
1674 // while 3 - 208 Vol. 2A
1675 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1676 //
1677 // the 0 on a last bit is reserved for a different flavor of this instruction :
1678 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1679 p = REX_W;
1680 break;
1681 default:
1682 assert(0, "Unsupported value for a sizeInBytes argument");
1683 break;
1684 }
1685 LP64_ONLY(prefix(crc, v, p);)
1686 emit_int8((int8_t)0x0F);
1687 emit_int8(0x38);
1688 emit_int8((int8_t)(0xF0 | w));
1689 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1690 }
1691
1692 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1693 assert(VM_Version::supports_sse4_2(), "");
1694 InstructionMark im(this);
1695 int8_t w = 0x01;
1696 Prefix p = Prefix_EMPTY;
1697
1698 emit_int8((int8_t)0xF2);
1699 switch (sizeInBytes) {
1700 case 1:
1701 w = 0;
1702 break;
1703 case 2:
1704 case 4:
1705 break;
1706 LP64_ONLY(case 8:)
1707 // This instruction is not valid in 32 bits
1708 p = REX_W;
1709 break;
1710 default:
1711 assert(0, "Unsupported value for a sizeInBytes argument");
1712 break;
1713 }
1714 LP64_ONLY(prefix(crc, adr, p);)
1715 emit_int8((int8_t)0x0F);
1716 emit_int8(0x38);
1717 emit_int8((int8_t)(0xF0 | w));
1718 emit_operand(crc, adr);
1719 }
1720
1721 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1724 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1725 emit_int8((unsigned char)0xE6);
1726 emit_int8((unsigned char)(0xC0 | encode));
1727 }
1728
1729 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1731 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1732 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1733 emit_int8(0x5B);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1740 attributes.set_rex_vex_w_reverted();
1741 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1742 emit_int8(0x5A);
1743 emit_int8((unsigned char)(0xC0 | encode));
1744 }
1745
1746 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 InstructionMark im(this);
1749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1751 attributes.set_rex_vex_w_reverted();
1752 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x5A);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1761 emit_int8(0x2A);
1762 emit_int8((unsigned char)(0xC0 | encode));
1763 }
1764
1765 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 InstructionMark im(this);
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1770 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_operand(dst, src);
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1779 emit_int8(0x2A);
1780 emit_int8((unsigned char)(0xC0 | encode));
1781 }
1782
1783 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1784 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1785 InstructionMark im(this);
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1788 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_operand(dst, src);
1791 }
1792
1793 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x2A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_int8((unsigned char)(0xC0 | encode));
1807 }
1808
1809 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionMark im(this);
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1813 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1814 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x5A);
1816 emit_operand(dst, src);
1817 }
1818
1819
1820 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2C);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1839 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1840 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1841 emit_int8((unsigned char)0xE6);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::decl(Address dst) {
1846 // Don't use it directly. Use MacroAssembler::decrement() instead.
1847 InstructionMark im(this);
1848 prefix(dst);
1849 emit_int8((unsigned char)0xFF);
1850 emit_operand(rcx, dst);
1851 }
1852
1853 void Assembler::divsd(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1858 attributes.set_rex_vex_w_reverted();
1859 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 attributes.set_rex_vex_w_reverted();
1868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1869 emit_int8(0x5E);
1870 emit_int8((unsigned char)(0xC0 | encode));
1871 }
1872
1873 void Assembler::divss(XMMRegister dst, Address src) {
1874 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1875 InstructionMark im(this);
1876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1878 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879 emit_int8(0x5E);
1880 emit_operand(dst, src);
1881 }
1882
1883 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1884 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1886 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1887 emit_int8(0x5E);
1888 emit_int8((unsigned char)(0xC0 | encode));
1889 }
1890
1891 void Assembler::emms() {
1892 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1893 emit_int8(0x0F);
1894 emit_int8(0x77);
1895 }
1896
1897 void Assembler::hlt() {
1898 emit_int8((unsigned char)0xF4);
1899 }
1900
1901 void Assembler::idivl(Register src) {
1902 int encode = prefix_and_encode(src->encoding());
1903 emit_int8((unsigned char)0xF7);
1904 emit_int8((unsigned char)(0xF8 | encode));
1905 }
1906
1907 void Assembler::divl(Register src) { // Unsigned
1908 int encode = prefix_and_encode(src->encoding());
1909 emit_int8((unsigned char)0xF7);
1910 emit_int8((unsigned char)(0xF0 | encode));
1911 }
1912
1913 void Assembler::imull(Register src) {
1914 int encode = prefix_and_encode(src->encoding());
1915 emit_int8((unsigned char)0xF7);
1916 emit_int8((unsigned char)(0xE8 | encode));
1917 }
1918
1919 void Assembler::imull(Register dst, Register src) {
1920 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921 emit_int8(0x0F);
1922 emit_int8((unsigned char)0xAF);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926
1927 void Assembler::imull(Register dst, Register src, int value) {
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 if (is8bit(value)) {
1930 emit_int8(0x6B);
1931 emit_int8((unsigned char)(0xC0 | encode));
1932 emit_int8(value & 0xFF);
1933 } else {
1934 emit_int8(0x69);
1935 emit_int8((unsigned char)(0xC0 | encode));
1936 emit_int32(value);
1937 }
1938 }
1939
1940 void Assembler::imull(Register dst, Address src) {
1941 InstructionMark im(this);
1942 prefix(src, dst);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char) 0xAF);
1945 emit_operand(dst, src);
1946 }
1947
1948
1949 void Assembler::incl(Address dst) {
1950 // Don't use it directly. Use MacroAssembler::increment() instead.
1951 InstructionMark im(this);
1952 prefix(dst);
1953 emit_int8((unsigned char)0xFF);
1954 emit_operand(rax, dst);
1955 }
1956
1957 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1958 InstructionMark im(this);
1959 assert((0 <= cc) && (cc < 16), "illegal cc");
1960 if (L.is_bound()) {
1961 address dst = target(L);
1962 assert(dst != NULL, "jcc most probably wrong");
1963
1964 const int short_size = 2;
1965 const int long_size = 6;
1966 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1967 if (maybe_short && is8bit(offs - short_size)) {
1968 // 0111 tttn #8-bit disp
1969 emit_int8(0x70 | cc);
1970 emit_int8((offs - short_size) & 0xFF);
1971 } else {
1972 // 0000 1111 1000 tttn #32-bit disp
1973 assert(is_simm32(offs - long_size),
1974 "must be 32bit offset (call4)");
1975 emit_int8(0x0F);
1976 emit_int8((unsigned char)(0x80 | cc));
1977 emit_int32(offs - long_size);
1978 }
1979 } else {
1980 // Note: could eliminate cond. jumps to this jump if condition
1981 // is the same however, seems to be rather unlikely case.
1982 // Note: use jccb() if label to be bound is very close to get
1983 // an 8-bit displacement
1984 L.add_patch_at(code(), locator());
1985 emit_int8(0x0F);
1986 emit_int8((unsigned char)(0x80 | cc));
1987 emit_int32(0);
1988 }
1989 }
1990
1991 void Assembler::jccb(Condition cc, Label& L) {
1992 if (L.is_bound()) {
1993 const int short_size = 2;
1994 address entry = target(L);
1995 #ifdef ASSERT
1996 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1997 intptr_t delta = short_branch_delta();
1998 if (delta != 0) {
1999 dist += (dist < 0 ? (-delta) :delta);
2000 }
2001 assert(is8bit(dist), "Dispacement too large for a short jmp");
2002 #endif
2003 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2004 // 0111 tttn #8-bit disp
2005 emit_int8(0x70 | cc);
2006 emit_int8((offs - short_size) & 0xFF);
2007 } else {
2008 InstructionMark im(this);
2009 L.add_patch_at(code(), locator());
2010 emit_int8(0x70 | cc);
2011 emit_int8(0);
2012 }
2013 }
2014
2015 void Assembler::jmp(Address adr) {
2016 InstructionMark im(this);
2017 prefix(adr);
2018 emit_int8((unsigned char)0xFF);
2019 emit_operand(rsp, adr);
2020 }
2021
2022 void Assembler::jmp(Label& L, bool maybe_short) {
2023 if (L.is_bound()) {
2024 address entry = target(L);
2025 assert(entry != NULL, "jmp most probably wrong");
2026 InstructionMark im(this);
2027 const int short_size = 2;
2028 const int long_size = 5;
2029 intptr_t offs = entry - pc();
2030 if (maybe_short && is8bit(offs - short_size)) {
2031 emit_int8((unsigned char)0xEB);
2032 emit_int8((offs - short_size) & 0xFF);
2033 } else {
2034 emit_int8((unsigned char)0xE9);
2035 emit_int32(offs - long_size);
2036 }
2037 } else {
2038 // By default, forward jumps are always 32-bit displacements, since
2039 // we can't yet know where the label will be bound. If you're sure that
2040 // the forward jump will not run beyond 256 bytes, use jmpb to
2041 // force an 8-bit displacement.
2042 InstructionMark im(this);
2043 L.add_patch_at(code(), locator());
2044 emit_int8((unsigned char)0xE9);
2045 emit_int32(0);
2046 }
2047 }
2048
2049 void Assembler::jmp(Register entry) {
2050 int encode = prefix_and_encode(entry->encoding());
2051 emit_int8((unsigned char)0xFF);
2052 emit_int8((unsigned char)(0xE0 | encode));
2053 }
2054
2055 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2056 InstructionMark im(this);
2057 emit_int8((unsigned char)0xE9);
2058 assert(dest != NULL, "must have a target");
2059 intptr_t disp = dest - (pc() + sizeof(int32_t));
2060 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2061 emit_data(disp, rspec.reloc(), call32_operand);
2062 }
2063
2064 void Assembler::jmpb(Label& L) {
2065 if (L.is_bound()) {
2066 const int short_size = 2;
2067 address entry = target(L);
2068 assert(entry != NULL, "jmp most probably wrong");
2069 #ifdef ASSERT
2070 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2071 intptr_t delta = short_branch_delta();
2072 if (delta != 0) {
2073 dist += (dist < 0 ? (-delta) :delta);
2074 }
2075 assert(is8bit(dist), "Dispacement too large for a short jmp");
2076 #endif
2077 intptr_t offs = entry - pc();
2078 emit_int8((unsigned char)0xEB);
2079 emit_int8((offs - short_size) & 0xFF);
2080 } else {
2081 InstructionMark im(this);
2082 L.add_patch_at(code(), locator());
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8(0);
2085 }
2086 }
2087
2088 void Assembler::ldmxcsr( Address src) {
2089 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2090 InstructionMark im(this);
2091 prefix(src);
2092 emit_int8(0x0F);
2093 emit_int8((unsigned char)0xAE);
2094 emit_operand(as_Register(2), src);
2095 }
2096
2097 void Assembler::leal(Register dst, Address src) {
2098 InstructionMark im(this);
2099 #ifdef _LP64
2100 emit_int8(0x67); // addr32
2101 prefix(src, dst);
2102 #endif // LP64
2103 emit_int8((unsigned char)0x8D);
2104 emit_operand(dst, src);
2105 }
2106
2107 void Assembler::lfence() {
2108 emit_int8(0x0F);
2109 emit_int8((unsigned char)0xAE);
2110 emit_int8((unsigned char)0xE8);
2111 }
2112
2113 void Assembler::lock() {
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::lzcntl(Register dst, Register src) {
2118 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2119 emit_int8((unsigned char)0xF3);
2120 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2121 emit_int8(0x0F);
2122 emit_int8((unsigned char)0xBD);
2123 emit_int8((unsigned char)(0xC0 | encode));
2124 }
2125
2126 // Emit mfence instruction
2127 void Assembler::mfence() {
2128 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2129 emit_int8(0x0F);
2130 emit_int8((unsigned char)0xAE);
2131 emit_int8((unsigned char)0xF0);
2132 }
2133
2134 void Assembler::mov(Register dst, Register src) {
2135 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2136 }
2137
2138 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2140 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2141 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2142 attributes.set_rex_vex_w_reverted();
2143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2144 emit_int8(0x28);
2145 emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147
2148 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2151 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2152 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2153 emit_int8(0x28);
2154 emit_int8((unsigned char)(0xC0 | encode));
2155 }
2156
2157 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2158 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2160 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2161 emit_int8(0x16);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 void Assembler::movb(Register dst, Address src) {
2166 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2167 InstructionMark im(this);
2168 prefix(src, dst, true);
2169 emit_int8((unsigned char)0x8A);
2170 emit_operand(dst, src);
2171 }
2172
2173 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2174 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2175 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2176 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2177 attributes.set_rex_vex_w_reverted();
2178 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2179 emit_int8(0x12);
2180 emit_int8(0xC0 | encode);
2181 }
2182
2183 void Assembler::kmovbl(KRegister dst, Register src) {
2184 assert(VM_Version::supports_avx512dq(), "");
2185 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2186 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2187 emit_int8((unsigned char)0x92);
2188 emit_int8((unsigned char)(0xC0 | encode));
2189 }
2190
2191 void Assembler::kmovbl(Register dst, KRegister src) {
2192 assert(VM_Version::supports_avx512dq(), "");
2193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2194 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2195 emit_int8((unsigned char)0x93);
2196 emit_int8((unsigned char)(0xC0 | encode));
2197 }
2198
2199 void Assembler::kmovwl(KRegister dst, Register src) {
2200 assert(VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::kmovwl(Register dst, KRegister src) {
2208 assert(VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2211 emit_int8((unsigned char)0x93);
2212 emit_int8((unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::kmovwl(KRegister dst, Address src) {
2216 assert(VM_Version::supports_evex(), "");
2217 InstructionMark im(this);
2218 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2219 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2220 emit_int8((unsigned char)0x90);
2221 emit_operand((Register)dst, src);
2222 }
2223
2224 void Assembler::kmovdl(KRegister dst, Register src) {
2225 assert(VM_Version::supports_avx512bw(), "");
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x92);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::kmovdl(Register dst, KRegister src) {
2233 assert(VM_Version::supports_avx512bw(), "");
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2236 emit_int8((unsigned char)0x93);
2237 emit_int8((unsigned char)(0xC0 | encode));
2238 }
2239
2240 void Assembler::kmovql(KRegister dst, KRegister src) {
2241 assert(VM_Version::supports_avx512bw(), "");
2242 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2243 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int8((unsigned char)0x90);
2245 emit_int8((unsigned char)(0xC0 | encode));
2246 }
2247
2248 void Assembler::kmovql(KRegister dst, Address src) {
2249 assert(VM_Version::supports_avx512bw(), "");
2250 InstructionMark im(this);
2251 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2252 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2253 emit_int8((unsigned char)0x90);
2254 emit_operand((Register)dst, src);
2255 }
2256
2257 void Assembler::kmovql(Address dst, KRegister src) {
2258 assert(VM_Version::supports_avx512bw(), "");
2259 InstructionMark im(this);
2260 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2261 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2262 emit_int8((unsigned char)0x90);
2263 emit_operand((Register)src, dst);
2264 }
2265
2266 void Assembler::kmovql(KRegister dst, Register src) {
2267 assert(VM_Version::supports_avx512bw(), "");
2268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2269 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2270 emit_int8((unsigned char)0x92);
2271 emit_int8((unsigned char)(0xC0 | encode));
2272 }
2273
2274 void Assembler::kmovql(Register dst, KRegister src) {
2275 assert(VM_Version::supports_avx512bw(), "");
2276 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2277 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2278 emit_int8((unsigned char)0x93);
2279 emit_int8((unsigned char)(0xC0 | encode));
2280 }
2281
2282 void Assembler::knotwl(KRegister dst, KRegister src) {
2283 assert(VM_Version::supports_evex(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x44);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2292 assert(VM_Version::supports_avx512dq(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x98);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 // This instruction produces ZF or CF flags
2300 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2301 assert(VM_Version::supports_evex(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x98);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 // This instruction produces ZF or CF flags
2327 void Assembler::ktestql(KRegister src1, KRegister src2) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x99);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::movb(Address dst, int imm8) {
2336 InstructionMark im(this);
2337 prefix(dst);
2338 emit_int8((unsigned char)0xC6);
2339 emit_operand(rax, dst, 1);
2340 emit_int8(imm8);
2341 }
2342
2343
2344 void Assembler::movb(Address dst, Register src) {
2345 assert(src->has_byte_register(), "must have byte register");
2346 InstructionMark im(this);
2347 prefix(dst, src, true);
2348 emit_int8((unsigned char)0x88);
2349 emit_operand(src, dst);
2350 }
2351
2352 void Assembler::movdl(XMMRegister dst, Register src) {
2353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2355 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2356 emit_int8(0x6E);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 void Assembler::movdl(Register dst, XMMRegister src) {
2361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2363 // swap src/dst to get correct prefix
2364 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2365 emit_int8(0x7E);
2366 emit_int8((unsigned char)(0xC0 | encode));
2367 }
2368
2369 void Assembler::movdl(XMMRegister dst, Address src) {
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 InstructionMark im(this);
2372 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2373 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2374 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2375 emit_int8(0x6E);
2376 emit_operand(dst, src);
2377 }
2378
2379 void Assembler::movdl(Address dst, XMMRegister src) {
2380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2381 InstructionMark im(this);
2382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2383 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2384 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2385 emit_int8(0x7E);
2386 emit_operand(src, dst);
2387 }
2388
2389 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2391 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2392 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2393 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2394 emit_int8(0x6F);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 }
2397
2398 void Assembler::movdqa(XMMRegister dst, Address src) {
2399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2400 InstructionMark im(this);
2401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2403 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2404 emit_int8(0x6F);
2405 emit_operand(dst, src);
2406 }
2407
2408 void Assembler::movdqu(XMMRegister dst, Address src) {
2409 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2410 InstructionMark im(this);
2411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2412 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2413 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2414 emit_int8(0x6F);
2415 emit_operand(dst, src);
2416 }
2417
2418 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2421 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2422 emit_int8(0x6F);
2423 emit_int8((unsigned char)(0xC0 | encode));
2424 }
2425
2426 void Assembler::movdqu(Address dst, XMMRegister src) {
2427 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2428 InstructionMark im(this);
2429 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2430 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2431 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x7F);
2433 emit_operand(src, dst);
2434 }
2435
2436 // Move Unaligned 256bit Vector
2437 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2438 assert(UseAVX > 0, "");
2439 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2440 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2441 emit_int8(0x6F);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2446 assert(UseAVX > 0, "");
2447 InstructionMark im(this);
2448 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2450 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x6F);
2452 emit_operand(dst, src);
2453 }
2454
2455 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2456 assert(UseAVX > 0, "");
2457 InstructionMark im(this);
2458 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2459 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2460 // swap src<->dst for encoding
2461 assert(src != xnoreg, "sanity");
2462 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2463 emit_int8(0x7F);
2464 emit_operand(src, dst);
2465 }
2466
2467 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2468 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2469 assert(VM_Version::supports_evex(), "");
2470 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2471 attributes.set_is_evex_instruction();
2472 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2473 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2474 emit_int8(0x6F);
2475 emit_int8((unsigned char)(0xC0 | encode));
2476 }
2477
2478 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2479 assert(VM_Version::supports_evex(), "");
2480 InstructionMark im(this);
2481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2482 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2483 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2484 attributes.set_is_evex_instruction();
2485 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2486 emit_int8(0x6F);
2487 emit_operand(dst, src);
2488 }
2489
2490 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2491 assert(VM_Version::supports_evex(), "");
2492 assert(src != xnoreg, "sanity");
2493 InstructionMark im(this);
2494 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2495 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2496 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2497 attributes.set_is_evex_instruction();
2498 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2499 emit_int8(0x7F);
2500 emit_operand(src, dst);
2501 }
2502
2503 void Assembler::evmovdqub(KRegister mask, bool zeroing, XMMRegister dst, Address src, int vector_len) {
2504 assert(VM_Version::supports_avx512vlbw(), "");
2505 assert(is_programmed_mask_reg(), "");
2506 InstructionMark im(this);
2507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2508 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2509 attributes.set_embedded_opmask_register_specifier(mask);
2510 if (zeroing) attributes.set_is_clear_context();
2511 attributes.set_is_evex_instruction();
2512 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2513 emit_int8(0x6F);
2514 emit_operand(dst, src);
2515 }
2516
2517 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2518 assert(VM_Version::supports_evex(), "");
2519 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2520 attributes.set_is_evex_instruction();
2521 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2522 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2523 emit_int8(0x6F);
2524 emit_int8((unsigned char)(0xC0 | encode));
2525 }
2526
2527 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2528 assert(VM_Version::supports_evex(), "");
2529 InstructionMark im(this);
2530 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2531 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2532 attributes.set_is_evex_instruction();
2533 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2534 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2535 emit_int8(0x6F);
2536 emit_operand(dst, src);
2537 }
2538
2539 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2540 assert(VM_Version::supports_evex(), "");
2541 assert(src != xnoreg, "sanity");
2542 InstructionMark im(this);
2543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2544 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2545 attributes.set_is_evex_instruction();
2546 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2547 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2548 emit_int8(0x7F);
2549 emit_operand(src, dst);
2550 }
2551
2552 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2553 assert(VM_Version::supports_evex(), "");
2554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2555 attributes.set_is_evex_instruction();
2556 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2557 emit_int8(0x6F);
2558 emit_int8((unsigned char)(0xC0 | encode));
2559 }
2560
2561 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2562 assert(VM_Version::supports_evex(), "");
2563 InstructionMark im(this);
2564 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2565 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2566 attributes.set_is_evex_instruction();
2567 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2568 emit_int8(0x6F);
2569 emit_operand(dst, src);
2570 }
2571
2572 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2573 assert(VM_Version::supports_evex(), "");
2574 assert(src != xnoreg, "sanity");
2575 InstructionMark im(this);
2576 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2577 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2578 attributes.set_is_evex_instruction();
2579 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2580 emit_int8(0x7F);
2581 emit_operand(src, dst);
2582 }
2583
2584 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2585 assert(VM_Version::supports_evex(), "");
2586 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2587 attributes.set_is_evex_instruction();
2588 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2589 emit_int8(0x6F);
2590 emit_int8((unsigned char)(0xC0 | encode));
2591 }
2592
2593 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2594 assert(VM_Version::supports_evex(), "");
2595 InstructionMark im(this);
2596 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2597 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2598 attributes.set_is_evex_instruction();
2599 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2600 emit_int8(0x6F);
2601 emit_operand(dst, src);
2602 }
2603
2604 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2605 assert(VM_Version::supports_evex(), "");
2606 assert(src != xnoreg, "sanity");
2607 InstructionMark im(this);
2608 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2609 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2610 attributes.set_is_evex_instruction();
2611 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2612 emit_int8(0x7F);
2613 emit_operand(src, dst);
2614 }
2615
2616 // Uses zero extension on 64bit
2617
2618 void Assembler::movl(Register dst, int32_t imm32) {
2619 int encode = prefix_and_encode(dst->encoding());
2620 emit_int8((unsigned char)(0xB8 | encode));
2621 emit_int32(imm32);
2622 }
2623
2624 void Assembler::movl(Register dst, Register src) {
2625 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2626 emit_int8((unsigned char)0x8B);
2627 emit_int8((unsigned char)(0xC0 | encode));
2628 }
2629
2630 void Assembler::movl(Register dst, Address src) {
2631 InstructionMark im(this);
2632 prefix(src, dst);
2633 emit_int8((unsigned char)0x8B);
2634 emit_operand(dst, src);
2635 }
2636
2637 void Assembler::movl(Address dst, int32_t imm32) {
2638 InstructionMark im(this);
2639 prefix(dst);
2640 emit_int8((unsigned char)0xC7);
2641 emit_operand(rax, dst, 4);
2642 emit_int32(imm32);
2643 }
2644
2645 void Assembler::movl(Address dst, Register src) {
2646 InstructionMark im(this);
2647 prefix(dst, src);
2648 emit_int8((unsigned char)0x89);
2649 emit_operand(src, dst);
2650 }
2651
2652 // New cpus require to use movsd and movss to avoid partial register stall
2653 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2654 // The selection is done in MacroAssembler::movdbl() and movflt().
2655 void Assembler::movlpd(XMMRegister dst, Address src) {
2656 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2657 InstructionMark im(this);
2658 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2659 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2660 attributes.set_rex_vex_w_reverted();
2661 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2662 emit_int8(0x12);
2663 emit_operand(dst, src);
2664 }
2665
2666 void Assembler::movq( MMXRegister dst, Address src ) {
2667 assert( VM_Version::supports_mmx(), "" );
2668 emit_int8(0x0F);
2669 emit_int8(0x6F);
2670 emit_operand(dst, src);
2671 }
2672
2673 void Assembler::movq( Address dst, MMXRegister src ) {
2674 assert( VM_Version::supports_mmx(), "" );
2675 emit_int8(0x0F);
2676 emit_int8(0x7F);
2677 // workaround gcc (3.2.1-7a) bug
2678 // In that version of gcc with only an emit_operand(MMX, Address)
2679 // gcc will tail jump and try and reverse the parameters completely
2680 // obliterating dst in the process. By having a version available
2681 // that doesn't need to swap the args at the tail jump the bug is
2682 // avoided.
2683 emit_operand(dst, src);
2684 }
2685
2686 void Assembler::movq(XMMRegister dst, Address src) {
2687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2688 InstructionMark im(this);
2689 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2690 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2691 attributes.set_rex_vex_w_reverted();
2692 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2693 emit_int8(0x7E);
2694 emit_operand(dst, src);
2695 }
2696
2697 void Assembler::movq(Address dst, XMMRegister src) {
2698 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2699 InstructionMark im(this);
2700 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2701 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2702 attributes.set_rex_vex_w_reverted();
2703 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2704 emit_int8((unsigned char)0xD6);
2705 emit_operand(src, dst);
2706 }
2707
2708 void Assembler::movsbl(Register dst, Address src) { // movsxb
2709 InstructionMark im(this);
2710 prefix(src, dst);
2711 emit_int8(0x0F);
2712 emit_int8((unsigned char)0xBE);
2713 emit_operand(dst, src);
2714 }
2715
2716 void Assembler::movsbl(Register dst, Register src) { // movsxb
2717 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2718 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2719 emit_int8(0x0F);
2720 emit_int8((unsigned char)0xBE);
2721 emit_int8((unsigned char)(0xC0 | encode));
2722 }
2723
2724 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2726 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2727 attributes.set_rex_vex_w_reverted();
2728 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2729 emit_int8(0x10);
2730 emit_int8((unsigned char)(0xC0 | encode));
2731 }
2732
2733 void Assembler::movsd(XMMRegister dst, Address src) {
2734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2735 InstructionMark im(this);
2736 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2737 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2738 attributes.set_rex_vex_w_reverted();
2739 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2740 emit_int8(0x10);
2741 emit_operand(dst, src);
2742 }
2743
2744 void Assembler::movsd(Address dst, XMMRegister src) {
2745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2746 InstructionMark im(this);
2747 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2748 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2749 attributes.set_rex_vex_w_reverted();
2750 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2751 emit_int8(0x11);
2752 emit_operand(src, dst);
2753 }
2754
2755 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2756 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2757 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2759 emit_int8(0x10);
2760 emit_int8((unsigned char)(0xC0 | encode));
2761 }
2762
2763 void Assembler::movss(XMMRegister dst, Address src) {
2764 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2765 InstructionMark im(this);
2766 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2768 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2769 emit_int8(0x10);
2770 emit_operand(dst, src);
2771 }
2772
2773 void Assembler::movss(Address dst, XMMRegister src) {
2774 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2775 InstructionMark im(this);
2776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2777 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2778 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2779 emit_int8(0x11);
2780 emit_operand(src, dst);
2781 }
2782
2783 void Assembler::movswl(Register dst, Address src) { // movsxw
2784 InstructionMark im(this);
2785 prefix(src, dst);
2786 emit_int8(0x0F);
2787 emit_int8((unsigned char)0xBF);
2788 emit_operand(dst, src);
2789 }
2790
2791 void Assembler::movswl(Register dst, Register src) { // movsxw
2792 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2793 emit_int8(0x0F);
2794 emit_int8((unsigned char)0xBF);
2795 emit_int8((unsigned char)(0xC0 | encode));
2796 }
2797
2798 void Assembler::movw(Address dst, int imm16) {
2799 InstructionMark im(this);
2800
2801 emit_int8(0x66); // switch to 16-bit mode
2802 prefix(dst);
2803 emit_int8((unsigned char)0xC7);
2804 emit_operand(rax, dst, 2);
2805 emit_int16(imm16);
2806 }
2807
2808 void Assembler::movw(Register dst, Address src) {
2809 InstructionMark im(this);
2810 emit_int8(0x66);
2811 prefix(src, dst);
2812 emit_int8((unsigned char)0x8B);
2813 emit_operand(dst, src);
2814 }
2815
2816 void Assembler::movw(Address dst, Register src) {
2817 InstructionMark im(this);
2818 emit_int8(0x66);
2819 prefix(dst, src);
2820 emit_int8((unsigned char)0x89);
2821 emit_operand(src, dst);
2822 }
2823
2824 void Assembler::movzbl(Register dst, Address src) { // movzxb
2825 InstructionMark im(this);
2826 prefix(src, dst);
2827 emit_int8(0x0F);
2828 emit_int8((unsigned char)0xB6);
2829 emit_operand(dst, src);
2830 }
2831
2832 void Assembler::movzbl(Register dst, Register src) { // movzxb
2833 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2834 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2835 emit_int8(0x0F);
2836 emit_int8((unsigned char)0xB6);
2837 emit_int8(0xC0 | encode);
2838 }
2839
2840 void Assembler::movzwl(Register dst, Address src) { // movzxw
2841 InstructionMark im(this);
2842 prefix(src, dst);
2843 emit_int8(0x0F);
2844 emit_int8((unsigned char)0xB7);
2845 emit_operand(dst, src);
2846 }
2847
2848 void Assembler::movzwl(Register dst, Register src) { // movzxw
2849 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2850 emit_int8(0x0F);
2851 emit_int8((unsigned char)0xB7);
2852 emit_int8(0xC0 | encode);
2853 }
2854
2855 void Assembler::mull(Address src) {
2856 InstructionMark im(this);
2857 prefix(src);
2858 emit_int8((unsigned char)0xF7);
2859 emit_operand(rsp, src);
2860 }
2861
2862 void Assembler::mull(Register src) {
2863 int encode = prefix_and_encode(src->encoding());
2864 emit_int8((unsigned char)0xF7);
2865 emit_int8((unsigned char)(0xE0 | encode));
2866 }
2867
2868 void Assembler::mulsd(XMMRegister dst, Address src) {
2869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2870 InstructionMark im(this);
2871 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2872 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2873 attributes.set_rex_vex_w_reverted();
2874 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2875 emit_int8(0x59);
2876 emit_operand(dst, src);
2877 }
2878
2879 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2880 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2881 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2882 attributes.set_rex_vex_w_reverted();
2883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2884 emit_int8(0x59);
2885 emit_int8((unsigned char)(0xC0 | encode));
2886 }
2887
2888 void Assembler::mulss(XMMRegister dst, Address src) {
2889 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2890 InstructionMark im(this);
2891 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2892 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2893 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2894 emit_int8(0x59);
2895 emit_operand(dst, src);
2896 }
2897
2898 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2899 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2900 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2901 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2902 emit_int8(0x59);
2903 emit_int8((unsigned char)(0xC0 | encode));
2904 }
2905
2906 void Assembler::negl(Register dst) {
2907 int encode = prefix_and_encode(dst->encoding());
2908 emit_int8((unsigned char)0xF7);
2909 emit_int8((unsigned char)(0xD8 | encode));
2910 }
2911
2912 void Assembler::nop(int i) {
2913 #ifdef ASSERT
2914 assert(i > 0, " ");
2915 // The fancy nops aren't currently recognized by debuggers making it a
2916 // pain to disassemble code while debugging. If asserts are on clearly
2917 // speed is not an issue so simply use the single byte traditional nop
2918 // to do alignment.
2919
2920 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2921 return;
2922
2923 #endif // ASSERT
2924
2925 if (UseAddressNop && VM_Version::is_intel()) {
2926 //
2927 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2928 // 1: 0x90
2929 // 2: 0x66 0x90
2930 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2931 // 4: 0x0F 0x1F 0x40 0x00
2932 // 5: 0x0F 0x1F 0x44 0x00 0x00
2933 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2934 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2935 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2936 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2937 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2938 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2939
2940 // The rest coding is Intel specific - don't use consecutive address nops
2941
2942 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2943 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2944 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2945 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2946
2947 while(i >= 15) {
2948 // For Intel don't generate consecutive addess nops (mix with regular nops)
2949 i -= 15;
2950 emit_int8(0x66); // size prefix
2951 emit_int8(0x66); // size prefix
2952 emit_int8(0x66); // size prefix
2953 addr_nop_8();
2954 emit_int8(0x66); // size prefix
2955 emit_int8(0x66); // size prefix
2956 emit_int8(0x66); // size prefix
2957 emit_int8((unsigned char)0x90);
2958 // nop
2959 }
2960 switch (i) {
2961 case 14:
2962 emit_int8(0x66); // size prefix
2963 case 13:
2964 emit_int8(0x66); // size prefix
2965 case 12:
2966 addr_nop_8();
2967 emit_int8(0x66); // size prefix
2968 emit_int8(0x66); // size prefix
2969 emit_int8(0x66); // size prefix
2970 emit_int8((unsigned char)0x90);
2971 // nop
2972 break;
2973 case 11:
2974 emit_int8(0x66); // size prefix
2975 case 10:
2976 emit_int8(0x66); // size prefix
2977 case 9:
2978 emit_int8(0x66); // size prefix
2979 case 8:
2980 addr_nop_8();
2981 break;
2982 case 7:
2983 addr_nop_7();
2984 break;
2985 case 6:
2986 emit_int8(0x66); // size prefix
2987 case 5:
2988 addr_nop_5();
2989 break;
2990 case 4:
2991 addr_nop_4();
2992 break;
2993 case 3:
2994 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2995 emit_int8(0x66); // size prefix
2996 case 2:
2997 emit_int8(0x66); // size prefix
2998 case 1:
2999 emit_int8((unsigned char)0x90);
3000 // nop
3001 break;
3002 default:
3003 assert(i == 0, " ");
3004 }
3005 return;
3006 }
3007 if (UseAddressNop && VM_Version::is_amd()) {
3008 //
3009 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3010 // 1: 0x90
3011 // 2: 0x66 0x90
3012 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3013 // 4: 0x0F 0x1F 0x40 0x00
3014 // 5: 0x0F 0x1F 0x44 0x00 0x00
3015 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3016 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3017 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3018 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3019 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3020 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3021
3022 // The rest coding is AMD specific - use consecutive address nops
3023
3024 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3025 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3026 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3027 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3028 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3029 // Size prefixes (0x66) are added for larger sizes
3030
3031 while(i >= 22) {
3032 i -= 11;
3033 emit_int8(0x66); // size prefix
3034 emit_int8(0x66); // size prefix
3035 emit_int8(0x66); // size prefix
3036 addr_nop_8();
3037 }
3038 // Generate first nop for size between 21-12
3039 switch (i) {
3040 case 21:
3041 i -= 1;
3042 emit_int8(0x66); // size prefix
3043 case 20:
3044 case 19:
3045 i -= 1;
3046 emit_int8(0x66); // size prefix
3047 case 18:
3048 case 17:
3049 i -= 1;
3050 emit_int8(0x66); // size prefix
3051 case 16:
3052 case 15:
3053 i -= 8;
3054 addr_nop_8();
3055 break;
3056 case 14:
3057 case 13:
3058 i -= 7;
3059 addr_nop_7();
3060 break;
3061 case 12:
3062 i -= 6;
3063 emit_int8(0x66); // size prefix
3064 addr_nop_5();
3065 break;
3066 default:
3067 assert(i < 12, " ");
3068 }
3069
3070 // Generate second nop for size between 11-1
3071 switch (i) {
3072 case 11:
3073 emit_int8(0x66); // size prefix
3074 case 10:
3075 emit_int8(0x66); // size prefix
3076 case 9:
3077 emit_int8(0x66); // size prefix
3078 case 8:
3079 addr_nop_8();
3080 break;
3081 case 7:
3082 addr_nop_7();
3083 break;
3084 case 6:
3085 emit_int8(0x66); // size prefix
3086 case 5:
3087 addr_nop_5();
3088 break;
3089 case 4:
3090 addr_nop_4();
3091 break;
3092 case 3:
3093 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3094 emit_int8(0x66); // size prefix
3095 case 2:
3096 emit_int8(0x66); // size prefix
3097 case 1:
3098 emit_int8((unsigned char)0x90);
3099 // nop
3100 break;
3101 default:
3102 assert(i == 0, " ");
3103 }
3104 return;
3105 }
3106
3107 // Using nops with size prefixes "0x66 0x90".
3108 // From AMD Optimization Guide:
3109 // 1: 0x90
3110 // 2: 0x66 0x90
3111 // 3: 0x66 0x66 0x90
3112 // 4: 0x66 0x66 0x66 0x90
3113 // 5: 0x66 0x66 0x90 0x66 0x90
3114 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3115 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3116 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3117 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3118 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3119 //
3120 while(i > 12) {
3121 i -= 4;
3122 emit_int8(0x66); // size prefix
3123 emit_int8(0x66);
3124 emit_int8(0x66);
3125 emit_int8((unsigned char)0x90);
3126 // nop
3127 }
3128 // 1 - 12 nops
3129 if(i > 8) {
3130 if(i > 9) {
3131 i -= 1;
3132 emit_int8(0x66);
3133 }
3134 i -= 3;
3135 emit_int8(0x66);
3136 emit_int8(0x66);
3137 emit_int8((unsigned char)0x90);
3138 }
3139 // 1 - 8 nops
3140 if(i > 4) {
3141 if(i > 6) {
3142 i -= 1;
3143 emit_int8(0x66);
3144 }
3145 i -= 3;
3146 emit_int8(0x66);
3147 emit_int8(0x66);
3148 emit_int8((unsigned char)0x90);
3149 }
3150 switch (i) {
3151 case 4:
3152 emit_int8(0x66);
3153 case 3:
3154 emit_int8(0x66);
3155 case 2:
3156 emit_int8(0x66);
3157 case 1:
3158 emit_int8((unsigned char)0x90);
3159 break;
3160 default:
3161 assert(i == 0, " ");
3162 }
3163 }
3164
3165 void Assembler::notl(Register dst) {
3166 int encode = prefix_and_encode(dst->encoding());
3167 emit_int8((unsigned char)0xF7);
3168 emit_int8((unsigned char)(0xD0 | encode));
3169 }
3170
3171 void Assembler::orl(Address dst, int32_t imm32) {
3172 InstructionMark im(this);
3173 prefix(dst);
3174 emit_arith_operand(0x81, rcx, dst, imm32);
3175 }
3176
3177 void Assembler::orl(Register dst, int32_t imm32) {
3178 prefix(dst);
3179 emit_arith(0x81, 0xC8, dst, imm32);
3180 }
3181
3182 void Assembler::orl(Register dst, Address src) {
3183 InstructionMark im(this);
3184 prefix(src, dst);
3185 emit_int8(0x0B);
3186 emit_operand(dst, src);
3187 }
3188
3189 void Assembler::orl(Register dst, Register src) {
3190 (void) prefix_and_encode(dst->encoding(), src->encoding());
3191 emit_arith(0x0B, 0xC0, dst, src);
3192 }
3193
3194 void Assembler::orl(Address dst, Register src) {
3195 InstructionMark im(this);
3196 prefix(dst, src);
3197 emit_int8(0x09);
3198 emit_operand(src, dst);
3199 }
3200
3201 void Assembler::packuswb(XMMRegister dst, Address src) {
3202 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3203 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3204 InstructionMark im(this);
3205 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3206 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3207 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3208 emit_int8(0x67);
3209 emit_operand(dst, src);
3210 }
3211
3212 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3213 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3214 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3215 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3216 emit_int8(0x67);
3217 emit_int8((unsigned char)(0xC0 | encode));
3218 }
3219
3220 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3221 assert(UseAVX > 0, "some form of AVX must be enabled");
3222 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3223 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3224 emit_int8(0x67);
3225 emit_int8((unsigned char)(0xC0 | encode));
3226 }
3227
3228 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3229 assert(VM_Version::supports_avx2(), "");
3230 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3231 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3232 emit_int8(0x00);
3233 emit_int8(0xC0 | encode);
3234 emit_int8(imm8);
3235 }
3236
3237 void Assembler::pause() {
3238 emit_int8((unsigned char)0xF3);
3239 emit_int8((unsigned char)0x90);
3240 }
3241
3242 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3243 assert(VM_Version::supports_sse4_2(), "");
3244 InstructionMark im(this);
3245 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3246 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3247 emit_int8(0x61);
3248 emit_operand(dst, src);
3249 emit_int8(imm8);
3250 }
3251
3252 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3253 assert(VM_Version::supports_sse4_2(), "");
3254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3255 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3256 emit_int8(0x61);
3257 emit_int8((unsigned char)(0xC0 | encode));
3258 emit_int8(imm8);
3259 }
3260
3261 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3262 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3263 assert(VM_Version::supports_sse2(), "");
3264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3266 emit_int8(0x74);
3267 emit_int8((unsigned char)(0xC0 | encode));
3268 }
3269
3270 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3271 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3272 assert(VM_Version::supports_avx(), "");
3273 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3274 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3275 emit_int8(0x74);
3276 emit_int8((unsigned char)(0xC0 | encode));
3277 }
3278
3279 // In this context, kdst is written the mask used to process the equal components
3280 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3281 assert(VM_Version::supports_avx512bw(), "");
3282 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3283 attributes.set_is_evex_instruction();
3284 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3285 emit_int8(0x74);
3286 emit_int8((unsigned char)(0xC0 | encode));
3287 }
3288
3289 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3290 assert(VM_Version::supports_avx512bw(), "");
3291 InstructionMark im(this);
3292 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3293 attributes.set_is_evex_instruction();
3294 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3295 int dst_enc = kdst->encoding();
3296 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3297 emit_int8(0x74);
3298 emit_operand(as_Register(dst_enc), src);
3299 }
3300
3301 void Assembler::evpcmpeqb(KRegister mask, bool zeroing, KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3302 bool no_reg_mask = (mask == NULL && zeroing == false) ? true : false;
3303 assert(VM_Version::supports_avx512vlbw(), "");
3304 assert(is_programmed_mask_reg(), "");
3305 InstructionMark im(this);
3306 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, no_reg_mask, /* uses_vl */ false);
3307 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3308 if (!no_reg_mask) {
3309 attributes.set_embedded_opmask_register_specifier(mask);
3310 if (zeroing) attributes.set_is_clear_context();
3311 }
3312 attributes.set_is_evex_instruction();
3313 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3314 emit_int8(0x74);
3315 emit_operand(as_Register(kdst->encoding()), src);
3316 }
3317
3318 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3319 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3320 assert(VM_Version::supports_sse2(), "");
3321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3323 emit_int8(0x75);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 }
3326
3327 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3328 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3329 assert(VM_Version::supports_avx(), "");
3330 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3331 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3332 emit_int8(0x75);
3333 emit_int8((unsigned char)(0xC0 | encode));
3334 }
3335
3336 // In this context, kdst is written the mask used to process the equal components
3337 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3338 assert(VM_Version::supports_avx512bw(), "");
3339 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3340 attributes.set_is_evex_instruction();
3341 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3342 emit_int8(0x75);
3343 emit_int8((unsigned char)(0xC0 | encode));
3344 }
3345
3346 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3347 assert(VM_Version::supports_avx512bw(), "");
3348 InstructionMark im(this);
3349 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3350 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3351 attributes.set_is_evex_instruction();
3352 int dst_enc = kdst->encoding();
3353 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3354 emit_int8(0x75);
3355 emit_operand(as_Register(dst_enc), src);
3356 }
3357
3358 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3359 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3360 assert(VM_Version::supports_sse2(), "");
3361 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3362 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3363 emit_int8(0x76);
3364 emit_int8((unsigned char)(0xC0 | encode));
3365 }
3366
3367 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3368 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3369 assert(VM_Version::supports_avx(), "");
3370 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3371 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3372 emit_int8(0x76);
3373 emit_int8((unsigned char)(0xC0 | encode));
3374 }
3375
3376 // In this context, kdst is written the mask used to process the equal components
3377 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3378 assert(VM_Version::supports_evex(), "");
3379 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3380 attributes.set_is_evex_instruction();
3381 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3382 emit_int8(0x76);
3383 emit_int8((unsigned char)(0xC0 | encode));
3384 }
3385
3386 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3387 assert(VM_Version::supports_evex(), "");
3388 InstructionMark im(this);
3389 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3390 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3391 attributes.set_is_evex_instruction();
3392 int dst_enc = kdst->encoding();
3393 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3394 emit_int8(0x76);
3395 emit_operand(as_Register(dst_enc), src);
3396 }
3397
3398 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3399 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3400 assert(VM_Version::supports_sse4_1(), "");
3401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3402 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3403 emit_int8(0x29);
3404 emit_int8((unsigned char)(0xC0 | encode));
3405 }
3406
3407 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3408 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3409 assert(VM_Version::supports_avx(), "");
3410 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3411 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3412 emit_int8(0x29);
3413 emit_int8((unsigned char)(0xC0 | encode));
3414 }
3415
3416 // In this context, kdst is written the mask used to process the equal components
3417 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3418 assert(VM_Version::supports_evex(), "");
3419 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3420 attributes.set_is_evex_instruction();
3421 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3422 emit_int8(0x29);
3423 emit_int8((unsigned char)(0xC0 | encode));
3424 }
3425
3426 // In this context, kdst is written the mask used to process the equal components
3427 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3428 assert(VM_Version::supports_evex(), "");
3429 InstructionMark im(this);
3430 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3431 attributes.set_is_evex_instruction();
3432 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3433 int dst_enc = kdst->encoding();
3434 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3435 emit_int8(0x29);
3436 emit_operand(as_Register(dst_enc), src);
3437 }
3438
3439 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3440 assert(VM_Version::supports_sse2(), "");
3441 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3442 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3443 emit_int8((unsigned char)0xD7);
3444 emit_int8((unsigned char)(0xC0 | encode));
3445 }
3446
3447 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3448 assert(VM_Version::supports_avx2(), "");
3449 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3450 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3451 emit_int8((unsigned char)0xD7);
3452 emit_int8((unsigned char)(0xC0 | encode));
3453 }
3454
3455 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3456 assert(VM_Version::supports_sse4_1(), "");
3457 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3458 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3459 emit_int8(0x16);
3460 emit_int8((unsigned char)(0xC0 | encode));
3461 emit_int8(imm8);
3462 }
3463
3464 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3465 assert(VM_Version::supports_sse4_1(), "");
3466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3467 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3468 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3469 emit_int8(0x16);
3470 emit_operand(src, dst);
3471 emit_int8(imm8);
3472 }
3473
3474 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3475 assert(VM_Version::supports_sse4_1(), "");
3476 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3477 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3478 emit_int8(0x16);
3479 emit_int8((unsigned char)(0xC0 | encode));
3480 emit_int8(imm8);
3481 }
3482
3483 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3484 assert(VM_Version::supports_sse4_1(), "");
3485 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3486 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3487 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3488 emit_int8(0x16);
3489 emit_operand(src, dst);
3490 emit_int8(imm8);
3491 }
3492
3493 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3494 assert(VM_Version::supports_sse2(), "");
3495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3496 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3497 emit_int8((unsigned char)0xC5);
3498 emit_int8((unsigned char)(0xC0 | encode));
3499 emit_int8(imm8);
3500 }
3501
3502 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3503 assert(VM_Version::supports_sse4_1(), "");
3504 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3505 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3506 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3507 emit_int8((unsigned char)0x15);
3508 emit_operand(src, dst);
3509 emit_int8(imm8);
3510 }
3511
3512 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3513 assert(VM_Version::supports_sse4_1(), "");
3514 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3515 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3516 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3517 emit_int8(0x14);
3518 emit_operand(src, dst);
3519 emit_int8(imm8);
3520 }
3521
3522 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3523 assert(VM_Version::supports_sse4_1(), "");
3524 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3525 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3526 emit_int8(0x22);
3527 emit_int8((unsigned char)(0xC0 | encode));
3528 emit_int8(imm8);
3529 }
3530
3531 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3532 assert(VM_Version::supports_sse4_1(), "");
3533 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3534 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3535 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3536 emit_int8(0x22);
3537 emit_operand(dst,src);
3538 emit_int8(imm8);
3539 }
3540
3541 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3542 assert(VM_Version::supports_sse4_1(), "");
3543 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3544 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3545 emit_int8(0x22);
3546 emit_int8((unsigned char)(0xC0 | encode));
3547 emit_int8(imm8);
3548 }
3549
3550 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3551 assert(VM_Version::supports_sse4_1(), "");
3552 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3553 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3554 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3555 emit_int8(0x22);
3556 emit_operand(dst, src);
3557 emit_int8(imm8);
3558 }
3559
3560 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3561 assert(VM_Version::supports_sse2(), "");
3562 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3563 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3564 emit_int8((unsigned char)0xC4);
3565 emit_int8((unsigned char)(0xC0 | encode));
3566 emit_int8(imm8);
3567 }
3568
3569 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3570 assert(VM_Version::supports_sse2(), "");
3571 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3572 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3573 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3574 emit_int8((unsigned char)0xC4);
3575 emit_operand(dst, src);
3576 emit_int8(imm8);
3577 }
3578
3579 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3580 assert(VM_Version::supports_sse4_1(), "");
3581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3582 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3583 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3584 emit_int8(0x20);
3585 emit_operand(dst, src);
3586 emit_int8(imm8);
3587 }
3588
3589 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3590 assert(VM_Version::supports_sse4_1(), "");
3591 InstructionMark im(this);
3592 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3593 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3594 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3595 emit_int8(0x30);
3596 emit_operand(dst, src);
3597 }
3598
3599 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3600 assert(VM_Version::supports_sse4_1(), "");
3601 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3602 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3603 emit_int8(0x30);
3604 emit_int8((unsigned char)(0xC0 | encode));
3605 }
3606
3607 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3608 assert(VM_Version::supports_avx(), "");
3609 InstructionMark im(this);
3610 assert(dst != xnoreg, "sanity");
3611 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3612 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3613 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3614 emit_int8(0x30);
3615 emit_operand(dst, src);
3616 }
3617
3618 // generic
3619 void Assembler::pop(Register dst) {
3620 int encode = prefix_and_encode(dst->encoding());
3621 emit_int8(0x58 | encode);
3622 }
3623
3624 void Assembler::popcntl(Register dst, Address src) {
3625 assert(VM_Version::supports_popcnt(), "must support");
3626 InstructionMark im(this);
3627 emit_int8((unsigned char)0xF3);
3628 prefix(src, dst);
3629 emit_int8(0x0F);
3630 emit_int8((unsigned char)0xB8);
3631 emit_operand(dst, src);
3632 }
3633
3634 void Assembler::popcntl(Register dst, Register src) {
3635 assert(VM_Version::supports_popcnt(), "must support");
3636 emit_int8((unsigned char)0xF3);
3637 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3638 emit_int8(0x0F);
3639 emit_int8((unsigned char)0xB8);
3640 emit_int8((unsigned char)(0xC0 | encode));
3641 }
3642
3643 void Assembler::popf() {
3644 emit_int8((unsigned char)0x9D);
3645 }
3646
3647 #ifndef _LP64 // no 32bit push/pop on amd64
3648 void Assembler::popl(Address dst) {
3649 // NOTE: this will adjust stack by 8byte on 64bits
3650 InstructionMark im(this);
3651 prefix(dst);
3652 emit_int8((unsigned char)0x8F);
3653 emit_operand(rax, dst);
3654 }
3655 #endif
3656
3657 void Assembler::prefetch_prefix(Address src) {
3658 prefix(src);
3659 emit_int8(0x0F);
3660 }
3661
3662 void Assembler::prefetchnta(Address src) {
3663 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3664 InstructionMark im(this);
3665 prefetch_prefix(src);
3666 emit_int8(0x18);
3667 emit_operand(rax, src); // 0, src
3668 }
3669
3670 void Assembler::prefetchr(Address src) {
3671 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3672 InstructionMark im(this);
3673 prefetch_prefix(src);
3674 emit_int8(0x0D);
3675 emit_operand(rax, src); // 0, src
3676 }
3677
3678 void Assembler::prefetcht0(Address src) {
3679 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3680 InstructionMark im(this);
3681 prefetch_prefix(src);
3682 emit_int8(0x18);
3683 emit_operand(rcx, src); // 1, src
3684 }
3685
3686 void Assembler::prefetcht1(Address src) {
3687 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3688 InstructionMark im(this);
3689 prefetch_prefix(src);
3690 emit_int8(0x18);
3691 emit_operand(rdx, src); // 2, src
3692 }
3693
3694 void Assembler::prefetcht2(Address src) {
3695 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3696 InstructionMark im(this);
3697 prefetch_prefix(src);
3698 emit_int8(0x18);
3699 emit_operand(rbx, src); // 3, src
3700 }
3701
3702 void Assembler::prefetchw(Address src) {
3703 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3704 InstructionMark im(this);
3705 prefetch_prefix(src);
3706 emit_int8(0x0D);
3707 emit_operand(rcx, src); // 1, src
3708 }
3709
3710 void Assembler::prefix(Prefix p) {
3711 emit_int8(p);
3712 }
3713
3714 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3715 assert(VM_Version::supports_ssse3(), "");
3716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3717 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3718 emit_int8(0x00);
3719 emit_int8((unsigned char)(0xC0 | encode));
3720 }
3721
3722 void Assembler::pshufb(XMMRegister dst, Address src) {
3723 assert(VM_Version::supports_ssse3(), "");
3724 InstructionMark im(this);
3725 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3726 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3727 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3728 emit_int8(0x00);
3729 emit_operand(dst, src);
3730 }
3731
3732 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3733 assert(isByte(mode), "invalid value");
3734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3735 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3736 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3737 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3738 emit_int8(0x70);
3739 emit_int8((unsigned char)(0xC0 | encode));
3740 emit_int8(mode & 0xFF);
3741 }
3742
3743 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3744 assert(isByte(mode), "invalid value");
3745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3746 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3747 InstructionMark im(this);
3748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3749 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3750 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3751 emit_int8(0x70);
3752 emit_operand(dst, src);
3753 emit_int8(mode & 0xFF);
3754 }
3755
3756 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3757 assert(isByte(mode), "invalid value");
3758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3760 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3761 emit_int8(0x70);
3762 emit_int8((unsigned char)(0xC0 | encode));
3763 emit_int8(mode & 0xFF);
3764 }
3765
3766 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3767 assert(isByte(mode), "invalid value");
3768 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3769 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3770 InstructionMark im(this);
3771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3772 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3773 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3774 emit_int8(0x70);
3775 emit_operand(dst, src);
3776 emit_int8(mode & 0xFF);
3777 }
3778
3779 void Assembler::psrldq(XMMRegister dst, int shift) {
3780 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3783 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3784 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3785 emit_int8(0x73);
3786 emit_int8((unsigned char)(0xC0 | encode));
3787 emit_int8(shift);
3788 }
3789
3790 void Assembler::pslldq(XMMRegister dst, int shift) {
3791 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3794 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3795 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3796 emit_int8(0x73);
3797 emit_int8((unsigned char)(0xC0 | encode));
3798 emit_int8(shift);
3799 }
3800
3801 void Assembler::ptest(XMMRegister dst, Address src) {
3802 assert(VM_Version::supports_sse4_1(), "");
3803 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3804 InstructionMark im(this);
3805 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3806 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3807 emit_int8(0x17);
3808 emit_operand(dst, src);
3809 }
3810
3811 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3812 assert(VM_Version::supports_sse4_1(), "");
3813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3814 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3815 emit_int8(0x17);
3816 emit_int8((unsigned char)(0xC0 | encode));
3817 }
3818
3819 void Assembler::vptest(XMMRegister dst, Address src) {
3820 assert(VM_Version::supports_avx(), "");
3821 InstructionMark im(this);
3822 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3823 assert(dst != xnoreg, "sanity");
3824 // swap src<->dst for encoding
3825 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3826 emit_int8(0x17);
3827 emit_operand(dst, src);
3828 }
3829
3830 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3831 assert(VM_Version::supports_avx(), "");
3832 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3833 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3834 emit_int8(0x17);
3835 emit_int8((unsigned char)(0xC0 | encode));
3836 }
3837
3838 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3840 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3841 InstructionMark im(this);
3842 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3843 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3844 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3845 emit_int8(0x60);
3846 emit_operand(dst, src);
3847 }
3848
3849 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3850 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3853 emit_int8(0x60);
3854 emit_int8((unsigned char)(0xC0 | encode));
3855 }
3856
3857 void Assembler::punpckldq(XMMRegister dst, Address src) {
3858 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3859 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3860 InstructionMark im(this);
3861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3862 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3863 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3864 emit_int8(0x62);
3865 emit_operand(dst, src);
3866 }
3867
3868 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3870 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3871 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3872 emit_int8(0x62);
3873 emit_int8((unsigned char)(0xC0 | encode));
3874 }
3875
3876 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3877 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3878 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3879 attributes.set_rex_vex_w_reverted();
3880 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3881 emit_int8(0x6C);
3882 emit_int8((unsigned char)(0xC0 | encode));
3883 }
3884
3885 void Assembler::push(int32_t imm32) {
3886 // in 64bits we push 64bits onto the stack but only
3887 // take a 32bit immediate
3888 emit_int8(0x68);
3889 emit_int32(imm32);
3890 }
3891
3892 void Assembler::push(Register src) {
3893 int encode = prefix_and_encode(src->encoding());
3894
3895 emit_int8(0x50 | encode);
3896 }
3897
3898 void Assembler::pushf() {
3899 emit_int8((unsigned char)0x9C);
3900 }
3901
3902 #ifndef _LP64 // no 32bit push/pop on amd64
3903 void Assembler::pushl(Address src) {
3904 // Note this will push 64bit on 64bit
3905 InstructionMark im(this);
3906 prefix(src);
3907 emit_int8((unsigned char)0xFF);
3908 emit_operand(rsi, src);
3909 }
3910 #endif
3911
3912 void Assembler::rcll(Register dst, int imm8) {
3913 assert(isShiftCount(imm8), "illegal shift count");
3914 int encode = prefix_and_encode(dst->encoding());
3915 if (imm8 == 1) {
3916 emit_int8((unsigned char)0xD1);
3917 emit_int8((unsigned char)(0xD0 | encode));
3918 } else {
3919 emit_int8((unsigned char)0xC1);
3920 emit_int8((unsigned char)0xD0 | encode);
3921 emit_int8(imm8);
3922 }
3923 }
3924
3925 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3927 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3929 emit_int8(0x53);
3930 emit_int8((unsigned char)(0xC0 | encode));
3931 }
3932
3933 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3934 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3935 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3936 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3937 emit_int8(0x53);
3938 emit_int8((unsigned char)(0xC0 | encode));
3939 }
3940
3941 void Assembler::rdtsc() {
3942 emit_int8((unsigned char)0x0F);
3943 emit_int8((unsigned char)0x31);
3944 }
3945
3946 // copies data from [esi] to [edi] using rcx pointer sized words
3947 // generic
3948 void Assembler::rep_mov() {
3949 emit_int8((unsigned char)0xF3);
3950 // MOVSQ
3951 LP64_ONLY(prefix(REX_W));
3952 emit_int8((unsigned char)0xA5);
3953 }
3954
3955 // sets rcx bytes with rax, value at [edi]
3956 void Assembler::rep_stosb() {
3957 emit_int8((unsigned char)0xF3); // REP
3958 LP64_ONLY(prefix(REX_W));
3959 emit_int8((unsigned char)0xAA); // STOSB
3960 }
3961
3962 // sets rcx pointer sized words with rax, value at [edi]
3963 // generic
3964 void Assembler::rep_stos() {
3965 emit_int8((unsigned char)0xF3); // REP
3966 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3967 emit_int8((unsigned char)0xAB);
3968 }
3969
3970 // scans rcx pointer sized words at [edi] for occurance of rax,
3971 // generic
3972 void Assembler::repne_scan() { // repne_scan
3973 emit_int8((unsigned char)0xF2);
3974 // SCASQ
3975 LP64_ONLY(prefix(REX_W));
3976 emit_int8((unsigned char)0xAF);
3977 }
3978
3979 #ifdef _LP64
3980 // scans rcx 4 byte words at [edi] for occurance of rax,
3981 // generic
3982 void Assembler::repne_scanl() { // repne_scan
3983 emit_int8((unsigned char)0xF2);
3984 // SCASL
3985 emit_int8((unsigned char)0xAF);
3986 }
3987 #endif
3988
3989 void Assembler::ret(int imm16) {
3990 if (imm16 == 0) {
3991 emit_int8((unsigned char)0xC3);
3992 } else {
3993 emit_int8((unsigned char)0xC2);
3994 emit_int16(imm16);
3995 }
3996 }
3997
3998 void Assembler::sahf() {
3999 #ifdef _LP64
4000 // Not supported in 64bit mode
4001 ShouldNotReachHere();
4002 #endif
4003 emit_int8((unsigned char)0x9E);
4004 }
4005
4006 void Assembler::sarl(Register dst, int imm8) {
4007 int encode = prefix_and_encode(dst->encoding());
4008 assert(isShiftCount(imm8), "illegal shift count");
4009 if (imm8 == 1) {
4010 emit_int8((unsigned char)0xD1);
4011 emit_int8((unsigned char)(0xF8 | encode));
4012 } else {
4013 emit_int8((unsigned char)0xC1);
4014 emit_int8((unsigned char)(0xF8 | encode));
4015 emit_int8(imm8);
4016 }
4017 }
4018
4019 void Assembler::sarl(Register dst) {
4020 int encode = prefix_and_encode(dst->encoding());
4021 emit_int8((unsigned char)0xD3);
4022 emit_int8((unsigned char)(0xF8 | encode));
4023 }
4024
4025 void Assembler::sbbl(Address dst, int32_t imm32) {
4026 InstructionMark im(this);
4027 prefix(dst);
4028 emit_arith_operand(0x81, rbx, dst, imm32);
4029 }
4030
4031 void Assembler::sbbl(Register dst, int32_t imm32) {
4032 prefix(dst);
4033 emit_arith(0x81, 0xD8, dst, imm32);
4034 }
4035
4036
4037 void Assembler::sbbl(Register dst, Address src) {
4038 InstructionMark im(this);
4039 prefix(src, dst);
4040 emit_int8(0x1B);
4041 emit_operand(dst, src);
4042 }
4043
4044 void Assembler::sbbl(Register dst, Register src) {
4045 (void) prefix_and_encode(dst->encoding(), src->encoding());
4046 emit_arith(0x1B, 0xC0, dst, src);
4047 }
4048
4049 void Assembler::setb(Condition cc, Register dst) {
4050 assert(0 <= cc && cc < 16, "illegal cc");
4051 int encode = prefix_and_encode(dst->encoding(), true);
4052 emit_int8(0x0F);
4053 emit_int8((unsigned char)0x90 | cc);
4054 emit_int8((unsigned char)(0xC0 | encode));
4055 }
4056
4057 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4058 assert(VM_Version::supports_ssse3(), "");
4059 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4060 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4061 emit_int8((unsigned char)0x0F);
4062 emit_int8((unsigned char)(0xC0 | encode));
4063 emit_int8(imm8);
4064 }
4065
4066 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4067 assert(VM_Version::supports_sse4_1(), "");
4068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4070 emit_int8((unsigned char)0x0E);
4071 emit_int8((unsigned char)(0xC0 | encode));
4072 emit_int8(imm8);
4073 }
4074
4075 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4076 assert(VM_Version::supports_sha(), "");
4077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4078 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4079 emit_int8((unsigned char)0xCC);
4080 emit_int8((unsigned char)(0xC0 | encode));
4081 emit_int8((unsigned char)imm8);
4082 }
4083
4084 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4085 assert(VM_Version::supports_sha(), "");
4086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4087 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4088 emit_int8((unsigned char)0xC8);
4089 emit_int8((unsigned char)(0xC0 | encode));
4090 }
4091
4092 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4093 assert(VM_Version::supports_sha(), "");
4094 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4095 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4096 emit_int8((unsigned char)0xC9);
4097 emit_int8((unsigned char)(0xC0 | encode));
4098 }
4099
4100 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4101 assert(VM_Version::supports_sha(), "");
4102 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4103 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4104 emit_int8((unsigned char)0xCA);
4105 emit_int8((unsigned char)(0xC0 | encode));
4106 }
4107
4108 // xmm0 is implicit additional source to this instruction.
4109 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4110 assert(VM_Version::supports_sha(), "");
4111 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4112 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4113 emit_int8((unsigned char)0xCB);
4114 emit_int8((unsigned char)(0xC0 | encode));
4115 }
4116
4117 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4118 assert(VM_Version::supports_sha(), "");
4119 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4120 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4121 emit_int8((unsigned char)0xCC);
4122 emit_int8((unsigned char)(0xC0 | encode));
4123 }
4124
4125 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4126 assert(VM_Version::supports_sha(), "");
4127 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4128 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4129 emit_int8((unsigned char)0xCD);
4130 emit_int8((unsigned char)(0xC0 | encode));
4131 }
4132
4133
4134 void Assembler::shll(Register dst, int imm8) {
4135 assert(isShiftCount(imm8), "illegal shift count");
4136 int encode = prefix_and_encode(dst->encoding());
4137 if (imm8 == 1 ) {
4138 emit_int8((unsigned char)0xD1);
4139 emit_int8((unsigned char)(0xE0 | encode));
4140 } else {
4141 emit_int8((unsigned char)0xC1);
4142 emit_int8((unsigned char)(0xE0 | encode));
4143 emit_int8(imm8);
4144 }
4145 }
4146
4147 void Assembler::shll(Register dst) {
4148 int encode = prefix_and_encode(dst->encoding());
4149 emit_int8((unsigned char)0xD3);
4150 emit_int8((unsigned char)(0xE0 | encode));
4151 }
4152
4153 void Assembler::shrl(Register dst, int imm8) {
4154 assert(isShiftCount(imm8), "illegal shift count");
4155 int encode = prefix_and_encode(dst->encoding());
4156 emit_int8((unsigned char)0xC1);
4157 emit_int8((unsigned char)(0xE8 | encode));
4158 emit_int8(imm8);
4159 }
4160
4161 void Assembler::shrl(Register dst) {
4162 int encode = prefix_and_encode(dst->encoding());
4163 emit_int8((unsigned char)0xD3);
4164 emit_int8((unsigned char)(0xE8 | encode));
4165 }
4166
4167 // copies a single word from [esi] to [edi]
4168 void Assembler::smovl() {
4169 emit_int8((unsigned char)0xA5);
4170 }
4171
4172 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4174 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4175 attributes.set_rex_vex_w_reverted();
4176 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4177 emit_int8(0x51);
4178 emit_int8((unsigned char)(0xC0 | encode));
4179 }
4180
4181 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4182 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4183 InstructionMark im(this);
4184 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4185 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4186 attributes.set_rex_vex_w_reverted();
4187 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4188 emit_int8(0x51);
4189 emit_operand(dst, src);
4190 }
4191
4192 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4193 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4194 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4195 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4196 emit_int8(0x51);
4197 emit_int8((unsigned char)(0xC0 | encode));
4198 }
4199
4200 void Assembler::std() {
4201 emit_int8((unsigned char)0xFD);
4202 }
4203
4204 void Assembler::sqrtss(XMMRegister dst, Address src) {
4205 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4206 InstructionMark im(this);
4207 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4208 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4209 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4210 emit_int8(0x51);
4211 emit_operand(dst, src);
4212 }
4213
4214 void Assembler::stmxcsr( Address dst) {
4215 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4216 InstructionMark im(this);
4217 prefix(dst);
4218 emit_int8(0x0F);
4219 emit_int8((unsigned char)0xAE);
4220 emit_operand(as_Register(3), dst);
4221 }
4222
4223 void Assembler::subl(Address dst, int32_t imm32) {
4224 InstructionMark im(this);
4225 prefix(dst);
4226 emit_arith_operand(0x81, rbp, dst, imm32);
4227 }
4228
4229 void Assembler::subl(Address dst, Register src) {
4230 InstructionMark im(this);
4231 prefix(dst, src);
4232 emit_int8(0x29);
4233 emit_operand(src, dst);
4234 }
4235
4236 void Assembler::subl(Register dst, int32_t imm32) {
4237 prefix(dst);
4238 emit_arith(0x81, 0xE8, dst, imm32);
4239 }
4240
4241 // Force generation of a 4 byte immediate value even if it fits into 8bit
4242 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4243 prefix(dst);
4244 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4245 }
4246
4247 void Assembler::subl(Register dst, Address src) {
4248 InstructionMark im(this);
4249 prefix(src, dst);
4250 emit_int8(0x2B);
4251 emit_operand(dst, src);
4252 }
4253
4254 void Assembler::subl(Register dst, Register src) {
4255 (void) prefix_and_encode(dst->encoding(), src->encoding());
4256 emit_arith(0x2B, 0xC0, dst, src);
4257 }
4258
4259 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4261 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4262 attributes.set_rex_vex_w_reverted();
4263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4264 emit_int8(0x5C);
4265 emit_int8((unsigned char)(0xC0 | encode));
4266 }
4267
4268 void Assembler::subsd(XMMRegister dst, Address src) {
4269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4270 InstructionMark im(this);
4271 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4272 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4273 attributes.set_rex_vex_w_reverted();
4274 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4275 emit_int8(0x5C);
4276 emit_operand(dst, src);
4277 }
4278
4279 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4280 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4283 emit_int8(0x5C);
4284 emit_int8((unsigned char)(0xC0 | encode));
4285 }
4286
4287 void Assembler::subss(XMMRegister dst, Address src) {
4288 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4289 InstructionMark im(this);
4290 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4291 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4292 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4293 emit_int8(0x5C);
4294 emit_operand(dst, src);
4295 }
4296
4297 void Assembler::testb(Register dst, int imm8) {
4298 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4299 (void) prefix_and_encode(dst->encoding(), true);
4300 emit_arith_b(0xF6, 0xC0, dst, imm8);
4301 }
4302
4303 void Assembler::testb(Address dst, int imm8) {
4304 InstructionMark im(this);
4305 prefix(dst);
4306 emit_int8((unsigned char)0xF6);
4307 emit_operand(rax, dst, 1);
4308 emit_int8(imm8);
4309 }
4310
4311 void Assembler::testl(Register dst, int32_t imm32) {
4312 // not using emit_arith because test
4313 // doesn't support sign-extension of
4314 // 8bit operands
4315 int encode = dst->encoding();
4316 if (encode == 0) {
4317 emit_int8((unsigned char)0xA9);
4318 } else {
4319 encode = prefix_and_encode(encode);
4320 emit_int8((unsigned char)0xF7);
4321 emit_int8((unsigned char)(0xC0 | encode));
4322 }
4323 emit_int32(imm32);
4324 }
4325
4326 void Assembler::testl(Register dst, Register src) {
4327 (void) prefix_and_encode(dst->encoding(), src->encoding());
4328 emit_arith(0x85, 0xC0, dst, src);
4329 }
4330
4331 void Assembler::testl(Register dst, Address src) {
4332 InstructionMark im(this);
4333 prefix(src, dst);
4334 emit_int8((unsigned char)0x85);
4335 emit_operand(dst, src);
4336 }
4337
4338 void Assembler::tzcntl(Register dst, Register src) {
4339 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4340 emit_int8((unsigned char)0xF3);
4341 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4342 emit_int8(0x0F);
4343 emit_int8((unsigned char)0xBC);
4344 emit_int8((unsigned char)0xC0 | encode);
4345 }
4346
4347 void Assembler::tzcntq(Register dst, Register src) {
4348 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4349 emit_int8((unsigned char)0xF3);
4350 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4351 emit_int8(0x0F);
4352 emit_int8((unsigned char)0xBC);
4353 emit_int8((unsigned char)(0xC0 | encode));
4354 }
4355
4356 void Assembler::ucomisd(XMMRegister dst, Address src) {
4357 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4358 InstructionMark im(this);
4359 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4360 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4361 attributes.set_rex_vex_w_reverted();
4362 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4363 emit_int8(0x2E);
4364 emit_operand(dst, src);
4365 }
4366
4367 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4369 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4370 attributes.set_rex_vex_w_reverted();
4371 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4372 emit_int8(0x2E);
4373 emit_int8((unsigned char)(0xC0 | encode));
4374 }
4375
4376 void Assembler::ucomiss(XMMRegister dst, Address src) {
4377 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4378 InstructionMark im(this);
4379 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4380 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4381 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4382 emit_int8(0x2E);
4383 emit_operand(dst, src);
4384 }
4385
4386 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4387 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4388 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4389 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4390 emit_int8(0x2E);
4391 emit_int8((unsigned char)(0xC0 | encode));
4392 }
4393
4394 void Assembler::xabort(int8_t imm8) {
4395 emit_int8((unsigned char)0xC6);
4396 emit_int8((unsigned char)0xF8);
4397 emit_int8((unsigned char)(imm8 & 0xFF));
4398 }
4399
4400 void Assembler::xaddl(Address dst, Register src) {
4401 InstructionMark im(this);
4402 prefix(dst, src);
4403 emit_int8(0x0F);
4404 emit_int8((unsigned char)0xC1);
4405 emit_operand(src, dst);
4406 }
4407
4408 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4409 InstructionMark im(this);
4410 relocate(rtype);
4411 if (abort.is_bound()) {
4412 address entry = target(abort);
4413 assert(entry != NULL, "abort entry NULL");
4414 intptr_t offset = entry - pc();
4415 emit_int8((unsigned char)0xC7);
4416 emit_int8((unsigned char)0xF8);
4417 emit_int32(offset - 6); // 2 opcode + 4 address
4418 } else {
4419 abort.add_patch_at(code(), locator());
4420 emit_int8((unsigned char)0xC7);
4421 emit_int8((unsigned char)0xF8);
4422 emit_int32(0);
4423 }
4424 }
4425
4426 void Assembler::xchgl(Register dst, Address src) { // xchg
4427 InstructionMark im(this);
4428 prefix(src, dst);
4429 emit_int8((unsigned char)0x87);
4430 emit_operand(dst, src);
4431 }
4432
4433 void Assembler::xchgl(Register dst, Register src) {
4434 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4435 emit_int8((unsigned char)0x87);
4436 emit_int8((unsigned char)(0xC0 | encode));
4437 }
4438
4439 void Assembler::xend() {
4440 emit_int8((unsigned char)0x0F);
4441 emit_int8((unsigned char)0x01);
4442 emit_int8((unsigned char)0xD5);
4443 }
4444
4445 void Assembler::xgetbv() {
4446 emit_int8(0x0F);
4447 emit_int8(0x01);
4448 emit_int8((unsigned char)0xD0);
4449 }
4450
4451 void Assembler::xorl(Register dst, int32_t imm32) {
4452 prefix(dst);
4453 emit_arith(0x81, 0xF0, dst, imm32);
4454 }
4455
4456 void Assembler::xorl(Register dst, Address src) {
4457 InstructionMark im(this);
4458 prefix(src, dst);
4459 emit_int8(0x33);
4460 emit_operand(dst, src);
4461 }
4462
4463 void Assembler::xorl(Register dst, Register src) {
4464 (void) prefix_and_encode(dst->encoding(), src->encoding());
4465 emit_arith(0x33, 0xC0, dst, src);
4466 }
4467
4468 void Assembler::xorb(Register dst, Address src) {
4469 InstructionMark im(this);
4470 prefix(src, dst);
4471 emit_int8(0x32);
4472 emit_operand(dst, src);
4473 }
4474
4475 // AVX 3-operands scalar float-point arithmetic instructions
4476
4477 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4478 assert(VM_Version::supports_avx(), "");
4479 InstructionMark im(this);
4480 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4481 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4482 attributes.set_rex_vex_w_reverted();
4483 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4484 emit_int8(0x58);
4485 emit_operand(dst, src);
4486 }
4487
4488 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4489 assert(VM_Version::supports_avx(), "");
4490 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4491 attributes.set_rex_vex_w_reverted();
4492 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4493 emit_int8(0x58);
4494 emit_int8((unsigned char)(0xC0 | encode));
4495 }
4496
4497 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4498 assert(VM_Version::supports_avx(), "");
4499 InstructionMark im(this);
4500 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4501 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4502 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4503 emit_int8(0x58);
4504 emit_operand(dst, src);
4505 }
4506
4507 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4508 assert(VM_Version::supports_avx(), "");
4509 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4510 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4511 emit_int8(0x58);
4512 emit_int8((unsigned char)(0xC0 | encode));
4513 }
4514
4515 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4516 assert(VM_Version::supports_avx(), "");
4517 InstructionMark im(this);
4518 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4519 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4520 attributes.set_rex_vex_w_reverted();
4521 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4522 emit_int8(0x5E);
4523 emit_operand(dst, src);
4524 }
4525
4526 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4527 assert(VM_Version::supports_avx(), "");
4528 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4529 attributes.set_rex_vex_w_reverted();
4530 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4531 emit_int8(0x5E);
4532 emit_int8((unsigned char)(0xC0 | encode));
4533 }
4534
4535 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4536 assert(VM_Version::supports_avx(), "");
4537 InstructionMark im(this);
4538 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4539 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4540 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4541 emit_int8(0x5E);
4542 emit_operand(dst, src);
4543 }
4544
4545 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4546 assert(VM_Version::supports_avx(), "");
4547 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4548 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4549 emit_int8(0x5E);
4550 emit_int8((unsigned char)(0xC0 | encode));
4551 }
4552
4553 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4554 assert(VM_Version::supports_avx(), "");
4555 InstructionMark im(this);
4556 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4557 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4558 attributes.set_rex_vex_w_reverted();
4559 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4560 emit_int8(0x59);
4561 emit_operand(dst, src);
4562 }
4563
4564 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4565 assert(VM_Version::supports_avx(), "");
4566 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4567 attributes.set_rex_vex_w_reverted();
4568 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4569 emit_int8(0x59);
4570 emit_int8((unsigned char)(0xC0 | encode));
4571 }
4572
4573 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4574 assert(VM_Version::supports_avx(), "");
4575 InstructionMark im(this);
4576 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4577 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4578 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4579 emit_int8(0x59);
4580 emit_operand(dst, src);
4581 }
4582
4583 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4584 assert(VM_Version::supports_avx(), "");
4585 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4586 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4587 emit_int8(0x59);
4588 emit_int8((unsigned char)(0xC0 | encode));
4589 }
4590
4591 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4592 assert(VM_Version::supports_avx(), "");
4593 InstructionMark im(this);
4594 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4595 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4596 attributes.set_rex_vex_w_reverted();
4597 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4598 emit_int8(0x5C);
4599 emit_operand(dst, src);
4600 }
4601
4602 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4603 assert(VM_Version::supports_avx(), "");
4604 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4605 attributes.set_rex_vex_w_reverted();
4606 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4607 emit_int8(0x5C);
4608 emit_int8((unsigned char)(0xC0 | encode));
4609 }
4610
4611 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4612 assert(VM_Version::supports_avx(), "");
4613 InstructionMark im(this);
4614 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4615 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4616 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4617 emit_int8(0x5C);
4618 emit_operand(dst, src);
4619 }
4620
4621 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4622 assert(VM_Version::supports_avx(), "");
4623 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4624 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4625 emit_int8(0x5C);
4626 emit_int8((unsigned char)(0xC0 | encode));
4627 }
4628
4629 //====================VECTOR ARITHMETIC=====================================
4630
4631 // Float-point vector arithmetic
4632
4633 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4635 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4636 attributes.set_rex_vex_w_reverted();
4637 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4638 emit_int8(0x58);
4639 emit_int8((unsigned char)(0xC0 | encode));
4640 }
4641
4642 void Assembler::addpd(XMMRegister dst, Address src) {
4643 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4644 InstructionMark im(this);
4645 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4646 attributes.set_rex_vex_w_reverted();
4647 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4648 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4649 emit_int8(0x58);
4650 emit_operand(dst, src);
4651 }
4652
4653
4654 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4657 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4658 emit_int8(0x58);
4659 emit_int8((unsigned char)(0xC0 | encode));
4660 }
4661
4662 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4663 assert(VM_Version::supports_avx(), "");
4664 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4665 attributes.set_rex_vex_w_reverted();
4666 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4667 emit_int8(0x58);
4668 emit_int8((unsigned char)(0xC0 | encode));
4669 }
4670
4671 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4672 assert(VM_Version::supports_avx(), "");
4673 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4674 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4675 emit_int8(0x58);
4676 emit_int8((unsigned char)(0xC0 | encode));
4677 }
4678
4679 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4680 assert(VM_Version::supports_avx(), "");
4681 InstructionMark im(this);
4682 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4683 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4684 attributes.set_rex_vex_w_reverted();
4685 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4686 emit_int8(0x58);
4687 emit_operand(dst, src);
4688 }
4689
4690 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4691 assert(VM_Version::supports_avx(), "");
4692 InstructionMark im(this);
4693 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4694 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4695 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4696 emit_int8(0x58);
4697 emit_operand(dst, src);
4698 }
4699
4700 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4701 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4702 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4703 attributes.set_rex_vex_w_reverted();
4704 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4705 emit_int8(0x5C);
4706 emit_int8((unsigned char)(0xC0 | encode));
4707 }
4708
4709 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4711 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4712 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4713 emit_int8(0x5C);
4714 emit_int8((unsigned char)(0xC0 | encode));
4715 }
4716
4717 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4718 assert(VM_Version::supports_avx(), "");
4719 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4720 attributes.set_rex_vex_w_reverted();
4721 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4722 emit_int8(0x5C);
4723 emit_int8((unsigned char)(0xC0 | encode));
4724 }
4725
4726 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4727 assert(VM_Version::supports_avx(), "");
4728 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4729 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4730 emit_int8(0x5C);
4731 emit_int8((unsigned char)(0xC0 | encode));
4732 }
4733
4734 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4735 assert(VM_Version::supports_avx(), "");
4736 InstructionMark im(this);
4737 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4738 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4739 attributes.set_rex_vex_w_reverted();
4740 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4741 emit_int8(0x5C);
4742 emit_operand(dst, src);
4743 }
4744
4745 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4746 assert(VM_Version::supports_avx(), "");
4747 InstructionMark im(this);
4748 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4749 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4750 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4751 emit_int8(0x5C);
4752 emit_operand(dst, src);
4753 }
4754
4755 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4757 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4758 attributes.set_rex_vex_w_reverted();
4759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4760 emit_int8(0x59);
4761 emit_int8((unsigned char)(0xC0 | encode));
4762 }
4763
4764 void Assembler::mulpd(XMMRegister dst, Address src) {
4765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4766 InstructionMark im(this);
4767 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4768 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4769 attributes.set_rex_vex_w_reverted();
4770 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4771 emit_int8(0x59);
4772 emit_operand(dst, src);
4773 }
4774
4775 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4778 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4779 emit_int8(0x59);
4780 emit_int8((unsigned char)(0xC0 | encode));
4781 }
4782
4783 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4784 assert(VM_Version::supports_avx(), "");
4785 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4786 attributes.set_rex_vex_w_reverted();
4787 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4788 emit_int8(0x59);
4789 emit_int8((unsigned char)(0xC0 | encode));
4790 }
4791
4792 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4793 assert(VM_Version::supports_avx(), "");
4794 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4795 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4796 emit_int8(0x59);
4797 emit_int8((unsigned char)(0xC0 | encode));
4798 }
4799
4800 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4801 assert(VM_Version::supports_avx(), "");
4802 InstructionMark im(this);
4803 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4804 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4805 attributes.set_rex_vex_w_reverted();
4806 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4807 emit_int8(0x59);
4808 emit_operand(dst, src);
4809 }
4810
4811 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4812 assert(VM_Version::supports_avx(), "");
4813 InstructionMark im(this);
4814 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4815 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4816 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4817 emit_int8(0x59);
4818 emit_operand(dst, src);
4819 }
4820
4821 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4822 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4823 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4824 attributes.set_rex_vex_w_reverted();
4825 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4826 emit_int8(0x5E);
4827 emit_int8((unsigned char)(0xC0 | encode));
4828 }
4829
4830 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4832 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4833 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4834 emit_int8(0x5E);
4835 emit_int8((unsigned char)(0xC0 | encode));
4836 }
4837
4838 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4839 assert(VM_Version::supports_avx(), "");
4840 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4841 attributes.set_rex_vex_w_reverted();
4842 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4843 emit_int8(0x5E);
4844 emit_int8((unsigned char)(0xC0 | encode));
4845 }
4846
4847 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4848 assert(VM_Version::supports_avx(), "");
4849 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4850 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4851 emit_int8(0x5E);
4852 emit_int8((unsigned char)(0xC0 | encode));
4853 }
4854
4855 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4856 assert(VM_Version::supports_avx(), "");
4857 InstructionMark im(this);
4858 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4859 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4860 attributes.set_rex_vex_w_reverted();
4861 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4862 emit_int8(0x5E);
4863 emit_operand(dst, src);
4864 }
4865
4866 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4867 assert(VM_Version::supports_avx(), "");
4868 InstructionMark im(this);
4869 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4870 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4871 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4872 emit_int8(0x5E);
4873 emit_operand(dst, src);
4874 }
4875
4876 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4877 assert(VM_Version::supports_avx(), "");
4878 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4879 attributes.set_rex_vex_w_reverted();
4880 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4881 emit_int8(0x51);
4882 emit_int8((unsigned char)(0xC0 | encode));
4883 }
4884
4885 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4886 assert(VM_Version::supports_avx(), "");
4887 InstructionMark im(this);
4888 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4889 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4890 attributes.set_rex_vex_w_reverted();
4891 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4892 emit_int8(0x51);
4893 emit_operand(dst, src);
4894 }
4895
4896 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4897 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4898 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4899 attributes.set_rex_vex_w_reverted();
4900 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4901 emit_int8(0x54);
4902 emit_int8((unsigned char)(0xC0 | encode));
4903 }
4904
4905 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4906 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4907 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4908 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4909 emit_int8(0x54);
4910 emit_int8((unsigned char)(0xC0 | encode));
4911 }
4912
4913 void Assembler::andps(XMMRegister dst, Address src) {
4914 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4915 InstructionMark im(this);
4916 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4917 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4918 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4919 emit_int8(0x54);
4920 emit_operand(dst, src);
4921 }
4922
4923 void Assembler::andpd(XMMRegister dst, Address src) {
4924 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4925 InstructionMark im(this);
4926 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4927 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4928 attributes.set_rex_vex_w_reverted();
4929 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4930 emit_int8(0x54);
4931 emit_operand(dst, src);
4932 }
4933
4934 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4935 assert(VM_Version::supports_avx(), "");
4936 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4937 attributes.set_rex_vex_w_reverted();
4938 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4939 emit_int8(0x54);
4940 emit_int8((unsigned char)(0xC0 | encode));
4941 }
4942
4943 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4944 assert(VM_Version::supports_avx(), "");
4945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4946 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4947 emit_int8(0x54);
4948 emit_int8((unsigned char)(0xC0 | encode));
4949 }
4950
4951 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4952 assert(VM_Version::supports_avx(), "");
4953 InstructionMark im(this);
4954 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4955 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4956 attributes.set_rex_vex_w_reverted();
4957 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4958 emit_int8(0x54);
4959 emit_operand(dst, src);
4960 }
4961
4962 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4963 assert(VM_Version::supports_avx(), "");
4964 InstructionMark im(this);
4965 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4966 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4967 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4968 emit_int8(0x54);
4969 emit_operand(dst, src);
4970 }
4971
4972 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4973 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4974 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4975 attributes.set_rex_vex_w_reverted();
4976 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x15);
4978 emit_int8((unsigned char)(0xC0 | encode));
4979 }
4980
4981 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4982 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4983 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4984 attributes.set_rex_vex_w_reverted();
4985 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4986 emit_int8(0x14);
4987 emit_int8((unsigned char)(0xC0 | encode));
4988 }
4989
4990 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4991 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4992 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4993 attributes.set_rex_vex_w_reverted();
4994 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4995 emit_int8(0x57);
4996 emit_int8((unsigned char)(0xC0 | encode));
4997 }
4998
4999 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5000 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5001 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5002 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5003 emit_int8(0x57);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::xorpd(XMMRegister dst, Address src) {
5008 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5009 InstructionMark im(this);
5010 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5011 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5012 attributes.set_rex_vex_w_reverted();
5013 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5014 emit_int8(0x57);
5015 emit_operand(dst, src);
5016 }
5017
5018 void Assembler::xorps(XMMRegister dst, Address src) {
5019 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5020 InstructionMark im(this);
5021 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5022 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5023 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5024 emit_int8(0x57);
5025 emit_operand(dst, src);
5026 }
5027
5028 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5029 assert(VM_Version::supports_avx(), "");
5030 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5031 attributes.set_rex_vex_w_reverted();
5032 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5033 emit_int8(0x57);
5034 emit_int8((unsigned char)(0xC0 | encode));
5035 }
5036
5037 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5038 assert(VM_Version::supports_avx(), "");
5039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5040 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5041 emit_int8(0x57);
5042 emit_int8((unsigned char)(0xC0 | encode));
5043 }
5044
5045 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5046 assert(VM_Version::supports_avx(), "");
5047 InstructionMark im(this);
5048 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5049 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5050 attributes.set_rex_vex_w_reverted();
5051 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5052 emit_int8(0x57);
5053 emit_operand(dst, src);
5054 }
5055
5056 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5057 assert(VM_Version::supports_avx(), "");
5058 InstructionMark im(this);
5059 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5060 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5061 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5062 emit_int8(0x57);
5063 emit_operand(dst, src);
5064 }
5065
5066 // Integer vector arithmetic
5067 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5068 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5069 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5070 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5071 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5072 emit_int8(0x01);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 }
5075
5076 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5077 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5078 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5079 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5080 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5081 emit_int8(0x02);
5082 emit_int8((unsigned char)(0xC0 | encode));
5083 }
5084
5085 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5086 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5087 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5088 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5089 emit_int8((unsigned char)0xFC);
5090 emit_int8((unsigned char)(0xC0 | encode));
5091 }
5092
5093 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5094 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5095 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5096 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5097 emit_int8((unsigned char)0xFD);
5098 emit_int8((unsigned char)(0xC0 | encode));
5099 }
5100
5101 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5102 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5104 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5105 emit_int8((unsigned char)0xFE);
5106 emit_int8((unsigned char)(0xC0 | encode));
5107 }
5108
5109 void Assembler::paddd(XMMRegister dst, Address src) {
5110 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5111 InstructionMark im(this);
5112 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5113 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5114 emit_int8((unsigned char)0xFE);
5115 emit_operand(dst, src);
5116 }
5117
5118 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5119 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5120 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5121 attributes.set_rex_vex_w_reverted();
5122 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5123 emit_int8((unsigned char)0xD4);
5124 emit_int8((unsigned char)(0xC0 | encode));
5125 }
5126
5127 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5128 assert(VM_Version::supports_sse3(), "");
5129 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5130 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5131 emit_int8(0x01);
5132 emit_int8((unsigned char)(0xC0 | encode));
5133 }
5134
5135 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5136 assert(VM_Version::supports_sse3(), "");
5137 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5138 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5139 emit_int8(0x02);
5140 emit_int8((unsigned char)(0xC0 | encode));
5141 }
5142
5143 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5144 assert(UseAVX > 0, "requires some form of AVX");
5145 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5146 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5147 emit_int8((unsigned char)0xFC);
5148 emit_int8((unsigned char)(0xC0 | encode));
5149 }
5150
5151 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5152 assert(UseAVX > 0, "requires some form of AVX");
5153 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5154 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5155 emit_int8((unsigned char)0xFD);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5158
5159 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5160 assert(UseAVX > 0, "requires some form of AVX");
5161 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5162 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5163 emit_int8((unsigned char)0xFE);
5164 emit_int8((unsigned char)(0xC0 | encode));
5165 }
5166
5167 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5168 assert(UseAVX > 0, "requires some form of AVX");
5169 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5170 attributes.set_rex_vex_w_reverted();
5171 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5172 emit_int8((unsigned char)0xD4);
5173 emit_int8((unsigned char)(0xC0 | encode));
5174 }
5175
5176 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5177 assert(UseAVX > 0, "requires some form of AVX");
5178 InstructionMark im(this);
5179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5180 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5181 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5182 emit_int8((unsigned char)0xFC);
5183 emit_operand(dst, src);
5184 }
5185
5186 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5187 assert(UseAVX > 0, "requires some form of AVX");
5188 InstructionMark im(this);
5189 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5190 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5191 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5192 emit_int8((unsigned char)0xFD);
5193 emit_operand(dst, src);
5194 }
5195
5196 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5197 assert(UseAVX > 0, "requires some form of AVX");
5198 InstructionMark im(this);
5199 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5200 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5201 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5202 emit_int8((unsigned char)0xFE);
5203 emit_operand(dst, src);
5204 }
5205
5206 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5207 assert(UseAVX > 0, "requires some form of AVX");
5208 InstructionMark im(this);
5209 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5210 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5211 attributes.set_rex_vex_w_reverted();
5212 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5213 emit_int8((unsigned char)0xD4);
5214 emit_operand(dst, src);
5215 }
5216
5217 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5218 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5220 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5221 emit_int8((unsigned char)0xF8);
5222 emit_int8((unsigned char)(0xC0 | encode));
5223 }
5224
5225 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5226 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5227 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5228 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5229 emit_int8((unsigned char)0xF9);
5230 emit_int8((unsigned char)(0xC0 | encode));
5231 }
5232
5233 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5235 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5236 emit_int8((unsigned char)0xFA);
5237 emit_int8((unsigned char)(0xC0 | encode));
5238 }
5239
5240 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5243 attributes.set_rex_vex_w_reverted();
5244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5245 emit_int8((unsigned char)0xFB);
5246 emit_int8((unsigned char)(0xC0 | encode));
5247 }
5248
5249 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5250 assert(UseAVX > 0, "requires some form of AVX");
5251 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5252 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5253 emit_int8((unsigned char)0xF8);
5254 emit_int8((unsigned char)(0xC0 | encode));
5255 }
5256
5257 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5258 assert(UseAVX > 0, "requires some form of AVX");
5259 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5260 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5261 emit_int8((unsigned char)0xF9);
5262 emit_int8((unsigned char)(0xC0 | encode));
5263 }
5264
5265 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5266 assert(UseAVX > 0, "requires some form of AVX");
5267 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5269 emit_int8((unsigned char)0xFA);
5270 emit_int8((unsigned char)(0xC0 | encode));
5271 }
5272
5273 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5274 assert(UseAVX > 0, "requires some form of AVX");
5275 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5276 attributes.set_rex_vex_w_reverted();
5277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5278 emit_int8((unsigned char)0xFB);
5279 emit_int8((unsigned char)(0xC0 | encode));
5280 }
5281
5282 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5283 assert(UseAVX > 0, "requires some form of AVX");
5284 InstructionMark im(this);
5285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5286 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5287 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5288 emit_int8((unsigned char)0xF8);
5289 emit_operand(dst, src);
5290 }
5291
5292 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5293 assert(UseAVX > 0, "requires some form of AVX");
5294 InstructionMark im(this);
5295 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5296 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5297 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5298 emit_int8((unsigned char)0xF9);
5299 emit_operand(dst, src);
5300 }
5301
5302 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5303 assert(UseAVX > 0, "requires some form of AVX");
5304 InstructionMark im(this);
5305 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5306 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5307 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5308 emit_int8((unsigned char)0xFA);
5309 emit_operand(dst, src);
5310 }
5311
5312 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5313 assert(UseAVX > 0, "requires some form of AVX");
5314 InstructionMark im(this);
5315 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5316 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5317 attributes.set_rex_vex_w_reverted();
5318 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5319 emit_int8((unsigned char)0xFB);
5320 emit_operand(dst, src);
5321 }
5322
5323 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5324 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5325 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5326 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5327 emit_int8((unsigned char)0xD5);
5328 emit_int8((unsigned char)(0xC0 | encode));
5329 }
5330
5331 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5332 assert(VM_Version::supports_sse4_1(), "");
5333 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5334 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5335 emit_int8(0x40);
5336 emit_int8((unsigned char)(0xC0 | encode));
5337 }
5338
5339 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5340 assert(UseAVX > 0, "requires some form of AVX");
5341 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5343 emit_int8((unsigned char)0xD5);
5344 emit_int8((unsigned char)(0xC0 | encode));
5345 }
5346
5347 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5348 assert(UseAVX > 0, "requires some form of AVX");
5349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5350 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5351 emit_int8(0x40);
5352 emit_int8((unsigned char)(0xC0 | encode));
5353 }
5354
5355 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5356 assert(UseAVX > 2, "requires some form of EVEX");
5357 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5358 attributes.set_is_evex_instruction();
5359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5360 emit_int8(0x40);
5361 emit_int8((unsigned char)(0xC0 | encode));
5362 }
5363
5364 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5365 assert(UseAVX > 0, "requires some form of AVX");
5366 InstructionMark im(this);
5367 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5368 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5369 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5370 emit_int8((unsigned char)0xD5);
5371 emit_operand(dst, src);
5372 }
5373
5374 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5375 assert(UseAVX > 0, "requires some form of AVX");
5376 InstructionMark im(this);
5377 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5378 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5379 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5380 emit_int8(0x40);
5381 emit_operand(dst, src);
5382 }
5383
5384 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5385 assert(UseAVX > 2, "requires some form of EVEX");
5386 InstructionMark im(this);
5387 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5388 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5389 attributes.set_is_evex_instruction();
5390 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5391 emit_int8(0x40);
5392 emit_operand(dst, src);
5393 }
5394
5395 // Shift packed integers left by specified number of bits.
5396 void Assembler::psllw(XMMRegister dst, int shift) {
5397 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5399 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5400 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5401 emit_int8(0x71);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 emit_int8(shift & 0xFF);
5404 }
5405
5406 void Assembler::pslld(XMMRegister dst, int shift) {
5407 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5408 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5409 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5410 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5411 emit_int8(0x72);
5412 emit_int8((unsigned char)(0xC0 | encode));
5413 emit_int8(shift & 0xFF);
5414 }
5415
5416 void Assembler::psllq(XMMRegister dst, int shift) {
5417 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5418 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5419 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5420 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5421 emit_int8(0x73);
5422 emit_int8((unsigned char)(0xC0 | encode));
5423 emit_int8(shift & 0xFF);
5424 }
5425
5426 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5427 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5428 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5429 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5430 emit_int8((unsigned char)0xF1);
5431 emit_int8((unsigned char)(0xC0 | encode));
5432 }
5433
5434 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5437 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5438 emit_int8((unsigned char)0xF2);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 }
5441
5442 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5444 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5445 attributes.set_rex_vex_w_reverted();
5446 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5447 emit_int8((unsigned char)0xF3);
5448 emit_int8((unsigned char)(0xC0 | encode));
5449 }
5450
5451 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5452 assert(UseAVX > 0, "requires some form of AVX");
5453 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5454 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5455 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5456 emit_int8(0x71);
5457 emit_int8((unsigned char)(0xC0 | encode));
5458 emit_int8(shift & 0xFF);
5459 }
5460
5461 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5462 assert(UseAVX > 0, "requires some form of AVX");
5463 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5464 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5465 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5466 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5467 emit_int8(0x72);
5468 emit_int8((unsigned char)(0xC0 | encode));
5469 emit_int8(shift & 0xFF);
5470 }
5471
5472 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5473 assert(UseAVX > 0, "requires some form of AVX");
5474 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5475 attributes.set_rex_vex_w_reverted();
5476 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5477 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5478 emit_int8(0x73);
5479 emit_int8((unsigned char)(0xC0 | encode));
5480 emit_int8(shift & 0xFF);
5481 }
5482
5483 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5484 assert(UseAVX > 0, "requires some form of AVX");
5485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5486 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5487 emit_int8((unsigned char)0xF1);
5488 emit_int8((unsigned char)(0xC0 | encode));
5489 }
5490
5491 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5492 assert(UseAVX > 0, "requires some form of AVX");
5493 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5494 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5495 emit_int8((unsigned char)0xF2);
5496 emit_int8((unsigned char)(0xC0 | encode));
5497 }
5498
5499 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5500 assert(UseAVX > 0, "requires some form of AVX");
5501 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5502 attributes.set_rex_vex_w_reverted();
5503 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5504 emit_int8((unsigned char)0xF3);
5505 emit_int8((unsigned char)(0xC0 | encode));
5506 }
5507
5508 // Shift packed integers logically right by specified number of bits.
5509 void Assembler::psrlw(XMMRegister dst, int shift) {
5510 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5511 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5512 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5513 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5514 emit_int8(0x71);
5515 emit_int8((unsigned char)(0xC0 | encode));
5516 emit_int8(shift & 0xFF);
5517 }
5518
5519 void Assembler::psrld(XMMRegister dst, int shift) {
5520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5521 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5522 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5523 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5524 emit_int8(0x72);
5525 emit_int8((unsigned char)(0xC0 | encode));
5526 emit_int8(shift & 0xFF);
5527 }
5528
5529 void Assembler::psrlq(XMMRegister dst, int shift) {
5530 // Do not confuse it with psrldq SSE2 instruction which
5531 // shifts 128 bit value in xmm register by number of bytes.
5532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5533 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5534 attributes.set_rex_vex_w_reverted();
5535 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5536 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5537 emit_int8(0x73);
5538 emit_int8((unsigned char)(0xC0 | encode));
5539 emit_int8(shift & 0xFF);
5540 }
5541
5542 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5543 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5544 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5545 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5546 emit_int8((unsigned char)0xD1);
5547 emit_int8((unsigned char)(0xC0 | encode));
5548 }
5549
5550 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5551 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5552 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5553 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5554 emit_int8((unsigned char)0xD2);
5555 emit_int8((unsigned char)(0xC0 | encode));
5556 }
5557
5558 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5559 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5560 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5561 attributes.set_rex_vex_w_reverted();
5562 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5563 emit_int8((unsigned char)0xD3);
5564 emit_int8((unsigned char)(0xC0 | encode));
5565 }
5566
5567 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5568 assert(UseAVX > 0, "requires some form of AVX");
5569 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5570 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5571 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5572 emit_int8(0x71);
5573 emit_int8((unsigned char)(0xC0 | encode));
5574 emit_int8(shift & 0xFF);
5575 }
5576
5577 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5578 assert(UseAVX > 0, "requires some form of AVX");
5579 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5580 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5581 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5582 emit_int8(0x72);
5583 emit_int8((unsigned char)(0xC0 | encode));
5584 emit_int8(shift & 0xFF);
5585 }
5586
5587 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5588 assert(UseAVX > 0, "requires some form of AVX");
5589 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5590 attributes.set_rex_vex_w_reverted();
5591 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5592 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5593 emit_int8(0x73);
5594 emit_int8((unsigned char)(0xC0 | encode));
5595 emit_int8(shift & 0xFF);
5596 }
5597
5598 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5599 assert(UseAVX > 0, "requires some form of AVX");
5600 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5601 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5602 emit_int8((unsigned char)0xD1);
5603 emit_int8((unsigned char)(0xC0 | encode));
5604 }
5605
5606 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5607 assert(UseAVX > 0, "requires some form of AVX");
5608 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5609 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5610 emit_int8((unsigned char)0xD2);
5611 emit_int8((unsigned char)(0xC0 | encode));
5612 }
5613
5614 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5615 assert(UseAVX > 0, "requires some form of AVX");
5616 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5617 attributes.set_rex_vex_w_reverted();
5618 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5619 emit_int8((unsigned char)0xD3);
5620 emit_int8((unsigned char)(0xC0 | encode));
5621 }
5622
5623 // Shift packed integers arithmetically right by specified number of bits.
5624 void Assembler::psraw(XMMRegister dst, int shift) {
5625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5626 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5627 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5628 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5629 emit_int8(0x71);
5630 emit_int8((unsigned char)(0xC0 | encode));
5631 emit_int8(shift & 0xFF);
5632 }
5633
5634 void Assembler::psrad(XMMRegister dst, int shift) {
5635 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5636 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5637 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5638 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5639 emit_int8(0x72);
5640 emit_int8((unsigned char)(0xC0 | encode));
5641 emit_int8(shift & 0xFF);
5642 }
5643
5644 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5646 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5647 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5648 emit_int8((unsigned char)0xE1);
5649 emit_int8((unsigned char)(0xC0 | encode));
5650 }
5651
5652 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5654 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5655 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5656 emit_int8((unsigned char)0xE2);
5657 emit_int8((unsigned char)(0xC0 | encode));
5658 }
5659
5660 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5661 assert(UseAVX > 0, "requires some form of AVX");
5662 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5663 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5664 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5665 emit_int8(0x71);
5666 emit_int8((unsigned char)(0xC0 | encode));
5667 emit_int8(shift & 0xFF);
5668 }
5669
5670 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5671 assert(UseAVX > 0, "requires some form of AVX");
5672 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5673 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5674 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5675 emit_int8(0x72);
5676 emit_int8((unsigned char)(0xC0 | encode));
5677 emit_int8(shift & 0xFF);
5678 }
5679
5680 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5681 assert(UseAVX > 0, "requires some form of AVX");
5682 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5683 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5684 emit_int8((unsigned char)0xE1);
5685 emit_int8((unsigned char)(0xC0 | encode));
5686 }
5687
5688 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5689 assert(UseAVX > 0, "requires some form of AVX");
5690 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5691 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5692 emit_int8((unsigned char)0xE2);
5693 emit_int8((unsigned char)(0xC0 | encode));
5694 }
5695
5696
5697 // logical operations packed integers
5698 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5699 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5700 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5701 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5702 emit_int8((unsigned char)0xDB);
5703 emit_int8((unsigned char)(0xC0 | encode));
5704 }
5705
5706 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5707 assert(UseAVX > 0, "requires some form of AVX");
5708 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5709 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5710 emit_int8((unsigned char)0xDB);
5711 emit_int8((unsigned char)(0xC0 | encode));
5712 }
5713
5714 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5715 assert(UseAVX > 0, "requires some form of AVX");
5716 InstructionMark im(this);
5717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5718 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5719 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5720 emit_int8((unsigned char)0xDB);
5721 emit_operand(dst, src);
5722 }
5723
5724 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5726 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5727 attributes.set_rex_vex_w_reverted();
5728 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5729 emit_int8((unsigned char)0xDF);
5730 emit_int8((unsigned char)(0xC0 | encode));
5731 }
5732
5733 void Assembler::por(XMMRegister dst, XMMRegister src) {
5734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5735 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5737 emit_int8((unsigned char)0xEB);
5738 emit_int8((unsigned char)(0xC0 | encode));
5739 }
5740
5741 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5742 assert(UseAVX > 0, "requires some form of AVX");
5743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5744 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5745 emit_int8((unsigned char)0xEB);
5746 emit_int8((unsigned char)(0xC0 | encode));
5747 }
5748
5749 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5750 assert(UseAVX > 0, "requires some form of AVX");
5751 InstructionMark im(this);
5752 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5753 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5754 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5755 emit_int8((unsigned char)0xEB);
5756 emit_operand(dst, src);
5757 }
5758
5759 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5761 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5762 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5763 emit_int8((unsigned char)0xEF);
5764 emit_int8((unsigned char)(0xC0 | encode));
5765 }
5766
5767 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5768 assert(UseAVX > 0, "requires some form of AVX");
5769 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5770 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5771 emit_int8((unsigned char)0xEF);
5772 emit_int8((unsigned char)(0xC0 | encode));
5773 }
5774
5775 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5776 assert(UseAVX > 0, "requires some form of AVX");
5777 InstructionMark im(this);
5778 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5779 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5780 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5781 emit_int8((unsigned char)0xEF);
5782 emit_operand(dst, src);
5783 }
5784
5785
5786 // vinserti forms
5787
5788 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5789 assert(VM_Version::supports_avx2(), "");
5790 assert(imm8 <= 0x01, "imm8: %u", imm8);
5791 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5792 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5793 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5794 emit_int8(0x38);
5795 emit_int8((unsigned char)(0xC0 | encode));
5796 // 0x00 - insert into lower 128 bits
5797 // 0x01 - insert into upper 128 bits
5798 emit_int8(imm8 & 0x01);
5799 }
5800
5801 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5802 assert(VM_Version::supports_avx2(), "");
5803 assert(dst != xnoreg, "sanity");
5804 assert(imm8 <= 0x01, "imm8: %u", imm8);
5805 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5806 InstructionMark im(this);
5807 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5808 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5809 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5810 emit_int8(0x38);
5811 emit_operand(dst, src);
5812 // 0x00 - insert into lower 128 bits
5813 // 0x01 - insert into upper 128 bits
5814 emit_int8(imm8 & 0x01);
5815 }
5816
5817 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5818 assert(VM_Version::supports_evex(), "");
5819 assert(imm8 <= 0x03, "imm8: %u", imm8);
5820 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5821 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5822 emit_int8(0x38);
5823 emit_int8((unsigned char)(0xC0 | encode));
5824 // 0x00 - insert into q0 128 bits (0..127)
5825 // 0x01 - insert into q1 128 bits (128..255)
5826 // 0x02 - insert into q2 128 bits (256..383)
5827 // 0x03 - insert into q3 128 bits (384..511)
5828 emit_int8(imm8 & 0x03);
5829 }
5830
5831 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5832 assert(VM_Version::supports_avx(), "");
5833 assert(dst != xnoreg, "sanity");
5834 assert(imm8 <= 0x03, "imm8: %u", imm8);
5835 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5836 InstructionMark im(this);
5837 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5838 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5839 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5840 emit_int8(0x18);
5841 emit_operand(dst, src);
5842 // 0x00 - insert into q0 128 bits (0..127)
5843 // 0x01 - insert into q1 128 bits (128..255)
5844 // 0x02 - insert into q2 128 bits (256..383)
5845 // 0x03 - insert into q3 128 bits (384..511)
5846 emit_int8(imm8 & 0x03);
5847 }
5848
5849 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5850 assert(VM_Version::supports_evex(), "");
5851 assert(imm8 <= 0x01, "imm8: %u", imm8);
5852 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5853 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5854 emit_int8(0x38);
5855 emit_int8((unsigned char)(0xC0 | encode));
5856 // 0x00 - insert into lower 256 bits
5857 // 0x01 - insert into upper 256 bits
5858 emit_int8(imm8 & 0x01);
5859 }
5860
5861
5862 // vinsertf forms
5863
5864 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5865 assert(VM_Version::supports_avx(), "");
5866 assert(imm8 <= 0x01, "imm8: %u", imm8);
5867 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5869 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5870 emit_int8(0x18);
5871 emit_int8((unsigned char)(0xC0 | encode));
5872 // 0x00 - insert into lower 128 bits
5873 // 0x01 - insert into upper 128 bits
5874 emit_int8(imm8 & 0x01);
5875 }
5876
5877 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5878 assert(VM_Version::supports_avx(), "");
5879 assert(dst != xnoreg, "sanity");
5880 assert(imm8 <= 0x01, "imm8: %u", imm8);
5881 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5882 InstructionMark im(this);
5883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5884 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5885 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5886 emit_int8(0x18);
5887 emit_operand(dst, src);
5888 // 0x00 - insert into lower 128 bits
5889 // 0x01 - insert into upper 128 bits
5890 emit_int8(imm8 & 0x01);
5891 }
5892
5893 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5894 assert(VM_Version::supports_evex(), "");
5895 assert(imm8 <= 0x03, "imm8: %u", imm8);
5896 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5897 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5898 emit_int8(0x18);
5899 emit_int8((unsigned char)(0xC0 | encode));
5900 // 0x00 - insert into q0 128 bits (0..127)
5901 // 0x01 - insert into q1 128 bits (128..255)
5902 // 0x02 - insert into q2 128 bits (256..383)
5903 // 0x03 - insert into q3 128 bits (384..511)
5904 emit_int8(imm8 & 0x03);
5905 }
5906
5907 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5908 assert(VM_Version::supports_avx(), "");
5909 assert(dst != xnoreg, "sanity");
5910 assert(imm8 <= 0x03, "imm8: %u", imm8);
5911 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5912 InstructionMark im(this);
5913 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5914 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5915 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5916 emit_int8(0x18);
5917 emit_operand(dst, src);
5918 // 0x00 - insert into q0 128 bits (0..127)
5919 // 0x01 - insert into q1 128 bits (128..255)
5920 // 0x02 - insert into q2 128 bits (256..383)
5921 // 0x03 - insert into q3 128 bits (384..511)
5922 emit_int8(imm8 & 0x03);
5923 }
5924
5925 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5926 assert(VM_Version::supports_evex(), "");
5927 assert(imm8 <= 0x01, "imm8: %u", imm8);
5928 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5929 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5930 emit_int8(0x1A);
5931 emit_int8((unsigned char)(0xC0 | encode));
5932 // 0x00 - insert into lower 256 bits
5933 // 0x01 - insert into upper 256 bits
5934 emit_int8(imm8 & 0x01);
5935 }
5936
5937 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5938 assert(VM_Version::supports_evex(), "");
5939 assert(dst != xnoreg, "sanity");
5940 assert(imm8 <= 0x01, "imm8: %u", imm8);
5941 InstructionMark im(this);
5942 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5943 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5944 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5945 emit_int8(0x1A);
5946 emit_operand(dst, src);
5947 // 0x00 - insert into lower 256 bits
5948 // 0x01 - insert into upper 256 bits
5949 emit_int8(imm8 & 0x01);
5950 }
5951
5952
5953 // vextracti forms
5954
5955 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5956 assert(VM_Version::supports_avx(), "");
5957 assert(imm8 <= 0x01, "imm8: %u", imm8);
5958 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5959 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5960 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5961 emit_int8(0x39);
5962 emit_int8((unsigned char)(0xC0 | encode));
5963 // 0x00 - extract from lower 128 bits
5964 // 0x01 - extract from upper 128 bits
5965 emit_int8(imm8 & 0x01);
5966 }
5967
5968 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5969 assert(VM_Version::supports_avx2(), "");
5970 assert(src != xnoreg, "sanity");
5971 assert(imm8 <= 0x01, "imm8: %u", imm8);
5972 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5973 InstructionMark im(this);
5974 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5975 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5976 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5977 emit_int8(0x39);
5978 emit_operand(src, dst);
5979 // 0x00 - extract from lower 128 bits
5980 // 0x01 - extract from upper 128 bits
5981 emit_int8(imm8 & 0x01);
5982 }
5983
5984 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5985 assert(VM_Version::supports_avx(), "");
5986 assert(imm8 <= 0x03, "imm8: %u", imm8);
5987 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5988 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5989 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5990 emit_int8(0x39);
5991 emit_int8((unsigned char)(0xC0 | encode));
5992 // 0x00 - extract from bits 127:0
5993 // 0x01 - extract from bits 255:128
5994 // 0x02 - extract from bits 383:256
5995 // 0x03 - extract from bits 511:384
5996 emit_int8(imm8 & 0x03);
5997 }
5998
5999 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6000 assert(VM_Version::supports_evex(), "");
6001 assert(src != xnoreg, "sanity");
6002 assert(imm8 <= 0x03, "imm8: %u", imm8);
6003 InstructionMark im(this);
6004 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6005 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6006 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6007 emit_int8(0x39);
6008 emit_operand(src, dst);
6009 // 0x00 - extract from bits 127:0
6010 // 0x01 - extract from bits 255:128
6011 // 0x02 - extract from bits 383:256
6012 // 0x03 - extract from bits 511:384
6013 emit_int8(imm8 & 0x03);
6014 }
6015
6016 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6017 assert(VM_Version::supports_avx512dq(), "");
6018 assert(imm8 <= 0x03, "imm8: %u", imm8);
6019 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6020 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6021 emit_int8(0x39);
6022 emit_int8((unsigned char)(0xC0 | encode));
6023 // 0x00 - extract from bits 127:0
6024 // 0x01 - extract from bits 255:128
6025 // 0x02 - extract from bits 383:256
6026 // 0x03 - extract from bits 511:384
6027 emit_int8(imm8 & 0x03);
6028 }
6029
6030 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6031 assert(VM_Version::supports_evex(), "");
6032 assert(imm8 <= 0x01, "imm8: %u", imm8);
6033 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6034 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6035 emit_int8(0x3B);
6036 emit_int8((unsigned char)(0xC0 | encode));
6037 // 0x00 - extract from lower 256 bits
6038 // 0x01 - extract from upper 256 bits
6039 emit_int8(imm8 & 0x01);
6040 }
6041
6042
6043 // vextractf forms
6044
6045 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6046 assert(VM_Version::supports_avx(), "");
6047 assert(imm8 <= 0x01, "imm8: %u", imm8);
6048 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6049 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6050 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6051 emit_int8(0x19);
6052 emit_int8((unsigned char)(0xC0 | encode));
6053 // 0x00 - extract from lower 128 bits
6054 // 0x01 - extract from upper 128 bits
6055 emit_int8(imm8 & 0x01);
6056 }
6057
6058 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6059 assert(VM_Version::supports_avx(), "");
6060 assert(src != xnoreg, "sanity");
6061 assert(imm8 <= 0x01, "imm8: %u", imm8);
6062 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6063 InstructionMark im(this);
6064 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6065 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6066 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6067 emit_int8(0x19);
6068 emit_operand(src, dst);
6069 // 0x00 - extract from lower 128 bits
6070 // 0x01 - extract from upper 128 bits
6071 emit_int8(imm8 & 0x01);
6072 }
6073
6074 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6075 assert(VM_Version::supports_avx(), "");
6076 assert(imm8 <= 0x03, "imm8: %u", imm8);
6077 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6079 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6080 emit_int8(0x19);
6081 emit_int8((unsigned char)(0xC0 | encode));
6082 // 0x00 - extract from bits 127:0
6083 // 0x01 - extract from bits 255:128
6084 // 0x02 - extract from bits 383:256
6085 // 0x03 - extract from bits 511:384
6086 emit_int8(imm8 & 0x03);
6087 }
6088
6089 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6090 assert(VM_Version::supports_evex(), "");
6091 assert(src != xnoreg, "sanity");
6092 assert(imm8 <= 0x03, "imm8: %u", imm8);
6093 InstructionMark im(this);
6094 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6095 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6096 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6097 emit_int8(0x19);
6098 emit_operand(src, dst);
6099 // 0x00 - extract from bits 127:0
6100 // 0x01 - extract from bits 255:128
6101 // 0x02 - extract from bits 383:256
6102 // 0x03 - extract from bits 511:384
6103 emit_int8(imm8 & 0x03);
6104 }
6105
6106 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6107 assert(VM_Version::supports_avx512dq(), "");
6108 assert(imm8 <= 0x03, "imm8: %u", imm8);
6109 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6110 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6111 emit_int8(0x19);
6112 emit_int8((unsigned char)(0xC0 | encode));
6113 // 0x00 - extract from bits 127:0
6114 // 0x01 - extract from bits 255:128
6115 // 0x02 - extract from bits 383:256
6116 // 0x03 - extract from bits 511:384
6117 emit_int8(imm8 & 0x03);
6118 }
6119
6120 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6121 assert(VM_Version::supports_evex(), "");
6122 assert(imm8 <= 0x01, "imm8: %u", imm8);
6123 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6124 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6125 emit_int8(0x1B);
6126 emit_int8((unsigned char)(0xC0 | encode));
6127 // 0x00 - extract from lower 256 bits
6128 // 0x01 - extract from upper 256 bits
6129 emit_int8(imm8 & 0x01);
6130 }
6131
6132 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6133 assert(VM_Version::supports_evex(), "");
6134 assert(src != xnoreg, "sanity");
6135 assert(imm8 <= 0x01, "imm8: %u", imm8);
6136 InstructionMark im(this);
6137 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6138 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6139 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6140 emit_int8(0x1B);
6141 emit_operand(src, dst);
6142 // 0x00 - extract from lower 256 bits
6143 // 0x01 - extract from upper 256 bits
6144 emit_int8(imm8 & 0x01);
6145 }
6146
6147
6148 // legacy word/dword replicate
6149 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6150 assert(VM_Version::supports_avx2(), "");
6151 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6152 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6153 emit_int8(0x79);
6154 emit_int8((unsigned char)(0xC0 | encode));
6155 }
6156
6157 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6158 assert(VM_Version::supports_avx2(), "");
6159 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6160 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6161 emit_int8(0x58);
6162 emit_int8((unsigned char)(0xC0 | encode));
6163 }
6164
6165
6166 // xmm/mem sourced byte/word/dword/qword replicate
6167
6168 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6169 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6170 assert(VM_Version::supports_evex(), "");
6171 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6172 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6173 emit_int8(0x78);
6174 emit_int8((unsigned char)(0xC0 | encode));
6175 }
6176
6177 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6178 assert(VM_Version::supports_evex(), "");
6179 assert(dst != xnoreg, "sanity");
6180 InstructionMark im(this);
6181 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6182 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6183 // swap src<->dst for encoding
6184 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6185 emit_int8(0x78);
6186 emit_operand(dst, src);
6187 }
6188
6189 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6190 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6191 assert(VM_Version::supports_evex(), "");
6192 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6193 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6194 emit_int8(0x79);
6195 emit_int8((unsigned char)(0xC0 | encode));
6196 }
6197
6198 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6199 assert(VM_Version::supports_evex(), "");
6200 assert(dst != xnoreg, "sanity");
6201 InstructionMark im(this);
6202 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6203 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6204 // swap src<->dst for encoding
6205 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6206 emit_int8(0x79);
6207 emit_operand(dst, src);
6208 }
6209
6210 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6211 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6212 assert(VM_Version::supports_evex(), "");
6213 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6214 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6215 emit_int8(0x58);
6216 emit_int8((unsigned char)(0xC0 | encode));
6217 }
6218
6219 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6220 assert(VM_Version::supports_evex(), "");
6221 assert(dst != xnoreg, "sanity");
6222 InstructionMark im(this);
6223 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6224 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6225 // swap src<->dst for encoding
6226 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6227 emit_int8(0x58);
6228 emit_operand(dst, src);
6229 }
6230
6231 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6232 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6233 assert(VM_Version::supports_evex(), "");
6234 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6235 attributes.set_rex_vex_w_reverted();
6236 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6237 emit_int8(0x59);
6238 emit_int8((unsigned char)(0xC0 | encode));
6239 }
6240
6241 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6242 assert(VM_Version::supports_evex(), "");
6243 assert(dst != xnoreg, "sanity");
6244 InstructionMark im(this);
6245 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6246 attributes.set_rex_vex_w_reverted();
6247 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6248 // swap src<->dst for encoding
6249 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6250 emit_int8(0x59);
6251 emit_operand(dst, src);
6252 }
6253
6254
6255 // scalar single/double precision replicate
6256
6257 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6258 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6259 assert(VM_Version::supports_evex(), "");
6260 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6261 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6262 emit_int8(0x18);
6263 emit_int8((unsigned char)(0xC0 | encode));
6264 }
6265
6266 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6267 assert(VM_Version::supports_evex(), "");
6268 assert(dst != xnoreg, "sanity");
6269 InstructionMark im(this);
6270 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6271 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6272 // swap src<->dst for encoding
6273 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6274 emit_int8(0x18);
6275 emit_operand(dst, src);
6276 }
6277
6278 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6279 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6280 assert(VM_Version::supports_evex(), "");
6281 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6282 attributes.set_rex_vex_w_reverted();
6283 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6284 emit_int8(0x19);
6285 emit_int8((unsigned char)(0xC0 | encode));
6286 }
6287
6288 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6289 assert(VM_Version::supports_evex(), "");
6290 assert(dst != xnoreg, "sanity");
6291 InstructionMark im(this);
6292 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6293 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6294 attributes.set_rex_vex_w_reverted();
6295 // swap src<->dst for encoding
6296 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6297 emit_int8(0x19);
6298 emit_operand(dst, src);
6299 }
6300
6301
6302 // gpr source broadcast forms
6303
6304 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6305 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6306 assert(VM_Version::supports_evex(), "");
6307 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6308 attributes.set_is_evex_instruction();
6309 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6310 emit_int8(0x7A);
6311 emit_int8((unsigned char)(0xC0 | encode));
6312 }
6313
6314 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6315 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6316 assert(VM_Version::supports_evex(), "");
6317 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6318 attributes.set_is_evex_instruction();
6319 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6320 emit_int8(0x7B);
6321 emit_int8((unsigned char)(0xC0 | encode));
6322 }
6323
6324 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6325 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6326 assert(VM_Version::supports_evex(), "");
6327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6328 attributes.set_is_evex_instruction();
6329 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6330 emit_int8(0x7C);
6331 emit_int8((unsigned char)(0xC0 | encode));
6332 }
6333
6334 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6335 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6336 assert(VM_Version::supports_evex(), "");
6337 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6338 attributes.set_is_evex_instruction();
6339 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6340 emit_int8(0x7C);
6341 emit_int8((unsigned char)(0xC0 | encode));
6342 }
6343
6344
6345 // Carry-Less Multiplication Quadword
6346 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6347 assert(VM_Version::supports_clmul(), "");
6348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6350 emit_int8(0x44);
6351 emit_int8((unsigned char)(0xC0 | encode));
6352 emit_int8((unsigned char)mask);
6353 }
6354
6355 // Carry-Less Multiplication Quadword
6356 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6357 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6358 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6360 emit_int8(0x44);
6361 emit_int8((unsigned char)(0xC0 | encode));
6362 emit_int8((unsigned char)mask);
6363 }
6364
6365 void Assembler::vzeroupper() {
6366 assert(VM_Version::supports_avx(), "");
6367 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6368 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6369 emit_int8(0x77);
6370 }
6371
6372
6373 #ifndef _LP64
6374 // 32bit only pieces of the assembler
6375
6376 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6377 // NO PREFIX AS NEVER 64BIT
6378 InstructionMark im(this);
6379 emit_int8((unsigned char)0x81);
6380 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6381 emit_data(imm32, rspec, 0);
6382 }
6383
6384 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6385 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6386 InstructionMark im(this);
6387 emit_int8((unsigned char)0x81);
6388 emit_operand(rdi, src1);
6389 emit_data(imm32, rspec, 0);
6390 }
6391
6392 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6393 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6394 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6395 void Assembler::cmpxchg8(Address adr) {
6396 InstructionMark im(this);
6397 emit_int8(0x0F);
6398 emit_int8((unsigned char)0xC7);
6399 emit_operand(rcx, adr);
6400 }
6401
6402 void Assembler::decl(Register dst) {
6403 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6404 emit_int8(0x48 | dst->encoding());
6405 }
6406
6407 #endif // _LP64
6408
6409 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6410
6411 void Assembler::fabs() {
6412 emit_int8((unsigned char)0xD9);
6413 emit_int8((unsigned char)0xE1);
6414 }
6415
6416 void Assembler::fadd(int i) {
6417 emit_farith(0xD8, 0xC0, i);
6418 }
6419
6420 void Assembler::fadd_d(Address src) {
6421 InstructionMark im(this);
6422 emit_int8((unsigned char)0xDC);
6423 emit_operand32(rax, src);
6424 }
6425
6426 void Assembler::fadd_s(Address src) {
6427 InstructionMark im(this);
6428 emit_int8((unsigned char)0xD8);
6429 emit_operand32(rax, src);
6430 }
6431
6432 void Assembler::fadda(int i) {
6433 emit_farith(0xDC, 0xC0, i);
6434 }
6435
6436 void Assembler::faddp(int i) {
6437 emit_farith(0xDE, 0xC0, i);
6438 }
6439
6440 void Assembler::fchs() {
6441 emit_int8((unsigned char)0xD9);
6442 emit_int8((unsigned char)0xE0);
6443 }
6444
6445 void Assembler::fcom(int i) {
6446 emit_farith(0xD8, 0xD0, i);
6447 }
6448
6449 void Assembler::fcomp(int i) {
6450 emit_farith(0xD8, 0xD8, i);
6451 }
6452
6453 void Assembler::fcomp_d(Address src) {
6454 InstructionMark im(this);
6455 emit_int8((unsigned char)0xDC);
6456 emit_operand32(rbx, src);
6457 }
6458
6459 void Assembler::fcomp_s(Address src) {
6460 InstructionMark im(this);
6461 emit_int8((unsigned char)0xD8);
6462 emit_operand32(rbx, src);
6463 }
6464
6465 void Assembler::fcompp() {
6466 emit_int8((unsigned char)0xDE);
6467 emit_int8((unsigned char)0xD9);
6468 }
6469
6470 void Assembler::fcos() {
6471 emit_int8((unsigned char)0xD9);
6472 emit_int8((unsigned char)0xFF);
6473 }
6474
6475 void Assembler::fdecstp() {
6476 emit_int8((unsigned char)0xD9);
6477 emit_int8((unsigned char)0xF6);
6478 }
6479
6480 void Assembler::fdiv(int i) {
6481 emit_farith(0xD8, 0xF0, i);
6482 }
6483
6484 void Assembler::fdiv_d(Address src) {
6485 InstructionMark im(this);
6486 emit_int8((unsigned char)0xDC);
6487 emit_operand32(rsi, src);
6488 }
6489
6490 void Assembler::fdiv_s(Address src) {
6491 InstructionMark im(this);
6492 emit_int8((unsigned char)0xD8);
6493 emit_operand32(rsi, src);
6494 }
6495
6496 void Assembler::fdiva(int i) {
6497 emit_farith(0xDC, 0xF8, i);
6498 }
6499
6500 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6501 // is erroneous for some of the floating-point instructions below.
6502
6503 void Assembler::fdivp(int i) {
6504 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6505 }
6506
6507 void Assembler::fdivr(int i) {
6508 emit_farith(0xD8, 0xF8, i);
6509 }
6510
6511 void Assembler::fdivr_d(Address src) {
6512 InstructionMark im(this);
6513 emit_int8((unsigned char)0xDC);
6514 emit_operand32(rdi, src);
6515 }
6516
6517 void Assembler::fdivr_s(Address src) {
6518 InstructionMark im(this);
6519 emit_int8((unsigned char)0xD8);
6520 emit_operand32(rdi, src);
6521 }
6522
6523 void Assembler::fdivra(int i) {
6524 emit_farith(0xDC, 0xF0, i);
6525 }
6526
6527 void Assembler::fdivrp(int i) {
6528 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6529 }
6530
6531 void Assembler::ffree(int i) {
6532 emit_farith(0xDD, 0xC0, i);
6533 }
6534
6535 void Assembler::fild_d(Address adr) {
6536 InstructionMark im(this);
6537 emit_int8((unsigned char)0xDF);
6538 emit_operand32(rbp, adr);
6539 }
6540
6541 void Assembler::fild_s(Address adr) {
6542 InstructionMark im(this);
6543 emit_int8((unsigned char)0xDB);
6544 emit_operand32(rax, adr);
6545 }
6546
6547 void Assembler::fincstp() {
6548 emit_int8((unsigned char)0xD9);
6549 emit_int8((unsigned char)0xF7);
6550 }
6551
6552 void Assembler::finit() {
6553 emit_int8((unsigned char)0x9B);
6554 emit_int8((unsigned char)0xDB);
6555 emit_int8((unsigned char)0xE3);
6556 }
6557
6558 void Assembler::fist_s(Address adr) {
6559 InstructionMark im(this);
6560 emit_int8((unsigned char)0xDB);
6561 emit_operand32(rdx, adr);
6562 }
6563
6564 void Assembler::fistp_d(Address adr) {
6565 InstructionMark im(this);
6566 emit_int8((unsigned char)0xDF);
6567 emit_operand32(rdi, adr);
6568 }
6569
6570 void Assembler::fistp_s(Address adr) {
6571 InstructionMark im(this);
6572 emit_int8((unsigned char)0xDB);
6573 emit_operand32(rbx, adr);
6574 }
6575
6576 void Assembler::fld1() {
6577 emit_int8((unsigned char)0xD9);
6578 emit_int8((unsigned char)0xE8);
6579 }
6580
6581 void Assembler::fld_d(Address adr) {
6582 InstructionMark im(this);
6583 emit_int8((unsigned char)0xDD);
6584 emit_operand32(rax, adr);
6585 }
6586
6587 void Assembler::fld_s(Address adr) {
6588 InstructionMark im(this);
6589 emit_int8((unsigned char)0xD9);
6590 emit_operand32(rax, adr);
6591 }
6592
6593
6594 void Assembler::fld_s(int index) {
6595 emit_farith(0xD9, 0xC0, index);
6596 }
6597
6598 void Assembler::fld_x(Address adr) {
6599 InstructionMark im(this);
6600 emit_int8((unsigned char)0xDB);
6601 emit_operand32(rbp, adr);
6602 }
6603
6604 void Assembler::fldcw(Address src) {
6605 InstructionMark im(this);
6606 emit_int8((unsigned char)0xD9);
6607 emit_operand32(rbp, src);
6608 }
6609
6610 void Assembler::fldenv(Address src) {
6611 InstructionMark im(this);
6612 emit_int8((unsigned char)0xD9);
6613 emit_operand32(rsp, src);
6614 }
6615
6616 void Assembler::fldlg2() {
6617 emit_int8((unsigned char)0xD9);
6618 emit_int8((unsigned char)0xEC);
6619 }
6620
6621 void Assembler::fldln2() {
6622 emit_int8((unsigned char)0xD9);
6623 emit_int8((unsigned char)0xED);
6624 }
6625
6626 void Assembler::fldz() {
6627 emit_int8((unsigned char)0xD9);
6628 emit_int8((unsigned char)0xEE);
6629 }
6630
6631 void Assembler::flog() {
6632 fldln2();
6633 fxch();
6634 fyl2x();
6635 }
6636
6637 void Assembler::flog10() {
6638 fldlg2();
6639 fxch();
6640 fyl2x();
6641 }
6642
6643 void Assembler::fmul(int i) {
6644 emit_farith(0xD8, 0xC8, i);
6645 }
6646
6647 void Assembler::fmul_d(Address src) {
6648 InstructionMark im(this);
6649 emit_int8((unsigned char)0xDC);
6650 emit_operand32(rcx, src);
6651 }
6652
6653 void Assembler::fmul_s(Address src) {
6654 InstructionMark im(this);
6655 emit_int8((unsigned char)0xD8);
6656 emit_operand32(rcx, src);
6657 }
6658
6659 void Assembler::fmula(int i) {
6660 emit_farith(0xDC, 0xC8, i);
6661 }
6662
6663 void Assembler::fmulp(int i) {
6664 emit_farith(0xDE, 0xC8, i);
6665 }
6666
6667 void Assembler::fnsave(Address dst) {
6668 InstructionMark im(this);
6669 emit_int8((unsigned char)0xDD);
6670 emit_operand32(rsi, dst);
6671 }
6672
6673 void Assembler::fnstcw(Address src) {
6674 InstructionMark im(this);
6675 emit_int8((unsigned char)0x9B);
6676 emit_int8((unsigned char)0xD9);
6677 emit_operand32(rdi, src);
6678 }
6679
6680 void Assembler::fnstsw_ax() {
6681 emit_int8((unsigned char)0xDF);
6682 emit_int8((unsigned char)0xE0);
6683 }
6684
6685 void Assembler::fprem() {
6686 emit_int8((unsigned char)0xD9);
6687 emit_int8((unsigned char)0xF8);
6688 }
6689
6690 void Assembler::fprem1() {
6691 emit_int8((unsigned char)0xD9);
6692 emit_int8((unsigned char)0xF5);
6693 }
6694
6695 void Assembler::frstor(Address src) {
6696 InstructionMark im(this);
6697 emit_int8((unsigned char)0xDD);
6698 emit_operand32(rsp, src);
6699 }
6700
6701 void Assembler::fsin() {
6702 emit_int8((unsigned char)0xD9);
6703 emit_int8((unsigned char)0xFE);
6704 }
6705
6706 void Assembler::fsqrt() {
6707 emit_int8((unsigned char)0xD9);
6708 emit_int8((unsigned char)0xFA);
6709 }
6710
6711 void Assembler::fst_d(Address adr) {
6712 InstructionMark im(this);
6713 emit_int8((unsigned char)0xDD);
6714 emit_operand32(rdx, adr);
6715 }
6716
6717 void Assembler::fst_s(Address adr) {
6718 InstructionMark im(this);
6719 emit_int8((unsigned char)0xD9);
6720 emit_operand32(rdx, adr);
6721 }
6722
6723 void Assembler::fstp_d(Address adr) {
6724 InstructionMark im(this);
6725 emit_int8((unsigned char)0xDD);
6726 emit_operand32(rbx, adr);
6727 }
6728
6729 void Assembler::fstp_d(int index) {
6730 emit_farith(0xDD, 0xD8, index);
6731 }
6732
6733 void Assembler::fstp_s(Address adr) {
6734 InstructionMark im(this);
6735 emit_int8((unsigned char)0xD9);
6736 emit_operand32(rbx, adr);
6737 }
6738
6739 void Assembler::fstp_x(Address adr) {
6740 InstructionMark im(this);
6741 emit_int8((unsigned char)0xDB);
6742 emit_operand32(rdi, adr);
6743 }
6744
6745 void Assembler::fsub(int i) {
6746 emit_farith(0xD8, 0xE0, i);
6747 }
6748
6749 void Assembler::fsub_d(Address src) {
6750 InstructionMark im(this);
6751 emit_int8((unsigned char)0xDC);
6752 emit_operand32(rsp, src);
6753 }
6754
6755 void Assembler::fsub_s(Address src) {
6756 InstructionMark im(this);
6757 emit_int8((unsigned char)0xD8);
6758 emit_operand32(rsp, src);
6759 }
6760
6761 void Assembler::fsuba(int i) {
6762 emit_farith(0xDC, 0xE8, i);
6763 }
6764
6765 void Assembler::fsubp(int i) {
6766 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6767 }
6768
6769 void Assembler::fsubr(int i) {
6770 emit_farith(0xD8, 0xE8, i);
6771 }
6772
6773 void Assembler::fsubr_d(Address src) {
6774 InstructionMark im(this);
6775 emit_int8((unsigned char)0xDC);
6776 emit_operand32(rbp, src);
6777 }
6778
6779 void Assembler::fsubr_s(Address src) {
6780 InstructionMark im(this);
6781 emit_int8((unsigned char)0xD8);
6782 emit_operand32(rbp, src);
6783 }
6784
6785 void Assembler::fsubra(int i) {
6786 emit_farith(0xDC, 0xE0, i);
6787 }
6788
6789 void Assembler::fsubrp(int i) {
6790 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6791 }
6792
6793 void Assembler::ftan() {
6794 emit_int8((unsigned char)0xD9);
6795 emit_int8((unsigned char)0xF2);
6796 emit_int8((unsigned char)0xDD);
6797 emit_int8((unsigned char)0xD8);
6798 }
6799
6800 void Assembler::ftst() {
6801 emit_int8((unsigned char)0xD9);
6802 emit_int8((unsigned char)0xE4);
6803 }
6804
6805 void Assembler::fucomi(int i) {
6806 // make sure the instruction is supported (introduced for P6, together with cmov)
6807 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6808 emit_farith(0xDB, 0xE8, i);
6809 }
6810
6811 void Assembler::fucomip(int i) {
6812 // make sure the instruction is supported (introduced for P6, together with cmov)
6813 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6814 emit_farith(0xDF, 0xE8, i);
6815 }
6816
6817 void Assembler::fwait() {
6818 emit_int8((unsigned char)0x9B);
6819 }
6820
6821 void Assembler::fxch(int i) {
6822 emit_farith(0xD9, 0xC8, i);
6823 }
6824
6825 void Assembler::fyl2x() {
6826 emit_int8((unsigned char)0xD9);
6827 emit_int8((unsigned char)0xF1);
6828 }
6829
6830 void Assembler::frndint() {
6831 emit_int8((unsigned char)0xD9);
6832 emit_int8((unsigned char)0xFC);
6833 }
6834
6835 void Assembler::f2xm1() {
6836 emit_int8((unsigned char)0xD9);
6837 emit_int8((unsigned char)0xF0);
6838 }
6839
6840 void Assembler::fldl2e() {
6841 emit_int8((unsigned char)0xD9);
6842 emit_int8((unsigned char)0xEA);
6843 }
6844
6845 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6846 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6847 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6848 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6849
6850 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6851 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6852 if (pre > 0) {
6853 emit_int8(simd_pre[pre]);
6854 }
6855 if (rex_w) {
6856 prefixq(adr, xreg);
6857 } else {
6858 prefix(adr, xreg);
6859 }
6860 if (opc > 0) {
6861 emit_int8(0x0F);
6862 int opc2 = simd_opc[opc];
6863 if (opc2 > 0) {
6864 emit_int8(opc2);
6865 }
6866 }
6867 }
6868
6869 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6870 if (pre > 0) {
6871 emit_int8(simd_pre[pre]);
6872 }
6873 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6874 if (opc > 0) {
6875 emit_int8(0x0F);
6876 int opc2 = simd_opc[opc];
6877 if (opc2 > 0) {
6878 emit_int8(opc2);
6879 }
6880 }
6881 return encode;
6882 }
6883
6884
6885 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6886 int vector_len = _attributes->get_vector_len();
6887 bool vex_w = _attributes->is_rex_vex_w();
6888 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6889 prefix(VEX_3bytes);
6890
6891 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6892 byte1 = (~byte1) & 0xE0;
6893 byte1 |= opc;
6894 emit_int8(byte1);
6895
6896 int byte2 = ((~nds_enc) & 0xf) << 3;
6897 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6898 emit_int8(byte2);
6899 } else {
6900 prefix(VEX_2bytes);
6901
6902 int byte1 = vex_r ? VEX_R : 0;
6903 byte1 = (~byte1) & 0x80;
6904 byte1 |= ((~nds_enc) & 0xf) << 3;
6905 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6906 emit_int8(byte1);
6907 }
6908 }
6909
6910 // This is a 4 byte encoding
6911 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6912 // EVEX 0x62 prefix
6913 prefix(EVEX_4bytes);
6914 bool vex_w = _attributes->is_rex_vex_w();
6915 int evex_encoding = (vex_w ? VEX_W : 0);
6916 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6917 _attributes->set_evex_encoding(evex_encoding);
6918
6919 // P0: byte 2, initialized to RXBR`00mm
6920 // instead of not'd
6921 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6922 byte2 = (~byte2) & 0xF0;
6923 // confine opc opcode extensions in mm bits to lower two bits
6924 // of form {0F, 0F_38, 0F_3A}
6925 byte2 |= opc;
6926 emit_int8(byte2);
6927
6928 // P1: byte 3 as Wvvvv1pp
6929 int byte3 = ((~nds_enc) & 0xf) << 3;
6930 // p[10] is always 1
6931 byte3 |= EVEX_F;
6932 byte3 |= (vex_w & 1) << 7;
6933 // confine pre opcode extensions in pp bits to lower two bits
6934 // of form {66, F3, F2}
6935 byte3 |= pre;
6936 emit_int8(byte3);
6937
6938 // P2: byte 4 as zL'Lbv'aaa
6939 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6940 // EVEX.v` for extending EVEX.vvvv or VIDX
6941 byte4 |= (evex_v ? 0: EVEX_V);
6942 // third EXEC.b for broadcast actions
6943 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6944 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6945 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6946 // last is EVEX.z for zero/merge actions
6947 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6948 emit_int8(byte4);
6949 }
6950
6951 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6952 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6953 bool vex_b = adr.base_needs_rex();
6954 bool vex_x = adr.index_needs_rex();
6955 set_attributes(attributes);
6956 attributes->set_current_assembler(this);
6957
6958 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6959 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6960 switch (attributes->get_vector_len()) {
6961 case AVX_128bit:
6962 case AVX_256bit:
6963 attributes->set_is_legacy_mode();
6964 break;
6965 }
6966 }
6967
6968 // For pure EVEX check and see if this instruction
6969 // is allowed in legacy mode and has resources which will
6970 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6971 // else that field is set when we encode to EVEX
6972 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6973 !_is_managed && !attributes->is_evex_instruction()) {
6974 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6975 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6976 if (check_register_bank) {
6977 // check nds_enc and xreg_enc for upper bank usage
6978 if (nds_enc < 16 && xreg_enc < 16) {
6979 attributes->set_is_legacy_mode();
6980 }
6981 } else {
6982 attributes->set_is_legacy_mode();
6983 }
6984 }
6985 }
6986
6987 _is_managed = false;
6988 if (UseAVX > 2 && !attributes->is_legacy_mode())
6989 {
6990 bool evex_r = (xreg_enc >= 16);
6991 bool evex_v = (nds_enc >= 16);
6992 attributes->set_is_evex_instruction();
6993 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6994 } else {
6995 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
6996 attributes->set_rex_vex_w(false);
6997 }
6998 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6999 }
7000 }
7001
7002 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7003 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7004 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7005 bool vex_x = false;
7006 set_attributes(attributes);
7007 attributes->set_current_assembler(this);
7008 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7009
7010 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7011 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7012 switch (attributes->get_vector_len()) {
7013 case AVX_128bit:
7014 case AVX_256bit:
7015 if (check_register_bank) {
7016 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7017 // up propagate arithmetic instructions to meet RA requirements
7018 attributes->set_vector_len(AVX_512bit);
7019 } else {
7020 attributes->set_is_legacy_mode();
7021 }
7022 } else {
7023 attributes->set_is_legacy_mode();
7024 }
7025 break;
7026 }
7027 }
7028
7029 // For pure EVEX check and see if this instruction
7030 // is allowed in legacy mode and has resources which will
7031 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7032 // else that field is set when we encode to EVEX
7033 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7034 !_is_managed && !attributes->is_evex_instruction()) {
7035 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7036 if (check_register_bank) {
7037 // check dst_enc, nds_enc and src_enc for upper bank usage
7038 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7039 attributes->set_is_legacy_mode();
7040 }
7041 } else {
7042 attributes->set_is_legacy_mode();
7043 }
7044 }
7045 }
7046
7047 _is_managed = false;
7048 if (UseAVX > 2 && !attributes->is_legacy_mode())
7049 {
7050 bool evex_r = (dst_enc >= 16);
7051 bool evex_v = (nds_enc >= 16);
7052 // can use vex_x as bank extender on rm encoding
7053 vex_x = (src_enc >= 16);
7054 attributes->set_is_evex_instruction();
7055 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7056 } else {
7057 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7058 attributes->set_rex_vex_w(false);
7059 }
7060 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7061 }
7062
7063 // return modrm byte components for operands
7064 return (((dst_enc & 7) << 3) | (src_enc & 7));
7065 }
7066
7067
7068 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7069 VexOpcode opc, InstructionAttr *attributes) {
7070 if (UseAVX > 0) {
7071 int xreg_enc = xreg->encoding();
7072 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7073 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7074 } else {
7075 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7076 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7077 }
7078 }
7079
7080 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7081 VexOpcode opc, InstructionAttr *attributes) {
7082 int dst_enc = dst->encoding();
7083 int src_enc = src->encoding();
7084 if (UseAVX > 0) {
7085 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7086 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7087 } else {
7088 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7089 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7090 }
7091 }
7092
7093 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7094 assert(VM_Version::supports_avx(), "");
7095 assert(!VM_Version::supports_evex(), "");
7096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7097 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7098 emit_int8((unsigned char)0xC2);
7099 emit_int8((unsigned char)(0xC0 | encode));
7100 emit_int8((unsigned char)(0xF & cop));
7101 }
7102
7103 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7104 assert(VM_Version::supports_avx(), "");
7105 assert(!VM_Version::supports_evex(), "");
7106 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7107 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7108 emit_int8((unsigned char)0x4B);
7109 emit_int8((unsigned char)(0xC0 | encode));
7110 int src2_enc = src2->encoding();
7111 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7112 }
7113
7114 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7115 assert(VM_Version::supports_bmi2(), "");
7116 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7117 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7118 emit_int8((unsigned char)0xF7);
7119 emit_int8((unsigned char)(0xC0 | encode));
7120 }
7121
7122 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7123 assert(VM_Version::supports_bmi2(), "");
7124 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7125 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7126 emit_int8((unsigned char)0xF7);
7127 emit_int8((unsigned char)(0xC0 | encode));
7128 }
7129
7130 #ifndef _LP64
7131
7132 void Assembler::incl(Register dst) {
7133 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7134 emit_int8(0x40 | dst->encoding());
7135 }
7136
7137 void Assembler::lea(Register dst, Address src) {
7138 leal(dst, src);
7139 }
7140
7141 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7142 InstructionMark im(this);
7143 emit_int8((unsigned char)0xC7);
7144 emit_operand(rax, dst);
7145 emit_data((int)imm32, rspec, 0);
7146 }
7147
7148 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7149 InstructionMark im(this);
7150 int encode = prefix_and_encode(dst->encoding());
7151 emit_int8((unsigned char)(0xB8 | encode));
7152 emit_data((int)imm32, rspec, 0);
7153 }
7154
7155 void Assembler::popa() { // 32bit
7156 emit_int8(0x61);
7157 }
7158
7159 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7160 InstructionMark im(this);
7161 emit_int8(0x68);
7162 emit_data(imm32, rspec, 0);
7163 }
7164
7165 void Assembler::pusha() { // 32bit
7166 emit_int8(0x60);
7167 }
7168
7169 void Assembler::set_byte_if_not_zero(Register dst) {
7170 emit_int8(0x0F);
7171 emit_int8((unsigned char)0x95);
7172 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7173 }
7174
7175 void Assembler::shldl(Register dst, Register src) {
7176 emit_int8(0x0F);
7177 emit_int8((unsigned char)0xA5);
7178 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7179 }
7180
7181 // 0F A4 / r ib
7182 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7183 emit_int8(0x0F);
7184 emit_int8((unsigned char)0xA4);
7185 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7186 emit_int8(imm8);
7187 }
7188
7189 void Assembler::shrdl(Register dst, Register src) {
7190 emit_int8(0x0F);
7191 emit_int8((unsigned char)0xAD);
7192 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7193 }
7194
7195 #else // LP64
7196
7197 void Assembler::set_byte_if_not_zero(Register dst) {
7198 int enc = prefix_and_encode(dst->encoding(), true);
7199 emit_int8(0x0F);
7200 emit_int8((unsigned char)0x95);
7201 emit_int8((unsigned char)(0xE0 | enc));
7202 }
7203
7204 // 64bit only pieces of the assembler
7205 // This should only be used by 64bit instructions that can use rip-relative
7206 // it cannot be used by instructions that want an immediate value.
7207
7208 bool Assembler::reachable(AddressLiteral adr) {
7209 int64_t disp;
7210 // None will force a 64bit literal to the code stream. Likely a placeholder
7211 // for something that will be patched later and we need to certain it will
7212 // always be reachable.
7213 if (adr.reloc() == relocInfo::none) {
7214 return false;
7215 }
7216 if (adr.reloc() == relocInfo::internal_word_type) {
7217 // This should be rip relative and easily reachable.
7218 return true;
7219 }
7220 if (adr.reloc() == relocInfo::virtual_call_type ||
7221 adr.reloc() == relocInfo::opt_virtual_call_type ||
7222 adr.reloc() == relocInfo::static_call_type ||
7223 adr.reloc() == relocInfo::static_stub_type ) {
7224 // This should be rip relative within the code cache and easily
7225 // reachable until we get huge code caches. (At which point
7226 // ic code is going to have issues).
7227 return true;
7228 }
7229 if (adr.reloc() != relocInfo::external_word_type &&
7230 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7231 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7232 adr.reloc() != relocInfo::runtime_call_type ) {
7233 return false;
7234 }
7235
7236 // Stress the correction code
7237 if (ForceUnreachable) {
7238 // Must be runtimecall reloc, see if it is in the codecache
7239 // Flipping stuff in the codecache to be unreachable causes issues
7240 // with things like inline caches where the additional instructions
7241 // are not handled.
7242 if (CodeCache::find_blob(adr._target) == NULL) {
7243 return false;
7244 }
7245 }
7246 // For external_word_type/runtime_call_type if it is reachable from where we
7247 // are now (possibly a temp buffer) and where we might end up
7248 // anywhere in the codeCache then we are always reachable.
7249 // This would have to change if we ever save/restore shared code
7250 // to be more pessimistic.
7251 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7252 if (!is_simm32(disp)) return false;
7253 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7254 if (!is_simm32(disp)) return false;
7255
7256 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7257
7258 // Because rip relative is a disp + address_of_next_instruction and we
7259 // don't know the value of address_of_next_instruction we apply a fudge factor
7260 // to make sure we will be ok no matter the size of the instruction we get placed into.
7261 // We don't have to fudge the checks above here because they are already worst case.
7262
7263 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7264 // + 4 because better safe than sorry.
7265 const int fudge = 12 + 4;
7266 if (disp < 0) {
7267 disp -= fudge;
7268 } else {
7269 disp += fudge;
7270 }
7271 return is_simm32(disp);
7272 }
7273
7274 // Check if the polling page is not reachable from the code cache using rip-relative
7275 // addressing.
7276 bool Assembler::is_polling_page_far() {
7277 intptr_t addr = (intptr_t)os::get_polling_page();
7278 return ForceUnreachable ||
7279 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7280 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7281 }
7282
7283 void Assembler::emit_data64(jlong data,
7284 relocInfo::relocType rtype,
7285 int format) {
7286 if (rtype == relocInfo::none) {
7287 emit_int64(data);
7288 } else {
7289 emit_data64(data, Relocation::spec_simple(rtype), format);
7290 }
7291 }
7292
7293 void Assembler::emit_data64(jlong data,
7294 RelocationHolder const& rspec,
7295 int format) {
7296 assert(imm_operand == 0, "default format must be immediate in this file");
7297 assert(imm_operand == format, "must be immediate");
7298 assert(inst_mark() != NULL, "must be inside InstructionMark");
7299 // Do not use AbstractAssembler::relocate, which is not intended for
7300 // embedded words. Instead, relocate to the enclosing instruction.
7301 code_section()->relocate(inst_mark(), rspec, format);
7302 #ifdef ASSERT
7303 check_relocation(rspec, format);
7304 #endif
7305 emit_int64(data);
7306 }
7307
7308 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7309 if (reg_enc >= 8) {
7310 prefix(REX_B);
7311 reg_enc -= 8;
7312 } else if (byteinst && reg_enc >= 4) {
7313 prefix(REX);
7314 }
7315 return reg_enc;
7316 }
7317
7318 int Assembler::prefixq_and_encode(int reg_enc) {
7319 if (reg_enc < 8) {
7320 prefix(REX_W);
7321 } else {
7322 prefix(REX_WB);
7323 reg_enc -= 8;
7324 }
7325 return reg_enc;
7326 }
7327
7328 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7329 if (dst_enc < 8) {
7330 if (src_enc >= 8) {
7331 prefix(REX_B);
7332 src_enc -= 8;
7333 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7334 prefix(REX);
7335 }
7336 } else {
7337 if (src_enc < 8) {
7338 prefix(REX_R);
7339 } else {
7340 prefix(REX_RB);
7341 src_enc -= 8;
7342 }
7343 dst_enc -= 8;
7344 }
7345 return dst_enc << 3 | src_enc;
7346 }
7347
7348 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7349 if (dst_enc < 8) {
7350 if (src_enc < 8) {
7351 prefix(REX_W);
7352 } else {
7353 prefix(REX_WB);
7354 src_enc -= 8;
7355 }
7356 } else {
7357 if (src_enc < 8) {
7358 prefix(REX_WR);
7359 } else {
7360 prefix(REX_WRB);
7361 src_enc -= 8;
7362 }
7363 dst_enc -= 8;
7364 }
7365 return dst_enc << 3 | src_enc;
7366 }
7367
7368 void Assembler::prefix(Register reg) {
7369 if (reg->encoding() >= 8) {
7370 prefix(REX_B);
7371 }
7372 }
7373
7374 void Assembler::prefix(Register dst, Register src, Prefix p) {
7375 if (src->encoding() >= 8) {
7376 p = (Prefix)(p | REX_B);
7377 }
7378 if (dst->encoding() >= 8) {
7379 p = (Prefix)( p | REX_R);
7380 }
7381 if (p != Prefix_EMPTY) {
7382 // do not generate an empty prefix
7383 prefix(p);
7384 }
7385 }
7386
7387 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7388 if (adr.base_needs_rex()) {
7389 if (adr.index_needs_rex()) {
7390 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7391 } else {
7392 prefix(REX_B);
7393 }
7394 } else {
7395 if (adr.index_needs_rex()) {
7396 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7397 }
7398 }
7399 if (dst->encoding() >= 8) {
7400 p = (Prefix)(p | REX_R);
7401 }
7402 if (p != Prefix_EMPTY) {
7403 // do not generate an empty prefix
7404 prefix(p);
7405 }
7406 }
7407
7408 void Assembler::prefix(Address adr) {
7409 if (adr.base_needs_rex()) {
7410 if (adr.index_needs_rex()) {
7411 prefix(REX_XB);
7412 } else {
7413 prefix(REX_B);
7414 }
7415 } else {
7416 if (adr.index_needs_rex()) {
7417 prefix(REX_X);
7418 }
7419 }
7420 }
7421
7422 void Assembler::prefixq(Address adr) {
7423 if (adr.base_needs_rex()) {
7424 if (adr.index_needs_rex()) {
7425 prefix(REX_WXB);
7426 } else {
7427 prefix(REX_WB);
7428 }
7429 } else {
7430 if (adr.index_needs_rex()) {
7431 prefix(REX_WX);
7432 } else {
7433 prefix(REX_W);
7434 }
7435 }
7436 }
7437
7438
7439 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7440 if (reg->encoding() < 8) {
7441 if (adr.base_needs_rex()) {
7442 if (adr.index_needs_rex()) {
7443 prefix(REX_XB);
7444 } else {
7445 prefix(REX_B);
7446 }
7447 } else {
7448 if (adr.index_needs_rex()) {
7449 prefix(REX_X);
7450 } else if (byteinst && reg->encoding() >= 4 ) {
7451 prefix(REX);
7452 }
7453 }
7454 } else {
7455 if (adr.base_needs_rex()) {
7456 if (adr.index_needs_rex()) {
7457 prefix(REX_RXB);
7458 } else {
7459 prefix(REX_RB);
7460 }
7461 } else {
7462 if (adr.index_needs_rex()) {
7463 prefix(REX_RX);
7464 } else {
7465 prefix(REX_R);
7466 }
7467 }
7468 }
7469 }
7470
7471 void Assembler::prefixq(Address adr, Register src) {
7472 if (src->encoding() < 8) {
7473 if (adr.base_needs_rex()) {
7474 if (adr.index_needs_rex()) {
7475 prefix(REX_WXB);
7476 } else {
7477 prefix(REX_WB);
7478 }
7479 } else {
7480 if (adr.index_needs_rex()) {
7481 prefix(REX_WX);
7482 } else {
7483 prefix(REX_W);
7484 }
7485 }
7486 } else {
7487 if (adr.base_needs_rex()) {
7488 if (adr.index_needs_rex()) {
7489 prefix(REX_WRXB);
7490 } else {
7491 prefix(REX_WRB);
7492 }
7493 } else {
7494 if (adr.index_needs_rex()) {
7495 prefix(REX_WRX);
7496 } else {
7497 prefix(REX_WR);
7498 }
7499 }
7500 }
7501 }
7502
7503 void Assembler::prefix(Address adr, XMMRegister reg) {
7504 if (reg->encoding() < 8) {
7505 if (adr.base_needs_rex()) {
7506 if (adr.index_needs_rex()) {
7507 prefix(REX_XB);
7508 } else {
7509 prefix(REX_B);
7510 }
7511 } else {
7512 if (adr.index_needs_rex()) {
7513 prefix(REX_X);
7514 }
7515 }
7516 } else {
7517 if (adr.base_needs_rex()) {
7518 if (adr.index_needs_rex()) {
7519 prefix(REX_RXB);
7520 } else {
7521 prefix(REX_RB);
7522 }
7523 } else {
7524 if (adr.index_needs_rex()) {
7525 prefix(REX_RX);
7526 } else {
7527 prefix(REX_R);
7528 }
7529 }
7530 }
7531 }
7532
7533 void Assembler::prefixq(Address adr, XMMRegister src) {
7534 if (src->encoding() < 8) {
7535 if (adr.base_needs_rex()) {
7536 if (adr.index_needs_rex()) {
7537 prefix(REX_WXB);
7538 } else {
7539 prefix(REX_WB);
7540 }
7541 } else {
7542 if (adr.index_needs_rex()) {
7543 prefix(REX_WX);
7544 } else {
7545 prefix(REX_W);
7546 }
7547 }
7548 } else {
7549 if (adr.base_needs_rex()) {
7550 if (adr.index_needs_rex()) {
7551 prefix(REX_WRXB);
7552 } else {
7553 prefix(REX_WRB);
7554 }
7555 } else {
7556 if (adr.index_needs_rex()) {
7557 prefix(REX_WRX);
7558 } else {
7559 prefix(REX_WR);
7560 }
7561 }
7562 }
7563 }
7564
7565 void Assembler::adcq(Register dst, int32_t imm32) {
7566 (void) prefixq_and_encode(dst->encoding());
7567 emit_arith(0x81, 0xD0, dst, imm32);
7568 }
7569
7570 void Assembler::adcq(Register dst, Address src) {
7571 InstructionMark im(this);
7572 prefixq(src, dst);
7573 emit_int8(0x13);
7574 emit_operand(dst, src);
7575 }
7576
7577 void Assembler::adcq(Register dst, Register src) {
7578 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7579 emit_arith(0x13, 0xC0, dst, src);
7580 }
7581
7582 void Assembler::addq(Address dst, int32_t imm32) {
7583 InstructionMark im(this);
7584 prefixq(dst);
7585 emit_arith_operand(0x81, rax, dst,imm32);
7586 }
7587
7588 void Assembler::addq(Address dst, Register src) {
7589 InstructionMark im(this);
7590 prefixq(dst, src);
7591 emit_int8(0x01);
7592 emit_operand(src, dst);
7593 }
7594
7595 void Assembler::addq(Register dst, int32_t imm32) {
7596 (void) prefixq_and_encode(dst->encoding());
7597 emit_arith(0x81, 0xC0, dst, imm32);
7598 }
7599
7600 void Assembler::addq(Register dst, Address src) {
7601 InstructionMark im(this);
7602 prefixq(src, dst);
7603 emit_int8(0x03);
7604 emit_operand(dst, src);
7605 }
7606
7607 void Assembler::addq(Register dst, Register src) {
7608 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7609 emit_arith(0x03, 0xC0, dst, src);
7610 }
7611
7612 void Assembler::adcxq(Register dst, Register src) {
7613 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7614 emit_int8((unsigned char)0x66);
7615 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7616 emit_int8(0x0F);
7617 emit_int8(0x38);
7618 emit_int8((unsigned char)0xF6);
7619 emit_int8((unsigned char)(0xC0 | encode));
7620 }
7621
7622 void Assembler::adoxq(Register dst, Register src) {
7623 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7624 emit_int8((unsigned char)0xF3);
7625 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7626 emit_int8(0x0F);
7627 emit_int8(0x38);
7628 emit_int8((unsigned char)0xF6);
7629 emit_int8((unsigned char)(0xC0 | encode));
7630 }
7631
7632 void Assembler::andq(Address dst, int32_t imm32) {
7633 InstructionMark im(this);
7634 prefixq(dst);
7635 emit_int8((unsigned char)0x81);
7636 emit_operand(rsp, dst, 4);
7637 emit_int32(imm32);
7638 }
7639
7640 void Assembler::andq(Register dst, int32_t imm32) {
7641 (void) prefixq_and_encode(dst->encoding());
7642 emit_arith(0x81, 0xE0, dst, imm32);
7643 }
7644
7645 void Assembler::andq(Register dst, Address src) {
7646 InstructionMark im(this);
7647 prefixq(src, dst);
7648 emit_int8(0x23);
7649 emit_operand(dst, src);
7650 }
7651
7652 void Assembler::andq(Register dst, Register src) {
7653 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7654 emit_arith(0x23, 0xC0, dst, src);
7655 }
7656
7657 void Assembler::andnq(Register dst, Register src1, Register src2) {
7658 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7659 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7660 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7661 emit_int8((unsigned char)0xF2);
7662 emit_int8((unsigned char)(0xC0 | encode));
7663 }
7664
7665 void Assembler::andnq(Register dst, Register src1, Address src2) {
7666 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7667 InstructionMark im(this);
7668 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7669 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7670 emit_int8((unsigned char)0xF2);
7671 emit_operand(dst, src2);
7672 }
7673
7674 void Assembler::bsfq(Register dst, Register src) {
7675 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7676 emit_int8(0x0F);
7677 emit_int8((unsigned char)0xBC);
7678 emit_int8((unsigned char)(0xC0 | encode));
7679 }
7680
7681 void Assembler::bsrq(Register dst, Register src) {
7682 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7683 emit_int8(0x0F);
7684 emit_int8((unsigned char)0xBD);
7685 emit_int8((unsigned char)(0xC0 | encode));
7686 }
7687
7688 void Assembler::bswapq(Register reg) {
7689 int encode = prefixq_and_encode(reg->encoding());
7690 emit_int8(0x0F);
7691 emit_int8((unsigned char)(0xC8 | encode));
7692 }
7693
7694 void Assembler::blsiq(Register dst, Register src) {
7695 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7696 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7697 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7698 emit_int8((unsigned char)0xF3);
7699 emit_int8((unsigned char)(0xC0 | encode));
7700 }
7701
7702 void Assembler::blsiq(Register dst, Address src) {
7703 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7704 InstructionMark im(this);
7705 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7706 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7707 emit_int8((unsigned char)0xF3);
7708 emit_operand(rbx, src);
7709 }
7710
7711 void Assembler::blsmskq(Register dst, Register src) {
7712 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7713 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7714 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7715 emit_int8((unsigned char)0xF3);
7716 emit_int8((unsigned char)(0xC0 | encode));
7717 }
7718
7719 void Assembler::blsmskq(Register dst, Address src) {
7720 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7721 InstructionMark im(this);
7722 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7723 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7724 emit_int8((unsigned char)0xF3);
7725 emit_operand(rdx, src);
7726 }
7727
7728 void Assembler::blsrq(Register dst, Register src) {
7729 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7730 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7731 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7732 emit_int8((unsigned char)0xF3);
7733 emit_int8((unsigned char)(0xC0 | encode));
7734 }
7735
7736 void Assembler::blsrq(Register dst, Address src) {
7737 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7738 InstructionMark im(this);
7739 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7740 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7741 emit_int8((unsigned char)0xF3);
7742 emit_operand(rcx, src);
7743 }
7744
7745 void Assembler::cdqq() {
7746 prefix(REX_W);
7747 emit_int8((unsigned char)0x99);
7748 }
7749
7750 void Assembler::clflush(Address adr) {
7751 prefix(adr);
7752 emit_int8(0x0F);
7753 emit_int8((unsigned char)0xAE);
7754 emit_operand(rdi, adr);
7755 }
7756
7757 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7758 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7759 emit_int8(0x0F);
7760 emit_int8(0x40 | cc);
7761 emit_int8((unsigned char)(0xC0 | encode));
7762 }
7763
7764 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7765 InstructionMark im(this);
7766 prefixq(src, dst);
7767 emit_int8(0x0F);
7768 emit_int8(0x40 | cc);
7769 emit_operand(dst, src);
7770 }
7771
7772 void Assembler::cmpq(Address dst, int32_t imm32) {
7773 InstructionMark im(this);
7774 prefixq(dst);
7775 emit_int8((unsigned char)0x81);
7776 emit_operand(rdi, dst, 4);
7777 emit_int32(imm32);
7778 }
7779
7780 void Assembler::cmpq(Register dst, int32_t imm32) {
7781 (void) prefixq_and_encode(dst->encoding());
7782 emit_arith(0x81, 0xF8, dst, imm32);
7783 }
7784
7785 void Assembler::cmpq(Address dst, Register src) {
7786 InstructionMark im(this);
7787 prefixq(dst, src);
7788 emit_int8(0x3B);
7789 emit_operand(src, dst);
7790 }
7791
7792 void Assembler::cmpq(Register dst, Register src) {
7793 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7794 emit_arith(0x3B, 0xC0, dst, src);
7795 }
7796
7797 void Assembler::cmpq(Register dst, Address src) {
7798 InstructionMark im(this);
7799 prefixq(src, dst);
7800 emit_int8(0x3B);
7801 emit_operand(dst, src);
7802 }
7803
7804 void Assembler::cmpxchgq(Register reg, Address adr) {
7805 InstructionMark im(this);
7806 prefixq(adr, reg);
7807 emit_int8(0x0F);
7808 emit_int8((unsigned char)0xB1);
7809 emit_operand(reg, adr);
7810 }
7811
7812 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7814 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7815 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7816 emit_int8(0x2A);
7817 emit_int8((unsigned char)(0xC0 | encode));
7818 }
7819
7820 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7822 InstructionMark im(this);
7823 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7824 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7825 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7826 emit_int8(0x2A);
7827 emit_operand(dst, src);
7828 }
7829
7830 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7831 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7832 InstructionMark im(this);
7833 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7835 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7836 emit_int8(0x2A);
7837 emit_operand(dst, src);
7838 }
7839
7840 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7841 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7842 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7843 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7844 emit_int8(0x2C);
7845 emit_int8((unsigned char)(0xC0 | encode));
7846 }
7847
7848 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7849 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7850 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7851 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7852 emit_int8(0x2C);
7853 emit_int8((unsigned char)(0xC0 | encode));
7854 }
7855
7856 void Assembler::decl(Register dst) {
7857 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7858 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7859 int encode = prefix_and_encode(dst->encoding());
7860 emit_int8((unsigned char)0xFF);
7861 emit_int8((unsigned char)(0xC8 | encode));
7862 }
7863
7864 void Assembler::decq(Register dst) {
7865 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7866 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7867 int encode = prefixq_and_encode(dst->encoding());
7868 emit_int8((unsigned char)0xFF);
7869 emit_int8(0xC8 | encode);
7870 }
7871
7872 void Assembler::decq(Address dst) {
7873 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7874 InstructionMark im(this);
7875 prefixq(dst);
7876 emit_int8((unsigned char)0xFF);
7877 emit_operand(rcx, dst);
7878 }
7879
7880 void Assembler::fxrstor(Address src) {
7881 prefixq(src);
7882 emit_int8(0x0F);
7883 emit_int8((unsigned char)0xAE);
7884 emit_operand(as_Register(1), src);
7885 }
7886
7887 void Assembler::xrstor(Address src) {
7888 prefixq(src);
7889 emit_int8(0x0F);
7890 emit_int8((unsigned char)0xAE);
7891 emit_operand(as_Register(5), src);
7892 }
7893
7894 void Assembler::fxsave(Address dst) {
7895 prefixq(dst);
7896 emit_int8(0x0F);
7897 emit_int8((unsigned char)0xAE);
7898 emit_operand(as_Register(0), dst);
7899 }
7900
7901 void Assembler::xsave(Address dst) {
7902 prefixq(dst);
7903 emit_int8(0x0F);
7904 emit_int8((unsigned char)0xAE);
7905 emit_operand(as_Register(4), dst);
7906 }
7907
7908 void Assembler::idivq(Register src) {
7909 int encode = prefixq_and_encode(src->encoding());
7910 emit_int8((unsigned char)0xF7);
7911 emit_int8((unsigned char)(0xF8 | encode));
7912 }
7913
7914 void Assembler::imulq(Register dst, Register src) {
7915 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7916 emit_int8(0x0F);
7917 emit_int8((unsigned char)0xAF);
7918 emit_int8((unsigned char)(0xC0 | encode));
7919 }
7920
7921 void Assembler::imulq(Register dst, Register src, int value) {
7922 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7923 if (is8bit(value)) {
7924 emit_int8(0x6B);
7925 emit_int8((unsigned char)(0xC0 | encode));
7926 emit_int8(value & 0xFF);
7927 } else {
7928 emit_int8(0x69);
7929 emit_int8((unsigned char)(0xC0 | encode));
7930 emit_int32(value);
7931 }
7932 }
7933
7934 void Assembler::imulq(Register dst, Address src) {
7935 InstructionMark im(this);
7936 prefixq(src, dst);
7937 emit_int8(0x0F);
7938 emit_int8((unsigned char) 0xAF);
7939 emit_operand(dst, src);
7940 }
7941
7942 void Assembler::incl(Register dst) {
7943 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7944 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7945 int encode = prefix_and_encode(dst->encoding());
7946 emit_int8((unsigned char)0xFF);
7947 emit_int8((unsigned char)(0xC0 | encode));
7948 }
7949
7950 void Assembler::incq(Register dst) {
7951 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7952 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7953 int encode = prefixq_and_encode(dst->encoding());
7954 emit_int8((unsigned char)0xFF);
7955 emit_int8((unsigned char)(0xC0 | encode));
7956 }
7957
7958 void Assembler::incq(Address dst) {
7959 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7960 InstructionMark im(this);
7961 prefixq(dst);
7962 emit_int8((unsigned char)0xFF);
7963 emit_operand(rax, dst);
7964 }
7965
7966 void Assembler::lea(Register dst, Address src) {
7967 leaq(dst, src);
7968 }
7969
7970 void Assembler::leaq(Register dst, Address src) {
7971 InstructionMark im(this);
7972 prefixq(src, dst);
7973 emit_int8((unsigned char)0x8D);
7974 emit_operand(dst, src);
7975 }
7976
7977 void Assembler::mov64(Register dst, int64_t imm64) {
7978 InstructionMark im(this);
7979 int encode = prefixq_and_encode(dst->encoding());
7980 emit_int8((unsigned char)(0xB8 | encode));
7981 emit_int64(imm64);
7982 }
7983
7984 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7985 InstructionMark im(this);
7986 int encode = prefixq_and_encode(dst->encoding());
7987 emit_int8(0xB8 | encode);
7988 emit_data64(imm64, rspec);
7989 }
7990
7991 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7992 InstructionMark im(this);
7993 int encode = prefix_and_encode(dst->encoding());
7994 emit_int8((unsigned char)(0xB8 | encode));
7995 emit_data((int)imm32, rspec, narrow_oop_operand);
7996 }
7997
7998 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7999 InstructionMark im(this);
8000 prefix(dst);
8001 emit_int8((unsigned char)0xC7);
8002 emit_operand(rax, dst, 4);
8003 emit_data((int)imm32, rspec, narrow_oop_operand);
8004 }
8005
8006 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8007 InstructionMark im(this);
8008 int encode = prefix_and_encode(src1->encoding());
8009 emit_int8((unsigned char)0x81);
8010 emit_int8((unsigned char)(0xF8 | encode));
8011 emit_data((int)imm32, rspec, narrow_oop_operand);
8012 }
8013
8014 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8015 InstructionMark im(this);
8016 prefix(src1);
8017 emit_int8((unsigned char)0x81);
8018 emit_operand(rax, src1, 4);
8019 emit_data((int)imm32, rspec, narrow_oop_operand);
8020 }
8021
8022 void Assembler::lzcntq(Register dst, Register src) {
8023 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8024 emit_int8((unsigned char)0xF3);
8025 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8026 emit_int8(0x0F);
8027 emit_int8((unsigned char)0xBD);
8028 emit_int8((unsigned char)(0xC0 | encode));
8029 }
8030
8031 void Assembler::movdq(XMMRegister dst, Register src) {
8032 // table D-1 says MMX/SSE2
8033 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8034 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8035 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8036 emit_int8(0x6E);
8037 emit_int8((unsigned char)(0xC0 | encode));
8038 }
8039
8040 void Assembler::movdq(Register dst, XMMRegister src) {
8041 // table D-1 says MMX/SSE2
8042 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8043 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8044 // swap src/dst to get correct prefix
8045 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8046 emit_int8(0x7E);
8047 emit_int8((unsigned char)(0xC0 | encode));
8048 }
8049
8050 void Assembler::movq(Register dst, Register src) {
8051 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8052 emit_int8((unsigned char)0x8B);
8053 emit_int8((unsigned char)(0xC0 | encode));
8054 }
8055
8056 void Assembler::movq(Register dst, Address src) {
8057 InstructionMark im(this);
8058 prefixq(src, dst);
8059 emit_int8((unsigned char)0x8B);
8060 emit_operand(dst, src);
8061 }
8062
8063 void Assembler::movq(Address dst, Register src) {
8064 InstructionMark im(this);
8065 prefixq(dst, src);
8066 emit_int8((unsigned char)0x89);
8067 emit_operand(src, dst);
8068 }
8069
8070 void Assembler::movsbq(Register dst, Address src) {
8071 InstructionMark im(this);
8072 prefixq(src, dst);
8073 emit_int8(0x0F);
8074 emit_int8((unsigned char)0xBE);
8075 emit_operand(dst, src);
8076 }
8077
8078 void Assembler::movsbq(Register dst, Register src) {
8079 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8080 emit_int8(0x0F);
8081 emit_int8((unsigned char)0xBE);
8082 emit_int8((unsigned char)(0xC0 | encode));
8083 }
8084
8085 void Assembler::movslq(Register dst, int32_t imm32) {
8086 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8087 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8088 // as a result we shouldn't use until tested at runtime...
8089 ShouldNotReachHere();
8090 InstructionMark im(this);
8091 int encode = prefixq_and_encode(dst->encoding());
8092 emit_int8((unsigned char)(0xC7 | encode));
8093 emit_int32(imm32);
8094 }
8095
8096 void Assembler::movslq(Address dst, int32_t imm32) {
8097 assert(is_simm32(imm32), "lost bits");
8098 InstructionMark im(this);
8099 prefixq(dst);
8100 emit_int8((unsigned char)0xC7);
8101 emit_operand(rax, dst, 4);
8102 emit_int32(imm32);
8103 }
8104
8105 void Assembler::movslq(Register dst, Address src) {
8106 InstructionMark im(this);
8107 prefixq(src, dst);
8108 emit_int8(0x63);
8109 emit_operand(dst, src);
8110 }
8111
8112 void Assembler::movslq(Register dst, Register src) {
8113 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8114 emit_int8(0x63);
8115 emit_int8((unsigned char)(0xC0 | encode));
8116 }
8117
8118 void Assembler::movswq(Register dst, Address src) {
8119 InstructionMark im(this);
8120 prefixq(src, dst);
8121 emit_int8(0x0F);
8122 emit_int8((unsigned char)0xBF);
8123 emit_operand(dst, src);
8124 }
8125
8126 void Assembler::movswq(Register dst, Register src) {
8127 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8128 emit_int8((unsigned char)0x0F);
8129 emit_int8((unsigned char)0xBF);
8130 emit_int8((unsigned char)(0xC0 | encode));
8131 }
8132
8133 void Assembler::movzbq(Register dst, Address src) {
8134 InstructionMark im(this);
8135 prefixq(src, dst);
8136 emit_int8((unsigned char)0x0F);
8137 emit_int8((unsigned char)0xB6);
8138 emit_operand(dst, src);
8139 }
8140
8141 void Assembler::movzbq(Register dst, Register src) {
8142 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8143 emit_int8(0x0F);
8144 emit_int8((unsigned char)0xB6);
8145 emit_int8(0xC0 | encode);
8146 }
8147
8148 void Assembler::movzwq(Register dst, Address src) {
8149 InstructionMark im(this);
8150 prefixq(src, dst);
8151 emit_int8((unsigned char)0x0F);
8152 emit_int8((unsigned char)0xB7);
8153 emit_operand(dst, src);
8154 }
8155
8156 void Assembler::movzwq(Register dst, Register src) {
8157 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8158 emit_int8((unsigned char)0x0F);
8159 emit_int8((unsigned char)0xB7);
8160 emit_int8((unsigned char)(0xC0 | encode));
8161 }
8162
8163 void Assembler::mulq(Address src) {
8164 InstructionMark im(this);
8165 prefixq(src);
8166 emit_int8((unsigned char)0xF7);
8167 emit_operand(rsp, src);
8168 }
8169
8170 void Assembler::mulq(Register src) {
8171 int encode = prefixq_and_encode(src->encoding());
8172 emit_int8((unsigned char)0xF7);
8173 emit_int8((unsigned char)(0xE0 | encode));
8174 }
8175
8176 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8177 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8178 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8179 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8180 emit_int8((unsigned char)0xF6);
8181 emit_int8((unsigned char)(0xC0 | encode));
8182 }
8183
8184 void Assembler::negq(Register dst) {
8185 int encode = prefixq_and_encode(dst->encoding());
8186 emit_int8((unsigned char)0xF7);
8187 emit_int8((unsigned char)(0xD8 | encode));
8188 }
8189
8190 void Assembler::notq(Register dst) {
8191 int encode = prefixq_and_encode(dst->encoding());
8192 emit_int8((unsigned char)0xF7);
8193 emit_int8((unsigned char)(0xD0 | encode));
8194 }
8195
8196 void Assembler::orq(Address dst, int32_t imm32) {
8197 InstructionMark im(this);
8198 prefixq(dst);
8199 emit_int8((unsigned char)0x81);
8200 emit_operand(rcx, dst, 4);
8201 emit_int32(imm32);
8202 }
8203
8204 void Assembler::orq(Register dst, int32_t imm32) {
8205 (void) prefixq_and_encode(dst->encoding());
8206 emit_arith(0x81, 0xC8, dst, imm32);
8207 }
8208
8209 void Assembler::orq(Register dst, Address src) {
8210 InstructionMark im(this);
8211 prefixq(src, dst);
8212 emit_int8(0x0B);
8213 emit_operand(dst, src);
8214 }
8215
8216 void Assembler::orq(Register dst, Register src) {
8217 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8218 emit_arith(0x0B, 0xC0, dst, src);
8219 }
8220
8221 void Assembler::popa() { // 64bit
8222 movq(r15, Address(rsp, 0));
8223 movq(r14, Address(rsp, wordSize));
8224 movq(r13, Address(rsp, 2 * wordSize));
8225 movq(r12, Address(rsp, 3 * wordSize));
8226 movq(r11, Address(rsp, 4 * wordSize));
8227 movq(r10, Address(rsp, 5 * wordSize));
8228 movq(r9, Address(rsp, 6 * wordSize));
8229 movq(r8, Address(rsp, 7 * wordSize));
8230 movq(rdi, Address(rsp, 8 * wordSize));
8231 movq(rsi, Address(rsp, 9 * wordSize));
8232 movq(rbp, Address(rsp, 10 * wordSize));
8233 // skip rsp
8234 movq(rbx, Address(rsp, 12 * wordSize));
8235 movq(rdx, Address(rsp, 13 * wordSize));
8236 movq(rcx, Address(rsp, 14 * wordSize));
8237 movq(rax, Address(rsp, 15 * wordSize));
8238
8239 addq(rsp, 16 * wordSize);
8240 }
8241
8242 void Assembler::popcntq(Register dst, Address src) {
8243 assert(VM_Version::supports_popcnt(), "must support");
8244 InstructionMark im(this);
8245 emit_int8((unsigned char)0xF3);
8246 prefixq(src, dst);
8247 emit_int8((unsigned char)0x0F);
8248 emit_int8((unsigned char)0xB8);
8249 emit_operand(dst, src);
8250 }
8251
8252 void Assembler::popcntq(Register dst, Register src) {
8253 assert(VM_Version::supports_popcnt(), "must support");
8254 emit_int8((unsigned char)0xF3);
8255 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8256 emit_int8((unsigned char)0x0F);
8257 emit_int8((unsigned char)0xB8);
8258 emit_int8((unsigned char)(0xC0 | encode));
8259 }
8260
8261 void Assembler::popq(Address dst) {
8262 InstructionMark im(this);
8263 prefixq(dst);
8264 emit_int8((unsigned char)0x8F);
8265 emit_operand(rax, dst);
8266 }
8267
8268 void Assembler::pusha() { // 64bit
8269 // we have to store original rsp. ABI says that 128 bytes
8270 // below rsp are local scratch.
8271 movq(Address(rsp, -5 * wordSize), rsp);
8272
8273 subq(rsp, 16 * wordSize);
8274
8275 movq(Address(rsp, 15 * wordSize), rax);
8276 movq(Address(rsp, 14 * wordSize), rcx);
8277 movq(Address(rsp, 13 * wordSize), rdx);
8278 movq(Address(rsp, 12 * wordSize), rbx);
8279 // skip rsp
8280 movq(Address(rsp, 10 * wordSize), rbp);
8281 movq(Address(rsp, 9 * wordSize), rsi);
8282 movq(Address(rsp, 8 * wordSize), rdi);
8283 movq(Address(rsp, 7 * wordSize), r8);
8284 movq(Address(rsp, 6 * wordSize), r9);
8285 movq(Address(rsp, 5 * wordSize), r10);
8286 movq(Address(rsp, 4 * wordSize), r11);
8287 movq(Address(rsp, 3 * wordSize), r12);
8288 movq(Address(rsp, 2 * wordSize), r13);
8289 movq(Address(rsp, wordSize), r14);
8290 movq(Address(rsp, 0), r15);
8291 }
8292
8293 void Assembler::pushq(Address src) {
8294 InstructionMark im(this);
8295 prefixq(src);
8296 emit_int8((unsigned char)0xFF);
8297 emit_operand(rsi, src);
8298 }
8299
8300 void Assembler::rclq(Register dst, int imm8) {
8301 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8302 int encode = prefixq_and_encode(dst->encoding());
8303 if (imm8 == 1) {
8304 emit_int8((unsigned char)0xD1);
8305 emit_int8((unsigned char)(0xD0 | encode));
8306 } else {
8307 emit_int8((unsigned char)0xC1);
8308 emit_int8((unsigned char)(0xD0 | encode));
8309 emit_int8(imm8);
8310 }
8311 }
8312
8313 void Assembler::rcrq(Register dst, int imm8) {
8314 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8315 int encode = prefixq_and_encode(dst->encoding());
8316 if (imm8 == 1) {
8317 emit_int8((unsigned char)0xD1);
8318 emit_int8((unsigned char)(0xD8 | encode));
8319 } else {
8320 emit_int8((unsigned char)0xC1);
8321 emit_int8((unsigned char)(0xD8 | encode));
8322 emit_int8(imm8);
8323 }
8324 }
8325
8326 void Assembler::rorq(Register dst, int imm8) {
8327 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8328 int encode = prefixq_and_encode(dst->encoding());
8329 if (imm8 == 1) {
8330 emit_int8((unsigned char)0xD1);
8331 emit_int8((unsigned char)(0xC8 | encode));
8332 } else {
8333 emit_int8((unsigned char)0xC1);
8334 emit_int8((unsigned char)(0xc8 | encode));
8335 emit_int8(imm8);
8336 }
8337 }
8338
8339 void Assembler::rorxq(Register dst, Register src, int imm8) {
8340 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8341 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8342 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8343 emit_int8((unsigned char)0xF0);
8344 emit_int8((unsigned char)(0xC0 | encode));
8345 emit_int8(imm8);
8346 }
8347
8348 void Assembler::sarq(Register dst, int imm8) {
8349 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8350 int encode = prefixq_and_encode(dst->encoding());
8351 if (imm8 == 1) {
8352 emit_int8((unsigned char)0xD1);
8353 emit_int8((unsigned char)(0xF8 | encode));
8354 } else {
8355 emit_int8((unsigned char)0xC1);
8356 emit_int8((unsigned char)(0xF8 | encode));
8357 emit_int8(imm8);
8358 }
8359 }
8360
8361 void Assembler::sarq(Register dst) {
8362 int encode = prefixq_and_encode(dst->encoding());
8363 emit_int8((unsigned char)0xD3);
8364 emit_int8((unsigned char)(0xF8 | encode));
8365 }
8366
8367 void Assembler::sbbq(Address dst, int32_t imm32) {
8368 InstructionMark im(this);
8369 prefixq(dst);
8370 emit_arith_operand(0x81, rbx, dst, imm32);
8371 }
8372
8373 void Assembler::sbbq(Register dst, int32_t imm32) {
8374 (void) prefixq_and_encode(dst->encoding());
8375 emit_arith(0x81, 0xD8, dst, imm32);
8376 }
8377
8378 void Assembler::sbbq(Register dst, Address src) {
8379 InstructionMark im(this);
8380 prefixq(src, dst);
8381 emit_int8(0x1B);
8382 emit_operand(dst, src);
8383 }
8384
8385 void Assembler::sbbq(Register dst, Register src) {
8386 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8387 emit_arith(0x1B, 0xC0, dst, src);
8388 }
8389
8390 void Assembler::shlq(Register dst, int imm8) {
8391 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8392 int encode = prefixq_and_encode(dst->encoding());
8393 if (imm8 == 1) {
8394 emit_int8((unsigned char)0xD1);
8395 emit_int8((unsigned char)(0xE0 | encode));
8396 } else {
8397 emit_int8((unsigned char)0xC1);
8398 emit_int8((unsigned char)(0xE0 | encode));
8399 emit_int8(imm8);
8400 }
8401 }
8402
8403 void Assembler::shlq(Register dst) {
8404 int encode = prefixq_and_encode(dst->encoding());
8405 emit_int8((unsigned char)0xD3);
8406 emit_int8((unsigned char)(0xE0 | encode));
8407 }
8408
8409 void Assembler::shrq(Register dst, int imm8) {
8410 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8411 int encode = prefixq_and_encode(dst->encoding());
8412 emit_int8((unsigned char)0xC1);
8413 emit_int8((unsigned char)(0xE8 | encode));
8414 emit_int8(imm8);
8415 }
8416
8417 void Assembler::shrq(Register dst) {
8418 int encode = prefixq_and_encode(dst->encoding());
8419 emit_int8((unsigned char)0xD3);
8420 emit_int8(0xE8 | encode);
8421 }
8422
8423 void Assembler::subq(Address dst, int32_t imm32) {
8424 InstructionMark im(this);
8425 prefixq(dst);
8426 emit_arith_operand(0x81, rbp, dst, imm32);
8427 }
8428
8429 void Assembler::subq(Address dst, Register src) {
8430 InstructionMark im(this);
8431 prefixq(dst, src);
8432 emit_int8(0x29);
8433 emit_operand(src, dst);
8434 }
8435
8436 void Assembler::subq(Register dst, int32_t imm32) {
8437 (void) prefixq_and_encode(dst->encoding());
8438 emit_arith(0x81, 0xE8, dst, imm32);
8439 }
8440
8441 // Force generation of a 4 byte immediate value even if it fits into 8bit
8442 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8443 (void) prefixq_and_encode(dst->encoding());
8444 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8445 }
8446
8447 void Assembler::subq(Register dst, Address src) {
8448 InstructionMark im(this);
8449 prefixq(src, dst);
8450 emit_int8(0x2B);
8451 emit_operand(dst, src);
8452 }
8453
8454 void Assembler::subq(Register dst, Register src) {
8455 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8456 emit_arith(0x2B, 0xC0, dst, src);
8457 }
8458
8459 void Assembler::testq(Register dst, int32_t imm32) {
8460 // not using emit_arith because test
8461 // doesn't support sign-extension of
8462 // 8bit operands
8463 int encode = dst->encoding();
8464 if (encode == 0) {
8465 prefix(REX_W);
8466 emit_int8((unsigned char)0xA9);
8467 } else {
8468 encode = prefixq_and_encode(encode);
8469 emit_int8((unsigned char)0xF7);
8470 emit_int8((unsigned char)(0xC0 | encode));
8471 }
8472 emit_int32(imm32);
8473 }
8474
8475 void Assembler::testq(Register dst, Register src) {
8476 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8477 emit_arith(0x85, 0xC0, dst, src);
8478 }
8479
8480 void Assembler::xaddq(Address dst, Register src) {
8481 InstructionMark im(this);
8482 prefixq(dst, src);
8483 emit_int8(0x0F);
8484 emit_int8((unsigned char)0xC1);
8485 emit_operand(src, dst);
8486 }
8487
8488 void Assembler::xchgq(Register dst, Address src) {
8489 InstructionMark im(this);
8490 prefixq(src, dst);
8491 emit_int8((unsigned char)0x87);
8492 emit_operand(dst, src);
8493 }
8494
8495 void Assembler::xchgq(Register dst, Register src) {
8496 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8497 emit_int8((unsigned char)0x87);
8498 emit_int8((unsigned char)(0xc0 | encode));
8499 }
8500
8501 void Assembler::xorq(Register dst, Register src) {
8502 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8503 emit_arith(0x33, 0xC0, dst, src);
8504 }
8505
8506 void Assembler::xorq(Register dst, Address src) {
8507 InstructionMark im(this);
8508 prefixq(src, dst);
8509 emit_int8(0x33);
8510 emit_operand(dst, src);
8511 }
8512
8513 #endif // !LP64