2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 void Assembler::movb(Address dst, int imm8) {
2327 InstructionMark im(this);
2328 prefix(dst);
2329 emit_int8((unsigned char)0xC6);
2330 emit_operand(rax, dst, 1);
2331 emit_int8(imm8);
2332 }
2333
2334
2335 void Assembler::movb(Address dst, Register src) {
2336 assert(src->has_byte_register(), "must have byte register");
2337 InstructionMark im(this);
2338 prefix(dst, src, true);
2339 emit_int8((unsigned char)0x88);
2340 emit_operand(src, dst);
2341 }
2342
2343 void Assembler::movdl(XMMRegister dst, Register src) {
2344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2474 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2475 attributes.set_is_evex_instruction();
2476 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2477 emit_int8(0x6F);
2478 emit_operand(dst, src);
2479 }
2480
2481 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2482 assert(VM_Version::supports_evex(), "");
2483 assert(src != xnoreg, "sanity");
2484 InstructionMark im(this);
2485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2486 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2488 attributes.set_is_evex_instruction();
2489 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2490 emit_int8(0x7F);
2491 emit_operand(src, dst);
2492 }
2493
2494 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2495 assert(VM_Version::supports_evex(), "");
2496 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2497 attributes.set_is_evex_instruction();
2498 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2499 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2500 emit_int8(0x6F);
2501 emit_int8((unsigned char)(0xC0 | encode));
2502 }
2503
2504 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2505 assert(VM_Version::supports_evex(), "");
2506 InstructionMark im(this);
2507 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2508 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2509 attributes.set_is_evex_instruction();
2510 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2511 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2512 emit_int8(0x6F);
2513 emit_operand(dst, src);
3256 // In this context, kdst is written the mask used to process the equal components
3257 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3258 assert(VM_Version::supports_avx512bw(), "");
3259 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3260 attributes.set_is_evex_instruction();
3261 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3262 emit_int8(0x74);
3263 emit_int8((unsigned char)(0xC0 | encode));
3264 }
3265
3266 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3267 assert(VM_Version::supports_avx512bw(), "");
3268 InstructionMark im(this);
3269 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3270 attributes.set_is_evex_instruction();
3271 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3272 int dst_enc = kdst->encoding();
3273 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3274 emit_int8(0x74);
3275 emit_operand(as_Register(dst_enc), src);
3276 }
3277
3278 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3279 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3280 assert(VM_Version::supports_sse2(), "");
3281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3283 emit_int8(0x75);
3284 emit_int8((unsigned char)(0xC0 | encode));
3285 }
3286
3287 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3288 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3289 assert(VM_Version::supports_avx(), "");
3290 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3291 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3292 emit_int8(0x75);
3293 emit_int8((unsigned char)(0xC0 | encode));
3294 }
3295
|
2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 // This instruction produces ZF or CF flags
2327 void Assembler::ktestql(KRegister src1, KRegister src2) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x99);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::movb(Address dst, int imm8) {
2336 InstructionMark im(this);
2337 prefix(dst);
2338 emit_int8((unsigned char)0xC6);
2339 emit_operand(rax, dst, 1);
2340 emit_int8(imm8);
2341 }
2342
2343
2344 void Assembler::movb(Address dst, Register src) {
2345 assert(src->has_byte_register(), "must have byte register");
2346 InstructionMark im(this);
2347 prefix(dst, src, true);
2348 emit_int8((unsigned char)0x88);
2349 emit_operand(src, dst);
2350 }
2351
2352 void Assembler::movdl(XMMRegister dst, Register src) {
2353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2483 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2484 attributes.set_is_evex_instruction();
2485 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2486 emit_int8(0x6F);
2487 emit_operand(dst, src);
2488 }
2489
2490 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2491 assert(VM_Version::supports_evex(), "");
2492 assert(src != xnoreg, "sanity");
2493 InstructionMark im(this);
2494 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2495 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2496 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2497 attributes.set_is_evex_instruction();
2498 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2499 emit_int8(0x7F);
2500 emit_operand(src, dst);
2501 }
2502
2503 void Assembler::evmovdqub(KRegister mask, bool zeroing, XMMRegister dst, Address src, int vector_len) {
2504 assert(VM_Version::supports_avx512vlbw(), "");
2505 assert(is_programmed_mask_reg(), "");
2506 InstructionMark im(this);
2507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2508 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2509 attributes.set_embedded_opmask_register_specifier(mask);
2510 if (zeroing) attributes.set_is_clear_context();
2511 attributes.set_is_evex_instruction();
2512 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2513 emit_int8(0x6F);
2514 emit_operand(dst, src);
2515 }
2516
2517 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2518 assert(VM_Version::supports_evex(), "");
2519 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2520 attributes.set_is_evex_instruction();
2521 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2522 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2523 emit_int8(0x6F);
2524 emit_int8((unsigned char)(0xC0 | encode));
2525 }
2526
2527 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2528 assert(VM_Version::supports_evex(), "");
2529 InstructionMark im(this);
2530 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2531 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2532 attributes.set_is_evex_instruction();
2533 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2534 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2535 emit_int8(0x6F);
2536 emit_operand(dst, src);
3279 // In this context, kdst is written the mask used to process the equal components
3280 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3281 assert(VM_Version::supports_avx512bw(), "");
3282 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3283 attributes.set_is_evex_instruction();
3284 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3285 emit_int8(0x74);
3286 emit_int8((unsigned char)(0xC0 | encode));
3287 }
3288
3289 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3290 assert(VM_Version::supports_avx512bw(), "");
3291 InstructionMark im(this);
3292 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3293 attributes.set_is_evex_instruction();
3294 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3295 int dst_enc = kdst->encoding();
3296 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3297 emit_int8(0x74);
3298 emit_operand(as_Register(dst_enc), src);
3299 }
3300
3301 void Assembler::evpcmpeqb(KRegister mask, bool zeroing, KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3302 bool no_reg_mask = (mask == NULL && zeroing == false) ? true : false;
3303 assert(VM_Version::supports_avx512vlbw(), "");
3304 assert(is_programmed_mask_reg(), "");
3305 InstructionMark im(this);
3306 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, no_reg_mask, /* uses_vl */ false);
3307 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3308 if (!no_reg_mask) {
3309 attributes.set_embedded_opmask_register_specifier(mask);
3310 if (zeroing) attributes.set_is_clear_context();
3311 }
3312 attributes.set_is_evex_instruction();
3313 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3314 emit_int8(0x74);
3315 emit_operand(as_Register(kdst->encoding()), src);
3316 }
3317
3318 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3319 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3320 assert(VM_Version::supports_sse2(), "");
3321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3323 emit_int8(0x75);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 }
3326
3327 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3328 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3329 assert(VM_Version::supports_avx(), "");
3330 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3331 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3332 emit_int8(0x75);
3333 emit_int8((unsigned char)(0xC0 | encode));
3334 }
3335
|