1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "vm_version_x86.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument VALUE_OBJ_CLASS_SPEC {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292
146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
149
150 // Address is an abstraction used to represent a memory location
151 // using any of the amd64 addressing modes with one object.
152 //
153 // Note: A register location is represented via a Register, not
154 // via an address for efficiency & simplicity reasons.
155
156 class ArrayAddress;
157
158 class Address VALUE_OBJ_CLASS_SPEC {
159 public:
160 enum ScaleFactor {
161 no_scale = -1,
162 times_1 = 0,
163 times_2 = 1,
164 times_4 = 2,
165 times_8 = 3,
166 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
167 };
168 static ScaleFactor times(int size) {
169 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
170 if (size == 8) return times_8;
171 if (size == 4) return times_4;
172 if (size == 2) return times_2;
173 return times_1;
174 }
175 static int scale_size(ScaleFactor scale) {
176 assert(scale != no_scale, "");
177 assert(((1 << (int)times_1) == 1 &&
178 (1 << (int)times_2) == 2 &&
179 (1 << (int)times_4) == 4 &&
180 (1 << (int)times_8) == 8), "");
181 return (1 << (int)scale);
182 }
183
184 private:
185 Register _base;
186 Register _index;
187 ScaleFactor _scale;
188 int _disp;
189 RelocationHolder _rspec;
190
191 // Easily misused constructors make them private
192 // %%% can we make these go away?
193 NOT_LP64(Address(address loc, RelocationHolder spec);)
194 Address(int disp, address loc, relocInfo::relocType rtype);
195 Address(int disp, address loc, RelocationHolder spec);
196
197 public:
198
199 int disp() { return _disp; }
200 // creation
201 Address()
202 : _base(noreg),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(0) {
206 }
207
208 // No default displacement otherwise Register can be implicitly
209 // converted to 0(Register) which is quite a different animal.
210
211 Address(Register base, int disp)
212 : _base(base),
213 _index(noreg),
214 _scale(no_scale),
215 _disp(disp) {
216 }
217
218 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
219 : _base (base),
220 _index(index),
221 _scale(scale),
222 _disp (disp) {
223 assert(!index->is_valid() == (scale == Address::no_scale),
224 "inconsistent address");
225 }
226
227 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
228 : _base (base),
229 _index(index.register_or_noreg()),
230 _scale(scale),
231 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
232 if (!index.is_register()) scale = Address::no_scale;
233 assert(!_index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address plus_disp(int disp) const {
238 Address a = (*this);
239 a._disp += disp;
240 return a;
241 }
242 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
243 Address a = (*this);
244 a._disp += disp.constant_or_zero() * scale_size(scale);
245 if (disp.is_register()) {
246 assert(!a.index()->is_valid(), "competing indexes");
247 a._index = disp.as_register();
248 a._scale = scale;
249 }
250 return a;
251 }
252 bool is_same_address(Address a) const {
253 // disregard _rspec
254 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
255 }
256
257 // The following two overloads are used in connection with the
258 // ByteSize type (see sizes.hpp). They simplify the use of
259 // ByteSize'd arguments in assembly code. Note that their equivalent
260 // for the optimized build are the member functions with int disp
261 // argument since ByteSize is mapped to an int type in that case.
262 //
263 // Note: DO NOT introduce similar overloaded functions for WordSize
264 // arguments as in the optimized mode, both ByteSize and WordSize
265 // are mapped to the same type and thus the compiler cannot make a
266 // distinction anymore (=> compiler errors).
267
268 #ifdef ASSERT
269 Address(Register base, ByteSize disp)
270 : _base(base),
271 _index(noreg),
272 _scale(no_scale),
273 _disp(in_bytes(disp)) {
274 }
275
276 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
277 : _base(base),
278 _index(index),
279 _scale(scale),
280 _disp(in_bytes(disp)) {
281 assert(!index->is_valid() == (scale == Address::no_scale),
282 "inconsistent address");
283 }
284
285 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
286 : _base (base),
287 _index(index.register_or_noreg()),
288 _scale(scale),
289 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
290 if (!index.is_register()) scale = Address::no_scale;
291 assert(!_index->is_valid() == (scale == Address::no_scale),
292 "inconsistent address");
293 }
294
295 #endif // ASSERT
296
297 // accessors
298 bool uses(Register reg) const { return _base == reg || _index == reg; }
299 Register base() const { return _base; }
300 Register index() const { return _index; }
301 ScaleFactor scale() const { return _scale; }
302 int disp() const { return _disp; }
303
304 // Convert the raw encoding form into the form expected by the constructor for
305 // Address. An index of 4 (rsp) corresponds to having no index, so convert
306 // that to noreg for the Address constructor.
307 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
308
309 static Address make_array(ArrayAddress);
310
311 private:
312 bool base_needs_rex() const {
313 return _base != noreg && _base->encoding() >= 8;
314 }
315
316 bool index_needs_rex() const {
317 return _index != noreg &&_index->encoding() >= 8;
318 }
319
320 relocInfo::relocType reloc() const { return _rspec.type(); }
321
322 friend class Assembler;
323 friend class MacroAssembler;
324 friend class LIR_Assembler; // base/index/scale/disp
325 };
326
327 //
328 // AddressLiteral has been split out from Address because operands of this type
329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
330 // the few instructions that need to deal with address literals are unique and the
331 // MacroAssembler does not have to implement every instruction in the Assembler
332 // in order to search for address literals that may need special handling depending
333 // on the instruction and the platform. As small step on the way to merging i486/amd64
334 // directories.
335 //
336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
337 friend class ArrayAddress;
338 RelocationHolder _rspec;
339 // Typically we use AddressLiterals we want to use their rval
340 // However in some situations we want the lval (effect address) of the item.
341 // We provide a special factory for making those lvals.
342 bool _is_lval;
343
344 // If the target is far we'll need to load the ea of this to
345 // a register to reach it. Otherwise if near we can do rip
346 // relative addressing.
347
348 address _target;
349
350 protected:
351 // creation
352 AddressLiteral()
353 : _is_lval(false),
354 _target(NULL)
355 {}
356
357 public:
358
359
360 AddressLiteral(address target, relocInfo::relocType rtype);
361
362 AddressLiteral(address target, RelocationHolder const& rspec)
363 : _rspec(rspec),
364 _is_lval(false),
365 _target(target)
366 {}
367
368 AddressLiteral addr() {
369 AddressLiteral ret = *this;
370 ret._is_lval = true;
371 return ret;
372 }
373
374
375 private:
376
377 address target() { return _target; }
378 bool is_lval() { return _is_lval; }
379
380 relocInfo::relocType reloc() const { return _rspec.type(); }
381 const RelocationHolder& rspec() const { return _rspec; }
382
383 friend class Assembler;
384 friend class MacroAssembler;
385 friend class Address;
386 friend class LIR_Assembler;
387 };
388
389 // Convience classes
390 class RuntimeAddress: public AddressLiteral {
391
392 public:
393
394 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
395
396 };
397
398 class ExternalAddress: public AddressLiteral {
399 private:
400 static relocInfo::relocType reloc_for_target(address target) {
401 // Sometimes ExternalAddress is used for values which aren't
402 // exactly addresses, like the card table base.
403 // external_word_type can't be used for values in the first page
404 // so just skip the reloc in that case.
405 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
406 }
407
408 public:
409
410 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
411
412 };
413
414 class InternalAddress: public AddressLiteral {
415
416 public:
417
418 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
419
420 };
421
422 // x86 can do array addressing as a single operation since disp can be an absolute
423 // address amd64 can't. We create a class that expresses the concept but does extra
424 // magic on amd64 to get the final result
425
426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
427 private:
428
429 AddressLiteral _base;
430 Address _index;
431
432 public:
433
434 ArrayAddress() {};
435 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
436 AddressLiteral base() { return _base; }
437 Address index() { return _index; }
438
439 };
440
441 class InstructionAttr;
442
443 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
444 // See fxsave and xsave(EVEX enabled) documentation for layout
445 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
446
447 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
448 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
449 // is what you get. The Assembler is generating code into a CodeBuffer.
450
451 class Assembler : public AbstractAssembler {
452 friend class AbstractAssembler; // for the non-virtual hack
453 friend class LIR_Assembler; // as_Address()
454 friend class StubGenerator;
455
456 public:
457 enum Condition { // The x86 condition codes used for conditional jumps/moves.
458 zero = 0x4,
459 notZero = 0x5,
460 equal = 0x4,
461 notEqual = 0x5,
462 less = 0xc,
463 lessEqual = 0xe,
464 greater = 0xf,
465 greaterEqual = 0xd,
466 below = 0x2,
467 belowEqual = 0x6,
468 above = 0x7,
469 aboveEqual = 0x3,
470 overflow = 0x0,
471 noOverflow = 0x1,
472 carrySet = 0x2,
473 carryClear = 0x3,
474 negative = 0x8,
475 positive = 0x9,
476 parity = 0xa,
477 noParity = 0xb
478 };
479
480 enum Prefix {
481 // segment overrides
482 CS_segment = 0x2e,
483 SS_segment = 0x36,
484 DS_segment = 0x3e,
485 ES_segment = 0x26,
486 FS_segment = 0x64,
487 GS_segment = 0x65,
488
489 REX = 0x40,
490
491 REX_B = 0x41,
492 REX_X = 0x42,
493 REX_XB = 0x43,
494 REX_R = 0x44,
495 REX_RB = 0x45,
496 REX_RX = 0x46,
497 REX_RXB = 0x47,
498
499 REX_W = 0x48,
500
501 REX_WB = 0x49,
502 REX_WX = 0x4A,
503 REX_WXB = 0x4B,
504 REX_WR = 0x4C,
505 REX_WRB = 0x4D,
506 REX_WRX = 0x4E,
507 REX_WRXB = 0x4F,
508
509 VEX_3bytes = 0xC4,
510 VEX_2bytes = 0xC5,
511 EVEX_4bytes = 0x62,
512 Prefix_EMPTY = 0x0
513 };
514
515 enum VexPrefix {
516 VEX_B = 0x20,
517 VEX_X = 0x40,
518 VEX_R = 0x80,
519 VEX_W = 0x80
520 };
521
522 enum ExexPrefix {
523 EVEX_F = 0x04,
524 EVEX_V = 0x08,
525 EVEX_Rb = 0x10,
526 EVEX_X = 0x40,
527 EVEX_Z = 0x80
528 };
529
530 enum VexSimdPrefix {
531 VEX_SIMD_NONE = 0x0,
532 VEX_SIMD_66 = 0x1,
533 VEX_SIMD_F3 = 0x2,
534 VEX_SIMD_F2 = 0x3
535 };
536
537 enum VexOpcode {
538 VEX_OPCODE_NONE = 0x0,
539 VEX_OPCODE_0F = 0x1,
540 VEX_OPCODE_0F_38 = 0x2,
541 VEX_OPCODE_0F_3A = 0x3,
542 VEX_OPCODE_MASK = 0x1F
543 };
544
545 enum AvxVectorLen {
546 AVX_128bit = 0x0,
547 AVX_256bit = 0x1,
548 AVX_512bit = 0x2,
549 AVX_NoVec = 0x4
550 };
551
552 enum EvexTupleType {
553 EVEX_FV = 0,
554 EVEX_HV = 4,
555 EVEX_FVM = 6,
556 EVEX_T1S = 7,
557 EVEX_T1F = 11,
558 EVEX_T2 = 13,
559 EVEX_T4 = 15,
560 EVEX_T8 = 17,
561 EVEX_HVM = 18,
562 EVEX_QVM = 19,
563 EVEX_OVM = 20,
564 EVEX_M128 = 21,
565 EVEX_DUP = 22,
566 EVEX_ETUP = 23
567 };
568
569 enum EvexInputSizeInBits {
570 EVEX_8bit = 0,
571 EVEX_16bit = 1,
572 EVEX_32bit = 2,
573 EVEX_64bit = 3,
574 EVEX_NObit = 4
575 };
576
577 enum WhichOperand {
578 // input to locate_operand, and format code for relocations
579 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
580 disp32_operand = 1, // embedded 32-bit displacement or address
581 call32_operand = 2, // embedded 32-bit self-relative displacement
582 #ifndef _LP64
583 _WhichOperand_limit = 3
584 #else
585 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
586 _WhichOperand_limit = 4
587 #endif
588 };
589
590
591
592 // NOTE: The general philopsophy of the declarations here is that 64bit versions
593 // of instructions are freely declared without the need for wrapping them an ifdef.
594 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
595 // In the .cpp file the implementations are wrapped so that they are dropped out
596 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
597 // to the size it was prior to merging up the 32bit and 64bit assemblers.
598 //
599 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
600 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
601
602 private:
603
604 bool _legacy_mode_bw;
605 bool _legacy_mode_dq;
606 bool _legacy_mode_vl;
607 bool _legacy_mode_vlbw;
608 bool _is_managed;
609 bool _programmed_mask_reg;
610
611 class InstructionAttr *_attributes;
612
613 // 64bit prefixes
614 int prefix_and_encode(int reg_enc, bool byteinst = false);
615 int prefixq_and_encode(int reg_enc);
616
617 int prefix_and_encode(int dst_enc, int src_enc) {
618 return prefix_and_encode(dst_enc, false, src_enc, false);
619 }
620 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
621 int prefixq_and_encode(int dst_enc, int src_enc);
622
623 void prefix(Register reg);
624 void prefix(Register dst, Register src, Prefix p);
625 void prefix(Register dst, Address adr, Prefix p);
626 void prefix(Address adr);
627 void prefixq(Address adr);
628
629 void prefix(Address adr, Register reg, bool byteinst = false);
630 void prefix(Address adr, XMMRegister reg);
631 void prefixq(Address adr, Register reg);
632 void prefixq(Address adr, XMMRegister reg);
633
634 void prefetch_prefix(Address src);
635
636 void rex_prefix(Address adr, XMMRegister xreg,
637 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
638 int rex_prefix_and_encode(int dst_enc, int src_enc,
639 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
640
641 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
642
643 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
644 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
645
646 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
647 VexSimdPrefix pre, VexOpcode opc,
648 InstructionAttr *attributes);
649
650 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
651 VexSimdPrefix pre, VexOpcode opc,
652 InstructionAttr *attributes);
653
654 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
655 VexOpcode opc, InstructionAttr *attributes);
656
657 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
658 VexOpcode opc, InstructionAttr *attributes);
659
660 // Helper functions for groups of instructions
661 void emit_arith_b(int op1, int op2, Register dst, int imm8);
662
663 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
664 // Force generation of a 4 byte immediate value even if it fits into 8bit
665 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
666 void emit_arith(int op1, int op2, Register dst, Register src);
667
668 bool emit_compressed_disp_byte(int &disp);
669
670 void emit_operand(Register reg,
671 Register base, Register index, Address::ScaleFactor scale,
672 int disp,
673 RelocationHolder const& rspec,
674 int rip_relative_correction = 0);
675
676 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
677
678 // operands that only take the original 32bit registers
679 void emit_operand32(Register reg, Address adr);
680
681 void emit_operand(XMMRegister reg,
682 Register base, Register index, Address::ScaleFactor scale,
683 int disp,
684 RelocationHolder const& rspec);
685
686 void emit_operand(XMMRegister reg, Address adr);
687
688 void emit_operand(MMXRegister reg, Address adr);
689
690 // workaround gcc (3.2.1-7) bug
691 void emit_operand(Address adr, MMXRegister reg);
692
693
694 // Immediate-to-memory forms
695 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
696
697 void emit_farith(int b1, int b2, int i);
698
699
700 protected:
701 #ifdef ASSERT
702 void check_relocation(RelocationHolder const& rspec, int format);
703 #endif
704
705 void emit_data(jint data, relocInfo::relocType rtype, int format);
706 void emit_data(jint data, RelocationHolder const& rspec, int format);
707 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
708 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
709
710 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
711
712 // These are all easily abused and hence protected
713
714 // 32BIT ONLY SECTION
715 #ifndef _LP64
716 // Make these disappear in 64bit mode since they would never be correct
717 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
718 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
719
720 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
721 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
722
723 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
724 #else
725 // 64BIT ONLY SECTION
726 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
727
728 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
729 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
730
731 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
732 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
733 #endif // _LP64
734
735 // These are unique in that we are ensured by the caller that the 32bit
736 // relative in these instructions will always be able to reach the potentially
737 // 64bit address described by entry. Since they can take a 64bit address they
738 // don't have the 32 suffix like the other instructions in this class.
739
740 void call_literal(address entry, RelocationHolder const& rspec);
741 void jmp_literal(address entry, RelocationHolder const& rspec);
742
743 // Avoid using directly section
744 // Instructions in this section are actually usable by anyone without danger
745 // of failure but have performance issues that are addressed my enhanced
746 // instructions which will do the proper thing base on the particular cpu.
747 // We protect them because we don't trust you...
748
749 // Don't use next inc() and dec() methods directly. INC & DEC instructions
750 // could cause a partial flag stall since they don't set CF flag.
751 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
752 // which call inc() & dec() or add() & sub() in accordance with
753 // the product flag UseIncDec value.
754
755 void decl(Register dst);
756 void decl(Address dst);
757 void decq(Register dst);
758 void decq(Address dst);
759
760 void incl(Register dst);
761 void incl(Address dst);
762 void incq(Register dst);
763 void incq(Address dst);
764
765 // New cpus require use of movsd and movss to avoid partial register stall
766 // when loading from memory. But for old Opteron use movlpd instead of movsd.
767 // The selection is done in MacroAssembler::movdbl() and movflt().
768
769 // Move Scalar Single-Precision Floating-Point Values
770 void movss(XMMRegister dst, Address src);
771 void movss(XMMRegister dst, XMMRegister src);
772 void movss(Address dst, XMMRegister src);
773
774 // Move Scalar Double-Precision Floating-Point Values
775 void movsd(XMMRegister dst, Address src);
776 void movsd(XMMRegister dst, XMMRegister src);
777 void movsd(Address dst, XMMRegister src);
778 void movlpd(XMMRegister dst, Address src);
779
780 // New cpus require use of movaps and movapd to avoid partial register stall
781 // when moving between registers.
782 void movaps(XMMRegister dst, XMMRegister src);
783 void movapd(XMMRegister dst, XMMRegister src);
784
785 // End avoid using directly
786
787
788 // Instruction prefixes
789 void prefix(Prefix p);
790
791 public:
792
793 // Creation
794 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
795 init_attributes();
796 }
797
798 // Decoding
799 static address locate_operand(address inst, WhichOperand which);
800 static address locate_next_instruction(address inst);
801
802 // Utilities
803 static bool is_polling_page_far() NOT_LP64({ return false;});
804 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
805 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
806
807 // Generic instructions
808 // Does 32bit or 64bit as needed for the platform. In some sense these
809 // belong in macro assembler but there is no need for both varieties to exist
810
811 void init_attributes(void) {
812 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
813 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
814 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
815 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
816 _is_managed = false;
817 _programmed_mask_reg = false;
818 _attributes = NULL;
819 }
820
821 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
822 void clear_attributes(void) { _attributes = NULL; }
823
824 void set_managed(void) { _is_managed = true; }
825 void clear_managed(void) { _is_managed = false; }
826 bool is_managed(void) { return _is_managed; }
827
828 void set_programmed_mask_reg(void) { _programmed_mask_reg = true; }
829 void clear_programmed_mask_reg(void) { _programmed_mask_reg = false; }
830 bool is_programmed_mask_reg(void) { return _programmed_mask_reg; }
831
832
833 void lea(Register dst, Address src);
834
835 void mov(Register dst, Register src);
836
837 void pusha();
838 void popa();
839
840 void pushf();
841 void popf();
842
843 void push(int32_t imm32);
844
845 void push(Register src);
846
847 void pop(Register dst);
848
849 // These are dummies to prevent surprise implicit conversions to Register
850 void push(void* v);
851 void pop(void* v);
852
853 // These do register sized moves/scans
854 void rep_mov();
855 void rep_stos();
856 void rep_stosb();
857 void repne_scan();
858 #ifdef _LP64
859 void repne_scanl();
860 #endif
861
862 // Vanilla instructions in lexical order
863
864 void adcl(Address dst, int32_t imm32);
865 void adcl(Address dst, Register src);
866 void adcl(Register dst, int32_t imm32);
867 void adcl(Register dst, Address src);
868 void adcl(Register dst, Register src);
869
870 void adcq(Register dst, int32_t imm32);
871 void adcq(Register dst, Address src);
872 void adcq(Register dst, Register src);
873
874 void addl(Address dst, int32_t imm32);
875 void addl(Address dst, Register src);
876 void addl(Register dst, int32_t imm32);
877 void addl(Register dst, Address src);
878 void addl(Register dst, Register src);
879
880 void addq(Address dst, int32_t imm32);
881 void addq(Address dst, Register src);
882 void addq(Register dst, int32_t imm32);
883 void addq(Register dst, Address src);
884 void addq(Register dst, Register src);
885
886 #ifdef _LP64
887 //Add Unsigned Integers with Carry Flag
888 void adcxq(Register dst, Register src);
889
890 //Add Unsigned Integers with Overflow Flag
891 void adoxq(Register dst, Register src);
892 #endif
893
894 void addr_nop_4();
895 void addr_nop_5();
896 void addr_nop_7();
897 void addr_nop_8();
898
899 // Add Scalar Double-Precision Floating-Point Values
900 void addsd(XMMRegister dst, Address src);
901 void addsd(XMMRegister dst, XMMRegister src);
902
903 // Add Scalar Single-Precision Floating-Point Values
904 void addss(XMMRegister dst, Address src);
905 void addss(XMMRegister dst, XMMRegister src);
906
907 // AES instructions
908 void aesdec(XMMRegister dst, Address src);
909 void aesdec(XMMRegister dst, XMMRegister src);
910 void aesdeclast(XMMRegister dst, Address src);
911 void aesdeclast(XMMRegister dst, XMMRegister src);
912 void aesenc(XMMRegister dst, Address src);
913 void aesenc(XMMRegister dst, XMMRegister src);
914 void aesenclast(XMMRegister dst, Address src);
915 void aesenclast(XMMRegister dst, XMMRegister src);
916
917
918 void andl(Address dst, int32_t imm32);
919 void andl(Register dst, int32_t imm32);
920 void andl(Register dst, Address src);
921 void andl(Register dst, Register src);
922
923 void andq(Address dst, int32_t imm32);
924 void andq(Register dst, int32_t imm32);
925 void andq(Register dst, Address src);
926 void andq(Register dst, Register src);
927
928 // BMI instructions
929 void andnl(Register dst, Register src1, Register src2);
930 void andnl(Register dst, Register src1, Address src2);
931 void andnq(Register dst, Register src1, Register src2);
932 void andnq(Register dst, Register src1, Address src2);
933
934 void blsil(Register dst, Register src);
935 void blsil(Register dst, Address src);
936 void blsiq(Register dst, Register src);
937 void blsiq(Register dst, Address src);
938
939 void blsmskl(Register dst, Register src);
940 void blsmskl(Register dst, Address src);
941 void blsmskq(Register dst, Register src);
942 void blsmskq(Register dst, Address src);
943
944 void blsrl(Register dst, Register src);
945 void blsrl(Register dst, Address src);
946 void blsrq(Register dst, Register src);
947 void blsrq(Register dst, Address src);
948
949 void bsfl(Register dst, Register src);
950 void bsrl(Register dst, Register src);
951
952 #ifdef _LP64
953 void bsfq(Register dst, Register src);
954 void bsrq(Register dst, Register src);
955 #endif
956
957 void bswapl(Register reg);
958
959 void bswapq(Register reg);
960
961 void call(Label& L, relocInfo::relocType rtype);
962 void call(Register reg); // push pc; pc <- reg
963 void call(Address adr); // push pc; pc <- adr
964
965 void cdql();
966
967 void cdqq();
968
969 void cld();
970
971 void clflush(Address adr);
972
973 void cmovl(Condition cc, Register dst, Register src);
974 void cmovl(Condition cc, Register dst, Address src);
975
976 void cmovq(Condition cc, Register dst, Register src);
977 void cmovq(Condition cc, Register dst, Address src);
978
979
980 void cmpb(Address dst, int imm8);
981
982 void cmpl(Address dst, int32_t imm32);
983
984 void cmpl(Register dst, int32_t imm32);
985 void cmpl(Register dst, Register src);
986 void cmpl(Register dst, Address src);
987
988 void cmpq(Address dst, int32_t imm32);
989 void cmpq(Address dst, Register src);
990
991 void cmpq(Register dst, int32_t imm32);
992 void cmpq(Register dst, Register src);
993 void cmpq(Register dst, Address src);
994
995 // these are dummies used to catch attempting to convert NULL to Register
996 void cmpl(Register dst, void* junk); // dummy
997 void cmpq(Register dst, void* junk); // dummy
998
999 void cmpw(Address dst, int imm16);
1000
1001 void cmpxchg8 (Address adr);
1002
1003 void cmpxchgb(Register reg, Address adr);
1004 void cmpxchgl(Register reg, Address adr);
1005
1006 void cmpxchgq(Register reg, Address adr);
1007
1008 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1009 void comisd(XMMRegister dst, Address src);
1010 void comisd(XMMRegister dst, XMMRegister src);
1011
1012 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1013 void comiss(XMMRegister dst, Address src);
1014 void comiss(XMMRegister dst, XMMRegister src);
1015
1016 // Identify processor type and features
1017 void cpuid();
1018
1019 // CRC32C
1020 void crc32(Register crc, Register v, int8_t sizeInBytes);
1021 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1022
1023 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1024 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1025 void cvtsd2ss(XMMRegister dst, Address src);
1026
1027 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1028 void cvtsi2sdl(XMMRegister dst, Register src);
1029 void cvtsi2sdl(XMMRegister dst, Address src);
1030 void cvtsi2sdq(XMMRegister dst, Register src);
1031 void cvtsi2sdq(XMMRegister dst, Address src);
1032
1033 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1034 void cvtsi2ssl(XMMRegister dst, Register src);
1035 void cvtsi2ssl(XMMRegister dst, Address src);
1036 void cvtsi2ssq(XMMRegister dst, Register src);
1037 void cvtsi2ssq(XMMRegister dst, Address src);
1038
1039 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1040 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1041
1042 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1043 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1044
1045 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1046 void cvtss2sd(XMMRegister dst, XMMRegister src);
1047 void cvtss2sd(XMMRegister dst, Address src);
1048
1049 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1050 void cvttsd2sil(Register dst, Address src);
1051 void cvttsd2sil(Register dst, XMMRegister src);
1052 void cvttsd2siq(Register dst, XMMRegister src);
1053
1054 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1055 void cvttss2sil(Register dst, XMMRegister src);
1056 void cvttss2siq(Register dst, XMMRegister src);
1057
1058 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1059
1060 // Divide Scalar Double-Precision Floating-Point Values
1061 void divsd(XMMRegister dst, Address src);
1062 void divsd(XMMRegister dst, XMMRegister src);
1063
1064 // Divide Scalar Single-Precision Floating-Point Values
1065 void divss(XMMRegister dst, Address src);
1066 void divss(XMMRegister dst, XMMRegister src);
1067
1068 void emms();
1069
1070 void fabs();
1071
1072 void fadd(int i);
1073
1074 void fadd_d(Address src);
1075 void fadd_s(Address src);
1076
1077 // "Alternate" versions of x87 instructions place result down in FPU
1078 // stack instead of on TOS
1079
1080 void fadda(int i); // "alternate" fadd
1081 void faddp(int i = 1);
1082
1083 void fchs();
1084
1085 void fcom(int i);
1086
1087 void fcomp(int i = 1);
1088 void fcomp_d(Address src);
1089 void fcomp_s(Address src);
1090
1091 void fcompp();
1092
1093 void fcos();
1094
1095 void fdecstp();
1096
1097 void fdiv(int i);
1098 void fdiv_d(Address src);
1099 void fdivr_s(Address src);
1100 void fdiva(int i); // "alternate" fdiv
1101 void fdivp(int i = 1);
1102
1103 void fdivr(int i);
1104 void fdivr_d(Address src);
1105 void fdiv_s(Address src);
1106
1107 void fdivra(int i); // "alternate" reversed fdiv
1108
1109 void fdivrp(int i = 1);
1110
1111 void ffree(int i = 0);
1112
1113 void fild_d(Address adr);
1114 void fild_s(Address adr);
1115
1116 void fincstp();
1117
1118 void finit();
1119
1120 void fist_s (Address adr);
1121 void fistp_d(Address adr);
1122 void fistp_s(Address adr);
1123
1124 void fld1();
1125
1126 void fld_d(Address adr);
1127 void fld_s(Address adr);
1128 void fld_s(int index);
1129 void fld_x(Address adr); // extended-precision (80-bit) format
1130
1131 void fldcw(Address src);
1132
1133 void fldenv(Address src);
1134
1135 void fldlg2();
1136
1137 void fldln2();
1138
1139 void fldz();
1140
1141 void flog();
1142 void flog10();
1143
1144 void fmul(int i);
1145
1146 void fmul_d(Address src);
1147 void fmul_s(Address src);
1148
1149 void fmula(int i); // "alternate" fmul
1150
1151 void fmulp(int i = 1);
1152
1153 void fnsave(Address dst);
1154
1155 void fnstcw(Address src);
1156
1157 void fnstsw_ax();
1158
1159 void fprem();
1160 void fprem1();
1161
1162 void frstor(Address src);
1163
1164 void fsin();
1165
1166 void fsqrt();
1167
1168 void fst_d(Address adr);
1169 void fst_s(Address adr);
1170
1171 void fstp_d(Address adr);
1172 void fstp_d(int index);
1173 void fstp_s(Address adr);
1174 void fstp_x(Address adr); // extended-precision (80-bit) format
1175
1176 void fsub(int i);
1177 void fsub_d(Address src);
1178 void fsub_s(Address src);
1179
1180 void fsuba(int i); // "alternate" fsub
1181
1182 void fsubp(int i = 1);
1183
1184 void fsubr(int i);
1185 void fsubr_d(Address src);
1186 void fsubr_s(Address src);
1187
1188 void fsubra(int i); // "alternate" reversed fsub
1189
1190 void fsubrp(int i = 1);
1191
1192 void ftan();
1193
1194 void ftst();
1195
1196 void fucomi(int i = 1);
1197 void fucomip(int i = 1);
1198
1199 void fwait();
1200
1201 void fxch(int i = 1);
1202
1203 void fxrstor(Address src);
1204 void xrstor(Address src);
1205
1206 void fxsave(Address dst);
1207 void xsave(Address dst);
1208
1209 void fyl2x();
1210 void frndint();
1211 void f2xm1();
1212 void fldl2e();
1213
1214 void hlt();
1215
1216 void idivl(Register src);
1217 void divl(Register src); // Unsigned division
1218
1219 #ifdef _LP64
1220 void idivq(Register src);
1221 #endif
1222
1223 void imull(Register src);
1224 void imull(Register dst, Register src);
1225 void imull(Register dst, Register src, int value);
1226 void imull(Register dst, Address src);
1227
1228 #ifdef _LP64
1229 void imulq(Register dst, Register src);
1230 void imulq(Register dst, Register src, int value);
1231 void imulq(Register dst, Address src);
1232 #endif
1233
1234 // jcc is the generic conditional branch generator to run-
1235 // time routines, jcc is used for branches to labels. jcc
1236 // takes a branch opcode (cc) and a label (L) and generates
1237 // either a backward branch or a forward branch and links it
1238 // to the label fixup chain. Usage:
1239 //
1240 // Label L; // unbound label
1241 // jcc(cc, L); // forward branch to unbound label
1242 // bind(L); // bind label to the current pc
1243 // jcc(cc, L); // backward branch to bound label
1244 // bind(L); // illegal: a label may be bound only once
1245 //
1246 // Note: The same Label can be used for forward and backward branches
1247 // but it may be bound only once.
1248
1249 void jcc(Condition cc, Label& L, bool maybe_short = true);
1250
1251 // Conditional jump to a 8-bit offset to L.
1252 // WARNING: be very careful using this for forward jumps. If the label is
1253 // not bound within an 8-bit offset of this instruction, a run-time error
1254 // will occur.
1255 void jccb(Condition cc, Label& L);
1256
1257 void jmp(Address entry); // pc <- entry
1258
1259 // Label operations & relative jumps (PPUM Appendix D)
1260 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1261
1262 void jmp(Register entry); // pc <- entry
1263
1264 // Unconditional 8-bit offset jump to L.
1265 // WARNING: be very careful using this for forward jumps. If the label is
1266 // not bound within an 8-bit offset of this instruction, a run-time error
1267 // will occur.
1268 void jmpb(Label& L);
1269
1270 void ldmxcsr( Address src );
1271
1272 void leal(Register dst, Address src);
1273
1274 void leaq(Register dst, Address src);
1275
1276 void lfence();
1277
1278 void lock();
1279
1280 void lzcntl(Register dst, Register src);
1281
1282 #ifdef _LP64
1283 void lzcntq(Register dst, Register src);
1284 #endif
1285
1286 enum Membar_mask_bits {
1287 StoreStore = 1 << 3,
1288 LoadStore = 1 << 2,
1289 StoreLoad = 1 << 1,
1290 LoadLoad = 1 << 0
1291 };
1292
1293 // Serializes memory and blows flags
1294 void membar(Membar_mask_bits order_constraint) {
1295 if (os::is_MP()) {
1296 // We only have to handle StoreLoad
1297 if (order_constraint & StoreLoad) {
1298 // All usable chips support "locked" instructions which suffice
1299 // as barriers, and are much faster than the alternative of
1300 // using cpuid instruction. We use here a locked add [esp-C],0.
1301 // This is conveniently otherwise a no-op except for blowing
1302 // flags, and introducing a false dependency on target memory
1303 // location. We can't do anything with flags, but we can avoid
1304 // memory dependencies in the current method by locked-adding
1305 // somewhere else on the stack. Doing [esp+C] will collide with
1306 // something on stack in current method, hence we go for [esp-C].
1307 // It is convenient since it is almost always in data cache, for
1308 // any small C. We need to step back from SP to avoid data
1309 // dependencies with other things on below SP (callee-saves, for
1310 // example). Without a clear way to figure out the minimal safe
1311 // distance from SP, it makes sense to step back the complete
1312 // cache line, as this will also avoid possible second-order effects
1313 // with locked ops against the cache line. Our choice of offset
1314 // is bounded by x86 operand encoding, which should stay within
1315 // [-128; +127] to have the 8-byte displacement encoding.
1316 //
1317 // Any change to this code may need to revisit other places in
1318 // the code where this idiom is used, in particular the
1319 // orderAccess code.
1320
1321 int offset = -VM_Version::L1_line_size();
1322 if (offset < -128) {
1323 offset = -128;
1324 }
1325
1326 lock();
1327 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1328 }
1329 }
1330 }
1331
1332 void mfence();
1333
1334 // Moves
1335
1336 void mov64(Register dst, int64_t imm64);
1337
1338 void movb(Address dst, Register src);
1339 void movb(Address dst, int imm8);
1340 void movb(Register dst, Address src);
1341
1342 void movddup(XMMRegister dst, XMMRegister src);
1343
1344 void kmovbl(KRegister dst, Register src);
1345 void kmovbl(Register dst, KRegister src);
1346 void kmovwl(KRegister dst, Register src);
1347 void kmovwl(KRegister dst, Address src);
1348 void kmovwl(Register dst, KRegister src);
1349 void kmovdl(KRegister dst, Register src);
1350 void kmovdl(Register dst, KRegister src);
1351 void kmovql(KRegister dst, KRegister src);
1352 void kmovql(Address dst, KRegister src);
1353 void kmovql(KRegister dst, Address src);
1354 void kmovql(KRegister dst, Register src);
1355 void kmovql(Register dst, KRegister src);
1356
1357 void knotwl(KRegister dst, KRegister src);
1358
1359 void kortestbl(KRegister dst, KRegister src);
1360 void kortestwl(KRegister dst, KRegister src);
1361 void kortestdl(KRegister dst, KRegister src);
1362 void kortestql(KRegister dst, KRegister src);
1363
1364 void ktestql(KRegister dst, KRegister src);
1365
1366 void movdl(XMMRegister dst, Register src);
1367 void movdl(Register dst, XMMRegister src);
1368 void movdl(XMMRegister dst, Address src);
1369 void movdl(Address dst, XMMRegister src);
1370
1371 // Move Double Quadword
1372 void movdq(XMMRegister dst, Register src);
1373 void movdq(Register dst, XMMRegister src);
1374
1375 // Move Aligned Double Quadword
1376 void movdqa(XMMRegister dst, XMMRegister src);
1377 void movdqa(XMMRegister dst, Address src);
1378
1379 // Move Unaligned Double Quadword
1380 void movdqu(Address dst, XMMRegister src);
1381 void movdqu(XMMRegister dst, Address src);
1382 void movdqu(XMMRegister dst, XMMRegister src);
1383
1384 // Move Unaligned 256bit Vector
1385 void vmovdqu(Address dst, XMMRegister src);
1386 void vmovdqu(XMMRegister dst, Address src);
1387 void vmovdqu(XMMRegister dst, XMMRegister src);
1388
1389 // Move Unaligned 512bit Vector
1390 void evmovdqub(Address dst, XMMRegister src, int vector_len);
1391 void evmovdqub(XMMRegister dst, Address src, int vector_len);
1392 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1393 void evmovdqub(KRegister mask, bool zeroing, XMMRegister dst, Address src, int vector_len);
1394 void evmovdquw(Address dst, XMMRegister src, int vector_len);
1395 void evmovdquw(XMMRegister dst, Address src, int vector_len);
1396 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len);
1397 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1398 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1399 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1400 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1401 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1402 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1403
1404 // Move lower 64bit to high 64bit in 128bit register
1405 void movlhps(XMMRegister dst, XMMRegister src);
1406
1407 void movl(Register dst, int32_t imm32);
1408 void movl(Address dst, int32_t imm32);
1409 void movl(Register dst, Register src);
1410 void movl(Register dst, Address src);
1411 void movl(Address dst, Register src);
1412
1413 // These dummies prevent using movl from converting a zero (like NULL) into Register
1414 // by giving the compiler two choices it can't resolve
1415
1416 void movl(Address dst, void* junk);
1417 void movl(Register dst, void* junk);
1418
1419 #ifdef _LP64
1420 void movq(Register dst, Register src);
1421 void movq(Register dst, Address src);
1422 void movq(Address dst, Register src);
1423 #endif
1424
1425 void movq(Address dst, MMXRegister src );
1426 void movq(MMXRegister dst, Address src );
1427
1428 #ifdef _LP64
1429 // These dummies prevent using movq from converting a zero (like NULL) into Register
1430 // by giving the compiler two choices it can't resolve
1431
1432 void movq(Address dst, void* dummy);
1433 void movq(Register dst, void* dummy);
1434 #endif
1435
1436 // Move Quadword
1437 void movq(Address dst, XMMRegister src);
1438 void movq(XMMRegister dst, Address src);
1439
1440 void movsbl(Register dst, Address src);
1441 void movsbl(Register dst, Register src);
1442
1443 #ifdef _LP64
1444 void movsbq(Register dst, Address src);
1445 void movsbq(Register dst, Register src);
1446
1447 // Move signed 32bit immediate to 64bit extending sign
1448 void movslq(Address dst, int32_t imm64);
1449 void movslq(Register dst, int32_t imm64);
1450
1451 void movslq(Register dst, Address src);
1452 void movslq(Register dst, Register src);
1453 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1454 #endif
1455
1456 void movswl(Register dst, Address src);
1457 void movswl(Register dst, Register src);
1458
1459 #ifdef _LP64
1460 void movswq(Register dst, Address src);
1461 void movswq(Register dst, Register src);
1462 #endif
1463
1464 void movw(Address dst, int imm16);
1465 void movw(Register dst, Address src);
1466 void movw(Address dst, Register src);
1467
1468 void movzbl(Register dst, Address src);
1469 void movzbl(Register dst, Register src);
1470
1471 #ifdef _LP64
1472 void movzbq(Register dst, Address src);
1473 void movzbq(Register dst, Register src);
1474 #endif
1475
1476 void movzwl(Register dst, Address src);
1477 void movzwl(Register dst, Register src);
1478
1479 #ifdef _LP64
1480 void movzwq(Register dst, Address src);
1481 void movzwq(Register dst, Register src);
1482 #endif
1483
1484 // Unsigned multiply with RAX destination register
1485 void mull(Address src);
1486 void mull(Register src);
1487
1488 #ifdef _LP64
1489 void mulq(Address src);
1490 void mulq(Register src);
1491 void mulxq(Register dst1, Register dst2, Register src);
1492 #endif
1493
1494 // Multiply Scalar Double-Precision Floating-Point Values
1495 void mulsd(XMMRegister dst, Address src);
1496 void mulsd(XMMRegister dst, XMMRegister src);
1497
1498 // Multiply Scalar Single-Precision Floating-Point Values
1499 void mulss(XMMRegister dst, Address src);
1500 void mulss(XMMRegister dst, XMMRegister src);
1501
1502 void negl(Register dst);
1503
1504 #ifdef _LP64
1505 void negq(Register dst);
1506 #endif
1507
1508 void nop(int i = 1);
1509
1510 void notl(Register dst);
1511
1512 #ifdef _LP64
1513 void notq(Register dst);
1514 #endif
1515
1516 void orl(Address dst, int32_t imm32);
1517 void orl(Register dst, int32_t imm32);
1518 void orl(Register dst, Address src);
1519 void orl(Register dst, Register src);
1520 void orl(Address dst, Register src);
1521
1522 void orq(Address dst, int32_t imm32);
1523 void orq(Register dst, int32_t imm32);
1524 void orq(Register dst, Address src);
1525 void orq(Register dst, Register src);
1526
1527 // Pack with unsigned saturation
1528 void packuswb(XMMRegister dst, XMMRegister src);
1529 void packuswb(XMMRegister dst, Address src);
1530 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1531
1532 // Pemutation of 64bit words
1533 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1534 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1535
1536 void pause();
1537
1538 // SSE4.2 string instructions
1539 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1540 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1541
1542 void pcmpeqb(XMMRegister dst, XMMRegister src);
1543 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1544 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1545 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1546 void evpcmpeqb(KRegister mask, bool zeroing, KRegister kdst, XMMRegister nds, Address src, int vector_len);
1547
1548 void pcmpeqw(XMMRegister dst, XMMRegister src);
1549 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1550 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1551 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1552
1553 void pcmpeqd(XMMRegister dst, XMMRegister src);
1554 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1555 void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1556 void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1557
1558 void pcmpeqq(XMMRegister dst, XMMRegister src);
1559 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1560 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1561 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1562
1563 void pmovmskb(Register dst, XMMRegister src);
1564 void vpmovmskb(Register dst, XMMRegister src);
1565
1566 // SSE 4.1 extract
1567 void pextrd(Register dst, XMMRegister src, int imm8);
1568 void pextrq(Register dst, XMMRegister src, int imm8);
1569 void pextrd(Address dst, XMMRegister src, int imm8);
1570 void pextrq(Address dst, XMMRegister src, int imm8);
1571 void pextrb(Address dst, XMMRegister src, int imm8);
1572 // SSE 2 extract
1573 void pextrw(Register dst, XMMRegister src, int imm8);
1574 void pextrw(Address dst, XMMRegister src, int imm8);
1575
1576 // SSE 4.1 insert
1577 void pinsrd(XMMRegister dst, Register src, int imm8);
1578 void pinsrq(XMMRegister dst, Register src, int imm8);
1579 void pinsrd(XMMRegister dst, Address src, int imm8);
1580 void pinsrq(XMMRegister dst, Address src, int imm8);
1581 void pinsrb(XMMRegister dst, Address src, int imm8);
1582 // SSE 2 insert
1583 void pinsrw(XMMRegister dst, Register src, int imm8);
1584 void pinsrw(XMMRegister dst, Address src, int imm8);
1585
1586 // SSE4.1 packed move
1587 void pmovzxbw(XMMRegister dst, XMMRegister src);
1588 void pmovzxbw(XMMRegister dst, Address src);
1589
1590 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1591
1592 #ifndef _LP64 // no 32bit push/pop on amd64
1593 void popl(Address dst);
1594 #endif
1595
1596 #ifdef _LP64
1597 void popq(Address dst);
1598 #endif
1599
1600 void popcntl(Register dst, Address src);
1601 void popcntl(Register dst, Register src);
1602
1603 #ifdef _LP64
1604 void popcntq(Register dst, Address src);
1605 void popcntq(Register dst, Register src);
1606 #endif
1607
1608 // Prefetches (SSE, SSE2, 3DNOW only)
1609
1610 void prefetchnta(Address src);
1611 void prefetchr(Address src);
1612 void prefetcht0(Address src);
1613 void prefetcht1(Address src);
1614 void prefetcht2(Address src);
1615 void prefetchw(Address src);
1616
1617 // Shuffle Bytes
1618 void pshufb(XMMRegister dst, XMMRegister src);
1619 void pshufb(XMMRegister dst, Address src);
1620
1621 // Shuffle Packed Doublewords
1622 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1623 void pshufd(XMMRegister dst, Address src, int mode);
1624
1625 // Shuffle Packed Low Words
1626 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1627 void pshuflw(XMMRegister dst, Address src, int mode);
1628
1629 // Shift Right by bytes Logical DoubleQuadword Immediate
1630 void psrldq(XMMRegister dst, int shift);
1631 // Shift Left by bytes Logical DoubleQuadword Immediate
1632 void pslldq(XMMRegister dst, int shift);
1633
1634 // Logical Compare 128bit
1635 void ptest(XMMRegister dst, XMMRegister src);
1636 void ptest(XMMRegister dst, Address src);
1637 // Logical Compare 256bit
1638 void vptest(XMMRegister dst, XMMRegister src);
1639 void vptest(XMMRegister dst, Address src);
1640
1641 // Interleave Low Bytes
1642 void punpcklbw(XMMRegister dst, XMMRegister src);
1643 void punpcklbw(XMMRegister dst, Address src);
1644
1645 // Interleave Low Doublewords
1646 void punpckldq(XMMRegister dst, XMMRegister src);
1647 void punpckldq(XMMRegister dst, Address src);
1648
1649 // Interleave Low Quadwords
1650 void punpcklqdq(XMMRegister dst, XMMRegister src);
1651
1652 #ifndef _LP64 // no 32bit push/pop on amd64
1653 void pushl(Address src);
1654 #endif
1655
1656 void pushq(Address src);
1657
1658 void rcll(Register dst, int imm8);
1659
1660 void rclq(Register dst, int imm8);
1661
1662 void rcrq(Register dst, int imm8);
1663
1664 void rcpps(XMMRegister dst, XMMRegister src);
1665
1666 void rcpss(XMMRegister dst, XMMRegister src);
1667
1668 void rdtsc();
1669
1670 void ret(int imm16);
1671
1672 #ifdef _LP64
1673 void rorq(Register dst, int imm8);
1674 void rorxq(Register dst, Register src, int imm8);
1675 #endif
1676
1677 void sahf();
1678
1679 void sarl(Register dst, int imm8);
1680 void sarl(Register dst);
1681
1682 void sarq(Register dst, int imm8);
1683 void sarq(Register dst);
1684
1685 void sbbl(Address dst, int32_t imm32);
1686 void sbbl(Register dst, int32_t imm32);
1687 void sbbl(Register dst, Address src);
1688 void sbbl(Register dst, Register src);
1689
1690 void sbbq(Address dst, int32_t imm32);
1691 void sbbq(Register dst, int32_t imm32);
1692 void sbbq(Register dst, Address src);
1693 void sbbq(Register dst, Register src);
1694
1695 void setb(Condition cc, Register dst);
1696
1697 void palignr(XMMRegister dst, XMMRegister src, int imm8);
1698 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1699
1700 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1701 void sha1nexte(XMMRegister dst, XMMRegister src);
1702 void sha1msg1(XMMRegister dst, XMMRegister src);
1703 void sha1msg2(XMMRegister dst, XMMRegister src);
1704 // xmm0 is implicit additional source to the following instruction.
1705 void sha256rnds2(XMMRegister dst, XMMRegister src);
1706 void sha256msg1(XMMRegister dst, XMMRegister src);
1707 void sha256msg2(XMMRegister dst, XMMRegister src);
1708
1709 void shldl(Register dst, Register src);
1710 void shldl(Register dst, Register src, int8_t imm8);
1711
1712 void shll(Register dst, int imm8);
1713 void shll(Register dst);
1714
1715 void shlq(Register dst, int imm8);
1716 void shlq(Register dst);
1717
1718 void shrdl(Register dst, Register src);
1719
1720 void shrl(Register dst, int imm8);
1721 void shrl(Register dst);
1722
1723 void shrq(Register dst, int imm8);
1724 void shrq(Register dst);
1725
1726 void smovl(); // QQQ generic?
1727
1728 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1729 void sqrtsd(XMMRegister dst, Address src);
1730 void sqrtsd(XMMRegister dst, XMMRegister src);
1731
1732 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1733 void sqrtss(XMMRegister dst, Address src);
1734 void sqrtss(XMMRegister dst, XMMRegister src);
1735
1736 void std();
1737
1738 void stmxcsr( Address dst );
1739
1740 void subl(Address dst, int32_t imm32);
1741 void subl(Address dst, Register src);
1742 void subl(Register dst, int32_t imm32);
1743 void subl(Register dst, Address src);
1744 void subl(Register dst, Register src);
1745
1746 void subq(Address dst, int32_t imm32);
1747 void subq(Address dst, Register src);
1748 void subq(Register dst, int32_t imm32);
1749 void subq(Register dst, Address src);
1750 void subq(Register dst, Register src);
1751
1752 // Force generation of a 4 byte immediate value even if it fits into 8bit
1753 void subl_imm32(Register dst, int32_t imm32);
1754 void subq_imm32(Register dst, int32_t imm32);
1755
1756 // Subtract Scalar Double-Precision Floating-Point Values
1757 void subsd(XMMRegister dst, Address src);
1758 void subsd(XMMRegister dst, XMMRegister src);
1759
1760 // Subtract Scalar Single-Precision Floating-Point Values
1761 void subss(XMMRegister dst, Address src);
1762 void subss(XMMRegister dst, XMMRegister src);
1763
1764 void testb(Register dst, int imm8);
1765 void testb(Address dst, int imm8);
1766
1767 void testl(Register dst, int32_t imm32);
1768 void testl(Register dst, Register src);
1769 void testl(Register dst, Address src);
1770
1771 void testq(Register dst, int32_t imm32);
1772 void testq(Register dst, Register src);
1773
1774 // BMI - count trailing zeros
1775 void tzcntl(Register dst, Register src);
1776 void tzcntq(Register dst, Register src);
1777
1778 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1779 void ucomisd(XMMRegister dst, Address src);
1780 void ucomisd(XMMRegister dst, XMMRegister src);
1781
1782 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1783 void ucomiss(XMMRegister dst, Address src);
1784 void ucomiss(XMMRegister dst, XMMRegister src);
1785
1786 void xabort(int8_t imm8);
1787
1788 void xaddl(Address dst, Register src);
1789
1790 void xaddq(Address dst, Register src);
1791
1792 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1793
1794 void xchgl(Register reg, Address adr);
1795 void xchgl(Register dst, Register src);
1796
1797 void xchgq(Register reg, Address adr);
1798 void xchgq(Register dst, Register src);
1799
1800 void xend();
1801
1802 // Get Value of Extended Control Register
1803 void xgetbv();
1804
1805 void xorl(Register dst, int32_t imm32);
1806 void xorl(Register dst, Address src);
1807 void xorl(Register dst, Register src);
1808
1809 void xorb(Register dst, Address src);
1810
1811 void xorq(Register dst, Address src);
1812 void xorq(Register dst, Register src);
1813
1814 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1815
1816 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1817
1818 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1819 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1820 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1821 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1822 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1823 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1824 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1825 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1826 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1827 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1828 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1829 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1830 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1831 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1832 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1833 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1834
1835
1836 //====================VECTOR ARITHMETIC=====================================
1837
1838 // Add Packed Floating-Point Values
1839 void addpd(XMMRegister dst, XMMRegister src);
1840 void addpd(XMMRegister dst, Address src);
1841 void addps(XMMRegister dst, XMMRegister src);
1842 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1843 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1844 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1845 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1846
1847 // Subtract Packed Floating-Point Values
1848 void subpd(XMMRegister dst, XMMRegister src);
1849 void subps(XMMRegister dst, XMMRegister src);
1850 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1851 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1852 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1853 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1854
1855 // Multiply Packed Floating-Point Values
1856 void mulpd(XMMRegister dst, XMMRegister src);
1857 void mulpd(XMMRegister dst, Address src);
1858 void mulps(XMMRegister dst, XMMRegister src);
1859 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1860 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1861 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1862 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1863
1864 // Divide Packed Floating-Point Values
1865 void divpd(XMMRegister dst, XMMRegister src);
1866 void divps(XMMRegister dst, XMMRegister src);
1867 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1868 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1869 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1870 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1871
1872 // Sqrt Packed Floating-Point Values - Double precision only
1873 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1874 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1875
1876 // Bitwise Logical AND of Packed Floating-Point Values
1877 void andpd(XMMRegister dst, XMMRegister src);
1878 void andps(XMMRegister dst, XMMRegister src);
1879 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1880 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1881 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1882 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1883
1884 void unpckhpd(XMMRegister dst, XMMRegister src);
1885 void unpcklpd(XMMRegister dst, XMMRegister src);
1886
1887 // Bitwise Logical XOR of Packed Floating-Point Values
1888 void xorpd(XMMRegister dst, XMMRegister src);
1889 void xorps(XMMRegister dst, XMMRegister src);
1890 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1891 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1892 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1893 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1894
1895 // Add horizontal packed integers
1896 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1897 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1898 void phaddw(XMMRegister dst, XMMRegister src);
1899 void phaddd(XMMRegister dst, XMMRegister src);
1900
1901 // Add packed integers
1902 void paddb(XMMRegister dst, XMMRegister src);
1903 void paddw(XMMRegister dst, XMMRegister src);
1904 void paddd(XMMRegister dst, XMMRegister src);
1905 void paddd(XMMRegister dst, Address src);
1906 void paddq(XMMRegister dst, XMMRegister src);
1907 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1908 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1909 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1910 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1911 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1912 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1913 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1914 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1915
1916 // Sub packed integers
1917 void psubb(XMMRegister dst, XMMRegister src);
1918 void psubw(XMMRegister dst, XMMRegister src);
1919 void psubd(XMMRegister dst, XMMRegister src);
1920 void psubq(XMMRegister dst, XMMRegister src);
1921 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1922 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1923 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1924 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1925 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1926 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1927 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1928 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1929
1930 // Multiply packed integers (only shorts and ints)
1931 void pmullw(XMMRegister dst, XMMRegister src);
1932 void pmulld(XMMRegister dst, XMMRegister src);
1933 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1934 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1935 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1936 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1937 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1938 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1939
1940 // Shift left packed integers
1941 void psllw(XMMRegister dst, int shift);
1942 void pslld(XMMRegister dst, int shift);
1943 void psllq(XMMRegister dst, int shift);
1944 void psllw(XMMRegister dst, XMMRegister shift);
1945 void pslld(XMMRegister dst, XMMRegister shift);
1946 void psllq(XMMRegister dst, XMMRegister shift);
1947 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1948 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1949 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1950 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1951 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1952 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1953
1954 // Logical shift right packed integers
1955 void psrlw(XMMRegister dst, int shift);
1956 void psrld(XMMRegister dst, int shift);
1957 void psrlq(XMMRegister dst, int shift);
1958 void psrlw(XMMRegister dst, XMMRegister shift);
1959 void psrld(XMMRegister dst, XMMRegister shift);
1960 void psrlq(XMMRegister dst, XMMRegister shift);
1961 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1962 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1963 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1964 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1965 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1966 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1967
1968 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1969 void psraw(XMMRegister dst, int shift);
1970 void psrad(XMMRegister dst, int shift);
1971 void psraw(XMMRegister dst, XMMRegister shift);
1972 void psrad(XMMRegister dst, XMMRegister shift);
1973 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1974 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1975 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1976 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1977
1978 // And packed integers
1979 void pand(XMMRegister dst, XMMRegister src);
1980 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1981 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1982
1983 // Andn packed integers
1984 void pandn(XMMRegister dst, XMMRegister src);
1985
1986 // Or packed integers
1987 void por(XMMRegister dst, XMMRegister src);
1988 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1989 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1990
1991 // Xor packed integers
1992 void pxor(XMMRegister dst, XMMRegister src);
1993 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1994 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1995
1996 // vinserti forms
1997 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1998 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
1999 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2000 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2001 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2002
2003 // vinsertf forms
2004 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2005 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2006 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2007 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2008 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2009 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2010
2011 // vextracti forms
2012 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2013 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2014 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2015 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2016 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2017 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2018
2019 // vextractf forms
2020 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2021 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2022 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2023 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2024 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2025 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2026 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2027
2028 // legacy xmm sourced word/dword replicate
2029 void vpbroadcastw(XMMRegister dst, XMMRegister src);
2030 void vpbroadcastd(XMMRegister dst, XMMRegister src);
2031
2032 // xmm/mem sourced byte/word/dword/qword replicate
2033 void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2034 void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2035 void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2036 void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2037 void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2038 void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2039 void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2040 void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2041
2042 // scalar single/double precision replicate
2043 void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2044 void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2045 void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2046 void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2047
2048 // gpr sourced byte/word/dword/qword replicate
2049 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2050 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2051 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2052 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2053
2054 // Carry-Less Multiplication Quadword
2055 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2056 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2057
2058 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2059 // to avoid transaction penalty between AVX and SSE states. There is no
2060 // penalty if legacy SSE instructions are encoded using VEX prefix because
2061 // they always clear upper 128 bits. It should be used before calling
2062 // runtime code and native libraries.
2063 void vzeroupper();
2064
2065 // AVX support for vectorized conditional move (double). The following two instructions used only coupled.
2066 void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2067 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2068
2069 void shlxl(Register dst, Register src1, Register src2);
2070 void shlxq(Register dst, Register src1, Register src2);
2071
2072 protected:
2073 // Next instructions require address alignment 16 bytes SSE mode.
2074 // They should be called only from corresponding MacroAssembler instructions.
2075 void andpd(XMMRegister dst, Address src);
2076 void andps(XMMRegister dst, Address src);
2077 void xorpd(XMMRegister dst, Address src);
2078 void xorps(XMMRegister dst, Address src);
2079
2080 };
2081
2082 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2083 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2084 // are applied.
2085 class InstructionAttr {
2086 public:
2087 InstructionAttr(
2088 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2089 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2090 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2091 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else k1 is used under the same condition
2092 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2093 :
2094 _avx_vector_len(vector_len),
2095 _rex_vex_w(rex_vex_w),
2096 _rex_vex_w_reverted(false),
2097 _legacy_mode(legacy_mode),
2098 _no_reg_mask(no_reg_mask),
2099 _uses_vl(uses_vl),
2100 _tuple_type(Assembler::EVEX_ETUP),
2101 _input_size_in_bits(Assembler::EVEX_NObit),
2102 _is_evex_instruction(false),
2103 _evex_encoding(0),
2104 _is_clear_context(false),
2105 _is_extended_context(false),
2106 _current_assembler(NULL),
2107 _embedded_opmask_register_specifier(1) { // hard code k1, it will be initialized for now
2108 if (UseAVX < 3) _legacy_mode = true;
2109 }
2110
2111 ~InstructionAttr() {
2112 if (_current_assembler != NULL) {
2113 _current_assembler->clear_attributes();
2114 }
2115 _current_assembler = NULL;
2116 }
2117
2118 private:
2119 int _avx_vector_len;
2120 bool _rex_vex_w;
2121 bool _rex_vex_w_reverted;
2122 bool _legacy_mode;
2123 bool _no_reg_mask;
2124 bool _uses_vl;
2125 int _tuple_type;
2126 int _input_size_in_bits;
2127 bool _is_evex_instruction;
2128 int _evex_encoding;
2129 bool _is_clear_context;
2130 bool _is_extended_context;
2131 int _embedded_opmask_register_specifier;
2132
2133 Assembler *_current_assembler;
2134
2135 public:
2136 // query functions for field accessors
2137 int get_vector_len(void) const { return _avx_vector_len; }
2138 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2139 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2140 bool is_legacy_mode(void) const { return _legacy_mode; }
2141 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2142 bool uses_vl(void) const { return _uses_vl; }
2143 int get_tuple_type(void) const { return _tuple_type; }
2144 int get_input_size(void) const { return _input_size_in_bits; }
2145 int is_evex_instruction(void) const { return _is_evex_instruction; }
2146 int get_evex_encoding(void) const { return _evex_encoding; }
2147 bool is_clear_context(void) const { return _is_clear_context; }
2148 bool is_extended_context(void) const { return _is_extended_context; }
2149
2150 // Set the vector len manually
2151 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2152
2153 // Set revert rex_vex_w for avx encoding
2154 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2155
2156 // Set rex_vex_w based on state
2157 void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2158
2159 // Set the instruction to be encoded in AVX mode
2160 void set_is_legacy_mode(void) { _legacy_mode = true; }
2161
2162 // Set the current instuction to be encoded as an EVEX instuction
2163 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2164
2165 // Internal encoding data used in compressed immediate offset programming
2166 void set_evex_encoding(int value) { _evex_encoding = value; }
2167
2168 // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2169 void set_is_clear_context(void) { _is_clear_context = true; }
2170
2171 // Map back to current asembler so that we can manage object level assocation
2172 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2173
2174 // Address modifiers used for compressed displacement calculation
2175 void set_address_attributes(int tuple_type, int input_size_in_bits) {
2176 if (VM_Version::supports_evex()) {
2177 _tuple_type = tuple_type;
2178 _input_size_in_bits = input_size_in_bits;
2179 }
2180 }
2181
2182 // Set embedded opmask register specifier.
2183 void set_embedded_opmask_register_specifier(KRegister mask) {
2184 _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2185 }
2186
2187 };
2188
2189 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP