1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 attributes.set_rex_vex_w_reverted();
1244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1245 emit_int8(0x58);
1246 emit_int8((unsigned char)(0xC0 | encode));
1247 }
1248
1249 void Assembler::addsd(XMMRegister dst, Address src) {
1250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1251 InstructionMark im(this);
1252 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1253 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1254 attributes.set_rex_vex_w_reverted();
1255 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1256 emit_int8(0x58);
1257 emit_operand(dst, src);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1264 emit_int8(0x58);
1265 emit_int8((unsigned char)(0xC0 | encode));
1266 }
1267
1268 void Assembler::addss(XMMRegister dst, Address src) {
1269 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1270 InstructionMark im(this);
1271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1272 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1273 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1274 emit_int8(0x58);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, Address src) {
1279 assert(VM_Version::supports_aes(), "");
1280 InstructionMark im(this);
1281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1282 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1283 emit_int8((unsigned char)0xDE);
1284 emit_operand(dst, src);
1285 }
1286
1287 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1288 assert(VM_Version::supports_aes(), "");
1289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1291 emit_int8((unsigned char)0xDE);
1292 emit_int8(0xC0 | encode);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1296 assert(VM_Version::supports_aes(), "");
1297 InstructionMark im(this);
1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1300 emit_int8((unsigned char)0xDF);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1308 emit_int8((unsigned char)0xDF);
1309 emit_int8((unsigned char)(0xC0 | encode));
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDC);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDC);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, Address src) {
1330 assert(VM_Version::supports_aes(), "");
1331 InstructionMark im(this);
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDD);
1335 emit_operand(dst, src);
1336 }
1337
1338 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1342 emit_int8((unsigned char)0xDD);
1343 emit_int8((unsigned char)(0xC0 | encode));
1344 }
1345
1346 void Assembler::andl(Address dst, int32_t imm32) {
1347 InstructionMark im(this);
1348 prefix(dst);
1349 emit_int8((unsigned char)0x81);
1350 emit_operand(rsp, dst, 4);
1351 emit_int32(imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, int32_t imm32) {
1355 prefix(dst);
1356 emit_arith(0x81, 0xE0, dst, imm32);
1357 }
1358
1359 void Assembler::andl(Register dst, Address src) {
1360 InstructionMark im(this);
1361 prefix(src, dst);
1362 emit_int8(0x23);
1363 emit_operand(dst, src);
1364 }
1365
1366 void Assembler::andl(Register dst, Register src) {
1367 (void) prefix_and_encode(dst->encoding(), src->encoding());
1368 emit_arith(0x23, 0xC0, dst, src);
1369 }
1370
1371 void Assembler::andnl(Register dst, Register src1, Register src2) {
1372 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1374 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1375 emit_int8((unsigned char)0xF2);
1376 emit_int8((unsigned char)(0xC0 | encode));
1377 }
1378
1379 void Assembler::andnl(Register dst, Register src1, Address src2) {
1380 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1381 InstructionMark im(this);
1382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1383 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1384 emit_int8((unsigned char)0xF2);
1385 emit_operand(dst, src2);
1386 }
1387
1388 void Assembler::bsfl(Register dst, Register src) {
1389 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1390 emit_int8(0x0F);
1391 emit_int8((unsigned char)0xBC);
1392 emit_int8((unsigned char)(0xC0 | encode));
1393 }
1394
1395 void Assembler::bsrl(Register dst, Register src) {
1396 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1397 emit_int8(0x0F);
1398 emit_int8((unsigned char)0xBD);
1399 emit_int8((unsigned char)(0xC0 | encode));
1400 }
1401
1402 void Assembler::bswapl(Register reg) { // bswap
1403 int encode = prefix_and_encode(reg->encoding());
1404 emit_int8(0x0F);
1405 emit_int8((unsigned char)(0xC8 | encode));
1406 }
1407
1408 void Assembler::blsil(Register dst, Register src) {
1409 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1410 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1411 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1412 emit_int8((unsigned char)0xF3);
1413 emit_int8((unsigned char)(0xC0 | encode));
1414 }
1415
1416 void Assembler::blsil(Register dst, Address src) {
1417 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1418 InstructionMark im(this);
1419 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1420 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1421 emit_int8((unsigned char)0xF3);
1422 emit_operand(rbx, src);
1423 }
1424
1425 void Assembler::blsmskl(Register dst, Register src) {
1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1428 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1429 emit_int8((unsigned char)0xF3);
1430 emit_int8((unsigned char)(0xC0 | encode));
1431 }
1432
1433 void Assembler::blsmskl(Register dst, Address src) {
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 InstructionMark im(this);
1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1437 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rdx, src);
1440 }
1441
1442 void Assembler::blsrl(Register dst, Register src) {
1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1445 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1446 emit_int8((unsigned char)0xF3);
1447 emit_int8((unsigned char)(0xC0 | encode));
1448 }
1449
1450 void Assembler::blsrl(Register dst, Address src) {
1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1452 InstructionMark im(this);
1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1454 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1455 emit_int8((unsigned char)0xF3);
1456 emit_operand(rcx, src);
1457 }
1458
1459 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1460 // suspect disp32 is always good
1461 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1462
1463 if (L.is_bound()) {
1464 const int long_size = 5;
1465 int offs = (int)( target(L) - pc() );
1466 assert(offs <= 0, "assembler error");
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 emit_int8((unsigned char)0xE8);
1470 emit_data(offs - long_size, rtype, operand);
1471 } else {
1472 InstructionMark im(this);
1473 // 1110 1000 #32-bit disp
1474 L.add_patch_at(code(), locator());
1475
1476 emit_int8((unsigned char)0xE8);
1477 emit_data(int(0), rtype, operand);
1478 }
1479 }
1480
1481 void Assembler::call(Register dst) {
1482 int encode = prefix_and_encode(dst->encoding());
1483 emit_int8((unsigned char)0xFF);
1484 emit_int8((unsigned char)(0xD0 | encode));
1485 }
1486
1487
1488 void Assembler::call(Address adr) {
1489 InstructionMark im(this);
1490 prefix(adr);
1491 emit_int8((unsigned char)0xFF);
1492 emit_operand(rdx, adr);
1493 }
1494
1495 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1496 assert(entry != NULL, "call most probably wrong");
1497 InstructionMark im(this);
1498 emit_int8((unsigned char)0xE8);
1499 intptr_t disp = entry - (pc() + sizeof(int32_t));
1500 assert(is_simm32(disp), "must be 32bit offset (call2)");
1501 // Technically, should use call32_operand, but this format is
1502 // implied by the fact that we're emitting a call instruction.
1503
1504 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1505 emit_data((int) disp, rspec, operand);
1506 }
1507
1508 void Assembler::cdql() {
1509 emit_int8((unsigned char)0x99);
1510 }
1511
1512 void Assembler::cld() {
1513 emit_int8((unsigned char)0xFC);
1514 }
1515
1516 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1517 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1518 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1519 emit_int8(0x0F);
1520 emit_int8(0x40 | cc);
1521 emit_int8((unsigned char)(0xC0 | encode));
1522 }
1523
1524
1525 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1526 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1527 prefix(src, dst);
1528 emit_int8(0x0F);
1529 emit_int8(0x40 | cc);
1530 emit_operand(dst, src);
1531 }
1532
1533 void Assembler::cmpb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_int8((unsigned char)0x80);
1537 emit_operand(rdi, dst, 1);
1538 emit_int8(imm8);
1539 }
1540
1541 void Assembler::cmpl(Address dst, int32_t imm32) {
1542 InstructionMark im(this);
1543 prefix(dst);
1544 emit_int8((unsigned char)0x81);
1545 emit_operand(rdi, dst, 4);
1546 emit_int32(imm32);
1547 }
1548
1549 void Assembler::cmpl(Register dst, int32_t imm32) {
1550 prefix(dst);
1551 emit_arith(0x81, 0xF8, dst, imm32);
1552 }
1553
1554 void Assembler::cmpl(Register dst, Register src) {
1555 (void) prefix_and_encode(dst->encoding(), src->encoding());
1556 emit_arith(0x3B, 0xC0, dst, src);
1557 }
1558
1559 void Assembler::cmpl(Register dst, Address src) {
1560 InstructionMark im(this);
1561 prefix(src, dst);
1562 emit_int8((unsigned char)0x3B);
1563 emit_operand(dst, src);
1564 }
1565
1566 void Assembler::cmpw(Address dst, int imm16) {
1567 InstructionMark im(this);
1568 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1569 emit_int8(0x66);
1570 emit_int8((unsigned char)0x81);
1571 emit_operand(rdi, dst, 2);
1572 emit_int16(imm16);
1573 }
1574
1575 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1576 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1577 // The ZF is set if the compared values were equal, and cleared otherwise.
1578 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1579 InstructionMark im(this);
1580 prefix(adr, reg);
1581 emit_int8(0x0F);
1582 emit_int8((unsigned char)0xB1);
1583 emit_operand(reg, adr);
1584 }
1585
1586 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1587 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1588 // The ZF is set if the compared values were equal, and cleared otherwise.
1589 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1590 InstructionMark im(this);
1591 prefix(adr, reg, true);
1592 emit_int8(0x0F);
1593 emit_int8((unsigned char)0xB0);
1594 emit_operand(reg, adr);
1595 }
1596
1597 void Assembler::comisd(XMMRegister dst, Address src) {
1598 // NOTE: dbx seems to decode this as comiss even though the
1599 // 0x66 is there. Strangly ucomisd comes out correct
1600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1601 InstructionMark im(this);
1602 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1604 attributes.set_rex_vex_w_reverted();
1605 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1606 emit_int8(0x2F);
1607 emit_operand(dst, src);
1608 }
1609
1610 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1613 attributes.set_rex_vex_w_reverted();
1614 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1615 emit_int8(0x2F);
1616 emit_int8((unsigned char)(0xC0 | encode));
1617 }
1618
1619 void Assembler::comiss(XMMRegister dst, Address src) {
1620 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1621 InstructionMark im(this);
1622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1623 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1624 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1625 emit_int8(0x2F);
1626 emit_operand(dst, src);
1627 }
1628
1629 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1632 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1633 emit_int8(0x2F);
1634 emit_int8((unsigned char)(0xC0 | encode));
1635 }
1636
1637 void Assembler::cpuid() {
1638 emit_int8(0x0F);
1639 emit_int8((unsigned char)0xA2);
1640 }
1641
1642 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1643 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1644 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1645 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1646 //
1647 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1648 //
1649 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1650 //
1651 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1652 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1653 assert(VM_Version::supports_sse4_2(), "");
1654 int8_t w = 0x01;
1655 Prefix p = Prefix_EMPTY;
1656
1657 emit_int8((int8_t)0xF2);
1658 switch (sizeInBytes) {
1659 case 1:
1660 w = 0;
1661 break;
1662 case 2:
1663 case 4:
1664 break;
1665 LP64_ONLY(case 8:)
1666 // This instruction is not valid in 32 bits
1667 // Note:
1668 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1669 //
1670 // Page B - 72 Vol. 2C says
1671 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1672 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1673 // F0!!!
1674 // while 3 - 208 Vol. 2A
1675 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1676 //
1677 // the 0 on a last bit is reserved for a different flavor of this instruction :
1678 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1679 p = REX_W;
1680 break;
1681 default:
1682 assert(0, "Unsupported value for a sizeInBytes argument");
1683 break;
1684 }
1685 LP64_ONLY(prefix(crc, v, p);)
1686 emit_int8((int8_t)0x0F);
1687 emit_int8(0x38);
1688 emit_int8((int8_t)(0xF0 | w));
1689 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1690 }
1691
1692 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1693 assert(VM_Version::supports_sse4_2(), "");
1694 InstructionMark im(this);
1695 int8_t w = 0x01;
1696 Prefix p = Prefix_EMPTY;
1697
1698 emit_int8((int8_t)0xF2);
1699 switch (sizeInBytes) {
1700 case 1:
1701 w = 0;
1702 break;
1703 case 2:
1704 case 4:
1705 break;
1706 LP64_ONLY(case 8:)
1707 // This instruction is not valid in 32 bits
1708 p = REX_W;
1709 break;
1710 default:
1711 assert(0, "Unsupported value for a sizeInBytes argument");
1712 break;
1713 }
1714 LP64_ONLY(prefix(crc, adr, p);)
1715 emit_int8((int8_t)0x0F);
1716 emit_int8(0x38);
1717 emit_int8((int8_t)(0xF0 | w));
1718 emit_operand(crc, adr);
1719 }
1720
1721 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1724 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1725 emit_int8((unsigned char)0xE6);
1726 emit_int8((unsigned char)(0xC0 | encode));
1727 }
1728
1729 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1731 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1732 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1733 emit_int8(0x5B);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1740 attributes.set_rex_vex_w_reverted();
1741 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1742 emit_int8(0x5A);
1743 emit_int8((unsigned char)(0xC0 | encode));
1744 }
1745
1746 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 InstructionMark im(this);
1749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1751 attributes.set_rex_vex_w_reverted();
1752 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x5A);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1761 emit_int8(0x2A);
1762 emit_int8((unsigned char)(0xC0 | encode));
1763 }
1764
1765 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 InstructionMark im(this);
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1770 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_operand(dst, src);
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1779 emit_int8(0x2A);
1780 emit_int8((unsigned char)(0xC0 | encode));
1781 }
1782
1783 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1784 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1785 InstructionMark im(this);
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1788 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_operand(dst, src);
1791 }
1792
1793 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x2A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_int8((unsigned char)(0xC0 | encode));
1807 }
1808
1809 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionMark im(this);
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1813 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1814 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x5A);
1816 emit_operand(dst, src);
1817 }
1818
1819
1820 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2C);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1839 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1840 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1841 emit_int8((unsigned char)0xE6);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::decl(Address dst) {
1846 // Don't use it directly. Use MacroAssembler::decrement() instead.
1847 InstructionMark im(this);
1848 prefix(dst);
1849 emit_int8((unsigned char)0xFF);
1850 emit_operand(rcx, dst);
1851 }
1852
1853 void Assembler::divsd(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1858 attributes.set_rex_vex_w_reverted();
1859 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 attributes.set_rex_vex_w_reverted();
1868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1869 emit_int8(0x5E);
1870 emit_int8((unsigned char)(0xC0 | encode));
1871 }
1872
1873 void Assembler::divss(XMMRegister dst, Address src) {
1874 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1875 InstructionMark im(this);
1876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1878 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879 emit_int8(0x5E);
1880 emit_operand(dst, src);
1881 }
1882
1883 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1884 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1886 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1887 emit_int8(0x5E);
1888 emit_int8((unsigned char)(0xC0 | encode));
1889 }
1890
1891 void Assembler::emms() {
1892 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1893 emit_int8(0x0F);
1894 emit_int8(0x77);
1895 }
1896
1897 void Assembler::hlt() {
1898 emit_int8((unsigned char)0xF4);
1899 }
1900
1901 void Assembler::idivl(Register src) {
1902 int encode = prefix_and_encode(src->encoding());
1903 emit_int8((unsigned char)0xF7);
1904 emit_int8((unsigned char)(0xF8 | encode));
1905 }
1906
1907 void Assembler::divl(Register src) { // Unsigned
1908 int encode = prefix_and_encode(src->encoding());
1909 emit_int8((unsigned char)0xF7);
1910 emit_int8((unsigned char)(0xF0 | encode));
1911 }
1912
1913 void Assembler::imull(Register src) {
1914 int encode = prefix_and_encode(src->encoding());
1915 emit_int8((unsigned char)0xF7);
1916 emit_int8((unsigned char)(0xE8 | encode));
1917 }
1918
1919 void Assembler::imull(Register dst, Register src) {
1920 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921 emit_int8(0x0F);
1922 emit_int8((unsigned char)0xAF);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926
1927 void Assembler::imull(Register dst, Register src, int value) {
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 if (is8bit(value)) {
1930 emit_int8(0x6B);
1931 emit_int8((unsigned char)(0xC0 | encode));
1932 emit_int8(value & 0xFF);
1933 } else {
1934 emit_int8(0x69);
1935 emit_int8((unsigned char)(0xC0 | encode));
1936 emit_int32(value);
1937 }
1938 }
1939
1940 void Assembler::imull(Register dst, Address src) {
1941 InstructionMark im(this);
1942 prefix(src, dst);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char) 0xAF);
1945 emit_operand(dst, src);
1946 }
1947
1948
1949 void Assembler::incl(Address dst) {
1950 // Don't use it directly. Use MacroAssembler::increment() instead.
1951 InstructionMark im(this);
1952 prefix(dst);
1953 emit_int8((unsigned char)0xFF);
1954 emit_operand(rax, dst);
1955 }
1956
1957 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1958 InstructionMark im(this);
1959 assert((0 <= cc) && (cc < 16), "illegal cc");
1960 if (L.is_bound()) {
1961 address dst = target(L);
1962 assert(dst != NULL, "jcc most probably wrong");
1963
1964 const int short_size = 2;
1965 const int long_size = 6;
1966 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1967 if (maybe_short && is8bit(offs - short_size)) {
1968 // 0111 tttn #8-bit disp
1969 emit_int8(0x70 | cc);
1970 emit_int8((offs - short_size) & 0xFF);
1971 } else {
1972 // 0000 1111 1000 tttn #32-bit disp
1973 assert(is_simm32(offs - long_size),
1974 "must be 32bit offset (call4)");
1975 emit_int8(0x0F);
1976 emit_int8((unsigned char)(0x80 | cc));
1977 emit_int32(offs - long_size);
1978 }
1979 } else {
1980 // Note: could eliminate cond. jumps to this jump if condition
1981 // is the same however, seems to be rather unlikely case.
1982 // Note: use jccb() if label to be bound is very close to get
1983 // an 8-bit displacement
1984 L.add_patch_at(code(), locator());
1985 emit_int8(0x0F);
1986 emit_int8((unsigned char)(0x80 | cc));
1987 emit_int32(0);
1988 }
1989 }
1990
1991 void Assembler::jccb(Condition cc, Label& L) {
1992 if (L.is_bound()) {
1993 const int short_size = 2;
1994 address entry = target(L);
1995 #ifdef ASSERT
1996 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1997 intptr_t delta = short_branch_delta();
1998 if (delta != 0) {
1999 dist += (dist < 0 ? (-delta) :delta);
2000 }
2001 assert(is8bit(dist), "Dispacement too large for a short jmp");
2002 #endif
2003 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2004 // 0111 tttn #8-bit disp
2005 emit_int8(0x70 | cc);
2006 emit_int8((offs - short_size) & 0xFF);
2007 } else {
2008 InstructionMark im(this);
2009 L.add_patch_at(code(), locator());
2010 emit_int8(0x70 | cc);
2011 emit_int8(0);
2012 }
2013 }
2014
2015 void Assembler::jmp(Address adr) {
2016 InstructionMark im(this);
2017 prefix(adr);
2018 emit_int8((unsigned char)0xFF);
2019 emit_operand(rsp, adr);
2020 }
2021
2022 void Assembler::jmp(Label& L, bool maybe_short) {
2023 if (L.is_bound()) {
2024 address entry = target(L);
2025 assert(entry != NULL, "jmp most probably wrong");
2026 InstructionMark im(this);
2027 const int short_size = 2;
2028 const int long_size = 5;
2029 intptr_t offs = entry - pc();
2030 if (maybe_short && is8bit(offs - short_size)) {
2031 emit_int8((unsigned char)0xEB);
2032 emit_int8((offs - short_size) & 0xFF);
2033 } else {
2034 emit_int8((unsigned char)0xE9);
2035 emit_int32(offs - long_size);
2036 }
2037 } else {
2038 // By default, forward jumps are always 32-bit displacements, since
2039 // we can't yet know where the label will be bound. If you're sure that
2040 // the forward jump will not run beyond 256 bytes, use jmpb to
2041 // force an 8-bit displacement.
2042 InstructionMark im(this);
2043 L.add_patch_at(code(), locator());
2044 emit_int8((unsigned char)0xE9);
2045 emit_int32(0);
2046 }
2047 }
2048
2049 void Assembler::jmp(Register entry) {
2050 int encode = prefix_and_encode(entry->encoding());
2051 emit_int8((unsigned char)0xFF);
2052 emit_int8((unsigned char)(0xE0 | encode));
2053 }
2054
2055 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2056 InstructionMark im(this);
2057 emit_int8((unsigned char)0xE9);
2058 assert(dest != NULL, "must have a target");
2059 intptr_t disp = dest - (pc() + sizeof(int32_t));
2060 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2061 emit_data(disp, rspec.reloc(), call32_operand);
2062 }
2063
2064 void Assembler::jmpb(Label& L) {
2065 if (L.is_bound()) {
2066 const int short_size = 2;
2067 address entry = target(L);
2068 assert(entry != NULL, "jmp most probably wrong");
2069 #ifdef ASSERT
2070 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2071 intptr_t delta = short_branch_delta();
2072 if (delta != 0) {
2073 dist += (dist < 0 ? (-delta) :delta);
2074 }
2075 assert(is8bit(dist), "Dispacement too large for a short jmp");
2076 #endif
2077 intptr_t offs = entry - pc();
2078 emit_int8((unsigned char)0xEB);
2079 emit_int8((offs - short_size) & 0xFF);
2080 } else {
2081 InstructionMark im(this);
2082 L.add_patch_at(code(), locator());
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8(0);
2085 }
2086 }
2087
2088 void Assembler::ldmxcsr( Address src) {
2089 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2090 InstructionMark im(this);
2091 prefix(src);
2092 emit_int8(0x0F);
2093 emit_int8((unsigned char)0xAE);
2094 emit_operand(as_Register(2), src);
2095 }
2096
2097 void Assembler::leal(Register dst, Address src) {
2098 InstructionMark im(this);
2099 #ifdef _LP64
2100 emit_int8(0x67); // addr32
2101 prefix(src, dst);
2102 #endif // LP64
2103 emit_int8((unsigned char)0x8D);
2104 emit_operand(dst, src);
2105 }
2106
2107 void Assembler::lfence() {
2108 emit_int8(0x0F);
2109 emit_int8((unsigned char)0xAE);
2110 emit_int8((unsigned char)0xE8);
2111 }
2112
2113 void Assembler::lock() {
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::lzcntl(Register dst, Register src) {
2118 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2119 emit_int8((unsigned char)0xF3);
2120 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2121 emit_int8(0x0F);
2122 emit_int8((unsigned char)0xBD);
2123 emit_int8((unsigned char)(0xC0 | encode));
2124 }
2125
2126 // Emit mfence instruction
2127 void Assembler::mfence() {
2128 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2129 emit_int8(0x0F);
2130 emit_int8((unsigned char)0xAE);
2131 emit_int8((unsigned char)0xF0);
2132 }
2133
2134 void Assembler::mov(Register dst, Register src) {
2135 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2136 }
2137
2138 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2140 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2141 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2142 attributes.set_rex_vex_w_reverted();
2143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2144 emit_int8(0x28);
2145 emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147
2148 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2151 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2152 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2153 emit_int8(0x28);
2154 emit_int8((unsigned char)(0xC0 | encode));
2155 }
2156
2157 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2158 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2160 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2161 emit_int8(0x16);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 void Assembler::movb(Register dst, Address src) {
2166 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2167 InstructionMark im(this);
2168 prefix(src, dst, true);
2169 emit_int8((unsigned char)0x8A);
2170 emit_operand(dst, src);
2171 }
2172
2173 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2174 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2175 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2176 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2177 attributes.set_rex_vex_w_reverted();
2178 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2179 emit_int8(0x12);
2180 emit_int8(0xC0 | encode);
2181 }
2182
2183 void Assembler::kmovbl(KRegister dst, Register src) {
2184 assert(VM_Version::supports_avx512dq(), "");
2185 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2186 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2187 emit_int8((unsigned char)0x92);
2188 emit_int8((unsigned char)(0xC0 | encode));
2189 }
2190
2191 void Assembler::kmovbl(Register dst, KRegister src) {
2192 assert(VM_Version::supports_avx512dq(), "");
2193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2194 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2195 emit_int8((unsigned char)0x93);
2196 emit_int8((unsigned char)(0xC0 | encode));
2197 }
2198
2199 void Assembler::kmovwl(KRegister dst, Register src) {
2200 assert(VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::kmovwl(Register dst, KRegister src) {
2208 assert(VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2211 emit_int8((unsigned char)0x93);
2212 emit_int8((unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::kmovwl(KRegister dst, Address src) {
2216 assert(VM_Version::supports_evex(), "");
2217 InstructionMark im(this);
2218 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2219 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2220 emit_int8((unsigned char)0x90);
2221 emit_operand((Register)dst, src);
2222 }
2223
2224 void Assembler::kmovdl(KRegister dst, Register src) {
2225 assert(VM_Version::supports_avx512bw(), "");
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x92);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::kmovdl(Register dst, KRegister src) {
2233 assert(VM_Version::supports_avx512bw(), "");
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2236 emit_int8((unsigned char)0x93);
2237 emit_int8((unsigned char)(0xC0 | encode));
2238 }
2239
2240 void Assembler::kmovql(KRegister dst, KRegister src) {
2241 assert(VM_Version::supports_avx512bw(), "");
2242 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2243 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int8((unsigned char)0x90);
2245 emit_int8((unsigned char)(0xC0 | encode));
2246 }
2247
2248 void Assembler::kmovql(KRegister dst, Address src) {
2249 assert(VM_Version::supports_avx512bw(), "");
2250 InstructionMark im(this);
2251 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2252 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2253 emit_int8((unsigned char)0x90);
2254 emit_operand((Register)dst, src);
2255 }
2256
2257 void Assembler::kmovql(Address dst, KRegister src) {
2258 assert(VM_Version::supports_avx512bw(), "");
2259 InstructionMark im(this);
2260 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2261 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2262 emit_int8((unsigned char)0x90);
2263 emit_operand((Register)src, dst);
2264 }
2265
2266 void Assembler::kmovql(KRegister dst, Register src) {
2267 assert(VM_Version::supports_avx512bw(), "");
2268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2269 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2270 emit_int8((unsigned char)0x92);
2271 emit_int8((unsigned char)(0xC0 | encode));
2272 }
2273
2274 void Assembler::kmovql(Register dst, KRegister src) {
2275 assert(VM_Version::supports_avx512bw(), "");
2276 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2277 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2278 emit_int8((unsigned char)0x93);
2279 emit_int8((unsigned char)(0xC0 | encode));
2280 }
2281
2282 void Assembler::knotwl(KRegister dst, KRegister src) {
2283 assert(VM_Version::supports_evex(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x44);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2292 assert(VM_Version::supports_avx512dq(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x98);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 // This instruction produces ZF or CF flags
2300 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2301 assert(VM_Version::supports_evex(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x98);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 // This instruction produces ZF or CF flags
2309 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x98);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 // This instruction produces ZF or CF flags
2318 void Assembler::kortestql(KRegister src1, KRegister src2) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x98);
2323 emit_int8((unsigned char)(0xC0 | encode));
2324 }
2325
2326 // This instruction produces ZF or CF flags
2327 void Assembler::ktestql(KRegister src1, KRegister src2) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x99);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::movb(Address dst, int imm8) {
2336 InstructionMark im(this);
2337 prefix(dst);
2338 emit_int8((unsigned char)0xC6);
2339 emit_operand(rax, dst, 1);
2340 emit_int8(imm8);
2341 }
2342
2343
2344 void Assembler::movb(Address dst, Register src) {
2345 assert(src->has_byte_register(), "must have byte register");
2346 InstructionMark im(this);
2347 prefix(dst, src, true);
2348 emit_int8((unsigned char)0x88);
2349 emit_operand(src, dst);
2350 }
2351
2352 void Assembler::movdl(XMMRegister dst, Register src) {
2353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2355 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2356 emit_int8(0x6E);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 void Assembler::movdl(Register dst, XMMRegister src) {
2361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2363 // swap src/dst to get correct prefix
2364 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2365 emit_int8(0x7E);
2366 emit_int8((unsigned char)(0xC0 | encode));
2367 }
2368
2369 void Assembler::movdl(XMMRegister dst, Address src) {
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 InstructionMark im(this);
2372 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2373 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2374 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2375 emit_int8(0x6E);
2376 emit_operand(dst, src);
2377 }
2378
2379 void Assembler::movdl(Address dst, XMMRegister src) {
2380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2381 InstructionMark im(this);
2382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2383 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2384 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2385 emit_int8(0x7E);
2386 emit_operand(src, dst);
2387 }
2388
2389 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2391 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2392 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2393 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2394 emit_int8(0x6F);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 }
2397
2398 void Assembler::movdqa(XMMRegister dst, Address src) {
2399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2400 InstructionMark im(this);
2401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2403 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2404 emit_int8(0x6F);
2405 emit_operand(dst, src);
2406 }
2407
2408 void Assembler::movdqu(XMMRegister dst, Address src) {
2409 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2410 InstructionMark im(this);
2411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2412 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2413 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2414 emit_int8(0x6F);
2415 emit_operand(dst, src);
2416 }
2417
2418 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2421 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2422 emit_int8(0x6F);
2423 emit_int8((unsigned char)(0xC0 | encode));
2424 }
2425
2426 void Assembler::movdqu(Address dst, XMMRegister src) {
2427 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2428 InstructionMark im(this);
2429 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2430 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2431 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x7F);
2433 emit_operand(src, dst);
2434 }
2435
2436 // Move Unaligned 256bit Vector
2437 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2438 assert(UseAVX > 0, "");
2439 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2440 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2441 emit_int8(0x6F);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2446 assert(UseAVX > 0, "");
2447 InstructionMark im(this);
2448 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2450 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x6F);
2452 emit_operand(dst, src);
2453 }
2454
2455 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2456 assert(UseAVX > 0, "");
2457 InstructionMark im(this);
2458 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2459 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2460 // swap src<->dst for encoding
2461 assert(src != xnoreg, "sanity");
2462 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2463 emit_int8(0x7F);
2464 emit_operand(src, dst);
2465 }
2466
2467 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2468 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2469 assert(VM_Version::supports_evex(), "");
2470 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2471 attributes.set_is_evex_instruction();
2472 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2473 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2474 emit_int8(0x6F);
2475 emit_int8((unsigned char)(0xC0 | encode));
2476 }
2477
2478 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2479 assert(VM_Version::supports_evex(), "");
2480 InstructionMark im(this);
2481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2482 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2483 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2484 attributes.set_is_evex_instruction();
2485 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2486 emit_int8(0x6F);
2487 emit_operand(dst, src);
2488 }
2489
2490 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2491 assert(VM_Version::supports_evex(), "");
2492 assert(src != xnoreg, "sanity");
2493 InstructionMark im(this);
2494 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2495 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2496 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2497 attributes.set_is_evex_instruction();
2498 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2499 emit_int8(0x7F);
2500 emit_operand(src, dst);
2501 }
2502
2503 void Assembler::evmovdqub(KRegister mask, XMMRegister dst, Address src, int vector_len) {
2504 assert(VM_Version::supports_avx512vlbw(), "");
2505 assert(is_vector_masking(), ""); // For stub code use only
2506 InstructionMark im(this);
2507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2508 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2509 attributes.set_embedded_opmask_register_specifier(mask);
2510 attributes.set_is_evex_instruction();
2511 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2512 emit_int8(0x6F);
2513 emit_operand(dst, src);
2514 }
2515
2516 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2517 assert(VM_Version::supports_evex(), "");
2518 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2519 attributes.set_is_evex_instruction();
2520 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2521 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2522 emit_int8(0x6F);
2523 emit_int8((unsigned char)(0xC0 | encode));
2524 }
2525
2526 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2527 assert(VM_Version::supports_evex(), "");
2528 InstructionMark im(this);
2529 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2530 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2531 attributes.set_is_evex_instruction();
2532 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2533 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2534 emit_int8(0x6F);
2535 emit_operand(dst, src);
2536 }
2537
2538 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2539 assert(VM_Version::supports_evex(), "");
2540 assert(src != xnoreg, "sanity");
2541 InstructionMark im(this);
2542 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2543 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2544 attributes.set_is_evex_instruction();
2545 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2546 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2547 emit_int8(0x7F);
2548 emit_operand(src, dst);
2549 }
2550
2551 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2552 assert(VM_Version::supports_evex(), "");
2553 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2554 attributes.set_is_evex_instruction();
2555 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2556 emit_int8(0x6F);
2557 emit_int8((unsigned char)(0xC0 | encode));
2558 }
2559
2560 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2561 assert(VM_Version::supports_evex(), "");
2562 InstructionMark im(this);
2563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2564 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2565 attributes.set_is_evex_instruction();
2566 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2567 emit_int8(0x6F);
2568 emit_operand(dst, src);
2569 }
2570
2571 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2572 assert(VM_Version::supports_evex(), "");
2573 assert(src != xnoreg, "sanity");
2574 InstructionMark im(this);
2575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2576 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2577 attributes.set_is_evex_instruction();
2578 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2579 emit_int8(0x7F);
2580 emit_operand(src, dst);
2581 }
2582
2583 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2584 assert(VM_Version::supports_evex(), "");
2585 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2586 attributes.set_is_evex_instruction();
2587 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_int8((unsigned char)(0xC0 | encode));
2590 }
2591
2592 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2593 assert(VM_Version::supports_evex(), "");
2594 InstructionMark im(this);
2595 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.set_is_evex_instruction();
2598 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2599 emit_int8(0x6F);
2600 emit_operand(dst, src);
2601 }
2602
2603 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2604 assert(VM_Version::supports_evex(), "");
2605 assert(src != xnoreg, "sanity");
2606 InstructionMark im(this);
2607 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2609 attributes.set_is_evex_instruction();
2610 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2611 emit_int8(0x7F);
2612 emit_operand(src, dst);
2613 }
2614
2615 // Uses zero extension on 64bit
2616
2617 void Assembler::movl(Register dst, int32_t imm32) {
2618 int encode = prefix_and_encode(dst->encoding());
2619 emit_int8((unsigned char)(0xB8 | encode));
2620 emit_int32(imm32);
2621 }
2622
2623 void Assembler::movl(Register dst, Register src) {
2624 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2625 emit_int8((unsigned char)0x8B);
2626 emit_int8((unsigned char)(0xC0 | encode));
2627 }
2628
2629 void Assembler::movl(Register dst, Address src) {
2630 InstructionMark im(this);
2631 prefix(src, dst);
2632 emit_int8((unsigned char)0x8B);
2633 emit_operand(dst, src);
2634 }
2635
2636 void Assembler::movl(Address dst, int32_t imm32) {
2637 InstructionMark im(this);
2638 prefix(dst);
2639 emit_int8((unsigned char)0xC7);
2640 emit_operand(rax, dst, 4);
2641 emit_int32(imm32);
2642 }
2643
2644 void Assembler::movl(Address dst, Register src) {
2645 InstructionMark im(this);
2646 prefix(dst, src);
2647 emit_int8((unsigned char)0x89);
2648 emit_operand(src, dst);
2649 }
2650
2651 // New cpus require to use movsd and movss to avoid partial register stall
2652 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2653 // The selection is done in MacroAssembler::movdbl() and movflt().
2654 void Assembler::movlpd(XMMRegister dst, Address src) {
2655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2656 InstructionMark im(this);
2657 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2658 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2659 attributes.set_rex_vex_w_reverted();
2660 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2661 emit_int8(0x12);
2662 emit_operand(dst, src);
2663 }
2664
2665 void Assembler::movq( MMXRegister dst, Address src ) {
2666 assert( VM_Version::supports_mmx(), "" );
2667 emit_int8(0x0F);
2668 emit_int8(0x6F);
2669 emit_operand(dst, src);
2670 }
2671
2672 void Assembler::movq( Address dst, MMXRegister src ) {
2673 assert( VM_Version::supports_mmx(), "" );
2674 emit_int8(0x0F);
2675 emit_int8(0x7F);
2676 // workaround gcc (3.2.1-7a) bug
2677 // In that version of gcc with only an emit_operand(MMX, Address)
2678 // gcc will tail jump and try and reverse the parameters completely
2679 // obliterating dst in the process. By having a version available
2680 // that doesn't need to swap the args at the tail jump the bug is
2681 // avoided.
2682 emit_operand(dst, src);
2683 }
2684
2685 void Assembler::movq(XMMRegister dst, Address src) {
2686 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2687 InstructionMark im(this);
2688 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2689 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2690 attributes.set_rex_vex_w_reverted();
2691 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2692 emit_int8(0x7E);
2693 emit_operand(dst, src);
2694 }
2695
2696 void Assembler::movq(Address dst, XMMRegister src) {
2697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2698 InstructionMark im(this);
2699 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2700 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2701 attributes.set_rex_vex_w_reverted();
2702 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2703 emit_int8((unsigned char)0xD6);
2704 emit_operand(src, dst);
2705 }
2706
2707 void Assembler::movsbl(Register dst, Address src) { // movsxb
2708 InstructionMark im(this);
2709 prefix(src, dst);
2710 emit_int8(0x0F);
2711 emit_int8((unsigned char)0xBE);
2712 emit_operand(dst, src);
2713 }
2714
2715 void Assembler::movsbl(Register dst, Register src) { // movsxb
2716 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2717 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2718 emit_int8(0x0F);
2719 emit_int8((unsigned char)0xBE);
2720 emit_int8((unsigned char)(0xC0 | encode));
2721 }
2722
2723 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2725 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2726 attributes.set_rex_vex_w_reverted();
2727 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2728 emit_int8(0x10);
2729 emit_int8((unsigned char)(0xC0 | encode));
2730 }
2731
2732 void Assembler::movsd(XMMRegister dst, Address src) {
2733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2734 InstructionMark im(this);
2735 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2736 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2737 attributes.set_rex_vex_w_reverted();
2738 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2739 emit_int8(0x10);
2740 emit_operand(dst, src);
2741 }
2742
2743 void Assembler::movsd(Address dst, XMMRegister src) {
2744 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2745 InstructionMark im(this);
2746 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2747 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2748 attributes.set_rex_vex_w_reverted();
2749 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2750 emit_int8(0x11);
2751 emit_operand(src, dst);
2752 }
2753
2754 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2755 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2756 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2758 emit_int8(0x10);
2759 emit_int8((unsigned char)(0xC0 | encode));
2760 }
2761
2762 void Assembler::movss(XMMRegister dst, Address src) {
2763 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2764 InstructionMark im(this);
2765 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2767 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2768 emit_int8(0x10);
2769 emit_operand(dst, src);
2770 }
2771
2772 void Assembler::movss(Address dst, XMMRegister src) {
2773 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2774 InstructionMark im(this);
2775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2776 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2777 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2778 emit_int8(0x11);
2779 emit_operand(src, dst);
2780 }
2781
2782 void Assembler::movswl(Register dst, Address src) { // movsxw
2783 InstructionMark im(this);
2784 prefix(src, dst);
2785 emit_int8(0x0F);
2786 emit_int8((unsigned char)0xBF);
2787 emit_operand(dst, src);
2788 }
2789
2790 void Assembler::movswl(Register dst, Register src) { // movsxw
2791 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2792 emit_int8(0x0F);
2793 emit_int8((unsigned char)0xBF);
2794 emit_int8((unsigned char)(0xC0 | encode));
2795 }
2796
2797 void Assembler::movw(Address dst, int imm16) {
2798 InstructionMark im(this);
2799
2800 emit_int8(0x66); // switch to 16-bit mode
2801 prefix(dst);
2802 emit_int8((unsigned char)0xC7);
2803 emit_operand(rax, dst, 2);
2804 emit_int16(imm16);
2805 }
2806
2807 void Assembler::movw(Register dst, Address src) {
2808 InstructionMark im(this);
2809 emit_int8(0x66);
2810 prefix(src, dst);
2811 emit_int8((unsigned char)0x8B);
2812 emit_operand(dst, src);
2813 }
2814
2815 void Assembler::movw(Address dst, Register src) {
2816 InstructionMark im(this);
2817 emit_int8(0x66);
2818 prefix(dst, src);
2819 emit_int8((unsigned char)0x89);
2820 emit_operand(src, dst);
2821 }
2822
2823 void Assembler::movzbl(Register dst, Address src) { // movzxb
2824 InstructionMark im(this);
2825 prefix(src, dst);
2826 emit_int8(0x0F);
2827 emit_int8((unsigned char)0xB6);
2828 emit_operand(dst, src);
2829 }
2830
2831 void Assembler::movzbl(Register dst, Register src) { // movzxb
2832 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2833 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2834 emit_int8(0x0F);
2835 emit_int8((unsigned char)0xB6);
2836 emit_int8(0xC0 | encode);
2837 }
2838
2839 void Assembler::movzwl(Register dst, Address src) { // movzxw
2840 InstructionMark im(this);
2841 prefix(src, dst);
2842 emit_int8(0x0F);
2843 emit_int8((unsigned char)0xB7);
2844 emit_operand(dst, src);
2845 }
2846
2847 void Assembler::movzwl(Register dst, Register src) { // movzxw
2848 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2849 emit_int8(0x0F);
2850 emit_int8((unsigned char)0xB7);
2851 emit_int8(0xC0 | encode);
2852 }
2853
2854 void Assembler::mull(Address src) {
2855 InstructionMark im(this);
2856 prefix(src);
2857 emit_int8((unsigned char)0xF7);
2858 emit_operand(rsp, src);
2859 }
2860
2861 void Assembler::mull(Register src) {
2862 int encode = prefix_and_encode(src->encoding());
2863 emit_int8((unsigned char)0xF7);
2864 emit_int8((unsigned char)(0xE0 | encode));
2865 }
2866
2867 void Assembler::mulsd(XMMRegister dst, Address src) {
2868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2869 InstructionMark im(this);
2870 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2871 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2872 attributes.set_rex_vex_w_reverted();
2873 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2874 emit_int8(0x59);
2875 emit_operand(dst, src);
2876 }
2877
2878 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2879 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2880 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2881 attributes.set_rex_vex_w_reverted();
2882 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2883 emit_int8(0x59);
2884 emit_int8((unsigned char)(0xC0 | encode));
2885 }
2886
2887 void Assembler::mulss(XMMRegister dst, Address src) {
2888 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2889 InstructionMark im(this);
2890 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2891 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2892 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2893 emit_int8(0x59);
2894 emit_operand(dst, src);
2895 }
2896
2897 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2898 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2899 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2900 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2901 emit_int8(0x59);
2902 emit_int8((unsigned char)(0xC0 | encode));
2903 }
2904
2905 void Assembler::negl(Register dst) {
2906 int encode = prefix_and_encode(dst->encoding());
2907 emit_int8((unsigned char)0xF7);
2908 emit_int8((unsigned char)(0xD8 | encode));
2909 }
2910
2911 void Assembler::nop(int i) {
2912 #ifdef ASSERT
2913 assert(i > 0, " ");
2914 // The fancy nops aren't currently recognized by debuggers making it a
2915 // pain to disassemble code while debugging. If asserts are on clearly
2916 // speed is not an issue so simply use the single byte traditional nop
2917 // to do alignment.
2918
2919 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2920 return;
2921
2922 #endif // ASSERT
2923
2924 if (UseAddressNop && VM_Version::is_intel()) {
2925 //
2926 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2927 // 1: 0x90
2928 // 2: 0x66 0x90
2929 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2930 // 4: 0x0F 0x1F 0x40 0x00
2931 // 5: 0x0F 0x1F 0x44 0x00 0x00
2932 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2933 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2934 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2935 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2936 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2937 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2938
2939 // The rest coding is Intel specific - don't use consecutive address nops
2940
2941 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2942 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2943 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2944 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2945
2946 while(i >= 15) {
2947 // For Intel don't generate consecutive addess nops (mix with regular nops)
2948 i -= 15;
2949 emit_int8(0x66); // size prefix
2950 emit_int8(0x66); // size prefix
2951 emit_int8(0x66); // size prefix
2952 addr_nop_8();
2953 emit_int8(0x66); // size prefix
2954 emit_int8(0x66); // size prefix
2955 emit_int8(0x66); // size prefix
2956 emit_int8((unsigned char)0x90);
2957 // nop
2958 }
2959 switch (i) {
2960 case 14:
2961 emit_int8(0x66); // size prefix
2962 case 13:
2963 emit_int8(0x66); // size prefix
2964 case 12:
2965 addr_nop_8();
2966 emit_int8(0x66); // size prefix
2967 emit_int8(0x66); // size prefix
2968 emit_int8(0x66); // size prefix
2969 emit_int8((unsigned char)0x90);
2970 // nop
2971 break;
2972 case 11:
2973 emit_int8(0x66); // size prefix
2974 case 10:
2975 emit_int8(0x66); // size prefix
2976 case 9:
2977 emit_int8(0x66); // size prefix
2978 case 8:
2979 addr_nop_8();
2980 break;
2981 case 7:
2982 addr_nop_7();
2983 break;
2984 case 6:
2985 emit_int8(0x66); // size prefix
2986 case 5:
2987 addr_nop_5();
2988 break;
2989 case 4:
2990 addr_nop_4();
2991 break;
2992 case 3:
2993 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2994 emit_int8(0x66); // size prefix
2995 case 2:
2996 emit_int8(0x66); // size prefix
2997 case 1:
2998 emit_int8((unsigned char)0x90);
2999 // nop
3000 break;
3001 default:
3002 assert(i == 0, " ");
3003 }
3004 return;
3005 }
3006 if (UseAddressNop && VM_Version::is_amd()) {
3007 //
3008 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3009 // 1: 0x90
3010 // 2: 0x66 0x90
3011 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3012 // 4: 0x0F 0x1F 0x40 0x00
3013 // 5: 0x0F 0x1F 0x44 0x00 0x00
3014 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3015 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3016 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3017 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3018 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3019 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3020
3021 // The rest coding is AMD specific - use consecutive address nops
3022
3023 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3024 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3025 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3026 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3027 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3028 // Size prefixes (0x66) are added for larger sizes
3029
3030 while(i >= 22) {
3031 i -= 11;
3032 emit_int8(0x66); // size prefix
3033 emit_int8(0x66); // size prefix
3034 emit_int8(0x66); // size prefix
3035 addr_nop_8();
3036 }
3037 // Generate first nop for size between 21-12
3038 switch (i) {
3039 case 21:
3040 i -= 1;
3041 emit_int8(0x66); // size prefix
3042 case 20:
3043 case 19:
3044 i -= 1;
3045 emit_int8(0x66); // size prefix
3046 case 18:
3047 case 17:
3048 i -= 1;
3049 emit_int8(0x66); // size prefix
3050 case 16:
3051 case 15:
3052 i -= 8;
3053 addr_nop_8();
3054 break;
3055 case 14:
3056 case 13:
3057 i -= 7;
3058 addr_nop_7();
3059 break;
3060 case 12:
3061 i -= 6;
3062 emit_int8(0x66); // size prefix
3063 addr_nop_5();
3064 break;
3065 default:
3066 assert(i < 12, " ");
3067 }
3068
3069 // Generate second nop for size between 11-1
3070 switch (i) {
3071 case 11:
3072 emit_int8(0x66); // size prefix
3073 case 10:
3074 emit_int8(0x66); // size prefix
3075 case 9:
3076 emit_int8(0x66); // size prefix
3077 case 8:
3078 addr_nop_8();
3079 break;
3080 case 7:
3081 addr_nop_7();
3082 break;
3083 case 6:
3084 emit_int8(0x66); // size prefix
3085 case 5:
3086 addr_nop_5();
3087 break;
3088 case 4:
3089 addr_nop_4();
3090 break;
3091 case 3:
3092 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3093 emit_int8(0x66); // size prefix
3094 case 2:
3095 emit_int8(0x66); // size prefix
3096 case 1:
3097 emit_int8((unsigned char)0x90);
3098 // nop
3099 break;
3100 default:
3101 assert(i == 0, " ");
3102 }
3103 return;
3104 }
3105
3106 // Using nops with size prefixes "0x66 0x90".
3107 // From AMD Optimization Guide:
3108 // 1: 0x90
3109 // 2: 0x66 0x90
3110 // 3: 0x66 0x66 0x90
3111 // 4: 0x66 0x66 0x66 0x90
3112 // 5: 0x66 0x66 0x90 0x66 0x90
3113 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3114 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3115 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3116 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3117 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3118 //
3119 while(i > 12) {
3120 i -= 4;
3121 emit_int8(0x66); // size prefix
3122 emit_int8(0x66);
3123 emit_int8(0x66);
3124 emit_int8((unsigned char)0x90);
3125 // nop
3126 }
3127 // 1 - 12 nops
3128 if(i > 8) {
3129 if(i > 9) {
3130 i -= 1;
3131 emit_int8(0x66);
3132 }
3133 i -= 3;
3134 emit_int8(0x66);
3135 emit_int8(0x66);
3136 emit_int8((unsigned char)0x90);
3137 }
3138 // 1 - 8 nops
3139 if(i > 4) {
3140 if(i > 6) {
3141 i -= 1;
3142 emit_int8(0x66);
3143 }
3144 i -= 3;
3145 emit_int8(0x66);
3146 emit_int8(0x66);
3147 emit_int8((unsigned char)0x90);
3148 }
3149 switch (i) {
3150 case 4:
3151 emit_int8(0x66);
3152 case 3:
3153 emit_int8(0x66);
3154 case 2:
3155 emit_int8(0x66);
3156 case 1:
3157 emit_int8((unsigned char)0x90);
3158 break;
3159 default:
3160 assert(i == 0, " ");
3161 }
3162 }
3163
3164 void Assembler::notl(Register dst) {
3165 int encode = prefix_and_encode(dst->encoding());
3166 emit_int8((unsigned char)0xF7);
3167 emit_int8((unsigned char)(0xD0 | encode));
3168 }
3169
3170 void Assembler::orl(Address dst, int32_t imm32) {
3171 InstructionMark im(this);
3172 prefix(dst);
3173 emit_arith_operand(0x81, rcx, dst, imm32);
3174 }
3175
3176 void Assembler::orl(Register dst, int32_t imm32) {
3177 prefix(dst);
3178 emit_arith(0x81, 0xC8, dst, imm32);
3179 }
3180
3181 void Assembler::orl(Register dst, Address src) {
3182 InstructionMark im(this);
3183 prefix(src, dst);
3184 emit_int8(0x0B);
3185 emit_operand(dst, src);
3186 }
3187
3188 void Assembler::orl(Register dst, Register src) {
3189 (void) prefix_and_encode(dst->encoding(), src->encoding());
3190 emit_arith(0x0B, 0xC0, dst, src);
3191 }
3192
3193 void Assembler::orl(Address dst, Register src) {
3194 InstructionMark im(this);
3195 prefix(dst, src);
3196 emit_int8(0x09);
3197 emit_operand(src, dst);
3198 }
3199
3200 void Assembler::packuswb(XMMRegister dst, Address src) {
3201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3202 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3203 InstructionMark im(this);
3204 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3205 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3206 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3207 emit_int8(0x67);
3208 emit_operand(dst, src);
3209 }
3210
3211 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3212 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3213 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3214 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3215 emit_int8(0x67);
3216 emit_int8((unsigned char)(0xC0 | encode));
3217 }
3218
3219 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3220 assert(UseAVX > 0, "some form of AVX must be enabled");
3221 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3222 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3223 emit_int8(0x67);
3224 emit_int8((unsigned char)(0xC0 | encode));
3225 }
3226
3227 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3228 assert(VM_Version::supports_avx2(), "");
3229 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3230 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3231 emit_int8(0x00);
3232 emit_int8(0xC0 | encode);
3233 emit_int8(imm8);
3234 }
3235
3236 void Assembler::pause() {
3237 emit_int8((unsigned char)0xF3);
3238 emit_int8((unsigned char)0x90);
3239 }
3240
3241 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3242 assert(VM_Version::supports_sse4_2(), "");
3243 InstructionMark im(this);
3244 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3245 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3246 emit_int8(0x61);
3247 emit_operand(dst, src);
3248 emit_int8(imm8);
3249 }
3250
3251 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3252 assert(VM_Version::supports_sse4_2(), "");
3253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3254 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3255 emit_int8(0x61);
3256 emit_int8((unsigned char)(0xC0 | encode));
3257 emit_int8(imm8);
3258 }
3259
3260 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3261 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3262 assert(VM_Version::supports_sse2(), "");
3263 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3264 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3265 emit_int8(0x74);
3266 emit_int8((unsigned char)(0xC0 | encode));
3267 }
3268
3269 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3270 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3271 assert(VM_Version::supports_avx(), "");
3272 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3273 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3274 emit_int8(0x74);
3275 emit_int8((unsigned char)(0xC0 | encode));
3276 }
3277
3278 // In this context, kdst is written the mask used to process the equal components
3279 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3280 assert(VM_Version::supports_avx512bw(), "");
3281 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3282 attributes.set_is_evex_instruction();
3283 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3284 emit_int8(0x74);
3285 emit_int8((unsigned char)(0xC0 | encode));
3286 }
3287
3288 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3289 assert(VM_Version::supports_avx512bw(), "");
3290 InstructionMark im(this);
3291 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3292 attributes.set_is_evex_instruction();
3293 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3294 int dst_enc = kdst->encoding();
3295 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3296 emit_int8(0x74);
3297 emit_operand(as_Register(dst_enc), src);
3298 }
3299
3300 void Assembler::evpcmpeqb(KRegister mask, KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3301 assert(VM_Version::supports_avx512vlbw(), "");
3302 assert(is_vector_masking(), ""); // For stub code use only
3303 InstructionMark im(this);
3304 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3305 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3306 attributes.set_embedded_opmask_register_specifier(mask);
3307 attributes.set_is_evex_instruction();
3308 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3309 emit_int8(0x74);
3310 emit_operand(as_Register(kdst->encoding()), src);
3311 }
3312
3313 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3314 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3315 assert(VM_Version::supports_sse2(), "");
3316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3317 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3318 emit_int8(0x75);
3319 emit_int8((unsigned char)(0xC0 | encode));
3320 }
3321
3322 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3323 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3324 assert(VM_Version::supports_avx(), "");
3325 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3326 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3327 emit_int8(0x75);
3328 emit_int8((unsigned char)(0xC0 | encode));
3329 }
3330
3331 // In this context, kdst is written the mask used to process the equal components
3332 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3333 assert(VM_Version::supports_avx512bw(), "");
3334 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3335 attributes.set_is_evex_instruction();
3336 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3337 emit_int8(0x75);
3338 emit_int8((unsigned char)(0xC0 | encode));
3339 }
3340
3341 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3342 assert(VM_Version::supports_avx512bw(), "");
3343 InstructionMark im(this);
3344 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3345 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3346 attributes.set_is_evex_instruction();
3347 int dst_enc = kdst->encoding();
3348 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3349 emit_int8(0x75);
3350 emit_operand(as_Register(dst_enc), src);
3351 }
3352
3353 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3354 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3355 assert(VM_Version::supports_sse2(), "");
3356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3357 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3358 emit_int8(0x76);
3359 emit_int8((unsigned char)(0xC0 | encode));
3360 }
3361
3362 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3363 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3364 assert(VM_Version::supports_avx(), "");
3365 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3366 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3367 emit_int8(0x76);
3368 emit_int8((unsigned char)(0xC0 | encode));
3369 }
3370
3371 // In this context, kdst is written the mask used to process the equal components
3372 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3373 assert(VM_Version::supports_evex(), "");
3374 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3375 attributes.set_is_evex_instruction();
3376 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3377 emit_int8(0x76);
3378 emit_int8((unsigned char)(0xC0 | encode));
3379 }
3380
3381 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3382 assert(VM_Version::supports_evex(), "");
3383 InstructionMark im(this);
3384 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3385 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3386 attributes.set_is_evex_instruction();
3387 int dst_enc = kdst->encoding();
3388 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3389 emit_int8(0x76);
3390 emit_operand(as_Register(dst_enc), src);
3391 }
3392
3393 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3394 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3395 assert(VM_Version::supports_sse4_1(), "");
3396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3398 emit_int8(0x29);
3399 emit_int8((unsigned char)(0xC0 | encode));
3400 }
3401
3402 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3403 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3404 assert(VM_Version::supports_avx(), "");
3405 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3406 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3407 emit_int8(0x29);
3408 emit_int8((unsigned char)(0xC0 | encode));
3409 }
3410
3411 // In this context, kdst is written the mask used to process the equal components
3412 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3413 assert(VM_Version::supports_evex(), "");
3414 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3415 attributes.set_is_evex_instruction();
3416 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3417 emit_int8(0x29);
3418 emit_int8((unsigned char)(0xC0 | encode));
3419 }
3420
3421 // In this context, kdst is written the mask used to process the equal components
3422 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3423 assert(VM_Version::supports_evex(), "");
3424 InstructionMark im(this);
3425 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3426 attributes.set_is_evex_instruction();
3427 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3428 int dst_enc = kdst->encoding();
3429 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3430 emit_int8(0x29);
3431 emit_operand(as_Register(dst_enc), src);
3432 }
3433
3434 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3435 assert(VM_Version::supports_sse2(), "");
3436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3437 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3438 emit_int8((unsigned char)0xD7);
3439 emit_int8((unsigned char)(0xC0 | encode));
3440 }
3441
3442 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3443 assert(VM_Version::supports_avx2(), "");
3444 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3445 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3446 emit_int8((unsigned char)0xD7);
3447 emit_int8((unsigned char)(0xC0 | encode));
3448 }
3449
3450 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3451 assert(VM_Version::supports_sse4_1(), "");
3452 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3453 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3454 emit_int8(0x16);
3455 emit_int8((unsigned char)(0xC0 | encode));
3456 emit_int8(imm8);
3457 }
3458
3459 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3460 assert(VM_Version::supports_sse4_1(), "");
3461 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3462 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3463 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3464 emit_int8(0x16);
3465 emit_operand(src, dst);
3466 emit_int8(imm8);
3467 }
3468
3469 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3470 assert(VM_Version::supports_sse4_1(), "");
3471 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3472 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3473 emit_int8(0x16);
3474 emit_int8((unsigned char)(0xC0 | encode));
3475 emit_int8(imm8);
3476 }
3477
3478 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3479 assert(VM_Version::supports_sse4_1(), "");
3480 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3481 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3482 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3483 emit_int8(0x16);
3484 emit_operand(src, dst);
3485 emit_int8(imm8);
3486 }
3487
3488 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3489 assert(VM_Version::supports_sse2(), "");
3490 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3491 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3492 emit_int8((unsigned char)0xC5);
3493 emit_int8((unsigned char)(0xC0 | encode));
3494 emit_int8(imm8);
3495 }
3496
3497 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3498 assert(VM_Version::supports_sse4_1(), "");
3499 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3500 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3501 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3502 emit_int8((unsigned char)0x15);
3503 emit_operand(src, dst);
3504 emit_int8(imm8);
3505 }
3506
3507 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3508 assert(VM_Version::supports_sse4_1(), "");
3509 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3510 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3511 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3512 emit_int8(0x14);
3513 emit_operand(src, dst);
3514 emit_int8(imm8);
3515 }
3516
3517 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3518 assert(VM_Version::supports_sse4_1(), "");
3519 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3520 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3521 emit_int8(0x22);
3522 emit_int8((unsigned char)(0xC0 | encode));
3523 emit_int8(imm8);
3524 }
3525
3526 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3527 assert(VM_Version::supports_sse4_1(), "");
3528 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3529 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3530 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3531 emit_int8(0x22);
3532 emit_operand(dst,src);
3533 emit_int8(imm8);
3534 }
3535
3536 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3537 assert(VM_Version::supports_sse4_1(), "");
3538 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3539 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3540 emit_int8(0x22);
3541 emit_int8((unsigned char)(0xC0 | encode));
3542 emit_int8(imm8);
3543 }
3544
3545 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3546 assert(VM_Version::supports_sse4_1(), "");
3547 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3548 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3549 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3550 emit_int8(0x22);
3551 emit_operand(dst, src);
3552 emit_int8(imm8);
3553 }
3554
3555 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3556 assert(VM_Version::supports_sse2(), "");
3557 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3558 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3559 emit_int8((unsigned char)0xC4);
3560 emit_int8((unsigned char)(0xC0 | encode));
3561 emit_int8(imm8);
3562 }
3563
3564 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3565 assert(VM_Version::supports_sse2(), "");
3566 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3567 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3568 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3569 emit_int8((unsigned char)0xC4);
3570 emit_operand(dst, src);
3571 emit_int8(imm8);
3572 }
3573
3574 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3575 assert(VM_Version::supports_sse4_1(), "");
3576 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3577 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3578 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3579 emit_int8(0x20);
3580 emit_operand(dst, src);
3581 emit_int8(imm8);
3582 }
3583
3584 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3585 assert(VM_Version::supports_sse4_1(), "");
3586 InstructionMark im(this);
3587 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3588 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3589 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3590 emit_int8(0x30);
3591 emit_operand(dst, src);
3592 }
3593
3594 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3595 assert(VM_Version::supports_sse4_1(), "");
3596 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3597 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3598 emit_int8(0x30);
3599 emit_int8((unsigned char)(0xC0 | encode));
3600 }
3601
3602 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3603 assert(VM_Version::supports_avx(), "");
3604 InstructionMark im(this);
3605 assert(dst != xnoreg, "sanity");
3606 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3607 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3608 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3609 emit_int8(0x30);
3610 emit_operand(dst, src);
3611 }
3612
3613 // generic
3614 void Assembler::pop(Register dst) {
3615 int encode = prefix_and_encode(dst->encoding());
3616 emit_int8(0x58 | encode);
3617 }
3618
3619 void Assembler::popcntl(Register dst, Address src) {
3620 assert(VM_Version::supports_popcnt(), "must support");
3621 InstructionMark im(this);
3622 emit_int8((unsigned char)0xF3);
3623 prefix(src, dst);
3624 emit_int8(0x0F);
3625 emit_int8((unsigned char)0xB8);
3626 emit_operand(dst, src);
3627 }
3628
3629 void Assembler::popcntl(Register dst, Register src) {
3630 assert(VM_Version::supports_popcnt(), "must support");
3631 emit_int8((unsigned char)0xF3);
3632 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3633 emit_int8(0x0F);
3634 emit_int8((unsigned char)0xB8);
3635 emit_int8((unsigned char)(0xC0 | encode));
3636 }
3637
3638 void Assembler::popf() {
3639 emit_int8((unsigned char)0x9D);
3640 }
3641
3642 #ifndef _LP64 // no 32bit push/pop on amd64
3643 void Assembler::popl(Address dst) {
3644 // NOTE: this will adjust stack by 8byte on 64bits
3645 InstructionMark im(this);
3646 prefix(dst);
3647 emit_int8((unsigned char)0x8F);
3648 emit_operand(rax, dst);
3649 }
3650 #endif
3651
3652 void Assembler::prefetch_prefix(Address src) {
3653 prefix(src);
3654 emit_int8(0x0F);
3655 }
3656
3657 void Assembler::prefetchnta(Address src) {
3658 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3659 InstructionMark im(this);
3660 prefetch_prefix(src);
3661 emit_int8(0x18);
3662 emit_operand(rax, src); // 0, src
3663 }
3664
3665 void Assembler::prefetchr(Address src) {
3666 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3667 InstructionMark im(this);
3668 prefetch_prefix(src);
3669 emit_int8(0x0D);
3670 emit_operand(rax, src); // 0, src
3671 }
3672
3673 void Assembler::prefetcht0(Address src) {
3674 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3675 InstructionMark im(this);
3676 prefetch_prefix(src);
3677 emit_int8(0x18);
3678 emit_operand(rcx, src); // 1, src
3679 }
3680
3681 void Assembler::prefetcht1(Address src) {
3682 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3683 InstructionMark im(this);
3684 prefetch_prefix(src);
3685 emit_int8(0x18);
3686 emit_operand(rdx, src); // 2, src
3687 }
3688
3689 void Assembler::prefetcht2(Address src) {
3690 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3691 InstructionMark im(this);
3692 prefetch_prefix(src);
3693 emit_int8(0x18);
3694 emit_operand(rbx, src); // 3, src
3695 }
3696
3697 void Assembler::prefetchw(Address src) {
3698 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3699 InstructionMark im(this);
3700 prefetch_prefix(src);
3701 emit_int8(0x0D);
3702 emit_operand(rcx, src); // 1, src
3703 }
3704
3705 void Assembler::prefix(Prefix p) {
3706 emit_int8(p);
3707 }
3708
3709 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3710 assert(VM_Version::supports_ssse3(), "");
3711 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3712 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3713 emit_int8(0x00);
3714 emit_int8((unsigned char)(0xC0 | encode));
3715 }
3716
3717 void Assembler::pshufb(XMMRegister dst, Address src) {
3718 assert(VM_Version::supports_ssse3(), "");
3719 InstructionMark im(this);
3720 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3721 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3722 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3723 emit_int8(0x00);
3724 emit_operand(dst, src);
3725 }
3726
3727 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3728 assert(isByte(mode), "invalid value");
3729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3730 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3731 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3732 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3733 emit_int8(0x70);
3734 emit_int8((unsigned char)(0xC0 | encode));
3735 emit_int8(mode & 0xFF);
3736 }
3737
3738 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3739 assert(isByte(mode), "invalid value");
3740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3741 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3742 InstructionMark im(this);
3743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3744 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3745 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3746 emit_int8(0x70);
3747 emit_operand(dst, src);
3748 emit_int8(mode & 0xFF);
3749 }
3750
3751 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3752 assert(isByte(mode), "invalid value");
3753 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3754 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3755 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3756 emit_int8(0x70);
3757 emit_int8((unsigned char)(0xC0 | encode));
3758 emit_int8(mode & 0xFF);
3759 }
3760
3761 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3762 assert(isByte(mode), "invalid value");
3763 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3764 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3765 InstructionMark im(this);
3766 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3767 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3768 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3769 emit_int8(0x70);
3770 emit_operand(dst, src);
3771 emit_int8(mode & 0xFF);
3772 }
3773
3774 void Assembler::psrldq(XMMRegister dst, int shift) {
3775 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3778 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3779 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3780 emit_int8(0x73);
3781 emit_int8((unsigned char)(0xC0 | encode));
3782 emit_int8(shift);
3783 }
3784
3785 void Assembler::pslldq(XMMRegister dst, int shift) {
3786 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3788 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3789 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3790 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3791 emit_int8(0x73);
3792 emit_int8((unsigned char)(0xC0 | encode));
3793 emit_int8(shift);
3794 }
3795
3796 void Assembler::ptest(XMMRegister dst, Address src) {
3797 assert(VM_Version::supports_sse4_1(), "");
3798 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3799 InstructionMark im(this);
3800 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3801 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3802 emit_int8(0x17);
3803 emit_operand(dst, src);
3804 }
3805
3806 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3807 assert(VM_Version::supports_sse4_1(), "");
3808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3809 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3810 emit_int8(0x17);
3811 emit_int8((unsigned char)(0xC0 | encode));
3812 }
3813
3814 void Assembler::vptest(XMMRegister dst, Address src) {
3815 assert(VM_Version::supports_avx(), "");
3816 InstructionMark im(this);
3817 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3818 assert(dst != xnoreg, "sanity");
3819 // swap src<->dst for encoding
3820 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3821 emit_int8(0x17);
3822 emit_operand(dst, src);
3823 }
3824
3825 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3826 assert(VM_Version::supports_avx(), "");
3827 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3828 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3829 emit_int8(0x17);
3830 emit_int8((unsigned char)(0xC0 | encode));
3831 }
3832
3833 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3834 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3835 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3836 InstructionMark im(this);
3837 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3838 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3839 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3840 emit_int8(0x60);
3841 emit_operand(dst, src);
3842 }
3843
3844 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3846 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3847 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3848 emit_int8(0x60);
3849 emit_int8((unsigned char)(0xC0 | encode));
3850 }
3851
3852 void Assembler::punpckldq(XMMRegister dst, Address src) {
3853 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3854 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3855 InstructionMark im(this);
3856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3857 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3858 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3859 emit_int8(0x62);
3860 emit_operand(dst, src);
3861 }
3862
3863 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3864 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3866 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3867 emit_int8(0x62);
3868 emit_int8((unsigned char)(0xC0 | encode));
3869 }
3870
3871 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3872 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3874 attributes.set_rex_vex_w_reverted();
3875 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3876 emit_int8(0x6C);
3877 emit_int8((unsigned char)(0xC0 | encode));
3878 }
3879
3880 void Assembler::push(int32_t imm32) {
3881 // in 64bits we push 64bits onto the stack but only
3882 // take a 32bit immediate
3883 emit_int8(0x68);
3884 emit_int32(imm32);
3885 }
3886
3887 void Assembler::push(Register src) {
3888 int encode = prefix_and_encode(src->encoding());
3889
3890 emit_int8(0x50 | encode);
3891 }
3892
3893 void Assembler::pushf() {
3894 emit_int8((unsigned char)0x9C);
3895 }
3896
3897 #ifndef _LP64 // no 32bit push/pop on amd64
3898 void Assembler::pushl(Address src) {
3899 // Note this will push 64bit on 64bit
3900 InstructionMark im(this);
3901 prefix(src);
3902 emit_int8((unsigned char)0xFF);
3903 emit_operand(rsi, src);
3904 }
3905 #endif
3906
3907 void Assembler::rcll(Register dst, int imm8) {
3908 assert(isShiftCount(imm8), "illegal shift count");
3909 int encode = prefix_and_encode(dst->encoding());
3910 if (imm8 == 1) {
3911 emit_int8((unsigned char)0xD1);
3912 emit_int8((unsigned char)(0xD0 | encode));
3913 } else {
3914 emit_int8((unsigned char)0xC1);
3915 emit_int8((unsigned char)0xD0 | encode);
3916 emit_int8(imm8);
3917 }
3918 }
3919
3920 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3923 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3924 emit_int8(0x53);
3925 emit_int8((unsigned char)(0xC0 | encode));
3926 }
3927
3928 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3929 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3930 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3932 emit_int8(0x53);
3933 emit_int8((unsigned char)(0xC0 | encode));
3934 }
3935
3936 void Assembler::rdtsc() {
3937 emit_int8((unsigned char)0x0F);
3938 emit_int8((unsigned char)0x31);
3939 }
3940
3941 // copies data from [esi] to [edi] using rcx pointer sized words
3942 // generic
3943 void Assembler::rep_mov() {
3944 emit_int8((unsigned char)0xF3);
3945 // MOVSQ
3946 LP64_ONLY(prefix(REX_W));
3947 emit_int8((unsigned char)0xA5);
3948 }
3949
3950 // sets rcx bytes with rax, value at [edi]
3951 void Assembler::rep_stosb() {
3952 emit_int8((unsigned char)0xF3); // REP
3953 LP64_ONLY(prefix(REX_W));
3954 emit_int8((unsigned char)0xAA); // STOSB
3955 }
3956
3957 // sets rcx pointer sized words with rax, value at [edi]
3958 // generic
3959 void Assembler::rep_stos() {
3960 emit_int8((unsigned char)0xF3); // REP
3961 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3962 emit_int8((unsigned char)0xAB);
3963 }
3964
3965 // scans rcx pointer sized words at [edi] for occurance of rax,
3966 // generic
3967 void Assembler::repne_scan() { // repne_scan
3968 emit_int8((unsigned char)0xF2);
3969 // SCASQ
3970 LP64_ONLY(prefix(REX_W));
3971 emit_int8((unsigned char)0xAF);
3972 }
3973
3974 #ifdef _LP64
3975 // scans rcx 4 byte words at [edi] for occurance of rax,
3976 // generic
3977 void Assembler::repne_scanl() { // repne_scan
3978 emit_int8((unsigned char)0xF2);
3979 // SCASL
3980 emit_int8((unsigned char)0xAF);
3981 }
3982 #endif
3983
3984 void Assembler::ret(int imm16) {
3985 if (imm16 == 0) {
3986 emit_int8((unsigned char)0xC3);
3987 } else {
3988 emit_int8((unsigned char)0xC2);
3989 emit_int16(imm16);
3990 }
3991 }
3992
3993 void Assembler::sahf() {
3994 #ifdef _LP64
3995 // Not supported in 64bit mode
3996 ShouldNotReachHere();
3997 #endif
3998 emit_int8((unsigned char)0x9E);
3999 }
4000
4001 void Assembler::sarl(Register dst, int imm8) {
4002 int encode = prefix_and_encode(dst->encoding());
4003 assert(isShiftCount(imm8), "illegal shift count");
4004 if (imm8 == 1) {
4005 emit_int8((unsigned char)0xD1);
4006 emit_int8((unsigned char)(0xF8 | encode));
4007 } else {
4008 emit_int8((unsigned char)0xC1);
4009 emit_int8((unsigned char)(0xF8 | encode));
4010 emit_int8(imm8);
4011 }
4012 }
4013
4014 void Assembler::sarl(Register dst) {
4015 int encode = prefix_and_encode(dst->encoding());
4016 emit_int8((unsigned char)0xD3);
4017 emit_int8((unsigned char)(0xF8 | encode));
4018 }
4019
4020 void Assembler::sbbl(Address dst, int32_t imm32) {
4021 InstructionMark im(this);
4022 prefix(dst);
4023 emit_arith_operand(0x81, rbx, dst, imm32);
4024 }
4025
4026 void Assembler::sbbl(Register dst, int32_t imm32) {
4027 prefix(dst);
4028 emit_arith(0x81, 0xD8, dst, imm32);
4029 }
4030
4031
4032 void Assembler::sbbl(Register dst, Address src) {
4033 InstructionMark im(this);
4034 prefix(src, dst);
4035 emit_int8(0x1B);
4036 emit_operand(dst, src);
4037 }
4038
4039 void Assembler::sbbl(Register dst, Register src) {
4040 (void) prefix_and_encode(dst->encoding(), src->encoding());
4041 emit_arith(0x1B, 0xC0, dst, src);
4042 }
4043
4044 void Assembler::setb(Condition cc, Register dst) {
4045 assert(0 <= cc && cc < 16, "illegal cc");
4046 int encode = prefix_and_encode(dst->encoding(), true);
4047 emit_int8(0x0F);
4048 emit_int8((unsigned char)0x90 | cc);
4049 emit_int8((unsigned char)(0xC0 | encode));
4050 }
4051
4052 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4053 assert(VM_Version::supports_ssse3(), "");
4054 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4056 emit_int8((unsigned char)0x0F);
4057 emit_int8((unsigned char)(0xC0 | encode));
4058 emit_int8(imm8);
4059 }
4060
4061 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4062 assert(VM_Version::supports_sse4_1(), "");
4063 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4064 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4065 emit_int8((unsigned char)0x0E);
4066 emit_int8((unsigned char)(0xC0 | encode));
4067 emit_int8(imm8);
4068 }
4069
4070 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4071 assert(VM_Version::supports_sha(), "");
4072 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4073 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4074 emit_int8((unsigned char)0xCC);
4075 emit_int8((unsigned char)(0xC0 | encode));
4076 emit_int8((unsigned char)imm8);
4077 }
4078
4079 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4080 assert(VM_Version::supports_sha(), "");
4081 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4082 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4083 emit_int8((unsigned char)0xC8);
4084 emit_int8((unsigned char)(0xC0 | encode));
4085 }
4086
4087 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4088 assert(VM_Version::supports_sha(), "");
4089 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4090 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4091 emit_int8((unsigned char)0xC9);
4092 emit_int8((unsigned char)(0xC0 | encode));
4093 }
4094
4095 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4096 assert(VM_Version::supports_sha(), "");
4097 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4098 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4099 emit_int8((unsigned char)0xCA);
4100 emit_int8((unsigned char)(0xC0 | encode));
4101 }
4102
4103 // xmm0 is implicit additional source to this instruction.
4104 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4105 assert(VM_Version::supports_sha(), "");
4106 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4107 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4108 emit_int8((unsigned char)0xCB);
4109 emit_int8((unsigned char)(0xC0 | encode));
4110 }
4111
4112 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4113 assert(VM_Version::supports_sha(), "");
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4115 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4116 emit_int8((unsigned char)0xCC);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4121 assert(VM_Version::supports_sha(), "");
4122 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4123 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4124 emit_int8((unsigned char)0xCD);
4125 emit_int8((unsigned char)(0xC0 | encode));
4126 }
4127
4128
4129 void Assembler::shll(Register dst, int imm8) {
4130 assert(isShiftCount(imm8), "illegal shift count");
4131 int encode = prefix_and_encode(dst->encoding());
4132 if (imm8 == 1 ) {
4133 emit_int8((unsigned char)0xD1);
4134 emit_int8((unsigned char)(0xE0 | encode));
4135 } else {
4136 emit_int8((unsigned char)0xC1);
4137 emit_int8((unsigned char)(0xE0 | encode));
4138 emit_int8(imm8);
4139 }
4140 }
4141
4142 void Assembler::shll(Register dst) {
4143 int encode = prefix_and_encode(dst->encoding());
4144 emit_int8((unsigned char)0xD3);
4145 emit_int8((unsigned char)(0xE0 | encode));
4146 }
4147
4148 void Assembler::shrl(Register dst, int imm8) {
4149 assert(isShiftCount(imm8), "illegal shift count");
4150 int encode = prefix_and_encode(dst->encoding());
4151 emit_int8((unsigned char)0xC1);
4152 emit_int8((unsigned char)(0xE8 | encode));
4153 emit_int8(imm8);
4154 }
4155
4156 void Assembler::shrl(Register dst) {
4157 int encode = prefix_and_encode(dst->encoding());
4158 emit_int8((unsigned char)0xD3);
4159 emit_int8((unsigned char)(0xE8 | encode));
4160 }
4161
4162 // copies a single word from [esi] to [edi]
4163 void Assembler::smovl() {
4164 emit_int8((unsigned char)0xA5);
4165 }
4166
4167 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4168 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4169 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4170 attributes.set_rex_vex_w_reverted();
4171 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4172 emit_int8(0x51);
4173 emit_int8((unsigned char)(0xC0 | encode));
4174 }
4175
4176 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4178 InstructionMark im(this);
4179 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4180 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4181 attributes.set_rex_vex_w_reverted();
4182 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4183 emit_int8(0x51);
4184 emit_operand(dst, src);
4185 }
4186
4187 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4188 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4189 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4190 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4191 emit_int8(0x51);
4192 emit_int8((unsigned char)(0xC0 | encode));
4193 }
4194
4195 void Assembler::std() {
4196 emit_int8((unsigned char)0xFD);
4197 }
4198
4199 void Assembler::sqrtss(XMMRegister dst, Address src) {
4200 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4201 InstructionMark im(this);
4202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4203 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4204 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4205 emit_int8(0x51);
4206 emit_operand(dst, src);
4207 }
4208
4209 void Assembler::stmxcsr( Address dst) {
4210 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4211 InstructionMark im(this);
4212 prefix(dst);
4213 emit_int8(0x0F);
4214 emit_int8((unsigned char)0xAE);
4215 emit_operand(as_Register(3), dst);
4216 }
4217
4218 void Assembler::subl(Address dst, int32_t imm32) {
4219 InstructionMark im(this);
4220 prefix(dst);
4221 emit_arith_operand(0x81, rbp, dst, imm32);
4222 }
4223
4224 void Assembler::subl(Address dst, Register src) {
4225 InstructionMark im(this);
4226 prefix(dst, src);
4227 emit_int8(0x29);
4228 emit_operand(src, dst);
4229 }
4230
4231 void Assembler::subl(Register dst, int32_t imm32) {
4232 prefix(dst);
4233 emit_arith(0x81, 0xE8, dst, imm32);
4234 }
4235
4236 // Force generation of a 4 byte immediate value even if it fits into 8bit
4237 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4238 prefix(dst);
4239 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4240 }
4241
4242 void Assembler::subl(Register dst, Address src) {
4243 InstructionMark im(this);
4244 prefix(src, dst);
4245 emit_int8(0x2B);
4246 emit_operand(dst, src);
4247 }
4248
4249 void Assembler::subl(Register dst, Register src) {
4250 (void) prefix_and_encode(dst->encoding(), src->encoding());
4251 emit_arith(0x2B, 0xC0, dst, src);
4252 }
4253
4254 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4255 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4256 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4257 attributes.set_rex_vex_w_reverted();
4258 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4259 emit_int8(0x5C);
4260 emit_int8((unsigned char)(0xC0 | encode));
4261 }
4262
4263 void Assembler::subsd(XMMRegister dst, Address src) {
4264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4265 InstructionMark im(this);
4266 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4268 attributes.set_rex_vex_w_reverted();
4269 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4270 emit_int8(0x5C);
4271 emit_operand(dst, src);
4272 }
4273
4274 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4275 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4278 emit_int8(0x5C);
4279 emit_int8((unsigned char)(0xC0 | encode));
4280 }
4281
4282 void Assembler::subss(XMMRegister dst, Address src) {
4283 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4284 InstructionMark im(this);
4285 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4287 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4288 emit_int8(0x5C);
4289 emit_operand(dst, src);
4290 }
4291
4292 void Assembler::testb(Register dst, int imm8) {
4293 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4294 (void) prefix_and_encode(dst->encoding(), true);
4295 emit_arith_b(0xF6, 0xC0, dst, imm8);
4296 }
4297
4298 void Assembler::testb(Address dst, int imm8) {
4299 InstructionMark im(this);
4300 prefix(dst);
4301 emit_int8((unsigned char)0xF6);
4302 emit_operand(rax, dst, 1);
4303 emit_int8(imm8);
4304 }
4305
4306 void Assembler::testl(Register dst, int32_t imm32) {
4307 // not using emit_arith because test
4308 // doesn't support sign-extension of
4309 // 8bit operands
4310 int encode = dst->encoding();
4311 if (encode == 0) {
4312 emit_int8((unsigned char)0xA9);
4313 } else {
4314 encode = prefix_and_encode(encode);
4315 emit_int8((unsigned char)0xF7);
4316 emit_int8((unsigned char)(0xC0 | encode));
4317 }
4318 emit_int32(imm32);
4319 }
4320
4321 void Assembler::testl(Register dst, Register src) {
4322 (void) prefix_and_encode(dst->encoding(), src->encoding());
4323 emit_arith(0x85, 0xC0, dst, src);
4324 }
4325
4326 void Assembler::testl(Register dst, Address src) {
4327 InstructionMark im(this);
4328 prefix(src, dst);
4329 emit_int8((unsigned char)0x85);
4330 emit_operand(dst, src);
4331 }
4332
4333 void Assembler::tzcntl(Register dst, Register src) {
4334 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4335 emit_int8((unsigned char)0xF3);
4336 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4337 emit_int8(0x0F);
4338 emit_int8((unsigned char)0xBC);
4339 emit_int8((unsigned char)0xC0 | encode);
4340 }
4341
4342 void Assembler::tzcntq(Register dst, Register src) {
4343 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4344 emit_int8((unsigned char)0xF3);
4345 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4346 emit_int8(0x0F);
4347 emit_int8((unsigned char)0xBC);
4348 emit_int8((unsigned char)(0xC0 | encode));
4349 }
4350
4351 void Assembler::ucomisd(XMMRegister dst, Address src) {
4352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4353 InstructionMark im(this);
4354 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4355 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4356 attributes.set_rex_vex_w_reverted();
4357 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4358 emit_int8(0x2E);
4359 emit_operand(dst, src);
4360 }
4361
4362 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4363 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4364 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4365 attributes.set_rex_vex_w_reverted();
4366 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4367 emit_int8(0x2E);
4368 emit_int8((unsigned char)(0xC0 | encode));
4369 }
4370
4371 void Assembler::ucomiss(XMMRegister dst, Address src) {
4372 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4373 InstructionMark im(this);
4374 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4375 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4376 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4377 emit_int8(0x2E);
4378 emit_operand(dst, src);
4379 }
4380
4381 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4382 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4383 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4384 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4385 emit_int8(0x2E);
4386 emit_int8((unsigned char)(0xC0 | encode));
4387 }
4388
4389 void Assembler::xabort(int8_t imm8) {
4390 emit_int8((unsigned char)0xC6);
4391 emit_int8((unsigned char)0xF8);
4392 emit_int8((unsigned char)(imm8 & 0xFF));
4393 }
4394
4395 void Assembler::xaddl(Address dst, Register src) {
4396 InstructionMark im(this);
4397 prefix(dst, src);
4398 emit_int8(0x0F);
4399 emit_int8((unsigned char)0xC1);
4400 emit_operand(src, dst);
4401 }
4402
4403 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4404 InstructionMark im(this);
4405 relocate(rtype);
4406 if (abort.is_bound()) {
4407 address entry = target(abort);
4408 assert(entry != NULL, "abort entry NULL");
4409 intptr_t offset = entry - pc();
4410 emit_int8((unsigned char)0xC7);
4411 emit_int8((unsigned char)0xF8);
4412 emit_int32(offset - 6); // 2 opcode + 4 address
4413 } else {
4414 abort.add_patch_at(code(), locator());
4415 emit_int8((unsigned char)0xC7);
4416 emit_int8((unsigned char)0xF8);
4417 emit_int32(0);
4418 }
4419 }
4420
4421 void Assembler::xchgl(Register dst, Address src) { // xchg
4422 InstructionMark im(this);
4423 prefix(src, dst);
4424 emit_int8((unsigned char)0x87);
4425 emit_operand(dst, src);
4426 }
4427
4428 void Assembler::xchgl(Register dst, Register src) {
4429 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4430 emit_int8((unsigned char)0x87);
4431 emit_int8((unsigned char)(0xC0 | encode));
4432 }
4433
4434 void Assembler::xend() {
4435 emit_int8((unsigned char)0x0F);
4436 emit_int8((unsigned char)0x01);
4437 emit_int8((unsigned char)0xD5);
4438 }
4439
4440 void Assembler::xgetbv() {
4441 emit_int8(0x0F);
4442 emit_int8(0x01);
4443 emit_int8((unsigned char)0xD0);
4444 }
4445
4446 void Assembler::xorl(Register dst, int32_t imm32) {
4447 prefix(dst);
4448 emit_arith(0x81, 0xF0, dst, imm32);
4449 }
4450
4451 void Assembler::xorl(Register dst, Address src) {
4452 InstructionMark im(this);
4453 prefix(src, dst);
4454 emit_int8(0x33);
4455 emit_operand(dst, src);
4456 }
4457
4458 void Assembler::xorl(Register dst, Register src) {
4459 (void) prefix_and_encode(dst->encoding(), src->encoding());
4460 emit_arith(0x33, 0xC0, dst, src);
4461 }
4462
4463 void Assembler::xorb(Register dst, Address src) {
4464 InstructionMark im(this);
4465 prefix(src, dst);
4466 emit_int8(0x32);
4467 emit_operand(dst, src);
4468 }
4469
4470 // AVX 3-operands scalar float-point arithmetic instructions
4471
4472 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4473 assert(VM_Version::supports_avx(), "");
4474 InstructionMark im(this);
4475 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4476 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4477 attributes.set_rex_vex_w_reverted();
4478 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4479 emit_int8(0x58);
4480 emit_operand(dst, src);
4481 }
4482
4483 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4484 assert(VM_Version::supports_avx(), "");
4485 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4486 attributes.set_rex_vex_w_reverted();
4487 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4488 emit_int8(0x58);
4489 emit_int8((unsigned char)(0xC0 | encode));
4490 }
4491
4492 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4493 assert(VM_Version::supports_avx(), "");
4494 InstructionMark im(this);
4495 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4496 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4497 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4498 emit_int8(0x58);
4499 emit_operand(dst, src);
4500 }
4501
4502 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4503 assert(VM_Version::supports_avx(), "");
4504 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4505 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4506 emit_int8(0x58);
4507 emit_int8((unsigned char)(0xC0 | encode));
4508 }
4509
4510 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4511 assert(VM_Version::supports_avx(), "");
4512 InstructionMark im(this);
4513 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4514 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4515 attributes.set_rex_vex_w_reverted();
4516 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4517 emit_int8(0x5E);
4518 emit_operand(dst, src);
4519 }
4520
4521 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4522 assert(VM_Version::supports_avx(), "");
4523 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4524 attributes.set_rex_vex_w_reverted();
4525 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4526 emit_int8(0x5E);
4527 emit_int8((unsigned char)(0xC0 | encode));
4528 }
4529
4530 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4531 assert(VM_Version::supports_avx(), "");
4532 InstructionMark im(this);
4533 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4534 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4535 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4536 emit_int8(0x5E);
4537 emit_operand(dst, src);
4538 }
4539
4540 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4541 assert(VM_Version::supports_avx(), "");
4542 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4543 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4544 emit_int8(0x5E);
4545 emit_int8((unsigned char)(0xC0 | encode));
4546 }
4547
4548 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4549 assert(VM_Version::supports_avx(), "");
4550 InstructionMark im(this);
4551 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4552 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4553 attributes.set_rex_vex_w_reverted();
4554 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4555 emit_int8(0x59);
4556 emit_operand(dst, src);
4557 }
4558
4559 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4560 assert(VM_Version::supports_avx(), "");
4561 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4562 attributes.set_rex_vex_w_reverted();
4563 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4564 emit_int8(0x59);
4565 emit_int8((unsigned char)(0xC0 | encode));
4566 }
4567
4568 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4569 assert(VM_Version::supports_avx(), "");
4570 InstructionMark im(this);
4571 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4572 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4573 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4574 emit_int8(0x59);
4575 emit_operand(dst, src);
4576 }
4577
4578 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4579 assert(VM_Version::supports_avx(), "");
4580 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4581 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4582 emit_int8(0x59);
4583 emit_int8((unsigned char)(0xC0 | encode));
4584 }
4585
4586 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4587 assert(VM_Version::supports_avx(), "");
4588 InstructionMark im(this);
4589 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4590 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4591 attributes.set_rex_vex_w_reverted();
4592 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4593 emit_int8(0x5C);
4594 emit_operand(dst, src);
4595 }
4596
4597 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4598 assert(VM_Version::supports_avx(), "");
4599 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4600 attributes.set_rex_vex_w_reverted();
4601 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4602 emit_int8(0x5C);
4603 emit_int8((unsigned char)(0xC0 | encode));
4604 }
4605
4606 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4607 assert(VM_Version::supports_avx(), "");
4608 InstructionMark im(this);
4609 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4610 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4611 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4612 emit_int8(0x5C);
4613 emit_operand(dst, src);
4614 }
4615
4616 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4617 assert(VM_Version::supports_avx(), "");
4618 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4619 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4620 emit_int8(0x5C);
4621 emit_int8((unsigned char)(0xC0 | encode));
4622 }
4623
4624 //====================VECTOR ARITHMETIC=====================================
4625
4626 // Float-point vector arithmetic
4627
4628 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4629 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4630 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4631 attributes.set_rex_vex_w_reverted();
4632 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4633 emit_int8(0x58);
4634 emit_int8((unsigned char)(0xC0 | encode));
4635 }
4636
4637 void Assembler::addpd(XMMRegister dst, Address src) {
4638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4639 InstructionMark im(this);
4640 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4641 attributes.set_rex_vex_w_reverted();
4642 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4643 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4644 emit_int8(0x58);
4645 emit_operand(dst, src);
4646 }
4647
4648
4649 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4651 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4652 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4653 emit_int8(0x58);
4654 emit_int8((unsigned char)(0xC0 | encode));
4655 }
4656
4657 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4658 assert(VM_Version::supports_avx(), "");
4659 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4660 attributes.set_rex_vex_w_reverted();
4661 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4662 emit_int8(0x58);
4663 emit_int8((unsigned char)(0xC0 | encode));
4664 }
4665
4666 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4667 assert(VM_Version::supports_avx(), "");
4668 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4669 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4670 emit_int8(0x58);
4671 emit_int8((unsigned char)(0xC0 | encode));
4672 }
4673
4674 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4675 assert(VM_Version::supports_avx(), "");
4676 InstructionMark im(this);
4677 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4678 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4679 attributes.set_rex_vex_w_reverted();
4680 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4681 emit_int8(0x58);
4682 emit_operand(dst, src);
4683 }
4684
4685 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4686 assert(VM_Version::supports_avx(), "");
4687 InstructionMark im(this);
4688 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4689 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4690 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4691 emit_int8(0x58);
4692 emit_operand(dst, src);
4693 }
4694
4695 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4697 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4698 attributes.set_rex_vex_w_reverted();
4699 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4700 emit_int8(0x5C);
4701 emit_int8((unsigned char)(0xC0 | encode));
4702 }
4703
4704 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4705 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4706 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4707 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4708 emit_int8(0x5C);
4709 emit_int8((unsigned char)(0xC0 | encode));
4710 }
4711
4712 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4713 assert(VM_Version::supports_avx(), "");
4714 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4715 attributes.set_rex_vex_w_reverted();
4716 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4717 emit_int8(0x5C);
4718 emit_int8((unsigned char)(0xC0 | encode));
4719 }
4720
4721 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4722 assert(VM_Version::supports_avx(), "");
4723 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4724 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4725 emit_int8(0x5C);
4726 emit_int8((unsigned char)(0xC0 | encode));
4727 }
4728
4729 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4730 assert(VM_Version::supports_avx(), "");
4731 InstructionMark im(this);
4732 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4733 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4734 attributes.set_rex_vex_w_reverted();
4735 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4736 emit_int8(0x5C);
4737 emit_operand(dst, src);
4738 }
4739
4740 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4741 assert(VM_Version::supports_avx(), "");
4742 InstructionMark im(this);
4743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4744 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4745 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4746 emit_int8(0x5C);
4747 emit_operand(dst, src);
4748 }
4749
4750 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4752 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4753 attributes.set_rex_vex_w_reverted();
4754 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4755 emit_int8(0x59);
4756 emit_int8((unsigned char)(0xC0 | encode));
4757 }
4758
4759 void Assembler::mulpd(XMMRegister dst, Address src) {
4760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4761 InstructionMark im(this);
4762 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4763 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4764 attributes.set_rex_vex_w_reverted();
4765 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4766 emit_int8(0x59);
4767 emit_operand(dst, src);
4768 }
4769
4770 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4772 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4773 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4774 emit_int8(0x59);
4775 emit_int8((unsigned char)(0xC0 | encode));
4776 }
4777
4778 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4779 assert(VM_Version::supports_avx(), "");
4780 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4781 attributes.set_rex_vex_w_reverted();
4782 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4783 emit_int8(0x59);
4784 emit_int8((unsigned char)(0xC0 | encode));
4785 }
4786
4787 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4788 assert(VM_Version::supports_avx(), "");
4789 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4790 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4791 emit_int8(0x59);
4792 emit_int8((unsigned char)(0xC0 | encode));
4793 }
4794
4795 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4796 assert(VM_Version::supports_avx(), "");
4797 InstructionMark im(this);
4798 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4799 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4800 attributes.set_rex_vex_w_reverted();
4801 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4802 emit_int8(0x59);
4803 emit_operand(dst, src);
4804 }
4805
4806 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4807 assert(VM_Version::supports_avx(), "");
4808 InstructionMark im(this);
4809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4810 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4811 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4812 emit_int8(0x59);
4813 emit_operand(dst, src);
4814 }
4815
4816 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4818 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4819 attributes.set_rex_vex_w_reverted();
4820 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4821 emit_int8(0x5E);
4822 emit_int8((unsigned char)(0xC0 | encode));
4823 }
4824
4825 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4826 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4828 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4829 emit_int8(0x5E);
4830 emit_int8((unsigned char)(0xC0 | encode));
4831 }
4832
4833 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4834 assert(VM_Version::supports_avx(), "");
4835 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4836 attributes.set_rex_vex_w_reverted();
4837 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4838 emit_int8(0x5E);
4839 emit_int8((unsigned char)(0xC0 | encode));
4840 }
4841
4842 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4843 assert(VM_Version::supports_avx(), "");
4844 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4845 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4846 emit_int8(0x5E);
4847 emit_int8((unsigned char)(0xC0 | encode));
4848 }
4849
4850 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4851 assert(VM_Version::supports_avx(), "");
4852 InstructionMark im(this);
4853 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4854 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4855 attributes.set_rex_vex_w_reverted();
4856 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4857 emit_int8(0x5E);
4858 emit_operand(dst, src);
4859 }
4860
4861 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4862 assert(VM_Version::supports_avx(), "");
4863 InstructionMark im(this);
4864 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4865 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4866 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4867 emit_int8(0x5E);
4868 emit_operand(dst, src);
4869 }
4870
4871 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4872 assert(VM_Version::supports_avx(), "");
4873 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4874 attributes.set_rex_vex_w_reverted();
4875 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4876 emit_int8(0x51);
4877 emit_int8((unsigned char)(0xC0 | encode));
4878 }
4879
4880 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4881 assert(VM_Version::supports_avx(), "");
4882 InstructionMark im(this);
4883 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4884 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4885 attributes.set_rex_vex_w_reverted();
4886 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4887 emit_int8(0x51);
4888 emit_operand(dst, src);
4889 }
4890
4891 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4892 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4893 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4894 attributes.set_rex_vex_w_reverted();
4895 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4896 emit_int8(0x54);
4897 emit_int8((unsigned char)(0xC0 | encode));
4898 }
4899
4900 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4904 emit_int8(0x54);
4905 emit_int8((unsigned char)(0xC0 | encode));
4906 }
4907
4908 void Assembler::andps(XMMRegister dst, Address src) {
4909 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4910 InstructionMark im(this);
4911 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4912 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4913 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4914 emit_int8(0x54);
4915 emit_operand(dst, src);
4916 }
4917
4918 void Assembler::andpd(XMMRegister dst, Address src) {
4919 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4920 InstructionMark im(this);
4921 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4922 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4923 attributes.set_rex_vex_w_reverted();
4924 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4925 emit_int8(0x54);
4926 emit_operand(dst, src);
4927 }
4928
4929 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4930 assert(VM_Version::supports_avx(), "");
4931 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4932 attributes.set_rex_vex_w_reverted();
4933 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4934 emit_int8(0x54);
4935 emit_int8((unsigned char)(0xC0 | encode));
4936 }
4937
4938 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4939 assert(VM_Version::supports_avx(), "");
4940 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4941 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4942 emit_int8(0x54);
4943 emit_int8((unsigned char)(0xC0 | encode));
4944 }
4945
4946 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4947 assert(VM_Version::supports_avx(), "");
4948 InstructionMark im(this);
4949 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4950 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4951 attributes.set_rex_vex_w_reverted();
4952 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4953 emit_int8(0x54);
4954 emit_operand(dst, src);
4955 }
4956
4957 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4958 assert(VM_Version::supports_avx(), "");
4959 InstructionMark im(this);
4960 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4961 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4962 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4963 emit_int8(0x54);
4964 emit_operand(dst, src);
4965 }
4966
4967 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4968 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4969 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4970 attributes.set_rex_vex_w_reverted();
4971 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4972 emit_int8(0x15);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 }
4975
4976 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4977 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4978 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4979 attributes.set_rex_vex_w_reverted();
4980 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4981 emit_int8(0x14);
4982 emit_int8((unsigned char)(0xC0 | encode));
4983 }
4984
4985 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4986 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4987 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4988 attributes.set_rex_vex_w_reverted();
4989 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4990 emit_int8(0x57);
4991 emit_int8((unsigned char)(0xC0 | encode));
4992 }
4993
4994 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4995 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4996 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4997 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4998 emit_int8(0x57);
4999 emit_int8((unsigned char)(0xC0 | encode));
5000 }
5001
5002 void Assembler::xorpd(XMMRegister dst, Address src) {
5003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5004 InstructionMark im(this);
5005 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5006 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5007 attributes.set_rex_vex_w_reverted();
5008 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5009 emit_int8(0x57);
5010 emit_operand(dst, src);
5011 }
5012
5013 void Assembler::xorps(XMMRegister dst, Address src) {
5014 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5015 InstructionMark im(this);
5016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5017 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5018 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5019 emit_int8(0x57);
5020 emit_operand(dst, src);
5021 }
5022
5023 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5024 assert(VM_Version::supports_avx(), "");
5025 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5026 attributes.set_rex_vex_w_reverted();
5027 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5028 emit_int8(0x57);
5029 emit_int8((unsigned char)(0xC0 | encode));
5030 }
5031
5032 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5033 assert(VM_Version::supports_avx(), "");
5034 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5035 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5036 emit_int8(0x57);
5037 emit_int8((unsigned char)(0xC0 | encode));
5038 }
5039
5040 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5041 assert(VM_Version::supports_avx(), "");
5042 InstructionMark im(this);
5043 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5044 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5045 attributes.set_rex_vex_w_reverted();
5046 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5047 emit_int8(0x57);
5048 emit_operand(dst, src);
5049 }
5050
5051 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5052 assert(VM_Version::supports_avx(), "");
5053 InstructionMark im(this);
5054 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5055 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5056 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5057 emit_int8(0x57);
5058 emit_operand(dst, src);
5059 }
5060
5061 // Integer vector arithmetic
5062 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5063 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5064 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5065 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5066 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5067 emit_int8(0x01);
5068 emit_int8((unsigned char)(0xC0 | encode));
5069 }
5070
5071 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5072 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5073 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5074 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5075 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5076 emit_int8(0x02);
5077 emit_int8((unsigned char)(0xC0 | encode));
5078 }
5079
5080 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5081 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5082 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5083 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5084 emit_int8((unsigned char)0xFC);
5085 emit_int8((unsigned char)(0xC0 | encode));
5086 }
5087
5088 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5089 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5090 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5091 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5092 emit_int8((unsigned char)0xFD);
5093 emit_int8((unsigned char)(0xC0 | encode));
5094 }
5095
5096 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5098 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5099 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8((unsigned char)0xFE);
5101 emit_int8((unsigned char)(0xC0 | encode));
5102 }
5103
5104 void Assembler::paddd(XMMRegister dst, Address src) {
5105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5106 InstructionMark im(this);
5107 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5108 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5109 emit_int8((unsigned char)0xFE);
5110 emit_operand(dst, src);
5111 }
5112
5113 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5115 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5116 attributes.set_rex_vex_w_reverted();
5117 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5118 emit_int8((unsigned char)0xD4);
5119 emit_int8((unsigned char)(0xC0 | encode));
5120 }
5121
5122 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5123 assert(VM_Version::supports_sse3(), "");
5124 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5125 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5126 emit_int8(0x01);
5127 emit_int8((unsigned char)(0xC0 | encode));
5128 }
5129
5130 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5131 assert(VM_Version::supports_sse3(), "");
5132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5133 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5134 emit_int8(0x02);
5135 emit_int8((unsigned char)(0xC0 | encode));
5136 }
5137
5138 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5139 assert(UseAVX > 0, "requires some form of AVX");
5140 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5141 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5142 emit_int8((unsigned char)0xFC);
5143 emit_int8((unsigned char)(0xC0 | encode));
5144 }
5145
5146 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5147 assert(UseAVX > 0, "requires some form of AVX");
5148 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5149 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5150 emit_int8((unsigned char)0xFD);
5151 emit_int8((unsigned char)(0xC0 | encode));
5152 }
5153
5154 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5155 assert(UseAVX > 0, "requires some form of AVX");
5156 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5157 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5158 emit_int8((unsigned char)0xFE);
5159 emit_int8((unsigned char)(0xC0 | encode));
5160 }
5161
5162 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5163 assert(UseAVX > 0, "requires some form of AVX");
5164 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5165 attributes.set_rex_vex_w_reverted();
5166 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5167 emit_int8((unsigned char)0xD4);
5168 emit_int8((unsigned char)(0xC0 | encode));
5169 }
5170
5171 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5172 assert(UseAVX > 0, "requires some form of AVX");
5173 InstructionMark im(this);
5174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5175 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5176 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5177 emit_int8((unsigned char)0xFC);
5178 emit_operand(dst, src);
5179 }
5180
5181 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5182 assert(UseAVX > 0, "requires some form of AVX");
5183 InstructionMark im(this);
5184 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5185 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5186 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5187 emit_int8((unsigned char)0xFD);
5188 emit_operand(dst, src);
5189 }
5190
5191 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5192 assert(UseAVX > 0, "requires some form of AVX");
5193 InstructionMark im(this);
5194 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5195 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5196 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5197 emit_int8((unsigned char)0xFE);
5198 emit_operand(dst, src);
5199 }
5200
5201 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5202 assert(UseAVX > 0, "requires some form of AVX");
5203 InstructionMark im(this);
5204 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5205 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5206 attributes.set_rex_vex_w_reverted();
5207 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5208 emit_int8((unsigned char)0xD4);
5209 emit_operand(dst, src);
5210 }
5211
5212 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5213 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5214 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5215 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5216 emit_int8((unsigned char)0xF8);
5217 emit_int8((unsigned char)(0xC0 | encode));
5218 }
5219
5220 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5222 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5223 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5224 emit_int8((unsigned char)0xF9);
5225 emit_int8((unsigned char)(0xC0 | encode));
5226 }
5227
5228 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5229 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5230 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5231 emit_int8((unsigned char)0xFA);
5232 emit_int8((unsigned char)(0xC0 | encode));
5233 }
5234
5235 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5236 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5237 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5238 attributes.set_rex_vex_w_reverted();
5239 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5240 emit_int8((unsigned char)0xFB);
5241 emit_int8((unsigned char)(0xC0 | encode));
5242 }
5243
5244 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5245 assert(UseAVX > 0, "requires some form of AVX");
5246 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5247 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5248 emit_int8((unsigned char)0xF8);
5249 emit_int8((unsigned char)(0xC0 | encode));
5250 }
5251
5252 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5253 assert(UseAVX > 0, "requires some form of AVX");
5254 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5255 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5256 emit_int8((unsigned char)0xF9);
5257 emit_int8((unsigned char)(0xC0 | encode));
5258 }
5259
5260 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5261 assert(UseAVX > 0, "requires some form of AVX");
5262 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5263 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5264 emit_int8((unsigned char)0xFA);
5265 emit_int8((unsigned char)(0xC0 | encode));
5266 }
5267
5268 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5269 assert(UseAVX > 0, "requires some form of AVX");
5270 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5271 attributes.set_rex_vex_w_reverted();
5272 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5273 emit_int8((unsigned char)0xFB);
5274 emit_int8((unsigned char)(0xC0 | encode));
5275 }
5276
5277 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5278 assert(UseAVX > 0, "requires some form of AVX");
5279 InstructionMark im(this);
5280 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5281 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5282 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5283 emit_int8((unsigned char)0xF8);
5284 emit_operand(dst, src);
5285 }
5286
5287 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5288 assert(UseAVX > 0, "requires some form of AVX");
5289 InstructionMark im(this);
5290 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5291 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5292 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5293 emit_int8((unsigned char)0xF9);
5294 emit_operand(dst, src);
5295 }
5296
5297 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5298 assert(UseAVX > 0, "requires some form of AVX");
5299 InstructionMark im(this);
5300 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5301 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5302 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5303 emit_int8((unsigned char)0xFA);
5304 emit_operand(dst, src);
5305 }
5306
5307 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5308 assert(UseAVX > 0, "requires some form of AVX");
5309 InstructionMark im(this);
5310 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5311 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5312 attributes.set_rex_vex_w_reverted();
5313 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5314 emit_int8((unsigned char)0xFB);
5315 emit_operand(dst, src);
5316 }
5317
5318 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5320 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5321 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5322 emit_int8((unsigned char)0xD5);
5323 emit_int8((unsigned char)(0xC0 | encode));
5324 }
5325
5326 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5327 assert(VM_Version::supports_sse4_1(), "");
5328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5329 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5330 emit_int8(0x40);
5331 emit_int8((unsigned char)(0xC0 | encode));
5332 }
5333
5334 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5335 assert(UseAVX > 0, "requires some form of AVX");
5336 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5337 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5338 emit_int8((unsigned char)0xD5);
5339 emit_int8((unsigned char)(0xC0 | encode));
5340 }
5341
5342 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5343 assert(UseAVX > 0, "requires some form of AVX");
5344 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5345 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5346 emit_int8(0x40);
5347 emit_int8((unsigned char)(0xC0 | encode));
5348 }
5349
5350 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5351 assert(UseAVX > 2, "requires some form of EVEX");
5352 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5353 attributes.set_is_evex_instruction();
5354 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5355 emit_int8(0x40);
5356 emit_int8((unsigned char)(0xC0 | encode));
5357 }
5358
5359 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5360 assert(UseAVX > 0, "requires some form of AVX");
5361 InstructionMark im(this);
5362 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5363 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5364 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5365 emit_int8((unsigned char)0xD5);
5366 emit_operand(dst, src);
5367 }
5368
5369 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5370 assert(UseAVX > 0, "requires some form of AVX");
5371 InstructionMark im(this);
5372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5373 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5374 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5375 emit_int8(0x40);
5376 emit_operand(dst, src);
5377 }
5378
5379 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5380 assert(UseAVX > 2, "requires some form of EVEX");
5381 InstructionMark im(this);
5382 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5383 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5384 attributes.set_is_evex_instruction();
5385 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5386 emit_int8(0x40);
5387 emit_operand(dst, src);
5388 }
5389
5390 // Shift packed integers left by specified number of bits.
5391 void Assembler::psllw(XMMRegister dst, int shift) {
5392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5394 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5395 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5396 emit_int8(0x71);
5397 emit_int8((unsigned char)(0xC0 | encode));
5398 emit_int8(shift & 0xFF);
5399 }
5400
5401 void Assembler::pslld(XMMRegister dst, int shift) {
5402 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5404 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5405 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5406 emit_int8(0x72);
5407 emit_int8((unsigned char)(0xC0 | encode));
5408 emit_int8(shift & 0xFF);
5409 }
5410
5411 void Assembler::psllq(XMMRegister dst, int shift) {
5412 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5413 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5414 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5415 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5416 emit_int8(0x73);
5417 emit_int8((unsigned char)(0xC0 | encode));
5418 emit_int8(shift & 0xFF);
5419 }
5420
5421 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5424 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5425 emit_int8((unsigned char)0xF1);
5426 emit_int8((unsigned char)(0xC0 | encode));
5427 }
5428
5429 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5432 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5433 emit_int8((unsigned char)0xF2);
5434 emit_int8((unsigned char)(0xC0 | encode));
5435 }
5436
5437 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5439 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5440 attributes.set_rex_vex_w_reverted();
5441 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5442 emit_int8((unsigned char)0xF3);
5443 emit_int8((unsigned char)(0xC0 | encode));
5444 }
5445
5446 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5447 assert(UseAVX > 0, "requires some form of AVX");
5448 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5449 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5450 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5451 emit_int8(0x71);
5452 emit_int8((unsigned char)(0xC0 | encode));
5453 emit_int8(shift & 0xFF);
5454 }
5455
5456 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5457 assert(UseAVX > 0, "requires some form of AVX");
5458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5459 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5460 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5461 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5462 emit_int8(0x72);
5463 emit_int8((unsigned char)(0xC0 | encode));
5464 emit_int8(shift & 0xFF);
5465 }
5466
5467 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5468 assert(UseAVX > 0, "requires some form of AVX");
5469 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5470 attributes.set_rex_vex_w_reverted();
5471 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5472 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5473 emit_int8(0x73);
5474 emit_int8((unsigned char)(0xC0 | encode));
5475 emit_int8(shift & 0xFF);
5476 }
5477
5478 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5479 assert(UseAVX > 0, "requires some form of AVX");
5480 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5481 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5482 emit_int8((unsigned char)0xF1);
5483 emit_int8((unsigned char)(0xC0 | encode));
5484 }
5485
5486 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5487 assert(UseAVX > 0, "requires some form of AVX");
5488 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5489 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5490 emit_int8((unsigned char)0xF2);
5491 emit_int8((unsigned char)(0xC0 | encode));
5492 }
5493
5494 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5495 assert(UseAVX > 0, "requires some form of AVX");
5496 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5497 attributes.set_rex_vex_w_reverted();
5498 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5499 emit_int8((unsigned char)0xF3);
5500 emit_int8((unsigned char)(0xC0 | encode));
5501 }
5502
5503 // Shift packed integers logically right by specified number of bits.
5504 void Assembler::psrlw(XMMRegister dst, int shift) {
5505 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5506 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5507 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5508 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5509 emit_int8(0x71);
5510 emit_int8((unsigned char)(0xC0 | encode));
5511 emit_int8(shift & 0xFF);
5512 }
5513
5514 void Assembler::psrld(XMMRegister dst, int shift) {
5515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5516 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5517 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5518 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5519 emit_int8(0x72);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 emit_int8(shift & 0xFF);
5522 }
5523
5524 void Assembler::psrlq(XMMRegister dst, int shift) {
5525 // Do not confuse it with psrldq SSE2 instruction which
5526 // shifts 128 bit value in xmm register by number of bytes.
5527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5528 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5529 attributes.set_rex_vex_w_reverted();
5530 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5531 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5532 emit_int8(0x73);
5533 emit_int8((unsigned char)(0xC0 | encode));
5534 emit_int8(shift & 0xFF);
5535 }
5536
5537 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5540 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5541 emit_int8((unsigned char)0xD1);
5542 emit_int8((unsigned char)(0xC0 | encode));
5543 }
5544
5545 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5548 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5549 emit_int8((unsigned char)0xD2);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5554 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5555 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5556 attributes.set_rex_vex_w_reverted();
5557 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5558 emit_int8((unsigned char)0xD3);
5559 emit_int8((unsigned char)(0xC0 | encode));
5560 }
5561
5562 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5563 assert(UseAVX > 0, "requires some form of AVX");
5564 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5565 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5566 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5567 emit_int8(0x71);
5568 emit_int8((unsigned char)(0xC0 | encode));
5569 emit_int8(shift & 0xFF);
5570 }
5571
5572 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5573 assert(UseAVX > 0, "requires some form of AVX");
5574 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5575 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5576 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5577 emit_int8(0x72);
5578 emit_int8((unsigned char)(0xC0 | encode));
5579 emit_int8(shift & 0xFF);
5580 }
5581
5582 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5583 assert(UseAVX > 0, "requires some form of AVX");
5584 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5585 attributes.set_rex_vex_w_reverted();
5586 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5587 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5588 emit_int8(0x73);
5589 emit_int8((unsigned char)(0xC0 | encode));
5590 emit_int8(shift & 0xFF);
5591 }
5592
5593 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5594 assert(UseAVX > 0, "requires some form of AVX");
5595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5596 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5597 emit_int8((unsigned char)0xD1);
5598 emit_int8((unsigned char)(0xC0 | encode));
5599 }
5600
5601 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5602 assert(UseAVX > 0, "requires some form of AVX");
5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5604 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5605 emit_int8((unsigned char)0xD2);
5606 emit_int8((unsigned char)(0xC0 | encode));
5607 }
5608
5609 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5610 assert(UseAVX > 0, "requires some form of AVX");
5611 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5612 attributes.set_rex_vex_w_reverted();
5613 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5614 emit_int8((unsigned char)0xD3);
5615 emit_int8((unsigned char)(0xC0 | encode));
5616 }
5617
5618 // Shift packed integers arithmetically right by specified number of bits.
5619 void Assembler::psraw(XMMRegister dst, int shift) {
5620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5621 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5622 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5623 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5624 emit_int8(0x71);
5625 emit_int8((unsigned char)(0xC0 | encode));
5626 emit_int8(shift & 0xFF);
5627 }
5628
5629 void Assembler::psrad(XMMRegister dst, int shift) {
5630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5632 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5633 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int8(0x72);
5635 emit_int8((unsigned char)(0xC0 | encode));
5636 emit_int8(shift & 0xFF);
5637 }
5638
5639 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5641 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5642 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5643 emit_int8((unsigned char)0xE1);
5644 emit_int8((unsigned char)(0xC0 | encode));
5645 }
5646
5647 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5649 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5650 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5651 emit_int8((unsigned char)0xE2);
5652 emit_int8((unsigned char)(0xC0 | encode));
5653 }
5654
5655 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5656 assert(UseAVX > 0, "requires some form of AVX");
5657 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5658 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5659 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5660 emit_int8(0x71);
5661 emit_int8((unsigned char)(0xC0 | encode));
5662 emit_int8(shift & 0xFF);
5663 }
5664
5665 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5666 assert(UseAVX > 0, "requires some form of AVX");
5667 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5668 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5669 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5670 emit_int8(0x72);
5671 emit_int8((unsigned char)(0xC0 | encode));
5672 emit_int8(shift & 0xFF);
5673 }
5674
5675 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5676 assert(UseAVX > 0, "requires some form of AVX");
5677 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5678 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xE1);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 }
5682
5683 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5684 assert(UseAVX > 0, "requires some form of AVX");
5685 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5686 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5687 emit_int8((unsigned char)0xE2);
5688 emit_int8((unsigned char)(0xC0 | encode));
5689 }
5690
5691
5692 // logical operations packed integers
5693 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5696 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5697 emit_int8((unsigned char)0xDB);
5698 emit_int8((unsigned char)(0xC0 | encode));
5699 }
5700
5701 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5702 assert(UseAVX > 0, "requires some form of AVX");
5703 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5704 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5705 emit_int8((unsigned char)0xDB);
5706 emit_int8((unsigned char)(0xC0 | encode));
5707 }
5708
5709 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5710 assert(UseAVX > 0, "requires some form of AVX");
5711 InstructionMark im(this);
5712 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5713 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5714 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5715 emit_int8((unsigned char)0xDB);
5716 emit_operand(dst, src);
5717 }
5718
5719 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5721 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5722 attributes.set_rex_vex_w_reverted();
5723 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5724 emit_int8((unsigned char)0xDF);
5725 emit_int8((unsigned char)(0xC0 | encode));
5726 }
5727
5728 void Assembler::por(XMMRegister dst, XMMRegister src) {
5729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5730 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5731 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5732 emit_int8((unsigned char)0xEB);
5733 emit_int8((unsigned char)(0xC0 | encode));
5734 }
5735
5736 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5737 assert(UseAVX > 0, "requires some form of AVX");
5738 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5739 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5740 emit_int8((unsigned char)0xEB);
5741 emit_int8((unsigned char)(0xC0 | encode));
5742 }
5743
5744 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5745 assert(UseAVX > 0, "requires some form of AVX");
5746 InstructionMark im(this);
5747 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5748 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5749 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5750 emit_int8((unsigned char)0xEB);
5751 emit_operand(dst, src);
5752 }
5753
5754 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5756 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5758 emit_int8((unsigned char)0xEF);
5759 emit_int8((unsigned char)(0xC0 | encode));
5760 }
5761
5762 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5763 assert(UseAVX > 0, "requires some form of AVX");
5764 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5765 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5766 emit_int8((unsigned char)0xEF);
5767 emit_int8((unsigned char)(0xC0 | encode));
5768 }
5769
5770 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5771 assert(UseAVX > 0, "requires some form of AVX");
5772 InstructionMark im(this);
5773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5774 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5775 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5776 emit_int8((unsigned char)0xEF);
5777 emit_operand(dst, src);
5778 }
5779
5780
5781 // vinserti forms
5782
5783 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5784 assert(VM_Version::supports_avx2(), "");
5785 assert(imm8 <= 0x01, "imm8: %u", imm8);
5786 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5787 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5788 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5789 emit_int8(0x38);
5790 emit_int8((unsigned char)(0xC0 | encode));
5791 // 0x00 - insert into lower 128 bits
5792 // 0x01 - insert into upper 128 bits
5793 emit_int8(imm8 & 0x01);
5794 }
5795
5796 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5797 assert(VM_Version::supports_avx2(), "");
5798 assert(dst != xnoreg, "sanity");
5799 assert(imm8 <= 0x01, "imm8: %u", imm8);
5800 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5801 InstructionMark im(this);
5802 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5803 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5804 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5805 emit_int8(0x38);
5806 emit_operand(dst, src);
5807 // 0x00 - insert into lower 128 bits
5808 // 0x01 - insert into upper 128 bits
5809 emit_int8(imm8 & 0x01);
5810 }
5811
5812 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5813 assert(VM_Version::supports_evex(), "");
5814 assert(imm8 <= 0x03, "imm8: %u", imm8);
5815 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5816 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5817 emit_int8(0x38);
5818 emit_int8((unsigned char)(0xC0 | encode));
5819 // 0x00 - insert into q0 128 bits (0..127)
5820 // 0x01 - insert into q1 128 bits (128..255)
5821 // 0x02 - insert into q2 128 bits (256..383)
5822 // 0x03 - insert into q3 128 bits (384..511)
5823 emit_int8(imm8 & 0x03);
5824 }
5825
5826 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5827 assert(VM_Version::supports_avx(), "");
5828 assert(dst != xnoreg, "sanity");
5829 assert(imm8 <= 0x03, "imm8: %u", imm8);
5830 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5831 InstructionMark im(this);
5832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5833 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5834 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5835 emit_int8(0x18);
5836 emit_operand(dst, src);
5837 // 0x00 - insert into q0 128 bits (0..127)
5838 // 0x01 - insert into q1 128 bits (128..255)
5839 // 0x02 - insert into q2 128 bits (256..383)
5840 // 0x03 - insert into q3 128 bits (384..511)
5841 emit_int8(imm8 & 0x03);
5842 }
5843
5844 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5845 assert(VM_Version::supports_evex(), "");
5846 assert(imm8 <= 0x01, "imm8: %u", imm8);
5847 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5848 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5849 emit_int8(0x38);
5850 emit_int8((unsigned char)(0xC0 | encode));
5851 // 0x00 - insert into lower 256 bits
5852 // 0x01 - insert into upper 256 bits
5853 emit_int8(imm8 & 0x01);
5854 }
5855
5856
5857 // vinsertf forms
5858
5859 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5860 assert(VM_Version::supports_avx(), "");
5861 assert(imm8 <= 0x01, "imm8: %u", imm8);
5862 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5863 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5864 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5865 emit_int8(0x18);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 // 0x00 - insert into lower 128 bits
5868 // 0x01 - insert into upper 128 bits
5869 emit_int8(imm8 & 0x01);
5870 }
5871
5872 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5873 assert(VM_Version::supports_avx(), "");
5874 assert(dst != xnoreg, "sanity");
5875 assert(imm8 <= 0x01, "imm8: %u", imm8);
5876 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5877 InstructionMark im(this);
5878 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5879 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5880 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5881 emit_int8(0x18);
5882 emit_operand(dst, src);
5883 // 0x00 - insert into lower 128 bits
5884 // 0x01 - insert into upper 128 bits
5885 emit_int8(imm8 & 0x01);
5886 }
5887
5888 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5889 assert(VM_Version::supports_evex(), "");
5890 assert(imm8 <= 0x03, "imm8: %u", imm8);
5891 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5893 emit_int8(0x18);
5894 emit_int8((unsigned char)(0xC0 | encode));
5895 // 0x00 - insert into q0 128 bits (0..127)
5896 // 0x01 - insert into q1 128 bits (128..255)
5897 // 0x02 - insert into q2 128 bits (256..383)
5898 // 0x03 - insert into q3 128 bits (384..511)
5899 emit_int8(imm8 & 0x03);
5900 }
5901
5902 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5903 assert(VM_Version::supports_avx(), "");
5904 assert(dst != xnoreg, "sanity");
5905 assert(imm8 <= 0x03, "imm8: %u", imm8);
5906 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5907 InstructionMark im(this);
5908 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5909 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5910 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5911 emit_int8(0x18);
5912 emit_operand(dst, src);
5913 // 0x00 - insert into q0 128 bits (0..127)
5914 // 0x01 - insert into q1 128 bits (128..255)
5915 // 0x02 - insert into q2 128 bits (256..383)
5916 // 0x03 - insert into q3 128 bits (384..511)
5917 emit_int8(imm8 & 0x03);
5918 }
5919
5920 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5921 assert(VM_Version::supports_evex(), "");
5922 assert(imm8 <= 0x01, "imm8: %u", imm8);
5923 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5924 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5925 emit_int8(0x1A);
5926 emit_int8((unsigned char)(0xC0 | encode));
5927 // 0x00 - insert into lower 256 bits
5928 // 0x01 - insert into upper 256 bits
5929 emit_int8(imm8 & 0x01);
5930 }
5931
5932 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5933 assert(VM_Version::supports_evex(), "");
5934 assert(dst != xnoreg, "sanity");
5935 assert(imm8 <= 0x01, "imm8: %u", imm8);
5936 InstructionMark im(this);
5937 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5938 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5939 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5940 emit_int8(0x1A);
5941 emit_operand(dst, src);
5942 // 0x00 - insert into lower 256 bits
5943 // 0x01 - insert into upper 256 bits
5944 emit_int8(imm8 & 0x01);
5945 }
5946
5947
5948 // vextracti forms
5949
5950 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5951 assert(VM_Version::supports_avx(), "");
5952 assert(imm8 <= 0x01, "imm8: %u", imm8);
5953 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5954 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5955 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5956 emit_int8(0x39);
5957 emit_int8((unsigned char)(0xC0 | encode));
5958 // 0x00 - extract from lower 128 bits
5959 // 0x01 - extract from upper 128 bits
5960 emit_int8(imm8 & 0x01);
5961 }
5962
5963 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5964 assert(VM_Version::supports_avx2(), "");
5965 assert(src != xnoreg, "sanity");
5966 assert(imm8 <= 0x01, "imm8: %u", imm8);
5967 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5968 InstructionMark im(this);
5969 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5970 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5971 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5972 emit_int8(0x39);
5973 emit_operand(src, dst);
5974 // 0x00 - extract from lower 128 bits
5975 // 0x01 - extract from upper 128 bits
5976 emit_int8(imm8 & 0x01);
5977 }
5978
5979 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5980 assert(VM_Version::supports_avx(), "");
5981 assert(imm8 <= 0x03, "imm8: %u", imm8);
5982 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5983 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5984 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5985 emit_int8(0x39);
5986 emit_int8((unsigned char)(0xC0 | encode));
5987 // 0x00 - extract from bits 127:0
5988 // 0x01 - extract from bits 255:128
5989 // 0x02 - extract from bits 383:256
5990 // 0x03 - extract from bits 511:384
5991 emit_int8(imm8 & 0x03);
5992 }
5993
5994 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
5995 assert(VM_Version::supports_evex(), "");
5996 assert(src != xnoreg, "sanity");
5997 assert(imm8 <= 0x03, "imm8: %u", imm8);
5998 InstructionMark im(this);
5999 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6000 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6001 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6002 emit_int8(0x39);
6003 emit_operand(src, dst);
6004 // 0x00 - extract from bits 127:0
6005 // 0x01 - extract from bits 255:128
6006 // 0x02 - extract from bits 383:256
6007 // 0x03 - extract from bits 511:384
6008 emit_int8(imm8 & 0x03);
6009 }
6010
6011 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6012 assert(VM_Version::supports_avx512dq(), "");
6013 assert(imm8 <= 0x03, "imm8: %u", imm8);
6014 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6015 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6016 emit_int8(0x39);
6017 emit_int8((unsigned char)(0xC0 | encode));
6018 // 0x00 - extract from bits 127:0
6019 // 0x01 - extract from bits 255:128
6020 // 0x02 - extract from bits 383:256
6021 // 0x03 - extract from bits 511:384
6022 emit_int8(imm8 & 0x03);
6023 }
6024
6025 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6026 assert(VM_Version::supports_evex(), "");
6027 assert(imm8 <= 0x01, "imm8: %u", imm8);
6028 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6029 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6030 emit_int8(0x3B);
6031 emit_int8((unsigned char)(0xC0 | encode));
6032 // 0x00 - extract from lower 256 bits
6033 // 0x01 - extract from upper 256 bits
6034 emit_int8(imm8 & 0x01);
6035 }
6036
6037
6038 // vextractf forms
6039
6040 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6041 assert(VM_Version::supports_avx(), "");
6042 assert(imm8 <= 0x01, "imm8: %u", imm8);
6043 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6044 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6045 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6046 emit_int8(0x19);
6047 emit_int8((unsigned char)(0xC0 | encode));
6048 // 0x00 - extract from lower 128 bits
6049 // 0x01 - extract from upper 128 bits
6050 emit_int8(imm8 & 0x01);
6051 }
6052
6053 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6054 assert(VM_Version::supports_avx(), "");
6055 assert(src != xnoreg, "sanity");
6056 assert(imm8 <= 0x01, "imm8: %u", imm8);
6057 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6058 InstructionMark im(this);
6059 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6060 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6061 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6062 emit_int8(0x19);
6063 emit_operand(src, dst);
6064 // 0x00 - extract from lower 128 bits
6065 // 0x01 - extract from upper 128 bits
6066 emit_int8(imm8 & 0x01);
6067 }
6068
6069 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6070 assert(VM_Version::supports_avx(), "");
6071 assert(imm8 <= 0x03, "imm8: %u", imm8);
6072 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6073 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6074 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6075 emit_int8(0x19);
6076 emit_int8((unsigned char)(0xC0 | encode));
6077 // 0x00 - extract from bits 127:0
6078 // 0x01 - extract from bits 255:128
6079 // 0x02 - extract from bits 383:256
6080 // 0x03 - extract from bits 511:384
6081 emit_int8(imm8 & 0x03);
6082 }
6083
6084 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6085 assert(VM_Version::supports_evex(), "");
6086 assert(src != xnoreg, "sanity");
6087 assert(imm8 <= 0x03, "imm8: %u", imm8);
6088 InstructionMark im(this);
6089 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6090 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6091 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6092 emit_int8(0x19);
6093 emit_operand(src, dst);
6094 // 0x00 - extract from bits 127:0
6095 // 0x01 - extract from bits 255:128
6096 // 0x02 - extract from bits 383:256
6097 // 0x03 - extract from bits 511:384
6098 emit_int8(imm8 & 0x03);
6099 }
6100
6101 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6102 assert(VM_Version::supports_avx512dq(), "");
6103 assert(imm8 <= 0x03, "imm8: %u", imm8);
6104 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6105 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6106 emit_int8(0x19);
6107 emit_int8((unsigned char)(0xC0 | encode));
6108 // 0x00 - extract from bits 127:0
6109 // 0x01 - extract from bits 255:128
6110 // 0x02 - extract from bits 383:256
6111 // 0x03 - extract from bits 511:384
6112 emit_int8(imm8 & 0x03);
6113 }
6114
6115 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6116 assert(VM_Version::supports_evex(), "");
6117 assert(imm8 <= 0x01, "imm8: %u", imm8);
6118 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6119 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6120 emit_int8(0x1B);
6121 emit_int8((unsigned char)(0xC0 | encode));
6122 // 0x00 - extract from lower 256 bits
6123 // 0x01 - extract from upper 256 bits
6124 emit_int8(imm8 & 0x01);
6125 }
6126
6127 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6128 assert(VM_Version::supports_evex(), "");
6129 assert(src != xnoreg, "sanity");
6130 assert(imm8 <= 0x01, "imm8: %u", imm8);
6131 InstructionMark im(this);
6132 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6133 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6134 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6135 emit_int8(0x1B);
6136 emit_operand(src, dst);
6137 // 0x00 - extract from lower 256 bits
6138 // 0x01 - extract from upper 256 bits
6139 emit_int8(imm8 & 0x01);
6140 }
6141
6142
6143 // legacy word/dword replicate
6144 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6145 assert(VM_Version::supports_avx2(), "");
6146 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6147 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6148 emit_int8(0x79);
6149 emit_int8((unsigned char)(0xC0 | encode));
6150 }
6151
6152 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6153 assert(VM_Version::supports_avx2(), "");
6154 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6155 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6156 emit_int8(0x58);
6157 emit_int8((unsigned char)(0xC0 | encode));
6158 }
6159
6160
6161 // xmm/mem sourced byte/word/dword/qword replicate
6162
6163 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6164 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6165 assert(VM_Version::supports_evex(), "");
6166 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6167 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6168 emit_int8(0x78);
6169 emit_int8((unsigned char)(0xC0 | encode));
6170 }
6171
6172 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6173 assert(VM_Version::supports_evex(), "");
6174 assert(dst != xnoreg, "sanity");
6175 InstructionMark im(this);
6176 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6177 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6178 // swap src<->dst for encoding
6179 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6180 emit_int8(0x78);
6181 emit_operand(dst, src);
6182 }
6183
6184 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6185 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6186 assert(VM_Version::supports_evex(), "");
6187 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6188 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6189 emit_int8(0x79);
6190 emit_int8((unsigned char)(0xC0 | encode));
6191 }
6192
6193 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6194 assert(VM_Version::supports_evex(), "");
6195 assert(dst != xnoreg, "sanity");
6196 InstructionMark im(this);
6197 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6198 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6199 // swap src<->dst for encoding
6200 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6201 emit_int8(0x79);
6202 emit_operand(dst, src);
6203 }
6204
6205 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6206 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6207 assert(VM_Version::supports_evex(), "");
6208 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6209 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6210 emit_int8(0x58);
6211 emit_int8((unsigned char)(0xC0 | encode));
6212 }
6213
6214 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6215 assert(VM_Version::supports_evex(), "");
6216 assert(dst != xnoreg, "sanity");
6217 InstructionMark im(this);
6218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6219 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6220 // swap src<->dst for encoding
6221 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6222 emit_int8(0x58);
6223 emit_operand(dst, src);
6224 }
6225
6226 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6227 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6228 assert(VM_Version::supports_evex(), "");
6229 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6230 attributes.set_rex_vex_w_reverted();
6231 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6232 emit_int8(0x59);
6233 emit_int8((unsigned char)(0xC0 | encode));
6234 }
6235
6236 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6237 assert(VM_Version::supports_evex(), "");
6238 assert(dst != xnoreg, "sanity");
6239 InstructionMark im(this);
6240 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6241 attributes.set_rex_vex_w_reverted();
6242 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6243 // swap src<->dst for encoding
6244 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6245 emit_int8(0x59);
6246 emit_operand(dst, src);
6247 }
6248
6249
6250 // scalar single/double precision replicate
6251
6252 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6253 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6254 assert(VM_Version::supports_evex(), "");
6255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6256 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6257 emit_int8(0x18);
6258 emit_int8((unsigned char)(0xC0 | encode));
6259 }
6260
6261 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6262 assert(VM_Version::supports_evex(), "");
6263 assert(dst != xnoreg, "sanity");
6264 InstructionMark im(this);
6265 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6266 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6267 // swap src<->dst for encoding
6268 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6269 emit_int8(0x18);
6270 emit_operand(dst, src);
6271 }
6272
6273 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6274 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6275 assert(VM_Version::supports_evex(), "");
6276 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6277 attributes.set_rex_vex_w_reverted();
6278 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6279 emit_int8(0x19);
6280 emit_int8((unsigned char)(0xC0 | encode));
6281 }
6282
6283 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6284 assert(VM_Version::supports_evex(), "");
6285 assert(dst != xnoreg, "sanity");
6286 InstructionMark im(this);
6287 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6288 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6289 attributes.set_rex_vex_w_reverted();
6290 // swap src<->dst for encoding
6291 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6292 emit_int8(0x19);
6293 emit_operand(dst, src);
6294 }
6295
6296
6297 // gpr source broadcast forms
6298
6299 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6300 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6301 assert(VM_Version::supports_evex(), "");
6302 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6303 attributes.set_is_evex_instruction();
6304 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6305 emit_int8(0x7A);
6306 emit_int8((unsigned char)(0xC0 | encode));
6307 }
6308
6309 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6310 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6311 assert(VM_Version::supports_evex(), "");
6312 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6313 attributes.set_is_evex_instruction();
6314 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6315 emit_int8(0x7B);
6316 emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318
6319 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6320 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6321 assert(VM_Version::supports_evex(), "");
6322 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6323 attributes.set_is_evex_instruction();
6324 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6325 emit_int8(0x7C);
6326 emit_int8((unsigned char)(0xC0 | encode));
6327 }
6328
6329 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6330 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6331 assert(VM_Version::supports_evex(), "");
6332 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6333 attributes.set_is_evex_instruction();
6334 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6335 emit_int8(0x7C);
6336 emit_int8((unsigned char)(0xC0 | encode));
6337 }
6338
6339
6340 // Carry-Less Multiplication Quadword
6341 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6342 assert(VM_Version::supports_clmul(), "");
6343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6344 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6345 emit_int8(0x44);
6346 emit_int8((unsigned char)(0xC0 | encode));
6347 emit_int8((unsigned char)mask);
6348 }
6349
6350 // Carry-Less Multiplication Quadword
6351 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6352 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6353 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6354 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6355 emit_int8(0x44);
6356 emit_int8((unsigned char)(0xC0 | encode));
6357 emit_int8((unsigned char)mask);
6358 }
6359
6360 void Assembler::vzeroupper() {
6361 assert(VM_Version::supports_avx(), "");
6362 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6363 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6364 emit_int8(0x77);
6365 }
6366
6367
6368 #ifndef _LP64
6369 // 32bit only pieces of the assembler
6370
6371 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6372 // NO PREFIX AS NEVER 64BIT
6373 InstructionMark im(this);
6374 emit_int8((unsigned char)0x81);
6375 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6376 emit_data(imm32, rspec, 0);
6377 }
6378
6379 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6380 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6381 InstructionMark im(this);
6382 emit_int8((unsigned char)0x81);
6383 emit_operand(rdi, src1);
6384 emit_data(imm32, rspec, 0);
6385 }
6386
6387 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6388 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6389 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6390 void Assembler::cmpxchg8(Address adr) {
6391 InstructionMark im(this);
6392 emit_int8(0x0F);
6393 emit_int8((unsigned char)0xC7);
6394 emit_operand(rcx, adr);
6395 }
6396
6397 void Assembler::decl(Register dst) {
6398 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6399 emit_int8(0x48 | dst->encoding());
6400 }
6401
6402 #endif // _LP64
6403
6404 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6405
6406 void Assembler::fabs() {
6407 emit_int8((unsigned char)0xD9);
6408 emit_int8((unsigned char)0xE1);
6409 }
6410
6411 void Assembler::fadd(int i) {
6412 emit_farith(0xD8, 0xC0, i);
6413 }
6414
6415 void Assembler::fadd_d(Address src) {
6416 InstructionMark im(this);
6417 emit_int8((unsigned char)0xDC);
6418 emit_operand32(rax, src);
6419 }
6420
6421 void Assembler::fadd_s(Address src) {
6422 InstructionMark im(this);
6423 emit_int8((unsigned char)0xD8);
6424 emit_operand32(rax, src);
6425 }
6426
6427 void Assembler::fadda(int i) {
6428 emit_farith(0xDC, 0xC0, i);
6429 }
6430
6431 void Assembler::faddp(int i) {
6432 emit_farith(0xDE, 0xC0, i);
6433 }
6434
6435 void Assembler::fchs() {
6436 emit_int8((unsigned char)0xD9);
6437 emit_int8((unsigned char)0xE0);
6438 }
6439
6440 void Assembler::fcom(int i) {
6441 emit_farith(0xD8, 0xD0, i);
6442 }
6443
6444 void Assembler::fcomp(int i) {
6445 emit_farith(0xD8, 0xD8, i);
6446 }
6447
6448 void Assembler::fcomp_d(Address src) {
6449 InstructionMark im(this);
6450 emit_int8((unsigned char)0xDC);
6451 emit_operand32(rbx, src);
6452 }
6453
6454 void Assembler::fcomp_s(Address src) {
6455 InstructionMark im(this);
6456 emit_int8((unsigned char)0xD8);
6457 emit_operand32(rbx, src);
6458 }
6459
6460 void Assembler::fcompp() {
6461 emit_int8((unsigned char)0xDE);
6462 emit_int8((unsigned char)0xD9);
6463 }
6464
6465 void Assembler::fcos() {
6466 emit_int8((unsigned char)0xD9);
6467 emit_int8((unsigned char)0xFF);
6468 }
6469
6470 void Assembler::fdecstp() {
6471 emit_int8((unsigned char)0xD9);
6472 emit_int8((unsigned char)0xF6);
6473 }
6474
6475 void Assembler::fdiv(int i) {
6476 emit_farith(0xD8, 0xF0, i);
6477 }
6478
6479 void Assembler::fdiv_d(Address src) {
6480 InstructionMark im(this);
6481 emit_int8((unsigned char)0xDC);
6482 emit_operand32(rsi, src);
6483 }
6484
6485 void Assembler::fdiv_s(Address src) {
6486 InstructionMark im(this);
6487 emit_int8((unsigned char)0xD8);
6488 emit_operand32(rsi, src);
6489 }
6490
6491 void Assembler::fdiva(int i) {
6492 emit_farith(0xDC, 0xF8, i);
6493 }
6494
6495 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6496 // is erroneous for some of the floating-point instructions below.
6497
6498 void Assembler::fdivp(int i) {
6499 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6500 }
6501
6502 void Assembler::fdivr(int i) {
6503 emit_farith(0xD8, 0xF8, i);
6504 }
6505
6506 void Assembler::fdivr_d(Address src) {
6507 InstructionMark im(this);
6508 emit_int8((unsigned char)0xDC);
6509 emit_operand32(rdi, src);
6510 }
6511
6512 void Assembler::fdivr_s(Address src) {
6513 InstructionMark im(this);
6514 emit_int8((unsigned char)0xD8);
6515 emit_operand32(rdi, src);
6516 }
6517
6518 void Assembler::fdivra(int i) {
6519 emit_farith(0xDC, 0xF0, i);
6520 }
6521
6522 void Assembler::fdivrp(int i) {
6523 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6524 }
6525
6526 void Assembler::ffree(int i) {
6527 emit_farith(0xDD, 0xC0, i);
6528 }
6529
6530 void Assembler::fild_d(Address adr) {
6531 InstructionMark im(this);
6532 emit_int8((unsigned char)0xDF);
6533 emit_operand32(rbp, adr);
6534 }
6535
6536 void Assembler::fild_s(Address adr) {
6537 InstructionMark im(this);
6538 emit_int8((unsigned char)0xDB);
6539 emit_operand32(rax, adr);
6540 }
6541
6542 void Assembler::fincstp() {
6543 emit_int8((unsigned char)0xD9);
6544 emit_int8((unsigned char)0xF7);
6545 }
6546
6547 void Assembler::finit() {
6548 emit_int8((unsigned char)0x9B);
6549 emit_int8((unsigned char)0xDB);
6550 emit_int8((unsigned char)0xE3);
6551 }
6552
6553 void Assembler::fist_s(Address adr) {
6554 InstructionMark im(this);
6555 emit_int8((unsigned char)0xDB);
6556 emit_operand32(rdx, adr);
6557 }
6558
6559 void Assembler::fistp_d(Address adr) {
6560 InstructionMark im(this);
6561 emit_int8((unsigned char)0xDF);
6562 emit_operand32(rdi, adr);
6563 }
6564
6565 void Assembler::fistp_s(Address adr) {
6566 InstructionMark im(this);
6567 emit_int8((unsigned char)0xDB);
6568 emit_operand32(rbx, adr);
6569 }
6570
6571 void Assembler::fld1() {
6572 emit_int8((unsigned char)0xD9);
6573 emit_int8((unsigned char)0xE8);
6574 }
6575
6576 void Assembler::fld_d(Address adr) {
6577 InstructionMark im(this);
6578 emit_int8((unsigned char)0xDD);
6579 emit_operand32(rax, adr);
6580 }
6581
6582 void Assembler::fld_s(Address adr) {
6583 InstructionMark im(this);
6584 emit_int8((unsigned char)0xD9);
6585 emit_operand32(rax, adr);
6586 }
6587
6588
6589 void Assembler::fld_s(int index) {
6590 emit_farith(0xD9, 0xC0, index);
6591 }
6592
6593 void Assembler::fld_x(Address adr) {
6594 InstructionMark im(this);
6595 emit_int8((unsigned char)0xDB);
6596 emit_operand32(rbp, adr);
6597 }
6598
6599 void Assembler::fldcw(Address src) {
6600 InstructionMark im(this);
6601 emit_int8((unsigned char)0xD9);
6602 emit_operand32(rbp, src);
6603 }
6604
6605 void Assembler::fldenv(Address src) {
6606 InstructionMark im(this);
6607 emit_int8((unsigned char)0xD9);
6608 emit_operand32(rsp, src);
6609 }
6610
6611 void Assembler::fldlg2() {
6612 emit_int8((unsigned char)0xD9);
6613 emit_int8((unsigned char)0xEC);
6614 }
6615
6616 void Assembler::fldln2() {
6617 emit_int8((unsigned char)0xD9);
6618 emit_int8((unsigned char)0xED);
6619 }
6620
6621 void Assembler::fldz() {
6622 emit_int8((unsigned char)0xD9);
6623 emit_int8((unsigned char)0xEE);
6624 }
6625
6626 void Assembler::flog() {
6627 fldln2();
6628 fxch();
6629 fyl2x();
6630 }
6631
6632 void Assembler::flog10() {
6633 fldlg2();
6634 fxch();
6635 fyl2x();
6636 }
6637
6638 void Assembler::fmul(int i) {
6639 emit_farith(0xD8, 0xC8, i);
6640 }
6641
6642 void Assembler::fmul_d(Address src) {
6643 InstructionMark im(this);
6644 emit_int8((unsigned char)0xDC);
6645 emit_operand32(rcx, src);
6646 }
6647
6648 void Assembler::fmul_s(Address src) {
6649 InstructionMark im(this);
6650 emit_int8((unsigned char)0xD8);
6651 emit_operand32(rcx, src);
6652 }
6653
6654 void Assembler::fmula(int i) {
6655 emit_farith(0xDC, 0xC8, i);
6656 }
6657
6658 void Assembler::fmulp(int i) {
6659 emit_farith(0xDE, 0xC8, i);
6660 }
6661
6662 void Assembler::fnsave(Address dst) {
6663 InstructionMark im(this);
6664 emit_int8((unsigned char)0xDD);
6665 emit_operand32(rsi, dst);
6666 }
6667
6668 void Assembler::fnstcw(Address src) {
6669 InstructionMark im(this);
6670 emit_int8((unsigned char)0x9B);
6671 emit_int8((unsigned char)0xD9);
6672 emit_operand32(rdi, src);
6673 }
6674
6675 void Assembler::fnstsw_ax() {
6676 emit_int8((unsigned char)0xDF);
6677 emit_int8((unsigned char)0xE0);
6678 }
6679
6680 void Assembler::fprem() {
6681 emit_int8((unsigned char)0xD9);
6682 emit_int8((unsigned char)0xF8);
6683 }
6684
6685 void Assembler::fprem1() {
6686 emit_int8((unsigned char)0xD9);
6687 emit_int8((unsigned char)0xF5);
6688 }
6689
6690 void Assembler::frstor(Address src) {
6691 InstructionMark im(this);
6692 emit_int8((unsigned char)0xDD);
6693 emit_operand32(rsp, src);
6694 }
6695
6696 void Assembler::fsin() {
6697 emit_int8((unsigned char)0xD9);
6698 emit_int8((unsigned char)0xFE);
6699 }
6700
6701 void Assembler::fsqrt() {
6702 emit_int8((unsigned char)0xD9);
6703 emit_int8((unsigned char)0xFA);
6704 }
6705
6706 void Assembler::fst_d(Address adr) {
6707 InstructionMark im(this);
6708 emit_int8((unsigned char)0xDD);
6709 emit_operand32(rdx, adr);
6710 }
6711
6712 void Assembler::fst_s(Address adr) {
6713 InstructionMark im(this);
6714 emit_int8((unsigned char)0xD9);
6715 emit_operand32(rdx, adr);
6716 }
6717
6718 void Assembler::fstp_d(Address adr) {
6719 InstructionMark im(this);
6720 emit_int8((unsigned char)0xDD);
6721 emit_operand32(rbx, adr);
6722 }
6723
6724 void Assembler::fstp_d(int index) {
6725 emit_farith(0xDD, 0xD8, index);
6726 }
6727
6728 void Assembler::fstp_s(Address adr) {
6729 InstructionMark im(this);
6730 emit_int8((unsigned char)0xD9);
6731 emit_operand32(rbx, adr);
6732 }
6733
6734 void Assembler::fstp_x(Address adr) {
6735 InstructionMark im(this);
6736 emit_int8((unsigned char)0xDB);
6737 emit_operand32(rdi, adr);
6738 }
6739
6740 void Assembler::fsub(int i) {
6741 emit_farith(0xD8, 0xE0, i);
6742 }
6743
6744 void Assembler::fsub_d(Address src) {
6745 InstructionMark im(this);
6746 emit_int8((unsigned char)0xDC);
6747 emit_operand32(rsp, src);
6748 }
6749
6750 void Assembler::fsub_s(Address src) {
6751 InstructionMark im(this);
6752 emit_int8((unsigned char)0xD8);
6753 emit_operand32(rsp, src);
6754 }
6755
6756 void Assembler::fsuba(int i) {
6757 emit_farith(0xDC, 0xE8, i);
6758 }
6759
6760 void Assembler::fsubp(int i) {
6761 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6762 }
6763
6764 void Assembler::fsubr(int i) {
6765 emit_farith(0xD8, 0xE8, i);
6766 }
6767
6768 void Assembler::fsubr_d(Address src) {
6769 InstructionMark im(this);
6770 emit_int8((unsigned char)0xDC);
6771 emit_operand32(rbp, src);
6772 }
6773
6774 void Assembler::fsubr_s(Address src) {
6775 InstructionMark im(this);
6776 emit_int8((unsigned char)0xD8);
6777 emit_operand32(rbp, src);
6778 }
6779
6780 void Assembler::fsubra(int i) {
6781 emit_farith(0xDC, 0xE0, i);
6782 }
6783
6784 void Assembler::fsubrp(int i) {
6785 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6786 }
6787
6788 void Assembler::ftan() {
6789 emit_int8((unsigned char)0xD9);
6790 emit_int8((unsigned char)0xF2);
6791 emit_int8((unsigned char)0xDD);
6792 emit_int8((unsigned char)0xD8);
6793 }
6794
6795 void Assembler::ftst() {
6796 emit_int8((unsigned char)0xD9);
6797 emit_int8((unsigned char)0xE4);
6798 }
6799
6800 void Assembler::fucomi(int i) {
6801 // make sure the instruction is supported (introduced for P6, together with cmov)
6802 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6803 emit_farith(0xDB, 0xE8, i);
6804 }
6805
6806 void Assembler::fucomip(int i) {
6807 // make sure the instruction is supported (introduced for P6, together with cmov)
6808 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6809 emit_farith(0xDF, 0xE8, i);
6810 }
6811
6812 void Assembler::fwait() {
6813 emit_int8((unsigned char)0x9B);
6814 }
6815
6816 void Assembler::fxch(int i) {
6817 emit_farith(0xD9, 0xC8, i);
6818 }
6819
6820 void Assembler::fyl2x() {
6821 emit_int8((unsigned char)0xD9);
6822 emit_int8((unsigned char)0xF1);
6823 }
6824
6825 void Assembler::frndint() {
6826 emit_int8((unsigned char)0xD9);
6827 emit_int8((unsigned char)0xFC);
6828 }
6829
6830 void Assembler::f2xm1() {
6831 emit_int8((unsigned char)0xD9);
6832 emit_int8((unsigned char)0xF0);
6833 }
6834
6835 void Assembler::fldl2e() {
6836 emit_int8((unsigned char)0xD9);
6837 emit_int8((unsigned char)0xEA);
6838 }
6839
6840 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6841 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6842 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6843 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6844
6845 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6846 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6847 if (pre > 0) {
6848 emit_int8(simd_pre[pre]);
6849 }
6850 if (rex_w) {
6851 prefixq(adr, xreg);
6852 } else {
6853 prefix(adr, xreg);
6854 }
6855 if (opc > 0) {
6856 emit_int8(0x0F);
6857 int opc2 = simd_opc[opc];
6858 if (opc2 > 0) {
6859 emit_int8(opc2);
6860 }
6861 }
6862 }
6863
6864 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6865 if (pre > 0) {
6866 emit_int8(simd_pre[pre]);
6867 }
6868 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6869 if (opc > 0) {
6870 emit_int8(0x0F);
6871 int opc2 = simd_opc[opc];
6872 if (opc2 > 0) {
6873 emit_int8(opc2);
6874 }
6875 }
6876 return encode;
6877 }
6878
6879
6880 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6881 int vector_len = _attributes->get_vector_len();
6882 bool vex_w = _attributes->is_rex_vex_w();
6883 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6884 prefix(VEX_3bytes);
6885
6886 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6887 byte1 = (~byte1) & 0xE0;
6888 byte1 |= opc;
6889 emit_int8(byte1);
6890
6891 int byte2 = ((~nds_enc) & 0xf) << 3;
6892 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6893 emit_int8(byte2);
6894 } else {
6895 prefix(VEX_2bytes);
6896
6897 int byte1 = vex_r ? VEX_R : 0;
6898 byte1 = (~byte1) & 0x80;
6899 byte1 |= ((~nds_enc) & 0xf) << 3;
6900 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6901 emit_int8(byte1);
6902 }
6903 }
6904
6905 // This is a 4 byte encoding
6906 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6907 // EVEX 0x62 prefix
6908 prefix(EVEX_4bytes);
6909 bool vex_w = _attributes->is_rex_vex_w();
6910 int evex_encoding = (vex_w ? VEX_W : 0);
6911 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6912 _attributes->set_evex_encoding(evex_encoding);
6913
6914 // P0: byte 2, initialized to RXBR`00mm
6915 // instead of not'd
6916 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6917 byte2 = (~byte2) & 0xF0;
6918 // confine opc opcode extensions in mm bits to lower two bits
6919 // of form {0F, 0F_38, 0F_3A}
6920 byte2 |= opc;
6921 emit_int8(byte2);
6922
6923 // P1: byte 3 as Wvvvv1pp
6924 int byte3 = ((~nds_enc) & 0xf) << 3;
6925 // p[10] is always 1
6926 byte3 |= EVEX_F;
6927 byte3 |= (vex_w & 1) << 7;
6928 // confine pre opcode extensions in pp bits to lower two bits
6929 // of form {66, F3, F2}
6930 byte3 |= pre;
6931 emit_int8(byte3);
6932
6933 // P2: byte 4 as zL'Lbv'aaa
6934 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : _attributes->get_embedded_opmask_register_specifier(); // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6935 // EVEX.v` for extending EVEX.vvvv or VIDX
6936 byte4 |= (evex_v ? 0: EVEX_V);
6937 // third EXEC.b for broadcast actions
6938 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6939 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6940 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6941 // last is EVEX.z for zero/merge actions
6942 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6943 emit_int8(byte4);
6944 }
6945
6946 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6947 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6948 bool vex_b = adr.base_needs_rex();
6949 bool vex_x = adr.index_needs_rex();
6950 set_attributes(attributes);
6951 attributes->set_current_assembler(this);
6952
6953 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6954 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6955 switch (attributes->get_vector_len()) {
6956 case AVX_128bit:
6957 case AVX_256bit:
6958 attributes->set_is_legacy_mode();
6959 break;
6960 }
6961 }
6962
6963 // For pure EVEX check and see if this instruction
6964 // is allowed in legacy mode and has resources which will
6965 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6966 // else that field is set when we encode to EVEX
6967 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6968 !_is_managed && !attributes->is_evex_instruction()) {
6969 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6970 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6971 if (check_register_bank) {
6972 // check nds_enc and xreg_enc for upper bank usage
6973 if (nds_enc < 16 && xreg_enc < 16) {
6974 attributes->set_is_legacy_mode();
6975 }
6976 } else {
6977 attributes->set_is_legacy_mode();
6978 }
6979 }
6980 }
6981
6982 _is_managed = false;
6983 if (UseAVX > 2 && !attributes->is_legacy_mode())
6984 {
6985 bool evex_r = (xreg_enc >= 16);
6986 bool evex_v = (nds_enc >= 16);
6987 attributes->set_is_evex_instruction();
6988 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6989 } else {
6990 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
6991 attributes->set_rex_vex_w(false);
6992 }
6993 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6994 }
6995 }
6996
6997 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6998 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6999 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7000 bool vex_x = false;
7001 set_attributes(attributes);
7002 attributes->set_current_assembler(this);
7003 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7004
7005 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7006 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7007 switch (attributes->get_vector_len()) {
7008 case AVX_128bit:
7009 case AVX_256bit:
7010 if (check_register_bank) {
7011 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7012 // up propagate arithmetic instructions to meet RA requirements
7013 attributes->set_vector_len(AVX_512bit);
7014 } else {
7015 attributes->set_is_legacy_mode();
7016 }
7017 } else {
7018 attributes->set_is_legacy_mode();
7019 }
7020 break;
7021 }
7022 }
7023
7024 // For pure EVEX check and see if this instruction
7025 // is allowed in legacy mode and has resources which will
7026 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7027 // else that field is set when we encode to EVEX
7028 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7029 !_is_managed && !attributes->is_evex_instruction()) {
7030 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7031 if (check_register_bank) {
7032 // check dst_enc, nds_enc and src_enc for upper bank usage
7033 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7034 attributes->set_is_legacy_mode();
7035 }
7036 } else {
7037 attributes->set_is_legacy_mode();
7038 }
7039 }
7040 }
7041
7042 _is_managed = false;
7043 if (UseAVX > 2 && !attributes->is_legacy_mode())
7044 {
7045 bool evex_r = (dst_enc >= 16);
7046 bool evex_v = (nds_enc >= 16);
7047 // can use vex_x as bank extender on rm encoding
7048 vex_x = (src_enc >= 16);
7049 attributes->set_is_evex_instruction();
7050 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7051 } else {
7052 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7053 attributes->set_rex_vex_w(false);
7054 }
7055 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7056 }
7057
7058 // return modrm byte components for operands
7059 return (((dst_enc & 7) << 3) | (src_enc & 7));
7060 }
7061
7062
7063 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7064 VexOpcode opc, InstructionAttr *attributes) {
7065 if (UseAVX > 0) {
7066 int xreg_enc = xreg->encoding();
7067 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7068 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7069 } else {
7070 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7071 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7072 }
7073 }
7074
7075 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7076 VexOpcode opc, InstructionAttr *attributes) {
7077 int dst_enc = dst->encoding();
7078 int src_enc = src->encoding();
7079 if (UseAVX > 0) {
7080 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7081 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7082 } else {
7083 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7084 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7085 }
7086 }
7087
7088 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7089 assert(VM_Version::supports_avx(), "");
7090 assert(!VM_Version::supports_evex(), "");
7091 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7092 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7093 emit_int8((unsigned char)0xC2);
7094 emit_int8((unsigned char)(0xC0 | encode));
7095 emit_int8((unsigned char)(0xF & cop));
7096 }
7097
7098 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7099 assert(VM_Version::supports_avx(), "");
7100 assert(!VM_Version::supports_evex(), "");
7101 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7102 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7103 emit_int8((unsigned char)0x4B);
7104 emit_int8((unsigned char)(0xC0 | encode));
7105 int src2_enc = src2->encoding();
7106 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7107 }
7108
7109 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7110 assert(VM_Version::supports_bmi2(), "");
7111 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7112 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7113 emit_int8((unsigned char)0xF7);
7114 emit_int8((unsigned char)(0xC0 | encode));
7115 }
7116
7117 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7118 assert(VM_Version::supports_bmi2(), "");
7119 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7120 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7121 emit_int8((unsigned char)0xF7);
7122 emit_int8((unsigned char)(0xC0 | encode));
7123 }
7124
7125 #ifndef _LP64
7126
7127 void Assembler::incl(Register dst) {
7128 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7129 emit_int8(0x40 | dst->encoding());
7130 }
7131
7132 void Assembler::lea(Register dst, Address src) {
7133 leal(dst, src);
7134 }
7135
7136 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7137 InstructionMark im(this);
7138 emit_int8((unsigned char)0xC7);
7139 emit_operand(rax, dst);
7140 emit_data((int)imm32, rspec, 0);
7141 }
7142
7143 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7144 InstructionMark im(this);
7145 int encode = prefix_and_encode(dst->encoding());
7146 emit_int8((unsigned char)(0xB8 | encode));
7147 emit_data((int)imm32, rspec, 0);
7148 }
7149
7150 void Assembler::popa() { // 32bit
7151 emit_int8(0x61);
7152 }
7153
7154 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7155 InstructionMark im(this);
7156 emit_int8(0x68);
7157 emit_data(imm32, rspec, 0);
7158 }
7159
7160 void Assembler::pusha() { // 32bit
7161 emit_int8(0x60);
7162 }
7163
7164 void Assembler::set_byte_if_not_zero(Register dst) {
7165 emit_int8(0x0F);
7166 emit_int8((unsigned char)0x95);
7167 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7168 }
7169
7170 void Assembler::shldl(Register dst, Register src) {
7171 emit_int8(0x0F);
7172 emit_int8((unsigned char)0xA5);
7173 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7174 }
7175
7176 // 0F A4 / r ib
7177 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7178 emit_int8(0x0F);
7179 emit_int8((unsigned char)0xA4);
7180 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7181 emit_int8(imm8);
7182 }
7183
7184 void Assembler::shrdl(Register dst, Register src) {
7185 emit_int8(0x0F);
7186 emit_int8((unsigned char)0xAD);
7187 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7188 }
7189
7190 #else // LP64
7191
7192 void Assembler::set_byte_if_not_zero(Register dst) {
7193 int enc = prefix_and_encode(dst->encoding(), true);
7194 emit_int8(0x0F);
7195 emit_int8((unsigned char)0x95);
7196 emit_int8((unsigned char)(0xE0 | enc));
7197 }
7198
7199 // 64bit only pieces of the assembler
7200 // This should only be used by 64bit instructions that can use rip-relative
7201 // it cannot be used by instructions that want an immediate value.
7202
7203 bool Assembler::reachable(AddressLiteral adr) {
7204 int64_t disp;
7205 // None will force a 64bit literal to the code stream. Likely a placeholder
7206 // for something that will be patched later and we need to certain it will
7207 // always be reachable.
7208 if (adr.reloc() == relocInfo::none) {
7209 return false;
7210 }
7211 if (adr.reloc() == relocInfo::internal_word_type) {
7212 // This should be rip relative and easily reachable.
7213 return true;
7214 }
7215 if (adr.reloc() == relocInfo::virtual_call_type ||
7216 adr.reloc() == relocInfo::opt_virtual_call_type ||
7217 adr.reloc() == relocInfo::static_call_type ||
7218 adr.reloc() == relocInfo::static_stub_type ) {
7219 // This should be rip relative within the code cache and easily
7220 // reachable until we get huge code caches. (At which point
7221 // ic code is going to have issues).
7222 return true;
7223 }
7224 if (adr.reloc() != relocInfo::external_word_type &&
7225 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7226 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7227 adr.reloc() != relocInfo::runtime_call_type ) {
7228 return false;
7229 }
7230
7231 // Stress the correction code
7232 if (ForceUnreachable) {
7233 // Must be runtimecall reloc, see if it is in the codecache
7234 // Flipping stuff in the codecache to be unreachable causes issues
7235 // with things like inline caches where the additional instructions
7236 // are not handled.
7237 if (CodeCache::find_blob(adr._target) == NULL) {
7238 return false;
7239 }
7240 }
7241 // For external_word_type/runtime_call_type if it is reachable from where we
7242 // are now (possibly a temp buffer) and where we might end up
7243 // anywhere in the codeCache then we are always reachable.
7244 // This would have to change if we ever save/restore shared code
7245 // to be more pessimistic.
7246 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7247 if (!is_simm32(disp)) return false;
7248 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7249 if (!is_simm32(disp)) return false;
7250
7251 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7252
7253 // Because rip relative is a disp + address_of_next_instruction and we
7254 // don't know the value of address_of_next_instruction we apply a fudge factor
7255 // to make sure we will be ok no matter the size of the instruction we get placed into.
7256 // We don't have to fudge the checks above here because they are already worst case.
7257
7258 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7259 // + 4 because better safe than sorry.
7260 const int fudge = 12 + 4;
7261 if (disp < 0) {
7262 disp -= fudge;
7263 } else {
7264 disp += fudge;
7265 }
7266 return is_simm32(disp);
7267 }
7268
7269 // Check if the polling page is not reachable from the code cache using rip-relative
7270 // addressing.
7271 bool Assembler::is_polling_page_far() {
7272 intptr_t addr = (intptr_t)os::get_polling_page();
7273 return ForceUnreachable ||
7274 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7275 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7276 }
7277
7278 void Assembler::emit_data64(jlong data,
7279 relocInfo::relocType rtype,
7280 int format) {
7281 if (rtype == relocInfo::none) {
7282 emit_int64(data);
7283 } else {
7284 emit_data64(data, Relocation::spec_simple(rtype), format);
7285 }
7286 }
7287
7288 void Assembler::emit_data64(jlong data,
7289 RelocationHolder const& rspec,
7290 int format) {
7291 assert(imm_operand == 0, "default format must be immediate in this file");
7292 assert(imm_operand == format, "must be immediate");
7293 assert(inst_mark() != NULL, "must be inside InstructionMark");
7294 // Do not use AbstractAssembler::relocate, which is not intended for
7295 // embedded words. Instead, relocate to the enclosing instruction.
7296 code_section()->relocate(inst_mark(), rspec, format);
7297 #ifdef ASSERT
7298 check_relocation(rspec, format);
7299 #endif
7300 emit_int64(data);
7301 }
7302
7303 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7304 if (reg_enc >= 8) {
7305 prefix(REX_B);
7306 reg_enc -= 8;
7307 } else if (byteinst && reg_enc >= 4) {
7308 prefix(REX);
7309 }
7310 return reg_enc;
7311 }
7312
7313 int Assembler::prefixq_and_encode(int reg_enc) {
7314 if (reg_enc < 8) {
7315 prefix(REX_W);
7316 } else {
7317 prefix(REX_WB);
7318 reg_enc -= 8;
7319 }
7320 return reg_enc;
7321 }
7322
7323 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7324 if (dst_enc < 8) {
7325 if (src_enc >= 8) {
7326 prefix(REX_B);
7327 src_enc -= 8;
7328 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7329 prefix(REX);
7330 }
7331 } else {
7332 if (src_enc < 8) {
7333 prefix(REX_R);
7334 } else {
7335 prefix(REX_RB);
7336 src_enc -= 8;
7337 }
7338 dst_enc -= 8;
7339 }
7340 return dst_enc << 3 | src_enc;
7341 }
7342
7343 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7344 if (dst_enc < 8) {
7345 if (src_enc < 8) {
7346 prefix(REX_W);
7347 } else {
7348 prefix(REX_WB);
7349 src_enc -= 8;
7350 }
7351 } else {
7352 if (src_enc < 8) {
7353 prefix(REX_WR);
7354 } else {
7355 prefix(REX_WRB);
7356 src_enc -= 8;
7357 }
7358 dst_enc -= 8;
7359 }
7360 return dst_enc << 3 | src_enc;
7361 }
7362
7363 void Assembler::prefix(Register reg) {
7364 if (reg->encoding() >= 8) {
7365 prefix(REX_B);
7366 }
7367 }
7368
7369 void Assembler::prefix(Register dst, Register src, Prefix p) {
7370 if (src->encoding() >= 8) {
7371 p = (Prefix)(p | REX_B);
7372 }
7373 if (dst->encoding() >= 8) {
7374 p = (Prefix)( p | REX_R);
7375 }
7376 if (p != Prefix_EMPTY) {
7377 // do not generate an empty prefix
7378 prefix(p);
7379 }
7380 }
7381
7382 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7383 if (adr.base_needs_rex()) {
7384 if (adr.index_needs_rex()) {
7385 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7386 } else {
7387 prefix(REX_B);
7388 }
7389 } else {
7390 if (adr.index_needs_rex()) {
7391 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7392 }
7393 }
7394 if (dst->encoding() >= 8) {
7395 p = (Prefix)(p | REX_R);
7396 }
7397 if (p != Prefix_EMPTY) {
7398 // do not generate an empty prefix
7399 prefix(p);
7400 }
7401 }
7402
7403 void Assembler::prefix(Address adr) {
7404 if (adr.base_needs_rex()) {
7405 if (adr.index_needs_rex()) {
7406 prefix(REX_XB);
7407 } else {
7408 prefix(REX_B);
7409 }
7410 } else {
7411 if (adr.index_needs_rex()) {
7412 prefix(REX_X);
7413 }
7414 }
7415 }
7416
7417 void Assembler::prefixq(Address adr) {
7418 if (adr.base_needs_rex()) {
7419 if (adr.index_needs_rex()) {
7420 prefix(REX_WXB);
7421 } else {
7422 prefix(REX_WB);
7423 }
7424 } else {
7425 if (adr.index_needs_rex()) {
7426 prefix(REX_WX);
7427 } else {
7428 prefix(REX_W);
7429 }
7430 }
7431 }
7432
7433
7434 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7435 if (reg->encoding() < 8) {
7436 if (adr.base_needs_rex()) {
7437 if (adr.index_needs_rex()) {
7438 prefix(REX_XB);
7439 } else {
7440 prefix(REX_B);
7441 }
7442 } else {
7443 if (adr.index_needs_rex()) {
7444 prefix(REX_X);
7445 } else if (byteinst && reg->encoding() >= 4 ) {
7446 prefix(REX);
7447 }
7448 }
7449 } else {
7450 if (adr.base_needs_rex()) {
7451 if (adr.index_needs_rex()) {
7452 prefix(REX_RXB);
7453 } else {
7454 prefix(REX_RB);
7455 }
7456 } else {
7457 if (adr.index_needs_rex()) {
7458 prefix(REX_RX);
7459 } else {
7460 prefix(REX_R);
7461 }
7462 }
7463 }
7464 }
7465
7466 void Assembler::prefixq(Address adr, Register src) {
7467 if (src->encoding() < 8) {
7468 if (adr.base_needs_rex()) {
7469 if (adr.index_needs_rex()) {
7470 prefix(REX_WXB);
7471 } else {
7472 prefix(REX_WB);
7473 }
7474 } else {
7475 if (adr.index_needs_rex()) {
7476 prefix(REX_WX);
7477 } else {
7478 prefix(REX_W);
7479 }
7480 }
7481 } else {
7482 if (adr.base_needs_rex()) {
7483 if (adr.index_needs_rex()) {
7484 prefix(REX_WRXB);
7485 } else {
7486 prefix(REX_WRB);
7487 }
7488 } else {
7489 if (adr.index_needs_rex()) {
7490 prefix(REX_WRX);
7491 } else {
7492 prefix(REX_WR);
7493 }
7494 }
7495 }
7496 }
7497
7498 void Assembler::prefix(Address adr, XMMRegister reg) {
7499 if (reg->encoding() < 8) {
7500 if (adr.base_needs_rex()) {
7501 if (adr.index_needs_rex()) {
7502 prefix(REX_XB);
7503 } else {
7504 prefix(REX_B);
7505 }
7506 } else {
7507 if (adr.index_needs_rex()) {
7508 prefix(REX_X);
7509 }
7510 }
7511 } else {
7512 if (adr.base_needs_rex()) {
7513 if (adr.index_needs_rex()) {
7514 prefix(REX_RXB);
7515 } else {
7516 prefix(REX_RB);
7517 }
7518 } else {
7519 if (adr.index_needs_rex()) {
7520 prefix(REX_RX);
7521 } else {
7522 prefix(REX_R);
7523 }
7524 }
7525 }
7526 }
7527
7528 void Assembler::prefixq(Address adr, XMMRegister src) {
7529 if (src->encoding() < 8) {
7530 if (adr.base_needs_rex()) {
7531 if (adr.index_needs_rex()) {
7532 prefix(REX_WXB);
7533 } else {
7534 prefix(REX_WB);
7535 }
7536 } else {
7537 if (adr.index_needs_rex()) {
7538 prefix(REX_WX);
7539 } else {
7540 prefix(REX_W);
7541 }
7542 }
7543 } else {
7544 if (adr.base_needs_rex()) {
7545 if (adr.index_needs_rex()) {
7546 prefix(REX_WRXB);
7547 } else {
7548 prefix(REX_WRB);
7549 }
7550 } else {
7551 if (adr.index_needs_rex()) {
7552 prefix(REX_WRX);
7553 } else {
7554 prefix(REX_WR);
7555 }
7556 }
7557 }
7558 }
7559
7560 void Assembler::adcq(Register dst, int32_t imm32) {
7561 (void) prefixq_and_encode(dst->encoding());
7562 emit_arith(0x81, 0xD0, dst, imm32);
7563 }
7564
7565 void Assembler::adcq(Register dst, Address src) {
7566 InstructionMark im(this);
7567 prefixq(src, dst);
7568 emit_int8(0x13);
7569 emit_operand(dst, src);
7570 }
7571
7572 void Assembler::adcq(Register dst, Register src) {
7573 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7574 emit_arith(0x13, 0xC0, dst, src);
7575 }
7576
7577 void Assembler::addq(Address dst, int32_t imm32) {
7578 InstructionMark im(this);
7579 prefixq(dst);
7580 emit_arith_operand(0x81, rax, dst,imm32);
7581 }
7582
7583 void Assembler::addq(Address dst, Register src) {
7584 InstructionMark im(this);
7585 prefixq(dst, src);
7586 emit_int8(0x01);
7587 emit_operand(src, dst);
7588 }
7589
7590 void Assembler::addq(Register dst, int32_t imm32) {
7591 (void) prefixq_and_encode(dst->encoding());
7592 emit_arith(0x81, 0xC0, dst, imm32);
7593 }
7594
7595 void Assembler::addq(Register dst, Address src) {
7596 InstructionMark im(this);
7597 prefixq(src, dst);
7598 emit_int8(0x03);
7599 emit_operand(dst, src);
7600 }
7601
7602 void Assembler::addq(Register dst, Register src) {
7603 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7604 emit_arith(0x03, 0xC0, dst, src);
7605 }
7606
7607 void Assembler::adcxq(Register dst, Register src) {
7608 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7609 emit_int8((unsigned char)0x66);
7610 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7611 emit_int8(0x0F);
7612 emit_int8(0x38);
7613 emit_int8((unsigned char)0xF6);
7614 emit_int8((unsigned char)(0xC0 | encode));
7615 }
7616
7617 void Assembler::adoxq(Register dst, Register src) {
7618 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7619 emit_int8((unsigned char)0xF3);
7620 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7621 emit_int8(0x0F);
7622 emit_int8(0x38);
7623 emit_int8((unsigned char)0xF6);
7624 emit_int8((unsigned char)(0xC0 | encode));
7625 }
7626
7627 void Assembler::andq(Address dst, int32_t imm32) {
7628 InstructionMark im(this);
7629 prefixq(dst);
7630 emit_int8((unsigned char)0x81);
7631 emit_operand(rsp, dst, 4);
7632 emit_int32(imm32);
7633 }
7634
7635 void Assembler::andq(Register dst, int32_t imm32) {
7636 (void) prefixq_and_encode(dst->encoding());
7637 emit_arith(0x81, 0xE0, dst, imm32);
7638 }
7639
7640 void Assembler::andq(Register dst, Address src) {
7641 InstructionMark im(this);
7642 prefixq(src, dst);
7643 emit_int8(0x23);
7644 emit_operand(dst, src);
7645 }
7646
7647 void Assembler::andq(Register dst, Register src) {
7648 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7649 emit_arith(0x23, 0xC0, dst, src);
7650 }
7651
7652 void Assembler::andnq(Register dst, Register src1, Register src2) {
7653 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7654 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7655 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7656 emit_int8((unsigned char)0xF2);
7657 emit_int8((unsigned char)(0xC0 | encode));
7658 }
7659
7660 void Assembler::andnq(Register dst, Register src1, Address src2) {
7661 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7662 InstructionMark im(this);
7663 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7664 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7665 emit_int8((unsigned char)0xF2);
7666 emit_operand(dst, src2);
7667 }
7668
7669 void Assembler::bsfq(Register dst, Register src) {
7670 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7671 emit_int8(0x0F);
7672 emit_int8((unsigned char)0xBC);
7673 emit_int8((unsigned char)(0xC0 | encode));
7674 }
7675
7676 void Assembler::bsrq(Register dst, Register src) {
7677 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7678 emit_int8(0x0F);
7679 emit_int8((unsigned char)0xBD);
7680 emit_int8((unsigned char)(0xC0 | encode));
7681 }
7682
7683 void Assembler::bswapq(Register reg) {
7684 int encode = prefixq_and_encode(reg->encoding());
7685 emit_int8(0x0F);
7686 emit_int8((unsigned char)(0xC8 | encode));
7687 }
7688
7689 void Assembler::blsiq(Register dst, Register src) {
7690 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7691 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7692 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7693 emit_int8((unsigned char)0xF3);
7694 emit_int8((unsigned char)(0xC0 | encode));
7695 }
7696
7697 void Assembler::blsiq(Register dst, Address src) {
7698 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7699 InstructionMark im(this);
7700 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7701 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7702 emit_int8((unsigned char)0xF3);
7703 emit_operand(rbx, src);
7704 }
7705
7706 void Assembler::blsmskq(Register dst, Register src) {
7707 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7708 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7709 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7710 emit_int8((unsigned char)0xF3);
7711 emit_int8((unsigned char)(0xC0 | encode));
7712 }
7713
7714 void Assembler::blsmskq(Register dst, Address src) {
7715 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7716 InstructionMark im(this);
7717 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7718 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7719 emit_int8((unsigned char)0xF3);
7720 emit_operand(rdx, src);
7721 }
7722
7723 void Assembler::blsrq(Register dst, Register src) {
7724 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7725 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7726 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7727 emit_int8((unsigned char)0xF3);
7728 emit_int8((unsigned char)(0xC0 | encode));
7729 }
7730
7731 void Assembler::blsrq(Register dst, Address src) {
7732 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7733 InstructionMark im(this);
7734 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7735 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7736 emit_int8((unsigned char)0xF3);
7737 emit_operand(rcx, src);
7738 }
7739
7740 void Assembler::cdqq() {
7741 prefix(REX_W);
7742 emit_int8((unsigned char)0x99);
7743 }
7744
7745 void Assembler::clflush(Address adr) {
7746 prefix(adr);
7747 emit_int8(0x0F);
7748 emit_int8((unsigned char)0xAE);
7749 emit_operand(rdi, adr);
7750 }
7751
7752 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7753 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7754 emit_int8(0x0F);
7755 emit_int8(0x40 | cc);
7756 emit_int8((unsigned char)(0xC0 | encode));
7757 }
7758
7759 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7760 InstructionMark im(this);
7761 prefixq(src, dst);
7762 emit_int8(0x0F);
7763 emit_int8(0x40 | cc);
7764 emit_operand(dst, src);
7765 }
7766
7767 void Assembler::cmpq(Address dst, int32_t imm32) {
7768 InstructionMark im(this);
7769 prefixq(dst);
7770 emit_int8((unsigned char)0x81);
7771 emit_operand(rdi, dst, 4);
7772 emit_int32(imm32);
7773 }
7774
7775 void Assembler::cmpq(Register dst, int32_t imm32) {
7776 (void) prefixq_and_encode(dst->encoding());
7777 emit_arith(0x81, 0xF8, dst, imm32);
7778 }
7779
7780 void Assembler::cmpq(Address dst, Register src) {
7781 InstructionMark im(this);
7782 prefixq(dst, src);
7783 emit_int8(0x3B);
7784 emit_operand(src, dst);
7785 }
7786
7787 void Assembler::cmpq(Register dst, Register src) {
7788 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7789 emit_arith(0x3B, 0xC0, dst, src);
7790 }
7791
7792 void Assembler::cmpq(Register dst, Address src) {
7793 InstructionMark im(this);
7794 prefixq(src, dst);
7795 emit_int8(0x3B);
7796 emit_operand(dst, src);
7797 }
7798
7799 void Assembler::cmpxchgq(Register reg, Address adr) {
7800 InstructionMark im(this);
7801 prefixq(adr, reg);
7802 emit_int8(0x0F);
7803 emit_int8((unsigned char)0xB1);
7804 emit_operand(reg, adr);
7805 }
7806
7807 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7808 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7809 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7810 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7811 emit_int8(0x2A);
7812 emit_int8((unsigned char)(0xC0 | encode));
7813 }
7814
7815 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7816 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7817 InstructionMark im(this);
7818 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7819 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7820 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7821 emit_int8(0x2A);
7822 emit_operand(dst, src);
7823 }
7824
7825 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7826 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7827 InstructionMark im(this);
7828 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7829 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7830 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7831 emit_int8(0x2A);
7832 emit_operand(dst, src);
7833 }
7834
7835 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7837 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7838 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7839 emit_int8(0x2C);
7840 emit_int8((unsigned char)(0xC0 | encode));
7841 }
7842
7843 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7844 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7845 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7846 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7847 emit_int8(0x2C);
7848 emit_int8((unsigned char)(0xC0 | encode));
7849 }
7850
7851 void Assembler::decl(Register dst) {
7852 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7853 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7854 int encode = prefix_and_encode(dst->encoding());
7855 emit_int8((unsigned char)0xFF);
7856 emit_int8((unsigned char)(0xC8 | encode));
7857 }
7858
7859 void Assembler::decq(Register dst) {
7860 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7861 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7862 int encode = prefixq_and_encode(dst->encoding());
7863 emit_int8((unsigned char)0xFF);
7864 emit_int8(0xC8 | encode);
7865 }
7866
7867 void Assembler::decq(Address dst) {
7868 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7869 InstructionMark im(this);
7870 prefixq(dst);
7871 emit_int8((unsigned char)0xFF);
7872 emit_operand(rcx, dst);
7873 }
7874
7875 void Assembler::fxrstor(Address src) {
7876 prefixq(src);
7877 emit_int8(0x0F);
7878 emit_int8((unsigned char)0xAE);
7879 emit_operand(as_Register(1), src);
7880 }
7881
7882 void Assembler::xrstor(Address src) {
7883 prefixq(src);
7884 emit_int8(0x0F);
7885 emit_int8((unsigned char)0xAE);
7886 emit_operand(as_Register(5), src);
7887 }
7888
7889 void Assembler::fxsave(Address dst) {
7890 prefixq(dst);
7891 emit_int8(0x0F);
7892 emit_int8((unsigned char)0xAE);
7893 emit_operand(as_Register(0), dst);
7894 }
7895
7896 void Assembler::xsave(Address dst) {
7897 prefixq(dst);
7898 emit_int8(0x0F);
7899 emit_int8((unsigned char)0xAE);
7900 emit_operand(as_Register(4), dst);
7901 }
7902
7903 void Assembler::idivq(Register src) {
7904 int encode = prefixq_and_encode(src->encoding());
7905 emit_int8((unsigned char)0xF7);
7906 emit_int8((unsigned char)(0xF8 | encode));
7907 }
7908
7909 void Assembler::imulq(Register dst, Register src) {
7910 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7911 emit_int8(0x0F);
7912 emit_int8((unsigned char)0xAF);
7913 emit_int8((unsigned char)(0xC0 | encode));
7914 }
7915
7916 void Assembler::imulq(Register dst, Register src, int value) {
7917 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7918 if (is8bit(value)) {
7919 emit_int8(0x6B);
7920 emit_int8((unsigned char)(0xC0 | encode));
7921 emit_int8(value & 0xFF);
7922 } else {
7923 emit_int8(0x69);
7924 emit_int8((unsigned char)(0xC0 | encode));
7925 emit_int32(value);
7926 }
7927 }
7928
7929 void Assembler::imulq(Register dst, Address src) {
7930 InstructionMark im(this);
7931 prefixq(src, dst);
7932 emit_int8(0x0F);
7933 emit_int8((unsigned char) 0xAF);
7934 emit_operand(dst, src);
7935 }
7936
7937 void Assembler::incl(Register dst) {
7938 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7939 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7940 int encode = prefix_and_encode(dst->encoding());
7941 emit_int8((unsigned char)0xFF);
7942 emit_int8((unsigned char)(0xC0 | encode));
7943 }
7944
7945 void Assembler::incq(Register dst) {
7946 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7947 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7948 int encode = prefixq_and_encode(dst->encoding());
7949 emit_int8((unsigned char)0xFF);
7950 emit_int8((unsigned char)(0xC0 | encode));
7951 }
7952
7953 void Assembler::incq(Address dst) {
7954 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7955 InstructionMark im(this);
7956 prefixq(dst);
7957 emit_int8((unsigned char)0xFF);
7958 emit_operand(rax, dst);
7959 }
7960
7961 void Assembler::lea(Register dst, Address src) {
7962 leaq(dst, src);
7963 }
7964
7965 void Assembler::leaq(Register dst, Address src) {
7966 InstructionMark im(this);
7967 prefixq(src, dst);
7968 emit_int8((unsigned char)0x8D);
7969 emit_operand(dst, src);
7970 }
7971
7972 void Assembler::mov64(Register dst, int64_t imm64) {
7973 InstructionMark im(this);
7974 int encode = prefixq_and_encode(dst->encoding());
7975 emit_int8((unsigned char)(0xB8 | encode));
7976 emit_int64(imm64);
7977 }
7978
7979 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7980 InstructionMark im(this);
7981 int encode = prefixq_and_encode(dst->encoding());
7982 emit_int8(0xB8 | encode);
7983 emit_data64(imm64, rspec);
7984 }
7985
7986 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7987 InstructionMark im(this);
7988 int encode = prefix_and_encode(dst->encoding());
7989 emit_int8((unsigned char)(0xB8 | encode));
7990 emit_data((int)imm32, rspec, narrow_oop_operand);
7991 }
7992
7993 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7994 InstructionMark im(this);
7995 prefix(dst);
7996 emit_int8((unsigned char)0xC7);
7997 emit_operand(rax, dst, 4);
7998 emit_data((int)imm32, rspec, narrow_oop_operand);
7999 }
8000
8001 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8002 InstructionMark im(this);
8003 int encode = prefix_and_encode(src1->encoding());
8004 emit_int8((unsigned char)0x81);
8005 emit_int8((unsigned char)(0xF8 | encode));
8006 emit_data((int)imm32, rspec, narrow_oop_operand);
8007 }
8008
8009 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8010 InstructionMark im(this);
8011 prefix(src1);
8012 emit_int8((unsigned char)0x81);
8013 emit_operand(rax, src1, 4);
8014 emit_data((int)imm32, rspec, narrow_oop_operand);
8015 }
8016
8017 void Assembler::lzcntq(Register dst, Register src) {
8018 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8019 emit_int8((unsigned char)0xF3);
8020 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8021 emit_int8(0x0F);
8022 emit_int8((unsigned char)0xBD);
8023 emit_int8((unsigned char)(0xC0 | encode));
8024 }
8025
8026 void Assembler::movdq(XMMRegister dst, Register src) {
8027 // table D-1 says MMX/SSE2
8028 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8029 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8030 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8031 emit_int8(0x6E);
8032 emit_int8((unsigned char)(0xC0 | encode));
8033 }
8034
8035 void Assembler::movdq(Register dst, XMMRegister src) {
8036 // table D-1 says MMX/SSE2
8037 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8038 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8039 // swap src/dst to get correct prefix
8040 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8041 emit_int8(0x7E);
8042 emit_int8((unsigned char)(0xC0 | encode));
8043 }
8044
8045 void Assembler::movq(Register dst, Register src) {
8046 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8047 emit_int8((unsigned char)0x8B);
8048 emit_int8((unsigned char)(0xC0 | encode));
8049 }
8050
8051 void Assembler::movq(Register dst, Address src) {
8052 InstructionMark im(this);
8053 prefixq(src, dst);
8054 emit_int8((unsigned char)0x8B);
8055 emit_operand(dst, src);
8056 }
8057
8058 void Assembler::movq(Address dst, Register src) {
8059 InstructionMark im(this);
8060 prefixq(dst, src);
8061 emit_int8((unsigned char)0x89);
8062 emit_operand(src, dst);
8063 }
8064
8065 void Assembler::movsbq(Register dst, Address src) {
8066 InstructionMark im(this);
8067 prefixq(src, dst);
8068 emit_int8(0x0F);
8069 emit_int8((unsigned char)0xBE);
8070 emit_operand(dst, src);
8071 }
8072
8073 void Assembler::movsbq(Register dst, Register src) {
8074 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8075 emit_int8(0x0F);
8076 emit_int8((unsigned char)0xBE);
8077 emit_int8((unsigned char)(0xC0 | encode));
8078 }
8079
8080 void Assembler::movslq(Register dst, int32_t imm32) {
8081 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8082 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8083 // as a result we shouldn't use until tested at runtime...
8084 ShouldNotReachHere();
8085 InstructionMark im(this);
8086 int encode = prefixq_and_encode(dst->encoding());
8087 emit_int8((unsigned char)(0xC7 | encode));
8088 emit_int32(imm32);
8089 }
8090
8091 void Assembler::movslq(Address dst, int32_t imm32) {
8092 assert(is_simm32(imm32), "lost bits");
8093 InstructionMark im(this);
8094 prefixq(dst);
8095 emit_int8((unsigned char)0xC7);
8096 emit_operand(rax, dst, 4);
8097 emit_int32(imm32);
8098 }
8099
8100 void Assembler::movslq(Register dst, Address src) {
8101 InstructionMark im(this);
8102 prefixq(src, dst);
8103 emit_int8(0x63);
8104 emit_operand(dst, src);
8105 }
8106
8107 void Assembler::movslq(Register dst, Register src) {
8108 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8109 emit_int8(0x63);
8110 emit_int8((unsigned char)(0xC0 | encode));
8111 }
8112
8113 void Assembler::movswq(Register dst, Address src) {
8114 InstructionMark im(this);
8115 prefixq(src, dst);
8116 emit_int8(0x0F);
8117 emit_int8((unsigned char)0xBF);
8118 emit_operand(dst, src);
8119 }
8120
8121 void Assembler::movswq(Register dst, Register src) {
8122 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8123 emit_int8((unsigned char)0x0F);
8124 emit_int8((unsigned char)0xBF);
8125 emit_int8((unsigned char)(0xC0 | encode));
8126 }
8127
8128 void Assembler::movzbq(Register dst, Address src) {
8129 InstructionMark im(this);
8130 prefixq(src, dst);
8131 emit_int8((unsigned char)0x0F);
8132 emit_int8((unsigned char)0xB6);
8133 emit_operand(dst, src);
8134 }
8135
8136 void Assembler::movzbq(Register dst, Register src) {
8137 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8138 emit_int8(0x0F);
8139 emit_int8((unsigned char)0xB6);
8140 emit_int8(0xC0 | encode);
8141 }
8142
8143 void Assembler::movzwq(Register dst, Address src) {
8144 InstructionMark im(this);
8145 prefixq(src, dst);
8146 emit_int8((unsigned char)0x0F);
8147 emit_int8((unsigned char)0xB7);
8148 emit_operand(dst, src);
8149 }
8150
8151 void Assembler::movzwq(Register dst, Register src) {
8152 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8153 emit_int8((unsigned char)0x0F);
8154 emit_int8((unsigned char)0xB7);
8155 emit_int8((unsigned char)(0xC0 | encode));
8156 }
8157
8158 void Assembler::mulq(Address src) {
8159 InstructionMark im(this);
8160 prefixq(src);
8161 emit_int8((unsigned char)0xF7);
8162 emit_operand(rsp, src);
8163 }
8164
8165 void Assembler::mulq(Register src) {
8166 int encode = prefixq_and_encode(src->encoding());
8167 emit_int8((unsigned char)0xF7);
8168 emit_int8((unsigned char)(0xE0 | encode));
8169 }
8170
8171 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8172 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8173 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8174 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8175 emit_int8((unsigned char)0xF6);
8176 emit_int8((unsigned char)(0xC0 | encode));
8177 }
8178
8179 void Assembler::negq(Register dst) {
8180 int encode = prefixq_and_encode(dst->encoding());
8181 emit_int8((unsigned char)0xF7);
8182 emit_int8((unsigned char)(0xD8 | encode));
8183 }
8184
8185 void Assembler::notq(Register dst) {
8186 int encode = prefixq_and_encode(dst->encoding());
8187 emit_int8((unsigned char)0xF7);
8188 emit_int8((unsigned char)(0xD0 | encode));
8189 }
8190
8191 void Assembler::orq(Address dst, int32_t imm32) {
8192 InstructionMark im(this);
8193 prefixq(dst);
8194 emit_int8((unsigned char)0x81);
8195 emit_operand(rcx, dst, 4);
8196 emit_int32(imm32);
8197 }
8198
8199 void Assembler::orq(Register dst, int32_t imm32) {
8200 (void) prefixq_and_encode(dst->encoding());
8201 emit_arith(0x81, 0xC8, dst, imm32);
8202 }
8203
8204 void Assembler::orq(Register dst, Address src) {
8205 InstructionMark im(this);
8206 prefixq(src, dst);
8207 emit_int8(0x0B);
8208 emit_operand(dst, src);
8209 }
8210
8211 void Assembler::orq(Register dst, Register src) {
8212 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8213 emit_arith(0x0B, 0xC0, dst, src);
8214 }
8215
8216 void Assembler::popa() { // 64bit
8217 movq(r15, Address(rsp, 0));
8218 movq(r14, Address(rsp, wordSize));
8219 movq(r13, Address(rsp, 2 * wordSize));
8220 movq(r12, Address(rsp, 3 * wordSize));
8221 movq(r11, Address(rsp, 4 * wordSize));
8222 movq(r10, Address(rsp, 5 * wordSize));
8223 movq(r9, Address(rsp, 6 * wordSize));
8224 movq(r8, Address(rsp, 7 * wordSize));
8225 movq(rdi, Address(rsp, 8 * wordSize));
8226 movq(rsi, Address(rsp, 9 * wordSize));
8227 movq(rbp, Address(rsp, 10 * wordSize));
8228 // skip rsp
8229 movq(rbx, Address(rsp, 12 * wordSize));
8230 movq(rdx, Address(rsp, 13 * wordSize));
8231 movq(rcx, Address(rsp, 14 * wordSize));
8232 movq(rax, Address(rsp, 15 * wordSize));
8233
8234 addq(rsp, 16 * wordSize);
8235 }
8236
8237 void Assembler::popcntq(Register dst, Address src) {
8238 assert(VM_Version::supports_popcnt(), "must support");
8239 InstructionMark im(this);
8240 emit_int8((unsigned char)0xF3);
8241 prefixq(src, dst);
8242 emit_int8((unsigned char)0x0F);
8243 emit_int8((unsigned char)0xB8);
8244 emit_operand(dst, src);
8245 }
8246
8247 void Assembler::popcntq(Register dst, Register src) {
8248 assert(VM_Version::supports_popcnt(), "must support");
8249 emit_int8((unsigned char)0xF3);
8250 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8251 emit_int8((unsigned char)0x0F);
8252 emit_int8((unsigned char)0xB8);
8253 emit_int8((unsigned char)(0xC0 | encode));
8254 }
8255
8256 void Assembler::popq(Address dst) {
8257 InstructionMark im(this);
8258 prefixq(dst);
8259 emit_int8((unsigned char)0x8F);
8260 emit_operand(rax, dst);
8261 }
8262
8263 void Assembler::pusha() { // 64bit
8264 // we have to store original rsp. ABI says that 128 bytes
8265 // below rsp are local scratch.
8266 movq(Address(rsp, -5 * wordSize), rsp);
8267
8268 subq(rsp, 16 * wordSize);
8269
8270 movq(Address(rsp, 15 * wordSize), rax);
8271 movq(Address(rsp, 14 * wordSize), rcx);
8272 movq(Address(rsp, 13 * wordSize), rdx);
8273 movq(Address(rsp, 12 * wordSize), rbx);
8274 // skip rsp
8275 movq(Address(rsp, 10 * wordSize), rbp);
8276 movq(Address(rsp, 9 * wordSize), rsi);
8277 movq(Address(rsp, 8 * wordSize), rdi);
8278 movq(Address(rsp, 7 * wordSize), r8);
8279 movq(Address(rsp, 6 * wordSize), r9);
8280 movq(Address(rsp, 5 * wordSize), r10);
8281 movq(Address(rsp, 4 * wordSize), r11);
8282 movq(Address(rsp, 3 * wordSize), r12);
8283 movq(Address(rsp, 2 * wordSize), r13);
8284 movq(Address(rsp, wordSize), r14);
8285 movq(Address(rsp, 0), r15);
8286 }
8287
8288 void Assembler::pushq(Address src) {
8289 InstructionMark im(this);
8290 prefixq(src);
8291 emit_int8((unsigned char)0xFF);
8292 emit_operand(rsi, src);
8293 }
8294
8295 void Assembler::rclq(Register dst, int imm8) {
8296 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8297 int encode = prefixq_and_encode(dst->encoding());
8298 if (imm8 == 1) {
8299 emit_int8((unsigned char)0xD1);
8300 emit_int8((unsigned char)(0xD0 | encode));
8301 } else {
8302 emit_int8((unsigned char)0xC1);
8303 emit_int8((unsigned char)(0xD0 | encode));
8304 emit_int8(imm8);
8305 }
8306 }
8307
8308 void Assembler::rcrq(Register dst, int imm8) {
8309 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8310 int encode = prefixq_and_encode(dst->encoding());
8311 if (imm8 == 1) {
8312 emit_int8((unsigned char)0xD1);
8313 emit_int8((unsigned char)(0xD8 | encode));
8314 } else {
8315 emit_int8((unsigned char)0xC1);
8316 emit_int8((unsigned char)(0xD8 | encode));
8317 emit_int8(imm8);
8318 }
8319 }
8320
8321 void Assembler::rorq(Register dst, int imm8) {
8322 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8323 int encode = prefixq_and_encode(dst->encoding());
8324 if (imm8 == 1) {
8325 emit_int8((unsigned char)0xD1);
8326 emit_int8((unsigned char)(0xC8 | encode));
8327 } else {
8328 emit_int8((unsigned char)0xC1);
8329 emit_int8((unsigned char)(0xc8 | encode));
8330 emit_int8(imm8);
8331 }
8332 }
8333
8334 void Assembler::rorxq(Register dst, Register src, int imm8) {
8335 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8336 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8338 emit_int8((unsigned char)0xF0);
8339 emit_int8((unsigned char)(0xC0 | encode));
8340 emit_int8(imm8);
8341 }
8342
8343 void Assembler::sarq(Register dst, int imm8) {
8344 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8345 int encode = prefixq_and_encode(dst->encoding());
8346 if (imm8 == 1) {
8347 emit_int8((unsigned char)0xD1);
8348 emit_int8((unsigned char)(0xF8 | encode));
8349 } else {
8350 emit_int8((unsigned char)0xC1);
8351 emit_int8((unsigned char)(0xF8 | encode));
8352 emit_int8(imm8);
8353 }
8354 }
8355
8356 void Assembler::sarq(Register dst) {
8357 int encode = prefixq_and_encode(dst->encoding());
8358 emit_int8((unsigned char)0xD3);
8359 emit_int8((unsigned char)(0xF8 | encode));
8360 }
8361
8362 void Assembler::sbbq(Address dst, int32_t imm32) {
8363 InstructionMark im(this);
8364 prefixq(dst);
8365 emit_arith_operand(0x81, rbx, dst, imm32);
8366 }
8367
8368 void Assembler::sbbq(Register dst, int32_t imm32) {
8369 (void) prefixq_and_encode(dst->encoding());
8370 emit_arith(0x81, 0xD8, dst, imm32);
8371 }
8372
8373 void Assembler::sbbq(Register dst, Address src) {
8374 InstructionMark im(this);
8375 prefixq(src, dst);
8376 emit_int8(0x1B);
8377 emit_operand(dst, src);
8378 }
8379
8380 void Assembler::sbbq(Register dst, Register src) {
8381 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8382 emit_arith(0x1B, 0xC0, dst, src);
8383 }
8384
8385 void Assembler::shlq(Register dst, int imm8) {
8386 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8387 int encode = prefixq_and_encode(dst->encoding());
8388 if (imm8 == 1) {
8389 emit_int8((unsigned char)0xD1);
8390 emit_int8((unsigned char)(0xE0 | encode));
8391 } else {
8392 emit_int8((unsigned char)0xC1);
8393 emit_int8((unsigned char)(0xE0 | encode));
8394 emit_int8(imm8);
8395 }
8396 }
8397
8398 void Assembler::shlq(Register dst) {
8399 int encode = prefixq_and_encode(dst->encoding());
8400 emit_int8((unsigned char)0xD3);
8401 emit_int8((unsigned char)(0xE0 | encode));
8402 }
8403
8404 void Assembler::shrq(Register dst, int imm8) {
8405 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8406 int encode = prefixq_and_encode(dst->encoding());
8407 emit_int8((unsigned char)0xC1);
8408 emit_int8((unsigned char)(0xE8 | encode));
8409 emit_int8(imm8);
8410 }
8411
8412 void Assembler::shrq(Register dst) {
8413 int encode = prefixq_and_encode(dst->encoding());
8414 emit_int8((unsigned char)0xD3);
8415 emit_int8(0xE8 | encode);
8416 }
8417
8418 void Assembler::subq(Address dst, int32_t imm32) {
8419 InstructionMark im(this);
8420 prefixq(dst);
8421 emit_arith_operand(0x81, rbp, dst, imm32);
8422 }
8423
8424 void Assembler::subq(Address dst, Register src) {
8425 InstructionMark im(this);
8426 prefixq(dst, src);
8427 emit_int8(0x29);
8428 emit_operand(src, dst);
8429 }
8430
8431 void Assembler::subq(Register dst, int32_t imm32) {
8432 (void) prefixq_and_encode(dst->encoding());
8433 emit_arith(0x81, 0xE8, dst, imm32);
8434 }
8435
8436 // Force generation of a 4 byte immediate value even if it fits into 8bit
8437 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8438 (void) prefixq_and_encode(dst->encoding());
8439 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8440 }
8441
8442 void Assembler::subq(Register dst, Address src) {
8443 InstructionMark im(this);
8444 prefixq(src, dst);
8445 emit_int8(0x2B);
8446 emit_operand(dst, src);
8447 }
8448
8449 void Assembler::subq(Register dst, Register src) {
8450 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8451 emit_arith(0x2B, 0xC0, dst, src);
8452 }
8453
8454 void Assembler::testq(Register dst, int32_t imm32) {
8455 // not using emit_arith because test
8456 // doesn't support sign-extension of
8457 // 8bit operands
8458 int encode = dst->encoding();
8459 if (encode == 0) {
8460 prefix(REX_W);
8461 emit_int8((unsigned char)0xA9);
8462 } else {
8463 encode = prefixq_and_encode(encode);
8464 emit_int8((unsigned char)0xF7);
8465 emit_int8((unsigned char)(0xC0 | encode));
8466 }
8467 emit_int32(imm32);
8468 }
8469
8470 void Assembler::testq(Register dst, Register src) {
8471 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8472 emit_arith(0x85, 0xC0, dst, src);
8473 }
8474
8475 void Assembler::xaddq(Address dst, Register src) {
8476 InstructionMark im(this);
8477 prefixq(dst, src);
8478 emit_int8(0x0F);
8479 emit_int8((unsigned char)0xC1);
8480 emit_operand(src, dst);
8481 }
8482
8483 void Assembler::xchgq(Register dst, Address src) {
8484 InstructionMark im(this);
8485 prefixq(src, dst);
8486 emit_int8((unsigned char)0x87);
8487 emit_operand(dst, src);
8488 }
8489
8490 void Assembler::xchgq(Register dst, Register src) {
8491 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8492 emit_int8((unsigned char)0x87);
8493 emit_int8((unsigned char)(0xc0 | encode));
8494 }
8495
8496 void Assembler::xorq(Register dst, Register src) {
8497 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8498 emit_arith(0x33, 0xC0, dst, src);
8499 }
8500
8501 void Assembler::xorq(Register dst, Address src) {
8502 InstructionMark im(this);
8503 prefixq(src, dst);
8504 emit_int8(0x33);
8505 emit_operand(dst, src);
8506 }
8507
8508 #endif // !LP64