1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "logging/log.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "runtime/java.hpp" 31 #include "runtime/os.hpp" 32 #include "runtime/stubCodeGenerator.hpp" 33 #include "vm_version_x86.hpp" 34 35 36 int VM_Version::_cpu; 37 int VM_Version::_model; 38 int VM_Version::_stepping; 39 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 40 41 // Address of instruction which causes SEGV 42 address VM_Version::_cpuinfo_segv_addr = 0; 43 // Address of instruction after the one which causes SEGV 44 address VM_Version::_cpuinfo_cont_addr = 0; 45 46 static BufferBlob* stub_blob; 47 static const int stub_size = 1000; 48 49 extern "C" { 50 typedef void (*get_cpu_info_stub_t)(void*); 51 } 52 static get_cpu_info_stub_t get_cpu_info_stub = NULL; 53 54 55 class VM_Version_StubGenerator: public StubCodeGenerator { 56 public: 57 58 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 59 60 address generate_get_cpu_info() { 61 // Flags to test CPU type. 62 const uint32_t HS_EFL_AC = 0x40000; 63 const uint32_t HS_EFL_ID = 0x200000; 64 // Values for when we don't have a CPUID instruction. 65 const int CPU_FAMILY_SHIFT = 8; 66 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 67 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 68 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2); 69 70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; 71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup; 72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check; 73 74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); 75 # define __ _masm-> 76 77 address start = __ pc(); 78 79 // 80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); 81 // 82 // LP64: rcx and rdx are first and second argument registers on windows 83 84 __ push(rbp); 85 #ifdef _LP64 86 __ mov(rbp, c_rarg0); // cpuid_info address 87 #else 88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address 89 #endif 90 __ push(rbx); 91 __ push(rsi); 92 __ pushf(); // preserve rbx, and flags 93 __ pop(rax); 94 __ push(rax); 95 __ mov(rcx, rax); 96 // 97 // if we are unable to change the AC flag, we have a 386 98 // 99 __ xorl(rax, HS_EFL_AC); 100 __ push(rax); 101 __ popf(); 102 __ pushf(); 103 __ pop(rax); 104 __ cmpptr(rax, rcx); 105 __ jccb(Assembler::notEqual, detect_486); 106 107 __ movl(rax, CPU_FAMILY_386); 108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 109 __ jmp(done); 110 111 // 112 // If we are unable to change the ID flag, we have a 486 which does 113 // not support the "cpuid" instruction. 114 // 115 __ bind(detect_486); 116 __ mov(rax, rcx); 117 __ xorl(rax, HS_EFL_ID); 118 __ push(rax); 119 __ popf(); 120 __ pushf(); 121 __ pop(rax); 122 __ cmpptr(rcx, rax); 123 __ jccb(Assembler::notEqual, detect_586); 124 125 __ bind(cpu486); 126 __ movl(rax, CPU_FAMILY_486); 127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 128 __ jmp(done); 129 130 // 131 // At this point, we have a chip which supports the "cpuid" instruction 132 // 133 __ bind(detect_586); 134 __ xorl(rax, rax); 135 __ cpuid(); 136 __ orl(rax, rax); 137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input 138 // value of at least 1, we give up and 139 // assume a 486 140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); 141 __ movl(Address(rsi, 0), rax); 142 __ movl(Address(rsi, 4), rbx); 143 __ movl(Address(rsi, 8), rcx); 144 __ movl(Address(rsi,12), rdx); 145 146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? 147 __ jccb(Assembler::belowEqual, std_cpuid4); 148 149 // 150 // cpuid(0xB) Processor Topology 151 // 152 __ movl(rax, 0xb); 153 __ xorl(rcx, rcx); // Threads level 154 __ cpuid(); 155 156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); 157 __ movl(Address(rsi, 0), rax); 158 __ movl(Address(rsi, 4), rbx); 159 __ movl(Address(rsi, 8), rcx); 160 __ movl(Address(rsi,12), rdx); 161 162 __ movl(rax, 0xb); 163 __ movl(rcx, 1); // Cores level 164 __ cpuid(); 165 __ push(rax); 166 __ andl(rax, 0x1f); // Determine if valid topology level 167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 168 __ andl(rax, 0xffff); 169 __ pop(rax); 170 __ jccb(Assembler::equal, std_cpuid4); 171 172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); 173 __ movl(Address(rsi, 0), rax); 174 __ movl(Address(rsi, 4), rbx); 175 __ movl(Address(rsi, 8), rcx); 176 __ movl(Address(rsi,12), rdx); 177 178 __ movl(rax, 0xb); 179 __ movl(rcx, 2); // Packages level 180 __ cpuid(); 181 __ push(rax); 182 __ andl(rax, 0x1f); // Determine if valid topology level 183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 184 __ andl(rax, 0xffff); 185 __ pop(rax); 186 __ jccb(Assembler::equal, std_cpuid4); 187 188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); 189 __ movl(Address(rsi, 0), rax); 190 __ movl(Address(rsi, 4), rbx); 191 __ movl(Address(rsi, 8), rcx); 192 __ movl(Address(rsi,12), rdx); 193 194 // 195 // cpuid(0x4) Deterministic cache params 196 // 197 __ bind(std_cpuid4); 198 __ movl(rax, 4); 199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? 200 __ jccb(Assembler::greater, std_cpuid1); 201 202 __ xorl(rcx, rcx); // L1 cache 203 __ cpuid(); 204 __ push(rax); 205 __ andl(rax, 0x1f); // Determine if valid cache parameters used 206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache 207 __ pop(rax); 208 __ jccb(Assembler::equal, std_cpuid1); 209 210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); 211 __ movl(Address(rsi, 0), rax); 212 __ movl(Address(rsi, 4), rbx); 213 __ movl(Address(rsi, 8), rcx); 214 __ movl(Address(rsi,12), rdx); 215 216 // 217 // Standard cpuid(0x1) 218 // 219 __ bind(std_cpuid1); 220 __ movl(rax, 1); 221 __ cpuid(); 222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 223 __ movl(Address(rsi, 0), rax); 224 __ movl(Address(rsi, 4), rbx); 225 __ movl(Address(rsi, 8), rcx); 226 __ movl(Address(rsi,12), rdx); 227 228 // 229 // Check if OS has enabled XGETBV instruction to access XCR0 230 // (OSXSAVE feature flag) and CPU supports AVX 231 // 232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 233 __ cmpl(rcx, 0x18000000); 234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported 235 236 // 237 // XCR0, XFEATURE_ENABLED_MASK register 238 // 239 __ xorl(rcx, rcx); // zero for XCR0 register 240 __ xgetbv(); 241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); 242 __ movl(Address(rsi, 0), rax); 243 __ movl(Address(rsi, 4), rdx); 244 245 // 246 // cpuid(0x7) Structured Extended Features 247 // 248 __ bind(sef_cpuid); 249 __ movl(rax, 7); 250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? 251 __ jccb(Assembler::greater, ext_cpuid); 252 253 __ xorl(rcx, rcx); 254 __ cpuid(); 255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 256 __ movl(Address(rsi, 0), rax); 257 __ movl(Address(rsi, 4), rbx); 258 259 // 260 // Extended cpuid(0x80000000) 261 // 262 __ bind(ext_cpuid); 263 __ movl(rax, 0x80000000); 264 __ cpuid(); 265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? 266 __ jcc(Assembler::belowEqual, done); 267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? 268 __ jccb(Assembler::belowEqual, ext_cpuid1); 269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? 270 __ jccb(Assembler::belowEqual, ext_cpuid5); 271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? 272 __ jccb(Assembler::belowEqual, ext_cpuid7); 273 // 274 // Extended cpuid(0x80000008) 275 // 276 __ movl(rax, 0x80000008); 277 __ cpuid(); 278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); 279 __ movl(Address(rsi, 0), rax); 280 __ movl(Address(rsi, 4), rbx); 281 __ movl(Address(rsi, 8), rcx); 282 __ movl(Address(rsi,12), rdx); 283 284 // 285 // Extended cpuid(0x80000007) 286 // 287 __ bind(ext_cpuid7); 288 __ movl(rax, 0x80000007); 289 __ cpuid(); 290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); 291 __ movl(Address(rsi, 0), rax); 292 __ movl(Address(rsi, 4), rbx); 293 __ movl(Address(rsi, 8), rcx); 294 __ movl(Address(rsi,12), rdx); 295 296 // 297 // Extended cpuid(0x80000005) 298 // 299 __ bind(ext_cpuid5); 300 __ movl(rax, 0x80000005); 301 __ cpuid(); 302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); 303 __ movl(Address(rsi, 0), rax); 304 __ movl(Address(rsi, 4), rbx); 305 __ movl(Address(rsi, 8), rcx); 306 __ movl(Address(rsi,12), rdx); 307 308 // 309 // Extended cpuid(0x80000001) 310 // 311 __ bind(ext_cpuid1); 312 __ movl(rax, 0x80000001); 313 __ cpuid(); 314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); 315 __ movl(Address(rsi, 0), rax); 316 __ movl(Address(rsi, 4), rbx); 317 __ movl(Address(rsi, 8), rcx); 318 __ movl(Address(rsi,12), rdx); 319 320 // 321 // Check if OS has enabled XGETBV instruction to access XCR0 322 // (OSXSAVE feature flag) and CPU supports AVX 323 // 324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx 327 __ cmpl(rcx, 0x18000000); 328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported 329 330 __ movl(rax, 0x6); 331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 332 __ cmpl(rax, 0x6); 333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported 334 335 // we need to bridge farther than imm8, so we use this island as a thunk 336 __ bind(done); 337 __ jmp(wrapup); 338 339 __ bind(start_simd_check); 340 // 341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM 342 // registers are not restored after a signal processing. 343 // Generate SEGV here (reference through NULL) 344 // and check upper YMM/ZMM bits after it. 345 // 346 intx saved_useavx = UseAVX; 347 intx saved_usesse = UseSSE; 348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 350 __ movl(rax, 0x10000); 351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm 352 __ cmpl(rax, 0x10000); 353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 354 // check _cpuid_info.xem_xcr0_eax.bits.opmask 355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 357 __ movl(rax, 0xE0); 358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 359 __ cmpl(rax, 0xE0); 360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 361 362 // If UseAVX is unitialized or is set by the user to include EVEX 363 if (use_evex) { 364 // EVEX setup: run in lowest evex mode 365 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 366 UseAVX = 3; 367 UseSSE = 2; 368 #ifdef _WINDOWS 369 // xmm5-xmm15 are not preserved by caller on windows 370 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx 371 __ subptr(rsp, 64); 372 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit); 373 #ifdef _LP64 374 __ subptr(rsp, 64); 375 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit); 376 __ subptr(rsp, 64); 377 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit); 378 #endif // _LP64 379 #endif // _WINDOWS 380 381 // load value into all 64 bytes of zmm7 register 382 __ movl(rcx, VM_Version::ymm_test_value()); 383 __ movdl(xmm0, rcx); 384 __ movl(rcx, 0xffff); 385 __ kmovwl(k1, rcx); 386 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit); 387 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit); 388 #ifdef _LP64 389 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit); 390 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit); 391 #endif 392 VM_Version::clean_cpuFeatures(); 393 __ jmp(save_restore_except); 394 } 395 396 __ bind(legacy_setup); 397 // AVX setup 398 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 399 UseAVX = 1; 400 UseSSE = 2; 401 #ifdef _WINDOWS 402 __ subptr(rsp, 32); 403 __ vmovdqu(Address(rsp, 0), xmm7); 404 #ifdef _LP64 405 __ subptr(rsp, 32); 406 __ vmovdqu(Address(rsp, 0), xmm8); 407 __ subptr(rsp, 32); 408 __ vmovdqu(Address(rsp, 0), xmm15); 409 #endif // _LP64 410 #endif // _WINDOWS 411 412 // load value into all 32 bytes of ymm7 register 413 __ movl(rcx, VM_Version::ymm_test_value()); 414 415 __ movdl(xmm0, rcx); 416 __ pshufd(xmm0, xmm0, 0x00); 417 __ vinsertf128_high(xmm0, xmm0); 418 __ vmovdqu(xmm7, xmm0); 419 #ifdef _LP64 420 __ vmovdqu(xmm8, xmm0); 421 __ vmovdqu(xmm15, xmm0); 422 #endif 423 VM_Version::clean_cpuFeatures(); 424 425 __ bind(save_restore_except); 426 __ xorl(rsi, rsi); 427 VM_Version::set_cpuinfo_segv_addr(__ pc()); 428 // Generate SEGV 429 __ movl(rax, Address(rsi, 0)); 430 431 VM_Version::set_cpuinfo_cont_addr(__ pc()); 432 // Returns here after signal. Save xmm0 to check it later. 433 434 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 435 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 436 __ movl(rax, 0x10000); 437 __ andl(rax, Address(rsi, 4)); 438 __ cmpl(rax, 0x10000); 439 __ jccb(Assembler::notEqual, legacy_save_restore); 440 // check _cpuid_info.xem_xcr0_eax.bits.opmask 441 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 442 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 443 __ movl(rax, 0xE0); 444 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 445 __ cmpl(rax, 0xE0); 446 __ jccb(Assembler::notEqual, legacy_save_restore); 447 448 // If UseAVX is unitialized or is set by the user to include EVEX 449 if (use_evex) { 450 // EVEX check: run in lowest evex mode 451 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 452 UseAVX = 3; 453 UseSSE = 2; 454 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset()))); 455 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit); 456 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit); 457 #ifdef _LP64 458 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit); 459 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit); 460 #endif 461 462 #ifdef _WINDOWS 463 #ifdef _LP64 464 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit); 465 __ addptr(rsp, 64); 466 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit); 467 __ addptr(rsp, 64); 468 #endif // _LP64 469 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit); 470 __ addptr(rsp, 64); 471 #endif // _WINDOWS 472 VM_Version::clean_cpuFeatures(); 473 UseAVX = saved_useavx; 474 UseSSE = saved_usesse; 475 __ jmp(wrapup); 476 } 477 478 __ bind(legacy_save_restore); 479 // AVX check 480 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 481 UseAVX = 1; 482 UseSSE = 2; 483 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); 484 __ vmovdqu(Address(rsi, 0), xmm0); 485 __ vmovdqu(Address(rsi, 32), xmm7); 486 #ifdef _LP64 487 __ vmovdqu(Address(rsi, 64), xmm8); 488 __ vmovdqu(Address(rsi, 96), xmm15); 489 #endif 490 491 #ifdef _WINDOWS 492 #ifdef _LP64 493 __ vmovdqu(xmm15, Address(rsp, 0)); 494 __ addptr(rsp, 32); 495 __ vmovdqu(xmm8, Address(rsp, 0)); 496 __ addptr(rsp, 32); 497 #endif // _LP64 498 __ vmovdqu(xmm7, Address(rsp, 0)); 499 __ addptr(rsp, 32); 500 #endif // _WINDOWS 501 VM_Version::clean_cpuFeatures(); 502 UseAVX = saved_useavx; 503 UseSSE = saved_usesse; 504 505 __ bind(wrapup); 506 __ vzeroupper(); 507 __ popf(); 508 __ pop(rsi); 509 __ pop(rbx); 510 __ pop(rbp); 511 __ ret(0); 512 513 # undef __ 514 515 return start; 516 }; 517 }; 518 519 void VM_Version::get_processor_features() { 520 521 _cpu = 4; // 486 by default 522 _model = 0; 523 _stepping = 0; 524 _features = 0; 525 _logical_processors_per_package = 1; 526 // i486 internal cache is both I&D and has a 16-byte line size 527 _L1_data_cache_line_size = 16; 528 529 // Get raw processor info 530 531 get_cpu_info_stub(&_cpuid_info); 532 533 assert_is_initialized(); 534 _cpu = extended_cpu_family(); 535 _model = extended_cpu_model(); 536 _stepping = cpu_stepping(); 537 538 if (cpu_family() > 4) { // it supports CPUID 539 _features = feature_flags(); 540 // Logical processors are only available on P4s and above, 541 // and only if hyperthreading is available. 542 _logical_processors_per_package = logical_processor_count(); 543 _L1_data_cache_line_size = L1_line_size(); 544 } 545 546 _supports_cx8 = supports_cmpxchg8(); 547 // xchg and xadd instructions 548 _supports_atomic_getset4 = true; 549 _supports_atomic_getadd4 = true; 550 LP64_ONLY(_supports_atomic_getset8 = true); 551 LP64_ONLY(_supports_atomic_getadd8 = true); 552 553 #ifdef _LP64 554 // OS should support SSE for x64 and hardware should support at least SSE2. 555 if (!VM_Version::supports_sse2()) { 556 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); 557 } 558 // in 64 bit the use of SSE2 is the minimum 559 if (UseSSE < 2) UseSSE = 2; 560 #endif 561 562 #ifdef AMD64 563 // flush_icache_stub have to be generated first. 564 // That is why Icache line size is hard coded in ICache class, 565 // see icache_x86.hpp. It is also the reason why we can't use 566 // clflush instruction in 32-bit VM since it could be running 567 // on CPU which does not support it. 568 // 569 // The only thing we can do is to verify that flushed 570 // ICache::line_size has correct value. 571 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); 572 // clflush_size is size in quadwords (8 bytes). 573 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); 574 #endif 575 576 // If the OS doesn't support SSE, we can't use this feature even if the HW does 577 if (!os::supports_sse()) 578 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); 579 580 if (UseSSE < 4) { 581 _features &= ~CPU_SSE4_1; 582 _features &= ~CPU_SSE4_2; 583 } 584 585 if (UseSSE < 3) { 586 _features &= ~CPU_SSE3; 587 _features &= ~CPU_SSSE3; 588 _features &= ~CPU_SSE4A; 589 } 590 591 if (UseSSE < 2) 592 _features &= ~CPU_SSE2; 593 594 if (UseSSE < 1) 595 _features &= ~CPU_SSE; 596 597 // first try initial setting and detect what we can support 598 if (UseAVX > 0) { 599 if (UseAVX > 2 && supports_evex()) { 600 UseAVX = 3; 601 } else if (UseAVX > 1 && supports_avx2()) { 602 UseAVX = 2; 603 } else if (UseAVX > 0 && supports_avx()) { 604 UseAVX = 1; 605 } else { 606 UseAVX = 0; 607 } 608 } else if (UseAVX < 0) { 609 UseAVX = 0; 610 } 611 612 if (UseAVX < 3) { 613 _features &= ~CPU_AVX512F; 614 _features &= ~CPU_AVX512DQ; 615 _features &= ~CPU_AVX512CD; 616 _features &= ~CPU_AVX512BW; 617 _features &= ~CPU_AVX512VL; 618 } 619 620 if (UseAVX < 2) 621 _features &= ~CPU_AVX2; 622 623 if (UseAVX < 1) 624 _features &= ~CPU_AVX; 625 626 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) 627 _features &= ~CPU_AES; 628 629 if (logical_processors_per_package() == 1) { 630 // HT processor could be installed on a system which doesn't support HT. 631 _features &= ~CPU_HT; 632 } 633 634 char buf[256]; 635 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 636 cores_per_cpu(), threads_per_core(), 637 cpu_family(), _model, _stepping, 638 (supports_cmov() ? ", cmov" : ""), 639 (supports_cmpxchg8() ? ", cx8" : ""), 640 (supports_fxsr() ? ", fxsr" : ""), 641 (supports_mmx() ? ", mmx" : ""), 642 (supports_sse() ? ", sse" : ""), 643 (supports_sse2() ? ", sse2" : ""), 644 (supports_sse3() ? ", sse3" : ""), 645 (supports_ssse3()? ", ssse3": ""), 646 (supports_sse4_1() ? ", sse4.1" : ""), 647 (supports_sse4_2() ? ", sse4.2" : ""), 648 (supports_popcnt() ? ", popcnt" : ""), 649 (supports_avx() ? ", avx" : ""), 650 (supports_avx2() ? ", avx2" : ""), 651 (supports_aes() ? ", aes" : ""), 652 (supports_clmul() ? ", clmul" : ""), 653 (supports_erms() ? ", erms" : ""), 654 (supports_rtm() ? ", rtm" : ""), 655 (supports_mmx_ext() ? ", mmxext" : ""), 656 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), 657 (supports_lzcnt() ? ", lzcnt": ""), 658 (supports_sse4a() ? ", sse4a": ""), 659 (supports_ht() ? ", ht": ""), 660 (supports_tsc() ? ", tsc": ""), 661 (supports_tscinv_bit() ? ", tscinvbit": ""), 662 (supports_tscinv() ? ", tscinv": ""), 663 (supports_bmi1() ? ", bmi1" : ""), 664 (supports_bmi2() ? ", bmi2" : ""), 665 (supports_adx() ? ", adx" : ""), 666 (supports_evex() ? ", evex" : ""), 667 (supports_sha() ? ", sha" : ""), 668 (supports_fma() ? ", fma" : "")); 669 _features_string = os::strdup(buf); 670 671 // UseSSE is set to the smaller of what hardware supports and what 672 // the command line requires. I.e., you cannot set UseSSE to 2 on 673 // older Pentiums which do not support it. 674 if (UseSSE > 4) UseSSE=4; 675 if (UseSSE < 0) UseSSE=0; 676 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support 677 UseSSE = MIN2((intx)3,UseSSE); 678 if (!supports_sse3()) // Drop to 2 if no SSE3 support 679 UseSSE = MIN2((intx)2,UseSSE); 680 if (!supports_sse2()) // Drop to 1 if no SSE2 support 681 UseSSE = MIN2((intx)1,UseSSE); 682 if (!supports_sse ()) // Drop to 0 if no SSE support 683 UseSSE = 0; 684 685 // Use AES instructions if available. 686 if (supports_aes()) { 687 if (FLAG_IS_DEFAULT(UseAES)) { 688 FLAG_SET_DEFAULT(UseAES, true); 689 } 690 if (!UseAES) { 691 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 692 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 693 } 694 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 695 } else { 696 if (UseSSE > 2) { 697 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 698 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 699 } 700 } else { 701 // The AES intrinsic stubs require AES instruction support (of course) 702 // but also require sse3 mode or higher for instructions it use. 703 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 704 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled."); 705 } 706 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 707 } 708 709 // --AES-CTR begins-- 710 if (!UseAESIntrinsics) { 711 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 712 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled."); 713 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 714 } 715 } else { 716 if(supports_sse4_1()) { 717 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 718 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true); 719 } 720 } else { 721 // The AES-CTR intrinsic stubs require AES instruction support (of course) 722 // but also require sse4.1 mode or higher for instructions it use. 723 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 724 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled."); 725 } 726 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 727 } 728 } 729 // --AES-CTR ends-- 730 } 731 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) { 732 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 733 warning("AES instructions are not available on this CPU"); 734 FLAG_SET_DEFAULT(UseAES, false); 735 } 736 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 737 warning("AES intrinsics are not available on this CPU"); 738 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 739 } 740 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 741 warning("AES-CTR intrinsics are not available on this CPU"); 742 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 743 } 744 } 745 746 // Use CLMUL instructions if available. 747 if (supports_clmul()) { 748 if (FLAG_IS_DEFAULT(UseCLMUL)) { 749 UseCLMUL = true; 750 } 751 } else if (UseCLMUL) { 752 if (!FLAG_IS_DEFAULT(UseCLMUL)) 753 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); 754 FLAG_SET_DEFAULT(UseCLMUL, false); 755 } 756 757 if (UseCLMUL && (UseSSE > 2)) { 758 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 759 UseCRC32Intrinsics = true; 760 } 761 } else if (UseCRC32Intrinsics) { 762 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 763 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); 764 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 765 } 766 767 if (supports_sse4_2()) { 768 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 769 UseCRC32CIntrinsics = true; 770 } 771 } 772 else if (UseCRC32CIntrinsics) { 773 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 774 warning("CRC32C intrinsics are not available on this CPU"); 775 } 776 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 777 } 778 779 // GHASH/GCM intrinsics 780 if (UseCLMUL && (UseSSE > 2)) { 781 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 782 UseGHASHIntrinsics = true; 783 } 784 } else if (UseGHASHIntrinsics) { 785 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 786 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU"); 787 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 788 } 789 790 if (supports_fma() && UseSSE >= 2) { 791 if (FLAG_IS_DEFAULT(UseFMA)) { 792 UseFMA = true; 793 } 794 } else if (UseFMA) { 795 warning("FMA instructions are not available on this CPU"); 796 FLAG_SET_DEFAULT(UseFMA, false); 797 } 798 799 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) { 800 if (FLAG_IS_DEFAULT(UseSHA)) { 801 UseSHA = true; 802 } 803 } else if (UseSHA) { 804 warning("SHA instructions are not available on this CPU"); 805 FLAG_SET_DEFAULT(UseSHA, false); 806 } 807 808 if (supports_sha() && UseSHA) { 809 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 810 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 811 } 812 } else if (UseSHA1Intrinsics) { 813 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 814 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 815 } 816 817 if (UseSHA) { 818 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 819 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 820 } 821 } else if (UseSHA256Intrinsics) { 822 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 823 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 824 } 825 826 if (UseSHA) { 827 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 828 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 829 } 830 } else if (UseSHA512Intrinsics) { 831 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 832 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 833 } 834 835 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 836 FLAG_SET_DEFAULT(UseSHA, false); 837 } 838 839 if (UseAdler32Intrinsics) { 840 warning("Adler32Intrinsics not available on this CPU."); 841 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 842 } 843 844 if (!supports_rtm() && UseRTMLocking) { 845 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 846 // setting during arguments processing. See use_biased_locking(). 847 // VM_Version_init() is executed after UseBiasedLocking is used 848 // in Thread::allocate(). 849 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 850 } 851 852 #if INCLUDE_RTM_OPT 853 if (UseRTMLocking) { 854 if (is_client_compilation_mode_vm()) { 855 // Only C2 does RTM locking optimization. 856 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 857 // setting during arguments processing. See use_biased_locking(). 858 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM"); 859 } 860 if (is_intel_family_core()) { 861 if ((_model == CPU_MODEL_HASWELL_E3) || 862 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || 863 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) { 864 // currently a collision between SKL and HSW_E3 865 if (!UnlockExperimentalVMOptions && UseAVX < 3) { 866 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 867 } else { 868 warning("UseRTMLocking is only available as experimental option on this platform."); 869 } 870 } 871 } 872 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 873 // RTM locking should be used only for applications with 874 // high lock contention. For now we do not use it by default. 875 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 876 } 877 if (!is_power_of_2(RTMTotalCountIncrRate)) { 878 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 879 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 880 } 881 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 882 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 883 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 884 } 885 } else { // !UseRTMLocking 886 if (UseRTMForStackLocks) { 887 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 888 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 889 } 890 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 891 } 892 if (UseRTMDeopt) { 893 FLAG_SET_DEFAULT(UseRTMDeopt, false); 894 } 895 if (PrintPreciseRTMLockingStatistics) { 896 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 897 } 898 } 899 #else 900 if (UseRTMLocking) { 901 // Only C2 does RTM locking optimization. 902 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 903 // setting during arguments processing. See use_biased_locking(). 904 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 905 } 906 #endif 907 908 #ifdef COMPILER2 909 if (UseFPUForSpilling) { 910 if (UseSSE < 2) { 911 // Only supported with SSE2+ 912 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 913 } 914 } 915 #endif 916 #if defined(COMPILER2) || INCLUDE_JVMCI 917 if (MaxVectorSize > 0) { 918 if (!is_power_of_2(MaxVectorSize)) { 919 warning("MaxVectorSize must be a power of 2"); 920 FLAG_SET_DEFAULT(MaxVectorSize, 64); 921 } 922 if (UseSSE < 2) { 923 // Vectors (in XMM) are only supported with SSE2+ 924 if (MaxVectorSize > 0) { 925 if (!FLAG_IS_DEFAULT(MaxVectorSize)) 926 warning("MaxVectorSize must be 0"); 927 FLAG_SET_DEFAULT(MaxVectorSize, 0); 928 } 929 } 930 else if (UseAVX == 0 || !os_supports_avx_vectors()) { 931 // 32 bytes vectors (in YMM) are only supported with AVX+ 932 if (MaxVectorSize > 16) { 933 if (!FLAG_IS_DEFAULT(MaxVectorSize)) 934 warning("MaxVectorSize must be <= 16"); 935 FLAG_SET_DEFAULT(MaxVectorSize, 16); 936 } 937 } 938 else if (UseAVX == 1 || UseAVX == 2) { 939 // 64 bytes vectors (in ZMM) are only supported with AVX 3 940 if (MaxVectorSize > 32) { 941 if (!FLAG_IS_DEFAULT(MaxVectorSize)) 942 warning("MaxVectorSize must be <= 32"); 943 FLAG_SET_DEFAULT(MaxVectorSize, 32); 944 } 945 } 946 else if (UseAVX > 2 ) { 947 if (MaxVectorSize > 64) { 948 if (!FLAG_IS_DEFAULT(MaxVectorSize)) 949 warning("MaxVectorSize must be <= 64"); 950 FLAG_SET_DEFAULT(MaxVectorSize, 64); 951 } 952 } 953 #if defined(COMPILER2) && defined(ASSERT) 954 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { 955 tty->print_cr("State of YMM registers after signal handle:"); 956 int nreg = 2 LP64_ONLY(+2); 957 const char* ymm_name[4] = {"0", "7", "8", "15"}; 958 for (int i = 0; i < nreg; i++) { 959 tty->print("YMM%s:", ymm_name[i]); 960 for (int j = 7; j >=0; j--) { 961 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); 962 } 963 tty->cr(); 964 } 965 } 966 #endif // COMPILER2 && ASSERT 967 } 968 #endif // COMPILER2 || INCLUDE_JVMCI 969 970 #ifdef COMPILER2 971 #ifdef _LP64 972 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 973 UseMultiplyToLenIntrinsic = true; 974 } 975 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 976 UseSquareToLenIntrinsic = true; 977 } 978 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 979 UseMulAddIntrinsic = true; 980 } 981 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 982 UseMontgomeryMultiplyIntrinsic = true; 983 } 984 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 985 UseMontgomerySquareIntrinsic = true; 986 } 987 #else 988 if (UseMultiplyToLenIntrinsic) { 989 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 990 warning("multiplyToLen intrinsic is not available in 32-bit VM"); 991 } 992 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); 993 } 994 if (UseMontgomeryMultiplyIntrinsic) { 995 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 996 warning("montgomeryMultiply intrinsic is not available in 32-bit VM"); 997 } 998 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false); 999 } 1000 if (UseMontgomerySquareIntrinsic) { 1001 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 1002 warning("montgomerySquare intrinsic is not available in 32-bit VM"); 1003 } 1004 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false); 1005 } 1006 if (UseSquareToLenIntrinsic) { 1007 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 1008 warning("squareToLen intrinsic is not available in 32-bit VM"); 1009 } 1010 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false); 1011 } 1012 if (UseMulAddIntrinsic) { 1013 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 1014 warning("mulAdd intrinsic is not available in 32-bit VM"); 1015 } 1016 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false); 1017 } 1018 #endif 1019 #endif // COMPILER2 1020 1021 // On new cpus instructions which update whole XMM register should be used 1022 // to prevent partial register stall due to dependencies on high half. 1023 // 1024 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) 1025 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) 1026 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). 1027 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). 1028 1029 if( is_amd() ) { // AMD cpus specific settings 1030 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { 1031 // Use it on new AMD cpus starting from Opteron. 1032 UseAddressNop = true; 1033 } 1034 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { 1035 // Use it on new AMD cpus starting from Opteron. 1036 UseNewLongLShift = true; 1037 } 1038 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 1039 if (supports_sse4a()) { 1040 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron 1041 } else { 1042 UseXmmLoadAndClearUpper = false; 1043 } 1044 } 1045 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 1046 if( supports_sse4a() ) { 1047 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' 1048 } else { 1049 UseXmmRegToRegMoveAll = false; 1050 } 1051 } 1052 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { 1053 if( supports_sse4a() ) { 1054 UseXmmI2F = true; 1055 } else { 1056 UseXmmI2F = false; 1057 } 1058 } 1059 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { 1060 if( supports_sse4a() ) { 1061 UseXmmI2D = true; 1062 } else { 1063 UseXmmI2D = false; 1064 } 1065 } 1066 if (supports_sse4_2()) { 1067 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 1068 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); 1069 } 1070 } else { 1071 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 1072 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); 1073 } 1074 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); 1075 } 1076 1077 // some defaults for AMD family 15h 1078 if ( cpu_family() == 0x15 ) { 1079 // On family 15h processors default is no sw prefetch 1080 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 1081 AllocatePrefetchStyle = 0; 1082 } 1083 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW 1084 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 1085 AllocatePrefetchInstr = 3; 1086 } 1087 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy 1088 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 1089 UseXMMForArrayCopy = true; 1090 } 1091 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1092 UseUnalignedLoadStores = true; 1093 } 1094 } 1095 1096 #ifdef COMPILER2 1097 if (MaxVectorSize > 16) { 1098 // Limit vectors size to 16 bytes on current AMD cpus. 1099 FLAG_SET_DEFAULT(MaxVectorSize, 16); 1100 } 1101 #endif // COMPILER2 1102 } 1103 1104 if( is_intel() ) { // Intel cpus specific settings 1105 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { 1106 UseStoreImmI16 = false; // don't use it on Intel cpus 1107 } 1108 if( cpu_family() == 6 || cpu_family() == 15 ) { 1109 if( FLAG_IS_DEFAULT(UseAddressNop) ) { 1110 // Use it on all Intel cpus starting from PentiumPro 1111 UseAddressNop = true; 1112 } 1113 } 1114 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 1115 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus 1116 } 1117 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 1118 if( supports_sse3() ) { 1119 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus 1120 } else { 1121 UseXmmRegToRegMoveAll = false; 1122 } 1123 } 1124 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus 1125 #ifdef COMPILER2 1126 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { 1127 // For new Intel cpus do the next optimization: 1128 // don't align the beginning of a loop if there are enough instructions 1129 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) 1130 // in current fetch line (OptoLoopAlignment) or the padding 1131 // is big (> MaxLoopPad). 1132 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of 1133 // generated NOP instructions. 11 is the largest size of one 1134 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 1135 MaxLoopPad = 11; 1136 } 1137 #endif // COMPILER2 1138 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 1139 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus 1140 } 1141 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus 1142 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1143 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 1144 } 1145 } 1146 if (supports_sse4_2()) { 1147 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 1148 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); 1149 } 1150 } else { 1151 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 1152 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); 1153 } 1154 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); 1155 } 1156 } 1157 if ((cpu_family() == 0x06) && 1158 ((extended_cpu_model() == 0x36) || // Centerton 1159 (extended_cpu_model() == 0x37) || // Silvermont 1160 (extended_cpu_model() == 0x4D))) { 1161 #ifdef COMPILER2 1162 if (FLAG_IS_DEFAULT(OptoScheduling)) { 1163 OptoScheduling = true; 1164 } 1165 #endif 1166 if (supports_sse4_2()) { // Silvermont 1167 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1168 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 1169 } 1170 } 1171 } 1172 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { 1173 AllocatePrefetchInstr = 3; 1174 } 1175 if ((cpu_family() == 0x06) && 1176 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200 1177 (extended_cpu_model() == 0x85))) { // Future Xeon Phi 1178 if (FLAG_IS_DEFAULT(UseVzeroupper)) { 1179 FLAG_SET_DEFAULT(UseVzeroupper, false); 1180 } 1181 } 1182 } 1183 1184 1185 #ifdef _LP64 1186 if (UseSSE42Intrinsics) { 1187 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { 1188 UseVectorizedMismatchIntrinsic = true; 1189 } 1190 } else if (UseVectorizedMismatchIntrinsic) { 1191 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) 1192 warning("vectorizedMismatch intrinsics are not available on this CPU"); 1193 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 1194 } 1195 #else 1196 if (UseVectorizedMismatchIntrinsic) { 1197 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { 1198 warning("vectorizedMismatch intrinsic is not available in 32-bit VM"); 1199 } 1200 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 1201 } 1202 #endif // _LP64 1203 1204 // Use count leading zeros count instruction if available. 1205 if (supports_lzcnt()) { 1206 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { 1207 UseCountLeadingZerosInstruction = true; 1208 } 1209 } else if (UseCountLeadingZerosInstruction) { 1210 warning("lzcnt instruction is not available on this CPU"); 1211 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); 1212 } 1213 1214 // Use count trailing zeros instruction if available 1215 if (supports_bmi1()) { 1216 // tzcnt does not require VEX prefix 1217 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { 1218 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1219 // Don't use tzcnt if BMI1 is switched off on command line. 1220 UseCountTrailingZerosInstruction = false; 1221 } else { 1222 UseCountTrailingZerosInstruction = true; 1223 } 1224 } 1225 } else if (UseCountTrailingZerosInstruction) { 1226 warning("tzcnt instruction is not available on this CPU"); 1227 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); 1228 } 1229 1230 // BMI instructions (except tzcnt) use an encoding with VEX prefix. 1231 // VEX prefix is generated only when AVX > 0. 1232 if (supports_bmi1() && supports_avx()) { 1233 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1234 UseBMI1Instructions = true; 1235 } 1236 } else if (UseBMI1Instructions) { 1237 warning("BMI1 instructions are not available on this CPU (AVX is also required)"); 1238 FLAG_SET_DEFAULT(UseBMI1Instructions, false); 1239 } 1240 1241 if (supports_bmi2() && supports_avx()) { 1242 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { 1243 UseBMI2Instructions = true; 1244 } 1245 } else if (UseBMI2Instructions) { 1246 warning("BMI2 instructions are not available on this CPU (AVX is also required)"); 1247 FLAG_SET_DEFAULT(UseBMI2Instructions, false); 1248 } 1249 1250 // Use population count instruction if available. 1251 if (supports_popcnt()) { 1252 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 1253 UsePopCountInstruction = true; 1254 } 1255 } else if (UsePopCountInstruction) { 1256 warning("POPCNT instruction is not available on this CPU"); 1257 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 1258 } 1259 1260 // Use fast-string operations if available. 1261 if (supports_erms()) { 1262 if (FLAG_IS_DEFAULT(UseFastStosb)) { 1263 UseFastStosb = true; 1264 } 1265 } else if (UseFastStosb) { 1266 warning("fast-string operations are not available on this CPU"); 1267 FLAG_SET_DEFAULT(UseFastStosb, false); 1268 } 1269 1270 #ifdef COMPILER2 1271 if (FLAG_IS_DEFAULT(AlignVector)) { 1272 // Modern processors allow misaligned memory operations for vectors. 1273 AlignVector = !UseUnalignedLoadStores; 1274 } 1275 #endif // COMPILER2 1276 1277 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; 1278 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; 1279 1280 // Allocation prefetch settings 1281 intx cache_line_size = prefetch_data_size(); 1282 if( cache_line_size > AllocatePrefetchStepSize ) 1283 AllocatePrefetchStepSize = cache_line_size; 1284 1285 AllocatePrefetchDistance = allocate_prefetch_distance(); 1286 AllocatePrefetchStyle = allocate_prefetch_style(); 1287 1288 if (is_intel() && cpu_family() == 6 && supports_sse3()) { 1289 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core 1290 #ifdef _LP64 1291 AllocatePrefetchDistance = 384; 1292 #else 1293 AllocatePrefetchDistance = 320; 1294 #endif 1295 } 1296 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus 1297 AllocatePrefetchDistance = 192; 1298 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 1299 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); 1300 } 1301 } 1302 #ifdef COMPILER2 1303 if (supports_sse4_2()) { 1304 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { 1305 FLAG_SET_DEFAULT(UseFPUForSpilling, true); 1306 } 1307 } 1308 #endif 1309 } 1310 1311 #ifdef _LP64 1312 // Prefetch settings 1313 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 1314 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 1315 PrefetchFieldsAhead = prefetch_fields_ahead(); 1316 #endif 1317 1318 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 1319 (cache_line_size > ContendedPaddingWidth)) 1320 ContendedPaddingWidth = cache_line_size; 1321 1322 // This machine allows unaligned memory accesses 1323 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 1324 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 1325 } 1326 1327 #ifndef PRODUCT 1328 if (log_is_enabled(Info, os, cpu)) { 1329 outputStream* log = Log(os, cpu)::info_stream(); 1330 log->print_cr("Logical CPUs per core: %u", 1331 logical_processors_per_package()); 1332 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 1333 log->print("UseSSE=%d", (int) UseSSE); 1334 if (UseAVX > 0) { 1335 log->print(" UseAVX=%d", (int) UseAVX); 1336 } 1337 if (UseAES) { 1338 log->print(" UseAES=1"); 1339 } 1340 #ifdef COMPILER2 1341 if (MaxVectorSize > 0) { 1342 log->print(" MaxVectorSize=%d", (int) MaxVectorSize); 1343 } 1344 #endif 1345 log->cr(); 1346 log->print("Allocation"); 1347 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { 1348 log->print_cr(": no prefetching"); 1349 } else { 1350 log->print(" prefetching: "); 1351 if (UseSSE == 0 && supports_3dnow_prefetch()) { 1352 log->print("PREFETCHW"); 1353 } else if (UseSSE >= 1) { 1354 if (AllocatePrefetchInstr == 0) { 1355 log->print("PREFETCHNTA"); 1356 } else if (AllocatePrefetchInstr == 1) { 1357 log->print("PREFETCHT0"); 1358 } else if (AllocatePrefetchInstr == 2) { 1359 log->print("PREFETCHT2"); 1360 } else if (AllocatePrefetchInstr == 3) { 1361 log->print("PREFETCHW"); 1362 } 1363 } 1364 if (AllocatePrefetchLines > 1) { 1365 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 1366 } else { 1367 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 1368 } 1369 } 1370 1371 if (PrefetchCopyIntervalInBytes > 0) { 1372 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 1373 } 1374 if (PrefetchScanIntervalInBytes > 0) { 1375 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 1376 } 1377 if (PrefetchFieldsAhead > 0) { 1378 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 1379 } 1380 if (ContendedPaddingWidth > 0) { 1381 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 1382 } 1383 } 1384 #endif // !PRODUCT 1385 } 1386 1387 bool VM_Version::use_biased_locking() { 1388 #if INCLUDE_RTM_OPT 1389 // RTM locking is most useful when there is high lock contention and 1390 // low data contention. With high lock contention the lock is usually 1391 // inflated and biased locking is not suitable for that case. 1392 // RTM locking code requires that biased locking is off. 1393 // Note: we can't switch off UseBiasedLocking in get_processor_features() 1394 // because it is used by Thread::allocate() which is called before 1395 // VM_Version::initialize(). 1396 if (UseRTMLocking && UseBiasedLocking) { 1397 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 1398 FLAG_SET_DEFAULT(UseBiasedLocking, false); 1399 } else { 1400 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 1401 UseBiasedLocking = false; 1402 } 1403 } 1404 #endif 1405 return UseBiasedLocking; 1406 } 1407 1408 void VM_Version::initialize() { 1409 ResourceMark rm; 1410 // Making this stub must be FIRST use of assembler 1411 1412 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); 1413 if (stub_blob == NULL) { 1414 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); 1415 } 1416 CodeBuffer c(stub_blob); 1417 VM_Version_StubGenerator g(&c); 1418 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, 1419 g.generate_get_cpu_info()); 1420 1421 get_processor_features(); 1422 }