1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return UseVzeroupper ? 3: 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
867 if (framesize > 0) {
868 st->print("\n\t");
869 st->print("addq rbp, #%d", framesize);
870 }
871 }
872 }
873
874 if (VerifyStackAtCalls) {
875 st->print("\n\t");
876 framesize -= wordSize;
877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
878 #ifdef ASSERT
879 st->print("\n\t");
880 st->print("# stack alignment check");
881 #endif
882 }
883 st->cr();
884 }
885 #endif
886
887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
888 Compile* C = ra_->C;
889 MacroAssembler _masm(&cbuf);
890
891 int framesize = C->frame_size_in_bytes();
892 int bangsize = C->bang_size_in_bytes();
893
894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
895
896 C->set_frame_complete(cbuf.insts_size());
897
898 if (C->has_mach_constant_base_node()) {
899 // NOTE: We set the table base offset here because users might be
900 // emitted before MachConstantBaseNode.
901 Compile::ConstantTable& constant_table = C->constant_table();
902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
903 }
904 }
905
906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
907 {
908 return MachNode::size(ra_); // too many variables; just compute it
909 // the hard way
910 }
911
912 int MachPrologNode::reloc() const
913 {
914 return 0; // a large enough number
915 }
916
917 //=============================================================================
918 #ifndef PRODUCT
919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
920 {
921 Compile* C = ra_->C;
922 if (C->max_vector_size() > 16) {
923 st->print("vzeroupper");
924 st->cr(); st->print("\t");
925 }
926
927 int framesize = C->frame_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove word for return adr already pushed
930 // and RBP
931 framesize -= 2*wordSize;
932
933 if (framesize) {
934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
935 st->print("\t");
936 }
937
938 st->print_cr("popq rbp");
939 if (do_polling() && C->is_method_compilation()) {
940 st->print("\t");
941 if (Assembler::is_polling_page_far()) {
942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
943 "testl rax, [rscratch1]\t"
944 "# Safepoint: poll for GC");
945 } else {
946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
947 "# Safepoint: poll for GC");
948 }
949 }
950 }
951 #endif
952
953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
954 {
955 Compile* C = ra_->C;
956 MacroAssembler _masm(&cbuf);
957
958 if (C->max_vector_size() > 16) {
959 // Clear upper bits of YMM registers when current compiled code uses
960 // wide vectors to avoid AVX <-> SSE transition penalty during call.
961 __ vzeroupper();
962 }
963
964 int framesize = C->frame_size_in_bytes();
965 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
966 // Remove word for return adr already pushed
967 // and RBP
968 framesize -= 2*wordSize;
969
970 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
971
972 if (framesize) {
973 emit_opcode(cbuf, Assembler::REX_W);
974 if (framesize < 0x80) {
975 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
976 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
977 emit_d8(cbuf, framesize);
978 } else {
979 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d32(cbuf, framesize);
982 }
983 }
984
985 // popq rbp
986 emit_opcode(cbuf, 0x58 | RBP_enc);
987
988 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
989 __ reserved_stack_check();
990 }
991
992 if (do_polling() && C->is_method_compilation()) {
993 MacroAssembler _masm(&cbuf);
994 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
995 if (Assembler::is_polling_page_far()) {
996 __ lea(rscratch1, polling_page);
997 __ relocate(relocInfo::poll_return_type);
998 __ testl(rax, Address(rscratch1, 0));
999 } else {
1000 __ testl(rax, polling_page);
1001 }
1002 }
1003 }
1004
1005 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1006 {
1007 return MachNode::size(ra_); // too many variables; just compute it
1008 // the hard way
1009 }
1010
1011 int MachEpilogNode::reloc() const
1012 {
1013 return 2; // a large enough number
1014 }
1015
1016 const Pipeline* MachEpilogNode::pipeline() const
1017 {
1018 return MachNode::pipeline_class();
1019 }
1020
1021 int MachEpilogNode::safepoint_offset() const
1022 {
1023 return 0;
1024 }
1025
1026 //=============================================================================
1027
1028 enum RC {
1029 rc_bad,
1030 rc_int,
1031 rc_float,
1032 rc_stack
1033 };
1034
1035 static enum RC rc_class(OptoReg::Name reg)
1036 {
1037 if( !OptoReg::is_valid(reg) ) return rc_bad;
1038
1039 if (OptoReg::is_stack(reg)) return rc_stack;
1040
1041 VMReg r = OptoReg::as_VMReg(reg);
1042
1043 if (r->is_Register()) return rc_int;
1044
1045 assert(r->is_XMMRegister(), "must be");
1046 return rc_float;
1047 }
1048
1049 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1050 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1051 int src_hi, int dst_hi, uint ireg, outputStream* st);
1052
1053 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1054 int stack_offset, int reg, uint ireg, outputStream* st);
1055
1056 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1057 int dst_offset, uint ireg, outputStream* st) {
1058 if (cbuf) {
1059 MacroAssembler _masm(cbuf);
1060 switch (ireg) {
1061 case Op_VecS:
1062 __ movq(Address(rsp, -8), rax);
1063 __ movl(rax, Address(rsp, src_offset));
1064 __ movl(Address(rsp, dst_offset), rax);
1065 __ movq(rax, Address(rsp, -8));
1066 break;
1067 case Op_VecD:
1068 __ pushq(Address(rsp, src_offset));
1069 __ popq (Address(rsp, dst_offset));
1070 break;
1071 case Op_VecX:
1072 __ pushq(Address(rsp, src_offset));
1073 __ popq (Address(rsp, dst_offset));
1074 __ pushq(Address(rsp, src_offset+8));
1075 __ popq (Address(rsp, dst_offset+8));
1076 break;
1077 case Op_VecY:
1078 __ vmovdqu(Address(rsp, -32), xmm0);
1079 __ vmovdqu(xmm0, Address(rsp, src_offset));
1080 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1081 __ vmovdqu(xmm0, Address(rsp, -32));
1082 break;
1083 case Op_VecZ:
1084 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1085 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1086 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1087 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1088 break;
1089 default:
1090 ShouldNotReachHere();
1091 }
1092 #ifndef PRODUCT
1093 } else {
1094 switch (ireg) {
1095 case Op_VecS:
1096 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1097 "movl rax, [rsp + #%d]\n\t"
1098 "movl [rsp + #%d], rax\n\t"
1099 "movq rax, [rsp - #8]",
1100 src_offset, dst_offset);
1101 break;
1102 case Op_VecD:
1103 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1104 "popq [rsp + #%d]",
1105 src_offset, dst_offset);
1106 break;
1107 case Op_VecX:
1108 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1109 "popq [rsp + #%d]\n\t"
1110 "pushq [rsp + #%d]\n\t"
1111 "popq [rsp + #%d]",
1112 src_offset, dst_offset, src_offset+8, dst_offset+8);
1113 break;
1114 case Op_VecY:
1115 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
1117 "vmovdqu [rsp + #%d], xmm0\n\t"
1118 "vmovdqu xmm0, [rsp - #32]",
1119 src_offset, dst_offset);
1120 break;
1121 case Op_VecZ:
1122 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1123 "vmovdqu xmm0, [rsp + #%d]\n\t"
1124 "vmovdqu [rsp + #%d], xmm0\n\t"
1125 "vmovdqu xmm0, [rsp - #64]",
1126 src_offset, dst_offset);
1127 break;
1128 default:
1129 ShouldNotReachHere();
1130 }
1131 #endif
1132 }
1133 }
1134
1135 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1136 PhaseRegAlloc* ra_,
1137 bool do_size,
1138 outputStream* st) const {
1139 assert(cbuf != NULL || st != NULL, "sanity");
1140 // Get registers to move
1141 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1142 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1143 OptoReg::Name dst_second = ra_->get_reg_second(this);
1144 OptoReg::Name dst_first = ra_->get_reg_first(this);
1145
1146 enum RC src_second_rc = rc_class(src_second);
1147 enum RC src_first_rc = rc_class(src_first);
1148 enum RC dst_second_rc = rc_class(dst_second);
1149 enum RC dst_first_rc = rc_class(dst_first);
1150
1151 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1152 "must move at least 1 register" );
1153
1154 if (src_first == dst_first && src_second == dst_second) {
1155 // Self copy, no move
1156 return 0;
1157 }
1158 if (bottom_type()->isa_vect() != NULL) {
1159 uint ireg = ideal_reg();
1160 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1161 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1162 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1163 // mem -> mem
1164 int src_offset = ra_->reg2offset(src_first);
1165 int dst_offset = ra_->reg2offset(dst_first);
1166 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1167 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1168 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1169 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1170 int stack_offset = ra_->reg2offset(dst_first);
1171 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1172 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1173 int stack_offset = ra_->reg2offset(src_first);
1174 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1175 } else {
1176 ShouldNotReachHere();
1177 }
1178 return 0;
1179 }
1180 if (src_first_rc == rc_stack) {
1181 // mem ->
1182 if (dst_first_rc == rc_stack) {
1183 // mem -> mem
1184 assert(src_second != dst_first, "overlap");
1185 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1186 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1187 // 64-bit
1188 int src_offset = ra_->reg2offset(src_first);
1189 int dst_offset = ra_->reg2offset(dst_first);
1190 if (cbuf) {
1191 MacroAssembler _masm(cbuf);
1192 __ pushq(Address(rsp, src_offset));
1193 __ popq (Address(rsp, dst_offset));
1194 #ifndef PRODUCT
1195 } else {
1196 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1197 "popq [rsp + #%d]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 } else {
1202 // 32-bit
1203 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1204 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1205 // No pushl/popl, so:
1206 int src_offset = ra_->reg2offset(src_first);
1207 int dst_offset = ra_->reg2offset(dst_first);
1208 if (cbuf) {
1209 MacroAssembler _masm(cbuf);
1210 __ movq(Address(rsp, -8), rax);
1211 __ movl(rax, Address(rsp, src_offset));
1212 __ movl(Address(rsp, dst_offset), rax);
1213 __ movq(rax, Address(rsp, -8));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1217 "movl rax, [rsp + #%d]\n\t"
1218 "movl [rsp + #%d], rax\n\t"
1219 "movq rax, [rsp - #8]",
1220 src_offset, dst_offset);
1221 #endif
1222 }
1223 }
1224 return 0;
1225 } else if (dst_first_rc == rc_int) {
1226 // mem -> gpr
1227 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1228 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1229 // 64-bit
1230 int offset = ra_->reg2offset(src_first);
1231 if (cbuf) {
1232 MacroAssembler _masm(cbuf);
1233 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1234 #ifndef PRODUCT
1235 } else {
1236 st->print("movq %s, [rsp + #%d]\t# spill",
1237 Matcher::regName[dst_first],
1238 offset);
1239 #endif
1240 }
1241 } else {
1242 // 32-bit
1243 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1244 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1245 int offset = ra_->reg2offset(src_first);
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1249 #ifndef PRODUCT
1250 } else {
1251 st->print("movl %s, [rsp + #%d]\t# spill",
1252 Matcher::regName[dst_first],
1253 offset);
1254 #endif
1255 }
1256 }
1257 return 0;
1258 } else if (dst_first_rc == rc_float) {
1259 // mem-> xmm
1260 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1261 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1262 // 64-bit
1263 int offset = ra_->reg2offset(src_first);
1264 if (cbuf) {
1265 MacroAssembler _masm(cbuf);
1266 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1267 #ifndef PRODUCT
1268 } else {
1269 st->print("%s %s, [rsp + #%d]\t# spill",
1270 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1271 Matcher::regName[dst_first],
1272 offset);
1273 #endif
1274 }
1275 } else {
1276 // 32-bit
1277 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1278 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1279 int offset = ra_->reg2offset(src_first);
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movss %s, [rsp + #%d]\t# spill",
1286 Matcher::regName[dst_first],
1287 offset);
1288 #endif
1289 }
1290 }
1291 return 0;
1292 }
1293 } else if (src_first_rc == rc_int) {
1294 // gpr ->
1295 if (dst_first_rc == rc_stack) {
1296 // gpr -> mem
1297 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1298 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1299 // 64-bit
1300 int offset = ra_->reg2offset(dst_first);
1301 if (cbuf) {
1302 MacroAssembler _masm(cbuf);
1303 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1304 #ifndef PRODUCT
1305 } else {
1306 st->print("movq [rsp + #%d], %s\t# spill",
1307 offset,
1308 Matcher::regName[src_first]);
1309 #endif
1310 }
1311 } else {
1312 // 32-bit
1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1315 int offset = ra_->reg2offset(dst_first);
1316 if (cbuf) {
1317 MacroAssembler _masm(cbuf);
1318 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1319 #ifndef PRODUCT
1320 } else {
1321 st->print("movl [rsp + #%d], %s\t# spill",
1322 offset,
1323 Matcher::regName[src_first]);
1324 #endif
1325 }
1326 }
1327 return 0;
1328 } else if (dst_first_rc == rc_int) {
1329 // gpr -> gpr
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 if (cbuf) {
1334 MacroAssembler _masm(cbuf);
1335 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1336 as_Register(Matcher::_regEncode[src_first]));
1337 #ifndef PRODUCT
1338 } else {
1339 st->print("movq %s, %s\t# spill",
1340 Matcher::regName[dst_first],
1341 Matcher::regName[src_first]);
1342 #endif
1343 }
1344 return 0;
1345 } else {
1346 // 32-bit
1347 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1348 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1349 if (cbuf) {
1350 MacroAssembler _masm(cbuf);
1351 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1352 as_Register(Matcher::_regEncode[src_first]));
1353 #ifndef PRODUCT
1354 } else {
1355 st->print("movl %s, %s\t# spill",
1356 Matcher::regName[dst_first],
1357 Matcher::regName[src_first]);
1358 #endif
1359 }
1360 return 0;
1361 }
1362 } else if (dst_first_rc == rc_float) {
1363 // gpr -> xmm
1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1366 // 64-bit
1367 if (cbuf) {
1368 MacroAssembler _masm(cbuf);
1369 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1370 #ifndef PRODUCT
1371 } else {
1372 st->print("movdq %s, %s\t# spill",
1373 Matcher::regName[dst_first],
1374 Matcher::regName[src_first]);
1375 #endif
1376 }
1377 } else {
1378 // 32-bit
1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385 } else {
1386 st->print("movdl %s, %s\t# spill",
1387 Matcher::regName[dst_first],
1388 Matcher::regName[src_first]);
1389 #endif
1390 }
1391 }
1392 return 0;
1393 }
1394 } else if (src_first_rc == rc_float) {
1395 // xmm ->
1396 if (dst_first_rc == rc_stack) {
1397 // xmm -> mem
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1400 // 64-bit
1401 int offset = ra_->reg2offset(dst_first);
1402 if (cbuf) {
1403 MacroAssembler _masm(cbuf);
1404 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1405 #ifndef PRODUCT
1406 } else {
1407 st->print("movsd [rsp + #%d], %s\t# spill",
1408 offset,
1409 Matcher::regName[src_first]);
1410 #endif
1411 }
1412 } else {
1413 // 32-bit
1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1416 int offset = ra_->reg2offset(dst_first);
1417 if (cbuf) {
1418 MacroAssembler _masm(cbuf);
1419 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1420 #ifndef PRODUCT
1421 } else {
1422 st->print("movss [rsp + #%d], %s\t# spill",
1423 offset,
1424 Matcher::regName[src_first]);
1425 #endif
1426 }
1427 }
1428 return 0;
1429 } else if (dst_first_rc == rc_int) {
1430 // xmm -> gpr
1431 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1432 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1433 // 64-bit
1434 if (cbuf) {
1435 MacroAssembler _masm(cbuf);
1436 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("movdq %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 } else {
1445 // 32-bit
1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448 if (cbuf) {
1449 MacroAssembler _masm(cbuf);
1450 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1451 #ifndef PRODUCT
1452 } else {
1453 st->print("movdl %s, %s\t# spill",
1454 Matcher::regName[dst_first],
1455 Matcher::regName[src_first]);
1456 #endif
1457 }
1458 }
1459 return 0;
1460 } else if (dst_first_rc == rc_float) {
1461 // xmm -> xmm
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1463 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1464 // 64-bit
1465 if (cbuf) {
1466 MacroAssembler _masm(cbuf);
1467 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1468 #ifndef PRODUCT
1469 } else {
1470 st->print("%s %s, %s\t# spill",
1471 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 } else {
1477 // 32-bit
1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480 if (cbuf) {
1481 MacroAssembler _masm(cbuf);
1482 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484 } else {
1485 st->print("%s %s, %s\t# spill",
1486 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1487 Matcher::regName[dst_first],
1488 Matcher::regName[src_first]);
1489 #endif
1490 }
1491 }
1492 return 0;
1493 }
1494 }
1495
1496 assert(0," foo ");
1497 Unimplemented();
1498 return 0;
1499 }
1500
1501 #ifndef PRODUCT
1502 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1503 implementation(NULL, ra_, false, st);
1504 }
1505 #endif
1506
1507 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1508 implementation(&cbuf, ra_, false, NULL);
1509 }
1510
1511 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1512 return MachNode::size(ra_);
1513 }
1514
1515 //=============================================================================
1516 #ifndef PRODUCT
1517 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1518 {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("leaq %s, [rsp + #%d]\t# box lock",
1522 Matcher::regName[reg], offset);
1523 }
1524 #endif
1525
1526 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_encode(this);
1530 if (offset >= 0x80) {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d32(cbuf, offset);
1536 } else {
1537 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1538 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1539 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1540 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1541 emit_d8(cbuf, offset);
1542 }
1543 }
1544
1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1546 {
1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1548 return (offset < 0x80) ? 5 : 8; // REX
1549 }
1550
1551 //=============================================================================
1552 #ifndef PRODUCT
1553 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1554 {
1555 if (UseCompressedClassPointers) {
1556 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1557 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1558 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1559 } else {
1560 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1561 "# Inline cache check");
1562 }
1563 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1564 st->print_cr("\tnop\t# nops to align entry point");
1565 }
1566 #endif
1567
1568 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1569 {
1570 MacroAssembler masm(&cbuf);
1571 uint insts_size = cbuf.insts_size();
1572 if (UseCompressedClassPointers) {
1573 masm.load_klass(rscratch1, j_rarg0);
1574 masm.cmpptr(rax, rscratch1);
1575 } else {
1576 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1577 }
1578
1579 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1580
1581 /* WARNING these NOPs are critical so that verified entry point is properly
1582 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1583 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1584 if (OptoBreakpoint) {
1585 // Leave space for int3
1586 nops_cnt -= 1;
1587 }
1588 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1589 if (nops_cnt > 0)
1590 masm.nop(nops_cnt);
1591 }
1592
1593 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1594 {
1595 return MachNode::size(ra_); // too many variables; just compute it
1596 // the hard way
1597 }
1598
1599
1600 //=============================================================================
1601
1602 int Matcher::regnum_to_fpu_offset(int regnum)
1603 {
1604 return regnum - 32; // The FP registers are in the second chunk
1605 }
1606
1607 // This is UltraSparc specific, true just means we have fast l2f conversion
1608 const bool Matcher::convL2FSupported(void) {
1609 return true;
1610 }
1611
1612 // Is this branch offset short enough that a short branch can be used?
1613 //
1614 // NOTE: If the platform does not provide any short branch variants, then
1615 // this method should return false for offset 0.
1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1617 // The passed offset is relative to address of the branch.
1618 // On 86 a branch displacement is calculated relative to address
1619 // of a next instruction.
1620 offset -= br_size;
1621
1622 // the short version of jmpConUCF2 contains multiple branches,
1623 // making the reach slightly less
1624 if (rule == jmpConUCF2_rule)
1625 return (-126 <= offset && offset <= 125);
1626 return (-128 <= offset && offset <= 127);
1627 }
1628
1629 const bool Matcher::isSimpleConstant64(jlong value) {
1630 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1631 //return value == (int) value; // Cf. storeImmL and immL32.
1632
1633 // Probably always true, even if a temp register is required.
1634 return true;
1635 }
1636
1637 // The ecx parameter to rep stosq for the ClearArray node is in words.
1638 const bool Matcher::init_array_count_is_in_bytes = false;
1639
1640 // No additional cost for CMOVL.
1641 const int Matcher::long_cmove_cost() { return 0; }
1642
1643 // No CMOVF/CMOVD with SSE2
1644 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1645
1646 // Does the CPU require late expand (see block.cpp for description of late expand)?
1647 const bool Matcher::require_postalloc_expand = false;
1648
1649 // Do we need to mask the count passed to shift instructions or does
1650 // the cpu only look at the lower 5/6 bits anyway?
1651 const bool Matcher::need_masked_shift_count = false;
1652
1653 bool Matcher::narrow_oop_use_complex_address() {
1654 assert(UseCompressedOops, "only for compressed oops code");
1655 return (LogMinObjAlignmentInBytes <= 3);
1656 }
1657
1658 bool Matcher::narrow_klass_use_complex_address() {
1659 assert(UseCompressedClassPointers, "only for compressed klass code");
1660 return (LogKlassAlignmentInBytes <= 3);
1661 }
1662
1663 bool Matcher::const_oop_prefer_decode() {
1664 // Prefer ConN+DecodeN over ConP.
1665 return true;
1666 }
1667
1668 bool Matcher::const_klass_prefer_decode() {
1669 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1670 // or condisider the following:
1671 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1672 //return Universe::narrow_klass_base() == NULL;
1673 return true;
1674 }
1675
1676 // Is it better to copy float constants, or load them directly from
1677 // memory? Intel can load a float constant from a direct address,
1678 // requiring no extra registers. Most RISCs will have to materialize
1679 // an address into a register first, so they would do better to copy
1680 // the constant from stack.
1681 const bool Matcher::rematerialize_float_constants = true; // XXX
1682
1683 // If CPU can load and store mis-aligned doubles directly then no
1684 // fixup is needed. Else we split the double into 2 integer pieces
1685 // and move it piece-by-piece. Only happens when passing doubles into
1686 // C code as the Java calling convention forces doubles to be aligned.
1687 const bool Matcher::misaligned_doubles_ok = true;
1688
1689 // No-op on amd64
1690 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1691
1692 // Advertise here if the CPU requires explicit rounding operations to
1693 // implement the UseStrictFP mode.
1694 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1695
1696 // Are floats conerted to double when stored to stack during deoptimization?
1697 // On x64 it is stored without convertion so we can use normal access.
1698 bool Matcher::float_in_double() { return false; }
1699
1700 // Do ints take an entire long register or just half?
1701 const bool Matcher::int_in_long = true;
1702
1703 // Return whether or not this register is ever used as an argument.
1704 // This function is used on startup to build the trampoline stubs in
1705 // generateOptoStub. Registers not mentioned will be killed by the VM
1706 // call in the trampoline, and arguments in those registers not be
1707 // available to the callee.
1708 bool Matcher::can_be_java_arg(int reg)
1709 {
1710 return
1711 reg == RDI_num || reg == RDI_H_num ||
1712 reg == RSI_num || reg == RSI_H_num ||
1713 reg == RDX_num || reg == RDX_H_num ||
1714 reg == RCX_num || reg == RCX_H_num ||
1715 reg == R8_num || reg == R8_H_num ||
1716 reg == R9_num || reg == R9_H_num ||
1717 reg == R12_num || reg == R12_H_num ||
1718 reg == XMM0_num || reg == XMM0b_num ||
1719 reg == XMM1_num || reg == XMM1b_num ||
1720 reg == XMM2_num || reg == XMM2b_num ||
1721 reg == XMM3_num || reg == XMM3b_num ||
1722 reg == XMM4_num || reg == XMM4b_num ||
1723 reg == XMM5_num || reg == XMM5b_num ||
1724 reg == XMM6_num || reg == XMM6b_num ||
1725 reg == XMM7_num || reg == XMM7b_num;
1726 }
1727
1728 bool Matcher::is_spillable_arg(int reg)
1729 {
1730 return can_be_java_arg(reg);
1731 }
1732
1733 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1734 // In 64 bit mode a code which use multiply when
1735 // devisor is constant is faster than hardware
1736 // DIV instruction (it uses MulHiL).
1737 return false;
1738 }
1739
1740 // Register for DIVI projection of divmodI
1741 RegMask Matcher::divI_proj_mask() {
1742 return INT_RAX_REG_mask();
1743 }
1744
1745 // Register for MODI projection of divmodI
1746 RegMask Matcher::modI_proj_mask() {
1747 return INT_RDX_REG_mask();
1748 }
1749
1750 // Register for DIVL projection of divmodL
1751 RegMask Matcher::divL_proj_mask() {
1752 return LONG_RAX_REG_mask();
1753 }
1754
1755 // Register for MODL projection of divmodL
1756 RegMask Matcher::modL_proj_mask() {
1757 return LONG_RDX_REG_mask();
1758 }
1759
1760 // Register for saving SP into on method handle invokes. Not used on x86_64.
1761 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1762 return NO_REG_mask();
1763 }
1764
1765 %}
1766
1767 //----------ENCODING BLOCK-----------------------------------------------------
1768 // This block specifies the encoding classes used by the compiler to
1769 // output byte streams. Encoding classes are parameterized macros
1770 // used by Machine Instruction Nodes in order to generate the bit
1771 // encoding of the instruction. Operands specify their base encoding
1772 // interface with the interface keyword. There are currently
1773 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1774 // COND_INTER. REG_INTER causes an operand to generate a function
1775 // which returns its register number when queried. CONST_INTER causes
1776 // an operand to generate a function which returns the value of the
1777 // constant when queried. MEMORY_INTER causes an operand to generate
1778 // four functions which return the Base Register, the Index Register,
1779 // the Scale Value, and the Offset Value of the operand when queried.
1780 // COND_INTER causes an operand to generate six functions which return
1781 // the encoding code (ie - encoding bits for the instruction)
1782 // associated with each basic boolean condition for a conditional
1783 // instruction.
1784 //
1785 // Instructions specify two basic values for encoding. Again, a
1786 // function is available to check if the constant displacement is an
1787 // oop. They use the ins_encode keyword to specify their encoding
1788 // classes (which must be a sequence of enc_class names, and their
1789 // parameters, specified in the encoding block), and they use the
1790 // opcode keyword to specify, in order, their primary, secondary, and
1791 // tertiary opcode. Only the opcode sections which a particular
1792 // instruction needs for encoding need to be specified.
1793 encode %{
1794 // Build emit functions for each basic byte or larger field in the
1795 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1796 // from C++ code in the enc_class source block. Emit functions will
1797 // live in the main source block for now. In future, we can
1798 // generalize this by adding a syntax that specifies the sizes of
1799 // fields in an order, so that the adlc can build the emit functions
1800 // automagically
1801
1802 // Emit primary opcode
1803 enc_class OpcP
1804 %{
1805 emit_opcode(cbuf, $primary);
1806 %}
1807
1808 // Emit secondary opcode
1809 enc_class OpcS
1810 %{
1811 emit_opcode(cbuf, $secondary);
1812 %}
1813
1814 // Emit tertiary opcode
1815 enc_class OpcT
1816 %{
1817 emit_opcode(cbuf, $tertiary);
1818 %}
1819
1820 // Emit opcode directly
1821 enc_class Opcode(immI d8)
1822 %{
1823 emit_opcode(cbuf, $d8$$constant);
1824 %}
1825
1826 // Emit size prefix
1827 enc_class SizePrefix
1828 %{
1829 emit_opcode(cbuf, 0x66);
1830 %}
1831
1832 enc_class reg(rRegI reg)
1833 %{
1834 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1835 %}
1836
1837 enc_class reg_reg(rRegI dst, rRegI src)
1838 %{
1839 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1840 %}
1841
1842 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1843 %{
1844 emit_opcode(cbuf, $opcode$$constant);
1845 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1846 %}
1847
1848 enc_class cdql_enc(no_rax_rdx_RegI div)
1849 %{
1850 // Full implementation of Java idiv and irem; checks for
1851 // special case as described in JVM spec., p.243 & p.271.
1852 //
1853 // normal case special case
1854 //
1855 // input : rax: dividend min_int
1856 // reg: divisor -1
1857 //
1858 // output: rax: quotient (= rax idiv reg) min_int
1859 // rdx: remainder (= rax irem reg) 0
1860 //
1861 // Code sequnce:
1862 //
1863 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1864 // 5: 75 07/08 jne e <normal>
1865 // 7: 33 d2 xor %edx,%edx
1866 // [div >= 8 -> offset + 1]
1867 // [REX_B]
1868 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1869 // c: 74 03/04 je 11 <done>
1870 // 000000000000000e <normal>:
1871 // e: 99 cltd
1872 // [div >= 8 -> offset + 1]
1873 // [REX_B]
1874 // f: f7 f9 idiv $div
1875 // 0000000000000011 <done>:
1876
1877 // cmp $0x80000000,%eax
1878 emit_opcode(cbuf, 0x3d);
1879 emit_d8(cbuf, 0x00);
1880 emit_d8(cbuf, 0x00);
1881 emit_d8(cbuf, 0x00);
1882 emit_d8(cbuf, 0x80);
1883
1884 // jne e <normal>
1885 emit_opcode(cbuf, 0x75);
1886 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1887
1888 // xor %edx,%edx
1889 emit_opcode(cbuf, 0x33);
1890 emit_d8(cbuf, 0xD2);
1891
1892 // cmp $0xffffffffffffffff,%ecx
1893 if ($div$$reg >= 8) {
1894 emit_opcode(cbuf, Assembler::REX_B);
1895 }
1896 emit_opcode(cbuf, 0x83);
1897 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1898 emit_d8(cbuf, 0xFF);
1899
1900 // je 11 <done>
1901 emit_opcode(cbuf, 0x74);
1902 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1903
1904 // <normal>
1905 // cltd
1906 emit_opcode(cbuf, 0x99);
1907
1908 // idivl (note: must be emitted by the user of this rule)
1909 // <done>
1910 %}
1911
1912 enc_class cdqq_enc(no_rax_rdx_RegL div)
1913 %{
1914 // Full implementation of Java ldiv and lrem; checks for
1915 // special case as described in JVM spec., p.243 & p.271.
1916 //
1917 // normal case special case
1918 //
1919 // input : rax: dividend min_long
1920 // reg: divisor -1
1921 //
1922 // output: rax: quotient (= rax idiv reg) min_long
1923 // rdx: remainder (= rax irem reg) 0
1924 //
1925 // Code sequnce:
1926 //
1927 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1928 // 7: 00 00 80
1929 // a: 48 39 d0 cmp %rdx,%rax
1930 // d: 75 08 jne 17 <normal>
1931 // f: 33 d2 xor %edx,%edx
1932 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1933 // 15: 74 05 je 1c <done>
1934 // 0000000000000017 <normal>:
1935 // 17: 48 99 cqto
1936 // 19: 48 f7 f9 idiv $div
1937 // 000000000000001c <done>:
1938
1939 // mov $0x8000000000000000,%rdx
1940 emit_opcode(cbuf, Assembler::REX_W);
1941 emit_opcode(cbuf, 0xBA);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x00);
1944 emit_d8(cbuf, 0x00);
1945 emit_d8(cbuf, 0x00);
1946 emit_d8(cbuf, 0x00);
1947 emit_d8(cbuf, 0x00);
1948 emit_d8(cbuf, 0x00);
1949 emit_d8(cbuf, 0x80);
1950
1951 // cmp %rdx,%rax
1952 emit_opcode(cbuf, Assembler::REX_W);
1953 emit_opcode(cbuf, 0x39);
1954 emit_d8(cbuf, 0xD0);
1955
1956 // jne 17 <normal>
1957 emit_opcode(cbuf, 0x75);
1958 emit_d8(cbuf, 0x08);
1959
1960 // xor %edx,%edx
1961 emit_opcode(cbuf, 0x33);
1962 emit_d8(cbuf, 0xD2);
1963
1964 // cmp $0xffffffffffffffff,$div
1965 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1966 emit_opcode(cbuf, 0x83);
1967 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1968 emit_d8(cbuf, 0xFF);
1969
1970 // je 1e <done>
1971 emit_opcode(cbuf, 0x74);
1972 emit_d8(cbuf, 0x05);
1973
1974 // <normal>
1975 // cqto
1976 emit_opcode(cbuf, Assembler::REX_W);
1977 emit_opcode(cbuf, 0x99);
1978
1979 // idivq (note: must be emitted by the user of this rule)
1980 // <done>
1981 %}
1982
1983 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1984 enc_class OpcSE(immI imm)
1985 %{
1986 // Emit primary opcode and set sign-extend bit
1987 // Check for 8-bit immediate, and set sign extend bit in opcode
1988 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1989 emit_opcode(cbuf, $primary | 0x02);
1990 } else {
1991 // 32-bit immediate
1992 emit_opcode(cbuf, $primary);
1993 }
1994 %}
1995
1996 enc_class OpcSErm(rRegI dst, immI imm)
1997 %{
1998 // OpcSEr/m
1999 int dstenc = $dst$$reg;
2000 if (dstenc >= 8) {
2001 emit_opcode(cbuf, Assembler::REX_B);
2002 dstenc -= 8;
2003 }
2004 // Emit primary opcode and set sign-extend bit
2005 // Check for 8-bit immediate, and set sign extend bit in opcode
2006 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2007 emit_opcode(cbuf, $primary | 0x02);
2008 } else {
2009 // 32-bit immediate
2010 emit_opcode(cbuf, $primary);
2011 }
2012 // Emit r/m byte with secondary opcode, after primary opcode.
2013 emit_rm(cbuf, 0x3, $secondary, dstenc);
2014 %}
2015
2016 enc_class OpcSErm_wide(rRegL dst, immI imm)
2017 %{
2018 // OpcSEr/m
2019 int dstenc = $dst$$reg;
2020 if (dstenc < 8) {
2021 emit_opcode(cbuf, Assembler::REX_W);
2022 } else {
2023 emit_opcode(cbuf, Assembler::REX_WB);
2024 dstenc -= 8;
2025 }
2026 // Emit primary opcode and set sign-extend bit
2027 // Check for 8-bit immediate, and set sign extend bit in opcode
2028 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2029 emit_opcode(cbuf, $primary | 0x02);
2030 } else {
2031 // 32-bit immediate
2032 emit_opcode(cbuf, $primary);
2033 }
2034 // Emit r/m byte with secondary opcode, after primary opcode.
2035 emit_rm(cbuf, 0x3, $secondary, dstenc);
2036 %}
2037
2038 enc_class Con8or32(immI imm)
2039 %{
2040 // Check for 8-bit immediate, and set sign extend bit in opcode
2041 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2042 $$$emit8$imm$$constant;
2043 } else {
2044 // 32-bit immediate
2045 $$$emit32$imm$$constant;
2046 }
2047 %}
2048
2049 enc_class opc2_reg(rRegI dst)
2050 %{
2051 // BSWAP
2052 emit_cc(cbuf, $secondary, $dst$$reg);
2053 %}
2054
2055 enc_class opc3_reg(rRegI dst)
2056 %{
2057 // BSWAP
2058 emit_cc(cbuf, $tertiary, $dst$$reg);
2059 %}
2060
2061 enc_class reg_opc(rRegI div)
2062 %{
2063 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2064 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2065 %}
2066
2067 enc_class enc_cmov(cmpOp cop)
2068 %{
2069 // CMOV
2070 $$$emit8$primary;
2071 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2072 %}
2073
2074 enc_class enc_PartialSubtypeCheck()
2075 %{
2076 Register Rrdi = as_Register(RDI_enc); // result register
2077 Register Rrax = as_Register(RAX_enc); // super class
2078 Register Rrcx = as_Register(RCX_enc); // killed
2079 Register Rrsi = as_Register(RSI_enc); // sub class
2080 Label miss;
2081 const bool set_cond_codes = true;
2082
2083 MacroAssembler _masm(&cbuf);
2084 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2085 NULL, &miss,
2086 /*set_cond_codes:*/ true);
2087 if ($primary) {
2088 __ xorptr(Rrdi, Rrdi);
2089 }
2090 __ bind(miss);
2091 %}
2092
2093 enc_class clear_avx %{
2094 debug_only(int off0 = cbuf.insts_size());
2095 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2096 // Clear upper bits of YMM registers when current compiled code uses
2097 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2098 MacroAssembler _masm(&cbuf);
2099 __ vzeroupper();
2100 debug_only(int off1 = cbuf.insts_size());
2101 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2102 %}
2103
2104 enc_class Java_To_Runtime(method meth) %{
2105 // No relocation needed
2106 MacroAssembler _masm(&cbuf);
2107 __ mov64(r10, (int64_t) $meth$$method);
2108 __ call(r10);
2109 %}
2110
2111 enc_class Java_To_Interpreter(method meth)
2112 %{
2113 // CALL Java_To_Interpreter
2114 // This is the instruction starting address for relocation info.
2115 cbuf.set_insts_mark();
2116 $$$emit8$primary;
2117 // CALL directly to the runtime
2118 emit_d32_reloc(cbuf,
2119 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2120 runtime_call_Relocation::spec(),
2121 RELOC_DISP32);
2122 %}
2123
2124 enc_class Java_Static_Call(method meth)
2125 %{
2126 // JAVA STATIC CALL
2127 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2128 // determine who we intended to call.
2129 cbuf.set_insts_mark();
2130 $$$emit8$primary;
2131
2132 if (!_method) {
2133 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2134 runtime_call_Relocation::spec(),
2135 RELOC_DISP32);
2136 } else {
2137 int method_index = resolved_method_index(cbuf);
2138 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2139 : static_call_Relocation::spec(method_index);
2140 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2141 rspec, RELOC_DISP32);
2142 // Emit stubs for static call.
2143 address mark = cbuf.insts_mark();
2144 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2145 if (stub == NULL) {
2146 ciEnv::current()->record_failure("CodeCache is full");
2147 return;
2148 }
2149 #if INCLUDE_AOT
2150 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2151 #endif
2152 }
2153 %}
2154
2155 enc_class Java_Dynamic_Call(method meth) %{
2156 MacroAssembler _masm(&cbuf);
2157 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2158 %}
2159
2160 enc_class Java_Compiled_Call(method meth)
2161 %{
2162 // JAVA COMPILED CALL
2163 int disp = in_bytes(Method:: from_compiled_offset());
2164
2165 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2166 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2167
2168 // callq *disp(%rax)
2169 cbuf.set_insts_mark();
2170 $$$emit8$primary;
2171 if (disp < 0x80) {
2172 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2173 emit_d8(cbuf, disp); // Displacement
2174 } else {
2175 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2176 emit_d32(cbuf, disp); // Displacement
2177 }
2178 %}
2179
2180 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2181 %{
2182 // SAL, SAR, SHR
2183 int dstenc = $dst$$reg;
2184 if (dstenc >= 8) {
2185 emit_opcode(cbuf, Assembler::REX_B);
2186 dstenc -= 8;
2187 }
2188 $$$emit8$primary;
2189 emit_rm(cbuf, 0x3, $secondary, dstenc);
2190 $$$emit8$shift$$constant;
2191 %}
2192
2193 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2194 %{
2195 // SAL, SAR, SHR
2196 int dstenc = $dst$$reg;
2197 if (dstenc < 8) {
2198 emit_opcode(cbuf, Assembler::REX_W);
2199 } else {
2200 emit_opcode(cbuf, Assembler::REX_WB);
2201 dstenc -= 8;
2202 }
2203 $$$emit8$primary;
2204 emit_rm(cbuf, 0x3, $secondary, dstenc);
2205 $$$emit8$shift$$constant;
2206 %}
2207
2208 enc_class load_immI(rRegI dst, immI src)
2209 %{
2210 int dstenc = $dst$$reg;
2211 if (dstenc >= 8) {
2212 emit_opcode(cbuf, Assembler::REX_B);
2213 dstenc -= 8;
2214 }
2215 emit_opcode(cbuf, 0xB8 | dstenc);
2216 $$$emit32$src$$constant;
2217 %}
2218
2219 enc_class load_immL(rRegL dst, immL src)
2220 %{
2221 int dstenc = $dst$$reg;
2222 if (dstenc < 8) {
2223 emit_opcode(cbuf, Assembler::REX_W);
2224 } else {
2225 emit_opcode(cbuf, Assembler::REX_WB);
2226 dstenc -= 8;
2227 }
2228 emit_opcode(cbuf, 0xB8 | dstenc);
2229 emit_d64(cbuf, $src$$constant);
2230 %}
2231
2232 enc_class load_immUL32(rRegL dst, immUL32 src)
2233 %{
2234 // same as load_immI, but this time we care about zeroes in the high word
2235 int dstenc = $dst$$reg;
2236 if (dstenc >= 8) {
2237 emit_opcode(cbuf, Assembler::REX_B);
2238 dstenc -= 8;
2239 }
2240 emit_opcode(cbuf, 0xB8 | dstenc);
2241 $$$emit32$src$$constant;
2242 %}
2243
2244 enc_class load_immL32(rRegL dst, immL32 src)
2245 %{
2246 int dstenc = $dst$$reg;
2247 if (dstenc < 8) {
2248 emit_opcode(cbuf, Assembler::REX_W);
2249 } else {
2250 emit_opcode(cbuf, Assembler::REX_WB);
2251 dstenc -= 8;
2252 }
2253 emit_opcode(cbuf, 0xC7);
2254 emit_rm(cbuf, 0x03, 0x00, dstenc);
2255 $$$emit32$src$$constant;
2256 %}
2257
2258 enc_class load_immP31(rRegP dst, immP32 src)
2259 %{
2260 // same as load_immI, but this time we care about zeroes in the high word
2261 int dstenc = $dst$$reg;
2262 if (dstenc >= 8) {
2263 emit_opcode(cbuf, Assembler::REX_B);
2264 dstenc -= 8;
2265 }
2266 emit_opcode(cbuf, 0xB8 | dstenc);
2267 $$$emit32$src$$constant;
2268 %}
2269
2270 enc_class load_immP(rRegP dst, immP src)
2271 %{
2272 int dstenc = $dst$$reg;
2273 if (dstenc < 8) {
2274 emit_opcode(cbuf, Assembler::REX_W);
2275 } else {
2276 emit_opcode(cbuf, Assembler::REX_WB);
2277 dstenc -= 8;
2278 }
2279 emit_opcode(cbuf, 0xB8 | dstenc);
2280 // This next line should be generated from ADLC
2281 if ($src->constant_reloc() != relocInfo::none) {
2282 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2283 } else {
2284 emit_d64(cbuf, $src$$constant);
2285 }
2286 %}
2287
2288 enc_class Con32(immI src)
2289 %{
2290 // Output immediate
2291 $$$emit32$src$$constant;
2292 %}
2293
2294 enc_class Con32F_as_bits(immF src)
2295 %{
2296 // Output Float immediate bits
2297 jfloat jf = $src$$constant;
2298 jint jf_as_bits = jint_cast(jf);
2299 emit_d32(cbuf, jf_as_bits);
2300 %}
2301
2302 enc_class Con16(immI src)
2303 %{
2304 // Output immediate
2305 $$$emit16$src$$constant;
2306 %}
2307
2308 // How is this different from Con32??? XXX
2309 enc_class Con_d32(immI src)
2310 %{
2311 emit_d32(cbuf,$src$$constant);
2312 %}
2313
2314 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2315 // Output immediate memory reference
2316 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2317 emit_d32(cbuf, 0x00);
2318 %}
2319
2320 enc_class lock_prefix()
2321 %{
2322 if (os::is_MP()) {
2323 emit_opcode(cbuf, 0xF0); // lock
2324 }
2325 %}
2326
2327 enc_class REX_mem(memory mem)
2328 %{
2329 if ($mem$$base >= 8) {
2330 if ($mem$$index < 8) {
2331 emit_opcode(cbuf, Assembler::REX_B);
2332 } else {
2333 emit_opcode(cbuf, Assembler::REX_XB);
2334 }
2335 } else {
2336 if ($mem$$index >= 8) {
2337 emit_opcode(cbuf, Assembler::REX_X);
2338 }
2339 }
2340 %}
2341
2342 enc_class REX_mem_wide(memory mem)
2343 %{
2344 if ($mem$$base >= 8) {
2345 if ($mem$$index < 8) {
2346 emit_opcode(cbuf, Assembler::REX_WB);
2347 } else {
2348 emit_opcode(cbuf, Assembler::REX_WXB);
2349 }
2350 } else {
2351 if ($mem$$index < 8) {
2352 emit_opcode(cbuf, Assembler::REX_W);
2353 } else {
2354 emit_opcode(cbuf, Assembler::REX_WX);
2355 }
2356 }
2357 %}
2358
2359 // for byte regs
2360 enc_class REX_breg(rRegI reg)
2361 %{
2362 if ($reg$$reg >= 4) {
2363 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2364 }
2365 %}
2366
2367 // for byte regs
2368 enc_class REX_reg_breg(rRegI dst, rRegI src)
2369 %{
2370 if ($dst$$reg < 8) {
2371 if ($src$$reg >= 4) {
2372 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2373 }
2374 } else {
2375 if ($src$$reg < 8) {
2376 emit_opcode(cbuf, Assembler::REX_R);
2377 } else {
2378 emit_opcode(cbuf, Assembler::REX_RB);
2379 }
2380 }
2381 %}
2382
2383 // for byte regs
2384 enc_class REX_breg_mem(rRegI reg, memory mem)
2385 %{
2386 if ($reg$$reg < 8) {
2387 if ($mem$$base < 8) {
2388 if ($mem$$index >= 8) {
2389 emit_opcode(cbuf, Assembler::REX_X);
2390 } else if ($reg$$reg >= 4) {
2391 emit_opcode(cbuf, Assembler::REX);
2392 }
2393 } else {
2394 if ($mem$$index < 8) {
2395 emit_opcode(cbuf, Assembler::REX_B);
2396 } else {
2397 emit_opcode(cbuf, Assembler::REX_XB);
2398 }
2399 }
2400 } else {
2401 if ($mem$$base < 8) {
2402 if ($mem$$index < 8) {
2403 emit_opcode(cbuf, Assembler::REX_R);
2404 } else {
2405 emit_opcode(cbuf, Assembler::REX_RX);
2406 }
2407 } else {
2408 if ($mem$$index < 8) {
2409 emit_opcode(cbuf, Assembler::REX_RB);
2410 } else {
2411 emit_opcode(cbuf, Assembler::REX_RXB);
2412 }
2413 }
2414 }
2415 %}
2416
2417 enc_class REX_reg(rRegI reg)
2418 %{
2419 if ($reg$$reg >= 8) {
2420 emit_opcode(cbuf, Assembler::REX_B);
2421 }
2422 %}
2423
2424 enc_class REX_reg_wide(rRegI reg)
2425 %{
2426 if ($reg$$reg < 8) {
2427 emit_opcode(cbuf, Assembler::REX_W);
2428 } else {
2429 emit_opcode(cbuf, Assembler::REX_WB);
2430 }
2431 %}
2432
2433 enc_class REX_reg_reg(rRegI dst, rRegI src)
2434 %{
2435 if ($dst$$reg < 8) {
2436 if ($src$$reg >= 8) {
2437 emit_opcode(cbuf, Assembler::REX_B);
2438 }
2439 } else {
2440 if ($src$$reg < 8) {
2441 emit_opcode(cbuf, Assembler::REX_R);
2442 } else {
2443 emit_opcode(cbuf, Assembler::REX_RB);
2444 }
2445 }
2446 %}
2447
2448 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2449 %{
2450 if ($dst$$reg < 8) {
2451 if ($src$$reg < 8) {
2452 emit_opcode(cbuf, Assembler::REX_W);
2453 } else {
2454 emit_opcode(cbuf, Assembler::REX_WB);
2455 }
2456 } else {
2457 if ($src$$reg < 8) {
2458 emit_opcode(cbuf, Assembler::REX_WR);
2459 } else {
2460 emit_opcode(cbuf, Assembler::REX_WRB);
2461 }
2462 }
2463 %}
2464
2465 enc_class REX_reg_mem(rRegI reg, memory mem)
2466 %{
2467 if ($reg$$reg < 8) {
2468 if ($mem$$base < 8) {
2469 if ($mem$$index >= 8) {
2470 emit_opcode(cbuf, Assembler::REX_X);
2471 }
2472 } else {
2473 if ($mem$$index < 8) {
2474 emit_opcode(cbuf, Assembler::REX_B);
2475 } else {
2476 emit_opcode(cbuf, Assembler::REX_XB);
2477 }
2478 }
2479 } else {
2480 if ($mem$$base < 8) {
2481 if ($mem$$index < 8) {
2482 emit_opcode(cbuf, Assembler::REX_R);
2483 } else {
2484 emit_opcode(cbuf, Assembler::REX_RX);
2485 }
2486 } else {
2487 if ($mem$$index < 8) {
2488 emit_opcode(cbuf, Assembler::REX_RB);
2489 } else {
2490 emit_opcode(cbuf, Assembler::REX_RXB);
2491 }
2492 }
2493 }
2494 %}
2495
2496 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2497 %{
2498 if ($reg$$reg < 8) {
2499 if ($mem$$base < 8) {
2500 if ($mem$$index < 8) {
2501 emit_opcode(cbuf, Assembler::REX_W);
2502 } else {
2503 emit_opcode(cbuf, Assembler::REX_WX);
2504 }
2505 } else {
2506 if ($mem$$index < 8) {
2507 emit_opcode(cbuf, Assembler::REX_WB);
2508 } else {
2509 emit_opcode(cbuf, Assembler::REX_WXB);
2510 }
2511 }
2512 } else {
2513 if ($mem$$base < 8) {
2514 if ($mem$$index < 8) {
2515 emit_opcode(cbuf, Assembler::REX_WR);
2516 } else {
2517 emit_opcode(cbuf, Assembler::REX_WRX);
2518 }
2519 } else {
2520 if ($mem$$index < 8) {
2521 emit_opcode(cbuf, Assembler::REX_WRB);
2522 } else {
2523 emit_opcode(cbuf, Assembler::REX_WRXB);
2524 }
2525 }
2526 }
2527 %}
2528
2529 enc_class reg_mem(rRegI ereg, memory mem)
2530 %{
2531 // High registers handle in encode_RegMem
2532 int reg = $ereg$$reg;
2533 int base = $mem$$base;
2534 int index = $mem$$index;
2535 int scale = $mem$$scale;
2536 int disp = $mem$$disp;
2537 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2538
2539 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2540 %}
2541
2542 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2543 %{
2544 int rm_byte_opcode = $rm_opcode$$constant;
2545
2546 // High registers handle in encode_RegMem
2547 int base = $mem$$base;
2548 int index = $mem$$index;
2549 int scale = $mem$$scale;
2550 int displace = $mem$$disp;
2551
2552 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2553 // working with static
2554 // globals
2555 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2556 disp_reloc);
2557 %}
2558
2559 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2560 %{
2561 int reg_encoding = $dst$$reg;
2562 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2563 int index = 0x04; // 0x04 indicates no index
2564 int scale = 0x00; // 0x00 indicates no scale
2565 int displace = $src1$$constant; // 0x00 indicates no displacement
2566 relocInfo::relocType disp_reloc = relocInfo::none;
2567 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2568 disp_reloc);
2569 %}
2570
2571 enc_class neg_reg(rRegI dst)
2572 %{
2573 int dstenc = $dst$$reg;
2574 if (dstenc >= 8) {
2575 emit_opcode(cbuf, Assembler::REX_B);
2576 dstenc -= 8;
2577 }
2578 // NEG $dst
2579 emit_opcode(cbuf, 0xF7);
2580 emit_rm(cbuf, 0x3, 0x03, dstenc);
2581 %}
2582
2583 enc_class neg_reg_wide(rRegI dst)
2584 %{
2585 int dstenc = $dst$$reg;
2586 if (dstenc < 8) {
2587 emit_opcode(cbuf, Assembler::REX_W);
2588 } else {
2589 emit_opcode(cbuf, Assembler::REX_WB);
2590 dstenc -= 8;
2591 }
2592 // NEG $dst
2593 emit_opcode(cbuf, 0xF7);
2594 emit_rm(cbuf, 0x3, 0x03, dstenc);
2595 %}
2596
2597 enc_class setLT_reg(rRegI dst)
2598 %{
2599 int dstenc = $dst$$reg;
2600 if (dstenc >= 8) {
2601 emit_opcode(cbuf, Assembler::REX_B);
2602 dstenc -= 8;
2603 } else if (dstenc >= 4) {
2604 emit_opcode(cbuf, Assembler::REX);
2605 }
2606 // SETLT $dst
2607 emit_opcode(cbuf, 0x0F);
2608 emit_opcode(cbuf, 0x9C);
2609 emit_rm(cbuf, 0x3, 0x0, dstenc);
2610 %}
2611
2612 enc_class setNZ_reg(rRegI dst)
2613 %{
2614 int dstenc = $dst$$reg;
2615 if (dstenc >= 8) {
2616 emit_opcode(cbuf, Assembler::REX_B);
2617 dstenc -= 8;
2618 } else if (dstenc >= 4) {
2619 emit_opcode(cbuf, Assembler::REX);
2620 }
2621 // SETNZ $dst
2622 emit_opcode(cbuf, 0x0F);
2623 emit_opcode(cbuf, 0x95);
2624 emit_rm(cbuf, 0x3, 0x0, dstenc);
2625 %}
2626
2627
2628 // Compare the lonogs and set -1, 0, or 1 into dst
2629 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2630 %{
2631 int src1enc = $src1$$reg;
2632 int src2enc = $src2$$reg;
2633 int dstenc = $dst$$reg;
2634
2635 // cmpq $src1, $src2
2636 if (src1enc < 8) {
2637 if (src2enc < 8) {
2638 emit_opcode(cbuf, Assembler::REX_W);
2639 } else {
2640 emit_opcode(cbuf, Assembler::REX_WB);
2641 }
2642 } else {
2643 if (src2enc < 8) {
2644 emit_opcode(cbuf, Assembler::REX_WR);
2645 } else {
2646 emit_opcode(cbuf, Assembler::REX_WRB);
2647 }
2648 }
2649 emit_opcode(cbuf, 0x3B);
2650 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2651
2652 // movl $dst, -1
2653 if (dstenc >= 8) {
2654 emit_opcode(cbuf, Assembler::REX_B);
2655 }
2656 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2657 emit_d32(cbuf, -1);
2658
2659 // jl,s done
2660 emit_opcode(cbuf, 0x7C);
2661 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2662
2663 // setne $dst
2664 if (dstenc >= 4) {
2665 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2666 }
2667 emit_opcode(cbuf, 0x0F);
2668 emit_opcode(cbuf, 0x95);
2669 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2670
2671 // movzbl $dst, $dst
2672 if (dstenc >= 4) {
2673 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2674 }
2675 emit_opcode(cbuf, 0x0F);
2676 emit_opcode(cbuf, 0xB6);
2677 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2678 %}
2679
2680 enc_class Push_ResultXD(regD dst) %{
2681 MacroAssembler _masm(&cbuf);
2682 __ fstp_d(Address(rsp, 0));
2683 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2684 __ addptr(rsp, 8);
2685 %}
2686
2687 enc_class Push_SrcXD(regD src) %{
2688 MacroAssembler _masm(&cbuf);
2689 __ subptr(rsp, 8);
2690 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2691 __ fld_d(Address(rsp, 0));
2692 %}
2693
2694
2695 enc_class enc_rethrow()
2696 %{
2697 cbuf.set_insts_mark();
2698 emit_opcode(cbuf, 0xE9); // jmp entry
2699 emit_d32_reloc(cbuf,
2700 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2701 runtime_call_Relocation::spec(),
2702 RELOC_DISP32);
2703 %}
2704
2705 %}
2706
2707
2708
2709 //----------FRAME--------------------------------------------------------------
2710 // Definition of frame structure and management information.
2711 //
2712 // S T A C K L A Y O U T Allocators stack-slot number
2713 // | (to get allocators register number
2714 // G Owned by | | v add OptoReg::stack0())
2715 // r CALLER | |
2716 // o | +--------+ pad to even-align allocators stack-slot
2717 // w V | pad0 | numbers; owned by CALLER
2718 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2719 // h ^ | in | 5
2720 // | | args | 4 Holes in incoming args owned by SELF
2721 // | | | | 3
2722 // | | +--------+
2723 // V | | old out| Empty on Intel, window on Sparc
2724 // | old |preserve| Must be even aligned.
2725 // | SP-+--------+----> Matcher::_old_SP, even aligned
2726 // | | in | 3 area for Intel ret address
2727 // Owned by |preserve| Empty on Sparc.
2728 // SELF +--------+
2729 // | | pad2 | 2 pad to align old SP
2730 // | +--------+ 1
2731 // | | locks | 0
2732 // | +--------+----> OptoReg::stack0(), even aligned
2733 // | | pad1 | 11 pad to align new SP
2734 // | +--------+
2735 // | | | 10
2736 // | | spills | 9 spills
2737 // V | | 8 (pad0 slot for callee)
2738 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2739 // ^ | out | 7
2740 // | | args | 6 Holes in outgoing args owned by CALLEE
2741 // Owned by +--------+
2742 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2743 // | new |preserve| Must be even-aligned.
2744 // | SP-+--------+----> Matcher::_new_SP, even aligned
2745 // | | |
2746 //
2747 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2748 // known from SELF's arguments and the Java calling convention.
2749 // Region 6-7 is determined per call site.
2750 // Note 2: If the calling convention leaves holes in the incoming argument
2751 // area, those holes are owned by SELF. Holes in the outgoing area
2752 // are owned by the CALLEE. Holes should not be nessecary in the
2753 // incoming area, as the Java calling convention is completely under
2754 // the control of the AD file. Doubles can be sorted and packed to
2755 // avoid holes. Holes in the outgoing arguments may be nessecary for
2756 // varargs C calling conventions.
2757 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2758 // even aligned with pad0 as needed.
2759 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2760 // region 6-11 is even aligned; it may be padded out more so that
2761 // the region from SP to FP meets the minimum stack alignment.
2762 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2763 // alignment. Region 11, pad1, may be dynamically extended so that
2764 // SP meets the minimum alignment.
2765
2766 frame
2767 %{
2768 // What direction does stack grow in (assumed to be same for C & Java)
2769 stack_direction(TOWARDS_LOW);
2770
2771 // These three registers define part of the calling convention
2772 // between compiled code and the interpreter.
2773 inline_cache_reg(RAX); // Inline Cache Register
2774 interpreter_method_oop_reg(RBX); // Method Oop Register when
2775 // calling interpreter
2776
2777 // Optional: name the operand used by cisc-spilling to access
2778 // [stack_pointer + offset]
2779 cisc_spilling_operand_name(indOffset32);
2780
2781 // Number of stack slots consumed by locking an object
2782 sync_stack_slots(2);
2783
2784 // Compiled code's Frame Pointer
2785 frame_pointer(RSP);
2786
2787 // Interpreter stores its frame pointer in a register which is
2788 // stored to the stack by I2CAdaptors.
2789 // I2CAdaptors convert from interpreted java to compiled java.
2790 interpreter_frame_pointer(RBP);
2791
2792 // Stack alignment requirement
2793 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2794
2795 // Number of stack slots between incoming argument block and the start of
2796 // a new frame. The PROLOG must add this many slots to the stack. The
2797 // EPILOG must remove this many slots. amd64 needs two slots for
2798 // return address.
2799 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2800
2801 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2802 // for calls to C. Supports the var-args backing area for register parms.
2803 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2804
2805 // The after-PROLOG location of the return address. Location of
2806 // return address specifies a type (REG or STACK) and a number
2807 // representing the register number (i.e. - use a register name) or
2808 // stack slot.
2809 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2810 // Otherwise, it is above the locks and verification slot and alignment word
2811 return_addr(STACK - 2 +
2812 round_to((Compile::current()->in_preserve_stack_slots() +
2813 Compile::current()->fixed_slots()),
2814 stack_alignment_in_slots()));
2815
2816 // Body of function which returns an integer array locating
2817 // arguments either in registers or in stack slots. Passed an array
2818 // of ideal registers called "sig" and a "length" count. Stack-slot
2819 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2820 // arguments for a CALLEE. Incoming stack arguments are
2821 // automatically biased by the preserve_stack_slots field above.
2822
2823 calling_convention
2824 %{
2825 // No difference between ingoing/outgoing just pass false
2826 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2827 %}
2828
2829 c_calling_convention
2830 %{
2831 // This is obviously always outgoing
2832 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2833 %}
2834
2835 // Location of compiled Java return values. Same as C for now.
2836 return_value
2837 %{
2838 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2839 "only return normal values");
2840
2841 static const int lo[Op_RegL + 1] = {
2842 0,
2843 0,
2844 RAX_num, // Op_RegN
2845 RAX_num, // Op_RegI
2846 RAX_num, // Op_RegP
2847 XMM0_num, // Op_RegF
2848 XMM0_num, // Op_RegD
2849 RAX_num // Op_RegL
2850 };
2851 static const int hi[Op_RegL + 1] = {
2852 0,
2853 0,
2854 OptoReg::Bad, // Op_RegN
2855 OptoReg::Bad, // Op_RegI
2856 RAX_H_num, // Op_RegP
2857 OptoReg::Bad, // Op_RegF
2858 XMM0b_num, // Op_RegD
2859 RAX_H_num // Op_RegL
2860 };
2861 // Excluded flags and vector registers.
2862 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2863 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2864 %}
2865 %}
2866
2867 //----------ATTRIBUTES---------------------------------------------------------
2868 //----------Operand Attributes-------------------------------------------------
2869 op_attrib op_cost(0); // Required cost attribute
2870
2871 //----------Instruction Attributes---------------------------------------------
2872 ins_attrib ins_cost(100); // Required cost attribute
2873 ins_attrib ins_size(8); // Required size attribute (in bits)
2874 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2875 // a non-matching short branch variant
2876 // of some long branch?
2877 ins_attrib ins_alignment(1); // Required alignment attribute (must
2878 // be a power of 2) specifies the
2879 // alignment that some part of the
2880 // instruction (not necessarily the
2881 // start) requires. If > 1, a
2882 // compute_padding() function must be
2883 // provided for the instruction
2884
2885 //----------OPERANDS-----------------------------------------------------------
2886 // Operand definitions must precede instruction definitions for correct parsing
2887 // in the ADLC because operands constitute user defined types which are used in
2888 // instruction definitions.
2889
2890 //----------Simple Operands----------------------------------------------------
2891 // Immediate Operands
2892 // Integer Immediate
2893 operand immI()
2894 %{
2895 match(ConI);
2896
2897 op_cost(10);
2898 format %{ %}
2899 interface(CONST_INTER);
2900 %}
2901
2902 // Constant for test vs zero
2903 operand immI0()
2904 %{
2905 predicate(n->get_int() == 0);
2906 match(ConI);
2907
2908 op_cost(0);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 // Constant for increment
2914 operand immI1()
2915 %{
2916 predicate(n->get_int() == 1);
2917 match(ConI);
2918
2919 op_cost(0);
2920 format %{ %}
2921 interface(CONST_INTER);
2922 %}
2923
2924 // Constant for decrement
2925 operand immI_M1()
2926 %{
2927 predicate(n->get_int() == -1);
2928 match(ConI);
2929
2930 op_cost(0);
2931 format %{ %}
2932 interface(CONST_INTER);
2933 %}
2934
2935 // Valid scale values for addressing modes
2936 operand immI2()
2937 %{
2938 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2939 match(ConI);
2940
2941 format %{ %}
2942 interface(CONST_INTER);
2943 %}
2944
2945 operand immI8()
2946 %{
2947 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2948 match(ConI);
2949
2950 op_cost(5);
2951 format %{ %}
2952 interface(CONST_INTER);
2953 %}
2954
2955 operand immI16()
2956 %{
2957 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2958 match(ConI);
2959
2960 op_cost(10);
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 // Int Immediate non-negative
2966 operand immU31()
2967 %{
2968 predicate(n->get_int() >= 0);
2969 match(ConI);
2970
2971 op_cost(0);
2972 format %{ %}
2973 interface(CONST_INTER);
2974 %}
2975
2976 // Constant for long shifts
2977 operand immI_32()
2978 %{
2979 predicate( n->get_int() == 32 );
2980 match(ConI);
2981
2982 op_cost(0);
2983 format %{ %}
2984 interface(CONST_INTER);
2985 %}
2986
2987 // Constant for long shifts
2988 operand immI_64()
2989 %{
2990 predicate( n->get_int() == 64 );
2991 match(ConI);
2992
2993 op_cost(0);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 // Pointer Immediate
2999 operand immP()
3000 %{
3001 match(ConP);
3002
3003 op_cost(10);
3004 format %{ %}
3005 interface(CONST_INTER);
3006 %}
3007
3008 // NULL Pointer Immediate
3009 operand immP0()
3010 %{
3011 predicate(n->get_ptr() == 0);
3012 match(ConP);
3013
3014 op_cost(5);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Pointer Immediate
3020 operand immN() %{
3021 match(ConN);
3022
3023 op_cost(10);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 operand immNKlass() %{
3029 match(ConNKlass);
3030
3031 op_cost(10);
3032 format %{ %}
3033 interface(CONST_INTER);
3034 %}
3035
3036 // NULL Pointer Immediate
3037 operand immN0() %{
3038 predicate(n->get_narrowcon() == 0);
3039 match(ConN);
3040
3041 op_cost(5);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 operand immP31()
3047 %{
3048 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3049 && (n->get_ptr() >> 31) == 0);
3050 match(ConP);
3051
3052 op_cost(5);
3053 format %{ %}
3054 interface(CONST_INTER);
3055 %}
3056
3057
3058 // Long Immediate
3059 operand immL()
3060 %{
3061 match(ConL);
3062
3063 op_cost(20);
3064 format %{ %}
3065 interface(CONST_INTER);
3066 %}
3067
3068 // Long Immediate 8-bit
3069 operand immL8()
3070 %{
3071 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3072 match(ConL);
3073
3074 op_cost(5);
3075 format %{ %}
3076 interface(CONST_INTER);
3077 %}
3078
3079 // Long Immediate 32-bit unsigned
3080 operand immUL32()
3081 %{
3082 predicate(n->get_long() == (unsigned int) (n->get_long()));
3083 match(ConL);
3084
3085 op_cost(10);
3086 format %{ %}
3087 interface(CONST_INTER);
3088 %}
3089
3090 // Long Immediate 32-bit signed
3091 operand immL32()
3092 %{
3093 predicate(n->get_long() == (int) (n->get_long()));
3094 match(ConL);
3095
3096 op_cost(15);
3097 format %{ %}
3098 interface(CONST_INTER);
3099 %}
3100
3101 // Long Immediate zero
3102 operand immL0()
3103 %{
3104 predicate(n->get_long() == 0L);
3105 match(ConL);
3106
3107 op_cost(10);
3108 format %{ %}
3109 interface(CONST_INTER);
3110 %}
3111
3112 // Constant for increment
3113 operand immL1()
3114 %{
3115 predicate(n->get_long() == 1);
3116 match(ConL);
3117
3118 format %{ %}
3119 interface(CONST_INTER);
3120 %}
3121
3122 // Constant for decrement
3123 operand immL_M1()
3124 %{
3125 predicate(n->get_long() == -1);
3126 match(ConL);
3127
3128 format %{ %}
3129 interface(CONST_INTER);
3130 %}
3131
3132 // Long Immediate: the value 10
3133 operand immL10()
3134 %{
3135 predicate(n->get_long() == 10);
3136 match(ConL);
3137
3138 format %{ %}
3139 interface(CONST_INTER);
3140 %}
3141
3142 // Long immediate from 0 to 127.
3143 // Used for a shorter form of long mul by 10.
3144 operand immL_127()
3145 %{
3146 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3147 match(ConL);
3148
3149 op_cost(10);
3150 format %{ %}
3151 interface(CONST_INTER);
3152 %}
3153
3154 // Long Immediate: low 32-bit mask
3155 operand immL_32bits()
3156 %{
3157 predicate(n->get_long() == 0xFFFFFFFFL);
3158 match(ConL);
3159 op_cost(20);
3160
3161 format %{ %}
3162 interface(CONST_INTER);
3163 %}
3164
3165 // Float Immediate zero
3166 operand immF0()
3167 %{
3168 predicate(jint_cast(n->getf()) == 0);
3169 match(ConF);
3170
3171 op_cost(5);
3172 format %{ %}
3173 interface(CONST_INTER);
3174 %}
3175
3176 // Float Immediate
3177 operand immF()
3178 %{
3179 match(ConF);
3180
3181 op_cost(15);
3182 format %{ %}
3183 interface(CONST_INTER);
3184 %}
3185
3186 // Double Immediate zero
3187 operand immD0()
3188 %{
3189 predicate(jlong_cast(n->getd()) == 0);
3190 match(ConD);
3191
3192 op_cost(5);
3193 format %{ %}
3194 interface(CONST_INTER);
3195 %}
3196
3197 // Double Immediate
3198 operand immD()
3199 %{
3200 match(ConD);
3201
3202 op_cost(15);
3203 format %{ %}
3204 interface(CONST_INTER);
3205 %}
3206
3207 // Immediates for special shifts (sign extend)
3208
3209 // Constants for increment
3210 operand immI_16()
3211 %{
3212 predicate(n->get_int() == 16);
3213 match(ConI);
3214
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 operand immI_24()
3220 %{
3221 predicate(n->get_int() == 24);
3222 match(ConI);
3223
3224 format %{ %}
3225 interface(CONST_INTER);
3226 %}
3227
3228 // Constant for byte-wide masking
3229 operand immI_255()
3230 %{
3231 predicate(n->get_int() == 255);
3232 match(ConI);
3233
3234 format %{ %}
3235 interface(CONST_INTER);
3236 %}
3237
3238 // Constant for short-wide masking
3239 operand immI_65535()
3240 %{
3241 predicate(n->get_int() == 65535);
3242 match(ConI);
3243
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 // Constant for byte-wide masking
3249 operand immL_255()
3250 %{
3251 predicate(n->get_long() == 255);
3252 match(ConL);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 // Constant for short-wide masking
3259 operand immL_65535()
3260 %{
3261 predicate(n->get_long() == 65535);
3262 match(ConL);
3263
3264 format %{ %}
3265 interface(CONST_INTER);
3266 %}
3267
3268 // Register Operands
3269 // Integer Register
3270 operand rRegI()
3271 %{
3272 constraint(ALLOC_IN_RC(int_reg));
3273 match(RegI);
3274
3275 match(rax_RegI);
3276 match(rbx_RegI);
3277 match(rcx_RegI);
3278 match(rdx_RegI);
3279 match(rdi_RegI);
3280
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 // Special Registers
3286 operand rax_RegI()
3287 %{
3288 constraint(ALLOC_IN_RC(int_rax_reg));
3289 match(RegI);
3290 match(rRegI);
3291
3292 format %{ "RAX" %}
3293 interface(REG_INTER);
3294 %}
3295
3296 // Special Registers
3297 operand rbx_RegI()
3298 %{
3299 constraint(ALLOC_IN_RC(int_rbx_reg));
3300 match(RegI);
3301 match(rRegI);
3302
3303 format %{ "RBX" %}
3304 interface(REG_INTER);
3305 %}
3306
3307 operand rcx_RegI()
3308 %{
3309 constraint(ALLOC_IN_RC(int_rcx_reg));
3310 match(RegI);
3311 match(rRegI);
3312
3313 format %{ "RCX" %}
3314 interface(REG_INTER);
3315 %}
3316
3317 operand rdx_RegI()
3318 %{
3319 constraint(ALLOC_IN_RC(int_rdx_reg));
3320 match(RegI);
3321 match(rRegI);
3322
3323 format %{ "RDX" %}
3324 interface(REG_INTER);
3325 %}
3326
3327 operand rdi_RegI()
3328 %{
3329 constraint(ALLOC_IN_RC(int_rdi_reg));
3330 match(RegI);
3331 match(rRegI);
3332
3333 format %{ "RDI" %}
3334 interface(REG_INTER);
3335 %}
3336
3337 operand no_rcx_RegI()
3338 %{
3339 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3340 match(RegI);
3341 match(rax_RegI);
3342 match(rbx_RegI);
3343 match(rdx_RegI);
3344 match(rdi_RegI);
3345
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand no_rax_rdx_RegI()
3351 %{
3352 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3353 match(RegI);
3354 match(rbx_RegI);
3355 match(rcx_RegI);
3356 match(rdi_RegI);
3357
3358 format %{ %}
3359 interface(REG_INTER);
3360 %}
3361
3362 // Pointer Register
3363 operand any_RegP()
3364 %{
3365 constraint(ALLOC_IN_RC(any_reg));
3366 match(RegP);
3367 match(rax_RegP);
3368 match(rbx_RegP);
3369 match(rdi_RegP);
3370 match(rsi_RegP);
3371 match(rbp_RegP);
3372 match(r15_RegP);
3373 match(rRegP);
3374
3375 format %{ %}
3376 interface(REG_INTER);
3377 %}
3378
3379 operand rRegP()
3380 %{
3381 constraint(ALLOC_IN_RC(ptr_reg));
3382 match(RegP);
3383 match(rax_RegP);
3384 match(rbx_RegP);
3385 match(rdi_RegP);
3386 match(rsi_RegP);
3387 match(rbp_RegP); // See Q&A below about
3388 match(r15_RegP); // r15_RegP and rbp_RegP.
3389
3390 format %{ %}
3391 interface(REG_INTER);
3392 %}
3393
3394 operand rRegN() %{
3395 constraint(ALLOC_IN_RC(int_reg));
3396 match(RegN);
3397
3398 format %{ %}
3399 interface(REG_INTER);
3400 %}
3401
3402 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3403 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3404 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3405 // The output of an instruction is controlled by the allocator, which respects
3406 // register class masks, not match rules. Unless an instruction mentions
3407 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3408 // by the allocator as an input.
3409 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3410 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3411 // result, RBP is not included in the output of the instruction either.
3412
3413 operand no_rax_RegP()
3414 %{
3415 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3416 match(RegP);
3417 match(rbx_RegP);
3418 match(rsi_RegP);
3419 match(rdi_RegP);
3420
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 // This operand is not allowed to use RBP even if
3426 // RBP is not used to hold the frame pointer.
3427 operand no_rbp_RegP()
3428 %{
3429 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3430 match(RegP);
3431 match(rbx_RegP);
3432 match(rsi_RegP);
3433 match(rdi_RegP);
3434
3435 format %{ %}
3436 interface(REG_INTER);
3437 %}
3438
3439 operand no_rax_rbx_RegP()
3440 %{
3441 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3442 match(RegP);
3443 match(rsi_RegP);
3444 match(rdi_RegP);
3445
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 // Special Registers
3451 // Return a pointer value
3452 operand rax_RegP()
3453 %{
3454 constraint(ALLOC_IN_RC(ptr_rax_reg));
3455 match(RegP);
3456 match(rRegP);
3457
3458 format %{ %}
3459 interface(REG_INTER);
3460 %}
3461
3462 // Special Registers
3463 // Return a compressed pointer value
3464 operand rax_RegN()
3465 %{
3466 constraint(ALLOC_IN_RC(int_rax_reg));
3467 match(RegN);
3468 match(rRegN);
3469
3470 format %{ %}
3471 interface(REG_INTER);
3472 %}
3473
3474 // Used in AtomicAdd
3475 operand rbx_RegP()
3476 %{
3477 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3478 match(RegP);
3479 match(rRegP);
3480
3481 format %{ %}
3482 interface(REG_INTER);
3483 %}
3484
3485 operand rsi_RegP()
3486 %{
3487 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3488 match(RegP);
3489 match(rRegP);
3490
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 // Used in rep stosq
3496 operand rdi_RegP()
3497 %{
3498 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3499 match(RegP);
3500 match(rRegP);
3501
3502 format %{ %}
3503 interface(REG_INTER);
3504 %}
3505
3506 operand r15_RegP()
3507 %{
3508 constraint(ALLOC_IN_RC(ptr_r15_reg));
3509 match(RegP);
3510 match(rRegP);
3511
3512 format %{ %}
3513 interface(REG_INTER);
3514 %}
3515
3516 operand rRegL()
3517 %{
3518 constraint(ALLOC_IN_RC(long_reg));
3519 match(RegL);
3520 match(rax_RegL);
3521 match(rdx_RegL);
3522
3523 format %{ %}
3524 interface(REG_INTER);
3525 %}
3526
3527 // Special Registers
3528 operand no_rax_rdx_RegL()
3529 %{
3530 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3531 match(RegL);
3532 match(rRegL);
3533
3534 format %{ %}
3535 interface(REG_INTER);
3536 %}
3537
3538 operand no_rax_RegL()
3539 %{
3540 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3541 match(RegL);
3542 match(rRegL);
3543 match(rdx_RegL);
3544
3545 format %{ %}
3546 interface(REG_INTER);
3547 %}
3548
3549 operand no_rcx_RegL()
3550 %{
3551 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3552 match(RegL);
3553 match(rRegL);
3554
3555 format %{ %}
3556 interface(REG_INTER);
3557 %}
3558
3559 operand rax_RegL()
3560 %{
3561 constraint(ALLOC_IN_RC(long_rax_reg));
3562 match(RegL);
3563 match(rRegL);
3564
3565 format %{ "RAX" %}
3566 interface(REG_INTER);
3567 %}
3568
3569 operand rcx_RegL()
3570 %{
3571 constraint(ALLOC_IN_RC(long_rcx_reg));
3572 match(RegL);
3573 match(rRegL);
3574
3575 format %{ %}
3576 interface(REG_INTER);
3577 %}
3578
3579 operand rdx_RegL()
3580 %{
3581 constraint(ALLOC_IN_RC(long_rdx_reg));
3582 match(RegL);
3583 match(rRegL);
3584
3585 format %{ %}
3586 interface(REG_INTER);
3587 %}
3588
3589 // Flags register, used as output of compare instructions
3590 operand rFlagsReg()
3591 %{
3592 constraint(ALLOC_IN_RC(int_flags));
3593 match(RegFlags);
3594
3595 format %{ "RFLAGS" %}
3596 interface(REG_INTER);
3597 %}
3598
3599 // Flags register, used as output of FLOATING POINT compare instructions
3600 operand rFlagsRegU()
3601 %{
3602 constraint(ALLOC_IN_RC(int_flags));
3603 match(RegFlags);
3604
3605 format %{ "RFLAGS_U" %}
3606 interface(REG_INTER);
3607 %}
3608
3609 operand rFlagsRegUCF() %{
3610 constraint(ALLOC_IN_RC(int_flags));
3611 match(RegFlags);
3612 predicate(false);
3613
3614 format %{ "RFLAGS_U_CF" %}
3615 interface(REG_INTER);
3616 %}
3617
3618 // Float register operands
3619 operand regF() %{
3620 constraint(ALLOC_IN_RC(float_reg));
3621 match(RegF);
3622
3623 format %{ %}
3624 interface(REG_INTER);
3625 %}
3626
3627 // Double register operands
3628 operand regD() %{
3629 constraint(ALLOC_IN_RC(double_reg));
3630 match(RegD);
3631
3632 format %{ %}
3633 interface(REG_INTER);
3634 %}
3635
3636 // Vectors
3637 operand vecS() %{
3638 constraint(ALLOC_IN_RC(vectors_reg));
3639 match(VecS);
3640
3641 format %{ %}
3642 interface(REG_INTER);
3643 %}
3644
3645 operand vecD() %{
3646 constraint(ALLOC_IN_RC(vectord_reg));
3647 match(VecD);
3648
3649 format %{ %}
3650 interface(REG_INTER);
3651 %}
3652
3653 operand vecX() %{
3654 constraint(ALLOC_IN_RC(vectorx_reg));
3655 match(VecX);
3656
3657 format %{ %}
3658 interface(REG_INTER);
3659 %}
3660
3661 operand vecY() %{
3662 constraint(ALLOC_IN_RC(vectory_reg));
3663 match(VecY);
3664
3665 format %{ %}
3666 interface(REG_INTER);
3667 %}
3668
3669 //----------Memory Operands----------------------------------------------------
3670 // Direct Memory Operand
3671 // operand direct(immP addr)
3672 // %{
3673 // match(addr);
3674
3675 // format %{ "[$addr]" %}
3676 // interface(MEMORY_INTER) %{
3677 // base(0xFFFFFFFF);
3678 // index(0x4);
3679 // scale(0x0);
3680 // disp($addr);
3681 // %}
3682 // %}
3683
3684 // Indirect Memory Operand
3685 operand indirect(any_RegP reg)
3686 %{
3687 constraint(ALLOC_IN_RC(ptr_reg));
3688 match(reg);
3689
3690 format %{ "[$reg]" %}
3691 interface(MEMORY_INTER) %{
3692 base($reg);
3693 index(0x4);
3694 scale(0x0);
3695 disp(0x0);
3696 %}
3697 %}
3698
3699 // Indirect Memory Plus Short Offset Operand
3700 operand indOffset8(any_RegP reg, immL8 off)
3701 %{
3702 constraint(ALLOC_IN_RC(ptr_reg));
3703 match(AddP reg off);
3704
3705 format %{ "[$reg + $off (8-bit)]" %}
3706 interface(MEMORY_INTER) %{
3707 base($reg);
3708 index(0x4);
3709 scale(0x0);
3710 disp($off);
3711 %}
3712 %}
3713
3714 // Indirect Memory Plus Long Offset Operand
3715 operand indOffset32(any_RegP reg, immL32 off)
3716 %{
3717 constraint(ALLOC_IN_RC(ptr_reg));
3718 match(AddP reg off);
3719
3720 format %{ "[$reg + $off (32-bit)]" %}
3721 interface(MEMORY_INTER) %{
3722 base($reg);
3723 index(0x4);
3724 scale(0x0);
3725 disp($off);
3726 %}
3727 %}
3728
3729 // Indirect Memory Plus Index Register Plus Offset Operand
3730 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3731 %{
3732 constraint(ALLOC_IN_RC(ptr_reg));
3733 match(AddP (AddP reg lreg) off);
3734
3735 op_cost(10);
3736 format %{"[$reg + $off + $lreg]" %}
3737 interface(MEMORY_INTER) %{
3738 base($reg);
3739 index($lreg);
3740 scale(0x0);
3741 disp($off);
3742 %}
3743 %}
3744
3745 // Indirect Memory Plus Index Register Plus Offset Operand
3746 operand indIndex(any_RegP reg, rRegL lreg)
3747 %{
3748 constraint(ALLOC_IN_RC(ptr_reg));
3749 match(AddP reg lreg);
3750
3751 op_cost(10);
3752 format %{"[$reg + $lreg]" %}
3753 interface(MEMORY_INTER) %{
3754 base($reg);
3755 index($lreg);
3756 scale(0x0);
3757 disp(0x0);
3758 %}
3759 %}
3760
3761 // Indirect Memory Times Scale Plus Index Register
3762 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3763 %{
3764 constraint(ALLOC_IN_RC(ptr_reg));
3765 match(AddP reg (LShiftL lreg scale));
3766
3767 op_cost(10);
3768 format %{"[$reg + $lreg << $scale]" %}
3769 interface(MEMORY_INTER) %{
3770 base($reg);
3771 index($lreg);
3772 scale($scale);
3773 disp(0x0);
3774 %}
3775 %}
3776
3777 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3778 %{
3779 constraint(ALLOC_IN_RC(ptr_reg));
3780 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3781 match(AddP reg (LShiftL (ConvI2L idx) scale));
3782
3783 op_cost(10);
3784 format %{"[$reg + pos $idx << $scale]" %}
3785 interface(MEMORY_INTER) %{
3786 base($reg);
3787 index($idx);
3788 scale($scale);
3789 disp(0x0);
3790 %}
3791 %}
3792
3793 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3794 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3795 %{
3796 constraint(ALLOC_IN_RC(ptr_reg));
3797 match(AddP (AddP reg (LShiftL lreg scale)) off);
3798
3799 op_cost(10);
3800 format %{"[$reg + $off + $lreg << $scale]" %}
3801 interface(MEMORY_INTER) %{
3802 base($reg);
3803 index($lreg);
3804 scale($scale);
3805 disp($off);
3806 %}
3807 %}
3808
3809 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3810 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3811 %{
3812 constraint(ALLOC_IN_RC(ptr_reg));
3813 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3814 match(AddP (AddP reg (ConvI2L idx)) off);
3815
3816 op_cost(10);
3817 format %{"[$reg + $off + $idx]" %}
3818 interface(MEMORY_INTER) %{
3819 base($reg);
3820 index($idx);
3821 scale(0x0);
3822 disp($off);
3823 %}
3824 %}
3825
3826 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3827 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3828 %{
3829 constraint(ALLOC_IN_RC(ptr_reg));
3830 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3831 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3832
3833 op_cost(10);
3834 format %{"[$reg + $off + $idx << $scale]" %}
3835 interface(MEMORY_INTER) %{
3836 base($reg);
3837 index($idx);
3838 scale($scale);
3839 disp($off);
3840 %}
3841 %}
3842
3843 // Indirect Narrow Oop Plus Offset Operand
3844 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3845 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3846 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3847 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3848 constraint(ALLOC_IN_RC(ptr_reg));
3849 match(AddP (DecodeN reg) off);
3850
3851 op_cost(10);
3852 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3853 interface(MEMORY_INTER) %{
3854 base(0xc); // R12
3855 index($reg);
3856 scale(0x3);
3857 disp($off);
3858 %}
3859 %}
3860
3861 // Indirect Memory Operand
3862 operand indirectNarrow(rRegN reg)
3863 %{
3864 predicate(Universe::narrow_oop_shift() == 0);
3865 constraint(ALLOC_IN_RC(ptr_reg));
3866 match(DecodeN reg);
3867
3868 format %{ "[$reg]" %}
3869 interface(MEMORY_INTER) %{
3870 base($reg);
3871 index(0x4);
3872 scale(0x0);
3873 disp(0x0);
3874 %}
3875 %}
3876
3877 // Indirect Memory Plus Short Offset Operand
3878 operand indOffset8Narrow(rRegN reg, immL8 off)
3879 %{
3880 predicate(Universe::narrow_oop_shift() == 0);
3881 constraint(ALLOC_IN_RC(ptr_reg));
3882 match(AddP (DecodeN reg) off);
3883
3884 format %{ "[$reg + $off (8-bit)]" %}
3885 interface(MEMORY_INTER) %{
3886 base($reg);
3887 index(0x4);
3888 scale(0x0);
3889 disp($off);
3890 %}
3891 %}
3892
3893 // Indirect Memory Plus Long Offset Operand
3894 operand indOffset32Narrow(rRegN reg, immL32 off)
3895 %{
3896 predicate(Universe::narrow_oop_shift() == 0);
3897 constraint(ALLOC_IN_RC(ptr_reg));
3898 match(AddP (DecodeN reg) off);
3899
3900 format %{ "[$reg + $off (32-bit)]" %}
3901 interface(MEMORY_INTER) %{
3902 base($reg);
3903 index(0x4);
3904 scale(0x0);
3905 disp($off);
3906 %}
3907 %}
3908
3909 // Indirect Memory Plus Index Register Plus Offset Operand
3910 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3911 %{
3912 predicate(Universe::narrow_oop_shift() == 0);
3913 constraint(ALLOC_IN_RC(ptr_reg));
3914 match(AddP (AddP (DecodeN reg) lreg) off);
3915
3916 op_cost(10);
3917 format %{"[$reg + $off + $lreg]" %}
3918 interface(MEMORY_INTER) %{
3919 base($reg);
3920 index($lreg);
3921 scale(0x0);
3922 disp($off);
3923 %}
3924 %}
3925
3926 // Indirect Memory Plus Index Register Plus Offset Operand
3927 operand indIndexNarrow(rRegN reg, rRegL lreg)
3928 %{
3929 predicate(Universe::narrow_oop_shift() == 0);
3930 constraint(ALLOC_IN_RC(ptr_reg));
3931 match(AddP (DecodeN reg) lreg);
3932
3933 op_cost(10);
3934 format %{"[$reg + $lreg]" %}
3935 interface(MEMORY_INTER) %{
3936 base($reg);
3937 index($lreg);
3938 scale(0x0);
3939 disp(0x0);
3940 %}
3941 %}
3942
3943 // Indirect Memory Times Scale Plus Index Register
3944 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3945 %{
3946 predicate(Universe::narrow_oop_shift() == 0);
3947 constraint(ALLOC_IN_RC(ptr_reg));
3948 match(AddP (DecodeN reg) (LShiftL lreg scale));
3949
3950 op_cost(10);
3951 format %{"[$reg + $lreg << $scale]" %}
3952 interface(MEMORY_INTER) %{
3953 base($reg);
3954 index($lreg);
3955 scale($scale);
3956 disp(0x0);
3957 %}
3958 %}
3959
3960 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3961 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3962 %{
3963 predicate(Universe::narrow_oop_shift() == 0);
3964 constraint(ALLOC_IN_RC(ptr_reg));
3965 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3966
3967 op_cost(10);
3968 format %{"[$reg + $off + $lreg << $scale]" %}
3969 interface(MEMORY_INTER) %{
3970 base($reg);
3971 index($lreg);
3972 scale($scale);
3973 disp($off);
3974 %}
3975 %}
3976
3977 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3978 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3979 %{
3980 constraint(ALLOC_IN_RC(ptr_reg));
3981 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3982 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3983
3984 op_cost(10);
3985 format %{"[$reg + $off + $idx]" %}
3986 interface(MEMORY_INTER) %{
3987 base($reg);
3988 index($idx);
3989 scale(0x0);
3990 disp($off);
3991 %}
3992 %}
3993
3994 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3995 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3996 %{
3997 constraint(ALLOC_IN_RC(ptr_reg));
3998 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3999 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4000
4001 op_cost(10);
4002 format %{"[$reg + $off + $idx << $scale]" %}
4003 interface(MEMORY_INTER) %{
4004 base($reg);
4005 index($idx);
4006 scale($scale);
4007 disp($off);
4008 %}
4009 %}
4010
4011 //----------Special Memory Operands--------------------------------------------
4012 // Stack Slot Operand - This operand is used for loading and storing temporary
4013 // values on the stack where a match requires a value to
4014 // flow through memory.
4015 operand stackSlotP(sRegP reg)
4016 %{
4017 constraint(ALLOC_IN_RC(stack_slots));
4018 // No match rule because this operand is only generated in matching
4019
4020 format %{ "[$reg]" %}
4021 interface(MEMORY_INTER) %{
4022 base(0x4); // RSP
4023 index(0x4); // No Index
4024 scale(0x0); // No Scale
4025 disp($reg); // Stack Offset
4026 %}
4027 %}
4028
4029 operand stackSlotI(sRegI reg)
4030 %{
4031 constraint(ALLOC_IN_RC(stack_slots));
4032 // No match rule because this operand is only generated in matching
4033
4034 format %{ "[$reg]" %}
4035 interface(MEMORY_INTER) %{
4036 base(0x4); // RSP
4037 index(0x4); // No Index
4038 scale(0x0); // No Scale
4039 disp($reg); // Stack Offset
4040 %}
4041 %}
4042
4043 operand stackSlotF(sRegF reg)
4044 %{
4045 constraint(ALLOC_IN_RC(stack_slots));
4046 // No match rule because this operand is only generated in matching
4047
4048 format %{ "[$reg]" %}
4049 interface(MEMORY_INTER) %{
4050 base(0x4); // RSP
4051 index(0x4); // No Index
4052 scale(0x0); // No Scale
4053 disp($reg); // Stack Offset
4054 %}
4055 %}
4056
4057 operand stackSlotD(sRegD reg)
4058 %{
4059 constraint(ALLOC_IN_RC(stack_slots));
4060 // No match rule because this operand is only generated in matching
4061
4062 format %{ "[$reg]" %}
4063 interface(MEMORY_INTER) %{
4064 base(0x4); // RSP
4065 index(0x4); // No Index
4066 scale(0x0); // No Scale
4067 disp($reg); // Stack Offset
4068 %}
4069 %}
4070 operand stackSlotL(sRegL reg)
4071 %{
4072 constraint(ALLOC_IN_RC(stack_slots));
4073 // No match rule because this operand is only generated in matching
4074
4075 format %{ "[$reg]" %}
4076 interface(MEMORY_INTER) %{
4077 base(0x4); // RSP
4078 index(0x4); // No Index
4079 scale(0x0); // No Scale
4080 disp($reg); // Stack Offset
4081 %}
4082 %}
4083
4084 //----------Conditional Branch Operands----------------------------------------
4085 // Comparison Op - This is the operation of the comparison, and is limited to
4086 // the following set of codes:
4087 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4088 //
4089 // Other attributes of the comparison, such as unsignedness, are specified
4090 // by the comparison instruction that sets a condition code flags register.
4091 // That result is represented by a flags operand whose subtype is appropriate
4092 // to the unsignedness (etc.) of the comparison.
4093 //
4094 // Later, the instruction which matches both the Comparison Op (a Bool) and
4095 // the flags (produced by the Cmp) specifies the coding of the comparison op
4096 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4097
4098 // Comparision Code
4099 operand cmpOp()
4100 %{
4101 match(Bool);
4102
4103 format %{ "" %}
4104 interface(COND_INTER) %{
4105 equal(0x4, "e");
4106 not_equal(0x5, "ne");
4107 less(0xC, "l");
4108 greater_equal(0xD, "ge");
4109 less_equal(0xE, "le");
4110 greater(0xF, "g");
4111 overflow(0x0, "o");
4112 no_overflow(0x1, "no");
4113 %}
4114 %}
4115
4116 // Comparison Code, unsigned compare. Used by FP also, with
4117 // C2 (unordered) turned into GT or LT already. The other bits
4118 // C0 and C3 are turned into Carry & Zero flags.
4119 operand cmpOpU()
4120 %{
4121 match(Bool);
4122
4123 format %{ "" %}
4124 interface(COND_INTER) %{
4125 equal(0x4, "e");
4126 not_equal(0x5, "ne");
4127 less(0x2, "b");
4128 greater_equal(0x3, "nb");
4129 less_equal(0x6, "be");
4130 greater(0x7, "nbe");
4131 overflow(0x0, "o");
4132 no_overflow(0x1, "no");
4133 %}
4134 %}
4135
4136
4137 // Floating comparisons that don't require any fixup for the unordered case
4138 operand cmpOpUCF() %{
4139 match(Bool);
4140 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4141 n->as_Bool()->_test._test == BoolTest::ge ||
4142 n->as_Bool()->_test._test == BoolTest::le ||
4143 n->as_Bool()->_test._test == BoolTest::gt);
4144 format %{ "" %}
4145 interface(COND_INTER) %{
4146 equal(0x4, "e");
4147 not_equal(0x5, "ne");
4148 less(0x2, "b");
4149 greater_equal(0x3, "nb");
4150 less_equal(0x6, "be");
4151 greater(0x7, "nbe");
4152 overflow(0x0, "o");
4153 no_overflow(0x1, "no");
4154 %}
4155 %}
4156
4157
4158 // Floating comparisons that can be fixed up with extra conditional jumps
4159 operand cmpOpUCF2() %{
4160 match(Bool);
4161 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4162 n->as_Bool()->_test._test == BoolTest::eq);
4163 format %{ "" %}
4164 interface(COND_INTER) %{
4165 equal(0x4, "e");
4166 not_equal(0x5, "ne");
4167 less(0x2, "b");
4168 greater_equal(0x3, "nb");
4169 less_equal(0x6, "be");
4170 greater(0x7, "nbe");
4171 overflow(0x0, "o");
4172 no_overflow(0x1, "no");
4173 %}
4174 %}
4175
4176
4177 //----------OPERAND CLASSES----------------------------------------------------
4178 // Operand Classes are groups of operands that are used as to simplify
4179 // instruction definitions by not requiring the AD writer to specify separate
4180 // instructions for every form of operand when the instruction accepts
4181 // multiple operand types with the same basic encoding and format. The classic
4182 // case of this is memory operands.
4183
4184 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4185 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4186 indCompressedOopOffset,
4187 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4188 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4189 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4190
4191 //----------PIPELINE-----------------------------------------------------------
4192 // Rules which define the behavior of the target architectures pipeline.
4193 pipeline %{
4194
4195 //----------ATTRIBUTES---------------------------------------------------------
4196 attributes %{
4197 variable_size_instructions; // Fixed size instructions
4198 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4199 instruction_unit_size = 1; // An instruction is 1 bytes long
4200 instruction_fetch_unit_size = 16; // The processor fetches one line
4201 instruction_fetch_units = 1; // of 16 bytes
4202
4203 // List of nop instructions
4204 nops( MachNop );
4205 %}
4206
4207 //----------RESOURCES----------------------------------------------------------
4208 // Resources are the functional units available to the machine
4209
4210 // Generic P2/P3 pipeline
4211 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4212 // 3 instructions decoded per cycle.
4213 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4214 // 3 ALU op, only ALU0 handles mul instructions.
4215 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4216 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4217 BR, FPU,
4218 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4219
4220 //----------PIPELINE DESCRIPTION-----------------------------------------------
4221 // Pipeline Description specifies the stages in the machine's pipeline
4222
4223 // Generic P2/P3 pipeline
4224 pipe_desc(S0, S1, S2, S3, S4, S5);
4225
4226 //----------PIPELINE CLASSES---------------------------------------------------
4227 // Pipeline Classes describe the stages in which input and output are
4228 // referenced by the hardware pipeline.
4229
4230 // Naming convention: ialu or fpu
4231 // Then: _reg
4232 // Then: _reg if there is a 2nd register
4233 // Then: _long if it's a pair of instructions implementing a long
4234 // Then: _fat if it requires the big decoder
4235 // Or: _mem if it requires the big decoder and a memory unit.
4236
4237 // Integer ALU reg operation
4238 pipe_class ialu_reg(rRegI dst)
4239 %{
4240 single_instruction;
4241 dst : S4(write);
4242 dst : S3(read);
4243 DECODE : S0; // any decoder
4244 ALU : S3; // any alu
4245 %}
4246
4247 // Long ALU reg operation
4248 pipe_class ialu_reg_long(rRegL dst)
4249 %{
4250 instruction_count(2);
4251 dst : S4(write);
4252 dst : S3(read);
4253 DECODE : S0(2); // any 2 decoders
4254 ALU : S3(2); // both alus
4255 %}
4256
4257 // Integer ALU reg operation using big decoder
4258 pipe_class ialu_reg_fat(rRegI dst)
4259 %{
4260 single_instruction;
4261 dst : S4(write);
4262 dst : S3(read);
4263 D0 : S0; // big decoder only
4264 ALU : S3; // any alu
4265 %}
4266
4267 // Long ALU reg operation using big decoder
4268 pipe_class ialu_reg_long_fat(rRegL dst)
4269 %{
4270 instruction_count(2);
4271 dst : S4(write);
4272 dst : S3(read);
4273 D0 : S0(2); // big decoder only; twice
4274 ALU : S3(2); // any 2 alus
4275 %}
4276
4277 // Integer ALU reg-reg operation
4278 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4279 %{
4280 single_instruction;
4281 dst : S4(write);
4282 src : S3(read);
4283 DECODE : S0; // any decoder
4284 ALU : S3; // any alu
4285 %}
4286
4287 // Long ALU reg-reg operation
4288 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4289 %{
4290 instruction_count(2);
4291 dst : S4(write);
4292 src : S3(read);
4293 DECODE : S0(2); // any 2 decoders
4294 ALU : S3(2); // both alus
4295 %}
4296
4297 // Integer ALU reg-reg operation
4298 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4299 %{
4300 single_instruction;
4301 dst : S4(write);
4302 src : S3(read);
4303 D0 : S0; // big decoder only
4304 ALU : S3; // any alu
4305 %}
4306
4307 // Long ALU reg-reg operation
4308 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4309 %{
4310 instruction_count(2);
4311 dst : S4(write);
4312 src : S3(read);
4313 D0 : S0(2); // big decoder only; twice
4314 ALU : S3(2); // both alus
4315 %}
4316
4317 // Integer ALU reg-mem operation
4318 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4319 %{
4320 single_instruction;
4321 dst : S5(write);
4322 mem : S3(read);
4323 D0 : S0; // big decoder only
4324 ALU : S4; // any alu
4325 MEM : S3; // any mem
4326 %}
4327
4328 // Integer mem operation (prefetch)
4329 pipe_class ialu_mem(memory mem)
4330 %{
4331 single_instruction;
4332 mem : S3(read);
4333 D0 : S0; // big decoder only
4334 MEM : S3; // any mem
4335 %}
4336
4337 // Integer Store to Memory
4338 pipe_class ialu_mem_reg(memory mem, rRegI src)
4339 %{
4340 single_instruction;
4341 mem : S3(read);
4342 src : S5(read);
4343 D0 : S0; // big decoder only
4344 ALU : S4; // any alu
4345 MEM : S3;
4346 %}
4347
4348 // // Long Store to Memory
4349 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4350 // %{
4351 // instruction_count(2);
4352 // mem : S3(read);
4353 // src : S5(read);
4354 // D0 : S0(2); // big decoder only; twice
4355 // ALU : S4(2); // any 2 alus
4356 // MEM : S3(2); // Both mems
4357 // %}
4358
4359 // Integer Store to Memory
4360 pipe_class ialu_mem_imm(memory mem)
4361 %{
4362 single_instruction;
4363 mem : S3(read);
4364 D0 : S0; // big decoder only
4365 ALU : S4; // any alu
4366 MEM : S3;
4367 %}
4368
4369 // Integer ALU0 reg-reg operation
4370 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4371 %{
4372 single_instruction;
4373 dst : S4(write);
4374 src : S3(read);
4375 D0 : S0; // Big decoder only
4376 ALU0 : S3; // only alu0
4377 %}
4378
4379 // Integer ALU0 reg-mem operation
4380 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4381 %{
4382 single_instruction;
4383 dst : S5(write);
4384 mem : S3(read);
4385 D0 : S0; // big decoder only
4386 ALU0 : S4; // ALU0 only
4387 MEM : S3; // any mem
4388 %}
4389
4390 // Integer ALU reg-reg operation
4391 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4392 %{
4393 single_instruction;
4394 cr : S4(write);
4395 src1 : S3(read);
4396 src2 : S3(read);
4397 DECODE : S0; // any decoder
4398 ALU : S3; // any alu
4399 %}
4400
4401 // Integer ALU reg-imm operation
4402 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4403 %{
4404 single_instruction;
4405 cr : S4(write);
4406 src1 : S3(read);
4407 DECODE : S0; // any decoder
4408 ALU : S3; // any alu
4409 %}
4410
4411 // Integer ALU reg-mem operation
4412 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4413 %{
4414 single_instruction;
4415 cr : S4(write);
4416 src1 : S3(read);
4417 src2 : S3(read);
4418 D0 : S0; // big decoder only
4419 ALU : S4; // any alu
4420 MEM : S3;
4421 %}
4422
4423 // Conditional move reg-reg
4424 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4425 %{
4426 instruction_count(4);
4427 y : S4(read);
4428 q : S3(read);
4429 p : S3(read);
4430 DECODE : S0(4); // any decoder
4431 %}
4432
4433 // Conditional move reg-reg
4434 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4435 %{
4436 single_instruction;
4437 dst : S4(write);
4438 src : S3(read);
4439 cr : S3(read);
4440 DECODE : S0; // any decoder
4441 %}
4442
4443 // Conditional move reg-mem
4444 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4445 %{
4446 single_instruction;
4447 dst : S4(write);
4448 src : S3(read);
4449 cr : S3(read);
4450 DECODE : S0; // any decoder
4451 MEM : S3;
4452 %}
4453
4454 // Conditional move reg-reg long
4455 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4456 %{
4457 single_instruction;
4458 dst : S4(write);
4459 src : S3(read);
4460 cr : S3(read);
4461 DECODE : S0(2); // any 2 decoders
4462 %}
4463
4464 // XXX
4465 // // Conditional move double reg-reg
4466 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4467 // %{
4468 // single_instruction;
4469 // dst : S4(write);
4470 // src : S3(read);
4471 // cr : S3(read);
4472 // DECODE : S0; // any decoder
4473 // %}
4474
4475 // Float reg-reg operation
4476 pipe_class fpu_reg(regD dst)
4477 %{
4478 instruction_count(2);
4479 dst : S3(read);
4480 DECODE : S0(2); // any 2 decoders
4481 FPU : S3;
4482 %}
4483
4484 // Float reg-reg operation
4485 pipe_class fpu_reg_reg(regD dst, regD src)
4486 %{
4487 instruction_count(2);
4488 dst : S4(write);
4489 src : S3(read);
4490 DECODE : S0(2); // any 2 decoders
4491 FPU : S3;
4492 %}
4493
4494 // Float reg-reg operation
4495 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4496 %{
4497 instruction_count(3);
4498 dst : S4(write);
4499 src1 : S3(read);
4500 src2 : S3(read);
4501 DECODE : S0(3); // any 3 decoders
4502 FPU : S3(2);
4503 %}
4504
4505 // Float reg-reg operation
4506 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4507 %{
4508 instruction_count(4);
4509 dst : S4(write);
4510 src1 : S3(read);
4511 src2 : S3(read);
4512 src3 : S3(read);
4513 DECODE : S0(4); // any 3 decoders
4514 FPU : S3(2);
4515 %}
4516
4517 // Float reg-reg operation
4518 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4519 %{
4520 instruction_count(4);
4521 dst : S4(write);
4522 src1 : S3(read);
4523 src2 : S3(read);
4524 src3 : S3(read);
4525 DECODE : S1(3); // any 3 decoders
4526 D0 : S0; // Big decoder only
4527 FPU : S3(2);
4528 MEM : S3;
4529 %}
4530
4531 // Float reg-mem operation
4532 pipe_class fpu_reg_mem(regD dst, memory mem)
4533 %{
4534 instruction_count(2);
4535 dst : S5(write);
4536 mem : S3(read);
4537 D0 : S0; // big decoder only
4538 DECODE : S1; // any decoder for FPU POP
4539 FPU : S4;
4540 MEM : S3; // any mem
4541 %}
4542
4543 // Float reg-mem operation
4544 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4545 %{
4546 instruction_count(3);
4547 dst : S5(write);
4548 src1 : S3(read);
4549 mem : S3(read);
4550 D0 : S0; // big decoder only
4551 DECODE : S1(2); // any decoder for FPU POP
4552 FPU : S4;
4553 MEM : S3; // any mem
4554 %}
4555
4556 // Float mem-reg operation
4557 pipe_class fpu_mem_reg(memory mem, regD src)
4558 %{
4559 instruction_count(2);
4560 src : S5(read);
4561 mem : S3(read);
4562 DECODE : S0; // any decoder for FPU PUSH
4563 D0 : S1; // big decoder only
4564 FPU : S4;
4565 MEM : S3; // any mem
4566 %}
4567
4568 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4569 %{
4570 instruction_count(3);
4571 src1 : S3(read);
4572 src2 : S3(read);
4573 mem : S3(read);
4574 DECODE : S0(2); // any decoder for FPU PUSH
4575 D0 : S1; // big decoder only
4576 FPU : S4;
4577 MEM : S3; // any mem
4578 %}
4579
4580 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4581 %{
4582 instruction_count(3);
4583 src1 : S3(read);
4584 src2 : S3(read);
4585 mem : S4(read);
4586 DECODE : S0; // any decoder for FPU PUSH
4587 D0 : S0(2); // big decoder only
4588 FPU : S4;
4589 MEM : S3(2); // any mem
4590 %}
4591
4592 pipe_class fpu_mem_mem(memory dst, memory src1)
4593 %{
4594 instruction_count(2);
4595 src1 : S3(read);
4596 dst : S4(read);
4597 D0 : S0(2); // big decoder only
4598 MEM : S3(2); // any mem
4599 %}
4600
4601 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4602 %{
4603 instruction_count(3);
4604 src1 : S3(read);
4605 src2 : S3(read);
4606 dst : S4(read);
4607 D0 : S0(3); // big decoder only
4608 FPU : S4;
4609 MEM : S3(3); // any mem
4610 %}
4611
4612 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4613 %{
4614 instruction_count(3);
4615 src1 : S4(read);
4616 mem : S4(read);
4617 DECODE : S0; // any decoder for FPU PUSH
4618 D0 : S0(2); // big decoder only
4619 FPU : S4;
4620 MEM : S3(2); // any mem
4621 %}
4622
4623 // Float load constant
4624 pipe_class fpu_reg_con(regD dst)
4625 %{
4626 instruction_count(2);
4627 dst : S5(write);
4628 D0 : S0; // big decoder only for the load
4629 DECODE : S1; // any decoder for FPU POP
4630 FPU : S4;
4631 MEM : S3; // any mem
4632 %}
4633
4634 // Float load constant
4635 pipe_class fpu_reg_reg_con(regD dst, regD src)
4636 %{
4637 instruction_count(3);
4638 dst : S5(write);
4639 src : S3(read);
4640 D0 : S0; // big decoder only for the load
4641 DECODE : S1(2); // any decoder for FPU POP
4642 FPU : S4;
4643 MEM : S3; // any mem
4644 %}
4645
4646 // UnConditional branch
4647 pipe_class pipe_jmp(label labl)
4648 %{
4649 single_instruction;
4650 BR : S3;
4651 %}
4652
4653 // Conditional branch
4654 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4655 %{
4656 single_instruction;
4657 cr : S1(read);
4658 BR : S3;
4659 %}
4660
4661 // Allocation idiom
4662 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4663 %{
4664 instruction_count(1); force_serialization;
4665 fixed_latency(6);
4666 heap_ptr : S3(read);
4667 DECODE : S0(3);
4668 D0 : S2;
4669 MEM : S3;
4670 ALU : S3(2);
4671 dst : S5(write);
4672 BR : S5;
4673 %}
4674
4675 // Generic big/slow expanded idiom
4676 pipe_class pipe_slow()
4677 %{
4678 instruction_count(10); multiple_bundles; force_serialization;
4679 fixed_latency(100);
4680 D0 : S0(2);
4681 MEM : S3(2);
4682 %}
4683
4684 // The real do-nothing guy
4685 pipe_class empty()
4686 %{
4687 instruction_count(0);
4688 %}
4689
4690 // Define the class for the Nop node
4691 define
4692 %{
4693 MachNop = empty;
4694 %}
4695
4696 %}
4697
4698 //----------INSTRUCTIONS-------------------------------------------------------
4699 //
4700 // match -- States which machine-independent subtree may be replaced
4701 // by this instruction.
4702 // ins_cost -- The estimated cost of this instruction is used by instruction
4703 // selection to identify a minimum cost tree of machine
4704 // instructions that matches a tree of machine-independent
4705 // instructions.
4706 // format -- A string providing the disassembly for this instruction.
4707 // The value of an instruction's operand may be inserted
4708 // by referring to it with a '$' prefix.
4709 // opcode -- Three instruction opcodes may be provided. These are referred
4710 // to within an encode class as $primary, $secondary, and $tertiary
4711 // rrspectively. The primary opcode is commonly used to
4712 // indicate the type of machine instruction, while secondary
4713 // and tertiary are often used for prefix options or addressing
4714 // modes.
4715 // ins_encode -- A list of encode classes with parameters. The encode class
4716 // name must have been defined in an 'enc_class' specification
4717 // in the encode section of the architecture description.
4718
4719
4720 //----------Load/Store/Move Instructions---------------------------------------
4721 //----------Load Instructions--------------------------------------------------
4722
4723 // Load Byte (8 bit signed)
4724 instruct loadB(rRegI dst, memory mem)
4725 %{
4726 match(Set dst (LoadB mem));
4727
4728 ins_cost(125);
4729 format %{ "movsbl $dst, $mem\t# byte" %}
4730
4731 ins_encode %{
4732 __ movsbl($dst$$Register, $mem$$Address);
4733 %}
4734
4735 ins_pipe(ialu_reg_mem);
4736 %}
4737
4738 // Load Byte (8 bit signed) into Long Register
4739 instruct loadB2L(rRegL dst, memory mem)
4740 %{
4741 match(Set dst (ConvI2L (LoadB mem)));
4742
4743 ins_cost(125);
4744 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4745
4746 ins_encode %{
4747 __ movsbq($dst$$Register, $mem$$Address);
4748 %}
4749
4750 ins_pipe(ialu_reg_mem);
4751 %}
4752
4753 // Load Unsigned Byte (8 bit UNsigned)
4754 instruct loadUB(rRegI dst, memory mem)
4755 %{
4756 match(Set dst (LoadUB mem));
4757
4758 ins_cost(125);
4759 format %{ "movzbl $dst, $mem\t# ubyte" %}
4760
4761 ins_encode %{
4762 __ movzbl($dst$$Register, $mem$$Address);
4763 %}
4764
4765 ins_pipe(ialu_reg_mem);
4766 %}
4767
4768 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4769 instruct loadUB2L(rRegL dst, memory mem)
4770 %{
4771 match(Set dst (ConvI2L (LoadUB mem)));
4772
4773 ins_cost(125);
4774 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4775
4776 ins_encode %{
4777 __ movzbq($dst$$Register, $mem$$Address);
4778 %}
4779
4780 ins_pipe(ialu_reg_mem);
4781 %}
4782
4783 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4784 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4785 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4786 effect(KILL cr);
4787
4788 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4789 "andl $dst, right_n_bits($mask, 8)" %}
4790 ins_encode %{
4791 Register Rdst = $dst$$Register;
4792 __ movzbq(Rdst, $mem$$Address);
4793 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4794 %}
4795 ins_pipe(ialu_reg_mem);
4796 %}
4797
4798 // Load Short (16 bit signed)
4799 instruct loadS(rRegI dst, memory mem)
4800 %{
4801 match(Set dst (LoadS mem));
4802
4803 ins_cost(125);
4804 format %{ "movswl $dst, $mem\t# short" %}
4805
4806 ins_encode %{
4807 __ movswl($dst$$Register, $mem$$Address);
4808 %}
4809
4810 ins_pipe(ialu_reg_mem);
4811 %}
4812
4813 // Load Short (16 bit signed) to Byte (8 bit signed)
4814 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4815 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4816
4817 ins_cost(125);
4818 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4819 ins_encode %{
4820 __ movsbl($dst$$Register, $mem$$Address);
4821 %}
4822 ins_pipe(ialu_reg_mem);
4823 %}
4824
4825 // Load Short (16 bit signed) into Long Register
4826 instruct loadS2L(rRegL dst, memory mem)
4827 %{
4828 match(Set dst (ConvI2L (LoadS mem)));
4829
4830 ins_cost(125);
4831 format %{ "movswq $dst, $mem\t# short -> long" %}
4832
4833 ins_encode %{
4834 __ movswq($dst$$Register, $mem$$Address);
4835 %}
4836
4837 ins_pipe(ialu_reg_mem);
4838 %}
4839
4840 // Load Unsigned Short/Char (16 bit UNsigned)
4841 instruct loadUS(rRegI dst, memory mem)
4842 %{
4843 match(Set dst (LoadUS mem));
4844
4845 ins_cost(125);
4846 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4847
4848 ins_encode %{
4849 __ movzwl($dst$$Register, $mem$$Address);
4850 %}
4851
4852 ins_pipe(ialu_reg_mem);
4853 %}
4854
4855 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4856 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4857 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4858
4859 ins_cost(125);
4860 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4861 ins_encode %{
4862 __ movsbl($dst$$Register, $mem$$Address);
4863 %}
4864 ins_pipe(ialu_reg_mem);
4865 %}
4866
4867 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4868 instruct loadUS2L(rRegL dst, memory mem)
4869 %{
4870 match(Set dst (ConvI2L (LoadUS mem)));
4871
4872 ins_cost(125);
4873 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4874
4875 ins_encode %{
4876 __ movzwq($dst$$Register, $mem$$Address);
4877 %}
4878
4879 ins_pipe(ialu_reg_mem);
4880 %}
4881
4882 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4883 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4884 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4885
4886 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4887 ins_encode %{
4888 __ movzbq($dst$$Register, $mem$$Address);
4889 %}
4890 ins_pipe(ialu_reg_mem);
4891 %}
4892
4893 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4894 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4895 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4896 effect(KILL cr);
4897
4898 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4899 "andl $dst, right_n_bits($mask, 16)" %}
4900 ins_encode %{
4901 Register Rdst = $dst$$Register;
4902 __ movzwq(Rdst, $mem$$Address);
4903 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4904 %}
4905 ins_pipe(ialu_reg_mem);
4906 %}
4907
4908 // Load Integer
4909 instruct loadI(rRegI dst, memory mem)
4910 %{
4911 match(Set dst (LoadI mem));
4912
4913 ins_cost(125);
4914 format %{ "movl $dst, $mem\t# int" %}
4915
4916 ins_encode %{
4917 __ movl($dst$$Register, $mem$$Address);
4918 %}
4919
4920 ins_pipe(ialu_reg_mem);
4921 %}
4922
4923 // Load Integer (32 bit signed) to Byte (8 bit signed)
4924 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4925 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4926
4927 ins_cost(125);
4928 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4929 ins_encode %{
4930 __ movsbl($dst$$Register, $mem$$Address);
4931 %}
4932 ins_pipe(ialu_reg_mem);
4933 %}
4934
4935 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4936 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4937 match(Set dst (AndI (LoadI mem) mask));
4938
4939 ins_cost(125);
4940 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4941 ins_encode %{
4942 __ movzbl($dst$$Register, $mem$$Address);
4943 %}
4944 ins_pipe(ialu_reg_mem);
4945 %}
4946
4947 // Load Integer (32 bit signed) to Short (16 bit signed)
4948 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4949 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4950
4951 ins_cost(125);
4952 format %{ "movswl $dst, $mem\t# int -> short" %}
4953 ins_encode %{
4954 __ movswl($dst$$Register, $mem$$Address);
4955 %}
4956 ins_pipe(ialu_reg_mem);
4957 %}
4958
4959 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4960 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4961 match(Set dst (AndI (LoadI mem) mask));
4962
4963 ins_cost(125);
4964 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4965 ins_encode %{
4966 __ movzwl($dst$$Register, $mem$$Address);
4967 %}
4968 ins_pipe(ialu_reg_mem);
4969 %}
4970
4971 // Load Integer into Long Register
4972 instruct loadI2L(rRegL dst, memory mem)
4973 %{
4974 match(Set dst (ConvI2L (LoadI mem)));
4975
4976 ins_cost(125);
4977 format %{ "movslq $dst, $mem\t# int -> long" %}
4978
4979 ins_encode %{
4980 __ movslq($dst$$Register, $mem$$Address);
4981 %}
4982
4983 ins_pipe(ialu_reg_mem);
4984 %}
4985
4986 // Load Integer with mask 0xFF into Long Register
4987 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4988 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4989
4990 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4991 ins_encode %{
4992 __ movzbq($dst$$Register, $mem$$Address);
4993 %}
4994 ins_pipe(ialu_reg_mem);
4995 %}
4996
4997 // Load Integer with mask 0xFFFF into Long Register
4998 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4999 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5000
5001 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5002 ins_encode %{
5003 __ movzwq($dst$$Register, $mem$$Address);
5004 %}
5005 ins_pipe(ialu_reg_mem);
5006 %}
5007
5008 // Load Integer with a 31-bit mask into Long Register
5009 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5010 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5011 effect(KILL cr);
5012
5013 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5014 "andl $dst, $mask" %}
5015 ins_encode %{
5016 Register Rdst = $dst$$Register;
5017 __ movl(Rdst, $mem$$Address);
5018 __ andl(Rdst, $mask$$constant);
5019 %}
5020 ins_pipe(ialu_reg_mem);
5021 %}
5022
5023 // Load Unsigned Integer into Long Register
5024 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5025 %{
5026 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5027
5028 ins_cost(125);
5029 format %{ "movl $dst, $mem\t# uint -> long" %}
5030
5031 ins_encode %{
5032 __ movl($dst$$Register, $mem$$Address);
5033 %}
5034
5035 ins_pipe(ialu_reg_mem);
5036 %}
5037
5038 // Load Long
5039 instruct loadL(rRegL dst, memory mem)
5040 %{
5041 match(Set dst (LoadL mem));
5042
5043 ins_cost(125);
5044 format %{ "movq $dst, $mem\t# long" %}
5045
5046 ins_encode %{
5047 __ movq($dst$$Register, $mem$$Address);
5048 %}
5049
5050 ins_pipe(ialu_reg_mem); // XXX
5051 %}
5052
5053 // Load Range
5054 instruct loadRange(rRegI dst, memory mem)
5055 %{
5056 match(Set dst (LoadRange mem));
5057
5058 ins_cost(125); // XXX
5059 format %{ "movl $dst, $mem\t# range" %}
5060 opcode(0x8B);
5061 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5062 ins_pipe(ialu_reg_mem);
5063 %}
5064
5065 // Load Pointer
5066 instruct loadP(rRegP dst, memory mem)
5067 %{
5068 match(Set dst (LoadP mem));
5069
5070 ins_cost(125); // XXX
5071 format %{ "movq $dst, $mem\t# ptr" %}
5072 opcode(0x8B);
5073 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5074 ins_pipe(ialu_reg_mem); // XXX
5075 %}
5076
5077 // Load Compressed Pointer
5078 instruct loadN(rRegN dst, memory mem)
5079 %{
5080 match(Set dst (LoadN mem));
5081
5082 ins_cost(125); // XXX
5083 format %{ "movl $dst, $mem\t# compressed ptr" %}
5084 ins_encode %{
5085 __ movl($dst$$Register, $mem$$Address);
5086 %}
5087 ins_pipe(ialu_reg_mem); // XXX
5088 %}
5089
5090
5091 // Load Klass Pointer
5092 instruct loadKlass(rRegP dst, memory mem)
5093 %{
5094 match(Set dst (LoadKlass mem));
5095
5096 ins_cost(125); // XXX
5097 format %{ "movq $dst, $mem\t# class" %}
5098 opcode(0x8B);
5099 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5100 ins_pipe(ialu_reg_mem); // XXX
5101 %}
5102
5103 // Load narrow Klass Pointer
5104 instruct loadNKlass(rRegN dst, memory mem)
5105 %{
5106 match(Set dst (LoadNKlass mem));
5107
5108 ins_cost(125); // XXX
5109 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5110 ins_encode %{
5111 __ movl($dst$$Register, $mem$$Address);
5112 %}
5113 ins_pipe(ialu_reg_mem); // XXX
5114 %}
5115
5116 // Load Float
5117 instruct loadF(regF dst, memory mem)
5118 %{
5119 match(Set dst (LoadF mem));
5120
5121 ins_cost(145); // XXX
5122 format %{ "movss $dst, $mem\t# float" %}
5123 ins_encode %{
5124 __ movflt($dst$$XMMRegister, $mem$$Address);
5125 %}
5126 ins_pipe(pipe_slow); // XXX
5127 %}
5128
5129 // Load Double
5130 instruct loadD_partial(regD dst, memory mem)
5131 %{
5132 predicate(!UseXmmLoadAndClearUpper);
5133 match(Set dst (LoadD mem));
5134
5135 ins_cost(145); // XXX
5136 format %{ "movlpd $dst, $mem\t# double" %}
5137 ins_encode %{
5138 __ movdbl($dst$$XMMRegister, $mem$$Address);
5139 %}
5140 ins_pipe(pipe_slow); // XXX
5141 %}
5142
5143 instruct loadD(regD dst, memory mem)
5144 %{
5145 predicate(UseXmmLoadAndClearUpper);
5146 match(Set dst (LoadD mem));
5147
5148 ins_cost(145); // XXX
5149 format %{ "movsd $dst, $mem\t# double" %}
5150 ins_encode %{
5151 __ movdbl($dst$$XMMRegister, $mem$$Address);
5152 %}
5153 ins_pipe(pipe_slow); // XXX
5154 %}
5155
5156 // Load Effective Address
5157 instruct leaP8(rRegP dst, indOffset8 mem)
5158 %{
5159 match(Set dst mem);
5160
5161 ins_cost(110); // XXX
5162 format %{ "leaq $dst, $mem\t# ptr 8" %}
5163 opcode(0x8D);
5164 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5165 ins_pipe(ialu_reg_reg_fat);
5166 %}
5167
5168 instruct leaP32(rRegP dst, indOffset32 mem)
5169 %{
5170 match(Set dst mem);
5171
5172 ins_cost(110);
5173 format %{ "leaq $dst, $mem\t# ptr 32" %}
5174 opcode(0x8D);
5175 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5176 ins_pipe(ialu_reg_reg_fat);
5177 %}
5178
5179 // instruct leaPIdx(rRegP dst, indIndex mem)
5180 // %{
5181 // match(Set dst mem);
5182
5183 // ins_cost(110);
5184 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5185 // opcode(0x8D);
5186 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5187 // ins_pipe(ialu_reg_reg_fat);
5188 // %}
5189
5190 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5191 %{
5192 match(Set dst mem);
5193
5194 ins_cost(110);
5195 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5196 opcode(0x8D);
5197 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5198 ins_pipe(ialu_reg_reg_fat);
5199 %}
5200
5201 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5202 %{
5203 match(Set dst mem);
5204
5205 ins_cost(110);
5206 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5207 opcode(0x8D);
5208 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5209 ins_pipe(ialu_reg_reg_fat);
5210 %}
5211
5212 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5213 %{
5214 match(Set dst mem);
5215
5216 ins_cost(110);
5217 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5218 opcode(0x8D);
5219 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5220 ins_pipe(ialu_reg_reg_fat);
5221 %}
5222
5223 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5224 %{
5225 match(Set dst mem);
5226
5227 ins_cost(110);
5228 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5229 opcode(0x8D);
5230 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5231 ins_pipe(ialu_reg_reg_fat);
5232 %}
5233
5234 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5235 %{
5236 match(Set dst mem);
5237
5238 ins_cost(110);
5239 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5240 opcode(0x8D);
5241 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5242 ins_pipe(ialu_reg_reg_fat);
5243 %}
5244
5245 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5246 %{
5247 match(Set dst mem);
5248
5249 ins_cost(110);
5250 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5251 opcode(0x8D);
5252 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5253 ins_pipe(ialu_reg_reg_fat);
5254 %}
5255
5256 // Load Effective Address which uses Narrow (32-bits) oop
5257 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5258 %{
5259 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5260 match(Set dst mem);
5261
5262 ins_cost(110);
5263 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5264 opcode(0x8D);
5265 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5266 ins_pipe(ialu_reg_reg_fat);
5267 %}
5268
5269 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5270 %{
5271 predicate(Universe::narrow_oop_shift() == 0);
5272 match(Set dst mem);
5273
5274 ins_cost(110); // XXX
5275 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5276 opcode(0x8D);
5277 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5278 ins_pipe(ialu_reg_reg_fat);
5279 %}
5280
5281 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5282 %{
5283 predicate(Universe::narrow_oop_shift() == 0);
5284 match(Set dst mem);
5285
5286 ins_cost(110);
5287 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5288 opcode(0x8D);
5289 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5290 ins_pipe(ialu_reg_reg_fat);
5291 %}
5292
5293 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5294 %{
5295 predicate(Universe::narrow_oop_shift() == 0);
5296 match(Set dst mem);
5297
5298 ins_cost(110);
5299 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5300 opcode(0x8D);
5301 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5302 ins_pipe(ialu_reg_reg_fat);
5303 %}
5304
5305 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5306 %{
5307 predicate(Universe::narrow_oop_shift() == 0);
5308 match(Set dst mem);
5309
5310 ins_cost(110);
5311 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5312 opcode(0x8D);
5313 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5314 ins_pipe(ialu_reg_reg_fat);
5315 %}
5316
5317 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5318 %{
5319 predicate(Universe::narrow_oop_shift() == 0);
5320 match(Set dst mem);
5321
5322 ins_cost(110);
5323 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5324 opcode(0x8D);
5325 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5326 ins_pipe(ialu_reg_reg_fat);
5327 %}
5328
5329 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5330 %{
5331 predicate(Universe::narrow_oop_shift() == 0);
5332 match(Set dst mem);
5333
5334 ins_cost(110);
5335 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5336 opcode(0x8D);
5337 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5338 ins_pipe(ialu_reg_reg_fat);
5339 %}
5340
5341 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5342 %{
5343 predicate(Universe::narrow_oop_shift() == 0);
5344 match(Set dst mem);
5345
5346 ins_cost(110);
5347 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5348 opcode(0x8D);
5349 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5350 ins_pipe(ialu_reg_reg_fat);
5351 %}
5352
5353 instruct loadConI(rRegI dst, immI src)
5354 %{
5355 match(Set dst src);
5356
5357 format %{ "movl $dst, $src\t# int" %}
5358 ins_encode(load_immI(dst, src));
5359 ins_pipe(ialu_reg_fat); // XXX
5360 %}
5361
5362 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5363 %{
5364 match(Set dst src);
5365 effect(KILL cr);
5366
5367 ins_cost(50);
5368 format %{ "xorl $dst, $dst\t# int" %}
5369 opcode(0x33); /* + rd */
5370 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5371 ins_pipe(ialu_reg);
5372 %}
5373
5374 instruct loadConL(rRegL dst, immL src)
5375 %{
5376 match(Set dst src);
5377
5378 ins_cost(150);
5379 format %{ "movq $dst, $src\t# long" %}
5380 ins_encode(load_immL(dst, src));
5381 ins_pipe(ialu_reg);
5382 %}
5383
5384 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5385 %{
5386 match(Set dst src);
5387 effect(KILL cr);
5388
5389 ins_cost(50);
5390 format %{ "xorl $dst, $dst\t# long" %}
5391 opcode(0x33); /* + rd */
5392 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5393 ins_pipe(ialu_reg); // XXX
5394 %}
5395
5396 instruct loadConUL32(rRegL dst, immUL32 src)
5397 %{
5398 match(Set dst src);
5399
5400 ins_cost(60);
5401 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5402 ins_encode(load_immUL32(dst, src));
5403 ins_pipe(ialu_reg);
5404 %}
5405
5406 instruct loadConL32(rRegL dst, immL32 src)
5407 %{
5408 match(Set dst src);
5409
5410 ins_cost(70);
5411 format %{ "movq $dst, $src\t# long (32-bit)" %}
5412 ins_encode(load_immL32(dst, src));
5413 ins_pipe(ialu_reg);
5414 %}
5415
5416 instruct loadConP(rRegP dst, immP con) %{
5417 match(Set dst con);
5418
5419 format %{ "movq $dst, $con\t# ptr" %}
5420 ins_encode(load_immP(dst, con));
5421 ins_pipe(ialu_reg_fat); // XXX
5422 %}
5423
5424 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5425 %{
5426 match(Set dst src);
5427 effect(KILL cr);
5428
5429 ins_cost(50);
5430 format %{ "xorl $dst, $dst\t# ptr" %}
5431 opcode(0x33); /* + rd */
5432 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5433 ins_pipe(ialu_reg);
5434 %}
5435
5436 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5437 %{
5438 match(Set dst src);
5439 effect(KILL cr);
5440
5441 ins_cost(60);
5442 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5443 ins_encode(load_immP31(dst, src));
5444 ins_pipe(ialu_reg);
5445 %}
5446
5447 instruct loadConF(regF dst, immF con) %{
5448 match(Set dst con);
5449 ins_cost(125);
5450 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5451 ins_encode %{
5452 __ movflt($dst$$XMMRegister, $constantaddress($con));
5453 %}
5454 ins_pipe(pipe_slow);
5455 %}
5456
5457 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5458 match(Set dst src);
5459 effect(KILL cr);
5460 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5461 ins_encode %{
5462 __ xorq($dst$$Register, $dst$$Register);
5463 %}
5464 ins_pipe(ialu_reg);
5465 %}
5466
5467 instruct loadConN(rRegN dst, immN src) %{
5468 match(Set dst src);
5469
5470 ins_cost(125);
5471 format %{ "movl $dst, $src\t# compressed ptr" %}
5472 ins_encode %{
5473 address con = (address)$src$$constant;
5474 if (con == NULL) {
5475 ShouldNotReachHere();
5476 } else {
5477 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5478 }
5479 %}
5480 ins_pipe(ialu_reg_fat); // XXX
5481 %}
5482
5483 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5484 match(Set dst src);
5485
5486 ins_cost(125);
5487 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5488 ins_encode %{
5489 address con = (address)$src$$constant;
5490 if (con == NULL) {
5491 ShouldNotReachHere();
5492 } else {
5493 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5494 }
5495 %}
5496 ins_pipe(ialu_reg_fat); // XXX
5497 %}
5498
5499 instruct loadConF0(regF dst, immF0 src)
5500 %{
5501 match(Set dst src);
5502 ins_cost(100);
5503
5504 format %{ "xorps $dst, $dst\t# float 0.0" %}
5505 ins_encode %{
5506 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5507 %}
5508 ins_pipe(pipe_slow);
5509 %}
5510
5511 // Use the same format since predicate() can not be used here.
5512 instruct loadConD(regD dst, immD con) %{
5513 match(Set dst con);
5514 ins_cost(125);
5515 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5516 ins_encode %{
5517 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5518 %}
5519 ins_pipe(pipe_slow);
5520 %}
5521
5522 instruct loadConD0(regD dst, immD0 src)
5523 %{
5524 match(Set dst src);
5525 ins_cost(100);
5526
5527 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5528 ins_encode %{
5529 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5530 %}
5531 ins_pipe(pipe_slow);
5532 %}
5533
5534 instruct loadSSI(rRegI dst, stackSlotI src)
5535 %{
5536 match(Set dst src);
5537
5538 ins_cost(125);
5539 format %{ "movl $dst, $src\t# int stk" %}
5540 opcode(0x8B);
5541 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5542 ins_pipe(ialu_reg_mem);
5543 %}
5544
5545 instruct loadSSL(rRegL dst, stackSlotL src)
5546 %{
5547 match(Set dst src);
5548
5549 ins_cost(125);
5550 format %{ "movq $dst, $src\t# long stk" %}
5551 opcode(0x8B);
5552 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5553 ins_pipe(ialu_reg_mem);
5554 %}
5555
5556 instruct loadSSP(rRegP dst, stackSlotP src)
5557 %{
5558 match(Set dst src);
5559
5560 ins_cost(125);
5561 format %{ "movq $dst, $src\t# ptr stk" %}
5562 opcode(0x8B);
5563 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5564 ins_pipe(ialu_reg_mem);
5565 %}
5566
5567 instruct loadSSF(regF dst, stackSlotF src)
5568 %{
5569 match(Set dst src);
5570
5571 ins_cost(125);
5572 format %{ "movss $dst, $src\t# float stk" %}
5573 ins_encode %{
5574 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5575 %}
5576 ins_pipe(pipe_slow); // XXX
5577 %}
5578
5579 // Use the same format since predicate() can not be used here.
5580 instruct loadSSD(regD dst, stackSlotD src)
5581 %{
5582 match(Set dst src);
5583
5584 ins_cost(125);
5585 format %{ "movsd $dst, $src\t# double stk" %}
5586 ins_encode %{
5587 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5588 %}
5589 ins_pipe(pipe_slow); // XXX
5590 %}
5591
5592 // Prefetch instructions for allocation.
5593 // Must be safe to execute with invalid address (cannot fault).
5594
5595 instruct prefetchAlloc( memory mem ) %{
5596 predicate(AllocatePrefetchInstr==3);
5597 match(PrefetchAllocation mem);
5598 ins_cost(125);
5599
5600 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5601 ins_encode %{
5602 __ prefetchw($mem$$Address);
5603 %}
5604 ins_pipe(ialu_mem);
5605 %}
5606
5607 instruct prefetchAllocNTA( memory mem ) %{
5608 predicate(AllocatePrefetchInstr==0);
5609 match(PrefetchAllocation mem);
5610 ins_cost(125);
5611
5612 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5613 ins_encode %{
5614 __ prefetchnta($mem$$Address);
5615 %}
5616 ins_pipe(ialu_mem);
5617 %}
5618
5619 instruct prefetchAllocT0( memory mem ) %{
5620 predicate(AllocatePrefetchInstr==1);
5621 match(PrefetchAllocation mem);
5622 ins_cost(125);
5623
5624 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5625 ins_encode %{
5626 __ prefetcht0($mem$$Address);
5627 %}
5628 ins_pipe(ialu_mem);
5629 %}
5630
5631 instruct prefetchAllocT2( memory mem ) %{
5632 predicate(AllocatePrefetchInstr==2);
5633 match(PrefetchAllocation mem);
5634 ins_cost(125);
5635
5636 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5637 ins_encode %{
5638 __ prefetcht2($mem$$Address);
5639 %}
5640 ins_pipe(ialu_mem);
5641 %}
5642
5643 //----------Store Instructions-------------------------------------------------
5644
5645 // Store Byte
5646 instruct storeB(memory mem, rRegI src)
5647 %{
5648 match(Set mem (StoreB mem src));
5649
5650 ins_cost(125); // XXX
5651 format %{ "movb $mem, $src\t# byte" %}
5652 opcode(0x88);
5653 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5654 ins_pipe(ialu_mem_reg);
5655 %}
5656
5657 // Store Char/Short
5658 instruct storeC(memory mem, rRegI src)
5659 %{
5660 match(Set mem (StoreC mem src));
5661
5662 ins_cost(125); // XXX
5663 format %{ "movw $mem, $src\t# char/short" %}
5664 opcode(0x89);
5665 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5666 ins_pipe(ialu_mem_reg);
5667 %}
5668
5669 // Store Integer
5670 instruct storeI(memory mem, rRegI src)
5671 %{
5672 match(Set mem (StoreI mem src));
5673
5674 ins_cost(125); // XXX
5675 format %{ "movl $mem, $src\t# int" %}
5676 opcode(0x89);
5677 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5678 ins_pipe(ialu_mem_reg);
5679 %}
5680
5681 // Store Long
5682 instruct storeL(memory mem, rRegL src)
5683 %{
5684 match(Set mem (StoreL mem src));
5685
5686 ins_cost(125); // XXX
5687 format %{ "movq $mem, $src\t# long" %}
5688 opcode(0x89);
5689 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5690 ins_pipe(ialu_mem_reg); // XXX
5691 %}
5692
5693 // Store Pointer
5694 instruct storeP(memory mem, any_RegP src)
5695 %{
5696 match(Set mem (StoreP mem src));
5697
5698 ins_cost(125); // XXX
5699 format %{ "movq $mem, $src\t# ptr" %}
5700 opcode(0x89);
5701 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5702 ins_pipe(ialu_mem_reg);
5703 %}
5704
5705 instruct storeImmP0(memory mem, immP0 zero)
5706 %{
5707 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5708 match(Set mem (StoreP mem zero));
5709
5710 ins_cost(125); // XXX
5711 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5712 ins_encode %{
5713 __ movq($mem$$Address, r12);
5714 %}
5715 ins_pipe(ialu_mem_reg);
5716 %}
5717
5718 // Store NULL Pointer, mark word, or other simple pointer constant.
5719 instruct storeImmP(memory mem, immP31 src)
5720 %{
5721 match(Set mem (StoreP mem src));
5722
5723 ins_cost(150); // XXX
5724 format %{ "movq $mem, $src\t# ptr" %}
5725 opcode(0xC7); /* C7 /0 */
5726 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5727 ins_pipe(ialu_mem_imm);
5728 %}
5729
5730 // Store Compressed Pointer
5731 instruct storeN(memory mem, rRegN src)
5732 %{
5733 match(Set mem (StoreN mem src));
5734
5735 ins_cost(125); // XXX
5736 format %{ "movl $mem, $src\t# compressed ptr" %}
5737 ins_encode %{
5738 __ movl($mem$$Address, $src$$Register);
5739 %}
5740 ins_pipe(ialu_mem_reg);
5741 %}
5742
5743 instruct storeNKlass(memory mem, rRegN src)
5744 %{
5745 match(Set mem (StoreNKlass mem src));
5746
5747 ins_cost(125); // XXX
5748 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5749 ins_encode %{
5750 __ movl($mem$$Address, $src$$Register);
5751 %}
5752 ins_pipe(ialu_mem_reg);
5753 %}
5754
5755 instruct storeImmN0(memory mem, immN0 zero)
5756 %{
5757 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5758 match(Set mem (StoreN mem zero));
5759
5760 ins_cost(125); // XXX
5761 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5762 ins_encode %{
5763 __ movl($mem$$Address, r12);
5764 %}
5765 ins_pipe(ialu_mem_reg);
5766 %}
5767
5768 instruct storeImmN(memory mem, immN src)
5769 %{
5770 match(Set mem (StoreN mem src));
5771
5772 ins_cost(150); // XXX
5773 format %{ "movl $mem, $src\t# compressed ptr" %}
5774 ins_encode %{
5775 address con = (address)$src$$constant;
5776 if (con == NULL) {
5777 __ movl($mem$$Address, (int32_t)0);
5778 } else {
5779 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5780 }
5781 %}
5782 ins_pipe(ialu_mem_imm);
5783 %}
5784
5785 instruct storeImmNKlass(memory mem, immNKlass src)
5786 %{
5787 match(Set mem (StoreNKlass mem src));
5788
5789 ins_cost(150); // XXX
5790 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5791 ins_encode %{
5792 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5793 %}
5794 ins_pipe(ialu_mem_imm);
5795 %}
5796
5797 // Store Integer Immediate
5798 instruct storeImmI0(memory mem, immI0 zero)
5799 %{
5800 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5801 match(Set mem (StoreI mem zero));
5802
5803 ins_cost(125); // XXX
5804 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5805 ins_encode %{
5806 __ movl($mem$$Address, r12);
5807 %}
5808 ins_pipe(ialu_mem_reg);
5809 %}
5810
5811 instruct storeImmI(memory mem, immI src)
5812 %{
5813 match(Set mem (StoreI mem src));
5814
5815 ins_cost(150);
5816 format %{ "movl $mem, $src\t# int" %}
5817 opcode(0xC7); /* C7 /0 */
5818 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5819 ins_pipe(ialu_mem_imm);
5820 %}
5821
5822 // Store Long Immediate
5823 instruct storeImmL0(memory mem, immL0 zero)
5824 %{
5825 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5826 match(Set mem (StoreL mem zero));
5827
5828 ins_cost(125); // XXX
5829 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5830 ins_encode %{
5831 __ movq($mem$$Address, r12);
5832 %}
5833 ins_pipe(ialu_mem_reg);
5834 %}
5835
5836 instruct storeImmL(memory mem, immL32 src)
5837 %{
5838 match(Set mem (StoreL mem src));
5839
5840 ins_cost(150);
5841 format %{ "movq $mem, $src\t# long" %}
5842 opcode(0xC7); /* C7 /0 */
5843 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5844 ins_pipe(ialu_mem_imm);
5845 %}
5846
5847 // Store Short/Char Immediate
5848 instruct storeImmC0(memory mem, immI0 zero)
5849 %{
5850 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5851 match(Set mem (StoreC mem zero));
5852
5853 ins_cost(125); // XXX
5854 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5855 ins_encode %{
5856 __ movw($mem$$Address, r12);
5857 %}
5858 ins_pipe(ialu_mem_reg);
5859 %}
5860
5861 instruct storeImmI16(memory mem, immI16 src)
5862 %{
5863 predicate(UseStoreImmI16);
5864 match(Set mem (StoreC mem src));
5865
5866 ins_cost(150);
5867 format %{ "movw $mem, $src\t# short/char" %}
5868 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5869 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5870 ins_pipe(ialu_mem_imm);
5871 %}
5872
5873 // Store Byte Immediate
5874 instruct storeImmB0(memory mem, immI0 zero)
5875 %{
5876 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5877 match(Set mem (StoreB mem zero));
5878
5879 ins_cost(125); // XXX
5880 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5881 ins_encode %{
5882 __ movb($mem$$Address, r12);
5883 %}
5884 ins_pipe(ialu_mem_reg);
5885 %}
5886
5887 instruct storeImmB(memory mem, immI8 src)
5888 %{
5889 match(Set mem (StoreB mem src));
5890
5891 ins_cost(150); // XXX
5892 format %{ "movb $mem, $src\t# byte" %}
5893 opcode(0xC6); /* C6 /0 */
5894 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5895 ins_pipe(ialu_mem_imm);
5896 %}
5897
5898 // Store CMS card-mark Immediate
5899 instruct storeImmCM0_reg(memory mem, immI0 zero)
5900 %{
5901 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5902 match(Set mem (StoreCM mem zero));
5903
5904 ins_cost(125); // XXX
5905 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5906 ins_encode %{
5907 __ movb($mem$$Address, r12);
5908 %}
5909 ins_pipe(ialu_mem_reg);
5910 %}
5911
5912 instruct storeImmCM0(memory mem, immI0 src)
5913 %{
5914 match(Set mem (StoreCM mem src));
5915
5916 ins_cost(150); // XXX
5917 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5918 opcode(0xC6); /* C6 /0 */
5919 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5920 ins_pipe(ialu_mem_imm);
5921 %}
5922
5923 // Store Float
5924 instruct storeF(memory mem, regF src)
5925 %{
5926 match(Set mem (StoreF mem src));
5927
5928 ins_cost(95); // XXX
5929 format %{ "movss $mem, $src\t# float" %}
5930 ins_encode %{
5931 __ movflt($mem$$Address, $src$$XMMRegister);
5932 %}
5933 ins_pipe(pipe_slow); // XXX
5934 %}
5935
5936 // Store immediate Float value (it is faster than store from XMM register)
5937 instruct storeF0(memory mem, immF0 zero)
5938 %{
5939 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5940 match(Set mem (StoreF mem zero));
5941
5942 ins_cost(25); // XXX
5943 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5944 ins_encode %{
5945 __ movl($mem$$Address, r12);
5946 %}
5947 ins_pipe(ialu_mem_reg);
5948 %}
5949
5950 instruct storeF_imm(memory mem, immF src)
5951 %{
5952 match(Set mem (StoreF mem src));
5953
5954 ins_cost(50);
5955 format %{ "movl $mem, $src\t# float" %}
5956 opcode(0xC7); /* C7 /0 */
5957 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5958 ins_pipe(ialu_mem_imm);
5959 %}
5960
5961 // Store Double
5962 instruct storeD(memory mem, regD src)
5963 %{
5964 match(Set mem (StoreD mem src));
5965
5966 ins_cost(95); // XXX
5967 format %{ "movsd $mem, $src\t# double" %}
5968 ins_encode %{
5969 __ movdbl($mem$$Address, $src$$XMMRegister);
5970 %}
5971 ins_pipe(pipe_slow); // XXX
5972 %}
5973
5974 // Store immediate double 0.0 (it is faster than store from XMM register)
5975 instruct storeD0_imm(memory mem, immD0 src)
5976 %{
5977 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5978 match(Set mem (StoreD mem src));
5979
5980 ins_cost(50);
5981 format %{ "movq $mem, $src\t# double 0." %}
5982 opcode(0xC7); /* C7 /0 */
5983 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5984 ins_pipe(ialu_mem_imm);
5985 %}
5986
5987 instruct storeD0(memory mem, immD0 zero)
5988 %{
5989 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5990 match(Set mem (StoreD mem zero));
5991
5992 ins_cost(25); // XXX
5993 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5994 ins_encode %{
5995 __ movq($mem$$Address, r12);
5996 %}
5997 ins_pipe(ialu_mem_reg);
5998 %}
5999
6000 instruct storeSSI(stackSlotI dst, rRegI src)
6001 %{
6002 match(Set dst src);
6003
6004 ins_cost(100);
6005 format %{ "movl $dst, $src\t# int stk" %}
6006 opcode(0x89);
6007 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6008 ins_pipe( ialu_mem_reg );
6009 %}
6010
6011 instruct storeSSL(stackSlotL dst, rRegL src)
6012 %{
6013 match(Set dst src);
6014
6015 ins_cost(100);
6016 format %{ "movq $dst, $src\t# long stk" %}
6017 opcode(0x89);
6018 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6019 ins_pipe(ialu_mem_reg);
6020 %}
6021
6022 instruct storeSSP(stackSlotP dst, rRegP src)
6023 %{
6024 match(Set dst src);
6025
6026 ins_cost(100);
6027 format %{ "movq $dst, $src\t# ptr stk" %}
6028 opcode(0x89);
6029 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6030 ins_pipe(ialu_mem_reg);
6031 %}
6032
6033 instruct storeSSF(stackSlotF dst, regF src)
6034 %{
6035 match(Set dst src);
6036
6037 ins_cost(95); // XXX
6038 format %{ "movss $dst, $src\t# float stk" %}
6039 ins_encode %{
6040 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6041 %}
6042 ins_pipe(pipe_slow); // XXX
6043 %}
6044
6045 instruct storeSSD(stackSlotD dst, regD src)
6046 %{
6047 match(Set dst src);
6048
6049 ins_cost(95); // XXX
6050 format %{ "movsd $dst, $src\t# double stk" %}
6051 ins_encode %{
6052 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6053 %}
6054 ins_pipe(pipe_slow); // XXX
6055 %}
6056
6057 //----------BSWAP Instructions-------------------------------------------------
6058 instruct bytes_reverse_int(rRegI dst) %{
6059 match(Set dst (ReverseBytesI dst));
6060
6061 format %{ "bswapl $dst" %}
6062 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6063 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6064 ins_pipe( ialu_reg );
6065 %}
6066
6067 instruct bytes_reverse_long(rRegL dst) %{
6068 match(Set dst (ReverseBytesL dst));
6069
6070 format %{ "bswapq $dst" %}
6071 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6072 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6073 ins_pipe( ialu_reg);
6074 %}
6075
6076 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6077 match(Set dst (ReverseBytesUS dst));
6078 effect(KILL cr);
6079
6080 format %{ "bswapl $dst\n\t"
6081 "shrl $dst,16\n\t" %}
6082 ins_encode %{
6083 __ bswapl($dst$$Register);
6084 __ shrl($dst$$Register, 16);
6085 %}
6086 ins_pipe( ialu_reg );
6087 %}
6088
6089 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6090 match(Set dst (ReverseBytesS dst));
6091 effect(KILL cr);
6092
6093 format %{ "bswapl $dst\n\t"
6094 "sar $dst,16\n\t" %}
6095 ins_encode %{
6096 __ bswapl($dst$$Register);
6097 __ sarl($dst$$Register, 16);
6098 %}
6099 ins_pipe( ialu_reg );
6100 %}
6101
6102 //---------- Zeros Count Instructions ------------------------------------------
6103
6104 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6105 predicate(UseCountLeadingZerosInstruction);
6106 match(Set dst (CountLeadingZerosI src));
6107 effect(KILL cr);
6108
6109 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6110 ins_encode %{
6111 __ lzcntl($dst$$Register, $src$$Register);
6112 %}
6113 ins_pipe(ialu_reg);
6114 %}
6115
6116 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6117 predicate(!UseCountLeadingZerosInstruction);
6118 match(Set dst (CountLeadingZerosI src));
6119 effect(KILL cr);
6120
6121 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6122 "jnz skip\n\t"
6123 "movl $dst, -1\n"
6124 "skip:\n\t"
6125 "negl $dst\n\t"
6126 "addl $dst, 31" %}
6127 ins_encode %{
6128 Register Rdst = $dst$$Register;
6129 Register Rsrc = $src$$Register;
6130 Label skip;
6131 __ bsrl(Rdst, Rsrc);
6132 __ jccb(Assembler::notZero, skip);
6133 __ movl(Rdst, -1);
6134 __ bind(skip);
6135 __ negl(Rdst);
6136 __ addl(Rdst, BitsPerInt - 1);
6137 %}
6138 ins_pipe(ialu_reg);
6139 %}
6140
6141 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6142 predicate(UseCountLeadingZerosInstruction);
6143 match(Set dst (CountLeadingZerosL src));
6144 effect(KILL cr);
6145
6146 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6147 ins_encode %{
6148 __ lzcntq($dst$$Register, $src$$Register);
6149 %}
6150 ins_pipe(ialu_reg);
6151 %}
6152
6153 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6154 predicate(!UseCountLeadingZerosInstruction);
6155 match(Set dst (CountLeadingZerosL src));
6156 effect(KILL cr);
6157
6158 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6159 "jnz skip\n\t"
6160 "movl $dst, -1\n"
6161 "skip:\n\t"
6162 "negl $dst\n\t"
6163 "addl $dst, 63" %}
6164 ins_encode %{
6165 Register Rdst = $dst$$Register;
6166 Register Rsrc = $src$$Register;
6167 Label skip;
6168 __ bsrq(Rdst, Rsrc);
6169 __ jccb(Assembler::notZero, skip);
6170 __ movl(Rdst, -1);
6171 __ bind(skip);
6172 __ negl(Rdst);
6173 __ addl(Rdst, BitsPerLong - 1);
6174 %}
6175 ins_pipe(ialu_reg);
6176 %}
6177
6178 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6179 predicate(UseCountTrailingZerosInstruction);
6180 match(Set dst (CountTrailingZerosI src));
6181 effect(KILL cr);
6182
6183 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6184 ins_encode %{
6185 __ tzcntl($dst$$Register, $src$$Register);
6186 %}
6187 ins_pipe(ialu_reg);
6188 %}
6189
6190 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6191 predicate(!UseCountTrailingZerosInstruction);
6192 match(Set dst (CountTrailingZerosI src));
6193 effect(KILL cr);
6194
6195 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6196 "jnz done\n\t"
6197 "movl $dst, 32\n"
6198 "done:" %}
6199 ins_encode %{
6200 Register Rdst = $dst$$Register;
6201 Label done;
6202 __ bsfl(Rdst, $src$$Register);
6203 __ jccb(Assembler::notZero, done);
6204 __ movl(Rdst, BitsPerInt);
6205 __ bind(done);
6206 %}
6207 ins_pipe(ialu_reg);
6208 %}
6209
6210 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6211 predicate(UseCountTrailingZerosInstruction);
6212 match(Set dst (CountTrailingZerosL src));
6213 effect(KILL cr);
6214
6215 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6216 ins_encode %{
6217 __ tzcntq($dst$$Register, $src$$Register);
6218 %}
6219 ins_pipe(ialu_reg);
6220 %}
6221
6222 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6223 predicate(!UseCountTrailingZerosInstruction);
6224 match(Set dst (CountTrailingZerosL src));
6225 effect(KILL cr);
6226
6227 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6228 "jnz done\n\t"
6229 "movl $dst, 64\n"
6230 "done:" %}
6231 ins_encode %{
6232 Register Rdst = $dst$$Register;
6233 Label done;
6234 __ bsfq(Rdst, $src$$Register);
6235 __ jccb(Assembler::notZero, done);
6236 __ movl(Rdst, BitsPerLong);
6237 __ bind(done);
6238 %}
6239 ins_pipe(ialu_reg);
6240 %}
6241
6242
6243 //---------- Population Count Instructions -------------------------------------
6244
6245 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6246 predicate(UsePopCountInstruction);
6247 match(Set dst (PopCountI src));
6248 effect(KILL cr);
6249
6250 format %{ "popcnt $dst, $src" %}
6251 ins_encode %{
6252 __ popcntl($dst$$Register, $src$$Register);
6253 %}
6254 ins_pipe(ialu_reg);
6255 %}
6256
6257 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6258 predicate(UsePopCountInstruction);
6259 match(Set dst (PopCountI (LoadI mem)));
6260 effect(KILL cr);
6261
6262 format %{ "popcnt $dst, $mem" %}
6263 ins_encode %{
6264 __ popcntl($dst$$Register, $mem$$Address);
6265 %}
6266 ins_pipe(ialu_reg);
6267 %}
6268
6269 // Note: Long.bitCount(long) returns an int.
6270 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6271 predicate(UsePopCountInstruction);
6272 match(Set dst (PopCountL src));
6273 effect(KILL cr);
6274
6275 format %{ "popcnt $dst, $src" %}
6276 ins_encode %{
6277 __ popcntq($dst$$Register, $src$$Register);
6278 %}
6279 ins_pipe(ialu_reg);
6280 %}
6281
6282 // Note: Long.bitCount(long) returns an int.
6283 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6284 predicate(UsePopCountInstruction);
6285 match(Set dst (PopCountL (LoadL mem)));
6286 effect(KILL cr);
6287
6288 format %{ "popcnt $dst, $mem" %}
6289 ins_encode %{
6290 __ popcntq($dst$$Register, $mem$$Address);
6291 %}
6292 ins_pipe(ialu_reg);
6293 %}
6294
6295
6296 //----------MemBar Instructions-----------------------------------------------
6297 // Memory barrier flavors
6298
6299 instruct membar_acquire()
6300 %{
6301 match(MemBarAcquire);
6302 match(LoadFence);
6303 ins_cost(0);
6304
6305 size(0);
6306 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6307 ins_encode();
6308 ins_pipe(empty);
6309 %}
6310
6311 instruct membar_acquire_lock()
6312 %{
6313 match(MemBarAcquireLock);
6314 ins_cost(0);
6315
6316 size(0);
6317 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6318 ins_encode();
6319 ins_pipe(empty);
6320 %}
6321
6322 instruct membar_release()
6323 %{
6324 match(MemBarRelease);
6325 match(StoreFence);
6326 ins_cost(0);
6327
6328 size(0);
6329 format %{ "MEMBAR-release ! (empty encoding)" %}
6330 ins_encode();
6331 ins_pipe(empty);
6332 %}
6333
6334 instruct membar_release_lock()
6335 %{
6336 match(MemBarReleaseLock);
6337 ins_cost(0);
6338
6339 size(0);
6340 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6341 ins_encode();
6342 ins_pipe(empty);
6343 %}
6344
6345 instruct membar_volatile(rFlagsReg cr) %{
6346 match(MemBarVolatile);
6347 effect(KILL cr);
6348 ins_cost(400);
6349
6350 format %{
6351 $$template
6352 if (os::is_MP()) {
6353 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6354 } else {
6355 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6356 }
6357 %}
6358 ins_encode %{
6359 __ membar(Assembler::StoreLoad);
6360 %}
6361 ins_pipe(pipe_slow);
6362 %}
6363
6364 instruct unnecessary_membar_volatile()
6365 %{
6366 match(MemBarVolatile);
6367 predicate(Matcher::post_store_load_barrier(n));
6368 ins_cost(0);
6369
6370 size(0);
6371 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6372 ins_encode();
6373 ins_pipe(empty);
6374 %}
6375
6376 instruct membar_storestore() %{
6377 match(MemBarStoreStore);
6378 ins_cost(0);
6379
6380 size(0);
6381 format %{ "MEMBAR-storestore (empty encoding)" %}
6382 ins_encode( );
6383 ins_pipe(empty);
6384 %}
6385
6386 //----------Move Instructions--------------------------------------------------
6387
6388 instruct castX2P(rRegP dst, rRegL src)
6389 %{
6390 match(Set dst (CastX2P src));
6391
6392 format %{ "movq $dst, $src\t# long->ptr" %}
6393 ins_encode %{
6394 if ($dst$$reg != $src$$reg) {
6395 __ movptr($dst$$Register, $src$$Register);
6396 }
6397 %}
6398 ins_pipe(ialu_reg_reg); // XXX
6399 %}
6400
6401 instruct castP2X(rRegL dst, rRegP src)
6402 %{
6403 match(Set dst (CastP2X src));
6404
6405 format %{ "movq $dst, $src\t# ptr -> long" %}
6406 ins_encode %{
6407 if ($dst$$reg != $src$$reg) {
6408 __ movptr($dst$$Register, $src$$Register);
6409 }
6410 %}
6411 ins_pipe(ialu_reg_reg); // XXX
6412 %}
6413
6414 // Convert oop into int for vectors alignment masking
6415 instruct convP2I(rRegI dst, rRegP src)
6416 %{
6417 match(Set dst (ConvL2I (CastP2X src)));
6418
6419 format %{ "movl $dst, $src\t# ptr -> int" %}
6420 ins_encode %{
6421 __ movl($dst$$Register, $src$$Register);
6422 %}
6423 ins_pipe(ialu_reg_reg); // XXX
6424 %}
6425
6426 // Convert compressed oop into int for vectors alignment masking
6427 // in case of 32bit oops (heap < 4Gb).
6428 instruct convN2I(rRegI dst, rRegN src)
6429 %{
6430 predicate(Universe::narrow_oop_shift() == 0);
6431 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6432
6433 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6434 ins_encode %{
6435 __ movl($dst$$Register, $src$$Register);
6436 %}
6437 ins_pipe(ialu_reg_reg); // XXX
6438 %}
6439
6440 // Convert oop pointer into compressed form
6441 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6442 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6443 match(Set dst (EncodeP src));
6444 effect(KILL cr);
6445 format %{ "encode_heap_oop $dst,$src" %}
6446 ins_encode %{
6447 Register s = $src$$Register;
6448 Register d = $dst$$Register;
6449 if (s != d) {
6450 __ movq(d, s);
6451 }
6452 __ encode_heap_oop(d);
6453 %}
6454 ins_pipe(ialu_reg_long);
6455 %}
6456
6457 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6458 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6459 match(Set dst (EncodeP src));
6460 effect(KILL cr);
6461 format %{ "encode_heap_oop_not_null $dst,$src" %}
6462 ins_encode %{
6463 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6464 %}
6465 ins_pipe(ialu_reg_long);
6466 %}
6467
6468 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6469 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6470 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6471 match(Set dst (DecodeN src));
6472 effect(KILL cr);
6473 format %{ "decode_heap_oop $dst,$src" %}
6474 ins_encode %{
6475 Register s = $src$$Register;
6476 Register d = $dst$$Register;
6477 if (s != d) {
6478 __ movq(d, s);
6479 }
6480 __ decode_heap_oop(d);
6481 %}
6482 ins_pipe(ialu_reg_long);
6483 %}
6484
6485 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6486 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6487 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6488 match(Set dst (DecodeN src));
6489 effect(KILL cr);
6490 format %{ "decode_heap_oop_not_null $dst,$src" %}
6491 ins_encode %{
6492 Register s = $src$$Register;
6493 Register d = $dst$$Register;
6494 if (s != d) {
6495 __ decode_heap_oop_not_null(d, s);
6496 } else {
6497 __ decode_heap_oop_not_null(d);
6498 }
6499 %}
6500 ins_pipe(ialu_reg_long);
6501 %}
6502
6503 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6504 match(Set dst (EncodePKlass src));
6505 effect(KILL cr);
6506 format %{ "encode_klass_not_null $dst,$src" %}
6507 ins_encode %{
6508 __ encode_klass_not_null($dst$$Register, $src$$Register);
6509 %}
6510 ins_pipe(ialu_reg_long);
6511 %}
6512
6513 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6514 match(Set dst (DecodeNKlass src));
6515 effect(KILL cr);
6516 format %{ "decode_klass_not_null $dst,$src" %}
6517 ins_encode %{
6518 Register s = $src$$Register;
6519 Register d = $dst$$Register;
6520 if (s != d) {
6521 __ decode_klass_not_null(d, s);
6522 } else {
6523 __ decode_klass_not_null(d);
6524 }
6525 %}
6526 ins_pipe(ialu_reg_long);
6527 %}
6528
6529
6530 //----------Conditional Move---------------------------------------------------
6531 // Jump
6532 // dummy instruction for generating temp registers
6533 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6534 match(Jump (LShiftL switch_val shift));
6535 ins_cost(350);
6536 predicate(false);
6537 effect(TEMP dest);
6538
6539 format %{ "leaq $dest, [$constantaddress]\n\t"
6540 "jmp [$dest + $switch_val << $shift]\n\t" %}
6541 ins_encode %{
6542 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6543 // to do that and the compiler is using that register as one it can allocate.
6544 // So we build it all by hand.
6545 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6546 // ArrayAddress dispatch(table, index);
6547 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6548 __ lea($dest$$Register, $constantaddress);
6549 __ jmp(dispatch);
6550 %}
6551 ins_pipe(pipe_jmp);
6552 %}
6553
6554 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6555 match(Jump (AddL (LShiftL switch_val shift) offset));
6556 ins_cost(350);
6557 effect(TEMP dest);
6558
6559 format %{ "leaq $dest, [$constantaddress]\n\t"
6560 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6561 ins_encode %{
6562 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6563 // to do that and the compiler is using that register as one it can allocate.
6564 // So we build it all by hand.
6565 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6566 // ArrayAddress dispatch(table, index);
6567 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6568 __ lea($dest$$Register, $constantaddress);
6569 __ jmp(dispatch);
6570 %}
6571 ins_pipe(pipe_jmp);
6572 %}
6573
6574 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6575 match(Jump switch_val);
6576 ins_cost(350);
6577 effect(TEMP dest);
6578
6579 format %{ "leaq $dest, [$constantaddress]\n\t"
6580 "jmp [$dest + $switch_val]\n\t" %}
6581 ins_encode %{
6582 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6583 // to do that and the compiler is using that register as one it can allocate.
6584 // So we build it all by hand.
6585 // Address index(noreg, switch_reg, Address::times_1);
6586 // ArrayAddress dispatch(table, index);
6587 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6588 __ lea($dest$$Register, $constantaddress);
6589 __ jmp(dispatch);
6590 %}
6591 ins_pipe(pipe_jmp);
6592 %}
6593
6594 // Conditional move
6595 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6596 %{
6597 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6598
6599 ins_cost(200); // XXX
6600 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6601 opcode(0x0F, 0x40);
6602 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6603 ins_pipe(pipe_cmov_reg);
6604 %}
6605
6606 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6607 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6608
6609 ins_cost(200); // XXX
6610 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6611 opcode(0x0F, 0x40);
6612 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6613 ins_pipe(pipe_cmov_reg);
6614 %}
6615
6616 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6617 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6618 ins_cost(200);
6619 expand %{
6620 cmovI_regU(cop, cr, dst, src);
6621 %}
6622 %}
6623
6624 // Conditional move
6625 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6626 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6627
6628 ins_cost(250); // XXX
6629 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6630 opcode(0x0F, 0x40);
6631 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6632 ins_pipe(pipe_cmov_mem);
6633 %}
6634
6635 // Conditional move
6636 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6637 %{
6638 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6639
6640 ins_cost(250); // XXX
6641 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6642 opcode(0x0F, 0x40);
6643 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6644 ins_pipe(pipe_cmov_mem);
6645 %}
6646
6647 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6648 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6649 ins_cost(250);
6650 expand %{
6651 cmovI_memU(cop, cr, dst, src);
6652 %}
6653 %}
6654
6655 // Conditional move
6656 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6657 %{
6658 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6659
6660 ins_cost(200); // XXX
6661 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6662 opcode(0x0F, 0x40);
6663 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6664 ins_pipe(pipe_cmov_reg);
6665 %}
6666
6667 // Conditional move
6668 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6669 %{
6670 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6671
6672 ins_cost(200); // XXX
6673 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6674 opcode(0x0F, 0x40);
6675 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6676 ins_pipe(pipe_cmov_reg);
6677 %}
6678
6679 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6680 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6681 ins_cost(200);
6682 expand %{
6683 cmovN_regU(cop, cr, dst, src);
6684 %}
6685 %}
6686
6687 // Conditional move
6688 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6689 %{
6690 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6691
6692 ins_cost(200); // XXX
6693 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6694 opcode(0x0F, 0x40);
6695 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6696 ins_pipe(pipe_cmov_reg); // XXX
6697 %}
6698
6699 // Conditional move
6700 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6701 %{
6702 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6703
6704 ins_cost(200); // XXX
6705 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6706 opcode(0x0F, 0x40);
6707 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6708 ins_pipe(pipe_cmov_reg); // XXX
6709 %}
6710
6711 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6712 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6713 ins_cost(200);
6714 expand %{
6715 cmovP_regU(cop, cr, dst, src);
6716 %}
6717 %}
6718
6719 // DISABLED: Requires the ADLC to emit a bottom_type call that
6720 // correctly meets the two pointer arguments; one is an incoming
6721 // register but the other is a memory operand. ALSO appears to
6722 // be buggy with implicit null checks.
6723 //
6724 //// Conditional move
6725 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6726 //%{
6727 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6728 // ins_cost(250);
6729 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6730 // opcode(0x0F,0x40);
6731 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6732 // ins_pipe( pipe_cmov_mem );
6733 //%}
6734 //
6735 //// Conditional move
6736 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6737 //%{
6738 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6739 // ins_cost(250);
6740 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6741 // opcode(0x0F,0x40);
6742 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6743 // ins_pipe( pipe_cmov_mem );
6744 //%}
6745
6746 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6747 %{
6748 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6749
6750 ins_cost(200); // XXX
6751 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6752 opcode(0x0F, 0x40);
6753 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6754 ins_pipe(pipe_cmov_reg); // XXX
6755 %}
6756
6757 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6758 %{
6759 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6760
6761 ins_cost(200); // XXX
6762 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6763 opcode(0x0F, 0x40);
6764 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6765 ins_pipe(pipe_cmov_mem); // XXX
6766 %}
6767
6768 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6769 %{
6770 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6771
6772 ins_cost(200); // XXX
6773 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6774 opcode(0x0F, 0x40);
6775 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6776 ins_pipe(pipe_cmov_reg); // XXX
6777 %}
6778
6779 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6780 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6781 ins_cost(200);
6782 expand %{
6783 cmovL_regU(cop, cr, dst, src);
6784 %}
6785 %}
6786
6787 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6788 %{
6789 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6790
6791 ins_cost(200); // XXX
6792 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6793 opcode(0x0F, 0x40);
6794 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6795 ins_pipe(pipe_cmov_mem); // XXX
6796 %}
6797
6798 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6799 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6800 ins_cost(200);
6801 expand %{
6802 cmovL_memU(cop, cr, dst, src);
6803 %}
6804 %}
6805
6806 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6807 %{
6808 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6809
6810 ins_cost(200); // XXX
6811 format %{ "jn$cop skip\t# signed cmove float\n\t"
6812 "movss $dst, $src\n"
6813 "skip:" %}
6814 ins_encode %{
6815 Label Lskip;
6816 // Invert sense of branch from sense of CMOV
6817 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6818 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6819 __ bind(Lskip);
6820 %}
6821 ins_pipe(pipe_slow);
6822 %}
6823
6824 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6825 // %{
6826 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6827
6828 // ins_cost(200); // XXX
6829 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6830 // "movss $dst, $src\n"
6831 // "skip:" %}
6832 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6833 // ins_pipe(pipe_slow);
6834 // %}
6835
6836 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6837 %{
6838 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6839
6840 ins_cost(200); // XXX
6841 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6842 "movss $dst, $src\n"
6843 "skip:" %}
6844 ins_encode %{
6845 Label Lskip;
6846 // Invert sense of branch from sense of CMOV
6847 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6848 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6849 __ bind(Lskip);
6850 %}
6851 ins_pipe(pipe_slow);
6852 %}
6853
6854 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6855 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6856 ins_cost(200);
6857 expand %{
6858 cmovF_regU(cop, cr, dst, src);
6859 %}
6860 %}
6861
6862 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6863 %{
6864 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6865
6866 ins_cost(200); // XXX
6867 format %{ "jn$cop skip\t# signed cmove double\n\t"
6868 "movsd $dst, $src\n"
6869 "skip:" %}
6870 ins_encode %{
6871 Label Lskip;
6872 // Invert sense of branch from sense of CMOV
6873 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6874 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6875 __ bind(Lskip);
6876 %}
6877 ins_pipe(pipe_slow);
6878 %}
6879
6880 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6881 %{
6882 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6883
6884 ins_cost(200); // XXX
6885 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6886 "movsd $dst, $src\n"
6887 "skip:" %}
6888 ins_encode %{
6889 Label Lskip;
6890 // Invert sense of branch from sense of CMOV
6891 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6892 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6893 __ bind(Lskip);
6894 %}
6895 ins_pipe(pipe_slow);
6896 %}
6897
6898 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6899 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6900 ins_cost(200);
6901 expand %{
6902 cmovD_regU(cop, cr, dst, src);
6903 %}
6904 %}
6905
6906 //----------Arithmetic Instructions--------------------------------------------
6907 //----------Addition Instructions----------------------------------------------
6908
6909 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6910 %{
6911 match(Set dst (AddI dst src));
6912 effect(KILL cr);
6913
6914 format %{ "addl $dst, $src\t# int" %}
6915 opcode(0x03);
6916 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6917 ins_pipe(ialu_reg_reg);
6918 %}
6919
6920 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6921 %{
6922 match(Set dst (AddI dst src));
6923 effect(KILL cr);
6924
6925 format %{ "addl $dst, $src\t# int" %}
6926 opcode(0x81, 0x00); /* /0 id */
6927 ins_encode(OpcSErm(dst, src), Con8or32(src));
6928 ins_pipe( ialu_reg );
6929 %}
6930
6931 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6932 %{
6933 match(Set dst (AddI dst (LoadI src)));
6934 effect(KILL cr);
6935
6936 ins_cost(125); // XXX
6937 format %{ "addl $dst, $src\t# int" %}
6938 opcode(0x03);
6939 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6940 ins_pipe(ialu_reg_mem);
6941 %}
6942
6943 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6944 %{
6945 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6946 effect(KILL cr);
6947
6948 ins_cost(150); // XXX
6949 format %{ "addl $dst, $src\t# int" %}
6950 opcode(0x01); /* Opcode 01 /r */
6951 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6952 ins_pipe(ialu_mem_reg);
6953 %}
6954
6955 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6956 %{
6957 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6958 effect(KILL cr);
6959
6960 ins_cost(125); // XXX
6961 format %{ "addl $dst, $src\t# int" %}
6962 opcode(0x81); /* Opcode 81 /0 id */
6963 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6964 ins_pipe(ialu_mem_imm);
6965 %}
6966
6967 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6968 %{
6969 predicate(UseIncDec);
6970 match(Set dst (AddI dst src));
6971 effect(KILL cr);
6972
6973 format %{ "incl $dst\t# int" %}
6974 opcode(0xFF, 0x00); // FF /0
6975 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6976 ins_pipe(ialu_reg);
6977 %}
6978
6979 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6980 %{
6981 predicate(UseIncDec);
6982 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6983 effect(KILL cr);
6984
6985 ins_cost(125); // XXX
6986 format %{ "incl $dst\t# int" %}
6987 opcode(0xFF); /* Opcode FF /0 */
6988 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6989 ins_pipe(ialu_mem_imm);
6990 %}
6991
6992 // XXX why does that use AddI
6993 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6994 %{
6995 predicate(UseIncDec);
6996 match(Set dst (AddI dst src));
6997 effect(KILL cr);
6998
6999 format %{ "decl $dst\t# int" %}
7000 opcode(0xFF, 0x01); // FF /1
7001 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7002 ins_pipe(ialu_reg);
7003 %}
7004
7005 // XXX why does that use AddI
7006 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7007 %{
7008 predicate(UseIncDec);
7009 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7010 effect(KILL cr);
7011
7012 ins_cost(125); // XXX
7013 format %{ "decl $dst\t# int" %}
7014 opcode(0xFF); /* Opcode FF /1 */
7015 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7016 ins_pipe(ialu_mem_imm);
7017 %}
7018
7019 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7020 %{
7021 match(Set dst (AddI src0 src1));
7022
7023 ins_cost(110);
7024 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7025 opcode(0x8D); /* 0x8D /r */
7026 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7027 ins_pipe(ialu_reg_reg);
7028 %}
7029
7030 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7031 %{
7032 match(Set dst (AddL dst src));
7033 effect(KILL cr);
7034
7035 format %{ "addq $dst, $src\t# long" %}
7036 opcode(0x03);
7037 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7038 ins_pipe(ialu_reg_reg);
7039 %}
7040
7041 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7042 %{
7043 match(Set dst (AddL dst src));
7044 effect(KILL cr);
7045
7046 format %{ "addq $dst, $src\t# long" %}
7047 opcode(0x81, 0x00); /* /0 id */
7048 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7049 ins_pipe( ialu_reg );
7050 %}
7051
7052 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7053 %{
7054 match(Set dst (AddL dst (LoadL src)));
7055 effect(KILL cr);
7056
7057 ins_cost(125); // XXX
7058 format %{ "addq $dst, $src\t# long" %}
7059 opcode(0x03);
7060 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7061 ins_pipe(ialu_reg_mem);
7062 %}
7063
7064 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7065 %{
7066 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7067 effect(KILL cr);
7068
7069 ins_cost(150); // XXX
7070 format %{ "addq $dst, $src\t# long" %}
7071 opcode(0x01); /* Opcode 01 /r */
7072 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7073 ins_pipe(ialu_mem_reg);
7074 %}
7075
7076 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7077 %{
7078 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7079 effect(KILL cr);
7080
7081 ins_cost(125); // XXX
7082 format %{ "addq $dst, $src\t# long" %}
7083 opcode(0x81); /* Opcode 81 /0 id */
7084 ins_encode(REX_mem_wide(dst),
7085 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7086 ins_pipe(ialu_mem_imm);
7087 %}
7088
7089 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7090 %{
7091 predicate(UseIncDec);
7092 match(Set dst (AddL dst src));
7093 effect(KILL cr);
7094
7095 format %{ "incq $dst\t# long" %}
7096 opcode(0xFF, 0x00); // FF /0
7097 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7098 ins_pipe(ialu_reg);
7099 %}
7100
7101 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7102 %{
7103 predicate(UseIncDec);
7104 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7105 effect(KILL cr);
7106
7107 ins_cost(125); // XXX
7108 format %{ "incq $dst\t# long" %}
7109 opcode(0xFF); /* Opcode FF /0 */
7110 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7111 ins_pipe(ialu_mem_imm);
7112 %}
7113
7114 // XXX why does that use AddL
7115 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7116 %{
7117 predicate(UseIncDec);
7118 match(Set dst (AddL dst src));
7119 effect(KILL cr);
7120
7121 format %{ "decq $dst\t# long" %}
7122 opcode(0xFF, 0x01); // FF /1
7123 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7124 ins_pipe(ialu_reg);
7125 %}
7126
7127 // XXX why does that use AddL
7128 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7129 %{
7130 predicate(UseIncDec);
7131 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7132 effect(KILL cr);
7133
7134 ins_cost(125); // XXX
7135 format %{ "decq $dst\t# long" %}
7136 opcode(0xFF); /* Opcode FF /1 */
7137 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7138 ins_pipe(ialu_mem_imm);
7139 %}
7140
7141 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7142 %{
7143 match(Set dst (AddL src0 src1));
7144
7145 ins_cost(110);
7146 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7147 opcode(0x8D); /* 0x8D /r */
7148 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7149 ins_pipe(ialu_reg_reg);
7150 %}
7151
7152 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7153 %{
7154 match(Set dst (AddP dst src));
7155 effect(KILL cr);
7156
7157 format %{ "addq $dst, $src\t# ptr" %}
7158 opcode(0x03);
7159 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7160 ins_pipe(ialu_reg_reg);
7161 %}
7162
7163 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7164 %{
7165 match(Set dst (AddP dst src));
7166 effect(KILL cr);
7167
7168 format %{ "addq $dst, $src\t# ptr" %}
7169 opcode(0x81, 0x00); /* /0 id */
7170 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7171 ins_pipe( ialu_reg );
7172 %}
7173
7174 // XXX addP mem ops ????
7175
7176 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7177 %{
7178 match(Set dst (AddP src0 src1));
7179
7180 ins_cost(110);
7181 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7182 opcode(0x8D); /* 0x8D /r */
7183 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7184 ins_pipe(ialu_reg_reg);
7185 %}
7186
7187 instruct checkCastPP(rRegP dst)
7188 %{
7189 match(Set dst (CheckCastPP dst));
7190
7191 size(0);
7192 format %{ "# checkcastPP of $dst" %}
7193 ins_encode(/* empty encoding */);
7194 ins_pipe(empty);
7195 %}
7196
7197 instruct castPP(rRegP dst)
7198 %{
7199 match(Set dst (CastPP dst));
7200
7201 size(0);
7202 format %{ "# castPP of $dst" %}
7203 ins_encode(/* empty encoding */);
7204 ins_pipe(empty);
7205 %}
7206
7207 instruct castII(rRegI dst)
7208 %{
7209 match(Set dst (CastII dst));
7210
7211 size(0);
7212 format %{ "# castII of $dst" %}
7213 ins_encode(/* empty encoding */);
7214 ins_cost(0);
7215 ins_pipe(empty);
7216 %}
7217
7218 // LoadP-locked same as a regular LoadP when used with compare-swap
7219 instruct loadPLocked(rRegP dst, memory mem)
7220 %{
7221 match(Set dst (LoadPLocked mem));
7222
7223 ins_cost(125); // XXX
7224 format %{ "movq $dst, $mem\t# ptr locked" %}
7225 opcode(0x8B);
7226 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7227 ins_pipe(ialu_reg_mem); // XXX
7228 %}
7229
7230 // Conditional-store of the updated heap-top.
7231 // Used during allocation of the shared heap.
7232 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7233
7234 instruct storePConditional(memory heap_top_ptr,
7235 rax_RegP oldval, rRegP newval,
7236 rFlagsReg cr)
7237 %{
7238 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7239
7240 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7241 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7242 opcode(0x0F, 0xB1);
7243 ins_encode(lock_prefix,
7244 REX_reg_mem_wide(newval, heap_top_ptr),
7245 OpcP, OpcS,
7246 reg_mem(newval, heap_top_ptr));
7247 ins_pipe(pipe_cmpxchg);
7248 %}
7249
7250 // Conditional-store of an int value.
7251 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7252 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7253 %{
7254 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7255 effect(KILL oldval);
7256
7257 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7258 opcode(0x0F, 0xB1);
7259 ins_encode(lock_prefix,
7260 REX_reg_mem(newval, mem),
7261 OpcP, OpcS,
7262 reg_mem(newval, mem));
7263 ins_pipe(pipe_cmpxchg);
7264 %}
7265
7266 // Conditional-store of a long value.
7267 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7268 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7269 %{
7270 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7271 effect(KILL oldval);
7272
7273 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7274 opcode(0x0F, 0xB1);
7275 ins_encode(lock_prefix,
7276 REX_reg_mem_wide(newval, mem),
7277 OpcP, OpcS,
7278 reg_mem(newval, mem));
7279 ins_pipe(pipe_cmpxchg);
7280 %}
7281
7282
7283 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7284 instruct compareAndSwapP(rRegI res,
7285 memory mem_ptr,
7286 rax_RegP oldval, rRegP newval,
7287 rFlagsReg cr)
7288 %{
7289 predicate(VM_Version::supports_cx8());
7290 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7291 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7292 effect(KILL cr, KILL oldval);
7293
7294 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7295 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7296 "sete $res\n\t"
7297 "movzbl $res, $res" %}
7298 opcode(0x0F, 0xB1);
7299 ins_encode(lock_prefix,
7300 REX_reg_mem_wide(newval, mem_ptr),
7301 OpcP, OpcS,
7302 reg_mem(newval, mem_ptr),
7303 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7304 REX_reg_breg(res, res), // movzbl
7305 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7306 ins_pipe( pipe_cmpxchg );
7307 %}
7308
7309 instruct compareAndSwapL(rRegI res,
7310 memory mem_ptr,
7311 rax_RegL oldval, rRegL newval,
7312 rFlagsReg cr)
7313 %{
7314 predicate(VM_Version::supports_cx8());
7315 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7316 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7317 effect(KILL cr, KILL oldval);
7318
7319 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7320 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7321 "sete $res\n\t"
7322 "movzbl $res, $res" %}
7323 opcode(0x0F, 0xB1);
7324 ins_encode(lock_prefix,
7325 REX_reg_mem_wide(newval, mem_ptr),
7326 OpcP, OpcS,
7327 reg_mem(newval, mem_ptr),
7328 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7329 REX_reg_breg(res, res), // movzbl
7330 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7331 ins_pipe( pipe_cmpxchg );
7332 %}
7333
7334 instruct compareAndSwapI(rRegI res,
7335 memory mem_ptr,
7336 rax_RegI oldval, rRegI newval,
7337 rFlagsReg cr)
7338 %{
7339 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7340 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7341 effect(KILL cr, KILL oldval);
7342
7343 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7344 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7345 "sete $res\n\t"
7346 "movzbl $res, $res" %}
7347 opcode(0x0F, 0xB1);
7348 ins_encode(lock_prefix,
7349 REX_reg_mem(newval, mem_ptr),
7350 OpcP, OpcS,
7351 reg_mem(newval, mem_ptr),
7352 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7353 REX_reg_breg(res, res), // movzbl
7354 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7355 ins_pipe( pipe_cmpxchg );
7356 %}
7357
7358 instruct compareAndSwapB(rRegI res,
7359 memory mem_ptr,
7360 rax_RegI oldval, rRegI newval,
7361 rFlagsReg cr)
7362 %{
7363 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7364 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7365 effect(KILL cr, KILL oldval);
7366
7367 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7368 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7369 "sete $res\n\t"
7370 "movzbl $res, $res" %}
7371 opcode(0x0F, 0xB0);
7372 ins_encode(lock_prefix,
7373 REX_breg_mem(newval, mem_ptr),
7374 OpcP, OpcS,
7375 reg_mem(newval, mem_ptr),
7376 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7377 REX_reg_breg(res, res), // movzbl
7378 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7379 ins_pipe( pipe_cmpxchg );
7380 %}
7381
7382 instruct compareAndSwapS(rRegI res,
7383 memory mem_ptr,
7384 rax_RegI oldval, rRegI newval,
7385 rFlagsReg cr)
7386 %{
7387 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7388 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7389 effect(KILL cr, KILL oldval);
7390
7391 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7392 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7393 "sete $res\n\t"
7394 "movzbl $res, $res" %}
7395 opcode(0x0F, 0xB1);
7396 ins_encode(lock_prefix,
7397 SizePrefix,
7398 REX_reg_mem(newval, mem_ptr),
7399 OpcP, OpcS,
7400 reg_mem(newval, mem_ptr),
7401 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7402 REX_reg_breg(res, res), // movzbl
7403 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7404 ins_pipe( pipe_cmpxchg );
7405 %}
7406
7407 instruct compareAndSwapN(rRegI res,
7408 memory mem_ptr,
7409 rax_RegN oldval, rRegN newval,
7410 rFlagsReg cr) %{
7411 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7412 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7413 effect(KILL cr, KILL oldval);
7414
7415 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7416 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7417 "sete $res\n\t"
7418 "movzbl $res, $res" %}
7419 opcode(0x0F, 0xB1);
7420 ins_encode(lock_prefix,
7421 REX_reg_mem(newval, mem_ptr),
7422 OpcP, OpcS,
7423 reg_mem(newval, mem_ptr),
7424 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7425 REX_reg_breg(res, res), // movzbl
7426 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7427 ins_pipe( pipe_cmpxchg );
7428 %}
7429
7430 instruct compareAndExchangeB(
7431 memory mem_ptr,
7432 rax_RegI oldval, rRegI newval,
7433 rFlagsReg cr)
7434 %{
7435 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7436 effect(KILL cr);
7437
7438 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7439 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7440 opcode(0x0F, 0xB0);
7441 ins_encode(lock_prefix,
7442 REX_breg_mem(newval, mem_ptr),
7443 OpcP, OpcS,
7444 reg_mem(newval, mem_ptr) // lock cmpxchg
7445 );
7446 ins_pipe( pipe_cmpxchg );
7447 %}
7448
7449 instruct compareAndExchangeS(
7450 memory mem_ptr,
7451 rax_RegI oldval, rRegI newval,
7452 rFlagsReg cr)
7453 %{
7454 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7455 effect(KILL cr);
7456
7457 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7458 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7459 opcode(0x0F, 0xB1);
7460 ins_encode(lock_prefix,
7461 SizePrefix,
7462 REX_reg_mem(newval, mem_ptr),
7463 OpcP, OpcS,
7464 reg_mem(newval, mem_ptr) // lock cmpxchg
7465 );
7466 ins_pipe( pipe_cmpxchg );
7467 %}
7468
7469 instruct compareAndExchangeI(
7470 memory mem_ptr,
7471 rax_RegI oldval, rRegI newval,
7472 rFlagsReg cr)
7473 %{
7474 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7475 effect(KILL cr);
7476
7477 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7478 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7479 opcode(0x0F, 0xB1);
7480 ins_encode(lock_prefix,
7481 REX_reg_mem(newval, mem_ptr),
7482 OpcP, OpcS,
7483 reg_mem(newval, mem_ptr) // lock cmpxchg
7484 );
7485 ins_pipe( pipe_cmpxchg );
7486 %}
7487
7488 instruct compareAndExchangeL(
7489 memory mem_ptr,
7490 rax_RegL oldval, rRegL newval,
7491 rFlagsReg cr)
7492 %{
7493 predicate(VM_Version::supports_cx8());
7494 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7495 effect(KILL cr);
7496
7497 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7498 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7499 opcode(0x0F, 0xB1);
7500 ins_encode(lock_prefix,
7501 REX_reg_mem_wide(newval, mem_ptr),
7502 OpcP, OpcS,
7503 reg_mem(newval, mem_ptr) // lock cmpxchg
7504 );
7505 ins_pipe( pipe_cmpxchg );
7506 %}
7507
7508 instruct compareAndExchangeN(
7509 memory mem_ptr,
7510 rax_RegN oldval, rRegN newval,
7511 rFlagsReg cr) %{
7512 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7513 effect(KILL cr);
7514
7515 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7516 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7517 opcode(0x0F, 0xB1);
7518 ins_encode(lock_prefix,
7519 REX_reg_mem(newval, mem_ptr),
7520 OpcP, OpcS,
7521 reg_mem(newval, mem_ptr) // lock cmpxchg
7522 );
7523 ins_pipe( pipe_cmpxchg );
7524 %}
7525
7526 instruct compareAndExchangeP(
7527 memory mem_ptr,
7528 rax_RegP oldval, rRegP newval,
7529 rFlagsReg cr)
7530 %{
7531 predicate(VM_Version::supports_cx8());
7532 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7533 effect(KILL cr);
7534
7535 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7536 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7537 opcode(0x0F, 0xB1);
7538 ins_encode(lock_prefix,
7539 REX_reg_mem_wide(newval, mem_ptr),
7540 OpcP, OpcS,
7541 reg_mem(newval, mem_ptr) // lock cmpxchg
7542 );
7543 ins_pipe( pipe_cmpxchg );
7544 %}
7545
7546 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7547 predicate(n->as_LoadStore()->result_not_used());
7548 match(Set dummy (GetAndAddB mem add));
7549 effect(KILL cr);
7550 format %{ "ADDB [$mem],$add" %}
7551 ins_encode %{
7552 if (os::is_MP()) { __ lock(); }
7553 __ addb($mem$$Address, $add$$constant);
7554 %}
7555 ins_pipe( pipe_cmpxchg );
7556 %}
7557
7558 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7559 match(Set newval (GetAndAddB mem newval));
7560 effect(KILL cr);
7561 format %{ "XADDB [$mem],$newval" %}
7562 ins_encode %{
7563 if (os::is_MP()) { __ lock(); }
7564 __ xaddb($mem$$Address, $newval$$Register);
7565 %}
7566 ins_pipe( pipe_cmpxchg );
7567 %}
7568
7569 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7570 predicate(n->as_LoadStore()->result_not_used());
7571 match(Set dummy (GetAndAddS mem add));
7572 effect(KILL cr);
7573 format %{ "ADDW [$mem],$add" %}
7574 ins_encode %{
7575 if (os::is_MP()) { __ lock(); }
7576 __ addw($mem$$Address, $add$$constant);
7577 %}
7578 ins_pipe( pipe_cmpxchg );
7579 %}
7580
7581 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7582 match(Set newval (GetAndAddS mem newval));
7583 effect(KILL cr);
7584 format %{ "XADDW [$mem],$newval" %}
7585 ins_encode %{
7586 if (os::is_MP()) { __ lock(); }
7587 __ xaddw($mem$$Address, $newval$$Register);
7588 %}
7589 ins_pipe( pipe_cmpxchg );
7590 %}
7591
7592 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7593 predicate(n->as_LoadStore()->result_not_used());
7594 match(Set dummy (GetAndAddI mem add));
7595 effect(KILL cr);
7596 format %{ "ADDL [$mem],$add" %}
7597 ins_encode %{
7598 if (os::is_MP()) { __ lock(); }
7599 __ addl($mem$$Address, $add$$constant);
7600 %}
7601 ins_pipe( pipe_cmpxchg );
7602 %}
7603
7604 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7605 match(Set newval (GetAndAddI mem newval));
7606 effect(KILL cr);
7607 format %{ "XADDL [$mem],$newval" %}
7608 ins_encode %{
7609 if (os::is_MP()) { __ lock(); }
7610 __ xaddl($mem$$Address, $newval$$Register);
7611 %}
7612 ins_pipe( pipe_cmpxchg );
7613 %}
7614
7615 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7616 predicate(n->as_LoadStore()->result_not_used());
7617 match(Set dummy (GetAndAddL mem add));
7618 effect(KILL cr);
7619 format %{ "ADDQ [$mem],$add" %}
7620 ins_encode %{
7621 if (os::is_MP()) { __ lock(); }
7622 __ addq($mem$$Address, $add$$constant);
7623 %}
7624 ins_pipe( pipe_cmpxchg );
7625 %}
7626
7627 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7628 match(Set newval (GetAndAddL mem newval));
7629 effect(KILL cr);
7630 format %{ "XADDQ [$mem],$newval" %}
7631 ins_encode %{
7632 if (os::is_MP()) { __ lock(); }
7633 __ xaddq($mem$$Address, $newval$$Register);
7634 %}
7635 ins_pipe( pipe_cmpxchg );
7636 %}
7637
7638 instruct xchgB( memory mem, rRegI newval) %{
7639 match(Set newval (GetAndSetB mem newval));
7640 format %{ "XCHGB $newval,[$mem]" %}
7641 ins_encode %{
7642 __ xchgb($newval$$Register, $mem$$Address);
7643 %}
7644 ins_pipe( pipe_cmpxchg );
7645 %}
7646
7647 instruct xchgS( memory mem, rRegI newval) %{
7648 match(Set newval (GetAndSetS mem newval));
7649 format %{ "XCHGW $newval,[$mem]" %}
7650 ins_encode %{
7651 __ xchgw($newval$$Register, $mem$$Address);
7652 %}
7653 ins_pipe( pipe_cmpxchg );
7654 %}
7655
7656 instruct xchgI( memory mem, rRegI newval) %{
7657 match(Set newval (GetAndSetI mem newval));
7658 format %{ "XCHGL $newval,[$mem]" %}
7659 ins_encode %{
7660 __ xchgl($newval$$Register, $mem$$Address);
7661 %}
7662 ins_pipe( pipe_cmpxchg );
7663 %}
7664
7665 instruct xchgL( memory mem, rRegL newval) %{
7666 match(Set newval (GetAndSetL mem newval));
7667 format %{ "XCHGL $newval,[$mem]" %}
7668 ins_encode %{
7669 __ xchgq($newval$$Register, $mem$$Address);
7670 %}
7671 ins_pipe( pipe_cmpxchg );
7672 %}
7673
7674 instruct xchgP( memory mem, rRegP newval) %{
7675 match(Set newval (GetAndSetP mem newval));
7676 format %{ "XCHGQ $newval,[$mem]" %}
7677 ins_encode %{
7678 __ xchgq($newval$$Register, $mem$$Address);
7679 %}
7680 ins_pipe( pipe_cmpxchg );
7681 %}
7682
7683 instruct xchgN( memory mem, rRegN newval) %{
7684 match(Set newval (GetAndSetN mem newval));
7685 format %{ "XCHGL $newval,$mem]" %}
7686 ins_encode %{
7687 __ xchgl($newval$$Register, $mem$$Address);
7688 %}
7689 ins_pipe( pipe_cmpxchg );
7690 %}
7691
7692 //----------Subtraction Instructions-------------------------------------------
7693
7694 // Integer Subtraction Instructions
7695 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7696 %{
7697 match(Set dst (SubI dst src));
7698 effect(KILL cr);
7699
7700 format %{ "subl $dst, $src\t# int" %}
7701 opcode(0x2B);
7702 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7703 ins_pipe(ialu_reg_reg);
7704 %}
7705
7706 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7707 %{
7708 match(Set dst (SubI dst src));
7709 effect(KILL cr);
7710
7711 format %{ "subl $dst, $src\t# int" %}
7712 opcode(0x81, 0x05); /* Opcode 81 /5 */
7713 ins_encode(OpcSErm(dst, src), Con8or32(src));
7714 ins_pipe(ialu_reg);
7715 %}
7716
7717 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7718 %{
7719 match(Set dst (SubI dst (LoadI src)));
7720 effect(KILL cr);
7721
7722 ins_cost(125);
7723 format %{ "subl $dst, $src\t# int" %}
7724 opcode(0x2B);
7725 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7726 ins_pipe(ialu_reg_mem);
7727 %}
7728
7729 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7730 %{
7731 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7732 effect(KILL cr);
7733
7734 ins_cost(150);
7735 format %{ "subl $dst, $src\t# int" %}
7736 opcode(0x29); /* Opcode 29 /r */
7737 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7738 ins_pipe(ialu_mem_reg);
7739 %}
7740
7741 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7742 %{
7743 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7744 effect(KILL cr);
7745
7746 ins_cost(125); // XXX
7747 format %{ "subl $dst, $src\t# int" %}
7748 opcode(0x81); /* Opcode 81 /5 id */
7749 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7750 ins_pipe(ialu_mem_imm);
7751 %}
7752
7753 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7754 %{
7755 match(Set dst (SubL dst src));
7756 effect(KILL cr);
7757
7758 format %{ "subq $dst, $src\t# long" %}
7759 opcode(0x2B);
7760 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7761 ins_pipe(ialu_reg_reg);
7762 %}
7763
7764 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7765 %{
7766 match(Set dst (SubL dst src));
7767 effect(KILL cr);
7768
7769 format %{ "subq $dst, $src\t# long" %}
7770 opcode(0x81, 0x05); /* Opcode 81 /5 */
7771 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7772 ins_pipe(ialu_reg);
7773 %}
7774
7775 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7776 %{
7777 match(Set dst (SubL dst (LoadL src)));
7778 effect(KILL cr);
7779
7780 ins_cost(125);
7781 format %{ "subq $dst, $src\t# long" %}
7782 opcode(0x2B);
7783 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7784 ins_pipe(ialu_reg_mem);
7785 %}
7786
7787 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7788 %{
7789 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7790 effect(KILL cr);
7791
7792 ins_cost(150);
7793 format %{ "subq $dst, $src\t# long" %}
7794 opcode(0x29); /* Opcode 29 /r */
7795 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7796 ins_pipe(ialu_mem_reg);
7797 %}
7798
7799 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7800 %{
7801 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7802 effect(KILL cr);
7803
7804 ins_cost(125); // XXX
7805 format %{ "subq $dst, $src\t# long" %}
7806 opcode(0x81); /* Opcode 81 /5 id */
7807 ins_encode(REX_mem_wide(dst),
7808 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7809 ins_pipe(ialu_mem_imm);
7810 %}
7811
7812 // Subtract from a pointer
7813 // XXX hmpf???
7814 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7815 %{
7816 match(Set dst (AddP dst (SubI zero src)));
7817 effect(KILL cr);
7818
7819 format %{ "subq $dst, $src\t# ptr - int" %}
7820 opcode(0x2B);
7821 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7822 ins_pipe(ialu_reg_reg);
7823 %}
7824
7825 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7826 %{
7827 match(Set dst (SubI zero dst));
7828 effect(KILL cr);
7829
7830 format %{ "negl $dst\t# int" %}
7831 opcode(0xF7, 0x03); // Opcode F7 /3
7832 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7833 ins_pipe(ialu_reg);
7834 %}
7835
7836 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7837 %{
7838 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7839 effect(KILL cr);
7840
7841 format %{ "negl $dst\t# int" %}
7842 opcode(0xF7, 0x03); // Opcode F7 /3
7843 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7844 ins_pipe(ialu_reg);
7845 %}
7846
7847 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7848 %{
7849 match(Set dst (SubL zero dst));
7850 effect(KILL cr);
7851
7852 format %{ "negq $dst\t# long" %}
7853 opcode(0xF7, 0x03); // Opcode F7 /3
7854 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7855 ins_pipe(ialu_reg);
7856 %}
7857
7858 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7859 %{
7860 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7861 effect(KILL cr);
7862
7863 format %{ "negq $dst\t# long" %}
7864 opcode(0xF7, 0x03); // Opcode F7 /3
7865 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7866 ins_pipe(ialu_reg);
7867 %}
7868
7869 //----------Multiplication/Division Instructions-------------------------------
7870 // Integer Multiplication Instructions
7871 // Multiply Register
7872
7873 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7874 %{
7875 match(Set dst (MulI dst src));
7876 effect(KILL cr);
7877
7878 ins_cost(300);
7879 format %{ "imull $dst, $src\t# int" %}
7880 opcode(0x0F, 0xAF);
7881 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7882 ins_pipe(ialu_reg_reg_alu0);
7883 %}
7884
7885 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7886 %{
7887 match(Set dst (MulI src imm));
7888 effect(KILL cr);
7889
7890 ins_cost(300);
7891 format %{ "imull $dst, $src, $imm\t# int" %}
7892 opcode(0x69); /* 69 /r id */
7893 ins_encode(REX_reg_reg(dst, src),
7894 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7895 ins_pipe(ialu_reg_reg_alu0);
7896 %}
7897
7898 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7899 %{
7900 match(Set dst (MulI dst (LoadI src)));
7901 effect(KILL cr);
7902
7903 ins_cost(350);
7904 format %{ "imull $dst, $src\t# int" %}
7905 opcode(0x0F, 0xAF);
7906 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7907 ins_pipe(ialu_reg_mem_alu0);
7908 %}
7909
7910 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7911 %{
7912 match(Set dst (MulI (LoadI src) imm));
7913 effect(KILL cr);
7914
7915 ins_cost(300);
7916 format %{ "imull $dst, $src, $imm\t# int" %}
7917 opcode(0x69); /* 69 /r id */
7918 ins_encode(REX_reg_mem(dst, src),
7919 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7920 ins_pipe(ialu_reg_mem_alu0);
7921 %}
7922
7923 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7924 %{
7925 match(Set dst (MulL dst src));
7926 effect(KILL cr);
7927
7928 ins_cost(300);
7929 format %{ "imulq $dst, $src\t# long" %}
7930 opcode(0x0F, 0xAF);
7931 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7932 ins_pipe(ialu_reg_reg_alu0);
7933 %}
7934
7935 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7936 %{
7937 match(Set dst (MulL src imm));
7938 effect(KILL cr);
7939
7940 ins_cost(300);
7941 format %{ "imulq $dst, $src, $imm\t# long" %}
7942 opcode(0x69); /* 69 /r id */
7943 ins_encode(REX_reg_reg_wide(dst, src),
7944 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7945 ins_pipe(ialu_reg_reg_alu0);
7946 %}
7947
7948 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7949 %{
7950 match(Set dst (MulL dst (LoadL src)));
7951 effect(KILL cr);
7952
7953 ins_cost(350);
7954 format %{ "imulq $dst, $src\t# long" %}
7955 opcode(0x0F, 0xAF);
7956 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7957 ins_pipe(ialu_reg_mem_alu0);
7958 %}
7959
7960 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7961 %{
7962 match(Set dst (MulL (LoadL src) imm));
7963 effect(KILL cr);
7964
7965 ins_cost(300);
7966 format %{ "imulq $dst, $src, $imm\t# long" %}
7967 opcode(0x69); /* 69 /r id */
7968 ins_encode(REX_reg_mem_wide(dst, src),
7969 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7970 ins_pipe(ialu_reg_mem_alu0);
7971 %}
7972
7973 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7974 %{
7975 match(Set dst (MulHiL src rax));
7976 effect(USE_KILL rax, KILL cr);
7977
7978 ins_cost(300);
7979 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7980 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7981 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7982 ins_pipe(ialu_reg_reg_alu0);
7983 %}
7984
7985 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7986 rFlagsReg cr)
7987 %{
7988 match(Set rax (DivI rax div));
7989 effect(KILL rdx, KILL cr);
7990
7991 ins_cost(30*100+10*100); // XXX
7992 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7993 "jne,s normal\n\t"
7994 "xorl rdx, rdx\n\t"
7995 "cmpl $div, -1\n\t"
7996 "je,s done\n"
7997 "normal: cdql\n\t"
7998 "idivl $div\n"
7999 "done:" %}
8000 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8001 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8002 ins_pipe(ialu_reg_reg_alu0);
8003 %}
8004
8005 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8006 rFlagsReg cr)
8007 %{
8008 match(Set rax (DivL rax div));
8009 effect(KILL rdx, KILL cr);
8010
8011 ins_cost(30*100+10*100); // XXX
8012 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8013 "cmpq rax, rdx\n\t"
8014 "jne,s normal\n\t"
8015 "xorl rdx, rdx\n\t"
8016 "cmpq $div, -1\n\t"
8017 "je,s done\n"
8018 "normal: cdqq\n\t"
8019 "idivq $div\n"
8020 "done:" %}
8021 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8022 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8023 ins_pipe(ialu_reg_reg_alu0);
8024 %}
8025
8026 // Integer DIVMOD with Register, both quotient and mod results
8027 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8028 rFlagsReg cr)
8029 %{
8030 match(DivModI rax div);
8031 effect(KILL cr);
8032
8033 ins_cost(30*100+10*100); // XXX
8034 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8035 "jne,s normal\n\t"
8036 "xorl rdx, rdx\n\t"
8037 "cmpl $div, -1\n\t"
8038 "je,s done\n"
8039 "normal: cdql\n\t"
8040 "idivl $div\n"
8041 "done:" %}
8042 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8043 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8044 ins_pipe(pipe_slow);
8045 %}
8046
8047 // Long DIVMOD with Register, both quotient and mod results
8048 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8049 rFlagsReg cr)
8050 %{
8051 match(DivModL rax div);
8052 effect(KILL cr);
8053
8054 ins_cost(30*100+10*100); // XXX
8055 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8056 "cmpq rax, rdx\n\t"
8057 "jne,s normal\n\t"
8058 "xorl rdx, rdx\n\t"
8059 "cmpq $div, -1\n\t"
8060 "je,s done\n"
8061 "normal: cdqq\n\t"
8062 "idivq $div\n"
8063 "done:" %}
8064 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8065 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8066 ins_pipe(pipe_slow);
8067 %}
8068
8069 //----------- DivL-By-Constant-Expansions--------------------------------------
8070 // DivI cases are handled by the compiler
8071
8072 // Magic constant, reciprocal of 10
8073 instruct loadConL_0x6666666666666667(rRegL dst)
8074 %{
8075 effect(DEF dst);
8076
8077 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8078 ins_encode(load_immL(dst, 0x6666666666666667));
8079 ins_pipe(ialu_reg);
8080 %}
8081
8082 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8083 %{
8084 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8085
8086 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8087 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8088 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8089 ins_pipe(ialu_reg_reg_alu0);
8090 %}
8091
8092 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8093 %{
8094 effect(USE_DEF dst, KILL cr);
8095
8096 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8097 opcode(0xC1, 0x7); /* C1 /7 ib */
8098 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8099 ins_pipe(ialu_reg);
8100 %}
8101
8102 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8103 %{
8104 effect(USE_DEF dst, KILL cr);
8105
8106 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8107 opcode(0xC1, 0x7); /* C1 /7 ib */
8108 ins_encode(reg_opc_imm_wide(dst, 0x2));
8109 ins_pipe(ialu_reg);
8110 %}
8111
8112 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8113 %{
8114 match(Set dst (DivL src div));
8115
8116 ins_cost((5+8)*100);
8117 expand %{
8118 rax_RegL rax; // Killed temp
8119 rFlagsReg cr; // Killed
8120 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8121 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8122 sarL_rReg_63(src, cr); // sarq src, 63
8123 sarL_rReg_2(dst, cr); // sarq rdx, 2
8124 subL_rReg(dst, src, cr); // subl rdx, src
8125 %}
8126 %}
8127
8128 //-----------------------------------------------------------------------------
8129
8130 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8131 rFlagsReg cr)
8132 %{
8133 match(Set rdx (ModI rax div));
8134 effect(KILL rax, KILL cr);
8135
8136 ins_cost(300); // XXX
8137 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8138 "jne,s normal\n\t"
8139 "xorl rdx, rdx\n\t"
8140 "cmpl $div, -1\n\t"
8141 "je,s done\n"
8142 "normal: cdql\n\t"
8143 "idivl $div\n"
8144 "done:" %}
8145 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8146 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8147 ins_pipe(ialu_reg_reg_alu0);
8148 %}
8149
8150 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8151 rFlagsReg cr)
8152 %{
8153 match(Set rdx (ModL rax div));
8154 effect(KILL rax, KILL cr);
8155
8156 ins_cost(300); // XXX
8157 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8158 "cmpq rax, rdx\n\t"
8159 "jne,s normal\n\t"
8160 "xorl rdx, rdx\n\t"
8161 "cmpq $div, -1\n\t"
8162 "je,s done\n"
8163 "normal: cdqq\n\t"
8164 "idivq $div\n"
8165 "done:" %}
8166 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8167 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8168 ins_pipe(ialu_reg_reg_alu0);
8169 %}
8170
8171 // Integer Shift Instructions
8172 // Shift Left by one
8173 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8174 %{
8175 match(Set dst (LShiftI dst shift));
8176 effect(KILL cr);
8177
8178 format %{ "sall $dst, $shift" %}
8179 opcode(0xD1, 0x4); /* D1 /4 */
8180 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8181 ins_pipe(ialu_reg);
8182 %}
8183
8184 // Shift Left by one
8185 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8186 %{
8187 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8188 effect(KILL cr);
8189
8190 format %{ "sall $dst, $shift\t" %}
8191 opcode(0xD1, 0x4); /* D1 /4 */
8192 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8193 ins_pipe(ialu_mem_imm);
8194 %}
8195
8196 // Shift Left by 8-bit immediate
8197 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8198 %{
8199 match(Set dst (LShiftI dst shift));
8200 effect(KILL cr);
8201
8202 format %{ "sall $dst, $shift" %}
8203 opcode(0xC1, 0x4); /* C1 /4 ib */
8204 ins_encode(reg_opc_imm(dst, shift));
8205 ins_pipe(ialu_reg);
8206 %}
8207
8208 // Shift Left by 8-bit immediate
8209 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8210 %{
8211 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8212 effect(KILL cr);
8213
8214 format %{ "sall $dst, $shift" %}
8215 opcode(0xC1, 0x4); /* C1 /4 ib */
8216 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8217 ins_pipe(ialu_mem_imm);
8218 %}
8219
8220 // Shift Left by variable
8221 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8222 %{
8223 match(Set dst (LShiftI dst shift));
8224 effect(KILL cr);
8225
8226 format %{ "sall $dst, $shift" %}
8227 opcode(0xD3, 0x4); /* D3 /4 */
8228 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8229 ins_pipe(ialu_reg_reg);
8230 %}
8231
8232 // Shift Left by variable
8233 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8234 %{
8235 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8236 effect(KILL cr);
8237
8238 format %{ "sall $dst, $shift" %}
8239 opcode(0xD3, 0x4); /* D3 /4 */
8240 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8241 ins_pipe(ialu_mem_reg);
8242 %}
8243
8244 // Arithmetic shift right by one
8245 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8246 %{
8247 match(Set dst (RShiftI dst shift));
8248 effect(KILL cr);
8249
8250 format %{ "sarl $dst, $shift" %}
8251 opcode(0xD1, 0x7); /* D1 /7 */
8252 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8253 ins_pipe(ialu_reg);
8254 %}
8255
8256 // Arithmetic shift right by one
8257 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8258 %{
8259 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8260 effect(KILL cr);
8261
8262 format %{ "sarl $dst, $shift" %}
8263 opcode(0xD1, 0x7); /* D1 /7 */
8264 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8265 ins_pipe(ialu_mem_imm);
8266 %}
8267
8268 // Arithmetic Shift Right by 8-bit immediate
8269 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8270 %{
8271 match(Set dst (RShiftI dst shift));
8272 effect(KILL cr);
8273
8274 format %{ "sarl $dst, $shift" %}
8275 opcode(0xC1, 0x7); /* C1 /7 ib */
8276 ins_encode(reg_opc_imm(dst, shift));
8277 ins_pipe(ialu_mem_imm);
8278 %}
8279
8280 // Arithmetic Shift Right by 8-bit immediate
8281 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8282 %{
8283 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8284 effect(KILL cr);
8285
8286 format %{ "sarl $dst, $shift" %}
8287 opcode(0xC1, 0x7); /* C1 /7 ib */
8288 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8289 ins_pipe(ialu_mem_imm);
8290 %}
8291
8292 // Arithmetic Shift Right by variable
8293 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8294 %{
8295 match(Set dst (RShiftI dst shift));
8296 effect(KILL cr);
8297
8298 format %{ "sarl $dst, $shift" %}
8299 opcode(0xD3, 0x7); /* D3 /7 */
8300 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8301 ins_pipe(ialu_reg_reg);
8302 %}
8303
8304 // Arithmetic Shift Right by variable
8305 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8306 %{
8307 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8308 effect(KILL cr);
8309
8310 format %{ "sarl $dst, $shift" %}
8311 opcode(0xD3, 0x7); /* D3 /7 */
8312 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8313 ins_pipe(ialu_mem_reg);
8314 %}
8315
8316 // Logical shift right by one
8317 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8318 %{
8319 match(Set dst (URShiftI dst shift));
8320 effect(KILL cr);
8321
8322 format %{ "shrl $dst, $shift" %}
8323 opcode(0xD1, 0x5); /* D1 /5 */
8324 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8325 ins_pipe(ialu_reg);
8326 %}
8327
8328 // Logical shift right by one
8329 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8330 %{
8331 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8332 effect(KILL cr);
8333
8334 format %{ "shrl $dst, $shift" %}
8335 opcode(0xD1, 0x5); /* D1 /5 */
8336 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8337 ins_pipe(ialu_mem_imm);
8338 %}
8339
8340 // Logical Shift Right by 8-bit immediate
8341 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8342 %{
8343 match(Set dst (URShiftI dst shift));
8344 effect(KILL cr);
8345
8346 format %{ "shrl $dst, $shift" %}
8347 opcode(0xC1, 0x5); /* C1 /5 ib */
8348 ins_encode(reg_opc_imm(dst, shift));
8349 ins_pipe(ialu_reg);
8350 %}
8351
8352 // Logical Shift Right by 8-bit immediate
8353 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8354 %{
8355 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8356 effect(KILL cr);
8357
8358 format %{ "shrl $dst, $shift" %}
8359 opcode(0xC1, 0x5); /* C1 /5 ib */
8360 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8361 ins_pipe(ialu_mem_imm);
8362 %}
8363
8364 // Logical Shift Right by variable
8365 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8366 %{
8367 match(Set dst (URShiftI dst shift));
8368 effect(KILL cr);
8369
8370 format %{ "shrl $dst, $shift" %}
8371 opcode(0xD3, 0x5); /* D3 /5 */
8372 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8373 ins_pipe(ialu_reg_reg);
8374 %}
8375
8376 // Logical Shift Right by variable
8377 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8378 %{
8379 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8380 effect(KILL cr);
8381
8382 format %{ "shrl $dst, $shift" %}
8383 opcode(0xD3, 0x5); /* D3 /5 */
8384 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8385 ins_pipe(ialu_mem_reg);
8386 %}
8387
8388 // Long Shift Instructions
8389 // Shift Left by one
8390 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8391 %{
8392 match(Set dst (LShiftL dst shift));
8393 effect(KILL cr);
8394
8395 format %{ "salq $dst, $shift" %}
8396 opcode(0xD1, 0x4); /* D1 /4 */
8397 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8398 ins_pipe(ialu_reg);
8399 %}
8400
8401 // Shift Left by one
8402 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8403 %{
8404 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8405 effect(KILL cr);
8406
8407 format %{ "salq $dst, $shift" %}
8408 opcode(0xD1, 0x4); /* D1 /4 */
8409 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8410 ins_pipe(ialu_mem_imm);
8411 %}
8412
8413 // Shift Left by 8-bit immediate
8414 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8415 %{
8416 match(Set dst (LShiftL dst shift));
8417 effect(KILL cr);
8418
8419 format %{ "salq $dst, $shift" %}
8420 opcode(0xC1, 0x4); /* C1 /4 ib */
8421 ins_encode(reg_opc_imm_wide(dst, shift));
8422 ins_pipe(ialu_reg);
8423 %}
8424
8425 // Shift Left by 8-bit immediate
8426 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8427 %{
8428 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8429 effect(KILL cr);
8430
8431 format %{ "salq $dst, $shift" %}
8432 opcode(0xC1, 0x4); /* C1 /4 ib */
8433 ins_encode(REX_mem_wide(dst), OpcP,
8434 RM_opc_mem(secondary, dst), Con8or32(shift));
8435 ins_pipe(ialu_mem_imm);
8436 %}
8437
8438 // Shift Left by variable
8439 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8440 %{
8441 match(Set dst (LShiftL dst shift));
8442 effect(KILL cr);
8443
8444 format %{ "salq $dst, $shift" %}
8445 opcode(0xD3, 0x4); /* D3 /4 */
8446 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8447 ins_pipe(ialu_reg_reg);
8448 %}
8449
8450 // Shift Left by variable
8451 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8452 %{
8453 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8454 effect(KILL cr);
8455
8456 format %{ "salq $dst, $shift" %}
8457 opcode(0xD3, 0x4); /* D3 /4 */
8458 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8459 ins_pipe(ialu_mem_reg);
8460 %}
8461
8462 // Arithmetic shift right by one
8463 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8464 %{
8465 match(Set dst (RShiftL dst shift));
8466 effect(KILL cr);
8467
8468 format %{ "sarq $dst, $shift" %}
8469 opcode(0xD1, 0x7); /* D1 /7 */
8470 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8471 ins_pipe(ialu_reg);
8472 %}
8473
8474 // Arithmetic shift right by one
8475 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8476 %{
8477 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8478 effect(KILL cr);
8479
8480 format %{ "sarq $dst, $shift" %}
8481 opcode(0xD1, 0x7); /* D1 /7 */
8482 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8483 ins_pipe(ialu_mem_imm);
8484 %}
8485
8486 // Arithmetic Shift Right by 8-bit immediate
8487 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8488 %{
8489 match(Set dst (RShiftL dst shift));
8490 effect(KILL cr);
8491
8492 format %{ "sarq $dst, $shift" %}
8493 opcode(0xC1, 0x7); /* C1 /7 ib */
8494 ins_encode(reg_opc_imm_wide(dst, shift));
8495 ins_pipe(ialu_mem_imm);
8496 %}
8497
8498 // Arithmetic Shift Right by 8-bit immediate
8499 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8500 %{
8501 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8502 effect(KILL cr);
8503
8504 format %{ "sarq $dst, $shift" %}
8505 opcode(0xC1, 0x7); /* C1 /7 ib */
8506 ins_encode(REX_mem_wide(dst), OpcP,
8507 RM_opc_mem(secondary, dst), Con8or32(shift));
8508 ins_pipe(ialu_mem_imm);
8509 %}
8510
8511 // Arithmetic Shift Right by variable
8512 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8513 %{
8514 match(Set dst (RShiftL dst shift));
8515 effect(KILL cr);
8516
8517 format %{ "sarq $dst, $shift" %}
8518 opcode(0xD3, 0x7); /* D3 /7 */
8519 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8520 ins_pipe(ialu_reg_reg);
8521 %}
8522
8523 // Arithmetic Shift Right by variable
8524 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8525 %{
8526 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8527 effect(KILL cr);
8528
8529 format %{ "sarq $dst, $shift" %}
8530 opcode(0xD3, 0x7); /* D3 /7 */
8531 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8532 ins_pipe(ialu_mem_reg);
8533 %}
8534
8535 // Logical shift right by one
8536 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8537 %{
8538 match(Set dst (URShiftL dst shift));
8539 effect(KILL cr);
8540
8541 format %{ "shrq $dst, $shift" %}
8542 opcode(0xD1, 0x5); /* D1 /5 */
8543 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8544 ins_pipe(ialu_reg);
8545 %}
8546
8547 // Logical shift right by one
8548 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8549 %{
8550 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8551 effect(KILL cr);
8552
8553 format %{ "shrq $dst, $shift" %}
8554 opcode(0xD1, 0x5); /* D1 /5 */
8555 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8556 ins_pipe(ialu_mem_imm);
8557 %}
8558
8559 // Logical Shift Right by 8-bit immediate
8560 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8561 %{
8562 match(Set dst (URShiftL dst shift));
8563 effect(KILL cr);
8564
8565 format %{ "shrq $dst, $shift" %}
8566 opcode(0xC1, 0x5); /* C1 /5 ib */
8567 ins_encode(reg_opc_imm_wide(dst, shift));
8568 ins_pipe(ialu_reg);
8569 %}
8570
8571
8572 // Logical Shift Right by 8-bit immediate
8573 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8574 %{
8575 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8576 effect(KILL cr);
8577
8578 format %{ "shrq $dst, $shift" %}
8579 opcode(0xC1, 0x5); /* C1 /5 ib */
8580 ins_encode(REX_mem_wide(dst), OpcP,
8581 RM_opc_mem(secondary, dst), Con8or32(shift));
8582 ins_pipe(ialu_mem_imm);
8583 %}
8584
8585 // Logical Shift Right by variable
8586 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8587 %{
8588 match(Set dst (URShiftL dst shift));
8589 effect(KILL cr);
8590
8591 format %{ "shrq $dst, $shift" %}
8592 opcode(0xD3, 0x5); /* D3 /5 */
8593 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8594 ins_pipe(ialu_reg_reg);
8595 %}
8596
8597 // Logical Shift Right by variable
8598 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8599 %{
8600 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8601 effect(KILL cr);
8602
8603 format %{ "shrq $dst, $shift" %}
8604 opcode(0xD3, 0x5); /* D3 /5 */
8605 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8606 ins_pipe(ialu_mem_reg);
8607 %}
8608
8609 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8610 // This idiom is used by the compiler for the i2b bytecode.
8611 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8612 %{
8613 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8614
8615 format %{ "movsbl $dst, $src\t# i2b" %}
8616 opcode(0x0F, 0xBE);
8617 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8618 ins_pipe(ialu_reg_reg);
8619 %}
8620
8621 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8622 // This idiom is used by the compiler the i2s bytecode.
8623 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8624 %{
8625 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8626
8627 format %{ "movswl $dst, $src\t# i2s" %}
8628 opcode(0x0F, 0xBF);
8629 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8630 ins_pipe(ialu_reg_reg);
8631 %}
8632
8633 // ROL/ROR instructions
8634
8635 // ROL expand
8636 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8637 effect(KILL cr, USE_DEF dst);
8638
8639 format %{ "roll $dst" %}
8640 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8641 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8642 ins_pipe(ialu_reg);
8643 %}
8644
8645 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8646 effect(USE_DEF dst, USE shift, KILL cr);
8647
8648 format %{ "roll $dst, $shift" %}
8649 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8650 ins_encode( reg_opc_imm(dst, shift) );
8651 ins_pipe(ialu_reg);
8652 %}
8653
8654 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8655 %{
8656 effect(USE_DEF dst, USE shift, KILL cr);
8657
8658 format %{ "roll $dst, $shift" %}
8659 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8660 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8661 ins_pipe(ialu_reg_reg);
8662 %}
8663 // end of ROL expand
8664
8665 // Rotate Left by one
8666 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8667 %{
8668 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8669
8670 expand %{
8671 rolI_rReg_imm1(dst, cr);
8672 %}
8673 %}
8674
8675 // Rotate Left by 8-bit immediate
8676 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8677 %{
8678 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8679 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8680
8681 expand %{
8682 rolI_rReg_imm8(dst, lshift, cr);
8683 %}
8684 %}
8685
8686 // Rotate Left by variable
8687 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8688 %{
8689 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8690
8691 expand %{
8692 rolI_rReg_CL(dst, shift, cr);
8693 %}
8694 %}
8695
8696 // Rotate Left by variable
8697 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8698 %{
8699 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8700
8701 expand %{
8702 rolI_rReg_CL(dst, shift, cr);
8703 %}
8704 %}
8705
8706 // ROR expand
8707 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8708 %{
8709 effect(USE_DEF dst, KILL cr);
8710
8711 format %{ "rorl $dst" %}
8712 opcode(0xD1, 0x1); /* D1 /1 */
8713 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8714 ins_pipe(ialu_reg);
8715 %}
8716
8717 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8718 %{
8719 effect(USE_DEF dst, USE shift, KILL cr);
8720
8721 format %{ "rorl $dst, $shift" %}
8722 opcode(0xC1, 0x1); /* C1 /1 ib */
8723 ins_encode(reg_opc_imm(dst, shift));
8724 ins_pipe(ialu_reg);
8725 %}
8726
8727 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8728 %{
8729 effect(USE_DEF dst, USE shift, KILL cr);
8730
8731 format %{ "rorl $dst, $shift" %}
8732 opcode(0xD3, 0x1); /* D3 /1 */
8733 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8734 ins_pipe(ialu_reg_reg);
8735 %}
8736 // end of ROR expand
8737
8738 // Rotate Right by one
8739 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8740 %{
8741 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8742
8743 expand %{
8744 rorI_rReg_imm1(dst, cr);
8745 %}
8746 %}
8747
8748 // Rotate Right by 8-bit immediate
8749 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8750 %{
8751 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8752 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8753
8754 expand %{
8755 rorI_rReg_imm8(dst, rshift, cr);
8756 %}
8757 %}
8758
8759 // Rotate Right by variable
8760 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8761 %{
8762 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8763
8764 expand %{
8765 rorI_rReg_CL(dst, shift, cr);
8766 %}
8767 %}
8768
8769 // Rotate Right by variable
8770 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8771 %{
8772 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8773
8774 expand %{
8775 rorI_rReg_CL(dst, shift, cr);
8776 %}
8777 %}
8778
8779 // for long rotate
8780 // ROL expand
8781 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8782 effect(USE_DEF dst, KILL cr);
8783
8784 format %{ "rolq $dst" %}
8785 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8786 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8787 ins_pipe(ialu_reg);
8788 %}
8789
8790 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8791 effect(USE_DEF dst, USE shift, KILL cr);
8792
8793 format %{ "rolq $dst, $shift" %}
8794 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8795 ins_encode( reg_opc_imm_wide(dst, shift) );
8796 ins_pipe(ialu_reg);
8797 %}
8798
8799 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8800 %{
8801 effect(USE_DEF dst, USE shift, KILL cr);
8802
8803 format %{ "rolq $dst, $shift" %}
8804 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8805 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8806 ins_pipe(ialu_reg_reg);
8807 %}
8808 // end of ROL expand
8809
8810 // Rotate Left by one
8811 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8812 %{
8813 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8814
8815 expand %{
8816 rolL_rReg_imm1(dst, cr);
8817 %}
8818 %}
8819
8820 // Rotate Left by 8-bit immediate
8821 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8822 %{
8823 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8824 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8825
8826 expand %{
8827 rolL_rReg_imm8(dst, lshift, cr);
8828 %}
8829 %}
8830
8831 // Rotate Left by variable
8832 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8833 %{
8834 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8835
8836 expand %{
8837 rolL_rReg_CL(dst, shift, cr);
8838 %}
8839 %}
8840
8841 // Rotate Left by variable
8842 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8843 %{
8844 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8845
8846 expand %{
8847 rolL_rReg_CL(dst, shift, cr);
8848 %}
8849 %}
8850
8851 // ROR expand
8852 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8853 %{
8854 effect(USE_DEF dst, KILL cr);
8855
8856 format %{ "rorq $dst" %}
8857 opcode(0xD1, 0x1); /* D1 /1 */
8858 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8859 ins_pipe(ialu_reg);
8860 %}
8861
8862 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8863 %{
8864 effect(USE_DEF dst, USE shift, KILL cr);
8865
8866 format %{ "rorq $dst, $shift" %}
8867 opcode(0xC1, 0x1); /* C1 /1 ib */
8868 ins_encode(reg_opc_imm_wide(dst, shift));
8869 ins_pipe(ialu_reg);
8870 %}
8871
8872 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8873 %{
8874 effect(USE_DEF dst, USE shift, KILL cr);
8875
8876 format %{ "rorq $dst, $shift" %}
8877 opcode(0xD3, 0x1); /* D3 /1 */
8878 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8879 ins_pipe(ialu_reg_reg);
8880 %}
8881 // end of ROR expand
8882
8883 // Rotate Right by one
8884 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8885 %{
8886 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8887
8888 expand %{
8889 rorL_rReg_imm1(dst, cr);
8890 %}
8891 %}
8892
8893 // Rotate Right by 8-bit immediate
8894 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8895 %{
8896 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8897 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8898
8899 expand %{
8900 rorL_rReg_imm8(dst, rshift, cr);
8901 %}
8902 %}
8903
8904 // Rotate Right by variable
8905 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8906 %{
8907 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8908
8909 expand %{
8910 rorL_rReg_CL(dst, shift, cr);
8911 %}
8912 %}
8913
8914 // Rotate Right by variable
8915 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8916 %{
8917 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8918
8919 expand %{
8920 rorL_rReg_CL(dst, shift, cr);
8921 %}
8922 %}
8923
8924 // Logical Instructions
8925
8926 // Integer Logical Instructions
8927
8928 // And Instructions
8929 // And Register with Register
8930 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8931 %{
8932 match(Set dst (AndI dst src));
8933 effect(KILL cr);
8934
8935 format %{ "andl $dst, $src\t# int" %}
8936 opcode(0x23);
8937 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8938 ins_pipe(ialu_reg_reg);
8939 %}
8940
8941 // And Register with Immediate 255
8942 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8943 %{
8944 match(Set dst (AndI dst src));
8945
8946 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8947 opcode(0x0F, 0xB6);
8948 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8949 ins_pipe(ialu_reg);
8950 %}
8951
8952 // And Register with Immediate 255 and promote to long
8953 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8954 %{
8955 match(Set dst (ConvI2L (AndI src mask)));
8956
8957 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8958 opcode(0x0F, 0xB6);
8959 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8960 ins_pipe(ialu_reg);
8961 %}
8962
8963 // And Register with Immediate 65535
8964 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8965 %{
8966 match(Set dst (AndI dst src));
8967
8968 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8969 opcode(0x0F, 0xB7);
8970 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8971 ins_pipe(ialu_reg);
8972 %}
8973
8974 // And Register with Immediate 65535 and promote to long
8975 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8976 %{
8977 match(Set dst (ConvI2L (AndI src mask)));
8978
8979 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8980 opcode(0x0F, 0xB7);
8981 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8982 ins_pipe(ialu_reg);
8983 %}
8984
8985 // And Register with Immediate
8986 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8987 %{
8988 match(Set dst (AndI dst src));
8989 effect(KILL cr);
8990
8991 format %{ "andl $dst, $src\t# int" %}
8992 opcode(0x81, 0x04); /* Opcode 81 /4 */
8993 ins_encode(OpcSErm(dst, src), Con8or32(src));
8994 ins_pipe(ialu_reg);
8995 %}
8996
8997 // And Register with Memory
8998 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8999 %{
9000 match(Set dst (AndI dst (LoadI src)));
9001 effect(KILL cr);
9002
9003 ins_cost(125);
9004 format %{ "andl $dst, $src\t# int" %}
9005 opcode(0x23);
9006 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9007 ins_pipe(ialu_reg_mem);
9008 %}
9009
9010 // And Memory with Register
9011 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9012 %{
9013 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9014 effect(KILL cr);
9015
9016 ins_cost(150);
9017 format %{ "andl $dst, $src\t# int" %}
9018 opcode(0x21); /* Opcode 21 /r */
9019 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9020 ins_pipe(ialu_mem_reg);
9021 %}
9022
9023 // And Memory with Immediate
9024 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9025 %{
9026 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9027 effect(KILL cr);
9028
9029 ins_cost(125);
9030 format %{ "andl $dst, $src\t# int" %}
9031 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9032 ins_encode(REX_mem(dst), OpcSE(src),
9033 RM_opc_mem(secondary, dst), Con8or32(src));
9034 ins_pipe(ialu_mem_imm);
9035 %}
9036
9037 // BMI1 instructions
9038 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9039 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9040 predicate(UseBMI1Instructions);
9041 effect(KILL cr);
9042
9043 ins_cost(125);
9044 format %{ "andnl $dst, $src1, $src2" %}
9045
9046 ins_encode %{
9047 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9048 %}
9049 ins_pipe(ialu_reg_mem);
9050 %}
9051
9052 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9053 match(Set dst (AndI (XorI src1 minus_1) src2));
9054 predicate(UseBMI1Instructions);
9055 effect(KILL cr);
9056
9057 format %{ "andnl $dst, $src1, $src2" %}
9058
9059 ins_encode %{
9060 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9061 %}
9062 ins_pipe(ialu_reg);
9063 %}
9064
9065 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9066 match(Set dst (AndI (SubI imm_zero src) src));
9067 predicate(UseBMI1Instructions);
9068 effect(KILL cr);
9069
9070 format %{ "blsil $dst, $src" %}
9071
9072 ins_encode %{
9073 __ blsil($dst$$Register, $src$$Register);
9074 %}
9075 ins_pipe(ialu_reg);
9076 %}
9077
9078 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9079 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9080 predicate(UseBMI1Instructions);
9081 effect(KILL cr);
9082
9083 ins_cost(125);
9084 format %{ "blsil $dst, $src" %}
9085
9086 ins_encode %{
9087 __ blsil($dst$$Register, $src$$Address);
9088 %}
9089 ins_pipe(ialu_reg_mem);
9090 %}
9091
9092 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9093 %{
9094 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9095 predicate(UseBMI1Instructions);
9096 effect(KILL cr);
9097
9098 ins_cost(125);
9099 format %{ "blsmskl $dst, $src" %}
9100
9101 ins_encode %{
9102 __ blsmskl($dst$$Register, $src$$Address);
9103 %}
9104 ins_pipe(ialu_reg_mem);
9105 %}
9106
9107 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9108 %{
9109 match(Set dst (XorI (AddI src minus_1) src));
9110 predicate(UseBMI1Instructions);
9111 effect(KILL cr);
9112
9113 format %{ "blsmskl $dst, $src" %}
9114
9115 ins_encode %{
9116 __ blsmskl($dst$$Register, $src$$Register);
9117 %}
9118
9119 ins_pipe(ialu_reg);
9120 %}
9121
9122 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9123 %{
9124 match(Set dst (AndI (AddI src minus_1) src) );
9125 predicate(UseBMI1Instructions);
9126 effect(KILL cr);
9127
9128 format %{ "blsrl $dst, $src" %}
9129
9130 ins_encode %{
9131 __ blsrl($dst$$Register, $src$$Register);
9132 %}
9133
9134 ins_pipe(ialu_reg_mem);
9135 %}
9136
9137 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9138 %{
9139 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9140 predicate(UseBMI1Instructions);
9141 effect(KILL cr);
9142
9143 ins_cost(125);
9144 format %{ "blsrl $dst, $src" %}
9145
9146 ins_encode %{
9147 __ blsrl($dst$$Register, $src$$Address);
9148 %}
9149
9150 ins_pipe(ialu_reg);
9151 %}
9152
9153 // Or Instructions
9154 // Or Register with Register
9155 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9156 %{
9157 match(Set dst (OrI dst src));
9158 effect(KILL cr);
9159
9160 format %{ "orl $dst, $src\t# int" %}
9161 opcode(0x0B);
9162 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9163 ins_pipe(ialu_reg_reg);
9164 %}
9165
9166 // Or Register with Immediate
9167 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9168 %{
9169 match(Set dst (OrI dst src));
9170 effect(KILL cr);
9171
9172 format %{ "orl $dst, $src\t# int" %}
9173 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9174 ins_encode(OpcSErm(dst, src), Con8or32(src));
9175 ins_pipe(ialu_reg);
9176 %}
9177
9178 // Or Register with Memory
9179 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9180 %{
9181 match(Set dst (OrI dst (LoadI src)));
9182 effect(KILL cr);
9183
9184 ins_cost(125);
9185 format %{ "orl $dst, $src\t# int" %}
9186 opcode(0x0B);
9187 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9188 ins_pipe(ialu_reg_mem);
9189 %}
9190
9191 // Or Memory with Register
9192 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9193 %{
9194 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9195 effect(KILL cr);
9196
9197 ins_cost(150);
9198 format %{ "orl $dst, $src\t# int" %}
9199 opcode(0x09); /* Opcode 09 /r */
9200 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9201 ins_pipe(ialu_mem_reg);
9202 %}
9203
9204 // Or Memory with Immediate
9205 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9206 %{
9207 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9208 effect(KILL cr);
9209
9210 ins_cost(125);
9211 format %{ "orl $dst, $src\t# int" %}
9212 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9213 ins_encode(REX_mem(dst), OpcSE(src),
9214 RM_opc_mem(secondary, dst), Con8or32(src));
9215 ins_pipe(ialu_mem_imm);
9216 %}
9217
9218 // Xor Instructions
9219 // Xor Register with Register
9220 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9221 %{
9222 match(Set dst (XorI dst src));
9223 effect(KILL cr);
9224
9225 format %{ "xorl $dst, $src\t# int" %}
9226 opcode(0x33);
9227 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9228 ins_pipe(ialu_reg_reg);
9229 %}
9230
9231 // Xor Register with Immediate -1
9232 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9233 match(Set dst (XorI dst imm));
9234
9235 format %{ "not $dst" %}
9236 ins_encode %{
9237 __ notl($dst$$Register);
9238 %}
9239 ins_pipe(ialu_reg);
9240 %}
9241
9242 // Xor Register with Immediate
9243 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9244 %{
9245 match(Set dst (XorI dst src));
9246 effect(KILL cr);
9247
9248 format %{ "xorl $dst, $src\t# int" %}
9249 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9250 ins_encode(OpcSErm(dst, src), Con8or32(src));
9251 ins_pipe(ialu_reg);
9252 %}
9253
9254 // Xor Register with Memory
9255 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9256 %{
9257 match(Set dst (XorI dst (LoadI src)));
9258 effect(KILL cr);
9259
9260 ins_cost(125);
9261 format %{ "xorl $dst, $src\t# int" %}
9262 opcode(0x33);
9263 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9264 ins_pipe(ialu_reg_mem);
9265 %}
9266
9267 // Xor Memory with Register
9268 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9269 %{
9270 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9271 effect(KILL cr);
9272
9273 ins_cost(150);
9274 format %{ "xorl $dst, $src\t# int" %}
9275 opcode(0x31); /* Opcode 31 /r */
9276 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9277 ins_pipe(ialu_mem_reg);
9278 %}
9279
9280 // Xor Memory with Immediate
9281 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9282 %{
9283 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9284 effect(KILL cr);
9285
9286 ins_cost(125);
9287 format %{ "xorl $dst, $src\t# int" %}
9288 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9289 ins_encode(REX_mem(dst), OpcSE(src),
9290 RM_opc_mem(secondary, dst), Con8or32(src));
9291 ins_pipe(ialu_mem_imm);
9292 %}
9293
9294
9295 // Long Logical Instructions
9296
9297 // And Instructions
9298 // And Register with Register
9299 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9300 %{
9301 match(Set dst (AndL dst src));
9302 effect(KILL cr);
9303
9304 format %{ "andq $dst, $src\t# long" %}
9305 opcode(0x23);
9306 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9307 ins_pipe(ialu_reg_reg);
9308 %}
9309
9310 // And Register with Immediate 255
9311 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9312 %{
9313 match(Set dst (AndL dst src));
9314
9315 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9316 opcode(0x0F, 0xB6);
9317 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9318 ins_pipe(ialu_reg);
9319 %}
9320
9321 // And Register with Immediate 65535
9322 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9323 %{
9324 match(Set dst (AndL dst src));
9325
9326 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9327 opcode(0x0F, 0xB7);
9328 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9329 ins_pipe(ialu_reg);
9330 %}
9331
9332 // And Register with Immediate
9333 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9334 %{
9335 match(Set dst (AndL dst src));
9336 effect(KILL cr);
9337
9338 format %{ "andq $dst, $src\t# long" %}
9339 opcode(0x81, 0x04); /* Opcode 81 /4 */
9340 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9341 ins_pipe(ialu_reg);
9342 %}
9343
9344 // And Register with Memory
9345 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9346 %{
9347 match(Set dst (AndL dst (LoadL src)));
9348 effect(KILL cr);
9349
9350 ins_cost(125);
9351 format %{ "andq $dst, $src\t# long" %}
9352 opcode(0x23);
9353 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9354 ins_pipe(ialu_reg_mem);
9355 %}
9356
9357 // And Memory with Register
9358 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9359 %{
9360 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9361 effect(KILL cr);
9362
9363 ins_cost(150);
9364 format %{ "andq $dst, $src\t# long" %}
9365 opcode(0x21); /* Opcode 21 /r */
9366 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9367 ins_pipe(ialu_mem_reg);
9368 %}
9369
9370 // And Memory with Immediate
9371 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9372 %{
9373 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9374 effect(KILL cr);
9375
9376 ins_cost(125);
9377 format %{ "andq $dst, $src\t# long" %}
9378 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9379 ins_encode(REX_mem_wide(dst), OpcSE(src),
9380 RM_opc_mem(secondary, dst), Con8or32(src));
9381 ins_pipe(ialu_mem_imm);
9382 %}
9383
9384 // BMI1 instructions
9385 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9386 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9387 predicate(UseBMI1Instructions);
9388 effect(KILL cr);
9389
9390 ins_cost(125);
9391 format %{ "andnq $dst, $src1, $src2" %}
9392
9393 ins_encode %{
9394 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9395 %}
9396 ins_pipe(ialu_reg_mem);
9397 %}
9398
9399 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9400 match(Set dst (AndL (XorL src1 minus_1) src2));
9401 predicate(UseBMI1Instructions);
9402 effect(KILL cr);
9403
9404 format %{ "andnq $dst, $src1, $src2" %}
9405
9406 ins_encode %{
9407 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9408 %}
9409 ins_pipe(ialu_reg_mem);
9410 %}
9411
9412 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9413 match(Set dst (AndL (SubL imm_zero src) src));
9414 predicate(UseBMI1Instructions);
9415 effect(KILL cr);
9416
9417 format %{ "blsiq $dst, $src" %}
9418
9419 ins_encode %{
9420 __ blsiq($dst$$Register, $src$$Register);
9421 %}
9422 ins_pipe(ialu_reg);
9423 %}
9424
9425 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9426 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9427 predicate(UseBMI1Instructions);
9428 effect(KILL cr);
9429
9430 ins_cost(125);
9431 format %{ "blsiq $dst, $src" %}
9432
9433 ins_encode %{
9434 __ blsiq($dst$$Register, $src$$Address);
9435 %}
9436 ins_pipe(ialu_reg_mem);
9437 %}
9438
9439 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9440 %{
9441 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9442 predicate(UseBMI1Instructions);
9443 effect(KILL cr);
9444
9445 ins_cost(125);
9446 format %{ "blsmskq $dst, $src" %}
9447
9448 ins_encode %{
9449 __ blsmskq($dst$$Register, $src$$Address);
9450 %}
9451 ins_pipe(ialu_reg_mem);
9452 %}
9453
9454 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9455 %{
9456 match(Set dst (XorL (AddL src minus_1) src));
9457 predicate(UseBMI1Instructions);
9458 effect(KILL cr);
9459
9460 format %{ "blsmskq $dst, $src" %}
9461
9462 ins_encode %{
9463 __ blsmskq($dst$$Register, $src$$Register);
9464 %}
9465
9466 ins_pipe(ialu_reg);
9467 %}
9468
9469 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9470 %{
9471 match(Set dst (AndL (AddL src minus_1) src) );
9472 predicate(UseBMI1Instructions);
9473 effect(KILL cr);
9474
9475 format %{ "blsrq $dst, $src" %}
9476
9477 ins_encode %{
9478 __ blsrq($dst$$Register, $src$$Register);
9479 %}
9480
9481 ins_pipe(ialu_reg);
9482 %}
9483
9484 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9485 %{
9486 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9487 predicate(UseBMI1Instructions);
9488 effect(KILL cr);
9489
9490 ins_cost(125);
9491 format %{ "blsrq $dst, $src" %}
9492
9493 ins_encode %{
9494 __ blsrq($dst$$Register, $src$$Address);
9495 %}
9496
9497 ins_pipe(ialu_reg);
9498 %}
9499
9500 // Or Instructions
9501 // Or Register with Register
9502 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9503 %{
9504 match(Set dst (OrL dst src));
9505 effect(KILL cr);
9506
9507 format %{ "orq $dst, $src\t# long" %}
9508 opcode(0x0B);
9509 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9510 ins_pipe(ialu_reg_reg);
9511 %}
9512
9513 // Use any_RegP to match R15 (TLS register) without spilling.
9514 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9515 match(Set dst (OrL dst (CastP2X src)));
9516 effect(KILL cr);
9517
9518 format %{ "orq $dst, $src\t# long" %}
9519 opcode(0x0B);
9520 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9521 ins_pipe(ialu_reg_reg);
9522 %}
9523
9524
9525 // Or Register with Immediate
9526 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9527 %{
9528 match(Set dst (OrL dst src));
9529 effect(KILL cr);
9530
9531 format %{ "orq $dst, $src\t# long" %}
9532 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9533 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9534 ins_pipe(ialu_reg);
9535 %}
9536
9537 // Or Register with Memory
9538 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9539 %{
9540 match(Set dst (OrL dst (LoadL src)));
9541 effect(KILL cr);
9542
9543 ins_cost(125);
9544 format %{ "orq $dst, $src\t# long" %}
9545 opcode(0x0B);
9546 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9547 ins_pipe(ialu_reg_mem);
9548 %}
9549
9550 // Or Memory with Register
9551 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9552 %{
9553 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9554 effect(KILL cr);
9555
9556 ins_cost(150);
9557 format %{ "orq $dst, $src\t# long" %}
9558 opcode(0x09); /* Opcode 09 /r */
9559 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9560 ins_pipe(ialu_mem_reg);
9561 %}
9562
9563 // Or Memory with Immediate
9564 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9565 %{
9566 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9567 effect(KILL cr);
9568
9569 ins_cost(125);
9570 format %{ "orq $dst, $src\t# long" %}
9571 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9572 ins_encode(REX_mem_wide(dst), OpcSE(src),
9573 RM_opc_mem(secondary, dst), Con8or32(src));
9574 ins_pipe(ialu_mem_imm);
9575 %}
9576
9577 // Xor Instructions
9578 // Xor Register with Register
9579 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9580 %{
9581 match(Set dst (XorL dst src));
9582 effect(KILL cr);
9583
9584 format %{ "xorq $dst, $src\t# long" %}
9585 opcode(0x33);
9586 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9587 ins_pipe(ialu_reg_reg);
9588 %}
9589
9590 // Xor Register with Immediate -1
9591 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9592 match(Set dst (XorL dst imm));
9593
9594 format %{ "notq $dst" %}
9595 ins_encode %{
9596 __ notq($dst$$Register);
9597 %}
9598 ins_pipe(ialu_reg);
9599 %}
9600
9601 // Xor Register with Immediate
9602 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9603 %{
9604 match(Set dst (XorL dst src));
9605 effect(KILL cr);
9606
9607 format %{ "xorq $dst, $src\t# long" %}
9608 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9609 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9610 ins_pipe(ialu_reg);
9611 %}
9612
9613 // Xor Register with Memory
9614 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9615 %{
9616 match(Set dst (XorL dst (LoadL src)));
9617 effect(KILL cr);
9618
9619 ins_cost(125);
9620 format %{ "xorq $dst, $src\t# long" %}
9621 opcode(0x33);
9622 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9623 ins_pipe(ialu_reg_mem);
9624 %}
9625
9626 // Xor Memory with Register
9627 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9628 %{
9629 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9630 effect(KILL cr);
9631
9632 ins_cost(150);
9633 format %{ "xorq $dst, $src\t# long" %}
9634 opcode(0x31); /* Opcode 31 /r */
9635 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9636 ins_pipe(ialu_mem_reg);
9637 %}
9638
9639 // Xor Memory with Immediate
9640 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9641 %{
9642 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9643 effect(KILL cr);
9644
9645 ins_cost(125);
9646 format %{ "xorq $dst, $src\t# long" %}
9647 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9648 ins_encode(REX_mem_wide(dst), OpcSE(src),
9649 RM_opc_mem(secondary, dst), Con8or32(src));
9650 ins_pipe(ialu_mem_imm);
9651 %}
9652
9653 // Convert Int to Boolean
9654 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9655 %{
9656 match(Set dst (Conv2B src));
9657 effect(KILL cr);
9658
9659 format %{ "testl $src, $src\t# ci2b\n\t"
9660 "setnz $dst\n\t"
9661 "movzbl $dst, $dst" %}
9662 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9663 setNZ_reg(dst),
9664 REX_reg_breg(dst, dst), // movzbl
9665 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9666 ins_pipe(pipe_slow); // XXX
9667 %}
9668
9669 // Convert Pointer to Boolean
9670 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9671 %{
9672 match(Set dst (Conv2B src));
9673 effect(KILL cr);
9674
9675 format %{ "testq $src, $src\t# cp2b\n\t"
9676 "setnz $dst\n\t"
9677 "movzbl $dst, $dst" %}
9678 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9679 setNZ_reg(dst),
9680 REX_reg_breg(dst, dst), // movzbl
9681 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9682 ins_pipe(pipe_slow); // XXX
9683 %}
9684
9685 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9686 %{
9687 match(Set dst (CmpLTMask p q));
9688 effect(KILL cr);
9689
9690 ins_cost(400);
9691 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9692 "setlt $dst\n\t"
9693 "movzbl $dst, $dst\n\t"
9694 "negl $dst" %}
9695 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9696 setLT_reg(dst),
9697 REX_reg_breg(dst, dst), // movzbl
9698 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9699 neg_reg(dst));
9700 ins_pipe(pipe_slow);
9701 %}
9702
9703 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9704 %{
9705 match(Set dst (CmpLTMask dst zero));
9706 effect(KILL cr);
9707
9708 ins_cost(100);
9709 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9710 ins_encode %{
9711 __ sarl($dst$$Register, 31);
9712 %}
9713 ins_pipe(ialu_reg);
9714 %}
9715
9716 /* Better to save a register than avoid a branch */
9717 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9718 %{
9719 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9720 effect(KILL cr);
9721 ins_cost(300);
9722 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9723 "jge done\n\t"
9724 "addl $p,$y\n"
9725 "done: " %}
9726 ins_encode %{
9727 Register Rp = $p$$Register;
9728 Register Rq = $q$$Register;
9729 Register Ry = $y$$Register;
9730 Label done;
9731 __ subl(Rp, Rq);
9732 __ jccb(Assembler::greaterEqual, done);
9733 __ addl(Rp, Ry);
9734 __ bind(done);
9735 %}
9736 ins_pipe(pipe_cmplt);
9737 %}
9738
9739 /* Better to save a register than avoid a branch */
9740 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9741 %{
9742 match(Set y (AndI (CmpLTMask p q) y));
9743 effect(KILL cr);
9744
9745 ins_cost(300);
9746
9747 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9748 "jlt done\n\t"
9749 "xorl $y, $y\n"
9750 "done: " %}
9751 ins_encode %{
9752 Register Rp = $p$$Register;
9753 Register Rq = $q$$Register;
9754 Register Ry = $y$$Register;
9755 Label done;
9756 __ cmpl(Rp, Rq);
9757 __ jccb(Assembler::less, done);
9758 __ xorl(Ry, Ry);
9759 __ bind(done);
9760 %}
9761 ins_pipe(pipe_cmplt);
9762 %}
9763
9764
9765 //---------- FP Instructions------------------------------------------------
9766
9767 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9768 %{
9769 match(Set cr (CmpF src1 src2));
9770
9771 ins_cost(145);
9772 format %{ "ucomiss $src1, $src2\n\t"
9773 "jnp,s exit\n\t"
9774 "pushfq\t# saw NaN, set CF\n\t"
9775 "andq [rsp], #0xffffff2b\n\t"
9776 "popfq\n"
9777 "exit:" %}
9778 ins_encode %{
9779 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9780 emit_cmpfp_fixup(_masm);
9781 %}
9782 ins_pipe(pipe_slow);
9783 %}
9784
9785 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9786 match(Set cr (CmpF src1 src2));
9787
9788 ins_cost(100);
9789 format %{ "ucomiss $src1, $src2" %}
9790 ins_encode %{
9791 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9792 %}
9793 ins_pipe(pipe_slow);
9794 %}
9795
9796 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9797 %{
9798 match(Set cr (CmpF src1 (LoadF src2)));
9799
9800 ins_cost(145);
9801 format %{ "ucomiss $src1, $src2\n\t"
9802 "jnp,s exit\n\t"
9803 "pushfq\t# saw NaN, set CF\n\t"
9804 "andq [rsp], #0xffffff2b\n\t"
9805 "popfq\n"
9806 "exit:" %}
9807 ins_encode %{
9808 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9809 emit_cmpfp_fixup(_masm);
9810 %}
9811 ins_pipe(pipe_slow);
9812 %}
9813
9814 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9815 match(Set cr (CmpF src1 (LoadF src2)));
9816
9817 ins_cost(100);
9818 format %{ "ucomiss $src1, $src2" %}
9819 ins_encode %{
9820 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9821 %}
9822 ins_pipe(pipe_slow);
9823 %}
9824
9825 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9826 match(Set cr (CmpF src con));
9827
9828 ins_cost(145);
9829 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9830 "jnp,s exit\n\t"
9831 "pushfq\t# saw NaN, set CF\n\t"
9832 "andq [rsp], #0xffffff2b\n\t"
9833 "popfq\n"
9834 "exit:" %}
9835 ins_encode %{
9836 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9837 emit_cmpfp_fixup(_masm);
9838 %}
9839 ins_pipe(pipe_slow);
9840 %}
9841
9842 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9843 match(Set cr (CmpF src con));
9844 ins_cost(100);
9845 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9846 ins_encode %{
9847 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9848 %}
9849 ins_pipe(pipe_slow);
9850 %}
9851
9852 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9853 %{
9854 match(Set cr (CmpD src1 src2));
9855
9856 ins_cost(145);
9857 format %{ "ucomisd $src1, $src2\n\t"
9858 "jnp,s exit\n\t"
9859 "pushfq\t# saw NaN, set CF\n\t"
9860 "andq [rsp], #0xffffff2b\n\t"
9861 "popfq\n"
9862 "exit:" %}
9863 ins_encode %{
9864 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9865 emit_cmpfp_fixup(_masm);
9866 %}
9867 ins_pipe(pipe_slow);
9868 %}
9869
9870 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9871 match(Set cr (CmpD src1 src2));
9872
9873 ins_cost(100);
9874 format %{ "ucomisd $src1, $src2 test" %}
9875 ins_encode %{
9876 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9877 %}
9878 ins_pipe(pipe_slow);
9879 %}
9880
9881 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9882 %{
9883 match(Set cr (CmpD src1 (LoadD src2)));
9884
9885 ins_cost(145);
9886 format %{ "ucomisd $src1, $src2\n\t"
9887 "jnp,s exit\n\t"
9888 "pushfq\t# saw NaN, set CF\n\t"
9889 "andq [rsp], #0xffffff2b\n\t"
9890 "popfq\n"
9891 "exit:" %}
9892 ins_encode %{
9893 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9894 emit_cmpfp_fixup(_masm);
9895 %}
9896 ins_pipe(pipe_slow);
9897 %}
9898
9899 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9900 match(Set cr (CmpD src1 (LoadD src2)));
9901
9902 ins_cost(100);
9903 format %{ "ucomisd $src1, $src2" %}
9904 ins_encode %{
9905 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9906 %}
9907 ins_pipe(pipe_slow);
9908 %}
9909
9910 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9911 match(Set cr (CmpD src con));
9912
9913 ins_cost(145);
9914 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9915 "jnp,s exit\n\t"
9916 "pushfq\t# saw NaN, set CF\n\t"
9917 "andq [rsp], #0xffffff2b\n\t"
9918 "popfq\n"
9919 "exit:" %}
9920 ins_encode %{
9921 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9922 emit_cmpfp_fixup(_masm);
9923 %}
9924 ins_pipe(pipe_slow);
9925 %}
9926
9927 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9928 match(Set cr (CmpD src con));
9929 ins_cost(100);
9930 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9931 ins_encode %{
9932 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9933 %}
9934 ins_pipe(pipe_slow);
9935 %}
9936
9937 // Compare into -1,0,1
9938 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9939 %{
9940 match(Set dst (CmpF3 src1 src2));
9941 effect(KILL cr);
9942
9943 ins_cost(275);
9944 format %{ "ucomiss $src1, $src2\n\t"
9945 "movl $dst, #-1\n\t"
9946 "jp,s done\n\t"
9947 "jb,s done\n\t"
9948 "setne $dst\n\t"
9949 "movzbl $dst, $dst\n"
9950 "done:" %}
9951 ins_encode %{
9952 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9953 emit_cmpfp3(_masm, $dst$$Register);
9954 %}
9955 ins_pipe(pipe_slow);
9956 %}
9957
9958 // Compare into -1,0,1
9959 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9960 %{
9961 match(Set dst (CmpF3 src1 (LoadF src2)));
9962 effect(KILL cr);
9963
9964 ins_cost(275);
9965 format %{ "ucomiss $src1, $src2\n\t"
9966 "movl $dst, #-1\n\t"
9967 "jp,s done\n\t"
9968 "jb,s done\n\t"
9969 "setne $dst\n\t"
9970 "movzbl $dst, $dst\n"
9971 "done:" %}
9972 ins_encode %{
9973 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9974 emit_cmpfp3(_masm, $dst$$Register);
9975 %}
9976 ins_pipe(pipe_slow);
9977 %}
9978
9979 // Compare into -1,0,1
9980 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9981 match(Set dst (CmpF3 src con));
9982 effect(KILL cr);
9983
9984 ins_cost(275);
9985 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9986 "movl $dst, #-1\n\t"
9987 "jp,s done\n\t"
9988 "jb,s done\n\t"
9989 "setne $dst\n\t"
9990 "movzbl $dst, $dst\n"
9991 "done:" %}
9992 ins_encode %{
9993 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9994 emit_cmpfp3(_masm, $dst$$Register);
9995 %}
9996 ins_pipe(pipe_slow);
9997 %}
9998
9999 // Compare into -1,0,1
10000 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10001 %{
10002 match(Set dst (CmpD3 src1 src2));
10003 effect(KILL cr);
10004
10005 ins_cost(275);
10006 format %{ "ucomisd $src1, $src2\n\t"
10007 "movl $dst, #-1\n\t"
10008 "jp,s done\n\t"
10009 "jb,s done\n\t"
10010 "setne $dst\n\t"
10011 "movzbl $dst, $dst\n"
10012 "done:" %}
10013 ins_encode %{
10014 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10015 emit_cmpfp3(_masm, $dst$$Register);
10016 %}
10017 ins_pipe(pipe_slow);
10018 %}
10019
10020 // Compare into -1,0,1
10021 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10022 %{
10023 match(Set dst (CmpD3 src1 (LoadD src2)));
10024 effect(KILL cr);
10025
10026 ins_cost(275);
10027 format %{ "ucomisd $src1, $src2\n\t"
10028 "movl $dst, #-1\n\t"
10029 "jp,s done\n\t"
10030 "jb,s done\n\t"
10031 "setne $dst\n\t"
10032 "movzbl $dst, $dst\n"
10033 "done:" %}
10034 ins_encode %{
10035 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10036 emit_cmpfp3(_masm, $dst$$Register);
10037 %}
10038 ins_pipe(pipe_slow);
10039 %}
10040
10041 // Compare into -1,0,1
10042 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10043 match(Set dst (CmpD3 src con));
10044 effect(KILL cr);
10045
10046 ins_cost(275);
10047 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10048 "movl $dst, #-1\n\t"
10049 "jp,s done\n\t"
10050 "jb,s done\n\t"
10051 "setne $dst\n\t"
10052 "movzbl $dst, $dst\n"
10053 "done:" %}
10054 ins_encode %{
10055 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10056 emit_cmpfp3(_masm, $dst$$Register);
10057 %}
10058 ins_pipe(pipe_slow);
10059 %}
10060
10061 //----------Arithmetic Conversion Instructions---------------------------------
10062
10063 instruct roundFloat_nop(regF dst)
10064 %{
10065 match(Set dst (RoundFloat dst));
10066
10067 ins_cost(0);
10068 ins_encode();
10069 ins_pipe(empty);
10070 %}
10071
10072 instruct roundDouble_nop(regD dst)
10073 %{
10074 match(Set dst (RoundDouble dst));
10075
10076 ins_cost(0);
10077 ins_encode();
10078 ins_pipe(empty);
10079 %}
10080
10081 instruct convF2D_reg_reg(regD dst, regF src)
10082 %{
10083 match(Set dst (ConvF2D src));
10084
10085 format %{ "cvtss2sd $dst, $src" %}
10086 ins_encode %{
10087 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10088 %}
10089 ins_pipe(pipe_slow); // XXX
10090 %}
10091
10092 instruct convF2D_reg_mem(regD dst, memory src)
10093 %{
10094 match(Set dst (ConvF2D (LoadF src)));
10095
10096 format %{ "cvtss2sd $dst, $src" %}
10097 ins_encode %{
10098 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10099 %}
10100 ins_pipe(pipe_slow); // XXX
10101 %}
10102
10103 instruct convD2F_reg_reg(regF dst, regD src)
10104 %{
10105 match(Set dst (ConvD2F src));
10106
10107 format %{ "cvtsd2ss $dst, $src" %}
10108 ins_encode %{
10109 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10110 %}
10111 ins_pipe(pipe_slow); // XXX
10112 %}
10113
10114 instruct convD2F_reg_mem(regF dst, memory src)
10115 %{
10116 match(Set dst (ConvD2F (LoadD src)));
10117
10118 format %{ "cvtsd2ss $dst, $src" %}
10119 ins_encode %{
10120 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10121 %}
10122 ins_pipe(pipe_slow); // XXX
10123 %}
10124
10125 // XXX do mem variants
10126 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10127 %{
10128 match(Set dst (ConvF2I src));
10129 effect(KILL cr);
10130
10131 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10132 "cmpl $dst, #0x80000000\n\t"
10133 "jne,s done\n\t"
10134 "subq rsp, #8\n\t"
10135 "movss [rsp], $src\n\t"
10136 "call f2i_fixup\n\t"
10137 "popq $dst\n"
10138 "done: "%}
10139 ins_encode %{
10140 Label done;
10141 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10142 __ cmpl($dst$$Register, 0x80000000);
10143 __ jccb(Assembler::notEqual, done);
10144 __ subptr(rsp, 8);
10145 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10146 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10147 __ pop($dst$$Register);
10148 __ bind(done);
10149 %}
10150 ins_pipe(pipe_slow);
10151 %}
10152
10153 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10154 %{
10155 match(Set dst (ConvF2L src));
10156 effect(KILL cr);
10157
10158 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10159 "cmpq $dst, [0x8000000000000000]\n\t"
10160 "jne,s done\n\t"
10161 "subq rsp, #8\n\t"
10162 "movss [rsp], $src\n\t"
10163 "call f2l_fixup\n\t"
10164 "popq $dst\n"
10165 "done: "%}
10166 ins_encode %{
10167 Label done;
10168 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10169 __ cmp64($dst$$Register,
10170 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10171 __ jccb(Assembler::notEqual, done);
10172 __ subptr(rsp, 8);
10173 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10174 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10175 __ pop($dst$$Register);
10176 __ bind(done);
10177 %}
10178 ins_pipe(pipe_slow);
10179 %}
10180
10181 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10182 %{
10183 match(Set dst (ConvD2I src));
10184 effect(KILL cr);
10185
10186 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10187 "cmpl $dst, #0x80000000\n\t"
10188 "jne,s done\n\t"
10189 "subq rsp, #8\n\t"
10190 "movsd [rsp], $src\n\t"
10191 "call d2i_fixup\n\t"
10192 "popq $dst\n"
10193 "done: "%}
10194 ins_encode %{
10195 Label done;
10196 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10197 __ cmpl($dst$$Register, 0x80000000);
10198 __ jccb(Assembler::notEqual, done);
10199 __ subptr(rsp, 8);
10200 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10201 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10202 __ pop($dst$$Register);
10203 __ bind(done);
10204 %}
10205 ins_pipe(pipe_slow);
10206 %}
10207
10208 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10209 %{
10210 match(Set dst (ConvD2L src));
10211 effect(KILL cr);
10212
10213 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10214 "cmpq $dst, [0x8000000000000000]\n\t"
10215 "jne,s done\n\t"
10216 "subq rsp, #8\n\t"
10217 "movsd [rsp], $src\n\t"
10218 "call d2l_fixup\n\t"
10219 "popq $dst\n"
10220 "done: "%}
10221 ins_encode %{
10222 Label done;
10223 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10224 __ cmp64($dst$$Register,
10225 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10226 __ jccb(Assembler::notEqual, done);
10227 __ subptr(rsp, 8);
10228 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10229 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10230 __ pop($dst$$Register);
10231 __ bind(done);
10232 %}
10233 ins_pipe(pipe_slow);
10234 %}
10235
10236 instruct convI2F_reg_reg(regF dst, rRegI src)
10237 %{
10238 predicate(!UseXmmI2F);
10239 match(Set dst (ConvI2F src));
10240
10241 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10242 ins_encode %{
10243 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10244 %}
10245 ins_pipe(pipe_slow); // XXX
10246 %}
10247
10248 instruct convI2F_reg_mem(regF dst, memory src)
10249 %{
10250 match(Set dst (ConvI2F (LoadI src)));
10251
10252 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10253 ins_encode %{
10254 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10255 %}
10256 ins_pipe(pipe_slow); // XXX
10257 %}
10258
10259 instruct convI2D_reg_reg(regD dst, rRegI src)
10260 %{
10261 predicate(!UseXmmI2D);
10262 match(Set dst (ConvI2D src));
10263
10264 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10265 ins_encode %{
10266 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10267 %}
10268 ins_pipe(pipe_slow); // XXX
10269 %}
10270
10271 instruct convI2D_reg_mem(regD dst, memory src)
10272 %{
10273 match(Set dst (ConvI2D (LoadI src)));
10274
10275 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10276 ins_encode %{
10277 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10278 %}
10279 ins_pipe(pipe_slow); // XXX
10280 %}
10281
10282 instruct convXI2F_reg(regF dst, rRegI src)
10283 %{
10284 predicate(UseXmmI2F);
10285 match(Set dst (ConvI2F src));
10286
10287 format %{ "movdl $dst, $src\n\t"
10288 "cvtdq2psl $dst, $dst\t# i2f" %}
10289 ins_encode %{
10290 __ movdl($dst$$XMMRegister, $src$$Register);
10291 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10292 %}
10293 ins_pipe(pipe_slow); // XXX
10294 %}
10295
10296 instruct convXI2D_reg(regD dst, rRegI src)
10297 %{
10298 predicate(UseXmmI2D);
10299 match(Set dst (ConvI2D src));
10300
10301 format %{ "movdl $dst, $src\n\t"
10302 "cvtdq2pdl $dst, $dst\t# i2d" %}
10303 ins_encode %{
10304 __ movdl($dst$$XMMRegister, $src$$Register);
10305 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10306 %}
10307 ins_pipe(pipe_slow); // XXX
10308 %}
10309
10310 instruct convL2F_reg_reg(regF dst, rRegL src)
10311 %{
10312 match(Set dst (ConvL2F src));
10313
10314 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10315 ins_encode %{
10316 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10317 %}
10318 ins_pipe(pipe_slow); // XXX
10319 %}
10320
10321 instruct convL2F_reg_mem(regF dst, memory src)
10322 %{
10323 match(Set dst (ConvL2F (LoadL src)));
10324
10325 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10326 ins_encode %{
10327 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10328 %}
10329 ins_pipe(pipe_slow); // XXX
10330 %}
10331
10332 instruct convL2D_reg_reg(regD dst, rRegL src)
10333 %{
10334 match(Set dst (ConvL2D src));
10335
10336 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10337 ins_encode %{
10338 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10339 %}
10340 ins_pipe(pipe_slow); // XXX
10341 %}
10342
10343 instruct convL2D_reg_mem(regD dst, memory src)
10344 %{
10345 match(Set dst (ConvL2D (LoadL src)));
10346
10347 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10348 ins_encode %{
10349 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10350 %}
10351 ins_pipe(pipe_slow); // XXX
10352 %}
10353
10354 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10355 %{
10356 match(Set dst (ConvI2L src));
10357
10358 ins_cost(125);
10359 format %{ "movslq $dst, $src\t# i2l" %}
10360 ins_encode %{
10361 __ movslq($dst$$Register, $src$$Register);
10362 %}
10363 ins_pipe(ialu_reg_reg);
10364 %}
10365
10366 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10367 // %{
10368 // match(Set dst (ConvI2L src));
10369 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10370 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10371 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10372 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10373 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10374 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10375
10376 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10377 // ins_encode(enc_copy(dst, src));
10378 // // opcode(0x63); // needs REX.W
10379 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10380 // ins_pipe(ialu_reg_reg);
10381 // %}
10382
10383 // Zero-extend convert int to long
10384 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10385 %{
10386 match(Set dst (AndL (ConvI2L src) mask));
10387
10388 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10389 ins_encode %{
10390 if ($dst$$reg != $src$$reg) {
10391 __ movl($dst$$Register, $src$$Register);
10392 }
10393 %}
10394 ins_pipe(ialu_reg_reg);
10395 %}
10396
10397 // Zero-extend convert int to long
10398 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10399 %{
10400 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10401
10402 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10403 ins_encode %{
10404 __ movl($dst$$Register, $src$$Address);
10405 %}
10406 ins_pipe(ialu_reg_mem);
10407 %}
10408
10409 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10410 %{
10411 match(Set dst (AndL src mask));
10412
10413 format %{ "movl $dst, $src\t# zero-extend long" %}
10414 ins_encode %{
10415 __ movl($dst$$Register, $src$$Register);
10416 %}
10417 ins_pipe(ialu_reg_reg);
10418 %}
10419
10420 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10421 %{
10422 match(Set dst (ConvL2I src));
10423
10424 format %{ "movl $dst, $src\t# l2i" %}
10425 ins_encode %{
10426 __ movl($dst$$Register, $src$$Register);
10427 %}
10428 ins_pipe(ialu_reg_reg);
10429 %}
10430
10431
10432 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10433 match(Set dst (MoveF2I src));
10434 effect(DEF dst, USE src);
10435
10436 ins_cost(125);
10437 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10438 ins_encode %{
10439 __ movl($dst$$Register, Address(rsp, $src$$disp));
10440 %}
10441 ins_pipe(ialu_reg_mem);
10442 %}
10443
10444 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10445 match(Set dst (MoveI2F src));
10446 effect(DEF dst, USE src);
10447
10448 ins_cost(125);
10449 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10450 ins_encode %{
10451 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10452 %}
10453 ins_pipe(pipe_slow);
10454 %}
10455
10456 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10457 match(Set dst (MoveD2L src));
10458 effect(DEF dst, USE src);
10459
10460 ins_cost(125);
10461 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10462 ins_encode %{
10463 __ movq($dst$$Register, Address(rsp, $src$$disp));
10464 %}
10465 ins_pipe(ialu_reg_mem);
10466 %}
10467
10468 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10469 predicate(!UseXmmLoadAndClearUpper);
10470 match(Set dst (MoveL2D src));
10471 effect(DEF dst, USE src);
10472
10473 ins_cost(125);
10474 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10475 ins_encode %{
10476 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10477 %}
10478 ins_pipe(pipe_slow);
10479 %}
10480
10481 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10482 predicate(UseXmmLoadAndClearUpper);
10483 match(Set dst (MoveL2D src));
10484 effect(DEF dst, USE src);
10485
10486 ins_cost(125);
10487 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10488 ins_encode %{
10489 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10490 %}
10491 ins_pipe(pipe_slow);
10492 %}
10493
10494
10495 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10496 match(Set dst (MoveF2I src));
10497 effect(DEF dst, USE src);
10498
10499 ins_cost(95); // XXX
10500 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10501 ins_encode %{
10502 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10503 %}
10504 ins_pipe(pipe_slow);
10505 %}
10506
10507 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10508 match(Set dst (MoveI2F src));
10509 effect(DEF dst, USE src);
10510
10511 ins_cost(100);
10512 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10513 ins_encode %{
10514 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10515 %}
10516 ins_pipe( ialu_mem_reg );
10517 %}
10518
10519 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10520 match(Set dst (MoveD2L src));
10521 effect(DEF dst, USE src);
10522
10523 ins_cost(95); // XXX
10524 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10525 ins_encode %{
10526 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10527 %}
10528 ins_pipe(pipe_slow);
10529 %}
10530
10531 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10532 match(Set dst (MoveL2D src));
10533 effect(DEF dst, USE src);
10534
10535 ins_cost(100);
10536 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10537 ins_encode %{
10538 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10539 %}
10540 ins_pipe(ialu_mem_reg);
10541 %}
10542
10543 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10544 match(Set dst (MoveF2I src));
10545 effect(DEF dst, USE src);
10546 ins_cost(85);
10547 format %{ "movd $dst,$src\t# MoveF2I" %}
10548 ins_encode %{
10549 __ movdl($dst$$Register, $src$$XMMRegister);
10550 %}
10551 ins_pipe( pipe_slow );
10552 %}
10553
10554 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10555 match(Set dst (MoveD2L src));
10556 effect(DEF dst, USE src);
10557 ins_cost(85);
10558 format %{ "movd $dst,$src\t# MoveD2L" %}
10559 ins_encode %{
10560 __ movdq($dst$$Register, $src$$XMMRegister);
10561 %}
10562 ins_pipe( pipe_slow );
10563 %}
10564
10565 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10566 match(Set dst (MoveI2F src));
10567 effect(DEF dst, USE src);
10568 ins_cost(100);
10569 format %{ "movd $dst,$src\t# MoveI2F" %}
10570 ins_encode %{
10571 __ movdl($dst$$XMMRegister, $src$$Register);
10572 %}
10573 ins_pipe( pipe_slow );
10574 %}
10575
10576 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10577 match(Set dst (MoveL2D src));
10578 effect(DEF dst, USE src);
10579 ins_cost(100);
10580 format %{ "movd $dst,$src\t# MoveL2D" %}
10581 ins_encode %{
10582 __ movdq($dst$$XMMRegister, $src$$Register);
10583 %}
10584 ins_pipe( pipe_slow );
10585 %}
10586
10587
10588 // =======================================================================
10589 // fast clearing of an array
10590 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10591 rFlagsReg cr)
10592 %{
10593 predicate(!((ClearArrayNode*)n)->is_large());
10594 match(Set dummy (ClearArray cnt base));
10595 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10596
10597 format %{ $$template
10598 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10599 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10600 $$emit$$"jg LARGE\n\t"
10601 $$emit$$"dec rcx\n\t"
10602 $$emit$$"js DONE\t# Zero length\n\t"
10603 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10604 $$emit$$"dec rcx\n\t"
10605 $$emit$$"jge LOOP\n\t"
10606 $$emit$$"jmp DONE\n\t"
10607 $$emit$$"# LARGE:\n\t"
10608 if (UseFastStosb) {
10609 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10610 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10611 } else {
10612 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10613 }
10614 $$emit$$"# DONE"
10615 %}
10616 ins_encode %{
10617 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, false);
10618 %}
10619 ins_pipe(pipe_slow);
10620 %}
10621
10622 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10623 rFlagsReg cr)
10624 %{
10625 predicate(((ClearArrayNode*)n)->is_large());
10626 match(Set dummy (ClearArray cnt base));
10627 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10628
10629 format %{ $$template
10630 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10631 if (UseFastStosb) {
10632 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10633 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10634 } else {
10635 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10636 }
10637 %}
10638 ins_encode %{
10639 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, true);
10640 %}
10641 ins_pipe(pipe_slow);
10642 %}
10643
10644 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10645 rax_RegI result, regD tmp1, rFlagsReg cr)
10646 %{
10647 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10648 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10649 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10650
10651 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10652 ins_encode %{
10653 __ string_compare($str1$$Register, $str2$$Register,
10654 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10655 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10656 %}
10657 ins_pipe( pipe_slow );
10658 %}
10659
10660 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10661 rax_RegI result, regD tmp1, rFlagsReg cr)
10662 %{
10663 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10664 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10665 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10666
10667 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10668 ins_encode %{
10669 __ string_compare($str1$$Register, $str2$$Register,
10670 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10671 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10672 %}
10673 ins_pipe( pipe_slow );
10674 %}
10675
10676 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10677 rax_RegI result, regD tmp1, rFlagsReg cr)
10678 %{
10679 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10680 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10681 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10682
10683 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10684 ins_encode %{
10685 __ string_compare($str1$$Register, $str2$$Register,
10686 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10687 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10688 %}
10689 ins_pipe( pipe_slow );
10690 %}
10691
10692 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10693 rax_RegI result, regD tmp1, rFlagsReg cr)
10694 %{
10695 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10696 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10697 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10698
10699 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10700 ins_encode %{
10701 __ string_compare($str2$$Register, $str1$$Register,
10702 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10703 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10704 %}
10705 ins_pipe( pipe_slow );
10706 %}
10707
10708 // fast search of substring with known size.
10709 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10710 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10711 %{
10712 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10713 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10714 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10715
10716 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10717 ins_encode %{
10718 int icnt2 = (int)$int_cnt2$$constant;
10719 if (icnt2 >= 16) {
10720 // IndexOf for constant substrings with size >= 16 elements
10721 // which don't need to be loaded through stack.
10722 __ string_indexofC8($str1$$Register, $str2$$Register,
10723 $cnt1$$Register, $cnt2$$Register,
10724 icnt2, $result$$Register,
10725 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10726 } else {
10727 // Small strings are loaded through stack if they cross page boundary.
10728 __ string_indexof($str1$$Register, $str2$$Register,
10729 $cnt1$$Register, $cnt2$$Register,
10730 icnt2, $result$$Register,
10731 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10732 }
10733 %}
10734 ins_pipe( pipe_slow );
10735 %}
10736
10737 // fast search of substring with known size.
10738 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10739 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10740 %{
10741 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10742 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10743 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10744
10745 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10746 ins_encode %{
10747 int icnt2 = (int)$int_cnt2$$constant;
10748 if (icnt2 >= 8) {
10749 // IndexOf for constant substrings with size >= 8 elements
10750 // which don't need to be loaded through stack.
10751 __ string_indexofC8($str1$$Register, $str2$$Register,
10752 $cnt1$$Register, $cnt2$$Register,
10753 icnt2, $result$$Register,
10754 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10755 } else {
10756 // Small strings are loaded through stack if they cross page boundary.
10757 __ string_indexof($str1$$Register, $str2$$Register,
10758 $cnt1$$Register, $cnt2$$Register,
10759 icnt2, $result$$Register,
10760 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10761 }
10762 %}
10763 ins_pipe( pipe_slow );
10764 %}
10765
10766 // fast search of substring with known size.
10767 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10768 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10769 %{
10770 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10771 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10772 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10773
10774 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10775 ins_encode %{
10776 int icnt2 = (int)$int_cnt2$$constant;
10777 if (icnt2 >= 8) {
10778 // IndexOf for constant substrings with size >= 8 elements
10779 // which don't need to be loaded through stack.
10780 __ string_indexofC8($str1$$Register, $str2$$Register,
10781 $cnt1$$Register, $cnt2$$Register,
10782 icnt2, $result$$Register,
10783 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10784 } else {
10785 // Small strings are loaded through stack if they cross page boundary.
10786 __ string_indexof($str1$$Register, $str2$$Register,
10787 $cnt1$$Register, $cnt2$$Register,
10788 icnt2, $result$$Register,
10789 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10790 }
10791 %}
10792 ins_pipe( pipe_slow );
10793 %}
10794
10795 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10796 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10797 %{
10798 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10799 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10800 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10801
10802 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10803 ins_encode %{
10804 __ string_indexof($str1$$Register, $str2$$Register,
10805 $cnt1$$Register, $cnt2$$Register,
10806 (-1), $result$$Register,
10807 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10808 %}
10809 ins_pipe( pipe_slow );
10810 %}
10811
10812 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10813 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10814 %{
10815 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10816 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10817 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10818
10819 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10820 ins_encode %{
10821 __ string_indexof($str1$$Register, $str2$$Register,
10822 $cnt1$$Register, $cnt2$$Register,
10823 (-1), $result$$Register,
10824 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10825 %}
10826 ins_pipe( pipe_slow );
10827 %}
10828
10829 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10830 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10831 %{
10832 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10833 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10834 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10835
10836 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10837 ins_encode %{
10838 __ string_indexof($str1$$Register, $str2$$Register,
10839 $cnt1$$Register, $cnt2$$Register,
10840 (-1), $result$$Register,
10841 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10842 %}
10843 ins_pipe( pipe_slow );
10844 %}
10845
10846 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10847 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10848 %{
10849 predicate(UseSSE42Intrinsics);
10850 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10851 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10852 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10853 ins_encode %{
10854 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10855 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10856 %}
10857 ins_pipe( pipe_slow );
10858 %}
10859
10860 // fast string equals
10861 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10862 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10863 %{
10864 match(Set result (StrEquals (Binary str1 str2) cnt));
10865 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10866
10867 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10868 ins_encode %{
10869 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10870 $cnt$$Register, $result$$Register, $tmp3$$Register,
10871 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10872 %}
10873 ins_pipe( pipe_slow );
10874 %}
10875
10876 // fast array equals
10877 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10878 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10879 %{
10880 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10881 match(Set result (AryEq ary1 ary2));
10882 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10883
10884 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10885 ins_encode %{
10886 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10887 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10888 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10889 %}
10890 ins_pipe( pipe_slow );
10891 %}
10892
10893 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10894 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10895 %{
10896 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10897 match(Set result (AryEq ary1 ary2));
10898 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10899
10900 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10901 ins_encode %{
10902 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10903 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10904 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10905 %}
10906 ins_pipe( pipe_slow );
10907 %}
10908
10909 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10910 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10911 %{
10912 match(Set result (HasNegatives ary1 len));
10913 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10914
10915 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10916 ins_encode %{
10917 __ has_negatives($ary1$$Register, $len$$Register,
10918 $result$$Register, $tmp3$$Register,
10919 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10920 %}
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 // fast char[] to byte[] compression
10925 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10926 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10927 match(Set result (StrCompressedCopy src (Binary dst len)));
10928 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10929
10930 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10931 ins_encode %{
10932 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10933 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10934 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10935 %}
10936 ins_pipe( pipe_slow );
10937 %}
10938
10939 // fast byte[] to char[] inflation
10940 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10941 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10942 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10943 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10944
10945 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10946 ins_encode %{
10947 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10948 $tmp1$$XMMRegister, $tmp2$$Register);
10949 %}
10950 ins_pipe( pipe_slow );
10951 %}
10952
10953 // encode char[] to byte[] in ISO_8859_1
10954 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10955 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10956 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10957 match(Set result (EncodeISOArray src (Binary dst len)));
10958 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10959
10960 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10961 ins_encode %{
10962 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10963 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10964 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10965 %}
10966 ins_pipe( pipe_slow );
10967 %}
10968
10969 //----------Overflow Math Instructions-----------------------------------------
10970
10971 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10972 %{
10973 match(Set cr (OverflowAddI op1 op2));
10974 effect(DEF cr, USE_KILL op1, USE op2);
10975
10976 format %{ "addl $op1, $op2\t# overflow check int" %}
10977
10978 ins_encode %{
10979 __ addl($op1$$Register, $op2$$Register);
10980 %}
10981 ins_pipe(ialu_reg_reg);
10982 %}
10983
10984 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10985 %{
10986 match(Set cr (OverflowAddI op1 op2));
10987 effect(DEF cr, USE_KILL op1, USE op2);
10988
10989 format %{ "addl $op1, $op2\t# overflow check int" %}
10990
10991 ins_encode %{
10992 __ addl($op1$$Register, $op2$$constant);
10993 %}
10994 ins_pipe(ialu_reg_reg);
10995 %}
10996
10997 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10998 %{
10999 match(Set cr (OverflowAddL op1 op2));
11000 effect(DEF cr, USE_KILL op1, USE op2);
11001
11002 format %{ "addq $op1, $op2\t# overflow check long" %}
11003 ins_encode %{
11004 __ addq($op1$$Register, $op2$$Register);
11005 %}
11006 ins_pipe(ialu_reg_reg);
11007 %}
11008
11009 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11010 %{
11011 match(Set cr (OverflowAddL op1 op2));
11012 effect(DEF cr, USE_KILL op1, USE op2);
11013
11014 format %{ "addq $op1, $op2\t# overflow check long" %}
11015 ins_encode %{
11016 __ addq($op1$$Register, $op2$$constant);
11017 %}
11018 ins_pipe(ialu_reg_reg);
11019 %}
11020
11021 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11022 %{
11023 match(Set cr (OverflowSubI op1 op2));
11024
11025 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11026 ins_encode %{
11027 __ cmpl($op1$$Register, $op2$$Register);
11028 %}
11029 ins_pipe(ialu_reg_reg);
11030 %}
11031
11032 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11033 %{
11034 match(Set cr (OverflowSubI op1 op2));
11035
11036 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11037 ins_encode %{
11038 __ cmpl($op1$$Register, $op2$$constant);
11039 %}
11040 ins_pipe(ialu_reg_reg);
11041 %}
11042
11043 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11044 %{
11045 match(Set cr (OverflowSubL op1 op2));
11046
11047 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11048 ins_encode %{
11049 __ cmpq($op1$$Register, $op2$$Register);
11050 %}
11051 ins_pipe(ialu_reg_reg);
11052 %}
11053
11054 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11055 %{
11056 match(Set cr (OverflowSubL op1 op2));
11057
11058 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11059 ins_encode %{
11060 __ cmpq($op1$$Register, $op2$$constant);
11061 %}
11062 ins_pipe(ialu_reg_reg);
11063 %}
11064
11065 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11066 %{
11067 match(Set cr (OverflowSubI zero op2));
11068 effect(DEF cr, USE_KILL op2);
11069
11070 format %{ "negl $op2\t# overflow check int" %}
11071 ins_encode %{
11072 __ negl($op2$$Register);
11073 %}
11074 ins_pipe(ialu_reg_reg);
11075 %}
11076
11077 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11078 %{
11079 match(Set cr (OverflowSubL zero op2));
11080 effect(DEF cr, USE_KILL op2);
11081
11082 format %{ "negq $op2\t# overflow check long" %}
11083 ins_encode %{
11084 __ negq($op2$$Register);
11085 %}
11086 ins_pipe(ialu_reg_reg);
11087 %}
11088
11089 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11090 %{
11091 match(Set cr (OverflowMulI op1 op2));
11092 effect(DEF cr, USE_KILL op1, USE op2);
11093
11094 format %{ "imull $op1, $op2\t# overflow check int" %}
11095 ins_encode %{
11096 __ imull($op1$$Register, $op2$$Register);
11097 %}
11098 ins_pipe(ialu_reg_reg_alu0);
11099 %}
11100
11101 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11102 %{
11103 match(Set cr (OverflowMulI op1 op2));
11104 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11105
11106 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11107 ins_encode %{
11108 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11109 %}
11110 ins_pipe(ialu_reg_reg_alu0);
11111 %}
11112
11113 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11114 %{
11115 match(Set cr (OverflowMulL op1 op2));
11116 effect(DEF cr, USE_KILL op1, USE op2);
11117
11118 format %{ "imulq $op1, $op2\t# overflow check long" %}
11119 ins_encode %{
11120 __ imulq($op1$$Register, $op2$$Register);
11121 %}
11122 ins_pipe(ialu_reg_reg_alu0);
11123 %}
11124
11125 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11126 %{
11127 match(Set cr (OverflowMulL op1 op2));
11128 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11129
11130 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11131 ins_encode %{
11132 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11133 %}
11134 ins_pipe(ialu_reg_reg_alu0);
11135 %}
11136
11137
11138 //----------Control Flow Instructions------------------------------------------
11139 // Signed compare Instructions
11140
11141 // XXX more variants!!
11142 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11143 %{
11144 match(Set cr (CmpI op1 op2));
11145 effect(DEF cr, USE op1, USE op2);
11146
11147 format %{ "cmpl $op1, $op2" %}
11148 opcode(0x3B); /* Opcode 3B /r */
11149 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11150 ins_pipe(ialu_cr_reg_reg);
11151 %}
11152
11153 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11154 %{
11155 match(Set cr (CmpI op1 op2));
11156
11157 format %{ "cmpl $op1, $op2" %}
11158 opcode(0x81, 0x07); /* Opcode 81 /7 */
11159 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11160 ins_pipe(ialu_cr_reg_imm);
11161 %}
11162
11163 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11164 %{
11165 match(Set cr (CmpI op1 (LoadI op2)));
11166
11167 ins_cost(500); // XXX
11168 format %{ "cmpl $op1, $op2" %}
11169 opcode(0x3B); /* Opcode 3B /r */
11170 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11171 ins_pipe(ialu_cr_reg_mem);
11172 %}
11173
11174 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11175 %{
11176 match(Set cr (CmpI src zero));
11177
11178 format %{ "testl $src, $src" %}
11179 opcode(0x85);
11180 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11181 ins_pipe(ialu_cr_reg_imm);
11182 %}
11183
11184 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11185 %{
11186 match(Set cr (CmpI (AndI src con) zero));
11187
11188 format %{ "testl $src, $con" %}
11189 opcode(0xF7, 0x00);
11190 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11191 ins_pipe(ialu_cr_reg_imm);
11192 %}
11193
11194 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11195 %{
11196 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11197
11198 format %{ "testl $src, $mem" %}
11199 opcode(0x85);
11200 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11201 ins_pipe(ialu_cr_reg_mem);
11202 %}
11203
11204 // Unsigned compare Instructions; really, same as signed except they
11205 // produce an rFlagsRegU instead of rFlagsReg.
11206 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11207 %{
11208 match(Set cr (CmpU op1 op2));
11209
11210 format %{ "cmpl $op1, $op2\t# unsigned" %}
11211 opcode(0x3B); /* Opcode 3B /r */
11212 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11213 ins_pipe(ialu_cr_reg_reg);
11214 %}
11215
11216 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11217 %{
11218 match(Set cr (CmpU op1 op2));
11219
11220 format %{ "cmpl $op1, $op2\t# unsigned" %}
11221 opcode(0x81,0x07); /* Opcode 81 /7 */
11222 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11223 ins_pipe(ialu_cr_reg_imm);
11224 %}
11225
11226 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11227 %{
11228 match(Set cr (CmpU op1 (LoadI op2)));
11229
11230 ins_cost(500); // XXX
11231 format %{ "cmpl $op1, $op2\t# unsigned" %}
11232 opcode(0x3B); /* Opcode 3B /r */
11233 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11234 ins_pipe(ialu_cr_reg_mem);
11235 %}
11236
11237 // // // Cisc-spilled version of cmpU_rReg
11238 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11239 // //%{
11240 // // match(Set cr (CmpU (LoadI op1) op2));
11241 // //
11242 // // format %{ "CMPu $op1,$op2" %}
11243 // // ins_cost(500);
11244 // // opcode(0x39); /* Opcode 39 /r */
11245 // // ins_encode( OpcP, reg_mem( op1, op2) );
11246 // //%}
11247
11248 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11249 %{
11250 match(Set cr (CmpU src zero));
11251
11252 format %{ "testl $src, $src\t# unsigned" %}
11253 opcode(0x85);
11254 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11255 ins_pipe(ialu_cr_reg_imm);
11256 %}
11257
11258 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11259 %{
11260 match(Set cr (CmpP op1 op2));
11261
11262 format %{ "cmpq $op1, $op2\t# ptr" %}
11263 opcode(0x3B); /* Opcode 3B /r */
11264 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11265 ins_pipe(ialu_cr_reg_reg);
11266 %}
11267
11268 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11269 %{
11270 match(Set cr (CmpP op1 (LoadP op2)));
11271
11272 ins_cost(500); // XXX
11273 format %{ "cmpq $op1, $op2\t# ptr" %}
11274 opcode(0x3B); /* Opcode 3B /r */
11275 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11276 ins_pipe(ialu_cr_reg_mem);
11277 %}
11278
11279 // // // Cisc-spilled version of cmpP_rReg
11280 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11281 // //%{
11282 // // match(Set cr (CmpP (LoadP op1) op2));
11283 // //
11284 // // format %{ "CMPu $op1,$op2" %}
11285 // // ins_cost(500);
11286 // // opcode(0x39); /* Opcode 39 /r */
11287 // // ins_encode( OpcP, reg_mem( op1, op2) );
11288 // //%}
11289
11290 // XXX this is generalized by compP_rReg_mem???
11291 // Compare raw pointer (used in out-of-heap check).
11292 // Only works because non-oop pointers must be raw pointers
11293 // and raw pointers have no anti-dependencies.
11294 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11295 %{
11296 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11297 match(Set cr (CmpP op1 (LoadP op2)));
11298
11299 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11300 opcode(0x3B); /* Opcode 3B /r */
11301 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11302 ins_pipe(ialu_cr_reg_mem);
11303 %}
11304
11305 // This will generate a signed flags result. This should be OK since
11306 // any compare to a zero should be eq/neq.
11307 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11308 %{
11309 match(Set cr (CmpP src zero));
11310
11311 format %{ "testq $src, $src\t# ptr" %}
11312 opcode(0x85);
11313 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11314 ins_pipe(ialu_cr_reg_imm);
11315 %}
11316
11317 // This will generate a signed flags result. This should be OK since
11318 // any compare to a zero should be eq/neq.
11319 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11320 %{
11321 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11322 match(Set cr (CmpP (LoadP op) zero));
11323
11324 ins_cost(500); // XXX
11325 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11326 opcode(0xF7); /* Opcode F7 /0 */
11327 ins_encode(REX_mem_wide(op),
11328 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11329 ins_pipe(ialu_cr_reg_imm);
11330 %}
11331
11332 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11333 %{
11334 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11335 match(Set cr (CmpP (LoadP mem) zero));
11336
11337 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11338 ins_encode %{
11339 __ cmpq(r12, $mem$$Address);
11340 %}
11341 ins_pipe(ialu_cr_reg_mem);
11342 %}
11343
11344 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11345 %{
11346 match(Set cr (CmpN op1 op2));
11347
11348 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11349 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11350 ins_pipe(ialu_cr_reg_reg);
11351 %}
11352
11353 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11354 %{
11355 match(Set cr (CmpN src (LoadN mem)));
11356
11357 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11358 ins_encode %{
11359 __ cmpl($src$$Register, $mem$$Address);
11360 %}
11361 ins_pipe(ialu_cr_reg_mem);
11362 %}
11363
11364 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11365 match(Set cr (CmpN op1 op2));
11366
11367 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11368 ins_encode %{
11369 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11370 %}
11371 ins_pipe(ialu_cr_reg_imm);
11372 %}
11373
11374 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11375 %{
11376 match(Set cr (CmpN src (LoadN mem)));
11377
11378 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11379 ins_encode %{
11380 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11381 %}
11382 ins_pipe(ialu_cr_reg_mem);
11383 %}
11384
11385 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11386 match(Set cr (CmpN op1 op2));
11387
11388 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11389 ins_encode %{
11390 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11391 %}
11392 ins_pipe(ialu_cr_reg_imm);
11393 %}
11394
11395 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11396 %{
11397 match(Set cr (CmpN src (LoadNKlass mem)));
11398
11399 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11400 ins_encode %{
11401 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11402 %}
11403 ins_pipe(ialu_cr_reg_mem);
11404 %}
11405
11406 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11407 match(Set cr (CmpN src zero));
11408
11409 format %{ "testl $src, $src\t# compressed ptr" %}
11410 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11411 ins_pipe(ialu_cr_reg_imm);
11412 %}
11413
11414 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11415 %{
11416 predicate(Universe::narrow_oop_base() != NULL);
11417 match(Set cr (CmpN (LoadN mem) zero));
11418
11419 ins_cost(500); // XXX
11420 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11421 ins_encode %{
11422 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11423 %}
11424 ins_pipe(ialu_cr_reg_mem);
11425 %}
11426
11427 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11428 %{
11429 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11430 match(Set cr (CmpN (LoadN mem) zero));
11431
11432 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11433 ins_encode %{
11434 __ cmpl(r12, $mem$$Address);
11435 %}
11436 ins_pipe(ialu_cr_reg_mem);
11437 %}
11438
11439 // Yanked all unsigned pointer compare operations.
11440 // Pointer compares are done with CmpP which is already unsigned.
11441
11442 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11443 %{
11444 match(Set cr (CmpL op1 op2));
11445
11446 format %{ "cmpq $op1, $op2" %}
11447 opcode(0x3B); /* Opcode 3B /r */
11448 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11449 ins_pipe(ialu_cr_reg_reg);
11450 %}
11451
11452 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11453 %{
11454 match(Set cr (CmpL op1 op2));
11455
11456 format %{ "cmpq $op1, $op2" %}
11457 opcode(0x81, 0x07); /* Opcode 81 /7 */
11458 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11459 ins_pipe(ialu_cr_reg_imm);
11460 %}
11461
11462 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11463 %{
11464 match(Set cr (CmpL op1 (LoadL op2)));
11465
11466 format %{ "cmpq $op1, $op2" %}
11467 opcode(0x3B); /* Opcode 3B /r */
11468 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11469 ins_pipe(ialu_cr_reg_mem);
11470 %}
11471
11472 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11473 %{
11474 match(Set cr (CmpL src zero));
11475
11476 format %{ "testq $src, $src" %}
11477 opcode(0x85);
11478 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11479 ins_pipe(ialu_cr_reg_imm);
11480 %}
11481
11482 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11483 %{
11484 match(Set cr (CmpL (AndL src con) zero));
11485
11486 format %{ "testq $src, $con\t# long" %}
11487 opcode(0xF7, 0x00);
11488 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11489 ins_pipe(ialu_cr_reg_imm);
11490 %}
11491
11492 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11493 %{
11494 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11495
11496 format %{ "testq $src, $mem" %}
11497 opcode(0x85);
11498 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11499 ins_pipe(ialu_cr_reg_mem);
11500 %}
11501
11502 // Manifest a CmpL result in an integer register. Very painful.
11503 // This is the test to avoid.
11504 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11505 %{
11506 match(Set dst (CmpL3 src1 src2));
11507 effect(KILL flags);
11508
11509 ins_cost(275); // XXX
11510 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11511 "movl $dst, -1\n\t"
11512 "jl,s done\n\t"
11513 "setne $dst\n\t"
11514 "movzbl $dst, $dst\n\t"
11515 "done:" %}
11516 ins_encode(cmpl3_flag(src1, src2, dst));
11517 ins_pipe(pipe_slow);
11518 %}
11519
11520 //----------Max and Min--------------------------------------------------------
11521 // Min Instructions
11522
11523 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11524 %{
11525 effect(USE_DEF dst, USE src, USE cr);
11526
11527 format %{ "cmovlgt $dst, $src\t# min" %}
11528 opcode(0x0F, 0x4F);
11529 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11530 ins_pipe(pipe_cmov_reg);
11531 %}
11532
11533
11534 instruct minI_rReg(rRegI dst, rRegI src)
11535 %{
11536 match(Set dst (MinI dst src));
11537
11538 ins_cost(200);
11539 expand %{
11540 rFlagsReg cr;
11541 compI_rReg(cr, dst, src);
11542 cmovI_reg_g(dst, src, cr);
11543 %}
11544 %}
11545
11546 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11547 %{
11548 effect(USE_DEF dst, USE src, USE cr);
11549
11550 format %{ "cmovllt $dst, $src\t# max" %}
11551 opcode(0x0F, 0x4C);
11552 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11553 ins_pipe(pipe_cmov_reg);
11554 %}
11555
11556
11557 instruct maxI_rReg(rRegI dst, rRegI src)
11558 %{
11559 match(Set dst (MaxI dst src));
11560
11561 ins_cost(200);
11562 expand %{
11563 rFlagsReg cr;
11564 compI_rReg(cr, dst, src);
11565 cmovI_reg_l(dst, src, cr);
11566 %}
11567 %}
11568
11569 // ============================================================================
11570 // Branch Instructions
11571
11572 // Jump Direct - Label defines a relative address from JMP+1
11573 instruct jmpDir(label labl)
11574 %{
11575 match(Goto);
11576 effect(USE labl);
11577
11578 ins_cost(300);
11579 format %{ "jmp $labl" %}
11580 size(5);
11581 ins_encode %{
11582 Label* L = $labl$$label;
11583 __ jmp(*L, false); // Always long jump
11584 %}
11585 ins_pipe(pipe_jmp);
11586 %}
11587
11588 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11589 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11590 %{
11591 match(If cop cr);
11592 effect(USE labl);
11593
11594 ins_cost(300);
11595 format %{ "j$cop $labl" %}
11596 size(6);
11597 ins_encode %{
11598 Label* L = $labl$$label;
11599 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11600 %}
11601 ins_pipe(pipe_jcc);
11602 %}
11603
11604 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11605 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11606 %{
11607 predicate(!n->has_vector_mask_set());
11608 match(CountedLoopEnd cop cr);
11609 effect(USE labl);
11610
11611 ins_cost(300);
11612 format %{ "j$cop $labl\t# loop end" %}
11613 size(6);
11614 ins_encode %{
11615 Label* L = $labl$$label;
11616 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11617 %}
11618 ins_pipe(pipe_jcc);
11619 %}
11620
11621 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11622 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11623 predicate(!n->has_vector_mask_set());
11624 match(CountedLoopEnd cop cmp);
11625 effect(USE labl);
11626
11627 ins_cost(300);
11628 format %{ "j$cop,u $labl\t# loop end" %}
11629 size(6);
11630 ins_encode %{
11631 Label* L = $labl$$label;
11632 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11633 %}
11634 ins_pipe(pipe_jcc);
11635 %}
11636
11637 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11638 predicate(!n->has_vector_mask_set());
11639 match(CountedLoopEnd cop cmp);
11640 effect(USE labl);
11641
11642 ins_cost(200);
11643 format %{ "j$cop,u $labl\t# loop end" %}
11644 size(6);
11645 ins_encode %{
11646 Label* L = $labl$$label;
11647 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11648 %}
11649 ins_pipe(pipe_jcc);
11650 %}
11651
11652 // mask version
11653 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11654 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
11655 %{
11656 predicate(n->has_vector_mask_set());
11657 match(CountedLoopEnd cop cr);
11658 effect(USE labl);
11659
11660 ins_cost(400);
11661 format %{ "j$cop $labl\t# loop end\n\t"
11662 "restorevectmask \t# vector mask restore for loops" %}
11663 size(10);
11664 ins_encode %{
11665 Label* L = $labl$$label;
11666 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11667 __ restorevectmask();
11668 %}
11669 ins_pipe(pipe_jcc);
11670 %}
11671
11672 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11673 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11674 predicate(n->has_vector_mask_set());
11675 match(CountedLoopEnd cop cmp);
11676 effect(USE labl);
11677
11678 ins_cost(400);
11679 format %{ "j$cop,u $labl\t# loop end\n\t"
11680 "restorevectmask \t# vector mask restore for loops" %}
11681 size(10);
11682 ins_encode %{
11683 Label* L = $labl$$label;
11684 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11685 __ restorevectmask();
11686 %}
11687 ins_pipe(pipe_jcc);
11688 %}
11689
11690 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11691 predicate(n->has_vector_mask_set());
11692 match(CountedLoopEnd cop cmp);
11693 effect(USE labl);
11694
11695 ins_cost(300);
11696 format %{ "j$cop,u $labl\t# loop end\n\t"
11697 "restorevectmask \t# vector mask restore for loops" %}
11698 size(10);
11699 ins_encode %{
11700 Label* L = $labl$$label;
11701 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11702 __ restorevectmask();
11703 %}
11704 ins_pipe(pipe_jcc);
11705 %}
11706
11707 // Jump Direct Conditional - using unsigned comparison
11708 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11709 match(If cop cmp);
11710 effect(USE labl);
11711
11712 ins_cost(300);
11713 format %{ "j$cop,u $labl" %}
11714 size(6);
11715 ins_encode %{
11716 Label* L = $labl$$label;
11717 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11718 %}
11719 ins_pipe(pipe_jcc);
11720 %}
11721
11722 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11723 match(If cop cmp);
11724 effect(USE labl);
11725
11726 ins_cost(200);
11727 format %{ "j$cop,u $labl" %}
11728 size(6);
11729 ins_encode %{
11730 Label* L = $labl$$label;
11731 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11732 %}
11733 ins_pipe(pipe_jcc);
11734 %}
11735
11736 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11737 match(If cop cmp);
11738 effect(USE labl);
11739
11740 ins_cost(200);
11741 format %{ $$template
11742 if ($cop$$cmpcode == Assembler::notEqual) {
11743 $$emit$$"jp,u $labl\n\t"
11744 $$emit$$"j$cop,u $labl"
11745 } else {
11746 $$emit$$"jp,u done\n\t"
11747 $$emit$$"j$cop,u $labl\n\t"
11748 $$emit$$"done:"
11749 }
11750 %}
11751 ins_encode %{
11752 Label* l = $labl$$label;
11753 if ($cop$$cmpcode == Assembler::notEqual) {
11754 __ jcc(Assembler::parity, *l, false);
11755 __ jcc(Assembler::notEqual, *l, false);
11756 } else if ($cop$$cmpcode == Assembler::equal) {
11757 Label done;
11758 __ jccb(Assembler::parity, done);
11759 __ jcc(Assembler::equal, *l, false);
11760 __ bind(done);
11761 } else {
11762 ShouldNotReachHere();
11763 }
11764 %}
11765 ins_pipe(pipe_jcc);
11766 %}
11767
11768 // ============================================================================
11769 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11770 // superklass array for an instance of the superklass. Set a hidden
11771 // internal cache on a hit (cache is checked with exposed code in
11772 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11773 // encoding ALSO sets flags.
11774
11775 instruct partialSubtypeCheck(rdi_RegP result,
11776 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11777 rFlagsReg cr)
11778 %{
11779 match(Set result (PartialSubtypeCheck sub super));
11780 effect(KILL rcx, KILL cr);
11781
11782 ins_cost(1100); // slightly larger than the next version
11783 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11784 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11785 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11786 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11787 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11788 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11789 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11790 "miss:\t" %}
11791
11792 opcode(0x1); // Force a XOR of RDI
11793 ins_encode(enc_PartialSubtypeCheck());
11794 ins_pipe(pipe_slow);
11795 %}
11796
11797 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11798 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11799 immP0 zero,
11800 rdi_RegP result)
11801 %{
11802 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11803 effect(KILL rcx, KILL result);
11804
11805 ins_cost(1000);
11806 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11807 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11808 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11809 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11810 "jne,s miss\t\t# Missed: flags nz\n\t"
11811 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11812 "miss:\t" %}
11813
11814 opcode(0x0); // No need to XOR RDI
11815 ins_encode(enc_PartialSubtypeCheck());
11816 ins_pipe(pipe_slow);
11817 %}
11818
11819 // ============================================================================
11820 // Branch Instructions -- short offset versions
11821 //
11822 // These instructions are used to replace jumps of a long offset (the default
11823 // match) with jumps of a shorter offset. These instructions are all tagged
11824 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11825 // match rules in general matching. Instead, the ADLC generates a conversion
11826 // method in the MachNode which can be used to do in-place replacement of the
11827 // long variant with the shorter variant. The compiler will determine if a
11828 // branch can be taken by the is_short_branch_offset() predicate in the machine
11829 // specific code section of the file.
11830
11831 // Jump Direct - Label defines a relative address from JMP+1
11832 instruct jmpDir_short(label labl) %{
11833 match(Goto);
11834 effect(USE labl);
11835
11836 ins_cost(300);
11837 format %{ "jmp,s $labl" %}
11838 size(2);
11839 ins_encode %{
11840 Label* L = $labl$$label;
11841 __ jmpb(*L);
11842 %}
11843 ins_pipe(pipe_jmp);
11844 ins_short_branch(1);
11845 %}
11846
11847 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11848 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11849 match(If cop cr);
11850 effect(USE labl);
11851
11852 ins_cost(300);
11853 format %{ "j$cop,s $labl" %}
11854 size(2);
11855 ins_encode %{
11856 Label* L = $labl$$label;
11857 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11858 %}
11859 ins_pipe(pipe_jcc);
11860 ins_short_branch(1);
11861 %}
11862
11863 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11864 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11865 match(CountedLoopEnd cop cr);
11866 effect(USE labl);
11867
11868 ins_cost(300);
11869 format %{ "j$cop,s $labl\t# loop end" %}
11870 size(2);
11871 ins_encode %{
11872 Label* L = $labl$$label;
11873 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11874 %}
11875 ins_pipe(pipe_jcc);
11876 ins_short_branch(1);
11877 %}
11878
11879 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11880 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11881 match(CountedLoopEnd cop cmp);
11882 effect(USE labl);
11883
11884 ins_cost(300);
11885 format %{ "j$cop,us $labl\t# loop end" %}
11886 size(2);
11887 ins_encode %{
11888 Label* L = $labl$$label;
11889 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11890 %}
11891 ins_pipe(pipe_jcc);
11892 ins_short_branch(1);
11893 %}
11894
11895 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11896 match(CountedLoopEnd cop cmp);
11897 effect(USE labl);
11898
11899 ins_cost(300);
11900 format %{ "j$cop,us $labl\t# loop end" %}
11901 size(2);
11902 ins_encode %{
11903 Label* L = $labl$$label;
11904 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11905 %}
11906 ins_pipe(pipe_jcc);
11907 ins_short_branch(1);
11908 %}
11909
11910 // Jump Direct Conditional - using unsigned comparison
11911 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11912 match(If cop cmp);
11913 effect(USE labl);
11914
11915 ins_cost(300);
11916 format %{ "j$cop,us $labl" %}
11917 size(2);
11918 ins_encode %{
11919 Label* L = $labl$$label;
11920 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11921 %}
11922 ins_pipe(pipe_jcc);
11923 ins_short_branch(1);
11924 %}
11925
11926 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11927 match(If cop cmp);
11928 effect(USE labl);
11929
11930 ins_cost(300);
11931 format %{ "j$cop,us $labl" %}
11932 size(2);
11933 ins_encode %{
11934 Label* L = $labl$$label;
11935 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11936 %}
11937 ins_pipe(pipe_jcc);
11938 ins_short_branch(1);
11939 %}
11940
11941 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11942 match(If cop cmp);
11943 effect(USE labl);
11944
11945 ins_cost(300);
11946 format %{ $$template
11947 if ($cop$$cmpcode == Assembler::notEqual) {
11948 $$emit$$"jp,u,s $labl\n\t"
11949 $$emit$$"j$cop,u,s $labl"
11950 } else {
11951 $$emit$$"jp,u,s done\n\t"
11952 $$emit$$"j$cop,u,s $labl\n\t"
11953 $$emit$$"done:"
11954 }
11955 %}
11956 size(4);
11957 ins_encode %{
11958 Label* l = $labl$$label;
11959 if ($cop$$cmpcode == Assembler::notEqual) {
11960 __ jccb(Assembler::parity, *l);
11961 __ jccb(Assembler::notEqual, *l);
11962 } else if ($cop$$cmpcode == Assembler::equal) {
11963 Label done;
11964 __ jccb(Assembler::parity, done);
11965 __ jccb(Assembler::equal, *l);
11966 __ bind(done);
11967 } else {
11968 ShouldNotReachHere();
11969 }
11970 %}
11971 ins_pipe(pipe_jcc);
11972 ins_short_branch(1);
11973 %}
11974
11975 // ============================================================================
11976 // inlined locking and unlocking
11977
11978 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11979 predicate(Compile::current()->use_rtm());
11980 match(Set cr (FastLock object box));
11981 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11982 ins_cost(300);
11983 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11984 ins_encode %{
11985 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11986 $scr$$Register, $cx1$$Register, $cx2$$Register,
11987 _counters, _rtm_counters, _stack_rtm_counters,
11988 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11989 true, ra_->C->profile_rtm());
11990 %}
11991 ins_pipe(pipe_slow);
11992 %}
11993
11994 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11995 predicate(!Compile::current()->use_rtm());
11996 match(Set cr (FastLock object box));
11997 effect(TEMP tmp, TEMP scr, USE_KILL box);
11998 ins_cost(300);
11999 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12000 ins_encode %{
12001 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12002 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12003 %}
12004 ins_pipe(pipe_slow);
12005 %}
12006
12007 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12008 match(Set cr (FastUnlock object box));
12009 effect(TEMP tmp, USE_KILL box);
12010 ins_cost(300);
12011 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12012 ins_encode %{
12013 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12014 %}
12015 ins_pipe(pipe_slow);
12016 %}
12017
12018
12019 // ============================================================================
12020 // Safepoint Instructions
12021 instruct safePoint_poll(rFlagsReg cr)
12022 %{
12023 predicate(!Assembler::is_polling_page_far());
12024 match(SafePoint);
12025 effect(KILL cr);
12026
12027 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12028 "# Safepoint: poll for GC" %}
12029 ins_cost(125);
12030 ins_encode %{
12031 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12032 __ testl(rax, addr);
12033 %}
12034 ins_pipe(ialu_reg_mem);
12035 %}
12036
12037 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12038 %{
12039 predicate(Assembler::is_polling_page_far());
12040 match(SafePoint poll);
12041 effect(KILL cr, USE poll);
12042
12043 format %{ "testl rax, [$poll]\t"
12044 "# Safepoint: poll for GC" %}
12045 ins_cost(125);
12046 ins_encode %{
12047 __ relocate(relocInfo::poll_type);
12048 __ testl(rax, Address($poll$$Register, 0));
12049 %}
12050 ins_pipe(ialu_reg_mem);
12051 %}
12052
12053 // ============================================================================
12054 // Procedure Call/Return Instructions
12055 // Call Java Static Instruction
12056 // Note: If this code changes, the corresponding ret_addr_offset() and
12057 // compute_padding() functions will have to be adjusted.
12058 instruct CallStaticJavaDirect(method meth) %{
12059 match(CallStaticJava);
12060 effect(USE meth);
12061
12062 ins_cost(300);
12063 format %{ "call,static " %}
12064 opcode(0xE8); /* E8 cd */
12065 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12066 ins_pipe(pipe_slow);
12067 ins_alignment(4);
12068 %}
12069
12070 // Call Java Dynamic Instruction
12071 // Note: If this code changes, the corresponding ret_addr_offset() and
12072 // compute_padding() functions will have to be adjusted.
12073 instruct CallDynamicJavaDirect(method meth)
12074 %{
12075 match(CallDynamicJava);
12076 effect(USE meth);
12077
12078 ins_cost(300);
12079 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12080 "call,dynamic " %}
12081 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12082 ins_pipe(pipe_slow);
12083 ins_alignment(4);
12084 %}
12085
12086 // Call Runtime Instruction
12087 instruct CallRuntimeDirect(method meth)
12088 %{
12089 match(CallRuntime);
12090 effect(USE meth);
12091
12092 ins_cost(300);
12093 format %{ "call,runtime " %}
12094 ins_encode(clear_avx, Java_To_Runtime(meth));
12095 ins_pipe(pipe_slow);
12096 %}
12097
12098 // Call runtime without safepoint
12099 instruct CallLeafDirect(method meth)
12100 %{
12101 match(CallLeaf);
12102 effect(USE meth);
12103
12104 ins_cost(300);
12105 format %{ "call_leaf,runtime " %}
12106 ins_encode(clear_avx, Java_To_Runtime(meth));
12107 ins_pipe(pipe_slow);
12108 %}
12109
12110 // Call runtime without safepoint
12111 instruct CallLeafNoFPDirect(method meth)
12112 %{
12113 match(CallLeafNoFP);
12114 effect(USE meth);
12115
12116 ins_cost(300);
12117 format %{ "call_leaf_nofp,runtime " %}
12118 ins_encode(clear_avx, Java_To_Runtime(meth));
12119 ins_pipe(pipe_slow);
12120 %}
12121
12122 // Return Instruction
12123 // Remove the return address & jump to it.
12124 // Notice: We always emit a nop after a ret to make sure there is room
12125 // for safepoint patching
12126 instruct Ret()
12127 %{
12128 match(Return);
12129
12130 format %{ "ret" %}
12131 opcode(0xC3);
12132 ins_encode(OpcP);
12133 ins_pipe(pipe_jmp);
12134 %}
12135
12136 // Tail Call; Jump from runtime stub to Java code.
12137 // Also known as an 'interprocedural jump'.
12138 // Target of jump will eventually return to caller.
12139 // TailJump below removes the return address.
12140 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12141 %{
12142 match(TailCall jump_target method_oop);
12143
12144 ins_cost(300);
12145 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12146 opcode(0xFF, 0x4); /* Opcode FF /4 */
12147 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12148 ins_pipe(pipe_jmp);
12149 %}
12150
12151 // Tail Jump; remove the return address; jump to target.
12152 // TailCall above leaves the return address around.
12153 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12154 %{
12155 match(TailJump jump_target ex_oop);
12156
12157 ins_cost(300);
12158 format %{ "popq rdx\t# pop return address\n\t"
12159 "jmp $jump_target" %}
12160 opcode(0xFF, 0x4); /* Opcode FF /4 */
12161 ins_encode(Opcode(0x5a), // popq rdx
12162 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12163 ins_pipe(pipe_jmp);
12164 %}
12165
12166 // Create exception oop: created by stack-crawling runtime code.
12167 // Created exception is now available to this handler, and is setup
12168 // just prior to jumping to this handler. No code emitted.
12169 instruct CreateException(rax_RegP ex_oop)
12170 %{
12171 match(Set ex_oop (CreateEx));
12172
12173 size(0);
12174 // use the following format syntax
12175 format %{ "# exception oop is in rax; no code emitted" %}
12176 ins_encode();
12177 ins_pipe(empty);
12178 %}
12179
12180 // Rethrow exception:
12181 // The exception oop will come in the first argument position.
12182 // Then JUMP (not call) to the rethrow stub code.
12183 instruct RethrowException()
12184 %{
12185 match(Rethrow);
12186
12187 // use the following format syntax
12188 format %{ "jmp rethrow_stub" %}
12189 ins_encode(enc_rethrow);
12190 ins_pipe(pipe_jmp);
12191 %}
12192
12193
12194 // ============================================================================
12195 // This name is KNOWN by the ADLC and cannot be changed.
12196 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12197 // for this guy.
12198 instruct tlsLoadP(r15_RegP dst) %{
12199 match(Set dst (ThreadLocal));
12200 effect(DEF dst);
12201
12202 size(0);
12203 format %{ "# TLS is in R15" %}
12204 ins_encode( /*empty encoding*/ );
12205 ins_pipe(ialu_reg_reg);
12206 %}
12207
12208
12209 //----------PEEPHOLE RULES-----------------------------------------------------
12210 // These must follow all instruction definitions as they use the names
12211 // defined in the instructions definitions.
12212 //
12213 // peepmatch ( root_instr_name [preceding_instruction]* );
12214 //
12215 // peepconstraint %{
12216 // (instruction_number.operand_name relational_op instruction_number.operand_name
12217 // [, ...] );
12218 // // instruction numbers are zero-based using left to right order in peepmatch
12219 //
12220 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12221 // // provide an instruction_number.operand_name for each operand that appears
12222 // // in the replacement instruction's match rule
12223 //
12224 // ---------VM FLAGS---------------------------------------------------------
12225 //
12226 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12227 //
12228 // Each peephole rule is given an identifying number starting with zero and
12229 // increasing by one in the order seen by the parser. An individual peephole
12230 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12231 // on the command-line.
12232 //
12233 // ---------CURRENT LIMITATIONS----------------------------------------------
12234 //
12235 // Only match adjacent instructions in same basic block
12236 // Only equality constraints
12237 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12238 // Only one replacement instruction
12239 //
12240 // ---------EXAMPLE----------------------------------------------------------
12241 //
12242 // // pertinent parts of existing instructions in architecture description
12243 // instruct movI(rRegI dst, rRegI src)
12244 // %{
12245 // match(Set dst (CopyI src));
12246 // %}
12247 //
12248 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12249 // %{
12250 // match(Set dst (AddI dst src));
12251 // effect(KILL cr);
12252 // %}
12253 //
12254 // // Change (inc mov) to lea
12255 // peephole %{
12256 // // increment preceeded by register-register move
12257 // peepmatch ( incI_rReg movI );
12258 // // require that the destination register of the increment
12259 // // match the destination register of the move
12260 // peepconstraint ( 0.dst == 1.dst );
12261 // // construct a replacement instruction that sets
12262 // // the destination to ( move's source register + one )
12263 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12264 // %}
12265 //
12266
12267 // Implementation no longer uses movX instructions since
12268 // machine-independent system no longer uses CopyX nodes.
12269 //
12270 // peephole
12271 // %{
12272 // peepmatch (incI_rReg movI);
12273 // peepconstraint (0.dst == 1.dst);
12274 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12275 // %}
12276
12277 // peephole
12278 // %{
12279 // peepmatch (decI_rReg movI);
12280 // peepconstraint (0.dst == 1.dst);
12281 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12282 // %}
12283
12284 // peephole
12285 // %{
12286 // peepmatch (addI_rReg_imm movI);
12287 // peepconstraint (0.dst == 1.dst);
12288 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12289 // %}
12290
12291 // peephole
12292 // %{
12293 // peepmatch (incL_rReg movL);
12294 // peepconstraint (0.dst == 1.dst);
12295 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12296 // %}
12297
12298 // peephole
12299 // %{
12300 // peepmatch (decL_rReg movL);
12301 // peepconstraint (0.dst == 1.dst);
12302 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12303 // %}
12304
12305 // peephole
12306 // %{
12307 // peepmatch (addL_rReg_imm movL);
12308 // peepconstraint (0.dst == 1.dst);
12309 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12310 // %}
12311
12312 // peephole
12313 // %{
12314 // peepmatch (addP_rReg_imm movP);
12315 // peepconstraint (0.dst == 1.dst);
12316 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12317 // %}
12318
12319 // // Change load of spilled value to only a spill
12320 // instruct storeI(memory mem, rRegI src)
12321 // %{
12322 // match(Set mem (StoreI mem src));
12323 // %}
12324 //
12325 // instruct loadI(rRegI dst, memory mem)
12326 // %{
12327 // match(Set dst (LoadI mem));
12328 // %}
12329 //
12330
12331 peephole
12332 %{
12333 peepmatch (loadI storeI);
12334 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12335 peepreplace (storeI(1.mem 1.mem 1.src));
12336 %}
12337
12338 peephole
12339 %{
12340 peepmatch (loadL storeL);
12341 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12342 peepreplace (storeL(1.mem 1.mem 1.src));
12343 %}
12344
12345 //----------SMARTSPILL RULES---------------------------------------------------
12346 // These must follow all instruction definitions as they use the names
12347 // defined in the instructions definitions.