519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
2075 %{
2076 Register Rrdi = as_Register(RDI_enc); // result register
2077 Register Rrax = as_Register(RAX_enc); // super class
2078 Register Rrcx = as_Register(RCX_enc); // killed
2079 Register Rrsi = as_Register(RSI_enc); // sub class
2080 Label miss;
2081 const bool set_cond_codes = true;
2082
2083 MacroAssembler _masm(&cbuf);
2084 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2085 NULL, &miss,
2086 /*set_cond_codes:*/ true);
2087 if ($primary) {
2088 __ xorptr(Rrdi, Rrdi);
2089 }
2090 __ bind(miss);
2091 %}
2092
2093 enc_class clear_avx %{
2094 debug_only(int off0 = cbuf.insts_size());
2095 if (ra_->C->max_vector_size() > 16) {
2096 // Clear upper bits of YMM registers when current compiled code uses
2097 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2098 MacroAssembler _masm(&cbuf);
2099 __ vzeroupper();
2100 }
2101 debug_only(int off1 = cbuf.insts_size());
2102 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2103 %}
2104
2105 enc_class Java_To_Runtime(method meth) %{
2106 // No relocation needed
2107 MacroAssembler _masm(&cbuf);
2108 __ mov64(r10, (int64_t) $meth$$method);
2109 __ call(r10);
2110 %}
2111
2112 enc_class Java_To_Interpreter(method meth)
2113 %{
2114 // CALL Java_To_Interpreter
2115 // This is the instruction starting address for relocation info.
2116 cbuf.set_insts_mark();
2117 $$$emit8$primary;
2118 // CALL directly to the runtime
2119 emit_d32_reloc(cbuf,
2120 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
12099 // Call runtime without safepoint
12100 instruct CallLeafDirect(method meth)
12101 %{
12102 match(CallLeaf);
12103 effect(USE meth);
12104
12105 ins_cost(300);
12106 format %{ "call_leaf,runtime " %}
12107 ins_encode(clear_avx, Java_To_Runtime(meth));
12108 ins_pipe(pipe_slow);
12109 %}
12110
12111 // Call runtime without safepoint
12112 instruct CallLeafNoFPDirect(method meth)
12113 %{
12114 match(CallLeafNoFP);
12115 effect(USE meth);
12116
12117 ins_cost(300);
12118 format %{ "call_leaf_nofp,runtime " %}
12119 ins_encode(Java_To_Runtime(meth));
12120 ins_pipe(pipe_slow);
12121 %}
12122
12123 // Return Instruction
12124 // Remove the return address & jump to it.
12125 // Notice: We always emit a nop after a ret to make sure there is room
12126 // for safepoint patching
12127 instruct Ret()
12128 %{
12129 match(Return);
12130
12131 format %{ "ret" %}
12132 opcode(0xC3);
12133 ins_encode(OpcP);
12134 ins_pipe(pipe_jmp);
12135 %}
12136
12137 // Tail Call; Jump from runtime stub to Java code.
12138 // Also known as an 'interprocedural jump'.
12139 // Target of jump will eventually return to caller.
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519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return UseVzeroupper ? 3: 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
2075 %{
2076 Register Rrdi = as_Register(RDI_enc); // result register
2077 Register Rrax = as_Register(RAX_enc); // super class
2078 Register Rrcx = as_Register(RCX_enc); // killed
2079 Register Rrsi = as_Register(RSI_enc); // sub class
2080 Label miss;
2081 const bool set_cond_codes = true;
2082
2083 MacroAssembler _masm(&cbuf);
2084 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2085 NULL, &miss,
2086 /*set_cond_codes:*/ true);
2087 if ($primary) {
2088 __ xorptr(Rrdi, Rrdi);
2089 }
2090 __ bind(miss);
2091 %}
2092
2093 enc_class clear_avx %{
2094 debug_only(int off0 = cbuf.insts_size());
2095 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2096 // Clear upper bits of YMM registers when current compiled code uses
2097 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2098 MacroAssembler _masm(&cbuf);
2099 __ vzeroupper();
2100 debug_only(int off1 = cbuf.insts_size());
2101 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2102 %}
2103
2104 enc_class Java_To_Runtime(method meth) %{
2105 // No relocation needed
2106 MacroAssembler _masm(&cbuf);
2107 __ mov64(r10, (int64_t) $meth$$method);
2108 __ call(r10);
2109 %}
2110
2111 enc_class Java_To_Interpreter(method meth)
2112 %{
2113 // CALL Java_To_Interpreter
2114 // This is the instruction starting address for relocation info.
2115 cbuf.set_insts_mark();
2116 $$$emit8$primary;
2117 // CALL directly to the runtime
2118 emit_d32_reloc(cbuf,
2119 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
12098 // Call runtime without safepoint
12099 instruct CallLeafDirect(method meth)
12100 %{
12101 match(CallLeaf);
12102 effect(USE meth);
12103
12104 ins_cost(300);
12105 format %{ "call_leaf,runtime " %}
12106 ins_encode(clear_avx, Java_To_Runtime(meth));
12107 ins_pipe(pipe_slow);
12108 %}
12109
12110 // Call runtime without safepoint
12111 instruct CallLeafNoFPDirect(method meth)
12112 %{
12113 match(CallLeafNoFP);
12114 effect(USE meth);
12115
12116 ins_cost(300);
12117 format %{ "call_leaf_nofp,runtime " %}
12118 ins_encode(clear_avx, Java_To_Runtime(meth));
12119 ins_pipe(pipe_slow);
12120 %}
12121
12122 // Return Instruction
12123 // Remove the return address & jump to it.
12124 // Notice: We always emit a nop after a ret to make sure there is room
12125 // for safepoint patching
12126 instruct Ret()
12127 %{
12128 match(Return);
12129
12130 format %{ "ret" %}
12131 opcode(0xC3);
12132 ins_encode(OpcP);
12133 ins_pipe(pipe_jmp);
12134 %}
12135
12136 // Tail Call; Jump from runtime stub to Java code.
12137 // Also known as an 'interprocedural jump'.
12138 // Target of jump will eventually return to caller.
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