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src/cpu/x86/vm/assembler_x86.cpp
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@@ -2101,16 +2101,24 @@
emit_int8(0);
}
}
void Assembler::ldmxcsr( Address src) {
+ if (UseAVX > 0 ) {
+ InstructionMark im(this);
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
+ vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
+ emit_int8((unsigned char)0xAE);
+ emit_operand(as_Register(2), src);
+ } else {
NOT_LP64(assert(VM_Version::supports_sse(), ""));
InstructionMark im(this);
prefix(src);
emit_int8(0x0F);
emit_int8((unsigned char)0xAE);
emit_operand(as_Register(2), src);
+ }
}
void Assembler::leal(Register dst, Address src) {
InstructionMark im(this);
#ifdef _LP64
@@ -4414,16 +4422,25 @@
emit_int8(0x51);
emit_operand(dst, src);
}
void Assembler::stmxcsr( Address dst) {
+ if (UseAVX > 0 ) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionMark im(this);
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
+ vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
+ emit_int8((unsigned char)0xAE);
+ emit_operand(as_Register(3), dst);
+ } else {
NOT_LP64(assert(VM_Version::supports_sse(), ""));
InstructionMark im(this);
prefix(dst);
emit_int8(0x0F);
emit_int8((unsigned char)0xAE);
emit_operand(as_Register(3), dst);
+ }
}
void Assembler::subl(Address dst, int32_t imm32) {
InstructionMark im(this);
prefix(dst);
@@ -6618,14 +6635,15 @@
emit_int8((unsigned char)(0xC0 | encode));
emit_int8((unsigned char)mask);
}
void Assembler::vzeroupper() {
- assert(VM_Version::supports_avx(), "");
+ if (VM_Version::supports_vzeroupper()) {
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
(void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
emit_int8(0x77);
+ }
}
#ifndef _LP64
// 32bit only pieces of the assembler
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