1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 756 // we must set sp to zero to clear frame 757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 758 // must clear fp, so that compiled frames are not confused; it is 759 // possible that we need it only for debugging 760 if (clear_fp) { 761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 762 } 763 764 // Always clear the pc because it could have been set by make_walkable() 765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 766 vzeroupper(); 767 } 768 769 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 770 Register last_java_fp, 771 address last_java_pc) { 772 vzeroupper(); 773 // determine last_java_sp register 774 if (!last_java_sp->is_valid()) { 775 last_java_sp = rsp; 776 } 777 778 // last_java_fp is optional 779 if (last_java_fp->is_valid()) { 780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 781 last_java_fp); 782 } 783 784 // last_java_pc is optional 785 if (last_java_pc != NULL) { 786 Address java_pc(r15_thread, 787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 788 lea(rscratch1, InternalAddress(last_java_pc)); 789 movptr(java_pc, rscratch1); 790 } 791 792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 793 } 794 795 static void pass_arg0(MacroAssembler* masm, Register arg) { 796 if (c_rarg0 != arg ) { 797 masm->mov(c_rarg0, arg); 798 } 799 } 800 801 static void pass_arg1(MacroAssembler* masm, Register arg) { 802 if (c_rarg1 != arg ) { 803 masm->mov(c_rarg1, arg); 804 } 805 } 806 807 static void pass_arg2(MacroAssembler* masm, Register arg) { 808 if (c_rarg2 != arg ) { 809 masm->mov(c_rarg2, arg); 810 } 811 } 812 813 static void pass_arg3(MacroAssembler* masm, Register arg) { 814 if (c_rarg3 != arg ) { 815 masm->mov(c_rarg3, arg); 816 } 817 } 818 819 void MacroAssembler::stop(const char* msg) { 820 address rip = pc(); 821 pusha(); // get regs on stack 822 lea(c_rarg0, ExternalAddress((address) msg)); 823 lea(c_rarg1, InternalAddress(rip)); 824 movq(c_rarg2, rsp); // pass pointer to regs array 825 andq(rsp, -16); // align stack as required by ABI 826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 827 hlt(); 828 } 829 830 void MacroAssembler::warn(const char* msg) { 831 push(rbp); 832 movq(rbp, rsp); 833 andq(rsp, -16); // align stack as required by push_CPU_state and call 834 push_CPU_state(); // keeps alignment at 16 bytes 835 lea(c_rarg0, ExternalAddress((address) msg)); 836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 837 pop_CPU_state(); 838 mov(rsp, rbp); 839 pop(rbp); 840 } 841 842 void MacroAssembler::print_state() { 843 address rip = pc(); 844 pusha(); // get regs on stack 845 push(rbp); 846 movq(rbp, rsp); 847 andq(rsp, -16); // align stack as required by push_CPU_state and call 848 push_CPU_state(); // keeps alignment at 16 bytes 849 850 lea(c_rarg0, InternalAddress(rip)); 851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 853 854 pop_CPU_state(); 855 mov(rsp, rbp); 856 pop(rbp); 857 popa(); 858 } 859 860 #ifndef PRODUCT 861 extern "C" void findpc(intptr_t x); 862 #endif 863 864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 865 // In order to get locks to work, we need to fake a in_VM state 866 if (ShowMessageBoxOnError) { 867 JavaThread* thread = JavaThread::current(); 868 JavaThreadState saved_state = thread->thread_state(); 869 thread->set_thread_state(_thread_in_vm); 870 #ifndef PRODUCT 871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 872 ttyLocker ttyl; 873 BytecodeCounter::print(); 874 } 875 #endif 876 // To see where a verify_oop failed, get $ebx+40/X for this frame. 877 // XXX correct this offset for amd64 878 // This is the value of eip which points to where verify_oop will return. 879 if (os::message_box(msg, "Execution stopped, print registers?")) { 880 print_state64(pc, regs); 881 BREAKPOINT; 882 assert(false, "start up GDB"); 883 } 884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 885 } else { 886 ttyLocker ttyl; 887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 888 msg); 889 assert(false, "DEBUG MESSAGE: %s", msg); 890 } 891 } 892 893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 894 ttyLocker ttyl; 895 FlagSetting fs(Debugging, true); 896 tty->print_cr("rip = 0x%016lx", pc); 897 #ifndef PRODUCT 898 tty->cr(); 899 findpc(pc); 900 tty->cr(); 901 #endif 902 #define PRINT_REG(rax, value) \ 903 { tty->print("%s = ", #rax); os::print_location(tty, value); } 904 PRINT_REG(rax, regs[15]); 905 PRINT_REG(rbx, regs[12]); 906 PRINT_REG(rcx, regs[14]); 907 PRINT_REG(rdx, regs[13]); 908 PRINT_REG(rdi, regs[8]); 909 PRINT_REG(rsi, regs[9]); 910 PRINT_REG(rbp, regs[10]); 911 PRINT_REG(rsp, regs[11]); 912 PRINT_REG(r8 , regs[7]); 913 PRINT_REG(r9 , regs[6]); 914 PRINT_REG(r10, regs[5]); 915 PRINT_REG(r11, regs[4]); 916 PRINT_REG(r12, regs[3]); 917 PRINT_REG(r13, regs[2]); 918 PRINT_REG(r14, regs[1]); 919 PRINT_REG(r15, regs[0]); 920 #undef PRINT_REG 921 // Print some words near top of staack. 922 int64_t* rsp = (int64_t*) regs[11]; 923 int64_t* dump_sp = rsp; 924 for (int col1 = 0; col1 < 8; col1++) { 925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 926 os::print_location(tty, *dump_sp++); 927 } 928 for (int row = 0; row < 25; row++) { 929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 930 for (int col = 0; col < 4; col++) { 931 tty->print(" 0x%016lx", *dump_sp++); 932 } 933 tty->cr(); 934 } 935 // Print some instructions around pc: 936 Disassembler::decode((address)pc-64, (address)pc); 937 tty->print_cr("--------"); 938 Disassembler::decode((address)pc, (address)pc+32); 939 } 940 941 #endif // _LP64 942 943 // Now versions that are common to 32/64 bit 944 945 void MacroAssembler::addptr(Register dst, int32_t imm32) { 946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 947 } 948 949 void MacroAssembler::addptr(Register dst, Register src) { 950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 951 } 952 953 void MacroAssembler::addptr(Address dst, Register src) { 954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 955 } 956 957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 958 if (reachable(src)) { 959 Assembler::addsd(dst, as_Address(src)); 960 } else { 961 lea(rscratch1, src); 962 Assembler::addsd(dst, Address(rscratch1, 0)); 963 } 964 } 965 966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 967 if (reachable(src)) { 968 addss(dst, as_Address(src)); 969 } else { 970 lea(rscratch1, src); 971 addss(dst, Address(rscratch1, 0)); 972 } 973 } 974 975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 976 if (reachable(src)) { 977 Assembler::addpd(dst, as_Address(src)); 978 } else { 979 lea(rscratch1, src); 980 Assembler::addpd(dst, Address(rscratch1, 0)); 981 } 982 } 983 984 void MacroAssembler::align(int modulus) { 985 align(modulus, offset()); 986 } 987 988 void MacroAssembler::align(int modulus, int target) { 989 if (target % modulus != 0) { 990 nop(modulus - (target % modulus)); 991 } 992 } 993 994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 995 // Used in sign-masking with aligned address. 996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 997 if (reachable(src)) { 998 Assembler::andpd(dst, as_Address(src)); 999 } else { 1000 lea(rscratch1, src); 1001 Assembler::andpd(dst, Address(rscratch1, 0)); 1002 } 1003 } 1004 1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1006 // Used in sign-masking with aligned address. 1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1008 if (reachable(src)) { 1009 Assembler::andps(dst, as_Address(src)); 1010 } else { 1011 lea(rscratch1, src); 1012 Assembler::andps(dst, Address(rscratch1, 0)); 1013 } 1014 } 1015 1016 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1018 } 1019 1020 void MacroAssembler::atomic_incl(Address counter_addr) { 1021 if (os::is_MP()) 1022 lock(); 1023 incrementl(counter_addr); 1024 } 1025 1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1027 if (reachable(counter_addr)) { 1028 atomic_incl(as_Address(counter_addr)); 1029 } else { 1030 lea(scr, counter_addr); 1031 atomic_incl(Address(scr, 0)); 1032 } 1033 } 1034 1035 #ifdef _LP64 1036 void MacroAssembler::atomic_incq(Address counter_addr) { 1037 if (os::is_MP()) 1038 lock(); 1039 incrementq(counter_addr); 1040 } 1041 1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1043 if (reachable(counter_addr)) { 1044 atomic_incq(as_Address(counter_addr)); 1045 } else { 1046 lea(scr, counter_addr); 1047 atomic_incq(Address(scr, 0)); 1048 } 1049 } 1050 #endif 1051 1052 // Writes to stack successive pages until offset reached to check for 1053 // stack overflow + shadow pages. This clobbers tmp. 1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1055 movptr(tmp, rsp); 1056 // Bang stack for total size given plus shadow page size. 1057 // Bang one page at a time because large size can bang beyond yellow and 1058 // red zones. 1059 Label loop; 1060 bind(loop); 1061 movl(Address(tmp, (-os::vm_page_size())), size ); 1062 subptr(tmp, os::vm_page_size()); 1063 subl(size, os::vm_page_size()); 1064 jcc(Assembler::greater, loop); 1065 1066 // Bang down shadow pages too. 1067 // At this point, (tmp-0) is the last address touched, so don't 1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1069 // was post-decremented.) Skip this address by starting at i=1, and 1070 // touch a few more pages below. N.B. It is important to touch all 1071 // the way down including all pages in the shadow zone. 1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1073 // this could be any sized move but this is can be a debugging crumb 1074 // so the bigger the better. 1075 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1076 } 1077 } 1078 1079 void MacroAssembler::reserved_stack_check() { 1080 // testing if reserved zone needs to be enabled 1081 Label no_reserved_zone_enabling; 1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1083 NOT_LP64(get_thread(rsi);) 1084 1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1086 jcc(Assembler::below, no_reserved_zone_enabling); 1087 1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1090 should_not_reach_here(); 1091 1092 bind(no_reserved_zone_enabling); 1093 } 1094 1095 int MacroAssembler::biased_locking_enter(Register lock_reg, 1096 Register obj_reg, 1097 Register swap_reg, 1098 Register tmp_reg, 1099 bool swap_reg_contains_mark, 1100 Label& done, 1101 Label* slow_case, 1102 BiasedLockingCounters* counters) { 1103 assert(UseBiasedLocking, "why call this otherwise?"); 1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1105 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1110 1111 if (PrintBiasedLockingStatistics && counters == NULL) { 1112 counters = BiasedLocking::counters(); 1113 } 1114 // Biased locking 1115 // See whether the lock is currently biased toward our thread and 1116 // whether the epoch is still valid 1117 // Note that the runtime guarantees sufficient alignment of JavaThread 1118 // pointers to allow age to be placed into low bits 1119 // First check to see whether biasing is even enabled for this object 1120 Label cas_label; 1121 int null_check_offset = -1; 1122 if (!swap_reg_contains_mark) { 1123 null_check_offset = offset(); 1124 movptr(swap_reg, mark_addr); 1125 } 1126 movptr(tmp_reg, swap_reg); 1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1129 jcc(Assembler::notEqual, cas_label); 1130 // The bias pattern is present in the object's header. Need to check 1131 // whether the bias owner and the epoch are both still current. 1132 #ifndef _LP64 1133 // Note that because there is no current thread register on x86_32 we 1134 // need to store off the mark word we read out of the object to 1135 // avoid reloading it and needing to recheck invariants below. This 1136 // store is unfortunate but it makes the overall code shorter and 1137 // simpler. 1138 movptr(saved_mark_addr, swap_reg); 1139 #endif 1140 if (swap_reg_contains_mark) { 1141 null_check_offset = offset(); 1142 } 1143 load_prototype_header(tmp_reg, obj_reg); 1144 #ifdef _LP64 1145 orptr(tmp_reg, r15_thread); 1146 xorptr(tmp_reg, swap_reg); 1147 Register header_reg = tmp_reg; 1148 #else 1149 xorptr(tmp_reg, swap_reg); 1150 get_thread(swap_reg); 1151 xorptr(swap_reg, tmp_reg); 1152 Register header_reg = swap_reg; 1153 #endif 1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1155 if (counters != NULL) { 1156 cond_inc32(Assembler::zero, 1157 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1158 } 1159 jcc(Assembler::equal, done); 1160 1161 Label try_revoke_bias; 1162 Label try_rebias; 1163 1164 // At this point we know that the header has the bias pattern and 1165 // that we are not the bias owner in the current epoch. We need to 1166 // figure out more details about the state of the header in order to 1167 // know what operations can be legally performed on the object's 1168 // header. 1169 1170 // If the low three bits in the xor result aren't clear, that means 1171 // the prototype header is no longer biased and we have to revoke 1172 // the bias on this object. 1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1174 jccb(Assembler::notZero, try_revoke_bias); 1175 1176 // Biasing is still enabled for this data type. See whether the 1177 // epoch of the current bias is still valid, meaning that the epoch 1178 // bits of the mark word are equal to the epoch bits of the 1179 // prototype header. (Note that the prototype header's epoch bits 1180 // only change at a safepoint.) If not, attempt to rebias the object 1181 // toward the current thread. Note that we must be absolutely sure 1182 // that the current epoch is invalid in order to do this because 1183 // otherwise the manipulations it performs on the mark word are 1184 // illegal. 1185 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1186 jccb(Assembler::notZero, try_rebias); 1187 1188 // The epoch of the current bias is still valid but we know nothing 1189 // about the owner; it might be set or it might be clear. Try to 1190 // acquire the bias of the object using an atomic operation. If this 1191 // fails we will go in to the runtime to revoke the object's bias. 1192 // Note that we first construct the presumed unbiased header so we 1193 // don't accidentally blow away another thread's valid bias. 1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1195 andptr(swap_reg, 1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1197 #ifdef _LP64 1198 movptr(tmp_reg, swap_reg); 1199 orptr(tmp_reg, r15_thread); 1200 #else 1201 get_thread(tmp_reg); 1202 orptr(tmp_reg, swap_reg); 1203 #endif 1204 if (os::is_MP()) { 1205 lock(); 1206 } 1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1208 // If the biasing toward our thread failed, this means that 1209 // another thread succeeded in biasing it toward itself and we 1210 // need to revoke that bias. The revocation will occur in the 1211 // interpreter runtime in the slow case. 1212 if (counters != NULL) { 1213 cond_inc32(Assembler::zero, 1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1215 } 1216 if (slow_case != NULL) { 1217 jcc(Assembler::notZero, *slow_case); 1218 } 1219 jmp(done); 1220 1221 bind(try_rebias); 1222 // At this point we know the epoch has expired, meaning that the 1223 // current "bias owner", if any, is actually invalid. Under these 1224 // circumstances _only_, we are allowed to use the current header's 1225 // value as the comparison value when doing the cas to acquire the 1226 // bias in the current epoch. In other words, we allow transfer of 1227 // the bias from one thread to another directly in this situation. 1228 // 1229 // FIXME: due to a lack of registers we currently blow away the age 1230 // bits in this situation. Should attempt to preserve them. 1231 load_prototype_header(tmp_reg, obj_reg); 1232 #ifdef _LP64 1233 orptr(tmp_reg, r15_thread); 1234 #else 1235 get_thread(swap_reg); 1236 orptr(tmp_reg, swap_reg); 1237 movptr(swap_reg, saved_mark_addr); 1238 #endif 1239 if (os::is_MP()) { 1240 lock(); 1241 } 1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1243 // If the biasing toward our thread failed, then another thread 1244 // succeeded in biasing it toward itself and we need to revoke that 1245 // bias. The revocation will occur in the runtime in the slow case. 1246 if (counters != NULL) { 1247 cond_inc32(Assembler::zero, 1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1249 } 1250 if (slow_case != NULL) { 1251 jcc(Assembler::notZero, *slow_case); 1252 } 1253 jmp(done); 1254 1255 bind(try_revoke_bias); 1256 // The prototype mark in the klass doesn't have the bias bit set any 1257 // more, indicating that objects of this data type are not supposed 1258 // to be biased any more. We are going to try to reset the mark of 1259 // this object to the prototype value and fall through to the 1260 // CAS-based locking scheme. Note that if our CAS fails, it means 1261 // that another thread raced us for the privilege of revoking the 1262 // bias of this particular object, so it's okay to continue in the 1263 // normal locking code. 1264 // 1265 // FIXME: due to a lack of registers we currently blow away the age 1266 // bits in this situation. Should attempt to preserve them. 1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1268 load_prototype_header(tmp_reg, obj_reg); 1269 if (os::is_MP()) { 1270 lock(); 1271 } 1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1273 // Fall through to the normal CAS-based lock, because no matter what 1274 // the result of the above CAS, some thread must have succeeded in 1275 // removing the bias bit from the object's header. 1276 if (counters != NULL) { 1277 cond_inc32(Assembler::zero, 1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1279 } 1280 1281 bind(cas_label); 1282 1283 return null_check_offset; 1284 } 1285 1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1287 assert(UseBiasedLocking, "why call this otherwise?"); 1288 1289 // Check for biased locking unlock case, which is a no-op 1290 // Note: we do not have to check the thread ID for two reasons. 1291 // First, the interpreter checks for IllegalMonitorStateException at 1292 // a higher level. Second, if the bias was revoked while we held the 1293 // lock, the object could not be rebiased toward another thread, so 1294 // the bias bit would be clear. 1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1298 jcc(Assembler::equal, done); 1299 } 1300 1301 #ifdef COMPILER2 1302 1303 #if INCLUDE_RTM_OPT 1304 1305 // Update rtm_counters based on abort status 1306 // input: abort_status 1307 // rtm_counters (RTMLockingCounters*) 1308 // flags are killed 1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1310 1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1312 if (PrintPreciseRTMLockingStatistics) { 1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1314 Label check_abort; 1315 testl(abort_status, (1<<i)); 1316 jccb(Assembler::equal, check_abort); 1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1318 bind(check_abort); 1319 } 1320 } 1321 } 1322 1323 // Branch if (random & (count-1) != 0), count is 2^n 1324 // tmp, scr and flags are killed 1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1326 assert(tmp == rax, ""); 1327 assert(scr == rdx, ""); 1328 rdtsc(); // modifies EDX:EAX 1329 andptr(tmp, count-1); 1330 jccb(Assembler::notZero, brLabel); 1331 } 1332 1333 // Perform abort ratio calculation, set no_rtm bit if high ratio 1334 // input: rtm_counters_Reg (RTMLockingCounters* address) 1335 // tmpReg, rtm_counters_Reg and flags are killed 1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1337 Register rtm_counters_Reg, 1338 RTMLockingCounters* rtm_counters, 1339 Metadata* method_data) { 1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1341 1342 if (RTMLockingCalculationDelay > 0) { 1343 // Delay calculation 1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1345 testptr(tmpReg, tmpReg); 1346 jccb(Assembler::equal, L_done); 1347 } 1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1349 // Aborted transactions = abort_count * 100 1350 // All transactions = total_count * RTMTotalCountIncrRate 1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1352 1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1354 cmpptr(tmpReg, RTMAbortThreshold); 1355 jccb(Assembler::below, L_check_always_rtm2); 1356 imulptr(tmpReg, tmpReg, 100); 1357 1358 Register scrReg = rtm_counters_Reg; 1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1361 imulptr(scrReg, scrReg, RTMAbortRatio); 1362 cmpptr(tmpReg, scrReg); 1363 jccb(Assembler::below, L_check_always_rtm1); 1364 if (method_data != NULL) { 1365 // set rtm_state to "no rtm" in MDO 1366 mov_metadata(tmpReg, method_data); 1367 if (os::is_MP()) { 1368 lock(); 1369 } 1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1371 } 1372 jmpb(L_done); 1373 bind(L_check_always_rtm1); 1374 // Reload RTMLockingCounters* address 1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1376 bind(L_check_always_rtm2); 1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1379 jccb(Assembler::below, L_done); 1380 if (method_data != NULL) { 1381 // set rtm_state to "always rtm" in MDO 1382 mov_metadata(tmpReg, method_data); 1383 if (os::is_MP()) { 1384 lock(); 1385 } 1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1387 } 1388 bind(L_done); 1389 } 1390 1391 // Update counters and perform abort ratio calculation 1392 // input: abort_status_Reg 1393 // rtm_counters_Reg, flags are killed 1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1395 Register rtm_counters_Reg, 1396 RTMLockingCounters* rtm_counters, 1397 Metadata* method_data, 1398 bool profile_rtm) { 1399 1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1401 // update rtm counters based on rax value at abort 1402 // reads abort_status_Reg, updates flags 1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1405 if (profile_rtm) { 1406 // Save abort status because abort_status_Reg is used by following code. 1407 if (RTMRetryCount > 0) { 1408 push(abort_status_Reg); 1409 } 1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1412 // restore abort status 1413 if (RTMRetryCount > 0) { 1414 pop(abort_status_Reg); 1415 } 1416 } 1417 } 1418 1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1420 // inputs: retry_count_Reg 1421 // : abort_status_Reg 1422 // output: retry_count_Reg decremented by 1 1423 // flags are killed 1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1425 Label doneRetry; 1426 assert(abort_status_Reg == rax, ""); 1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1429 // if reason is in 0x6 and retry count != 0 then retry 1430 andptr(abort_status_Reg, 0x6); 1431 jccb(Assembler::zero, doneRetry); 1432 testl(retry_count_Reg, retry_count_Reg); 1433 jccb(Assembler::zero, doneRetry); 1434 pause(); 1435 decrementl(retry_count_Reg); 1436 jmp(retryLabel); 1437 bind(doneRetry); 1438 } 1439 1440 // Spin and retry if lock is busy, 1441 // inputs: box_Reg (monitor address) 1442 // : retry_count_Reg 1443 // output: retry_count_Reg decremented by 1 1444 // : clear z flag if retry count exceeded 1445 // tmp_Reg, scr_Reg, flags are killed 1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1448 Label SpinLoop, SpinExit, doneRetry; 1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1450 1451 testl(retry_count_Reg, retry_count_Reg); 1452 jccb(Assembler::zero, doneRetry); 1453 decrementl(retry_count_Reg); 1454 movptr(scr_Reg, RTMSpinLoopCount); 1455 1456 bind(SpinLoop); 1457 pause(); 1458 decrementl(scr_Reg); 1459 jccb(Assembler::lessEqual, SpinExit); 1460 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1461 testptr(tmp_Reg, tmp_Reg); 1462 jccb(Assembler::notZero, SpinLoop); 1463 1464 bind(SpinExit); 1465 jmp(retryLabel); 1466 bind(doneRetry); 1467 incrementl(retry_count_Reg); // clear z flag 1468 } 1469 1470 // Use RTM for normal stack locks 1471 // Input: objReg (object to lock) 1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1473 Register retry_on_abort_count_Reg, 1474 RTMLockingCounters* stack_rtm_counters, 1475 Metadata* method_data, bool profile_rtm, 1476 Label& DONE_LABEL, Label& IsInflated) { 1477 assert(UseRTMForStackLocks, "why call this otherwise?"); 1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1479 assert(tmpReg == rax, ""); 1480 assert(scrReg == rdx, ""); 1481 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1482 1483 if (RTMRetryCount > 0) { 1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1485 bind(L_rtm_retry); 1486 } 1487 movptr(tmpReg, Address(objReg, 0)); 1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1489 jcc(Assembler::notZero, IsInflated); 1490 1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1492 Label L_noincrement; 1493 if (RTMTotalCountIncrRate > 1) { 1494 // tmpReg, scrReg and flags are killed 1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1496 } 1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1499 bind(L_noincrement); 1500 } 1501 xbegin(L_on_abort); 1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1506 1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1508 if (UseRTMXendForLockBusy) { 1509 xend(); 1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1511 jmp(L_decrement_retry); 1512 } 1513 else { 1514 xabort(0); 1515 } 1516 bind(L_on_abort); 1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1519 } 1520 bind(L_decrement_retry); 1521 if (RTMRetryCount > 0) { 1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1524 } 1525 } 1526 1527 // Use RTM for inflating locks 1528 // inputs: objReg (object to lock) 1529 // boxReg (on-stack box address (displaced header location) - KILLED) 1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1532 Register scrReg, Register retry_on_busy_count_Reg, 1533 Register retry_on_abort_count_Reg, 1534 RTMLockingCounters* rtm_counters, 1535 Metadata* method_data, bool profile_rtm, 1536 Label& DONE_LABEL) { 1537 assert(UseRTMLocking, "why call this otherwise?"); 1538 assert(tmpReg == rax, ""); 1539 assert(scrReg == rdx, ""); 1540 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1542 1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1546 1547 if (RTMRetryCount > 0) { 1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1550 bind(L_rtm_retry); 1551 } 1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1553 Label L_noincrement; 1554 if (RTMTotalCountIncrRate > 1) { 1555 // tmpReg, scrReg and flags are killed 1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1557 } 1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1560 bind(L_noincrement); 1561 } 1562 xbegin(L_on_abort); 1563 movptr(tmpReg, Address(objReg, 0)); 1564 movptr(tmpReg, Address(tmpReg, owner_offset)); 1565 testptr(tmpReg, tmpReg); 1566 jcc(Assembler::zero, DONE_LABEL); 1567 if (UseRTMXendForLockBusy) { 1568 xend(); 1569 jmp(L_decrement_retry); 1570 } 1571 else { 1572 xabort(0); 1573 } 1574 bind(L_on_abort); 1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1578 } 1579 if (RTMRetryCount > 0) { 1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1582 } 1583 1584 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1585 testptr(tmpReg, tmpReg) ; 1586 jccb(Assembler::notZero, L_decrement_retry) ; 1587 1588 // Appears unlocked - try to swing _owner from null to non-null. 1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1590 #ifdef _LP64 1591 Register threadReg = r15_thread; 1592 #else 1593 get_thread(scrReg); 1594 Register threadReg = scrReg; 1595 #endif 1596 if (os::is_MP()) { 1597 lock(); 1598 } 1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1600 1601 if (RTMRetryCount > 0) { 1602 // success done else retry 1603 jccb(Assembler::equal, DONE_LABEL) ; 1604 bind(L_decrement_retry); 1605 // Spin and retry if lock is busy. 1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1607 } 1608 else { 1609 bind(L_decrement_retry); 1610 } 1611 } 1612 1613 #endif // INCLUDE_RTM_OPT 1614 1615 // Fast_Lock and Fast_Unlock used by C2 1616 1617 // Because the transitions from emitted code to the runtime 1618 // monitorenter/exit helper stubs are so slow it's critical that 1619 // we inline both the stack-locking fast-path and the inflated fast path. 1620 // 1621 // See also: cmpFastLock and cmpFastUnlock. 1622 // 1623 // What follows is a specialized inline transliteration of the code 1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1625 // another option would be to emit TrySlowEnter and TrySlowExit methods 1626 // at startup-time. These methods would accept arguments as 1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1630 // In practice, however, the # of lock sites is bounded and is usually small. 1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1632 // if the processor uses simple bimodal branch predictors keyed by EIP 1633 // Since the helper routines would be called from multiple synchronization 1634 // sites. 1635 // 1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1638 // to those specialized methods. That'd give us a mostly platform-independent 1639 // implementation that the JITs could optimize and inline at their pleasure. 1640 // Done correctly, the only time we'd need to cross to native could would be 1641 // to park() or unpark() threads. We'd also need a few more unsafe operators 1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1643 // (b) explicit barriers or fence operations. 1644 // 1645 // TODO: 1646 // 1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1650 // the lock operators would typically be faster than reifying Self. 1651 // 1652 // * Ideally I'd define the primitives as: 1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1656 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1657 // Furthermore the register assignments are overconstrained, possibly resulting in 1658 // sub-optimal code near the synchronization site. 1659 // 1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1661 // Alternately, use a better sp-proximity test. 1662 // 1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1664 // Either one is sufficient to uniquely identify a thread. 1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1666 // 1667 // * Intrinsify notify() and notifyAll() for the common cases where the 1668 // object is locked by the calling thread but the waitlist is empty. 1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1670 // 1671 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1672 // But beware of excessive branch density on AMD Opterons. 1673 // 1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1675 // or failure of the fast-path. If the fast-path fails then we pass 1676 // control to the slow-path, typically in C. In Fast_Lock and 1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1678 // will emit a conditional branch immediately after the node. 1679 // So we have branches to branches and lots of ICC.ZF games. 1680 // Instead, it might be better to have C2 pass a "FailureLabel" 1681 // into Fast_Lock and Fast_Unlock. In the case of success, control 1682 // will drop through the node. ICC.ZF is undefined at exit. 1683 // In the case of failure, the node will branch directly to the 1684 // FailureLabel 1685 1686 1687 // obj: object to lock 1688 // box: on-stack box address (displaced header location) - KILLED 1689 // rax,: tmp -- KILLED 1690 // scr: tmp -- KILLED 1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1692 Register scrReg, Register cx1Reg, Register cx2Reg, 1693 BiasedLockingCounters* counters, 1694 RTMLockingCounters* rtm_counters, 1695 RTMLockingCounters* stack_rtm_counters, 1696 Metadata* method_data, 1697 bool use_rtm, bool profile_rtm) { 1698 // Ensure the register assignments are disjoint 1699 assert(tmpReg == rax, ""); 1700 1701 if (use_rtm) { 1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1703 } else { 1704 assert(cx1Reg == noreg, ""); 1705 assert(cx2Reg == noreg, ""); 1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1707 } 1708 1709 if (counters != NULL) { 1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1711 } 1712 if (EmitSync & 1) { 1713 // set box->dhw = markOopDesc::unused_mark() 1714 // Force all sync thru slow-path: slow_enter() and slow_exit() 1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1716 cmpptr (rsp, (int32_t)NULL_WORD); 1717 } else { 1718 // Possible cases that we'll encounter in fast_lock 1719 // ------------------------------------------------ 1720 // * Inflated 1721 // -- unlocked 1722 // -- Locked 1723 // = by self 1724 // = by other 1725 // * biased 1726 // -- by Self 1727 // -- by other 1728 // * neutral 1729 // * stack-locked 1730 // -- by self 1731 // = sp-proximity test hits 1732 // = sp-proximity test generates false-negative 1733 // -- by other 1734 // 1735 1736 Label IsInflated, DONE_LABEL; 1737 1738 // it's stack-locked, biased or neutral 1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1740 // order to reduce the number of conditional branches in the most common cases. 1741 // Beware -- there's a subtle invariant that fetch of the markword 1742 // at [FETCH], below, will never observe a biased encoding (*101b). 1743 // If this invariant is not held we risk exclusion (safety) failure. 1744 if (UseBiasedLocking && !UseOptoBiasInlining) { 1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1746 } 1747 1748 #if INCLUDE_RTM_OPT 1749 if (UseRTMForStackLocks && use_rtm) { 1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1751 stack_rtm_counters, method_data, profile_rtm, 1752 DONE_LABEL, IsInflated); 1753 } 1754 #endif // INCLUDE_RTM_OPT 1755 1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1758 jccb(Assembler::notZero, IsInflated); 1759 1760 // Attempt stack-locking ... 1761 orptr (tmpReg, markOopDesc::unlocked_value); 1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1763 if (os::is_MP()) { 1764 lock(); 1765 } 1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1767 if (counters != NULL) { 1768 cond_inc32(Assembler::equal, 1769 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1770 } 1771 jcc(Assembler::equal, DONE_LABEL); // Success 1772 1773 // Recursive locking. 1774 // The object is stack-locked: markword contains stack pointer to BasicLock. 1775 // Locked by current thread if difference with current SP is less than one page. 1776 subptr(tmpReg, rsp); 1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1779 movptr(Address(boxReg, 0), tmpReg); 1780 if (counters != NULL) { 1781 cond_inc32(Assembler::equal, 1782 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1783 } 1784 jmp(DONE_LABEL); 1785 1786 bind(IsInflated); 1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1788 1789 #if INCLUDE_RTM_OPT 1790 // Use the same RTM locking code in 32- and 64-bit VM. 1791 if (use_rtm) { 1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1793 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1794 } else { 1795 #endif // INCLUDE_RTM_OPT 1796 1797 #ifndef _LP64 1798 // The object is inflated. 1799 1800 // boxReg refers to the on-stack BasicLock in the current frame. 1801 // We'd like to write: 1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1804 // additional latency as we have another ST in the store buffer that must drain. 1805 1806 if (EmitSync & 8192) { 1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1808 get_thread (scrReg); 1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1811 if (os::is_MP()) { 1812 lock(); 1813 } 1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1815 } else 1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1817 // register juggle because we need tmpReg for cmpxchgptr below 1818 movptr(scrReg, boxReg); 1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1820 1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1823 // prefetchw [eax + Offset(_owner)-2] 1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1825 } 1826 1827 if ((EmitSync & 64) == 0) { 1828 // Optimistic form: consider XORL tmpReg,tmpReg 1829 movptr(tmpReg, NULL_WORD); 1830 } else { 1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1832 // Test-And-CAS instead of CAS 1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1834 testptr(tmpReg, tmpReg); // Locked ? 1835 jccb (Assembler::notZero, DONE_LABEL); 1836 } 1837 1838 // Appears unlocked - try to swing _owner from null to non-null. 1839 // Ideally, I'd manifest "Self" with get_thread and then attempt 1840 // to CAS the register containing Self into m->Owner. 1841 // But we don't have enough registers, so instead we can either try to CAS 1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1843 // we later store "Self" into m->Owner. Transiently storing a stack address 1844 // (rsp or the address of the box) into m->owner is harmless. 1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1846 if (os::is_MP()) { 1847 lock(); 1848 } 1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1851 // If we weren't able to swing _owner from NULL to the BasicLock 1852 // then take the slow path. 1853 jccb (Assembler::notZero, DONE_LABEL); 1854 // update _owner from BasicLock to thread 1855 get_thread (scrReg); // beware: clobbers ICCs 1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1858 1859 // If the CAS fails we can either retry or pass control to the slow-path. 1860 // We use the latter tactic. 1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1862 // If the CAS was successful ... 1863 // Self has acquired the lock 1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1865 // Intentional fall-through into DONE_LABEL ... 1866 } else { 1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1868 movptr(boxReg, tmpReg); 1869 1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1872 // prefetchw [eax + Offset(_owner)-2] 1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1874 } 1875 1876 if ((EmitSync & 64) == 0) { 1877 // Optimistic form 1878 xorptr (tmpReg, tmpReg); 1879 } else { 1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1882 testptr(tmpReg, tmpReg); // Locked ? 1883 jccb (Assembler::notZero, DONE_LABEL); 1884 } 1885 1886 // Appears unlocked - try to swing _owner from null to non-null. 1887 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1889 get_thread (scrReg); 1890 if (os::is_MP()) { 1891 lock(); 1892 } 1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1894 1895 // If the CAS fails we can either retry or pass control to the slow-path. 1896 // We use the latter tactic. 1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1898 // If the CAS was successful ... 1899 // Self has acquired the lock 1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1901 // Intentional fall-through into DONE_LABEL ... 1902 } 1903 #else // _LP64 1904 // It's inflated 1905 movq(scrReg, tmpReg); 1906 xorq(tmpReg, tmpReg); 1907 1908 if (os::is_MP()) { 1909 lock(); 1910 } 1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1913 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1915 // Intentional fall-through into DONE_LABEL ... 1916 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1917 #endif // _LP64 1918 #if INCLUDE_RTM_OPT 1919 } // use_rtm() 1920 #endif 1921 // DONE_LABEL is a hot target - we'd really like to place it at the 1922 // start of cache line by padding with NOPs. 1923 // See the AMD and Intel software optimization manuals for the 1924 // most efficient "long" NOP encodings. 1925 // Unfortunately none of our alignment mechanisms suffice. 1926 bind(DONE_LABEL); 1927 1928 // At DONE_LABEL the icc ZFlag is set as follows ... 1929 // Fast_Unlock uses the same protocol. 1930 // ZFlag == 1 -> Success 1931 // ZFlag == 0 -> Failure - force control through the slow-path 1932 } 1933 } 1934 1935 // obj: object to unlock 1936 // box: box address (displaced header location), killed. Must be EAX. 1937 // tmp: killed, cannot be obj nor box. 1938 // 1939 // Some commentary on balanced locking: 1940 // 1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1942 // Methods that don't have provably balanced locking are forced to run in the 1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1944 // The interpreter provides two properties: 1945 // I1: At return-time the interpreter automatically and quietly unlocks any 1946 // objects acquired the current activation (frame). Recall that the 1947 // interpreter maintains an on-stack list of locks currently held by 1948 // a frame. 1949 // I2: If a method attempts to unlock an object that is not held by the 1950 // the frame the interpreter throws IMSX. 1951 // 1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1953 // B() doesn't have provably balanced locking so it runs in the interpreter. 1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1955 // is still locked by A(). 1956 // 1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1961 // Arguably given that the spec legislates the JNI case as undefined our implementation 1962 // could reasonably *avoid* checking owner in Fast_Unlock(). 1963 // In the interest of performance we elide m->Owner==Self check in unlock. 1964 // A perfectly viable alternative is to elide the owner check except when 1965 // Xcheck:jni is enabled. 1966 1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1968 assert(boxReg == rax, ""); 1969 assert_different_registers(objReg, boxReg, tmpReg); 1970 1971 if (EmitSync & 4) { 1972 // Disable - inhibit all inlining. Force control through the slow-path 1973 cmpptr (rsp, 0); 1974 } else { 1975 Label DONE_LABEL, Stacked, CheckSucc; 1976 1977 // Critically, the biased locking test must have precedence over 1978 // and appear before the (box->dhw == 0) recursive stack-lock test. 1979 if (UseBiasedLocking && !UseOptoBiasInlining) { 1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1981 } 1982 1983 #if INCLUDE_RTM_OPT 1984 if (UseRTMForStackLocks && use_rtm) { 1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1986 Label L_regular_unlock; 1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1991 xend(); // otherwise end... 1992 jmp(DONE_LABEL); // ... and we're done 1993 bind(L_regular_unlock); 1994 } 1995 #endif 1996 1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 2001 jccb (Assembler::zero, Stacked); 2002 2003 // It's inflated. 2004 #if INCLUDE_RTM_OPT 2005 if (use_rtm) { 2006 Label L_regular_inflated_unlock; 2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2008 movptr(boxReg, Address(tmpReg, owner_offset)); 2009 testptr(boxReg, boxReg); 2010 jccb(Assembler::notZero, L_regular_inflated_unlock); 2011 xend(); 2012 jmpb(DONE_LABEL); 2013 bind(L_regular_inflated_unlock); 2014 } 2015 #endif 2016 2017 // Despite our balanced locking property we still check that m->_owner == Self 2018 // as java routines or native JNI code called by this thread might 2019 // have released the lock. 2020 // Refer to the comments in synchronizer.cpp for how we might encode extra 2021 // state in _succ so we can avoid fetching EntryList|cxq. 2022 // 2023 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2024 // such as recursive enter and exit -- but we have to be wary of 2025 // I$ bloat, T$ effects and BP$ effects. 2026 // 2027 // If there's no contention try a 1-0 exit. That is, exit without 2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2029 // we detect and recover from the race that the 1-0 exit admits. 2030 // 2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2032 // before it STs null into _owner, releasing the lock. Updates 2033 // to data protected by the critical section must be visible before 2034 // we drop the lock (and thus before any other thread could acquire 2035 // the lock and observe the fields protected by the lock). 2036 // IA32's memory-model is SPO, so STs are ordered with respect to 2037 // each other and there's no need for an explicit barrier (fence). 2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2039 #ifndef _LP64 2040 get_thread (boxReg); 2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2042 // prefetchw [ebx + Offset(_owner)-2] 2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2044 } 2045 2046 // Note that we could employ various encoding schemes to reduce 2047 // the number of loads below (currently 4) to just 2 or 3. 2048 // Refer to the comments in synchronizer.cpp. 2049 // In practice the chain of fetches doesn't seem to impact performance, however. 2050 xorptr(boxReg, boxReg); 2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2052 // Attempt to reduce branch density - AMD's branch predictor. 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2056 jccb (Assembler::notZero, DONE_LABEL); 2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2058 jmpb (DONE_LABEL); 2059 } else { 2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2061 jccb (Assembler::notZero, DONE_LABEL); 2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2064 jccb (Assembler::notZero, CheckSucc); 2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2066 jmpb (DONE_LABEL); 2067 } 2068 2069 // The Following code fragment (EmitSync & 65536) improves the performance of 2070 // contended applications and contended synchronization microbenchmarks. 2071 // Unfortunately the emission of the code - even though not executed - causes regressions 2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2073 // with an equal number of never-executed NOPs results in the same regression. 2074 // We leave it off by default. 2075 2076 if ((EmitSync & 65536) != 0) { 2077 Label LSuccess, LGoSlowPath ; 2078 2079 bind (CheckSucc); 2080 2081 // Optional pre-test ... it's safe to elide this 2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2083 jccb(Assembler::zero, LGoSlowPath); 2084 2085 // We have a classic Dekker-style idiom: 2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2087 // There are a number of ways to implement the barrier: 2088 // (1) lock:andl &m->_owner, 0 2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2092 // (2) If supported, an explicit MFENCE is appealing. 2093 // In older IA32 processors MFENCE is slower than lock:add or xchg 2094 // particularly if the write-buffer is full as might be the case if 2095 // if stores closely precede the fence or fence-equivalent instruction. 2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2097 // as the situation has changed with Nehalem and Shanghai. 2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2099 // The $lines underlying the top-of-stack should be in M-state. 2100 // The locked add instruction is serializing, of course. 2101 // (4) Use xchg, which is serializing 2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2104 // The integer condition codes will tell us if succ was 0. 2105 // Since _succ and _owner should reside in the same $line and 2106 // we just stored into _owner, it's likely that the $line 2107 // remains in M-state for the lock:orl. 2108 // 2109 // We currently use (3), although it's likely that switching to (2) 2110 // is correct for the future. 2111 2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2113 if (os::is_MP()) { 2114 lock(); addptr(Address(rsp, 0), 0); 2115 } 2116 // Ratify _succ remains non-null 2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2118 jccb (Assembler::notZero, LSuccess); 2119 2120 xorptr(boxReg, boxReg); // box is really EAX 2121 if (os::is_MP()) { lock(); } 2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2123 // There's no successor so we tried to regrab the lock with the 2124 // placeholder value. If that didn't work, then another thread 2125 // grabbed the lock so we're done (and exit was a success). 2126 jccb (Assembler::notEqual, LSuccess); 2127 // Since we're low on registers we installed rsp as a placeholding in _owner. 2128 // Now install Self over rsp. This is safe as we're transitioning from 2129 // non-null to non=null 2130 get_thread (boxReg); 2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2132 // Intentional fall-through into LGoSlowPath ... 2133 2134 bind (LGoSlowPath); 2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2136 jmpb (DONE_LABEL); 2137 2138 bind (LSuccess); 2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2140 jmpb (DONE_LABEL); 2141 } 2142 2143 bind (Stacked); 2144 // It's not inflated and it's not recursively stack-locked and it's not biased. 2145 // It must be stack-locked. 2146 // Try to reset the header to displaced header. 2147 // The "box" value on the stack is stable, so we can reload 2148 // and be assured we observe the same value as above. 2149 movptr(tmpReg, Address(boxReg, 0)); 2150 if (os::is_MP()) { 2151 lock(); 2152 } 2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2154 // Intention fall-thru into DONE_LABEL 2155 2156 // DONE_LABEL is a hot target - we'd really like to place it at the 2157 // start of cache line by padding with NOPs. 2158 // See the AMD and Intel software optimization manuals for the 2159 // most efficient "long" NOP encodings. 2160 // Unfortunately none of our alignment mechanisms suffice. 2161 if ((EmitSync & 65536) == 0) { 2162 bind (CheckSucc); 2163 } 2164 #else // _LP64 2165 // It's inflated 2166 if (EmitSync & 1024) { 2167 // Emit code to check that _owner == Self 2168 // We could fold the _owner test into subsequent code more efficiently 2169 // than using a stand-alone check, but since _owner checking is off by 2170 // default we don't bother. We also might consider predicating the 2171 // _owner==Self check on Xcheck:jni or running on a debug build. 2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2173 xorptr(boxReg, r15_thread); 2174 } else { 2175 xorptr(boxReg, boxReg); 2176 } 2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2178 jccb (Assembler::notZero, DONE_LABEL); 2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2181 jccb (Assembler::notZero, CheckSucc); 2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2183 jmpb (DONE_LABEL); 2184 2185 if ((EmitSync & 65536) == 0) { 2186 // Try to avoid passing control into the slow_path ... 2187 Label LSuccess, LGoSlowPath ; 2188 bind (CheckSucc); 2189 2190 // The following optional optimization can be elided if necessary 2191 // Effectively: if (succ == null) goto SlowPath 2192 // The code reduces the window for a race, however, 2193 // and thus benefits performance. 2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2195 jccb (Assembler::zero, LGoSlowPath); 2196 2197 xorptr(boxReg, boxReg); 2198 if ((EmitSync & 16) && os::is_MP()) { 2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2200 } else { 2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2202 if (os::is_MP()) { 2203 // Memory barrier/fence 2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2206 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2210 lock(); addl(Address(rsp, 0), 0); 2211 } 2212 } 2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2214 jccb (Assembler::notZero, LSuccess); 2215 2216 // Rare inopportune interleaving - race. 2217 // The successor vanished in the small window above. 2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2219 // We need to ensure progress and succession. 2220 // Try to reacquire the lock. 2221 // If that fails then the new owner is responsible for succession and this 2222 // thread needs to take no further action and can exit via the fast path (success). 2223 // If the re-acquire succeeds then pass control into the slow path. 2224 // As implemented, this latter mode is horrible because we generated more 2225 // coherence traffic on the lock *and* artifically extended the critical section 2226 // length while by virtue of passing control into the slow path. 2227 2228 // box is really RAX -- the following CMPXCHG depends on that binding 2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2230 if (os::is_MP()) { lock(); } 2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2232 // There's no successor so we tried to regrab the lock. 2233 // If that didn't work, then another thread grabbed the 2234 // lock so we're done (and exit was a success). 2235 jccb (Assembler::notEqual, LSuccess); 2236 // Intentional fall-through into slow-path 2237 2238 bind (LGoSlowPath); 2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2240 jmpb (DONE_LABEL); 2241 2242 bind (LSuccess); 2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2244 jmpb (DONE_LABEL); 2245 } 2246 2247 bind (Stacked); 2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2249 if (os::is_MP()) { lock(); } 2250 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2251 2252 if (EmitSync & 65536) { 2253 bind (CheckSucc); 2254 } 2255 #endif 2256 bind(DONE_LABEL); 2257 } 2258 } 2259 #endif // COMPILER2 2260 2261 void MacroAssembler::c2bool(Register x) { 2262 // implements x == 0 ? 0 : 1 2263 // note: must only look at least-significant byte of x 2264 // since C-style booleans are stored in one byte 2265 // only! (was bug) 2266 andl(x, 0xFF); 2267 setb(Assembler::notZero, x); 2268 } 2269 2270 // Wouldn't need if AddressLiteral version had new name 2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2272 Assembler::call(L, rtype); 2273 } 2274 2275 void MacroAssembler::call(Register entry) { 2276 Assembler::call(entry); 2277 } 2278 2279 void MacroAssembler::call(AddressLiteral entry) { 2280 if (reachable(entry)) { 2281 Assembler::call_literal(entry.target(), entry.rspec()); 2282 } else { 2283 lea(rscratch1, entry); 2284 Assembler::call(rscratch1); 2285 } 2286 } 2287 2288 void MacroAssembler::ic_call(address entry, jint method_index) { 2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2290 movptr(rax, (intptr_t)Universe::non_oop_word()); 2291 call(AddressLiteral(entry, rh)); 2292 } 2293 2294 // Implementation of call_VM versions 2295 2296 void MacroAssembler::call_VM(Register oop_result, 2297 address entry_point, 2298 bool check_exceptions) { 2299 Label C, E; 2300 call(C, relocInfo::none); 2301 jmp(E); 2302 2303 bind(C); 2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2305 ret(0); 2306 2307 bind(E); 2308 } 2309 2310 void MacroAssembler::call_VM(Register oop_result, 2311 address entry_point, 2312 Register arg_1, 2313 bool check_exceptions) { 2314 Label C, E; 2315 call(C, relocInfo::none); 2316 jmp(E); 2317 2318 bind(C); 2319 pass_arg1(this, arg_1); 2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2321 ret(0); 2322 2323 bind(E); 2324 } 2325 2326 void MacroAssembler::call_VM(Register oop_result, 2327 address entry_point, 2328 Register arg_1, 2329 Register arg_2, 2330 bool check_exceptions) { 2331 Label C, E; 2332 call(C, relocInfo::none); 2333 jmp(E); 2334 2335 bind(C); 2336 2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2338 2339 pass_arg2(this, arg_2); 2340 pass_arg1(this, arg_1); 2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2342 ret(0); 2343 2344 bind(E); 2345 } 2346 2347 void MacroAssembler::call_VM(Register oop_result, 2348 address entry_point, 2349 Register arg_1, 2350 Register arg_2, 2351 Register arg_3, 2352 bool check_exceptions) { 2353 Label C, E; 2354 call(C, relocInfo::none); 2355 jmp(E); 2356 2357 bind(C); 2358 2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2361 pass_arg3(this, arg_3); 2362 2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2364 pass_arg2(this, arg_2); 2365 2366 pass_arg1(this, arg_1); 2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2368 ret(0); 2369 2370 bind(E); 2371 } 2372 2373 void MacroAssembler::call_VM(Register oop_result, 2374 Register last_java_sp, 2375 address entry_point, 2376 int number_of_arguments, 2377 bool check_exceptions) { 2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2380 } 2381 2382 void MacroAssembler::call_VM(Register oop_result, 2383 Register last_java_sp, 2384 address entry_point, 2385 Register arg_1, 2386 bool check_exceptions) { 2387 pass_arg1(this, arg_1); 2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2389 } 2390 2391 void MacroAssembler::call_VM(Register oop_result, 2392 Register last_java_sp, 2393 address entry_point, 2394 Register arg_1, 2395 Register arg_2, 2396 bool check_exceptions) { 2397 2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2399 pass_arg2(this, arg_2); 2400 pass_arg1(this, arg_1); 2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2402 } 2403 2404 void MacroAssembler::call_VM(Register oop_result, 2405 Register last_java_sp, 2406 address entry_point, 2407 Register arg_1, 2408 Register arg_2, 2409 Register arg_3, 2410 bool check_exceptions) { 2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2413 pass_arg3(this, arg_3); 2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2415 pass_arg2(this, arg_2); 2416 pass_arg1(this, arg_1); 2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2418 } 2419 2420 void MacroAssembler::super_call_VM(Register oop_result, 2421 Register last_java_sp, 2422 address entry_point, 2423 int number_of_arguments, 2424 bool check_exceptions) { 2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2427 } 2428 2429 void MacroAssembler::super_call_VM(Register oop_result, 2430 Register last_java_sp, 2431 address entry_point, 2432 Register arg_1, 2433 bool check_exceptions) { 2434 pass_arg1(this, arg_1); 2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2436 } 2437 2438 void MacroAssembler::super_call_VM(Register oop_result, 2439 Register last_java_sp, 2440 address entry_point, 2441 Register arg_1, 2442 Register arg_2, 2443 bool check_exceptions) { 2444 2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2446 pass_arg2(this, arg_2); 2447 pass_arg1(this, arg_1); 2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2449 } 2450 2451 void MacroAssembler::super_call_VM(Register oop_result, 2452 Register last_java_sp, 2453 address entry_point, 2454 Register arg_1, 2455 Register arg_2, 2456 Register arg_3, 2457 bool check_exceptions) { 2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2460 pass_arg3(this, arg_3); 2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2462 pass_arg2(this, arg_2); 2463 pass_arg1(this, arg_1); 2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2465 } 2466 2467 void MacroAssembler::call_VM_base(Register oop_result, 2468 Register java_thread, 2469 Register last_java_sp, 2470 address entry_point, 2471 int number_of_arguments, 2472 bool check_exceptions) { 2473 // determine java_thread register 2474 if (!java_thread->is_valid()) { 2475 #ifdef _LP64 2476 java_thread = r15_thread; 2477 #else 2478 java_thread = rdi; 2479 get_thread(java_thread); 2480 #endif // LP64 2481 } 2482 // determine last_java_sp register 2483 if (!last_java_sp->is_valid()) { 2484 last_java_sp = rsp; 2485 } 2486 // debugging support 2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2489 #ifdef ASSERT 2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2491 // r12 is the heapbase. 2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2493 #endif // ASSERT 2494 2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2497 2498 // push java thread (becomes first argument of C function) 2499 2500 NOT_LP64(push(java_thread); number_of_arguments++); 2501 LP64_ONLY(mov(c_rarg0, r15_thread)); 2502 2503 // set last Java frame before call 2504 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2505 2506 // Only interpreter should have to set fp 2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2508 2509 // do the call, remove parameters 2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2511 2512 // restore the thread (cannot use the pushed argument since arguments 2513 // may be overwritten by C code generated by an optimizing compiler); 2514 // however can use the register value directly if it is callee saved. 2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2516 // rdi & rsi (also r15) are callee saved -> nothing to do 2517 #ifdef ASSERT 2518 guarantee(java_thread != rax, "change this code"); 2519 push(rax); 2520 { Label L; 2521 get_thread(rax); 2522 cmpptr(java_thread, rax); 2523 jcc(Assembler::equal, L); 2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2525 bind(L); 2526 } 2527 pop(rax); 2528 #endif 2529 } else { 2530 get_thread(java_thread); 2531 } 2532 // reset last Java frame 2533 // Only interpreter should have to clear fp 2534 reset_last_Java_frame(java_thread, true); 2535 2536 // C++ interp handles this in the interpreter 2537 check_and_handle_popframe(java_thread); 2538 check_and_handle_earlyret(java_thread); 2539 2540 if (check_exceptions) { 2541 // check for pending exceptions (java_thread is set upon return) 2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2543 #ifndef _LP64 2544 jump_cc(Assembler::notEqual, 2545 RuntimeAddress(StubRoutines::forward_exception_entry())); 2546 #else 2547 // This used to conditionally jump to forward_exception however it is 2548 // possible if we relocate that the branch will not reach. So we must jump 2549 // around so we can always reach 2550 2551 Label ok; 2552 jcc(Assembler::equal, ok); 2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2554 bind(ok); 2555 #endif // LP64 2556 } 2557 2558 // get oop result if there is one and reset the value in the thread 2559 if (oop_result->is_valid()) { 2560 get_vm_result(oop_result, java_thread); 2561 } 2562 } 2563 2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2565 2566 // Calculate the value for last_Java_sp 2567 // somewhat subtle. call_VM does an intermediate call 2568 // which places a return address on the stack just under the 2569 // stack pointer as the user finsihed with it. This allows 2570 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2571 // On 32bit we then have to push additional args on the stack to accomplish 2572 // the actual requested call. On 64bit call_VM only can use register args 2573 // so the only extra space is the return address that call_VM created. 2574 // This hopefully explains the calculations here. 2575 2576 #ifdef _LP64 2577 // We've pushed one address, correct last_Java_sp 2578 lea(rax, Address(rsp, wordSize)); 2579 #else 2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2581 #endif // LP64 2582 2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2584 2585 } 2586 2587 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2588 void MacroAssembler::call_VM_leaf0(address entry_point) { 2589 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2590 } 2591 2592 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2593 call_VM_leaf_base(entry_point, number_of_arguments); 2594 } 2595 2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2597 pass_arg0(this, arg_0); 2598 call_VM_leaf(entry_point, 1); 2599 } 2600 2601 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2602 2603 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2604 pass_arg1(this, arg_1); 2605 pass_arg0(this, arg_0); 2606 call_VM_leaf(entry_point, 2); 2607 } 2608 2609 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2610 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2611 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2612 pass_arg2(this, arg_2); 2613 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2614 pass_arg1(this, arg_1); 2615 pass_arg0(this, arg_0); 2616 call_VM_leaf(entry_point, 3); 2617 } 2618 2619 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2620 pass_arg0(this, arg_0); 2621 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2622 } 2623 2624 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2625 2626 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2627 pass_arg1(this, arg_1); 2628 pass_arg0(this, arg_0); 2629 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2630 } 2631 2632 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2633 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2634 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2635 pass_arg2(this, arg_2); 2636 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2637 pass_arg1(this, arg_1); 2638 pass_arg0(this, arg_0); 2639 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2640 } 2641 2642 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2643 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2644 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2645 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2646 pass_arg3(this, arg_3); 2647 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2648 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2649 pass_arg2(this, arg_2); 2650 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2651 pass_arg1(this, arg_1); 2652 pass_arg0(this, arg_0); 2653 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2654 } 2655 2656 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2657 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2658 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2659 verify_oop(oop_result, "broken oop in call_VM_base"); 2660 } 2661 2662 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2663 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2664 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2665 } 2666 2667 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2668 } 2669 2670 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2671 } 2672 2673 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2674 if (reachable(src1)) { 2675 cmpl(as_Address(src1), imm); 2676 } else { 2677 lea(rscratch1, src1); 2678 cmpl(Address(rscratch1, 0), imm); 2679 } 2680 } 2681 2682 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2683 assert(!src2.is_lval(), "use cmpptr"); 2684 if (reachable(src2)) { 2685 cmpl(src1, as_Address(src2)); 2686 } else { 2687 lea(rscratch1, src2); 2688 cmpl(src1, Address(rscratch1, 0)); 2689 } 2690 } 2691 2692 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2693 Assembler::cmpl(src1, imm); 2694 } 2695 2696 void MacroAssembler::cmp32(Register src1, Address src2) { 2697 Assembler::cmpl(src1, src2); 2698 } 2699 2700 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2701 ucomisd(opr1, opr2); 2702 2703 Label L; 2704 if (unordered_is_less) { 2705 movl(dst, -1); 2706 jcc(Assembler::parity, L); 2707 jcc(Assembler::below , L); 2708 movl(dst, 0); 2709 jcc(Assembler::equal , L); 2710 increment(dst); 2711 } else { // unordered is greater 2712 movl(dst, 1); 2713 jcc(Assembler::parity, L); 2714 jcc(Assembler::above , L); 2715 movl(dst, 0); 2716 jcc(Assembler::equal , L); 2717 decrementl(dst); 2718 } 2719 bind(L); 2720 } 2721 2722 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2723 ucomiss(opr1, opr2); 2724 2725 Label L; 2726 if (unordered_is_less) { 2727 movl(dst, -1); 2728 jcc(Assembler::parity, L); 2729 jcc(Assembler::below , L); 2730 movl(dst, 0); 2731 jcc(Assembler::equal , L); 2732 increment(dst); 2733 } else { // unordered is greater 2734 movl(dst, 1); 2735 jcc(Assembler::parity, L); 2736 jcc(Assembler::above , L); 2737 movl(dst, 0); 2738 jcc(Assembler::equal , L); 2739 decrementl(dst); 2740 } 2741 bind(L); 2742 } 2743 2744 2745 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2746 if (reachable(src1)) { 2747 cmpb(as_Address(src1), imm); 2748 } else { 2749 lea(rscratch1, src1); 2750 cmpb(Address(rscratch1, 0), imm); 2751 } 2752 } 2753 2754 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2755 #ifdef _LP64 2756 if (src2.is_lval()) { 2757 movptr(rscratch1, src2); 2758 Assembler::cmpq(src1, rscratch1); 2759 } else if (reachable(src2)) { 2760 cmpq(src1, as_Address(src2)); 2761 } else { 2762 lea(rscratch1, src2); 2763 Assembler::cmpq(src1, Address(rscratch1, 0)); 2764 } 2765 #else 2766 if (src2.is_lval()) { 2767 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2768 } else { 2769 cmpl(src1, as_Address(src2)); 2770 } 2771 #endif // _LP64 2772 } 2773 2774 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2775 assert(src2.is_lval(), "not a mem-mem compare"); 2776 #ifdef _LP64 2777 // moves src2's literal address 2778 movptr(rscratch1, src2); 2779 Assembler::cmpq(src1, rscratch1); 2780 #else 2781 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2782 #endif // _LP64 2783 } 2784 2785 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2786 if (reachable(adr)) { 2787 if (os::is_MP()) 2788 lock(); 2789 cmpxchgptr(reg, as_Address(adr)); 2790 } else { 2791 lea(rscratch1, adr); 2792 if (os::is_MP()) 2793 lock(); 2794 cmpxchgptr(reg, Address(rscratch1, 0)); 2795 } 2796 } 2797 2798 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2799 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2800 } 2801 2802 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2803 if (reachable(src)) { 2804 Assembler::comisd(dst, as_Address(src)); 2805 } else { 2806 lea(rscratch1, src); 2807 Assembler::comisd(dst, Address(rscratch1, 0)); 2808 } 2809 } 2810 2811 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2812 if (reachable(src)) { 2813 Assembler::comiss(dst, as_Address(src)); 2814 } else { 2815 lea(rscratch1, src); 2816 Assembler::comiss(dst, Address(rscratch1, 0)); 2817 } 2818 } 2819 2820 2821 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2822 Condition negated_cond = negate_condition(cond); 2823 Label L; 2824 jcc(negated_cond, L); 2825 pushf(); // Preserve flags 2826 atomic_incl(counter_addr); 2827 popf(); 2828 bind(L); 2829 } 2830 2831 int MacroAssembler::corrected_idivl(Register reg) { 2832 // Full implementation of Java idiv and irem; checks for 2833 // special case as described in JVM spec., p.243 & p.271. 2834 // The function returns the (pc) offset of the idivl 2835 // instruction - may be needed for implicit exceptions. 2836 // 2837 // normal case special case 2838 // 2839 // input : rax,: dividend min_int 2840 // reg: divisor (may not be rax,/rdx) -1 2841 // 2842 // output: rax,: quotient (= rax, idiv reg) min_int 2843 // rdx: remainder (= rax, irem reg) 0 2844 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2845 const int min_int = 0x80000000; 2846 Label normal_case, special_case; 2847 2848 // check for special case 2849 cmpl(rax, min_int); 2850 jcc(Assembler::notEqual, normal_case); 2851 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2852 cmpl(reg, -1); 2853 jcc(Assembler::equal, special_case); 2854 2855 // handle normal case 2856 bind(normal_case); 2857 cdql(); 2858 int idivl_offset = offset(); 2859 idivl(reg); 2860 2861 // normal and special case exit 2862 bind(special_case); 2863 2864 return idivl_offset; 2865 } 2866 2867 2868 2869 void MacroAssembler::decrementl(Register reg, int value) { 2870 if (value == min_jint) {subl(reg, value) ; return; } 2871 if (value < 0) { incrementl(reg, -value); return; } 2872 if (value == 0) { ; return; } 2873 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2874 /* else */ { subl(reg, value) ; return; } 2875 } 2876 2877 void MacroAssembler::decrementl(Address dst, int value) { 2878 if (value == min_jint) {subl(dst, value) ; return; } 2879 if (value < 0) { incrementl(dst, -value); return; } 2880 if (value == 0) { ; return; } 2881 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2882 /* else */ { subl(dst, value) ; return; } 2883 } 2884 2885 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2886 assert (shift_value > 0, "illegal shift value"); 2887 Label _is_positive; 2888 testl (reg, reg); 2889 jcc (Assembler::positive, _is_positive); 2890 int offset = (1 << shift_value) - 1 ; 2891 2892 if (offset == 1) { 2893 incrementl(reg); 2894 } else { 2895 addl(reg, offset); 2896 } 2897 2898 bind (_is_positive); 2899 sarl(reg, shift_value); 2900 } 2901 2902 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2903 if (reachable(src)) { 2904 Assembler::divsd(dst, as_Address(src)); 2905 } else { 2906 lea(rscratch1, src); 2907 Assembler::divsd(dst, Address(rscratch1, 0)); 2908 } 2909 } 2910 2911 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2912 if (reachable(src)) { 2913 Assembler::divss(dst, as_Address(src)); 2914 } else { 2915 lea(rscratch1, src); 2916 Assembler::divss(dst, Address(rscratch1, 0)); 2917 } 2918 } 2919 2920 // !defined(COMPILER2) is because of stupid core builds 2921 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2922 void MacroAssembler::empty_FPU_stack() { 2923 if (VM_Version::supports_mmx()) { 2924 emms(); 2925 } else { 2926 for (int i = 8; i-- > 0; ) ffree(i); 2927 } 2928 } 2929 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2930 2931 2932 // Defines obj, preserves var_size_in_bytes 2933 void MacroAssembler::eden_allocate(Register obj, 2934 Register var_size_in_bytes, 2935 int con_size_in_bytes, 2936 Register t1, 2937 Label& slow_case) { 2938 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2939 assert_different_registers(obj, var_size_in_bytes, t1); 2940 if (!Universe::heap()->supports_inline_contig_alloc()) { 2941 jmp(slow_case); 2942 } else { 2943 Register end = t1; 2944 Label retry; 2945 bind(retry); 2946 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2947 movptr(obj, heap_top); 2948 if (var_size_in_bytes == noreg) { 2949 lea(end, Address(obj, con_size_in_bytes)); 2950 } else { 2951 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2952 } 2953 // if end < obj then we wrapped around => object too long => slow case 2954 cmpptr(end, obj); 2955 jcc(Assembler::below, slow_case); 2956 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2957 jcc(Assembler::above, slow_case); 2958 // Compare obj with the top addr, and if still equal, store the new top addr in 2959 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2960 // it otherwise. Use lock prefix for atomicity on MPs. 2961 locked_cmpxchgptr(end, heap_top); 2962 jcc(Assembler::notEqual, retry); 2963 } 2964 } 2965 2966 void MacroAssembler::enter() { 2967 push(rbp); 2968 mov(rbp, rsp); 2969 } 2970 2971 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2972 void MacroAssembler::fat_nop() { 2973 if (UseAddressNop) { 2974 addr_nop_5(); 2975 } else { 2976 emit_int8(0x26); // es: 2977 emit_int8(0x2e); // cs: 2978 emit_int8(0x64); // fs: 2979 emit_int8(0x65); // gs: 2980 emit_int8((unsigned char)0x90); 2981 } 2982 } 2983 2984 void MacroAssembler::fcmp(Register tmp) { 2985 fcmp(tmp, 1, true, true); 2986 } 2987 2988 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2989 assert(!pop_right || pop_left, "usage error"); 2990 if (VM_Version::supports_cmov()) { 2991 assert(tmp == noreg, "unneeded temp"); 2992 if (pop_left) { 2993 fucomip(index); 2994 } else { 2995 fucomi(index); 2996 } 2997 if (pop_right) { 2998 fpop(); 2999 } 3000 } else { 3001 assert(tmp != noreg, "need temp"); 3002 if (pop_left) { 3003 if (pop_right) { 3004 fcompp(); 3005 } else { 3006 fcomp(index); 3007 } 3008 } else { 3009 fcom(index); 3010 } 3011 // convert FPU condition into eflags condition via rax, 3012 save_rax(tmp); 3013 fwait(); fnstsw_ax(); 3014 sahf(); 3015 restore_rax(tmp); 3016 } 3017 // condition codes set as follows: 3018 // 3019 // CF (corresponds to C0) if x < y 3020 // PF (corresponds to C2) if unordered 3021 // ZF (corresponds to C3) if x = y 3022 } 3023 3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3025 fcmp2int(dst, unordered_is_less, 1, true, true); 3026 } 3027 3028 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3029 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3030 Label L; 3031 if (unordered_is_less) { 3032 movl(dst, -1); 3033 jcc(Assembler::parity, L); 3034 jcc(Assembler::below , L); 3035 movl(dst, 0); 3036 jcc(Assembler::equal , L); 3037 increment(dst); 3038 } else { // unordered is greater 3039 movl(dst, 1); 3040 jcc(Assembler::parity, L); 3041 jcc(Assembler::above , L); 3042 movl(dst, 0); 3043 jcc(Assembler::equal , L); 3044 decrementl(dst); 3045 } 3046 bind(L); 3047 } 3048 3049 void MacroAssembler::fld_d(AddressLiteral src) { 3050 fld_d(as_Address(src)); 3051 } 3052 3053 void MacroAssembler::fld_s(AddressLiteral src) { 3054 fld_s(as_Address(src)); 3055 } 3056 3057 void MacroAssembler::fld_x(AddressLiteral src) { 3058 Assembler::fld_x(as_Address(src)); 3059 } 3060 3061 void MacroAssembler::fldcw(AddressLiteral src) { 3062 Assembler::fldcw(as_Address(src)); 3063 } 3064 3065 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3066 if (reachable(src)) { 3067 Assembler::mulpd(dst, as_Address(src)); 3068 } else { 3069 lea(rscratch1, src); 3070 Assembler::mulpd(dst, Address(rscratch1, 0)); 3071 } 3072 } 3073 3074 void MacroAssembler::increase_precision() { 3075 subptr(rsp, BytesPerWord); 3076 fnstcw(Address(rsp, 0)); 3077 movl(rax, Address(rsp, 0)); 3078 orl(rax, 0x300); 3079 push(rax); 3080 fldcw(Address(rsp, 0)); 3081 pop(rax); 3082 } 3083 3084 void MacroAssembler::restore_precision() { 3085 fldcw(Address(rsp, 0)); 3086 addptr(rsp, BytesPerWord); 3087 } 3088 3089 void MacroAssembler::fpop() { 3090 ffree(); 3091 fincstp(); 3092 } 3093 3094 void MacroAssembler::load_float(Address src) { 3095 if (UseSSE >= 1) { 3096 movflt(xmm0, src); 3097 } else { 3098 LP64_ONLY(ShouldNotReachHere()); 3099 NOT_LP64(fld_s(src)); 3100 } 3101 } 3102 3103 void MacroAssembler::store_float(Address dst) { 3104 if (UseSSE >= 1) { 3105 movflt(dst, xmm0); 3106 } else { 3107 LP64_ONLY(ShouldNotReachHere()); 3108 NOT_LP64(fstp_s(dst)); 3109 } 3110 } 3111 3112 void MacroAssembler::load_double(Address src) { 3113 if (UseSSE >= 2) { 3114 movdbl(xmm0, src); 3115 } else { 3116 LP64_ONLY(ShouldNotReachHere()); 3117 NOT_LP64(fld_d(src)); 3118 } 3119 } 3120 3121 void MacroAssembler::store_double(Address dst) { 3122 if (UseSSE >= 2) { 3123 movdbl(dst, xmm0); 3124 } else { 3125 LP64_ONLY(ShouldNotReachHere()); 3126 NOT_LP64(fstp_d(dst)); 3127 } 3128 } 3129 3130 void MacroAssembler::fremr(Register tmp) { 3131 save_rax(tmp); 3132 { Label L; 3133 bind(L); 3134 fprem(); 3135 fwait(); fnstsw_ax(); 3136 #ifdef _LP64 3137 testl(rax, 0x400); 3138 jcc(Assembler::notEqual, L); 3139 #else 3140 sahf(); 3141 jcc(Assembler::parity, L); 3142 #endif // _LP64 3143 } 3144 restore_rax(tmp); 3145 // Result is in ST0. 3146 // Note: fxch & fpop to get rid of ST1 3147 // (otherwise FPU stack could overflow eventually) 3148 fxch(1); 3149 fpop(); 3150 } 3151 3152 // dst = c = a * b + c 3153 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3154 Assembler::vfmadd231sd(c, a, b); 3155 if (dst != c) { 3156 movdbl(dst, c); 3157 } 3158 } 3159 3160 // dst = c = a * b + c 3161 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3162 Assembler::vfmadd231ss(c, a, b); 3163 if (dst != c) { 3164 movflt(dst, c); 3165 } 3166 } 3167 3168 3169 3170 3171 void MacroAssembler::incrementl(AddressLiteral dst) { 3172 if (reachable(dst)) { 3173 incrementl(as_Address(dst)); 3174 } else { 3175 lea(rscratch1, dst); 3176 incrementl(Address(rscratch1, 0)); 3177 } 3178 } 3179 3180 void MacroAssembler::incrementl(ArrayAddress dst) { 3181 incrementl(as_Address(dst)); 3182 } 3183 3184 void MacroAssembler::incrementl(Register reg, int value) { 3185 if (value == min_jint) {addl(reg, value) ; return; } 3186 if (value < 0) { decrementl(reg, -value); return; } 3187 if (value == 0) { ; return; } 3188 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3189 /* else */ { addl(reg, value) ; return; } 3190 } 3191 3192 void MacroAssembler::incrementl(Address dst, int value) { 3193 if (value == min_jint) {addl(dst, value) ; return; } 3194 if (value < 0) { decrementl(dst, -value); return; } 3195 if (value == 0) { ; return; } 3196 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3197 /* else */ { addl(dst, value) ; return; } 3198 } 3199 3200 void MacroAssembler::jump(AddressLiteral dst) { 3201 if (reachable(dst)) { 3202 jmp_literal(dst.target(), dst.rspec()); 3203 } else { 3204 lea(rscratch1, dst); 3205 jmp(rscratch1); 3206 } 3207 } 3208 3209 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3210 if (reachable(dst)) { 3211 InstructionMark im(this); 3212 relocate(dst.reloc()); 3213 const int short_size = 2; 3214 const int long_size = 6; 3215 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3216 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3217 // 0111 tttn #8-bit disp 3218 emit_int8(0x70 | cc); 3219 emit_int8((offs - short_size) & 0xFF); 3220 } else { 3221 // 0000 1111 1000 tttn #32-bit disp 3222 emit_int8(0x0F); 3223 emit_int8((unsigned char)(0x80 | cc)); 3224 emit_int32(offs - long_size); 3225 } 3226 } else { 3227 #ifdef ASSERT 3228 warning("reversing conditional branch"); 3229 #endif /* ASSERT */ 3230 Label skip; 3231 jccb(reverse[cc], skip); 3232 lea(rscratch1, dst); 3233 Assembler::jmp(rscratch1); 3234 bind(skip); 3235 } 3236 } 3237 3238 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3239 if (reachable(src)) { 3240 Assembler::ldmxcsr(as_Address(src)); 3241 } else { 3242 lea(rscratch1, src); 3243 Assembler::ldmxcsr(Address(rscratch1, 0)); 3244 } 3245 } 3246 3247 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3248 int off; 3249 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3250 off = offset(); 3251 movsbl(dst, src); // movsxb 3252 } else { 3253 off = load_unsigned_byte(dst, src); 3254 shll(dst, 24); 3255 sarl(dst, 24); 3256 } 3257 return off; 3258 } 3259 3260 // Note: load_signed_short used to be called load_signed_word. 3261 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3262 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3263 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3264 int MacroAssembler::load_signed_short(Register dst, Address src) { 3265 int off; 3266 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3267 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3268 // version but this is what 64bit has always done. This seems to imply 3269 // that users are only using 32bits worth. 3270 off = offset(); 3271 movswl(dst, src); // movsxw 3272 } else { 3273 off = load_unsigned_short(dst, src); 3274 shll(dst, 16); 3275 sarl(dst, 16); 3276 } 3277 return off; 3278 } 3279 3280 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3281 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3282 // and "3.9 Partial Register Penalties", p. 22). 3283 int off; 3284 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3285 off = offset(); 3286 movzbl(dst, src); // movzxb 3287 } else { 3288 xorl(dst, dst); 3289 off = offset(); 3290 movb(dst, src); 3291 } 3292 return off; 3293 } 3294 3295 // Note: load_unsigned_short used to be called load_unsigned_word. 3296 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3297 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3298 // and "3.9 Partial Register Penalties", p. 22). 3299 int off; 3300 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3301 off = offset(); 3302 movzwl(dst, src); // movzxw 3303 } else { 3304 xorl(dst, dst); 3305 off = offset(); 3306 movw(dst, src); 3307 } 3308 return off; 3309 } 3310 3311 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3312 switch (size_in_bytes) { 3313 #ifndef _LP64 3314 case 8: 3315 assert(dst2 != noreg, "second dest register required"); 3316 movl(dst, src); 3317 movl(dst2, src.plus_disp(BytesPerInt)); 3318 break; 3319 #else 3320 case 8: movq(dst, src); break; 3321 #endif 3322 case 4: movl(dst, src); break; 3323 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3324 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3325 default: ShouldNotReachHere(); 3326 } 3327 } 3328 3329 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3330 switch (size_in_bytes) { 3331 #ifndef _LP64 3332 case 8: 3333 assert(src2 != noreg, "second source register required"); 3334 movl(dst, src); 3335 movl(dst.plus_disp(BytesPerInt), src2); 3336 break; 3337 #else 3338 case 8: movq(dst, src); break; 3339 #endif 3340 case 4: movl(dst, src); break; 3341 case 2: movw(dst, src); break; 3342 case 1: movb(dst, src); break; 3343 default: ShouldNotReachHere(); 3344 } 3345 } 3346 3347 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3348 if (reachable(dst)) { 3349 movl(as_Address(dst), src); 3350 } else { 3351 lea(rscratch1, dst); 3352 movl(Address(rscratch1, 0), src); 3353 } 3354 } 3355 3356 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3357 if (reachable(src)) { 3358 movl(dst, as_Address(src)); 3359 } else { 3360 lea(rscratch1, src); 3361 movl(dst, Address(rscratch1, 0)); 3362 } 3363 } 3364 3365 // C++ bool manipulation 3366 3367 void MacroAssembler::movbool(Register dst, Address src) { 3368 if(sizeof(bool) == 1) 3369 movb(dst, src); 3370 else if(sizeof(bool) == 2) 3371 movw(dst, src); 3372 else if(sizeof(bool) == 4) 3373 movl(dst, src); 3374 else 3375 // unsupported 3376 ShouldNotReachHere(); 3377 } 3378 3379 void MacroAssembler::movbool(Address dst, bool boolconst) { 3380 if(sizeof(bool) == 1) 3381 movb(dst, (int) boolconst); 3382 else if(sizeof(bool) == 2) 3383 movw(dst, (int) boolconst); 3384 else if(sizeof(bool) == 4) 3385 movl(dst, (int) boolconst); 3386 else 3387 // unsupported 3388 ShouldNotReachHere(); 3389 } 3390 3391 void MacroAssembler::movbool(Address dst, Register src) { 3392 if(sizeof(bool) == 1) 3393 movb(dst, src); 3394 else if(sizeof(bool) == 2) 3395 movw(dst, src); 3396 else if(sizeof(bool) == 4) 3397 movl(dst, src); 3398 else 3399 // unsupported 3400 ShouldNotReachHere(); 3401 } 3402 3403 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3404 movb(as_Address(dst), src); 3405 } 3406 3407 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3408 if (reachable(src)) { 3409 movdl(dst, as_Address(src)); 3410 } else { 3411 lea(rscratch1, src); 3412 movdl(dst, Address(rscratch1, 0)); 3413 } 3414 } 3415 3416 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3417 if (reachable(src)) { 3418 movq(dst, as_Address(src)); 3419 } else { 3420 lea(rscratch1, src); 3421 movq(dst, Address(rscratch1, 0)); 3422 } 3423 } 3424 3425 void MacroAssembler::setvectmask(Register dst, Register src) { 3426 Assembler::movl(dst, 1); 3427 Assembler::shlxl(dst, dst, src); 3428 Assembler::decl(dst); 3429 Assembler::kmovdl(k1, dst); 3430 Assembler::movl(dst, src); 3431 } 3432 3433 void MacroAssembler::restorevectmask() { 3434 Assembler::knotwl(k1, k0); 3435 } 3436 3437 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3438 if (reachable(src)) { 3439 if (UseXmmLoadAndClearUpper) { 3440 movsd (dst, as_Address(src)); 3441 } else { 3442 movlpd(dst, as_Address(src)); 3443 } 3444 } else { 3445 lea(rscratch1, src); 3446 if (UseXmmLoadAndClearUpper) { 3447 movsd (dst, Address(rscratch1, 0)); 3448 } else { 3449 movlpd(dst, Address(rscratch1, 0)); 3450 } 3451 } 3452 } 3453 3454 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3455 if (reachable(src)) { 3456 movss(dst, as_Address(src)); 3457 } else { 3458 lea(rscratch1, src); 3459 movss(dst, Address(rscratch1, 0)); 3460 } 3461 } 3462 3463 void MacroAssembler::movptr(Register dst, Register src) { 3464 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3465 } 3466 3467 void MacroAssembler::movptr(Register dst, Address src) { 3468 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3469 } 3470 3471 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3472 void MacroAssembler::movptr(Register dst, intptr_t src) { 3473 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3474 } 3475 3476 void MacroAssembler::movptr(Address dst, Register src) { 3477 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3478 } 3479 3480 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3481 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3482 Assembler::vextractf32x4(dst, src, 0); 3483 } else { 3484 Assembler::movdqu(dst, src); 3485 } 3486 } 3487 3488 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3489 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3490 Assembler::vinsertf32x4(dst, dst, src, 0); 3491 } else { 3492 Assembler::movdqu(dst, src); 3493 } 3494 } 3495 3496 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3497 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3498 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3499 } else { 3500 Assembler::movdqu(dst, src); 3501 } 3502 } 3503 3504 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 3505 if (reachable(src)) { 3506 movdqu(dst, as_Address(src)); 3507 } else { 3508 lea(scratchReg, src); 3509 movdqu(dst, Address(scratchReg, 0)); 3510 } 3511 } 3512 3513 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3514 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3515 vextractf64x4_low(dst, src); 3516 } else { 3517 Assembler::vmovdqu(dst, src); 3518 } 3519 } 3520 3521 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3522 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3523 vinsertf64x4_low(dst, src); 3524 } else { 3525 Assembler::vmovdqu(dst, src); 3526 } 3527 } 3528 3529 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3530 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3531 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3532 } 3533 else { 3534 Assembler::vmovdqu(dst, src); 3535 } 3536 } 3537 3538 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3539 if (reachable(src)) { 3540 vmovdqu(dst, as_Address(src)); 3541 } 3542 else { 3543 lea(rscratch1, src); 3544 vmovdqu(dst, Address(rscratch1, 0)); 3545 } 3546 } 3547 3548 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3549 if (reachable(src)) { 3550 Assembler::movdqa(dst, as_Address(src)); 3551 } else { 3552 lea(rscratch1, src); 3553 Assembler::movdqa(dst, Address(rscratch1, 0)); 3554 } 3555 } 3556 3557 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3558 if (reachable(src)) { 3559 Assembler::movsd(dst, as_Address(src)); 3560 } else { 3561 lea(rscratch1, src); 3562 Assembler::movsd(dst, Address(rscratch1, 0)); 3563 } 3564 } 3565 3566 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3567 if (reachable(src)) { 3568 Assembler::movss(dst, as_Address(src)); 3569 } else { 3570 lea(rscratch1, src); 3571 Assembler::movss(dst, Address(rscratch1, 0)); 3572 } 3573 } 3574 3575 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3576 if (reachable(src)) { 3577 Assembler::mulsd(dst, as_Address(src)); 3578 } else { 3579 lea(rscratch1, src); 3580 Assembler::mulsd(dst, Address(rscratch1, 0)); 3581 } 3582 } 3583 3584 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3585 if (reachable(src)) { 3586 Assembler::mulss(dst, as_Address(src)); 3587 } else { 3588 lea(rscratch1, src); 3589 Assembler::mulss(dst, Address(rscratch1, 0)); 3590 } 3591 } 3592 3593 void MacroAssembler::null_check(Register reg, int offset) { 3594 if (needs_explicit_null_check(offset)) { 3595 // provoke OS NULL exception if reg = NULL by 3596 // accessing M[reg] w/o changing any (non-CC) registers 3597 // NOTE: cmpl is plenty here to provoke a segv 3598 cmpptr(rax, Address(reg, 0)); 3599 // Note: should probably use testl(rax, Address(reg, 0)); 3600 // may be shorter code (however, this version of 3601 // testl needs to be implemented first) 3602 } else { 3603 // nothing to do, (later) access of M[reg + offset] 3604 // will provoke OS NULL exception if reg = NULL 3605 } 3606 } 3607 3608 void MacroAssembler::os_breakpoint() { 3609 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3610 // (e.g., MSVC can't call ps() otherwise) 3611 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3612 } 3613 3614 #ifdef _LP64 3615 #define XSTATE_BV 0x200 3616 #endif 3617 3618 void MacroAssembler::pop_CPU_state() { 3619 pop_FPU_state(); 3620 pop_IU_state(); 3621 } 3622 3623 void MacroAssembler::pop_FPU_state() { 3624 #ifndef _LP64 3625 frstor(Address(rsp, 0)); 3626 #else 3627 fxrstor(Address(rsp, 0)); 3628 #endif 3629 addptr(rsp, FPUStateSizeInWords * wordSize); 3630 } 3631 3632 void MacroAssembler::pop_IU_state() { 3633 popa(); 3634 LP64_ONLY(addq(rsp, 8)); 3635 popf(); 3636 } 3637 3638 // Save Integer and Float state 3639 // Warning: Stack must be 16 byte aligned (64bit) 3640 void MacroAssembler::push_CPU_state() { 3641 push_IU_state(); 3642 push_FPU_state(); 3643 } 3644 3645 void MacroAssembler::push_FPU_state() { 3646 subptr(rsp, FPUStateSizeInWords * wordSize); 3647 #ifndef _LP64 3648 fnsave(Address(rsp, 0)); 3649 fwait(); 3650 #else 3651 fxsave(Address(rsp, 0)); 3652 #endif // LP64 3653 } 3654 3655 void MacroAssembler::push_IU_state() { 3656 // Push flags first because pusha kills them 3657 pushf(); 3658 // Make sure rsp stays 16-byte aligned 3659 LP64_ONLY(subq(rsp, 8)); 3660 pusha(); 3661 } 3662 3663 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3664 if (!java_thread->is_valid()) { 3665 java_thread = rdi; 3666 get_thread(java_thread); 3667 } 3668 // we must set sp to zero to clear frame 3669 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3670 if (clear_fp) { 3671 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3672 } 3673 3674 // Always clear the pc because it could have been set by make_walkable() 3675 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3676 3677 vzeroupper(); 3678 } 3679 3680 void MacroAssembler::restore_rax(Register tmp) { 3681 if (tmp == noreg) pop(rax); 3682 else if (tmp != rax) mov(rax, tmp); 3683 } 3684 3685 void MacroAssembler::round_to(Register reg, int modulus) { 3686 addptr(reg, modulus - 1); 3687 andptr(reg, -modulus); 3688 } 3689 3690 void MacroAssembler::save_rax(Register tmp) { 3691 if (tmp == noreg) push(rax); 3692 else if (tmp != rax) mov(tmp, rax); 3693 } 3694 3695 // Write serialization page so VM thread can do a pseudo remote membar. 3696 // We use the current thread pointer to calculate a thread specific 3697 // offset to write to within the page. This minimizes bus traffic 3698 // due to cache line collision. 3699 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3700 movl(tmp, thread); 3701 shrl(tmp, os::get_serialize_page_shift_count()); 3702 andl(tmp, (os::vm_page_size() - sizeof(int))); 3703 3704 Address index(noreg, tmp, Address::times_1); 3705 ExternalAddress page(os::get_memory_serialize_page()); 3706 3707 // Size of store must match masking code above 3708 movl(as_Address(ArrayAddress(page, index)), tmp); 3709 } 3710 3711 // Calls to C land 3712 // 3713 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3714 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3715 // has to be reset to 0. This is required to allow proper stack traversal. 3716 void MacroAssembler::set_last_Java_frame(Register java_thread, 3717 Register last_java_sp, 3718 Register last_java_fp, 3719 address last_java_pc) { 3720 vzeroupper(); 3721 // determine java_thread register 3722 if (!java_thread->is_valid()) { 3723 java_thread = rdi; 3724 get_thread(java_thread); 3725 } 3726 // determine last_java_sp register 3727 if (!last_java_sp->is_valid()) { 3728 last_java_sp = rsp; 3729 } 3730 3731 // last_java_fp is optional 3732 3733 if (last_java_fp->is_valid()) { 3734 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3735 } 3736 3737 // last_java_pc is optional 3738 3739 if (last_java_pc != NULL) { 3740 lea(Address(java_thread, 3741 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3742 InternalAddress(last_java_pc)); 3743 3744 } 3745 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3746 } 3747 3748 void MacroAssembler::shlptr(Register dst, int imm8) { 3749 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3750 } 3751 3752 void MacroAssembler::shrptr(Register dst, int imm8) { 3753 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3754 } 3755 3756 void MacroAssembler::sign_extend_byte(Register reg) { 3757 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3758 movsbl(reg, reg); // movsxb 3759 } else { 3760 shll(reg, 24); 3761 sarl(reg, 24); 3762 } 3763 } 3764 3765 void MacroAssembler::sign_extend_short(Register reg) { 3766 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3767 movswl(reg, reg); // movsxw 3768 } else { 3769 shll(reg, 16); 3770 sarl(reg, 16); 3771 } 3772 } 3773 3774 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3775 assert(reachable(src), "Address should be reachable"); 3776 testl(dst, as_Address(src)); 3777 } 3778 3779 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3780 int dst_enc = dst->encoding(); 3781 int src_enc = src->encoding(); 3782 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3783 Assembler::pcmpeqb(dst, src); 3784 } else if ((dst_enc < 16) && (src_enc < 16)) { 3785 Assembler::pcmpeqb(dst, src); 3786 } else if (src_enc < 16) { 3787 subptr(rsp, 64); 3788 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3789 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3790 Assembler::pcmpeqb(xmm0, src); 3791 movdqu(dst, xmm0); 3792 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3793 addptr(rsp, 64); 3794 } else if (dst_enc < 16) { 3795 subptr(rsp, 64); 3796 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3797 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3798 Assembler::pcmpeqb(dst, xmm0); 3799 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3800 addptr(rsp, 64); 3801 } else { 3802 subptr(rsp, 64); 3803 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3804 subptr(rsp, 64); 3805 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3806 movdqu(xmm0, src); 3807 movdqu(xmm1, dst); 3808 Assembler::pcmpeqb(xmm1, xmm0); 3809 movdqu(dst, xmm1); 3810 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3811 addptr(rsp, 64); 3812 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3813 addptr(rsp, 64); 3814 } 3815 } 3816 3817 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3818 int dst_enc = dst->encoding(); 3819 int src_enc = src->encoding(); 3820 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3821 Assembler::pcmpeqw(dst, src); 3822 } else if ((dst_enc < 16) && (src_enc < 16)) { 3823 Assembler::pcmpeqw(dst, src); 3824 } else if (src_enc < 16) { 3825 subptr(rsp, 64); 3826 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3827 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3828 Assembler::pcmpeqw(xmm0, src); 3829 movdqu(dst, xmm0); 3830 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3831 addptr(rsp, 64); 3832 } else if (dst_enc < 16) { 3833 subptr(rsp, 64); 3834 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3835 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3836 Assembler::pcmpeqw(dst, xmm0); 3837 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3838 addptr(rsp, 64); 3839 } else { 3840 subptr(rsp, 64); 3841 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3842 subptr(rsp, 64); 3843 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3844 movdqu(xmm0, src); 3845 movdqu(xmm1, dst); 3846 Assembler::pcmpeqw(xmm1, xmm0); 3847 movdqu(dst, xmm1); 3848 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3849 addptr(rsp, 64); 3850 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3851 addptr(rsp, 64); 3852 } 3853 } 3854 3855 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3856 int dst_enc = dst->encoding(); 3857 if (dst_enc < 16) { 3858 Assembler::pcmpestri(dst, src, imm8); 3859 } else { 3860 subptr(rsp, 64); 3861 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3862 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3863 Assembler::pcmpestri(xmm0, src, imm8); 3864 movdqu(dst, xmm0); 3865 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3866 addptr(rsp, 64); 3867 } 3868 } 3869 3870 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3871 int dst_enc = dst->encoding(); 3872 int src_enc = src->encoding(); 3873 if ((dst_enc < 16) && (src_enc < 16)) { 3874 Assembler::pcmpestri(dst, src, imm8); 3875 } else if (src_enc < 16) { 3876 subptr(rsp, 64); 3877 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3878 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3879 Assembler::pcmpestri(xmm0, src, imm8); 3880 movdqu(dst, xmm0); 3881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3882 addptr(rsp, 64); 3883 } else if (dst_enc < 16) { 3884 subptr(rsp, 64); 3885 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3886 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3887 Assembler::pcmpestri(dst, xmm0, imm8); 3888 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3889 addptr(rsp, 64); 3890 } else { 3891 subptr(rsp, 64); 3892 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3893 subptr(rsp, 64); 3894 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3895 movdqu(xmm0, src); 3896 movdqu(xmm1, dst); 3897 Assembler::pcmpestri(xmm1, xmm0, imm8); 3898 movdqu(dst, xmm1); 3899 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3900 addptr(rsp, 64); 3901 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3902 addptr(rsp, 64); 3903 } 3904 } 3905 3906 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3907 int dst_enc = dst->encoding(); 3908 int src_enc = src->encoding(); 3909 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3910 Assembler::pmovzxbw(dst, src); 3911 } else if ((dst_enc < 16) && (src_enc < 16)) { 3912 Assembler::pmovzxbw(dst, src); 3913 } else if (src_enc < 16) { 3914 subptr(rsp, 64); 3915 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3916 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3917 Assembler::pmovzxbw(xmm0, src); 3918 movdqu(dst, xmm0); 3919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3920 addptr(rsp, 64); 3921 } else if (dst_enc < 16) { 3922 subptr(rsp, 64); 3923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3924 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3925 Assembler::pmovzxbw(dst, xmm0); 3926 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3927 addptr(rsp, 64); 3928 } else { 3929 subptr(rsp, 64); 3930 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3931 subptr(rsp, 64); 3932 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3933 movdqu(xmm0, src); 3934 movdqu(xmm1, dst); 3935 Assembler::pmovzxbw(xmm1, xmm0); 3936 movdqu(dst, xmm1); 3937 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3938 addptr(rsp, 64); 3939 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3940 addptr(rsp, 64); 3941 } 3942 } 3943 3944 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3945 int dst_enc = dst->encoding(); 3946 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3947 Assembler::pmovzxbw(dst, src); 3948 } else if (dst_enc < 16) { 3949 Assembler::pmovzxbw(dst, src); 3950 } else { 3951 subptr(rsp, 64); 3952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3953 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3954 Assembler::pmovzxbw(xmm0, src); 3955 movdqu(dst, xmm0); 3956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3957 addptr(rsp, 64); 3958 } 3959 } 3960 3961 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3962 int src_enc = src->encoding(); 3963 if (src_enc < 16) { 3964 Assembler::pmovmskb(dst, src); 3965 } else { 3966 subptr(rsp, 64); 3967 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3968 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3969 Assembler::pmovmskb(dst, xmm0); 3970 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3971 addptr(rsp, 64); 3972 } 3973 } 3974 3975 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3976 int dst_enc = dst->encoding(); 3977 int src_enc = src->encoding(); 3978 if ((dst_enc < 16) && (src_enc < 16)) { 3979 Assembler::ptest(dst, src); 3980 } else if (src_enc < 16) { 3981 subptr(rsp, 64); 3982 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3983 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3984 Assembler::ptest(xmm0, src); 3985 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3986 addptr(rsp, 64); 3987 } else if (dst_enc < 16) { 3988 subptr(rsp, 64); 3989 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3990 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3991 Assembler::ptest(dst, xmm0); 3992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3993 addptr(rsp, 64); 3994 } else { 3995 subptr(rsp, 64); 3996 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3997 subptr(rsp, 64); 3998 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3999 movdqu(xmm0, src); 4000 movdqu(xmm1, dst); 4001 Assembler::ptest(xmm1, xmm0); 4002 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4003 addptr(rsp, 64); 4004 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4005 addptr(rsp, 64); 4006 } 4007 } 4008 4009 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4010 if (reachable(src)) { 4011 Assembler::sqrtsd(dst, as_Address(src)); 4012 } else { 4013 lea(rscratch1, src); 4014 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4015 } 4016 } 4017 4018 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4019 if (reachable(src)) { 4020 Assembler::sqrtss(dst, as_Address(src)); 4021 } else { 4022 lea(rscratch1, src); 4023 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4024 } 4025 } 4026 4027 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4028 if (reachable(src)) { 4029 Assembler::subsd(dst, as_Address(src)); 4030 } else { 4031 lea(rscratch1, src); 4032 Assembler::subsd(dst, Address(rscratch1, 0)); 4033 } 4034 } 4035 4036 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4037 if (reachable(src)) { 4038 Assembler::subss(dst, as_Address(src)); 4039 } else { 4040 lea(rscratch1, src); 4041 Assembler::subss(dst, Address(rscratch1, 0)); 4042 } 4043 } 4044 4045 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4046 if (reachable(src)) { 4047 Assembler::ucomisd(dst, as_Address(src)); 4048 } else { 4049 lea(rscratch1, src); 4050 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4051 } 4052 } 4053 4054 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4055 if (reachable(src)) { 4056 Assembler::ucomiss(dst, as_Address(src)); 4057 } else { 4058 lea(rscratch1, src); 4059 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4060 } 4061 } 4062 4063 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4064 // Used in sign-bit flipping with aligned address. 4065 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4066 if (reachable(src)) { 4067 Assembler::xorpd(dst, as_Address(src)); 4068 } else { 4069 lea(rscratch1, src); 4070 Assembler::xorpd(dst, Address(rscratch1, 0)); 4071 } 4072 } 4073 4074 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4075 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4076 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4077 } 4078 else { 4079 Assembler::xorpd(dst, src); 4080 } 4081 } 4082 4083 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4084 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4085 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4086 } else { 4087 Assembler::xorps(dst, src); 4088 } 4089 } 4090 4091 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4092 // Used in sign-bit flipping with aligned address. 4093 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4094 if (reachable(src)) { 4095 Assembler::xorps(dst, as_Address(src)); 4096 } else { 4097 lea(rscratch1, src); 4098 Assembler::xorps(dst, Address(rscratch1, 0)); 4099 } 4100 } 4101 4102 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4103 // Used in sign-bit flipping with aligned address. 4104 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4105 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4106 if (reachable(src)) { 4107 Assembler::pshufb(dst, as_Address(src)); 4108 } else { 4109 lea(rscratch1, src); 4110 Assembler::pshufb(dst, Address(rscratch1, 0)); 4111 } 4112 } 4113 4114 // AVX 3-operands instructions 4115 4116 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4117 if (reachable(src)) { 4118 vaddsd(dst, nds, as_Address(src)); 4119 } else { 4120 lea(rscratch1, src); 4121 vaddsd(dst, nds, Address(rscratch1, 0)); 4122 } 4123 } 4124 4125 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4126 if (reachable(src)) { 4127 vaddss(dst, nds, as_Address(src)); 4128 } else { 4129 lea(rscratch1, src); 4130 vaddss(dst, nds, Address(rscratch1, 0)); 4131 } 4132 } 4133 4134 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4135 int dst_enc = dst->encoding(); 4136 int nds_enc = nds->encoding(); 4137 int src_enc = src->encoding(); 4138 if ((dst_enc < 16) && (nds_enc < 16)) { 4139 vandps(dst, nds, negate_field, vector_len); 4140 } else if ((src_enc < 16) && (dst_enc < 16)) { 4141 movss(src, nds); 4142 vandps(dst, src, negate_field, vector_len); 4143 } else if (src_enc < 16) { 4144 movss(src, nds); 4145 vandps(src, src, negate_field, vector_len); 4146 movss(dst, src); 4147 } else if (dst_enc < 16) { 4148 movdqu(src, xmm0); 4149 movss(xmm0, nds); 4150 vandps(dst, xmm0, negate_field, vector_len); 4151 movdqu(xmm0, src); 4152 } else if (nds_enc < 16) { 4153 movdqu(src, xmm0); 4154 vandps(xmm0, nds, negate_field, vector_len); 4155 movss(dst, xmm0); 4156 movdqu(xmm0, src); 4157 } else { 4158 movdqu(src, xmm0); 4159 movss(xmm0, nds); 4160 vandps(xmm0, xmm0, negate_field, vector_len); 4161 movss(dst, xmm0); 4162 movdqu(xmm0, src); 4163 } 4164 } 4165 4166 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4167 int dst_enc = dst->encoding(); 4168 int nds_enc = nds->encoding(); 4169 int src_enc = src->encoding(); 4170 if ((dst_enc < 16) && (nds_enc < 16)) { 4171 vandpd(dst, nds, negate_field, vector_len); 4172 } else if ((src_enc < 16) && (dst_enc < 16)) { 4173 movsd(src, nds); 4174 vandpd(dst, src, negate_field, vector_len); 4175 } else if (src_enc < 16) { 4176 movsd(src, nds); 4177 vandpd(src, src, negate_field, vector_len); 4178 movsd(dst, src); 4179 } else if (dst_enc < 16) { 4180 movdqu(src, xmm0); 4181 movsd(xmm0, nds); 4182 vandpd(dst, xmm0, negate_field, vector_len); 4183 movdqu(xmm0, src); 4184 } else if (nds_enc < 16) { 4185 movdqu(src, xmm0); 4186 vandpd(xmm0, nds, negate_field, vector_len); 4187 movsd(dst, xmm0); 4188 movdqu(xmm0, src); 4189 } else { 4190 movdqu(src, xmm0); 4191 movsd(xmm0, nds); 4192 vandpd(xmm0, xmm0, negate_field, vector_len); 4193 movsd(dst, xmm0); 4194 movdqu(xmm0, src); 4195 } 4196 } 4197 4198 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4199 int dst_enc = dst->encoding(); 4200 int nds_enc = nds->encoding(); 4201 int src_enc = src->encoding(); 4202 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4203 Assembler::vpaddb(dst, nds, src, vector_len); 4204 } else if ((dst_enc < 16) && (src_enc < 16)) { 4205 Assembler::vpaddb(dst, dst, src, vector_len); 4206 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4207 // use nds as scratch for src 4208 evmovdqul(nds, src, Assembler::AVX_512bit); 4209 Assembler::vpaddb(dst, dst, nds, vector_len); 4210 } else if ((src_enc < 16) && (nds_enc < 16)) { 4211 // use nds as scratch for dst 4212 evmovdqul(nds, dst, Assembler::AVX_512bit); 4213 Assembler::vpaddb(nds, nds, src, vector_len); 4214 evmovdqul(dst, nds, Assembler::AVX_512bit); 4215 } else if (dst_enc < 16) { 4216 // use nds as scatch for xmm0 to hold src 4217 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4218 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4219 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4220 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4221 } else { 4222 // worse case scenario, all regs are in the upper bank 4223 subptr(rsp, 64); 4224 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4225 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4226 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4227 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4228 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4229 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4230 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4231 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4232 addptr(rsp, 64); 4233 } 4234 } 4235 4236 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4237 int dst_enc = dst->encoding(); 4238 int nds_enc = nds->encoding(); 4239 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4240 Assembler::vpaddb(dst, nds, src, vector_len); 4241 } else if (dst_enc < 16) { 4242 Assembler::vpaddb(dst, dst, src, vector_len); 4243 } else if (nds_enc < 16) { 4244 // implies dst_enc in upper bank with src as scratch 4245 evmovdqul(nds, dst, Assembler::AVX_512bit); 4246 Assembler::vpaddb(nds, nds, src, vector_len); 4247 evmovdqul(dst, nds, Assembler::AVX_512bit); 4248 } else { 4249 // worse case scenario, all regs in upper bank 4250 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4251 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4252 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4253 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4254 } 4255 } 4256 4257 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4258 int dst_enc = dst->encoding(); 4259 int nds_enc = nds->encoding(); 4260 int src_enc = src->encoding(); 4261 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4262 Assembler::vpaddw(dst, nds, src, vector_len); 4263 } else if ((dst_enc < 16) && (src_enc < 16)) { 4264 Assembler::vpaddw(dst, dst, src, vector_len); 4265 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4266 // use nds as scratch for src 4267 evmovdqul(nds, src, Assembler::AVX_512bit); 4268 Assembler::vpaddw(dst, dst, nds, vector_len); 4269 } else if ((src_enc < 16) && (nds_enc < 16)) { 4270 // use nds as scratch for dst 4271 evmovdqul(nds, dst, Assembler::AVX_512bit); 4272 Assembler::vpaddw(nds, nds, src, vector_len); 4273 evmovdqul(dst, nds, Assembler::AVX_512bit); 4274 } else if (dst_enc < 16) { 4275 // use nds as scatch for xmm0 to hold src 4276 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4277 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4278 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4279 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4280 } else { 4281 // worse case scenario, all regs are in the upper bank 4282 subptr(rsp, 64); 4283 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4284 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4285 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4286 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4287 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4288 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4289 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4290 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4291 addptr(rsp, 64); 4292 } 4293 } 4294 4295 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4296 int dst_enc = dst->encoding(); 4297 int nds_enc = nds->encoding(); 4298 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4299 Assembler::vpaddw(dst, nds, src, vector_len); 4300 } else if (dst_enc < 16) { 4301 Assembler::vpaddw(dst, dst, src, vector_len); 4302 } else if (nds_enc < 16) { 4303 // implies dst_enc in upper bank with src as scratch 4304 evmovdqul(nds, dst, Assembler::AVX_512bit); 4305 Assembler::vpaddw(nds, nds, src, vector_len); 4306 evmovdqul(dst, nds, Assembler::AVX_512bit); 4307 } else { 4308 // worse case scenario, all regs in upper bank 4309 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4310 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4311 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4312 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4313 } 4314 } 4315 4316 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4317 if (reachable(src)) { 4318 Assembler::vpand(dst, nds, as_Address(src), vector_len); 4319 } else { 4320 lea(rscratch1, src); 4321 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len); 4322 } 4323 } 4324 4325 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4326 int dst_enc = dst->encoding(); 4327 int src_enc = src->encoding(); 4328 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4329 Assembler::vpbroadcastw(dst, src); 4330 } else if ((dst_enc < 16) && (src_enc < 16)) { 4331 Assembler::vpbroadcastw(dst, src); 4332 } else if (src_enc < 16) { 4333 subptr(rsp, 64); 4334 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4335 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4336 Assembler::vpbroadcastw(xmm0, src); 4337 movdqu(dst, xmm0); 4338 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4339 addptr(rsp, 64); 4340 } else if (dst_enc < 16) { 4341 subptr(rsp, 64); 4342 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4343 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4344 Assembler::vpbroadcastw(dst, xmm0); 4345 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4346 addptr(rsp, 64); 4347 } else { 4348 subptr(rsp, 64); 4349 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4350 subptr(rsp, 64); 4351 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4352 movdqu(xmm0, src); 4353 movdqu(xmm1, dst); 4354 Assembler::vpbroadcastw(xmm1, xmm0); 4355 movdqu(dst, xmm1); 4356 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4357 addptr(rsp, 64); 4358 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4359 addptr(rsp, 64); 4360 } 4361 } 4362 4363 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4364 int dst_enc = dst->encoding(); 4365 int nds_enc = nds->encoding(); 4366 int src_enc = src->encoding(); 4367 assert(dst_enc == nds_enc, ""); 4368 if ((dst_enc < 16) && (src_enc < 16)) { 4369 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4370 } else if (src_enc < 16) { 4371 subptr(rsp, 64); 4372 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4373 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4374 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4375 movdqu(dst, xmm0); 4376 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4377 addptr(rsp, 64); 4378 } else if (dst_enc < 16) { 4379 subptr(rsp, 64); 4380 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4381 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4382 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4383 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4384 addptr(rsp, 64); 4385 } else { 4386 subptr(rsp, 64); 4387 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4388 subptr(rsp, 64); 4389 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4390 movdqu(xmm0, src); 4391 movdqu(xmm1, dst); 4392 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4393 movdqu(dst, xmm1); 4394 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4395 addptr(rsp, 64); 4396 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4397 addptr(rsp, 64); 4398 } 4399 } 4400 4401 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4402 int dst_enc = dst->encoding(); 4403 int nds_enc = nds->encoding(); 4404 int src_enc = src->encoding(); 4405 assert(dst_enc == nds_enc, ""); 4406 if ((dst_enc < 16) && (src_enc < 16)) { 4407 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4408 } else if (src_enc < 16) { 4409 subptr(rsp, 64); 4410 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4411 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4412 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4413 movdqu(dst, xmm0); 4414 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4415 addptr(rsp, 64); 4416 } else if (dst_enc < 16) { 4417 subptr(rsp, 64); 4418 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4419 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4420 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4421 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4422 addptr(rsp, 64); 4423 } else { 4424 subptr(rsp, 64); 4425 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4426 subptr(rsp, 64); 4427 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4428 movdqu(xmm0, src); 4429 movdqu(xmm1, dst); 4430 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4431 movdqu(dst, xmm1); 4432 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4433 addptr(rsp, 64); 4434 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4435 addptr(rsp, 64); 4436 } 4437 } 4438 4439 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4440 int dst_enc = dst->encoding(); 4441 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4442 Assembler::vpmovzxbw(dst, src, vector_len); 4443 } else if (dst_enc < 16) { 4444 Assembler::vpmovzxbw(dst, src, vector_len); 4445 } else { 4446 subptr(rsp, 64); 4447 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4448 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4449 Assembler::vpmovzxbw(xmm0, src, vector_len); 4450 movdqu(dst, xmm0); 4451 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4452 addptr(rsp, 64); 4453 } 4454 } 4455 4456 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4457 int src_enc = src->encoding(); 4458 if (src_enc < 16) { 4459 Assembler::vpmovmskb(dst, src); 4460 } else { 4461 subptr(rsp, 64); 4462 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4463 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4464 Assembler::vpmovmskb(dst, xmm0); 4465 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4466 addptr(rsp, 64); 4467 } 4468 } 4469 4470 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4471 int dst_enc = dst->encoding(); 4472 int nds_enc = nds->encoding(); 4473 int src_enc = src->encoding(); 4474 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4475 Assembler::vpmullw(dst, nds, src, vector_len); 4476 } else if ((dst_enc < 16) && (src_enc < 16)) { 4477 Assembler::vpmullw(dst, dst, src, vector_len); 4478 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4479 // use nds as scratch for src 4480 evmovdqul(nds, src, Assembler::AVX_512bit); 4481 Assembler::vpmullw(dst, dst, nds, vector_len); 4482 } else if ((src_enc < 16) && (nds_enc < 16)) { 4483 // use nds as scratch for dst 4484 evmovdqul(nds, dst, Assembler::AVX_512bit); 4485 Assembler::vpmullw(nds, nds, src, vector_len); 4486 evmovdqul(dst, nds, Assembler::AVX_512bit); 4487 } else if (dst_enc < 16) { 4488 // use nds as scatch for xmm0 to hold src 4489 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4490 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4491 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4492 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4493 } else { 4494 // worse case scenario, all regs are in the upper bank 4495 subptr(rsp, 64); 4496 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4497 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4498 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4499 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4500 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4501 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4502 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4503 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4504 addptr(rsp, 64); 4505 } 4506 } 4507 4508 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4509 int dst_enc = dst->encoding(); 4510 int nds_enc = nds->encoding(); 4511 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4512 Assembler::vpmullw(dst, nds, src, vector_len); 4513 } else if (dst_enc < 16) { 4514 Assembler::vpmullw(dst, dst, src, vector_len); 4515 } else if (nds_enc < 16) { 4516 // implies dst_enc in upper bank with src as scratch 4517 evmovdqul(nds, dst, Assembler::AVX_512bit); 4518 Assembler::vpmullw(nds, nds, src, vector_len); 4519 evmovdqul(dst, nds, Assembler::AVX_512bit); 4520 } else { 4521 // worse case scenario, all regs in upper bank 4522 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4523 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4524 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4525 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4526 } 4527 } 4528 4529 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4530 int dst_enc = dst->encoding(); 4531 int nds_enc = nds->encoding(); 4532 int src_enc = src->encoding(); 4533 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4534 Assembler::vpsubb(dst, nds, src, vector_len); 4535 } else if ((dst_enc < 16) && (src_enc < 16)) { 4536 Assembler::vpsubb(dst, dst, src, vector_len); 4537 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4538 // use nds as scratch for src 4539 evmovdqul(nds, src, Assembler::AVX_512bit); 4540 Assembler::vpsubb(dst, dst, nds, vector_len); 4541 } else if ((src_enc < 16) && (nds_enc < 16)) { 4542 // use nds as scratch for dst 4543 evmovdqul(nds, dst, Assembler::AVX_512bit); 4544 Assembler::vpsubb(nds, nds, src, vector_len); 4545 evmovdqul(dst, nds, Assembler::AVX_512bit); 4546 } else if (dst_enc < 16) { 4547 // use nds as scatch for xmm0 to hold src 4548 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4549 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4550 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4551 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4552 } else { 4553 // worse case scenario, all regs are in the upper bank 4554 subptr(rsp, 64); 4555 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4556 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4557 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4558 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4559 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4560 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4561 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4562 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4563 addptr(rsp, 64); 4564 } 4565 } 4566 4567 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4568 int dst_enc = dst->encoding(); 4569 int nds_enc = nds->encoding(); 4570 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4571 Assembler::vpsubb(dst, nds, src, vector_len); 4572 } else if (dst_enc < 16) { 4573 Assembler::vpsubb(dst, dst, src, vector_len); 4574 } else if (nds_enc < 16) { 4575 // implies dst_enc in upper bank with src as scratch 4576 evmovdqul(nds, dst, Assembler::AVX_512bit); 4577 Assembler::vpsubb(nds, nds, src, vector_len); 4578 evmovdqul(dst, nds, Assembler::AVX_512bit); 4579 } else { 4580 // worse case scenario, all regs in upper bank 4581 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4582 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4583 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4584 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4585 } 4586 } 4587 4588 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4589 int dst_enc = dst->encoding(); 4590 int nds_enc = nds->encoding(); 4591 int src_enc = src->encoding(); 4592 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4593 Assembler::vpsubw(dst, nds, src, vector_len); 4594 } else if ((dst_enc < 16) && (src_enc < 16)) { 4595 Assembler::vpsubw(dst, dst, src, vector_len); 4596 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4597 // use nds as scratch for src 4598 evmovdqul(nds, src, Assembler::AVX_512bit); 4599 Assembler::vpsubw(dst, dst, nds, vector_len); 4600 } else if ((src_enc < 16) && (nds_enc < 16)) { 4601 // use nds as scratch for dst 4602 evmovdqul(nds, dst, Assembler::AVX_512bit); 4603 Assembler::vpsubw(nds, nds, src, vector_len); 4604 evmovdqul(dst, nds, Assembler::AVX_512bit); 4605 } else if (dst_enc < 16) { 4606 // use nds as scatch for xmm0 to hold src 4607 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4608 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4609 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4610 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4611 } else { 4612 // worse case scenario, all regs are in the upper bank 4613 subptr(rsp, 64); 4614 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4615 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4616 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4617 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4618 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4619 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4620 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4621 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4622 addptr(rsp, 64); 4623 } 4624 } 4625 4626 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4627 int dst_enc = dst->encoding(); 4628 int nds_enc = nds->encoding(); 4629 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4630 Assembler::vpsubw(dst, nds, src, vector_len); 4631 } else if (dst_enc < 16) { 4632 Assembler::vpsubw(dst, dst, src, vector_len); 4633 } else if (nds_enc < 16) { 4634 // implies dst_enc in upper bank with src as scratch 4635 evmovdqul(nds, dst, Assembler::AVX_512bit); 4636 Assembler::vpsubw(nds, nds, src, vector_len); 4637 evmovdqul(dst, nds, Assembler::AVX_512bit); 4638 } else { 4639 // worse case scenario, all regs in upper bank 4640 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4641 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4642 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4643 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4644 } 4645 } 4646 4647 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4648 int dst_enc = dst->encoding(); 4649 int nds_enc = nds->encoding(); 4650 int shift_enc = shift->encoding(); 4651 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4652 Assembler::vpsraw(dst, nds, shift, vector_len); 4653 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4654 Assembler::vpsraw(dst, dst, shift, vector_len); 4655 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4656 // use nds_enc as scratch with shift 4657 evmovdqul(nds, shift, Assembler::AVX_512bit); 4658 Assembler::vpsraw(dst, dst, nds, vector_len); 4659 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4660 // use nds as scratch with dst 4661 evmovdqul(nds, dst, Assembler::AVX_512bit); 4662 Assembler::vpsraw(nds, nds, shift, vector_len); 4663 evmovdqul(dst, nds, Assembler::AVX_512bit); 4664 } else if (dst_enc < 16) { 4665 // use nds to save a copy of xmm0 and hold shift 4666 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4667 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4668 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4669 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4670 } else if (nds_enc < 16) { 4671 // use nds as dest as temps 4672 evmovdqul(nds, dst, Assembler::AVX_512bit); 4673 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4674 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4675 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4676 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4677 evmovdqul(dst, nds, Assembler::AVX_512bit); 4678 } else { 4679 // worse case scenario, all regs are in the upper bank 4680 subptr(rsp, 64); 4681 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4682 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4683 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4684 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4685 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4686 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4687 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4688 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4689 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4690 addptr(rsp, 64); 4691 } 4692 } 4693 4694 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4695 int dst_enc = dst->encoding(); 4696 int nds_enc = nds->encoding(); 4697 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4698 Assembler::vpsraw(dst, nds, shift, vector_len); 4699 } else if (dst_enc < 16) { 4700 Assembler::vpsraw(dst, dst, shift, vector_len); 4701 } else if (nds_enc < 16) { 4702 // use nds as scratch 4703 evmovdqul(nds, dst, Assembler::AVX_512bit); 4704 Assembler::vpsraw(nds, nds, shift, vector_len); 4705 evmovdqul(dst, nds, Assembler::AVX_512bit); 4706 } else { 4707 // use nds as scratch for xmm0 4708 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4709 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4710 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4711 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4712 } 4713 } 4714 4715 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4716 int dst_enc = dst->encoding(); 4717 int nds_enc = nds->encoding(); 4718 int shift_enc = shift->encoding(); 4719 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4720 Assembler::vpsrlw(dst, nds, shift, vector_len); 4721 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4722 Assembler::vpsrlw(dst, dst, shift, vector_len); 4723 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4724 // use nds_enc as scratch with shift 4725 evmovdqul(nds, shift, Assembler::AVX_512bit); 4726 Assembler::vpsrlw(dst, dst, nds, vector_len); 4727 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4728 // use nds as scratch with dst 4729 evmovdqul(nds, dst, Assembler::AVX_512bit); 4730 Assembler::vpsrlw(nds, nds, shift, vector_len); 4731 evmovdqul(dst, nds, Assembler::AVX_512bit); 4732 } else if (dst_enc < 16) { 4733 // use nds to save a copy of xmm0 and hold shift 4734 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4735 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4736 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4737 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4738 } else if (nds_enc < 16) { 4739 // use nds as dest as temps 4740 evmovdqul(nds, dst, Assembler::AVX_512bit); 4741 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4742 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4743 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4744 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4745 evmovdqul(dst, nds, Assembler::AVX_512bit); 4746 } else { 4747 // worse case scenario, all regs are in the upper bank 4748 subptr(rsp, 64); 4749 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4750 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4751 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4752 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4753 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4754 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4755 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4756 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4757 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4758 addptr(rsp, 64); 4759 } 4760 } 4761 4762 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4763 int dst_enc = dst->encoding(); 4764 int nds_enc = nds->encoding(); 4765 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4766 Assembler::vpsrlw(dst, nds, shift, vector_len); 4767 } else if (dst_enc < 16) { 4768 Assembler::vpsrlw(dst, dst, shift, vector_len); 4769 } else if (nds_enc < 16) { 4770 // use nds as scratch 4771 evmovdqul(nds, dst, Assembler::AVX_512bit); 4772 Assembler::vpsrlw(nds, nds, shift, vector_len); 4773 evmovdqul(dst, nds, Assembler::AVX_512bit); 4774 } else { 4775 // use nds as scratch for xmm0 4776 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4777 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4778 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4779 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4780 } 4781 } 4782 4783 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4784 int dst_enc = dst->encoding(); 4785 int nds_enc = nds->encoding(); 4786 int shift_enc = shift->encoding(); 4787 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4788 Assembler::vpsllw(dst, nds, shift, vector_len); 4789 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4790 Assembler::vpsllw(dst, dst, shift, vector_len); 4791 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4792 // use nds_enc as scratch with shift 4793 evmovdqul(nds, shift, Assembler::AVX_512bit); 4794 Assembler::vpsllw(dst, dst, nds, vector_len); 4795 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4796 // use nds as scratch with dst 4797 evmovdqul(nds, dst, Assembler::AVX_512bit); 4798 Assembler::vpsllw(nds, nds, shift, vector_len); 4799 evmovdqul(dst, nds, Assembler::AVX_512bit); 4800 } else if (dst_enc < 16) { 4801 // use nds to save a copy of xmm0 and hold shift 4802 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4803 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4804 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4805 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4806 } else if (nds_enc < 16) { 4807 // use nds as dest as temps 4808 evmovdqul(nds, dst, Assembler::AVX_512bit); 4809 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4810 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4811 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4812 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4813 evmovdqul(dst, nds, Assembler::AVX_512bit); 4814 } else { 4815 // worse case scenario, all regs are in the upper bank 4816 subptr(rsp, 64); 4817 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4818 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4819 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4820 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4821 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4822 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4823 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4824 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4825 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4826 addptr(rsp, 64); 4827 } 4828 } 4829 4830 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4831 int dst_enc = dst->encoding(); 4832 int nds_enc = nds->encoding(); 4833 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4834 Assembler::vpsllw(dst, nds, shift, vector_len); 4835 } else if (dst_enc < 16) { 4836 Assembler::vpsllw(dst, dst, shift, vector_len); 4837 } else if (nds_enc < 16) { 4838 // use nds as scratch 4839 evmovdqul(nds, dst, Assembler::AVX_512bit); 4840 Assembler::vpsllw(nds, nds, shift, vector_len); 4841 evmovdqul(dst, nds, Assembler::AVX_512bit); 4842 } else { 4843 // use nds as scratch for xmm0 4844 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4845 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4846 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4847 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4848 } 4849 } 4850 4851 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4852 int dst_enc = dst->encoding(); 4853 int src_enc = src->encoding(); 4854 if ((dst_enc < 16) && (src_enc < 16)) { 4855 Assembler::vptest(dst, src); 4856 } else if (src_enc < 16) { 4857 subptr(rsp, 64); 4858 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4859 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4860 Assembler::vptest(xmm0, src); 4861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4862 addptr(rsp, 64); 4863 } else if (dst_enc < 16) { 4864 subptr(rsp, 64); 4865 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4866 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4867 Assembler::vptest(dst, xmm0); 4868 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4869 addptr(rsp, 64); 4870 } else { 4871 subptr(rsp, 64); 4872 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4873 subptr(rsp, 64); 4874 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4875 movdqu(xmm0, src); 4876 movdqu(xmm1, dst); 4877 Assembler::vptest(xmm1, xmm0); 4878 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4879 addptr(rsp, 64); 4880 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4881 addptr(rsp, 64); 4882 } 4883 } 4884 4885 // This instruction exists within macros, ergo we cannot control its input 4886 // when emitted through those patterns. 4887 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4888 if (VM_Version::supports_avx512nobw()) { 4889 int dst_enc = dst->encoding(); 4890 int src_enc = src->encoding(); 4891 if (dst_enc == src_enc) { 4892 if (dst_enc < 16) { 4893 Assembler::punpcklbw(dst, src); 4894 } else { 4895 subptr(rsp, 64); 4896 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4897 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4898 Assembler::punpcklbw(xmm0, xmm0); 4899 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4900 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4901 addptr(rsp, 64); 4902 } 4903 } else { 4904 if ((src_enc < 16) && (dst_enc < 16)) { 4905 Assembler::punpcklbw(dst, src); 4906 } else if (src_enc < 16) { 4907 subptr(rsp, 64); 4908 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4909 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4910 Assembler::punpcklbw(xmm0, src); 4911 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4912 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4913 addptr(rsp, 64); 4914 } else if (dst_enc < 16) { 4915 subptr(rsp, 64); 4916 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4917 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4918 Assembler::punpcklbw(dst, xmm0); 4919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4920 addptr(rsp, 64); 4921 } else { 4922 subptr(rsp, 64); 4923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4924 subptr(rsp, 64); 4925 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4926 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4927 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4928 Assembler::punpcklbw(xmm0, xmm1); 4929 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4930 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4931 addptr(rsp, 64); 4932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4933 addptr(rsp, 64); 4934 } 4935 } 4936 } else { 4937 Assembler::punpcklbw(dst, src); 4938 } 4939 } 4940 4941 // This instruction exists within macros, ergo we cannot control its input 4942 // when emitted through those patterns. 4943 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4944 if (VM_Version::supports_avx512nobw()) { 4945 int dst_enc = dst->encoding(); 4946 int src_enc = src->encoding(); 4947 if (dst_enc == src_enc) { 4948 if (dst_enc < 16) { 4949 Assembler::pshuflw(dst, src, mode); 4950 } else { 4951 subptr(rsp, 64); 4952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4953 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4954 Assembler::pshuflw(xmm0, xmm0, mode); 4955 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4957 addptr(rsp, 64); 4958 } 4959 } else { 4960 if ((src_enc < 16) && (dst_enc < 16)) { 4961 Assembler::pshuflw(dst, src, mode); 4962 } else if (src_enc < 16) { 4963 subptr(rsp, 64); 4964 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4965 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4966 Assembler::pshuflw(xmm0, src, mode); 4967 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4968 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4969 addptr(rsp, 64); 4970 } else if (dst_enc < 16) { 4971 subptr(rsp, 64); 4972 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4973 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4974 Assembler::pshuflw(dst, xmm0, mode); 4975 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4976 addptr(rsp, 64); 4977 } else { 4978 subptr(rsp, 64); 4979 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4980 subptr(rsp, 64); 4981 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4982 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4983 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4984 Assembler::pshuflw(xmm0, xmm1, mode); 4985 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4986 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4987 addptr(rsp, 64); 4988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4989 addptr(rsp, 64); 4990 } 4991 } 4992 } else { 4993 Assembler::pshuflw(dst, src, mode); 4994 } 4995 } 4996 4997 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4998 if (reachable(src)) { 4999 vandpd(dst, nds, as_Address(src), vector_len); 5000 } else { 5001 lea(rscratch1, src); 5002 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 5003 } 5004 } 5005 5006 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5007 if (reachable(src)) { 5008 vandps(dst, nds, as_Address(src), vector_len); 5009 } else { 5010 lea(rscratch1, src); 5011 vandps(dst, nds, Address(rscratch1, 0), vector_len); 5012 } 5013 } 5014 5015 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5016 if (reachable(src)) { 5017 vdivsd(dst, nds, as_Address(src)); 5018 } else { 5019 lea(rscratch1, src); 5020 vdivsd(dst, nds, Address(rscratch1, 0)); 5021 } 5022 } 5023 5024 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5025 if (reachable(src)) { 5026 vdivss(dst, nds, as_Address(src)); 5027 } else { 5028 lea(rscratch1, src); 5029 vdivss(dst, nds, Address(rscratch1, 0)); 5030 } 5031 } 5032 5033 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5034 if (reachable(src)) { 5035 vmulsd(dst, nds, as_Address(src)); 5036 } else { 5037 lea(rscratch1, src); 5038 vmulsd(dst, nds, Address(rscratch1, 0)); 5039 } 5040 } 5041 5042 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5043 if (reachable(src)) { 5044 vmulss(dst, nds, as_Address(src)); 5045 } else { 5046 lea(rscratch1, src); 5047 vmulss(dst, nds, Address(rscratch1, 0)); 5048 } 5049 } 5050 5051 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5052 if (reachable(src)) { 5053 vsubsd(dst, nds, as_Address(src)); 5054 } else { 5055 lea(rscratch1, src); 5056 vsubsd(dst, nds, Address(rscratch1, 0)); 5057 } 5058 } 5059 5060 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5061 if (reachable(src)) { 5062 vsubss(dst, nds, as_Address(src)); 5063 } else { 5064 lea(rscratch1, src); 5065 vsubss(dst, nds, Address(rscratch1, 0)); 5066 } 5067 } 5068 5069 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5070 int nds_enc = nds->encoding(); 5071 int dst_enc = dst->encoding(); 5072 bool dst_upper_bank = (dst_enc > 15); 5073 bool nds_upper_bank = (nds_enc > 15); 5074 if (VM_Version::supports_avx512novl() && 5075 (nds_upper_bank || dst_upper_bank)) { 5076 if (dst_upper_bank) { 5077 subptr(rsp, 64); 5078 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5079 movflt(xmm0, nds); 5080 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5081 movflt(dst, xmm0); 5082 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5083 addptr(rsp, 64); 5084 } else { 5085 movflt(dst, nds); 5086 vxorps(dst, dst, src, Assembler::AVX_128bit); 5087 } 5088 } else { 5089 vxorps(dst, nds, src, Assembler::AVX_128bit); 5090 } 5091 } 5092 5093 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5094 int nds_enc = nds->encoding(); 5095 int dst_enc = dst->encoding(); 5096 bool dst_upper_bank = (dst_enc > 15); 5097 bool nds_upper_bank = (nds_enc > 15); 5098 if (VM_Version::supports_avx512novl() && 5099 (nds_upper_bank || dst_upper_bank)) { 5100 if (dst_upper_bank) { 5101 subptr(rsp, 64); 5102 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5103 movdbl(xmm0, nds); 5104 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5105 movdbl(dst, xmm0); 5106 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5107 addptr(rsp, 64); 5108 } else { 5109 movdbl(dst, nds); 5110 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5111 } 5112 } else { 5113 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5114 } 5115 } 5116 5117 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5118 if (reachable(src)) { 5119 vxorpd(dst, nds, as_Address(src), vector_len); 5120 } else { 5121 lea(rscratch1, src); 5122 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5123 } 5124 } 5125 5126 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5127 if (reachable(src)) { 5128 vxorps(dst, nds, as_Address(src), vector_len); 5129 } else { 5130 lea(rscratch1, src); 5131 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5132 } 5133 } 5134 5135 5136 ////////////////////////////////////////////////////////////////////////////////// 5137 #if INCLUDE_ALL_GCS 5138 5139 void MacroAssembler::g1_write_barrier_pre(Register obj, 5140 Register pre_val, 5141 Register thread, 5142 Register tmp, 5143 bool tosca_live, 5144 bool expand_call) { 5145 5146 // If expand_call is true then we expand the call_VM_leaf macro 5147 // directly to skip generating the check by 5148 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5149 5150 #ifdef _LP64 5151 assert(thread == r15_thread, "must be"); 5152 #endif // _LP64 5153 5154 Label done; 5155 Label runtime; 5156 5157 assert(pre_val != noreg, "check this code"); 5158 5159 if (obj != noreg) { 5160 assert_different_registers(obj, pre_val, tmp); 5161 assert(pre_val != rax, "check this code"); 5162 } 5163 5164 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5165 SATBMarkQueue::byte_offset_of_active())); 5166 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5167 SATBMarkQueue::byte_offset_of_index())); 5168 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5169 SATBMarkQueue::byte_offset_of_buf())); 5170 5171 5172 // Is marking active? 5173 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5174 cmpl(in_progress, 0); 5175 } else { 5176 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5177 cmpb(in_progress, 0); 5178 } 5179 jcc(Assembler::equal, done); 5180 5181 // Do we need to load the previous value? 5182 if (obj != noreg) { 5183 load_heap_oop(pre_val, Address(obj, 0)); 5184 } 5185 5186 // Is the previous value null? 5187 cmpptr(pre_val, (int32_t) NULL_WORD); 5188 jcc(Assembler::equal, done); 5189 5190 // Can we store original value in the thread's buffer? 5191 // Is index == 0? 5192 // (The index field is typed as size_t.) 5193 5194 movptr(tmp, index); // tmp := *index_adr 5195 cmpptr(tmp, 0); // tmp == 0? 5196 jcc(Assembler::equal, runtime); // If yes, goto runtime 5197 5198 subptr(tmp, wordSize); // tmp := tmp - wordSize 5199 movptr(index, tmp); // *index_adr := tmp 5200 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5201 5202 // Record the previous value 5203 movptr(Address(tmp, 0), pre_val); 5204 jmp(done); 5205 5206 bind(runtime); 5207 // save the live input values 5208 if(tosca_live) push(rax); 5209 5210 if (obj != noreg && obj != rax) 5211 push(obj); 5212 5213 if (pre_val != rax) 5214 push(pre_val); 5215 5216 // Calling the runtime using the regular call_VM_leaf mechanism generates 5217 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5218 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5219 // 5220 // If we care generating the pre-barrier without a frame (e.g. in the 5221 // intrinsified Reference.get() routine) then ebp might be pointing to 5222 // the caller frame and so this check will most likely fail at runtime. 5223 // 5224 // Expanding the call directly bypasses the generation of the check. 5225 // So when we do not have have a full interpreter frame on the stack 5226 // expand_call should be passed true. 5227 5228 NOT_LP64( push(thread); ) 5229 5230 if (expand_call) { 5231 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5232 pass_arg1(this, thread); 5233 pass_arg0(this, pre_val); 5234 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5235 } else { 5236 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5237 } 5238 5239 NOT_LP64( pop(thread); ) 5240 5241 // save the live input values 5242 if (pre_val != rax) 5243 pop(pre_val); 5244 5245 if (obj != noreg && obj != rax) 5246 pop(obj); 5247 5248 if(tosca_live) pop(rax); 5249 5250 bind(done); 5251 } 5252 5253 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5254 Register new_val, 5255 Register thread, 5256 Register tmp, 5257 Register tmp2) { 5258 #ifdef _LP64 5259 assert(thread == r15_thread, "must be"); 5260 #endif // _LP64 5261 5262 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5263 DirtyCardQueue::byte_offset_of_index())); 5264 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5265 DirtyCardQueue::byte_offset_of_buf())); 5266 5267 CardTableModRefBS* ct = 5268 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5269 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5270 5271 Label done; 5272 Label runtime; 5273 5274 // Does store cross heap regions? 5275 5276 movptr(tmp, store_addr); 5277 xorptr(tmp, new_val); 5278 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5279 jcc(Assembler::equal, done); 5280 5281 // crosses regions, storing NULL? 5282 5283 cmpptr(new_val, (int32_t) NULL_WORD); 5284 jcc(Assembler::equal, done); 5285 5286 // storing region crossing non-NULL, is card already dirty? 5287 5288 const Register card_addr = tmp; 5289 const Register cardtable = tmp2; 5290 5291 movptr(card_addr, store_addr); 5292 shrptr(card_addr, CardTableModRefBS::card_shift); 5293 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5294 // a valid address and therefore is not properly handled by the relocation code. 5295 movptr(cardtable, (intptr_t)ct->byte_map_base); 5296 addptr(card_addr, cardtable); 5297 5298 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5299 jcc(Assembler::equal, done); 5300 5301 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5302 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5303 jcc(Assembler::equal, done); 5304 5305 5306 // storing a region crossing, non-NULL oop, card is clean. 5307 // dirty card and log. 5308 5309 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5310 5311 cmpl(queue_index, 0); 5312 jcc(Assembler::equal, runtime); 5313 subl(queue_index, wordSize); 5314 movptr(tmp2, buffer); 5315 #ifdef _LP64 5316 movslq(rscratch1, queue_index); 5317 addq(tmp2, rscratch1); 5318 movq(Address(tmp2, 0), card_addr); 5319 #else 5320 addl(tmp2, queue_index); 5321 movl(Address(tmp2, 0), card_addr); 5322 #endif 5323 jmp(done); 5324 5325 bind(runtime); 5326 // save the live input values 5327 push(store_addr); 5328 push(new_val); 5329 #ifdef _LP64 5330 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5331 #else 5332 push(thread); 5333 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5334 pop(thread); 5335 #endif 5336 pop(new_val); 5337 pop(store_addr); 5338 5339 bind(done); 5340 } 5341 5342 #endif // INCLUDE_ALL_GCS 5343 ////////////////////////////////////////////////////////////////////////////////// 5344 5345 5346 void MacroAssembler::store_check(Register obj, Address dst) { 5347 store_check(obj); 5348 } 5349 5350 void MacroAssembler::store_check(Register obj) { 5351 // Does a store check for the oop in register obj. The content of 5352 // register obj is destroyed afterwards. 5353 BarrierSet* bs = Universe::heap()->barrier_set(); 5354 assert(bs->kind() == BarrierSet::CardTableForRS || 5355 bs->kind() == BarrierSet::CardTableExtension, 5356 "Wrong barrier set kind"); 5357 5358 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5359 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5360 5361 shrptr(obj, CardTableModRefBS::card_shift); 5362 5363 Address card_addr; 5364 5365 // The calculation for byte_map_base is as follows: 5366 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5367 // So this essentially converts an address to a displacement and it will 5368 // never need to be relocated. On 64bit however the value may be too 5369 // large for a 32bit displacement. 5370 intptr_t disp = (intptr_t) ct->byte_map_base; 5371 if (is_simm32(disp)) { 5372 card_addr = Address(noreg, obj, Address::times_1, disp); 5373 } else { 5374 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5375 // displacement and done in a single instruction given favorable mapping and a 5376 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5377 // entry and that entry is not properly handled by the relocation code. 5378 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5379 Address index(noreg, obj, Address::times_1); 5380 card_addr = as_Address(ArrayAddress(cardtable, index)); 5381 } 5382 5383 int dirty = CardTableModRefBS::dirty_card_val(); 5384 if (UseCondCardMark) { 5385 Label L_already_dirty; 5386 if (UseConcMarkSweepGC) { 5387 membar(Assembler::StoreLoad); 5388 } 5389 cmpb(card_addr, dirty); 5390 jcc(Assembler::equal, L_already_dirty); 5391 movb(card_addr, dirty); 5392 bind(L_already_dirty); 5393 } else { 5394 movb(card_addr, dirty); 5395 } 5396 } 5397 5398 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5399 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5400 } 5401 5402 // Force generation of a 4 byte immediate value even if it fits into 8bit 5403 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5404 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5405 } 5406 5407 void MacroAssembler::subptr(Register dst, Register src) { 5408 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5409 } 5410 5411 // C++ bool manipulation 5412 void MacroAssembler::testbool(Register dst) { 5413 if(sizeof(bool) == 1) 5414 testb(dst, 0xff); 5415 else if(sizeof(bool) == 2) { 5416 // testw implementation needed for two byte bools 5417 ShouldNotReachHere(); 5418 } else if(sizeof(bool) == 4) 5419 testl(dst, dst); 5420 else 5421 // unsupported 5422 ShouldNotReachHere(); 5423 } 5424 5425 void MacroAssembler::testptr(Register dst, Register src) { 5426 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5427 } 5428 5429 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5430 void MacroAssembler::tlab_allocate(Register obj, 5431 Register var_size_in_bytes, 5432 int con_size_in_bytes, 5433 Register t1, 5434 Register t2, 5435 Label& slow_case) { 5436 assert_different_registers(obj, t1, t2); 5437 assert_different_registers(obj, var_size_in_bytes, t1); 5438 Register end = t2; 5439 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5440 5441 verify_tlab(); 5442 5443 NOT_LP64(get_thread(thread)); 5444 5445 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5446 if (var_size_in_bytes == noreg) { 5447 lea(end, Address(obj, con_size_in_bytes)); 5448 } else { 5449 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5450 } 5451 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5452 jcc(Assembler::above, slow_case); 5453 5454 // update the tlab top pointer 5455 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5456 5457 // recover var_size_in_bytes if necessary 5458 if (var_size_in_bytes == end) { 5459 subptr(var_size_in_bytes, obj); 5460 } 5461 verify_tlab(); 5462 } 5463 5464 // Preserves rbx, and rdx. 5465 Register MacroAssembler::tlab_refill(Label& retry, 5466 Label& try_eden, 5467 Label& slow_case) { 5468 Register top = rax; 5469 Register t1 = rcx; // object size 5470 Register t2 = rsi; 5471 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5472 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5473 Label do_refill, discard_tlab; 5474 5475 if (!Universe::heap()->supports_inline_contig_alloc()) { 5476 // No allocation in the shared eden. 5477 jmp(slow_case); 5478 } 5479 5480 NOT_LP64(get_thread(thread_reg)); 5481 5482 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5483 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5484 5485 // calculate amount of free space 5486 subptr(t1, top); 5487 shrptr(t1, LogHeapWordSize); 5488 5489 // Retain tlab and allocate object in shared space if 5490 // the amount free in the tlab is too large to discard. 5491 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5492 jcc(Assembler::lessEqual, discard_tlab); 5493 5494 // Retain 5495 // %%% yuck as movptr... 5496 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5497 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5498 if (TLABStats) { 5499 // increment number of slow_allocations 5500 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5501 } 5502 jmp(try_eden); 5503 5504 bind(discard_tlab); 5505 if (TLABStats) { 5506 // increment number of refills 5507 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5508 // accumulate wastage -- t1 is amount free in tlab 5509 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5510 } 5511 5512 // if tlab is currently allocated (top or end != null) then 5513 // fill [top, end + alignment_reserve) with array object 5514 testptr(top, top); 5515 jcc(Assembler::zero, do_refill); 5516 5517 // set up the mark word 5518 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5519 // set the length to the remaining space 5520 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5521 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5522 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5523 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5524 // set klass to intArrayKlass 5525 // dubious reloc why not an oop reloc? 5526 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5527 // store klass last. concurrent gcs assumes klass length is valid if 5528 // klass field is not null. 5529 store_klass(top, t1); 5530 5531 movptr(t1, top); 5532 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5533 incr_allocated_bytes(thread_reg, t1, 0); 5534 5535 // refill the tlab with an eden allocation 5536 bind(do_refill); 5537 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5538 shlptr(t1, LogHeapWordSize); 5539 // allocate new tlab, address returned in top 5540 eden_allocate(top, t1, 0, t2, slow_case); 5541 5542 // Check that t1 was preserved in eden_allocate. 5543 #ifdef ASSERT 5544 if (UseTLAB) { 5545 Label ok; 5546 Register tsize = rsi; 5547 assert_different_registers(tsize, thread_reg, t1); 5548 push(tsize); 5549 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5550 shlptr(tsize, LogHeapWordSize); 5551 cmpptr(t1, tsize); 5552 jcc(Assembler::equal, ok); 5553 STOP("assert(t1 != tlab size)"); 5554 should_not_reach_here(); 5555 5556 bind(ok); 5557 pop(tsize); 5558 } 5559 #endif 5560 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5561 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5562 addptr(top, t1); 5563 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5564 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5565 5566 if (ZeroTLAB) { 5567 // This is a fast TLAB refill, therefore the GC is not notified of it. 5568 // So compiled code must fill the new TLAB with zeroes. 5569 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5570 zero_memory(top, t1, 0, t2); 5571 } 5572 5573 verify_tlab(); 5574 jmp(retry); 5575 5576 return thread_reg; // for use by caller 5577 } 5578 5579 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5580 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5581 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5582 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5583 Label done; 5584 5585 testptr(length_in_bytes, length_in_bytes); 5586 jcc(Assembler::zero, done); 5587 5588 // initialize topmost word, divide index by 2, check if odd and test if zero 5589 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5590 #ifdef ASSERT 5591 { 5592 Label L; 5593 testptr(length_in_bytes, BytesPerWord - 1); 5594 jcc(Assembler::zero, L); 5595 stop("length must be a multiple of BytesPerWord"); 5596 bind(L); 5597 } 5598 #endif 5599 Register index = length_in_bytes; 5600 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5601 if (UseIncDec) { 5602 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5603 } else { 5604 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5605 shrptr(index, 1); 5606 } 5607 #ifndef _LP64 5608 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5609 { 5610 Label even; 5611 // note: if index was a multiple of 8, then it cannot 5612 // be 0 now otherwise it must have been 0 before 5613 // => if it is even, we don't need to check for 0 again 5614 jcc(Assembler::carryClear, even); 5615 // clear topmost word (no jump would be needed if conditional assignment worked here) 5616 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5617 // index could be 0 now, must check again 5618 jcc(Assembler::zero, done); 5619 bind(even); 5620 } 5621 #endif // !_LP64 5622 // initialize remaining object fields: index is a multiple of 2 now 5623 { 5624 Label loop; 5625 bind(loop); 5626 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5627 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5628 decrement(index); 5629 jcc(Assembler::notZero, loop); 5630 } 5631 5632 bind(done); 5633 } 5634 5635 void MacroAssembler::incr_allocated_bytes(Register thread, 5636 Register var_size_in_bytes, 5637 int con_size_in_bytes, 5638 Register t1) { 5639 if (!thread->is_valid()) { 5640 #ifdef _LP64 5641 thread = r15_thread; 5642 #else 5643 assert(t1->is_valid(), "need temp reg"); 5644 thread = t1; 5645 get_thread(thread); 5646 #endif 5647 } 5648 5649 #ifdef _LP64 5650 if (var_size_in_bytes->is_valid()) { 5651 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5652 } else { 5653 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5654 } 5655 #else 5656 if (var_size_in_bytes->is_valid()) { 5657 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5658 } else { 5659 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5660 } 5661 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5662 #endif 5663 } 5664 5665 // Look up the method for a megamorphic invokeinterface call. 5666 // The target method is determined by <intf_klass, itable_index>. 5667 // The receiver klass is in recv_klass. 5668 // On success, the result will be in method_result, and execution falls through. 5669 // On failure, execution transfers to the given label. 5670 void MacroAssembler::lookup_interface_method(Register recv_klass, 5671 Register intf_klass, 5672 RegisterOrConstant itable_index, 5673 Register method_result, 5674 Register scan_temp, 5675 Label& L_no_such_interface) { 5676 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5677 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5678 "caller must use same register for non-constant itable index as for method"); 5679 5680 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5681 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5682 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5683 int scan_step = itableOffsetEntry::size() * wordSize; 5684 int vte_size = vtableEntry::size_in_bytes(); 5685 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5686 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5687 5688 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5689 5690 // %%% Could store the aligned, prescaled offset in the klassoop. 5691 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5692 5693 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5694 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5695 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5696 5697 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5698 // if (scan->interface() == intf) { 5699 // result = (klass + scan->offset() + itable_index); 5700 // } 5701 // } 5702 Label search, found_method; 5703 5704 for (int peel = 1; peel >= 0; peel--) { 5705 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5706 cmpptr(intf_klass, method_result); 5707 5708 if (peel) { 5709 jccb(Assembler::equal, found_method); 5710 } else { 5711 jccb(Assembler::notEqual, search); 5712 // (invert the test to fall through to found_method...) 5713 } 5714 5715 if (!peel) break; 5716 5717 bind(search); 5718 5719 // Check that the previous entry is non-null. A null entry means that 5720 // the receiver class doesn't implement the interface, and wasn't the 5721 // same as when the caller was compiled. 5722 testptr(method_result, method_result); 5723 jcc(Assembler::zero, L_no_such_interface); 5724 addptr(scan_temp, scan_step); 5725 } 5726 5727 bind(found_method); 5728 5729 // Got a hit. 5730 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5731 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5732 } 5733 5734 5735 // virtual method calling 5736 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5737 RegisterOrConstant vtable_index, 5738 Register method_result) { 5739 const int base = in_bytes(Klass::vtable_start_offset()); 5740 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5741 Address vtable_entry_addr(recv_klass, 5742 vtable_index, Address::times_ptr, 5743 base + vtableEntry::method_offset_in_bytes()); 5744 movptr(method_result, vtable_entry_addr); 5745 } 5746 5747 5748 void MacroAssembler::check_klass_subtype(Register sub_klass, 5749 Register super_klass, 5750 Register temp_reg, 5751 Label& L_success) { 5752 Label L_failure; 5753 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5754 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5755 bind(L_failure); 5756 } 5757 5758 5759 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5760 Register super_klass, 5761 Register temp_reg, 5762 Label* L_success, 5763 Label* L_failure, 5764 Label* L_slow_path, 5765 RegisterOrConstant super_check_offset) { 5766 assert_different_registers(sub_klass, super_klass, temp_reg); 5767 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5768 if (super_check_offset.is_register()) { 5769 assert_different_registers(sub_klass, super_klass, 5770 super_check_offset.as_register()); 5771 } else if (must_load_sco) { 5772 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5773 } 5774 5775 Label L_fallthrough; 5776 int label_nulls = 0; 5777 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5778 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5779 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5780 assert(label_nulls <= 1, "at most one NULL in the batch"); 5781 5782 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5783 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5784 Address super_check_offset_addr(super_klass, sco_offset); 5785 5786 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5787 // range of a jccb. If this routine grows larger, reconsider at 5788 // least some of these. 5789 #define local_jcc(assembler_cond, label) \ 5790 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5791 else jcc( assembler_cond, label) /*omit semi*/ 5792 5793 // Hacked jmp, which may only be used just before L_fallthrough. 5794 #define final_jmp(label) \ 5795 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5796 else jmp(label) /*omit semi*/ 5797 5798 // If the pointers are equal, we are done (e.g., String[] elements). 5799 // This self-check enables sharing of secondary supertype arrays among 5800 // non-primary types such as array-of-interface. Otherwise, each such 5801 // type would need its own customized SSA. 5802 // We move this check to the front of the fast path because many 5803 // type checks are in fact trivially successful in this manner, 5804 // so we get a nicely predicted branch right at the start of the check. 5805 cmpptr(sub_klass, super_klass); 5806 local_jcc(Assembler::equal, *L_success); 5807 5808 // Check the supertype display: 5809 if (must_load_sco) { 5810 // Positive movl does right thing on LP64. 5811 movl(temp_reg, super_check_offset_addr); 5812 super_check_offset = RegisterOrConstant(temp_reg); 5813 } 5814 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5815 cmpptr(super_klass, super_check_addr); // load displayed supertype 5816 5817 // This check has worked decisively for primary supers. 5818 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5819 // (Secondary supers are interfaces and very deeply nested subtypes.) 5820 // This works in the same check above because of a tricky aliasing 5821 // between the super_cache and the primary super display elements. 5822 // (The 'super_check_addr' can address either, as the case requires.) 5823 // Note that the cache is updated below if it does not help us find 5824 // what we need immediately. 5825 // So if it was a primary super, we can just fail immediately. 5826 // Otherwise, it's the slow path for us (no success at this point). 5827 5828 if (super_check_offset.is_register()) { 5829 local_jcc(Assembler::equal, *L_success); 5830 cmpl(super_check_offset.as_register(), sc_offset); 5831 if (L_failure == &L_fallthrough) { 5832 local_jcc(Assembler::equal, *L_slow_path); 5833 } else { 5834 local_jcc(Assembler::notEqual, *L_failure); 5835 final_jmp(*L_slow_path); 5836 } 5837 } else if (super_check_offset.as_constant() == sc_offset) { 5838 // Need a slow path; fast failure is impossible. 5839 if (L_slow_path == &L_fallthrough) { 5840 local_jcc(Assembler::equal, *L_success); 5841 } else { 5842 local_jcc(Assembler::notEqual, *L_slow_path); 5843 final_jmp(*L_success); 5844 } 5845 } else { 5846 // No slow path; it's a fast decision. 5847 if (L_failure == &L_fallthrough) { 5848 local_jcc(Assembler::equal, *L_success); 5849 } else { 5850 local_jcc(Assembler::notEqual, *L_failure); 5851 final_jmp(*L_success); 5852 } 5853 } 5854 5855 bind(L_fallthrough); 5856 5857 #undef local_jcc 5858 #undef final_jmp 5859 } 5860 5861 5862 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5863 Register super_klass, 5864 Register temp_reg, 5865 Register temp2_reg, 5866 Label* L_success, 5867 Label* L_failure, 5868 bool set_cond_codes) { 5869 assert_different_registers(sub_klass, super_klass, temp_reg); 5870 if (temp2_reg != noreg) 5871 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5872 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5873 5874 Label L_fallthrough; 5875 int label_nulls = 0; 5876 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5877 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5878 assert(label_nulls <= 1, "at most one NULL in the batch"); 5879 5880 // a couple of useful fields in sub_klass: 5881 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5882 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5883 Address secondary_supers_addr(sub_klass, ss_offset); 5884 Address super_cache_addr( sub_klass, sc_offset); 5885 5886 // Do a linear scan of the secondary super-klass chain. 5887 // This code is rarely used, so simplicity is a virtue here. 5888 // The repne_scan instruction uses fixed registers, which we must spill. 5889 // Don't worry too much about pre-existing connections with the input regs. 5890 5891 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5892 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5893 5894 // Get super_klass value into rax (even if it was in rdi or rcx). 5895 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5896 if (super_klass != rax || UseCompressedOops) { 5897 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5898 mov(rax, super_klass); 5899 } 5900 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5901 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5902 5903 #ifndef PRODUCT 5904 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5905 ExternalAddress pst_counter_addr((address) pst_counter); 5906 NOT_LP64( incrementl(pst_counter_addr) ); 5907 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5908 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5909 #endif //PRODUCT 5910 5911 // We will consult the secondary-super array. 5912 movptr(rdi, secondary_supers_addr); 5913 // Load the array length. (Positive movl does right thing on LP64.) 5914 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5915 // Skip to start of data. 5916 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5917 5918 // Scan RCX words at [RDI] for an occurrence of RAX. 5919 // Set NZ/Z based on last compare. 5920 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5921 // not change flags (only scas instruction which is repeated sets flags). 5922 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5923 5924 testptr(rax,rax); // Set Z = 0 5925 repne_scan(); 5926 5927 // Unspill the temp. registers: 5928 if (pushed_rdi) pop(rdi); 5929 if (pushed_rcx) pop(rcx); 5930 if (pushed_rax) pop(rax); 5931 5932 if (set_cond_codes) { 5933 // Special hack for the AD files: rdi is guaranteed non-zero. 5934 assert(!pushed_rdi, "rdi must be left non-NULL"); 5935 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5936 } 5937 5938 if (L_failure == &L_fallthrough) 5939 jccb(Assembler::notEqual, *L_failure); 5940 else jcc(Assembler::notEqual, *L_failure); 5941 5942 // Success. Cache the super we found and proceed in triumph. 5943 movptr(super_cache_addr, super_klass); 5944 5945 if (L_success != &L_fallthrough) { 5946 jmp(*L_success); 5947 } 5948 5949 #undef IS_A_TEMP 5950 5951 bind(L_fallthrough); 5952 } 5953 5954 5955 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5956 if (VM_Version::supports_cmov()) { 5957 cmovl(cc, dst, src); 5958 } else { 5959 Label L; 5960 jccb(negate_condition(cc), L); 5961 movl(dst, src); 5962 bind(L); 5963 } 5964 } 5965 5966 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5967 if (VM_Version::supports_cmov()) { 5968 cmovl(cc, dst, src); 5969 } else { 5970 Label L; 5971 jccb(negate_condition(cc), L); 5972 movl(dst, src); 5973 bind(L); 5974 } 5975 } 5976 5977 void MacroAssembler::verify_oop(Register reg, const char* s) { 5978 if (!VerifyOops) return; 5979 5980 // Pass register number to verify_oop_subroutine 5981 const char* b = NULL; 5982 { 5983 ResourceMark rm; 5984 stringStream ss; 5985 ss.print("verify_oop: %s: %s", reg->name(), s); 5986 b = code_string(ss.as_string()); 5987 } 5988 BLOCK_COMMENT("verify_oop {"); 5989 #ifdef _LP64 5990 push(rscratch1); // save r10, trashed by movptr() 5991 #endif 5992 push(rax); // save rax, 5993 push(reg); // pass register argument 5994 ExternalAddress buffer((address) b); 5995 // avoid using pushptr, as it modifies scratch registers 5996 // and our contract is not to modify anything 5997 movptr(rax, buffer.addr()); 5998 push(rax); 5999 // call indirectly to solve generation ordering problem 6000 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6001 call(rax); 6002 // Caller pops the arguments (oop, message) and restores rax, r10 6003 BLOCK_COMMENT("} verify_oop"); 6004 } 6005 6006 6007 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6008 Register tmp, 6009 int offset) { 6010 intptr_t value = *delayed_value_addr; 6011 if (value != 0) 6012 return RegisterOrConstant(value + offset); 6013 6014 // load indirectly to solve generation ordering problem 6015 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6016 6017 #ifdef ASSERT 6018 { Label L; 6019 testptr(tmp, tmp); 6020 if (WizardMode) { 6021 const char* buf = NULL; 6022 { 6023 ResourceMark rm; 6024 stringStream ss; 6025 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6026 buf = code_string(ss.as_string()); 6027 } 6028 jcc(Assembler::notZero, L); 6029 STOP(buf); 6030 } else { 6031 jccb(Assembler::notZero, L); 6032 hlt(); 6033 } 6034 bind(L); 6035 } 6036 #endif 6037 6038 if (offset != 0) 6039 addptr(tmp, offset); 6040 6041 return RegisterOrConstant(tmp); 6042 } 6043 6044 6045 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6046 int extra_slot_offset) { 6047 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6048 int stackElementSize = Interpreter::stackElementSize; 6049 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6050 #ifdef ASSERT 6051 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6052 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6053 #endif 6054 Register scale_reg = noreg; 6055 Address::ScaleFactor scale_factor = Address::no_scale; 6056 if (arg_slot.is_constant()) { 6057 offset += arg_slot.as_constant() * stackElementSize; 6058 } else { 6059 scale_reg = arg_slot.as_register(); 6060 scale_factor = Address::times(stackElementSize); 6061 } 6062 offset += wordSize; // return PC is on stack 6063 return Address(rsp, scale_reg, scale_factor, offset); 6064 } 6065 6066 6067 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6068 if (!VerifyOops) return; 6069 6070 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6071 // Pass register number to verify_oop_subroutine 6072 const char* b = NULL; 6073 { 6074 ResourceMark rm; 6075 stringStream ss; 6076 ss.print("verify_oop_addr: %s", s); 6077 b = code_string(ss.as_string()); 6078 } 6079 #ifdef _LP64 6080 push(rscratch1); // save r10, trashed by movptr() 6081 #endif 6082 push(rax); // save rax, 6083 // addr may contain rsp so we will have to adjust it based on the push 6084 // we just did (and on 64 bit we do two pushes) 6085 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6086 // stores rax into addr which is backwards of what was intended. 6087 if (addr.uses(rsp)) { 6088 lea(rax, addr); 6089 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6090 } else { 6091 pushptr(addr); 6092 } 6093 6094 ExternalAddress buffer((address) b); 6095 // pass msg argument 6096 // avoid using pushptr, as it modifies scratch registers 6097 // and our contract is not to modify anything 6098 movptr(rax, buffer.addr()); 6099 push(rax); 6100 6101 // call indirectly to solve generation ordering problem 6102 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6103 call(rax); 6104 // Caller pops the arguments (addr, message) and restores rax, r10. 6105 } 6106 6107 void MacroAssembler::verify_tlab() { 6108 #ifdef ASSERT 6109 if (UseTLAB && VerifyOops) { 6110 Label next, ok; 6111 Register t1 = rsi; 6112 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6113 6114 push(t1); 6115 NOT_LP64(push(thread_reg)); 6116 NOT_LP64(get_thread(thread_reg)); 6117 6118 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6119 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6120 jcc(Assembler::aboveEqual, next); 6121 STOP("assert(top >= start)"); 6122 should_not_reach_here(); 6123 6124 bind(next); 6125 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6126 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6127 jcc(Assembler::aboveEqual, ok); 6128 STOP("assert(top <= end)"); 6129 should_not_reach_here(); 6130 6131 bind(ok); 6132 NOT_LP64(pop(thread_reg)); 6133 pop(t1); 6134 } 6135 #endif 6136 } 6137 6138 class ControlWord { 6139 public: 6140 int32_t _value; 6141 6142 int rounding_control() const { return (_value >> 10) & 3 ; } 6143 int precision_control() const { return (_value >> 8) & 3 ; } 6144 bool precision() const { return ((_value >> 5) & 1) != 0; } 6145 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6146 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6147 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6148 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6149 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6150 6151 void print() const { 6152 // rounding control 6153 const char* rc; 6154 switch (rounding_control()) { 6155 case 0: rc = "round near"; break; 6156 case 1: rc = "round down"; break; 6157 case 2: rc = "round up "; break; 6158 case 3: rc = "chop "; break; 6159 }; 6160 // precision control 6161 const char* pc; 6162 switch (precision_control()) { 6163 case 0: pc = "24 bits "; break; 6164 case 1: pc = "reserved"; break; 6165 case 2: pc = "53 bits "; break; 6166 case 3: pc = "64 bits "; break; 6167 }; 6168 // flags 6169 char f[9]; 6170 f[0] = ' '; 6171 f[1] = ' '; 6172 f[2] = (precision ()) ? 'P' : 'p'; 6173 f[3] = (underflow ()) ? 'U' : 'u'; 6174 f[4] = (overflow ()) ? 'O' : 'o'; 6175 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6176 f[6] = (denormalized()) ? 'D' : 'd'; 6177 f[7] = (invalid ()) ? 'I' : 'i'; 6178 f[8] = '\x0'; 6179 // output 6180 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6181 } 6182 6183 }; 6184 6185 class StatusWord { 6186 public: 6187 int32_t _value; 6188 6189 bool busy() const { return ((_value >> 15) & 1) != 0; } 6190 bool C3() const { return ((_value >> 14) & 1) != 0; } 6191 bool C2() const { return ((_value >> 10) & 1) != 0; } 6192 bool C1() const { return ((_value >> 9) & 1) != 0; } 6193 bool C0() const { return ((_value >> 8) & 1) != 0; } 6194 int top() const { return (_value >> 11) & 7 ; } 6195 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6196 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6197 bool precision() const { return ((_value >> 5) & 1) != 0; } 6198 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6199 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6200 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6201 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6202 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6203 6204 void print() const { 6205 // condition codes 6206 char c[5]; 6207 c[0] = (C3()) ? '3' : '-'; 6208 c[1] = (C2()) ? '2' : '-'; 6209 c[2] = (C1()) ? '1' : '-'; 6210 c[3] = (C0()) ? '0' : '-'; 6211 c[4] = '\x0'; 6212 // flags 6213 char f[9]; 6214 f[0] = (error_status()) ? 'E' : '-'; 6215 f[1] = (stack_fault ()) ? 'S' : '-'; 6216 f[2] = (precision ()) ? 'P' : '-'; 6217 f[3] = (underflow ()) ? 'U' : '-'; 6218 f[4] = (overflow ()) ? 'O' : '-'; 6219 f[5] = (zero_divide ()) ? 'Z' : '-'; 6220 f[6] = (denormalized()) ? 'D' : '-'; 6221 f[7] = (invalid ()) ? 'I' : '-'; 6222 f[8] = '\x0'; 6223 // output 6224 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6225 } 6226 6227 }; 6228 6229 class TagWord { 6230 public: 6231 int32_t _value; 6232 6233 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6234 6235 void print() const { 6236 printf("%04x", _value & 0xFFFF); 6237 } 6238 6239 }; 6240 6241 class FPU_Register { 6242 public: 6243 int32_t _m0; 6244 int32_t _m1; 6245 int16_t _ex; 6246 6247 bool is_indefinite() const { 6248 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6249 } 6250 6251 void print() const { 6252 char sign = (_ex < 0) ? '-' : '+'; 6253 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6254 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6255 }; 6256 6257 }; 6258 6259 class FPU_State { 6260 public: 6261 enum { 6262 register_size = 10, 6263 number_of_registers = 8, 6264 register_mask = 7 6265 }; 6266 6267 ControlWord _control_word; 6268 StatusWord _status_word; 6269 TagWord _tag_word; 6270 int32_t _error_offset; 6271 int32_t _error_selector; 6272 int32_t _data_offset; 6273 int32_t _data_selector; 6274 int8_t _register[register_size * number_of_registers]; 6275 6276 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6277 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6278 6279 const char* tag_as_string(int tag) const { 6280 switch (tag) { 6281 case 0: return "valid"; 6282 case 1: return "zero"; 6283 case 2: return "special"; 6284 case 3: return "empty"; 6285 } 6286 ShouldNotReachHere(); 6287 return NULL; 6288 } 6289 6290 void print() const { 6291 // print computation registers 6292 { int t = _status_word.top(); 6293 for (int i = 0; i < number_of_registers; i++) { 6294 int j = (i - t) & register_mask; 6295 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6296 st(j)->print(); 6297 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6298 } 6299 } 6300 printf("\n"); 6301 // print control registers 6302 printf("ctrl = "); _control_word.print(); printf("\n"); 6303 printf("stat = "); _status_word .print(); printf("\n"); 6304 printf("tags = "); _tag_word .print(); printf("\n"); 6305 } 6306 6307 }; 6308 6309 class Flag_Register { 6310 public: 6311 int32_t _value; 6312 6313 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6314 bool direction() const { return ((_value >> 10) & 1) != 0; } 6315 bool sign() const { return ((_value >> 7) & 1) != 0; } 6316 bool zero() const { return ((_value >> 6) & 1) != 0; } 6317 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6318 bool parity() const { return ((_value >> 2) & 1) != 0; } 6319 bool carry() const { return ((_value >> 0) & 1) != 0; } 6320 6321 void print() const { 6322 // flags 6323 char f[8]; 6324 f[0] = (overflow ()) ? 'O' : '-'; 6325 f[1] = (direction ()) ? 'D' : '-'; 6326 f[2] = (sign ()) ? 'S' : '-'; 6327 f[3] = (zero ()) ? 'Z' : '-'; 6328 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6329 f[5] = (parity ()) ? 'P' : '-'; 6330 f[6] = (carry ()) ? 'C' : '-'; 6331 f[7] = '\x0'; 6332 // output 6333 printf("%08x flags = %s", _value, f); 6334 } 6335 6336 }; 6337 6338 class IU_Register { 6339 public: 6340 int32_t _value; 6341 6342 void print() const { 6343 printf("%08x %11d", _value, _value); 6344 } 6345 6346 }; 6347 6348 class IU_State { 6349 public: 6350 Flag_Register _eflags; 6351 IU_Register _rdi; 6352 IU_Register _rsi; 6353 IU_Register _rbp; 6354 IU_Register _rsp; 6355 IU_Register _rbx; 6356 IU_Register _rdx; 6357 IU_Register _rcx; 6358 IU_Register _rax; 6359 6360 void print() const { 6361 // computation registers 6362 printf("rax, = "); _rax.print(); printf("\n"); 6363 printf("rbx, = "); _rbx.print(); printf("\n"); 6364 printf("rcx = "); _rcx.print(); printf("\n"); 6365 printf("rdx = "); _rdx.print(); printf("\n"); 6366 printf("rdi = "); _rdi.print(); printf("\n"); 6367 printf("rsi = "); _rsi.print(); printf("\n"); 6368 printf("rbp, = "); _rbp.print(); printf("\n"); 6369 printf("rsp = "); _rsp.print(); printf("\n"); 6370 printf("\n"); 6371 // control registers 6372 printf("flgs = "); _eflags.print(); printf("\n"); 6373 } 6374 }; 6375 6376 6377 class CPU_State { 6378 public: 6379 FPU_State _fpu_state; 6380 IU_State _iu_state; 6381 6382 void print() const { 6383 printf("--------------------------------------------------\n"); 6384 _iu_state .print(); 6385 printf("\n"); 6386 _fpu_state.print(); 6387 printf("--------------------------------------------------\n"); 6388 } 6389 6390 }; 6391 6392 6393 static void _print_CPU_state(CPU_State* state) { 6394 state->print(); 6395 }; 6396 6397 6398 void MacroAssembler::print_CPU_state() { 6399 push_CPU_state(); 6400 push(rsp); // pass CPU state 6401 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6402 addptr(rsp, wordSize); // discard argument 6403 pop_CPU_state(); 6404 } 6405 6406 6407 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6408 static int counter = 0; 6409 FPU_State* fs = &state->_fpu_state; 6410 counter++; 6411 // For leaf calls, only verify that the top few elements remain empty. 6412 // We only need 1 empty at the top for C2 code. 6413 if( stack_depth < 0 ) { 6414 if( fs->tag_for_st(7) != 3 ) { 6415 printf("FPR7 not empty\n"); 6416 state->print(); 6417 assert(false, "error"); 6418 return false; 6419 } 6420 return true; // All other stack states do not matter 6421 } 6422 6423 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6424 "bad FPU control word"); 6425 6426 // compute stack depth 6427 int i = 0; 6428 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6429 int d = i; 6430 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6431 // verify findings 6432 if (i != FPU_State::number_of_registers) { 6433 // stack not contiguous 6434 printf("%s: stack not contiguous at ST%d\n", s, i); 6435 state->print(); 6436 assert(false, "error"); 6437 return false; 6438 } 6439 // check if computed stack depth corresponds to expected stack depth 6440 if (stack_depth < 0) { 6441 // expected stack depth is -stack_depth or less 6442 if (d > -stack_depth) { 6443 // too many elements on the stack 6444 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6445 state->print(); 6446 assert(false, "error"); 6447 return false; 6448 } 6449 } else { 6450 // expected stack depth is stack_depth 6451 if (d != stack_depth) { 6452 // wrong stack depth 6453 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6454 state->print(); 6455 assert(false, "error"); 6456 return false; 6457 } 6458 } 6459 // everything is cool 6460 return true; 6461 } 6462 6463 6464 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6465 if (!VerifyFPU) return; 6466 push_CPU_state(); 6467 push(rsp); // pass CPU state 6468 ExternalAddress msg((address) s); 6469 // pass message string s 6470 pushptr(msg.addr()); 6471 push(stack_depth); // pass stack depth 6472 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6473 addptr(rsp, 3 * wordSize); // discard arguments 6474 // check for error 6475 { Label L; 6476 testl(rax, rax); 6477 jcc(Assembler::notZero, L); 6478 int3(); // break if error condition 6479 bind(L); 6480 } 6481 pop_CPU_state(); 6482 } 6483 6484 void MacroAssembler::restore_cpu_control_state_after_jni() { 6485 // Either restore the MXCSR register after returning from the JNI Call 6486 // or verify that it wasn't changed (with -Xcheck:jni flag). 6487 if (VM_Version::supports_sse()) { 6488 if (RestoreMXCSROnJNICalls) { 6489 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6490 } else if (CheckJNICalls) { 6491 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6492 } 6493 } 6494 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6495 vzeroupper(); 6496 6497 #ifndef _LP64 6498 // Either restore the x87 floating pointer control word after returning 6499 // from the JNI call or verify that it wasn't changed. 6500 if (CheckJNICalls) { 6501 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6502 } 6503 #endif // _LP64 6504 } 6505 6506 void MacroAssembler::load_mirror(Register mirror, Register method) { 6507 // get mirror 6508 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6509 movptr(mirror, Address(method, Method::const_offset())); 6510 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6511 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6512 movptr(mirror, Address(mirror, mirror_offset)); 6513 } 6514 6515 void MacroAssembler::load_klass(Register dst, Register src) { 6516 #ifdef _LP64 6517 if (UseCompressedClassPointers) { 6518 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6519 decode_klass_not_null(dst); 6520 } else 6521 #endif 6522 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6523 } 6524 6525 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6526 load_klass(dst, src); 6527 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6528 } 6529 6530 void MacroAssembler::store_klass(Register dst, Register src) { 6531 #ifdef _LP64 6532 if (UseCompressedClassPointers) { 6533 encode_klass_not_null(src); 6534 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6535 } else 6536 #endif 6537 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6538 } 6539 6540 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6541 #ifdef _LP64 6542 // FIXME: Must change all places where we try to load the klass. 6543 if (UseCompressedOops) { 6544 movl(dst, src); 6545 decode_heap_oop(dst); 6546 } else 6547 #endif 6548 movptr(dst, src); 6549 } 6550 6551 // Doesn't do verfication, generates fixed size code 6552 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6553 #ifdef _LP64 6554 if (UseCompressedOops) { 6555 movl(dst, src); 6556 decode_heap_oop_not_null(dst); 6557 } else 6558 #endif 6559 movptr(dst, src); 6560 } 6561 6562 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6563 #ifdef _LP64 6564 if (UseCompressedOops) { 6565 assert(!dst.uses(src), "not enough registers"); 6566 encode_heap_oop(src); 6567 movl(dst, src); 6568 } else 6569 #endif 6570 movptr(dst, src); 6571 } 6572 6573 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6574 assert_different_registers(src1, tmp); 6575 #ifdef _LP64 6576 if (UseCompressedOops) { 6577 bool did_push = false; 6578 if (tmp == noreg) { 6579 tmp = rax; 6580 push(tmp); 6581 did_push = true; 6582 assert(!src2.uses(rsp), "can't push"); 6583 } 6584 load_heap_oop(tmp, src2); 6585 cmpptr(src1, tmp); 6586 if (did_push) pop(tmp); 6587 } else 6588 #endif 6589 cmpptr(src1, src2); 6590 } 6591 6592 // Used for storing NULLs. 6593 void MacroAssembler::store_heap_oop_null(Address dst) { 6594 #ifdef _LP64 6595 if (UseCompressedOops) { 6596 movl(dst, (int32_t)NULL_WORD); 6597 } else { 6598 movslq(dst, (int32_t)NULL_WORD); 6599 } 6600 #else 6601 movl(dst, (int32_t)NULL_WORD); 6602 #endif 6603 } 6604 6605 #ifdef _LP64 6606 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6607 if (UseCompressedClassPointers) { 6608 // Store to klass gap in destination 6609 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6610 } 6611 } 6612 6613 #ifdef ASSERT 6614 void MacroAssembler::verify_heapbase(const char* msg) { 6615 assert (UseCompressedOops, "should be compressed"); 6616 assert (Universe::heap() != NULL, "java heap should be initialized"); 6617 if (CheckCompressedOops) { 6618 Label ok; 6619 push(rscratch1); // cmpptr trashes rscratch1 6620 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6621 jcc(Assembler::equal, ok); 6622 STOP(msg); 6623 bind(ok); 6624 pop(rscratch1); 6625 } 6626 } 6627 #endif 6628 6629 // Algorithm must match oop.inline.hpp encode_heap_oop. 6630 void MacroAssembler::encode_heap_oop(Register r) { 6631 #ifdef ASSERT 6632 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6633 #endif 6634 verify_oop(r, "broken oop in encode_heap_oop"); 6635 if (Universe::narrow_oop_base() == NULL) { 6636 if (Universe::narrow_oop_shift() != 0) { 6637 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6638 shrq(r, LogMinObjAlignmentInBytes); 6639 } 6640 return; 6641 } 6642 testq(r, r); 6643 cmovq(Assembler::equal, r, r12_heapbase); 6644 subq(r, r12_heapbase); 6645 shrq(r, LogMinObjAlignmentInBytes); 6646 } 6647 6648 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6649 #ifdef ASSERT 6650 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6651 if (CheckCompressedOops) { 6652 Label ok; 6653 testq(r, r); 6654 jcc(Assembler::notEqual, ok); 6655 STOP("null oop passed to encode_heap_oop_not_null"); 6656 bind(ok); 6657 } 6658 #endif 6659 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6660 if (Universe::narrow_oop_base() != NULL) { 6661 subq(r, r12_heapbase); 6662 } 6663 if (Universe::narrow_oop_shift() != 0) { 6664 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6665 shrq(r, LogMinObjAlignmentInBytes); 6666 } 6667 } 6668 6669 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6670 #ifdef ASSERT 6671 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6672 if (CheckCompressedOops) { 6673 Label ok; 6674 testq(src, src); 6675 jcc(Assembler::notEqual, ok); 6676 STOP("null oop passed to encode_heap_oop_not_null2"); 6677 bind(ok); 6678 } 6679 #endif 6680 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6681 if (dst != src) { 6682 movq(dst, src); 6683 } 6684 if (Universe::narrow_oop_base() != NULL) { 6685 subq(dst, r12_heapbase); 6686 } 6687 if (Universe::narrow_oop_shift() != 0) { 6688 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6689 shrq(dst, LogMinObjAlignmentInBytes); 6690 } 6691 } 6692 6693 void MacroAssembler::decode_heap_oop(Register r) { 6694 #ifdef ASSERT 6695 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6696 #endif 6697 if (Universe::narrow_oop_base() == NULL) { 6698 if (Universe::narrow_oop_shift() != 0) { 6699 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6700 shlq(r, LogMinObjAlignmentInBytes); 6701 } 6702 } else { 6703 Label done; 6704 shlq(r, LogMinObjAlignmentInBytes); 6705 jccb(Assembler::equal, done); 6706 addq(r, r12_heapbase); 6707 bind(done); 6708 } 6709 verify_oop(r, "broken oop in decode_heap_oop"); 6710 } 6711 6712 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6713 // Note: it will change flags 6714 assert (UseCompressedOops, "should only be used for compressed headers"); 6715 assert (Universe::heap() != NULL, "java heap should be initialized"); 6716 // Cannot assert, unverified entry point counts instructions (see .ad file) 6717 // vtableStubs also counts instructions in pd_code_size_limit. 6718 // Also do not verify_oop as this is called by verify_oop. 6719 if (Universe::narrow_oop_shift() != 0) { 6720 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6721 shlq(r, LogMinObjAlignmentInBytes); 6722 if (Universe::narrow_oop_base() != NULL) { 6723 addq(r, r12_heapbase); 6724 } 6725 } else { 6726 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6727 } 6728 } 6729 6730 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6731 // Note: it will change flags 6732 assert (UseCompressedOops, "should only be used for compressed headers"); 6733 assert (Universe::heap() != NULL, "java heap should be initialized"); 6734 // Cannot assert, unverified entry point counts instructions (see .ad file) 6735 // vtableStubs also counts instructions in pd_code_size_limit. 6736 // Also do not verify_oop as this is called by verify_oop. 6737 if (Universe::narrow_oop_shift() != 0) { 6738 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6739 if (LogMinObjAlignmentInBytes == Address::times_8) { 6740 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6741 } else { 6742 if (dst != src) { 6743 movq(dst, src); 6744 } 6745 shlq(dst, LogMinObjAlignmentInBytes); 6746 if (Universe::narrow_oop_base() != NULL) { 6747 addq(dst, r12_heapbase); 6748 } 6749 } 6750 } else { 6751 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6752 if (dst != src) { 6753 movq(dst, src); 6754 } 6755 } 6756 } 6757 6758 void MacroAssembler::encode_klass_not_null(Register r) { 6759 if (Universe::narrow_klass_base() != NULL) { 6760 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6761 assert(r != r12_heapbase, "Encoding a klass in r12"); 6762 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6763 subq(r, r12_heapbase); 6764 } 6765 if (Universe::narrow_klass_shift() != 0) { 6766 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6767 shrq(r, LogKlassAlignmentInBytes); 6768 } 6769 if (Universe::narrow_klass_base() != NULL) { 6770 reinit_heapbase(); 6771 } 6772 } 6773 6774 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6775 if (dst == src) { 6776 encode_klass_not_null(src); 6777 } else { 6778 if (Universe::narrow_klass_base() != NULL) { 6779 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6780 negq(dst); 6781 addq(dst, src); 6782 } else { 6783 movptr(dst, src); 6784 } 6785 if (Universe::narrow_klass_shift() != 0) { 6786 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6787 shrq(dst, LogKlassAlignmentInBytes); 6788 } 6789 } 6790 } 6791 6792 // Function instr_size_for_decode_klass_not_null() counts the instructions 6793 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6794 // when (Universe::heap() != NULL). Hence, if the instructions they 6795 // generate change, then this method needs to be updated. 6796 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6797 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6798 if (Universe::narrow_klass_base() != NULL) { 6799 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6800 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6801 } else { 6802 // longest load decode klass function, mov64, leaq 6803 return 16; 6804 } 6805 } 6806 6807 // !!! If the instructions that get generated here change then function 6808 // instr_size_for_decode_klass_not_null() needs to get updated. 6809 void MacroAssembler::decode_klass_not_null(Register r) { 6810 // Note: it will change flags 6811 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6812 assert(r != r12_heapbase, "Decoding a klass in r12"); 6813 // Cannot assert, unverified entry point counts instructions (see .ad file) 6814 // vtableStubs also counts instructions in pd_code_size_limit. 6815 // Also do not verify_oop as this is called by verify_oop. 6816 if (Universe::narrow_klass_shift() != 0) { 6817 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6818 shlq(r, LogKlassAlignmentInBytes); 6819 } 6820 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6821 if (Universe::narrow_klass_base() != NULL) { 6822 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6823 addq(r, r12_heapbase); 6824 reinit_heapbase(); 6825 } 6826 } 6827 6828 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6829 // Note: it will change flags 6830 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6831 if (dst == src) { 6832 decode_klass_not_null(dst); 6833 } else { 6834 // Cannot assert, unverified entry point counts instructions (see .ad file) 6835 // vtableStubs also counts instructions in pd_code_size_limit. 6836 // Also do not verify_oop as this is called by verify_oop. 6837 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6838 if (Universe::narrow_klass_shift() != 0) { 6839 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6840 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6841 leaq(dst, Address(dst, src, Address::times_8, 0)); 6842 } else { 6843 addq(dst, src); 6844 } 6845 } 6846 } 6847 6848 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6849 assert (UseCompressedOops, "should only be used for compressed headers"); 6850 assert (Universe::heap() != NULL, "java heap should be initialized"); 6851 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6852 int oop_index = oop_recorder()->find_index(obj); 6853 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6854 mov_narrow_oop(dst, oop_index, rspec); 6855 } 6856 6857 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6858 assert (UseCompressedOops, "should only be used for compressed headers"); 6859 assert (Universe::heap() != NULL, "java heap should be initialized"); 6860 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6861 int oop_index = oop_recorder()->find_index(obj); 6862 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6863 mov_narrow_oop(dst, oop_index, rspec); 6864 } 6865 6866 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6867 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6868 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6869 int klass_index = oop_recorder()->find_index(k); 6870 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6871 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6872 } 6873 6874 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6875 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6876 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6877 int klass_index = oop_recorder()->find_index(k); 6878 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6879 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6880 } 6881 6882 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6883 assert (UseCompressedOops, "should only be used for compressed headers"); 6884 assert (Universe::heap() != NULL, "java heap should be initialized"); 6885 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6886 int oop_index = oop_recorder()->find_index(obj); 6887 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6888 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6889 } 6890 6891 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6892 assert (UseCompressedOops, "should only be used for compressed headers"); 6893 assert (Universe::heap() != NULL, "java heap should be initialized"); 6894 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6895 int oop_index = oop_recorder()->find_index(obj); 6896 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6897 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6898 } 6899 6900 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6901 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6902 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6903 int klass_index = oop_recorder()->find_index(k); 6904 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6905 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6906 } 6907 6908 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6909 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6910 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6911 int klass_index = oop_recorder()->find_index(k); 6912 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6913 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6914 } 6915 6916 void MacroAssembler::reinit_heapbase() { 6917 if (UseCompressedOops || UseCompressedClassPointers) { 6918 if (Universe::heap() != NULL) { 6919 if (Universe::narrow_oop_base() == NULL) { 6920 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6921 } else { 6922 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6923 } 6924 } else { 6925 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6926 } 6927 } 6928 } 6929 6930 #endif // _LP64 6931 6932 6933 // C2 compiled method's prolog code. 6934 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6935 6936 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6937 // NativeJump::patch_verified_entry will be able to patch out the entry 6938 // code safely. The push to verify stack depth is ok at 5 bytes, 6939 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6940 // stack bang then we must use the 6 byte frame allocation even if 6941 // we have no frame. :-( 6942 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6943 6944 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6945 // Remove word for return addr 6946 framesize -= wordSize; 6947 stack_bang_size -= wordSize; 6948 6949 // Calls to C2R adapters often do not accept exceptional returns. 6950 // We require that their callers must bang for them. But be careful, because 6951 // some VM calls (such as call site linkage) can use several kilobytes of 6952 // stack. But the stack safety zone should account for that. 6953 // See bugs 4446381, 4468289, 4497237. 6954 if (stack_bang_size > 0) { 6955 generate_stack_overflow_check(stack_bang_size); 6956 6957 // We always push rbp, so that on return to interpreter rbp, will be 6958 // restored correctly and we can correct the stack. 6959 push(rbp); 6960 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6961 if (PreserveFramePointer) { 6962 mov(rbp, rsp); 6963 } 6964 // Remove word for ebp 6965 framesize -= wordSize; 6966 6967 // Create frame 6968 if (framesize) { 6969 subptr(rsp, framesize); 6970 } 6971 } else { 6972 // Create frame (force generation of a 4 byte immediate value) 6973 subptr_imm32(rsp, framesize); 6974 6975 // Save RBP register now. 6976 framesize -= wordSize; 6977 movptr(Address(rsp, framesize), rbp); 6978 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6979 if (PreserveFramePointer) { 6980 movptr(rbp, rsp); 6981 if (framesize > 0) { 6982 addptr(rbp, framesize); 6983 } 6984 } 6985 } 6986 6987 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6988 framesize -= wordSize; 6989 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6990 } 6991 6992 #ifndef _LP64 6993 // If method sets FPU control word do it now 6994 if (fp_mode_24b) { 6995 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6996 } 6997 if (UseSSE >= 2 && VerifyFPU) { 6998 verify_FPU(0, "FPU stack must be clean on entry"); 6999 } 7000 #endif 7001 7002 #ifdef ASSERT 7003 if (VerifyStackAtCalls) { 7004 Label L; 7005 push(rax); 7006 mov(rax, rsp); 7007 andptr(rax, StackAlignmentInBytes-1); 7008 cmpptr(rax, StackAlignmentInBytes-wordSize); 7009 pop(rax); 7010 jcc(Assembler::equal, L); 7011 STOP("Stack is not properly aligned!"); 7012 bind(L); 7013 } 7014 #endif 7015 7016 } 7017 7018 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7019 // cnt - number of qwords (8-byte words). 7020 // base - start address, qword aligned. 7021 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7022 assert(base==rdi, "base register must be edi for rep stos"); 7023 assert(tmp==rax, "tmp register must be eax for rep stos"); 7024 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7025 assert(InitArrayShortSize % BytesPerLong == 0, 7026 "InitArrayShortSize should be the multiple of BytesPerLong"); 7027 7028 Label DONE; 7029 7030 xorptr(tmp, tmp); 7031 7032 if (!is_large) { 7033 Label LOOP, LONG; 7034 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7035 jccb(Assembler::greater, LONG); 7036 7037 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7038 7039 decrement(cnt); 7040 jccb(Assembler::negative, DONE); // Zero length 7041 7042 // Use individual pointer-sized stores for small counts: 7043 BIND(LOOP); 7044 movptr(Address(base, cnt, Address::times_ptr), tmp); 7045 decrement(cnt); 7046 jccb(Assembler::greaterEqual, LOOP); 7047 jmpb(DONE); 7048 7049 BIND(LONG); 7050 } 7051 7052 // Use longer rep-prefixed ops for non-small counts: 7053 if (UseFastStosb) { 7054 shlptr(cnt, 3); // convert to number of bytes 7055 rep_stosb(); 7056 } else { 7057 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7058 rep_stos(); 7059 } 7060 7061 BIND(DONE); 7062 } 7063 7064 #ifdef COMPILER2 7065 7066 // IndexOf for constant substrings with size >= 8 chars 7067 // which don't need to be loaded through stack. 7068 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7069 Register cnt1, Register cnt2, 7070 int int_cnt2, Register result, 7071 XMMRegister vec, Register tmp, 7072 int ae) { 7073 ShortBranchVerifier sbv(this); 7074 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7075 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7076 7077 // This method uses the pcmpestri instruction with bound registers 7078 // inputs: 7079 // xmm - substring 7080 // rax - substring length (elements count) 7081 // mem - scanned string 7082 // rdx - string length (elements count) 7083 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7084 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7085 // outputs: 7086 // rcx - matched index in string 7087 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7088 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7089 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7090 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7091 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7092 7093 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7094 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7095 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7096 7097 // Note, inline_string_indexOf() generates checks: 7098 // if (substr.count > string.count) return -1; 7099 // if (substr.count == 0) return 0; 7100 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7101 7102 // Load substring. 7103 if (ae == StrIntrinsicNode::UL) { 7104 pmovzxbw(vec, Address(str2, 0)); 7105 } else { 7106 movdqu(vec, Address(str2, 0)); 7107 } 7108 movl(cnt2, int_cnt2); 7109 movptr(result, str1); // string addr 7110 7111 if (int_cnt2 > stride) { 7112 jmpb(SCAN_TO_SUBSTR); 7113 7114 // Reload substr for rescan, this code 7115 // is executed only for large substrings (> 8 chars) 7116 bind(RELOAD_SUBSTR); 7117 if (ae == StrIntrinsicNode::UL) { 7118 pmovzxbw(vec, Address(str2, 0)); 7119 } else { 7120 movdqu(vec, Address(str2, 0)); 7121 } 7122 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7123 7124 bind(RELOAD_STR); 7125 // We came here after the beginning of the substring was 7126 // matched but the rest of it was not so we need to search 7127 // again. Start from the next element after the previous match. 7128 7129 // cnt2 is number of substring reminding elements and 7130 // cnt1 is number of string reminding elements when cmp failed. 7131 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7132 subl(cnt1, cnt2); 7133 addl(cnt1, int_cnt2); 7134 movl(cnt2, int_cnt2); // Now restore cnt2 7135 7136 decrementl(cnt1); // Shift to next element 7137 cmpl(cnt1, cnt2); 7138 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7139 7140 addptr(result, (1<<scale1)); 7141 7142 } // (int_cnt2 > 8) 7143 7144 // Scan string for start of substr in 16-byte vectors 7145 bind(SCAN_TO_SUBSTR); 7146 pcmpestri(vec, Address(result, 0), mode); 7147 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7148 subl(cnt1, stride); 7149 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7150 cmpl(cnt1, cnt2); 7151 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7152 addptr(result, 16); 7153 jmpb(SCAN_TO_SUBSTR); 7154 7155 // Found a potential substr 7156 bind(FOUND_CANDIDATE); 7157 // Matched whole vector if first element matched (tmp(rcx) == 0). 7158 if (int_cnt2 == stride) { 7159 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7160 } else { // int_cnt2 > 8 7161 jccb(Assembler::overflow, FOUND_SUBSTR); 7162 } 7163 // After pcmpestri tmp(rcx) contains matched element index 7164 // Compute start addr of substr 7165 lea(result, Address(result, tmp, scale1)); 7166 7167 // Make sure string is still long enough 7168 subl(cnt1, tmp); 7169 cmpl(cnt1, cnt2); 7170 if (int_cnt2 == stride) { 7171 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7172 } else { // int_cnt2 > 8 7173 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7174 } 7175 // Left less then substring. 7176 7177 bind(RET_NOT_FOUND); 7178 movl(result, -1); 7179 jmp(EXIT); 7180 7181 if (int_cnt2 > stride) { 7182 // This code is optimized for the case when whole substring 7183 // is matched if its head is matched. 7184 bind(MATCH_SUBSTR_HEAD); 7185 pcmpestri(vec, Address(result, 0), mode); 7186 // Reload only string if does not match 7187 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 7188 7189 Label CONT_SCAN_SUBSTR; 7190 // Compare the rest of substring (> 8 chars). 7191 bind(FOUND_SUBSTR); 7192 // First 8 chars are already matched. 7193 negptr(cnt2); 7194 addptr(cnt2, stride); 7195 7196 bind(SCAN_SUBSTR); 7197 subl(cnt1, stride); 7198 cmpl(cnt2, -stride); // Do not read beyond substring 7199 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7200 // Back-up strings to avoid reading beyond substring: 7201 // cnt1 = cnt1 - cnt2 + 8 7202 addl(cnt1, cnt2); // cnt2 is negative 7203 addl(cnt1, stride); 7204 movl(cnt2, stride); negptr(cnt2); 7205 bind(CONT_SCAN_SUBSTR); 7206 if (int_cnt2 < (int)G) { 7207 int tail_off1 = int_cnt2<<scale1; 7208 int tail_off2 = int_cnt2<<scale2; 7209 if (ae == StrIntrinsicNode::UL) { 7210 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7211 } else { 7212 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7213 } 7214 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7215 } else { 7216 // calculate index in register to avoid integer overflow (int_cnt2*2) 7217 movl(tmp, int_cnt2); 7218 addptr(tmp, cnt2); 7219 if (ae == StrIntrinsicNode::UL) { 7220 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7221 } else { 7222 movdqu(vec, Address(str2, tmp, scale2, 0)); 7223 } 7224 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7225 } 7226 // Need to reload strings pointers if not matched whole vector 7227 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7228 addptr(cnt2, stride); 7229 jcc(Assembler::negative, SCAN_SUBSTR); 7230 // Fall through if found full substring 7231 7232 } // (int_cnt2 > 8) 7233 7234 bind(RET_FOUND); 7235 // Found result if we matched full small substring. 7236 // Compute substr offset 7237 subptr(result, str1); 7238 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7239 shrl(result, 1); // index 7240 } 7241 bind(EXIT); 7242 7243 } // string_indexofC8 7244 7245 // Small strings are loaded through stack if they cross page boundary. 7246 void MacroAssembler::string_indexof(Register str1, Register str2, 7247 Register cnt1, Register cnt2, 7248 int int_cnt2, Register result, 7249 XMMRegister vec, Register tmp, 7250 int ae) { 7251 ShortBranchVerifier sbv(this); 7252 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7253 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7254 7255 // 7256 // int_cnt2 is length of small (< 8 chars) constant substring 7257 // or (-1) for non constant substring in which case its length 7258 // is in cnt2 register. 7259 // 7260 // Note, inline_string_indexOf() generates checks: 7261 // if (substr.count > string.count) return -1; 7262 // if (substr.count == 0) return 0; 7263 // 7264 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7265 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7266 // This method uses the pcmpestri instruction with bound registers 7267 // inputs: 7268 // xmm - substring 7269 // rax - substring length (elements count) 7270 // mem - scanned string 7271 // rdx - string length (elements count) 7272 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7273 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7274 // outputs: 7275 // rcx - matched index in string 7276 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7277 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7278 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7279 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7280 7281 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7282 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7283 FOUND_CANDIDATE; 7284 7285 { //======================================================== 7286 // We don't know where these strings are located 7287 // and we can't read beyond them. Load them through stack. 7288 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7289 7290 movptr(tmp, rsp); // save old SP 7291 7292 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7293 if (int_cnt2 == (1>>scale2)) { // One byte 7294 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7295 load_unsigned_byte(result, Address(str2, 0)); 7296 movdl(vec, result); // move 32 bits 7297 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7298 // Not enough header space in 32-bit VM: 12+3 = 15. 7299 movl(result, Address(str2, -1)); 7300 shrl(result, 8); 7301 movdl(vec, result); // move 32 bits 7302 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7303 load_unsigned_short(result, Address(str2, 0)); 7304 movdl(vec, result); // move 32 bits 7305 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7306 movdl(vec, Address(str2, 0)); // move 32 bits 7307 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7308 movq(vec, Address(str2, 0)); // move 64 bits 7309 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7310 // Array header size is 12 bytes in 32-bit VM 7311 // + 6 bytes for 3 chars == 18 bytes, 7312 // enough space to load vec and shift. 7313 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7314 if (ae == StrIntrinsicNode::UL) { 7315 int tail_off = int_cnt2-8; 7316 pmovzxbw(vec, Address(str2, tail_off)); 7317 psrldq(vec, -2*tail_off); 7318 } 7319 else { 7320 int tail_off = int_cnt2*(1<<scale2); 7321 movdqu(vec, Address(str2, tail_off-16)); 7322 psrldq(vec, 16-tail_off); 7323 } 7324 } 7325 } else { // not constant substring 7326 cmpl(cnt2, stride); 7327 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7328 7329 // We can read beyond string if srt+16 does not cross page boundary 7330 // since heaps are aligned and mapped by pages. 7331 assert(os::vm_page_size() < (int)G, "default page should be small"); 7332 movl(result, str2); // We need only low 32 bits 7333 andl(result, (os::vm_page_size()-1)); 7334 cmpl(result, (os::vm_page_size()-16)); 7335 jccb(Assembler::belowEqual, CHECK_STR); 7336 7337 // Move small strings to stack to allow load 16 bytes into vec. 7338 subptr(rsp, 16); 7339 int stk_offset = wordSize-(1<<scale2); 7340 push(cnt2); 7341 7342 bind(COPY_SUBSTR); 7343 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7344 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7345 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7346 } else if (ae == StrIntrinsicNode::UU) { 7347 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7348 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7349 } 7350 decrement(cnt2); 7351 jccb(Assembler::notZero, COPY_SUBSTR); 7352 7353 pop(cnt2); 7354 movptr(str2, rsp); // New substring address 7355 } // non constant 7356 7357 bind(CHECK_STR); 7358 cmpl(cnt1, stride); 7359 jccb(Assembler::aboveEqual, BIG_STRINGS); 7360 7361 // Check cross page boundary. 7362 movl(result, str1); // We need only low 32 bits 7363 andl(result, (os::vm_page_size()-1)); 7364 cmpl(result, (os::vm_page_size()-16)); 7365 jccb(Assembler::belowEqual, BIG_STRINGS); 7366 7367 subptr(rsp, 16); 7368 int stk_offset = -(1<<scale1); 7369 if (int_cnt2 < 0) { // not constant 7370 push(cnt2); 7371 stk_offset += wordSize; 7372 } 7373 movl(cnt2, cnt1); 7374 7375 bind(COPY_STR); 7376 if (ae == StrIntrinsicNode::LL) { 7377 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7378 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7379 } else { 7380 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7381 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7382 } 7383 decrement(cnt2); 7384 jccb(Assembler::notZero, COPY_STR); 7385 7386 if (int_cnt2 < 0) { // not constant 7387 pop(cnt2); 7388 } 7389 movptr(str1, rsp); // New string address 7390 7391 bind(BIG_STRINGS); 7392 // Load substring. 7393 if (int_cnt2 < 0) { // -1 7394 if (ae == StrIntrinsicNode::UL) { 7395 pmovzxbw(vec, Address(str2, 0)); 7396 } else { 7397 movdqu(vec, Address(str2, 0)); 7398 } 7399 push(cnt2); // substr count 7400 push(str2); // substr addr 7401 push(str1); // string addr 7402 } else { 7403 // Small (< 8 chars) constant substrings are loaded already. 7404 movl(cnt2, int_cnt2); 7405 } 7406 push(tmp); // original SP 7407 7408 } // Finished loading 7409 7410 //======================================================== 7411 // Start search 7412 // 7413 7414 movptr(result, str1); // string addr 7415 7416 if (int_cnt2 < 0) { // Only for non constant substring 7417 jmpb(SCAN_TO_SUBSTR); 7418 7419 // SP saved at sp+0 7420 // String saved at sp+1*wordSize 7421 // Substr saved at sp+2*wordSize 7422 // Substr count saved at sp+3*wordSize 7423 7424 // Reload substr for rescan, this code 7425 // is executed only for large substrings (> 8 chars) 7426 bind(RELOAD_SUBSTR); 7427 movptr(str2, Address(rsp, 2*wordSize)); 7428 movl(cnt2, Address(rsp, 3*wordSize)); 7429 if (ae == StrIntrinsicNode::UL) { 7430 pmovzxbw(vec, Address(str2, 0)); 7431 } else { 7432 movdqu(vec, Address(str2, 0)); 7433 } 7434 // We came here after the beginning of the substring was 7435 // matched but the rest of it was not so we need to search 7436 // again. Start from the next element after the previous match. 7437 subptr(str1, result); // Restore counter 7438 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7439 shrl(str1, 1); 7440 } 7441 addl(cnt1, str1); 7442 decrementl(cnt1); // Shift to next element 7443 cmpl(cnt1, cnt2); 7444 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7445 7446 addptr(result, (1<<scale1)); 7447 } // non constant 7448 7449 // Scan string for start of substr in 16-byte vectors 7450 bind(SCAN_TO_SUBSTR); 7451 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7452 pcmpestri(vec, Address(result, 0), mode); 7453 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7454 subl(cnt1, stride); 7455 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7456 cmpl(cnt1, cnt2); 7457 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7458 addptr(result, 16); 7459 7460 bind(ADJUST_STR); 7461 cmpl(cnt1, stride); // Do not read beyond string 7462 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7463 // Back-up string to avoid reading beyond string. 7464 lea(result, Address(result, cnt1, scale1, -16)); 7465 movl(cnt1, stride); 7466 jmpb(SCAN_TO_SUBSTR); 7467 7468 // Found a potential substr 7469 bind(FOUND_CANDIDATE); 7470 // After pcmpestri tmp(rcx) contains matched element index 7471 7472 // Make sure string is still long enough 7473 subl(cnt1, tmp); 7474 cmpl(cnt1, cnt2); 7475 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7476 // Left less then substring. 7477 7478 bind(RET_NOT_FOUND); 7479 movl(result, -1); 7480 jmpb(CLEANUP); 7481 7482 bind(FOUND_SUBSTR); 7483 // Compute start addr of substr 7484 lea(result, Address(result, tmp, scale1)); 7485 if (int_cnt2 > 0) { // Constant substring 7486 // Repeat search for small substring (< 8 chars) 7487 // from new point without reloading substring. 7488 // Have to check that we don't read beyond string. 7489 cmpl(tmp, stride-int_cnt2); 7490 jccb(Assembler::greater, ADJUST_STR); 7491 // Fall through if matched whole substring. 7492 } else { // non constant 7493 assert(int_cnt2 == -1, "should be != 0"); 7494 7495 addl(tmp, cnt2); 7496 // Found result if we matched whole substring. 7497 cmpl(tmp, stride); 7498 jccb(Assembler::lessEqual, RET_FOUND); 7499 7500 // Repeat search for small substring (<= 8 chars) 7501 // from new point 'str1' without reloading substring. 7502 cmpl(cnt2, stride); 7503 // Have to check that we don't read beyond string. 7504 jccb(Assembler::lessEqual, ADJUST_STR); 7505 7506 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7507 // Compare the rest of substring (> 8 chars). 7508 movptr(str1, result); 7509 7510 cmpl(tmp, cnt2); 7511 // First 8 chars are already matched. 7512 jccb(Assembler::equal, CHECK_NEXT); 7513 7514 bind(SCAN_SUBSTR); 7515 pcmpestri(vec, Address(str1, 0), mode); 7516 // Need to reload strings pointers if not matched whole vector 7517 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7518 7519 bind(CHECK_NEXT); 7520 subl(cnt2, stride); 7521 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7522 addptr(str1, 16); 7523 if (ae == StrIntrinsicNode::UL) { 7524 addptr(str2, 8); 7525 } else { 7526 addptr(str2, 16); 7527 } 7528 subl(cnt1, stride); 7529 cmpl(cnt2, stride); // Do not read beyond substring 7530 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7531 // Back-up strings to avoid reading beyond substring. 7532 7533 if (ae == StrIntrinsicNode::UL) { 7534 lea(str2, Address(str2, cnt2, scale2, -8)); 7535 lea(str1, Address(str1, cnt2, scale1, -16)); 7536 } else { 7537 lea(str2, Address(str2, cnt2, scale2, -16)); 7538 lea(str1, Address(str1, cnt2, scale1, -16)); 7539 } 7540 subl(cnt1, cnt2); 7541 movl(cnt2, stride); 7542 addl(cnt1, stride); 7543 bind(CONT_SCAN_SUBSTR); 7544 if (ae == StrIntrinsicNode::UL) { 7545 pmovzxbw(vec, Address(str2, 0)); 7546 } else { 7547 movdqu(vec, Address(str2, 0)); 7548 } 7549 jmp(SCAN_SUBSTR); 7550 7551 bind(RET_FOUND_LONG); 7552 movptr(str1, Address(rsp, wordSize)); 7553 } // non constant 7554 7555 bind(RET_FOUND); 7556 // Compute substr offset 7557 subptr(result, str1); 7558 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7559 shrl(result, 1); // index 7560 } 7561 bind(CLEANUP); 7562 pop(rsp); // restore SP 7563 7564 } // string_indexof 7565 7566 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7567 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7568 ShortBranchVerifier sbv(this); 7569 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7570 7571 int stride = 8; 7572 7573 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7574 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7575 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7576 FOUND_SEQ_CHAR, DONE_LABEL; 7577 7578 movptr(result, str1); 7579 if (UseAVX >= 2) { 7580 cmpl(cnt1, stride); 7581 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7582 cmpl(cnt1, 2*stride); 7583 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7584 movdl(vec1, ch); 7585 vpbroadcastw(vec1, vec1); 7586 vpxor(vec2, vec2); 7587 movl(tmp, cnt1); 7588 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7589 andl(cnt1,0x0000000F); //tail count (in chars) 7590 7591 bind(SCAN_TO_16_CHAR_LOOP); 7592 vmovdqu(vec3, Address(result, 0)); 7593 vpcmpeqw(vec3, vec3, vec1, 1); 7594 vptest(vec2, vec3); 7595 jcc(Assembler::carryClear, FOUND_CHAR); 7596 addptr(result, 32); 7597 subl(tmp, 2*stride); 7598 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7599 jmp(SCAN_TO_8_CHAR); 7600 bind(SCAN_TO_8_CHAR_INIT); 7601 movdl(vec1, ch); 7602 pshuflw(vec1, vec1, 0x00); 7603 pshufd(vec1, vec1, 0); 7604 pxor(vec2, vec2); 7605 } 7606 bind(SCAN_TO_8_CHAR); 7607 cmpl(cnt1, stride); 7608 if (UseAVX >= 2) { 7609 jcc(Assembler::less, SCAN_TO_CHAR); 7610 } else { 7611 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7612 movdl(vec1, ch); 7613 pshuflw(vec1, vec1, 0x00); 7614 pshufd(vec1, vec1, 0); 7615 pxor(vec2, vec2); 7616 } 7617 movl(tmp, cnt1); 7618 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7619 andl(cnt1,0x00000007); //tail count (in chars) 7620 7621 bind(SCAN_TO_8_CHAR_LOOP); 7622 movdqu(vec3, Address(result, 0)); 7623 pcmpeqw(vec3, vec1); 7624 ptest(vec2, vec3); 7625 jcc(Assembler::carryClear, FOUND_CHAR); 7626 addptr(result, 16); 7627 subl(tmp, stride); 7628 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7629 bind(SCAN_TO_CHAR); 7630 testl(cnt1, cnt1); 7631 jcc(Assembler::zero, RET_NOT_FOUND); 7632 bind(SCAN_TO_CHAR_LOOP); 7633 load_unsigned_short(tmp, Address(result, 0)); 7634 cmpl(ch, tmp); 7635 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7636 addptr(result, 2); 7637 subl(cnt1, 1); 7638 jccb(Assembler::zero, RET_NOT_FOUND); 7639 jmp(SCAN_TO_CHAR_LOOP); 7640 7641 bind(RET_NOT_FOUND); 7642 movl(result, -1); 7643 jmpb(DONE_LABEL); 7644 7645 bind(FOUND_CHAR); 7646 if (UseAVX >= 2) { 7647 vpmovmskb(tmp, vec3); 7648 } else { 7649 pmovmskb(tmp, vec3); 7650 } 7651 bsfl(ch, tmp); 7652 addl(result, ch); 7653 7654 bind(FOUND_SEQ_CHAR); 7655 subptr(result, str1); 7656 shrl(result, 1); 7657 7658 bind(DONE_LABEL); 7659 } // string_indexof_char 7660 7661 // helper function for string_compare 7662 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7663 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7664 Address::ScaleFactor scale2, Register index, int ae) { 7665 if (ae == StrIntrinsicNode::LL) { 7666 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7667 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7668 } else if (ae == StrIntrinsicNode::UU) { 7669 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7670 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7671 } else { 7672 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7673 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7674 } 7675 } 7676 7677 // Compare strings, used for char[] and byte[]. 7678 void MacroAssembler::string_compare(Register str1, Register str2, 7679 Register cnt1, Register cnt2, Register result, 7680 XMMRegister vec1, int ae) { 7681 ShortBranchVerifier sbv(this); 7682 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7683 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7684 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7685 int stride2x2 = 0x40; 7686 Address::ScaleFactor scale = Address::no_scale; 7687 Address::ScaleFactor scale1 = Address::no_scale; 7688 Address::ScaleFactor scale2 = Address::no_scale; 7689 7690 if (ae != StrIntrinsicNode::LL) { 7691 stride2x2 = 0x20; 7692 } 7693 7694 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7695 shrl(cnt2, 1); 7696 } 7697 // Compute the minimum of the string lengths and the 7698 // difference of the string lengths (stack). 7699 // Do the conditional move stuff 7700 movl(result, cnt1); 7701 subl(cnt1, cnt2); 7702 push(cnt1); 7703 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7704 7705 // Is the minimum length zero? 7706 testl(cnt2, cnt2); 7707 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7708 if (ae == StrIntrinsicNode::LL) { 7709 // Load first bytes 7710 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7711 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7712 } else if (ae == StrIntrinsicNode::UU) { 7713 // Load first characters 7714 load_unsigned_short(result, Address(str1, 0)); 7715 load_unsigned_short(cnt1, Address(str2, 0)); 7716 } else { 7717 load_unsigned_byte(result, Address(str1, 0)); 7718 load_unsigned_short(cnt1, Address(str2, 0)); 7719 } 7720 subl(result, cnt1); 7721 jcc(Assembler::notZero, POP_LABEL); 7722 7723 if (ae == StrIntrinsicNode::UU) { 7724 // Divide length by 2 to get number of chars 7725 shrl(cnt2, 1); 7726 } 7727 cmpl(cnt2, 1); 7728 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7729 7730 // Check if the strings start at the same location and setup scale and stride 7731 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7732 cmpptr(str1, str2); 7733 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7734 if (ae == StrIntrinsicNode::LL) { 7735 scale = Address::times_1; 7736 stride = 16; 7737 } else { 7738 scale = Address::times_2; 7739 stride = 8; 7740 } 7741 } else { 7742 scale1 = Address::times_1; 7743 scale2 = Address::times_2; 7744 // scale not used 7745 stride = 8; 7746 } 7747 7748 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7749 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7750 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7751 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7752 Label COMPARE_TAIL_LONG; 7753 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7754 7755 int pcmpmask = 0x19; 7756 if (ae == StrIntrinsicNode::LL) { 7757 pcmpmask &= ~0x01; 7758 } 7759 7760 // Setup to compare 16-chars (32-bytes) vectors, 7761 // start from first character again because it has aligned address. 7762 if (ae == StrIntrinsicNode::LL) { 7763 stride2 = 32; 7764 } else { 7765 stride2 = 16; 7766 } 7767 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7768 adr_stride = stride << scale; 7769 } else { 7770 adr_stride1 = 8; //stride << scale1; 7771 adr_stride2 = 16; //stride << scale2; 7772 } 7773 7774 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7775 // rax and rdx are used by pcmpestri as elements counters 7776 movl(result, cnt2); 7777 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7778 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7779 7780 // fast path : compare first 2 8-char vectors. 7781 bind(COMPARE_16_CHARS); 7782 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7783 movdqu(vec1, Address(str1, 0)); 7784 } else { 7785 pmovzxbw(vec1, Address(str1, 0)); 7786 } 7787 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7788 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7789 7790 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7791 movdqu(vec1, Address(str1, adr_stride)); 7792 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7793 } else { 7794 pmovzxbw(vec1, Address(str1, adr_stride1)); 7795 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7796 } 7797 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7798 addl(cnt1, stride); 7799 7800 // Compare the characters at index in cnt1 7801 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7802 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7803 subl(result, cnt2); 7804 jmp(POP_LABEL); 7805 7806 // Setup the registers to start vector comparison loop 7807 bind(COMPARE_WIDE_VECTORS); 7808 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7809 lea(str1, Address(str1, result, scale)); 7810 lea(str2, Address(str2, result, scale)); 7811 } else { 7812 lea(str1, Address(str1, result, scale1)); 7813 lea(str2, Address(str2, result, scale2)); 7814 } 7815 subl(result, stride2); 7816 subl(cnt2, stride2); 7817 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7818 negptr(result); 7819 7820 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7821 bind(COMPARE_WIDE_VECTORS_LOOP); 7822 7823 #ifdef _LP64 7824 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7825 cmpl(cnt2, stride2x2); 7826 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7827 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7828 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7829 7830 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7831 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7832 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7833 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7834 } else { 7835 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7836 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7837 } 7838 kortestql(k7, k7); 7839 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7840 addptr(result, stride2x2); // update since we already compared at this addr 7841 subl(cnt2, stride2x2); // and sub the size too 7842 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7843 7844 vpxor(vec1, vec1); 7845 jmpb(COMPARE_WIDE_TAIL); 7846 }//if (VM_Version::supports_avx512vlbw()) 7847 #endif // _LP64 7848 7849 7850 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7851 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7852 vmovdqu(vec1, Address(str1, result, scale)); 7853 vpxor(vec1, Address(str2, result, scale)); 7854 } else { 7855 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7856 vpxor(vec1, Address(str2, result, scale2)); 7857 } 7858 vptest(vec1, vec1); 7859 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7860 addptr(result, stride2); 7861 subl(cnt2, stride2); 7862 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7863 // clean upper bits of YMM registers 7864 vpxor(vec1, vec1); 7865 7866 // compare wide vectors tail 7867 bind(COMPARE_WIDE_TAIL); 7868 testptr(result, result); 7869 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7870 7871 movl(result, stride2); 7872 movl(cnt2, result); 7873 negptr(result); 7874 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7875 7876 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 7877 bind(VECTOR_NOT_EQUAL); 7878 // clean upper bits of YMM registers 7879 vpxor(vec1, vec1); 7880 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7881 lea(str1, Address(str1, result, scale)); 7882 lea(str2, Address(str2, result, scale)); 7883 } else { 7884 lea(str1, Address(str1, result, scale1)); 7885 lea(str2, Address(str2, result, scale2)); 7886 } 7887 jmp(COMPARE_16_CHARS); 7888 7889 // Compare tail chars, length between 1 to 15 chars 7890 bind(COMPARE_TAIL_LONG); 7891 movl(cnt2, result); 7892 cmpl(cnt2, stride); 7893 jcc(Assembler::less, COMPARE_SMALL_STR); 7894 7895 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7896 movdqu(vec1, Address(str1, 0)); 7897 } else { 7898 pmovzxbw(vec1, Address(str1, 0)); 7899 } 7900 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7901 jcc(Assembler::below, COMPARE_INDEX_CHAR); 7902 subptr(cnt2, stride); 7903 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7904 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7905 lea(str1, Address(str1, result, scale)); 7906 lea(str2, Address(str2, result, scale)); 7907 } else { 7908 lea(str1, Address(str1, result, scale1)); 7909 lea(str2, Address(str2, result, scale2)); 7910 } 7911 negptr(cnt2); 7912 jmpb(WHILE_HEAD_LABEL); 7913 7914 bind(COMPARE_SMALL_STR); 7915 } else if (UseSSE42Intrinsics) { 7916 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 7917 int pcmpmask = 0x19; 7918 // Setup to compare 8-char (16-byte) vectors, 7919 // start from first character again because it has aligned address. 7920 movl(result, cnt2); 7921 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 7922 if (ae == StrIntrinsicNode::LL) { 7923 pcmpmask &= ~0x01; 7924 } 7925 jcc(Assembler::zero, COMPARE_TAIL); 7926 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7927 lea(str1, Address(str1, result, scale)); 7928 lea(str2, Address(str2, result, scale)); 7929 } else { 7930 lea(str1, Address(str1, result, scale1)); 7931 lea(str2, Address(str2, result, scale2)); 7932 } 7933 negptr(result); 7934 7935 // pcmpestri 7936 // inputs: 7937 // vec1- substring 7938 // rax - negative string length (elements count) 7939 // mem - scanned string 7940 // rdx - string length (elements count) 7941 // pcmpmask - cmp mode: 11000 (string compare with negated result) 7942 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 7943 // outputs: 7944 // rcx - first mismatched element index 7945 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7946 7947 bind(COMPARE_WIDE_VECTORS); 7948 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7949 movdqu(vec1, Address(str1, result, scale)); 7950 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7951 } else { 7952 pmovzxbw(vec1, Address(str1, result, scale1)); 7953 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7954 } 7955 // After pcmpestri cnt1(rcx) contains mismatched element index 7956 7957 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 7958 addptr(result, stride); 7959 subptr(cnt2, stride); 7960 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 7961 7962 // compare wide vectors tail 7963 testptr(result, result); 7964 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7965 7966 movl(cnt2, stride); 7967 movl(result, stride); 7968 negptr(result); 7969 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7970 movdqu(vec1, Address(str1, result, scale)); 7971 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7972 } else { 7973 pmovzxbw(vec1, Address(str1, result, scale1)); 7974 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7975 } 7976 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 7977 7978 // Mismatched characters in the vectors 7979 bind(VECTOR_NOT_EQUAL); 7980 addptr(cnt1, result); 7981 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7982 subl(result, cnt2); 7983 jmpb(POP_LABEL); 7984 7985 bind(COMPARE_TAIL); // limit is zero 7986 movl(cnt2, result); 7987 // Fallthru to tail compare 7988 } 7989 // Shift str2 and str1 to the end of the arrays, negate min 7990 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7991 lea(str1, Address(str1, cnt2, scale)); 7992 lea(str2, Address(str2, cnt2, scale)); 7993 } else { 7994 lea(str1, Address(str1, cnt2, scale1)); 7995 lea(str2, Address(str2, cnt2, scale2)); 7996 } 7997 decrementl(cnt2); // first character was compared already 7998 negptr(cnt2); 7999 8000 // Compare the rest of the elements 8001 bind(WHILE_HEAD_LABEL); 8002 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8003 subl(result, cnt1); 8004 jccb(Assembler::notZero, POP_LABEL); 8005 increment(cnt2); 8006 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8007 8008 // Strings are equal up to min length. Return the length difference. 8009 bind(LENGTH_DIFF_LABEL); 8010 pop(result); 8011 if (ae == StrIntrinsicNode::UU) { 8012 // Divide diff by 2 to get number of chars 8013 sarl(result, 1); 8014 } 8015 jmpb(DONE_LABEL); 8016 8017 #ifdef _LP64 8018 if (VM_Version::supports_avx512vlbw()) { 8019 8020 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8021 8022 kmovql(cnt1, k7); 8023 notq(cnt1); 8024 bsfq(cnt2, cnt1); 8025 if (ae != StrIntrinsicNode::LL) { 8026 // Divide diff by 2 to get number of chars 8027 sarl(cnt2, 1); 8028 } 8029 addq(result, cnt2); 8030 if (ae == StrIntrinsicNode::LL) { 8031 load_unsigned_byte(cnt1, Address(str2, result)); 8032 load_unsigned_byte(result, Address(str1, result)); 8033 } else if (ae == StrIntrinsicNode::UU) { 8034 load_unsigned_short(cnt1, Address(str2, result, scale)); 8035 load_unsigned_short(result, Address(str1, result, scale)); 8036 } else { 8037 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8038 load_unsigned_byte(result, Address(str1, result, scale1)); 8039 } 8040 subl(result, cnt1); 8041 jmpb(POP_LABEL); 8042 }//if (VM_Version::supports_avx512vlbw()) 8043 #endif // _LP64 8044 8045 // Discard the stored length difference 8046 bind(POP_LABEL); 8047 pop(cnt1); 8048 8049 // That's it 8050 bind(DONE_LABEL); 8051 if(ae == StrIntrinsicNode::UL) { 8052 negl(result); 8053 } 8054 8055 } 8056 8057 // Search for Non-ASCII character (Negative byte value) in a byte array, 8058 // return true if it has any and false otherwise. 8059 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8060 // @HotSpotIntrinsicCandidate 8061 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8062 // for (int i = off; i < off + len; i++) { 8063 // if (ba[i] < 0) { 8064 // return true; 8065 // } 8066 // } 8067 // return false; 8068 // } 8069 void MacroAssembler::has_negatives(Register ary1, Register len, 8070 Register result, Register tmp1, 8071 XMMRegister vec1, XMMRegister vec2) { 8072 // rsi: byte array 8073 // rcx: len 8074 // rax: result 8075 ShortBranchVerifier sbv(this); 8076 assert_different_registers(ary1, len, result, tmp1); 8077 assert_different_registers(vec1, vec2); 8078 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8079 8080 // len == 0 8081 testl(len, len); 8082 jcc(Assembler::zero, FALSE_LABEL); 8083 8084 if ((UseAVX > 2) && // AVX512 8085 VM_Version::supports_avx512vlbw() && 8086 VM_Version::supports_bmi2()) { 8087 8088 set_vector_masking(); // opening of the stub context for programming mask registers 8089 8090 Label test_64_loop, test_tail; 8091 Register tmp3_aliased = len; 8092 8093 movl(tmp1, len); 8094 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8095 8096 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8097 andl(len, ~(64 - 1)); // vector count (in chars) 8098 jccb(Assembler::zero, test_tail); 8099 8100 lea(ary1, Address(ary1, len, Address::times_1)); 8101 negptr(len); 8102 8103 bind(test_64_loop); 8104 // Check whether our 64 elements of size byte contain negatives 8105 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8106 kortestql(k2, k2); 8107 jcc(Assembler::notZero, TRUE_LABEL); 8108 8109 addptr(len, 64); 8110 jccb(Assembler::notZero, test_64_loop); 8111 8112 8113 bind(test_tail); 8114 // bail out when there is nothing to be done 8115 testl(tmp1, -1); 8116 jcc(Assembler::zero, FALSE_LABEL); 8117 8118 // Save k1 8119 kmovql(k3, k1); 8120 8121 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8122 #ifdef _LP64 8123 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8124 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8125 notq(tmp3_aliased); 8126 kmovql(k1, tmp3_aliased); 8127 #else 8128 Label k_init; 8129 jmp(k_init); 8130 8131 // We could not read 64-bits from a general purpose register thus we move 8132 // data required to compose 64 1's to the instruction stream 8133 // We emit 64 byte wide series of elements from 0..63 which later on would 8134 // be used as a compare targets with tail count contained in tmp1 register. 8135 // Result would be a k1 register having tmp1 consecutive number or 1 8136 // counting from least significant bit. 8137 address tmp = pc(); 8138 emit_int64(0x0706050403020100); 8139 emit_int64(0x0F0E0D0C0B0A0908); 8140 emit_int64(0x1716151413121110); 8141 emit_int64(0x1F1E1D1C1B1A1918); 8142 emit_int64(0x2726252423222120); 8143 emit_int64(0x2F2E2D2C2B2A2928); 8144 emit_int64(0x3736353433323130); 8145 emit_int64(0x3F3E3D3C3B3A3938); 8146 8147 bind(k_init); 8148 lea(len, InternalAddress(tmp)); 8149 // create mask to test for negative byte inside a vector 8150 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8151 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8152 8153 #endif 8154 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8155 ktestq(k2, k1); 8156 // Restore k1 8157 kmovql(k1, k3); 8158 jcc(Assembler::notZero, TRUE_LABEL); 8159 8160 jmp(FALSE_LABEL); 8161 8162 clear_vector_masking(); // closing of the stub context for programming mask registers 8163 } else { 8164 movl(result, len); // copy 8165 8166 if (UseAVX == 2 && UseSSE >= 2) { 8167 // With AVX2, use 32-byte vector compare 8168 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8169 8170 // Compare 32-byte vectors 8171 andl(result, 0x0000001f); // tail count (in bytes) 8172 andl(len, 0xffffffe0); // vector count (in bytes) 8173 jccb(Assembler::zero, COMPARE_TAIL); 8174 8175 lea(ary1, Address(ary1, len, Address::times_1)); 8176 negptr(len); 8177 8178 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8179 movdl(vec2, tmp1); 8180 vpbroadcastd(vec2, vec2); 8181 8182 bind(COMPARE_WIDE_VECTORS); 8183 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8184 vptest(vec1, vec2); 8185 jccb(Assembler::notZero, TRUE_LABEL); 8186 addptr(len, 32); 8187 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8188 8189 testl(result, result); 8190 jccb(Assembler::zero, FALSE_LABEL); 8191 8192 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8193 vptest(vec1, vec2); 8194 jccb(Assembler::notZero, TRUE_LABEL); 8195 jmpb(FALSE_LABEL); 8196 8197 bind(COMPARE_TAIL); // len is zero 8198 movl(len, result); 8199 // Fallthru to tail compare 8200 } else if (UseSSE42Intrinsics) { 8201 // With SSE4.2, use double quad vector compare 8202 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8203 8204 // Compare 16-byte vectors 8205 andl(result, 0x0000000f); // tail count (in bytes) 8206 andl(len, 0xfffffff0); // vector count (in bytes) 8207 jccb(Assembler::zero, COMPARE_TAIL); 8208 8209 lea(ary1, Address(ary1, len, Address::times_1)); 8210 negptr(len); 8211 8212 movl(tmp1, 0x80808080); 8213 movdl(vec2, tmp1); 8214 pshufd(vec2, vec2, 0); 8215 8216 bind(COMPARE_WIDE_VECTORS); 8217 movdqu(vec1, Address(ary1, len, Address::times_1)); 8218 ptest(vec1, vec2); 8219 jccb(Assembler::notZero, TRUE_LABEL); 8220 addptr(len, 16); 8221 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8222 8223 testl(result, result); 8224 jccb(Assembler::zero, FALSE_LABEL); 8225 8226 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8227 ptest(vec1, vec2); 8228 jccb(Assembler::notZero, TRUE_LABEL); 8229 jmpb(FALSE_LABEL); 8230 8231 bind(COMPARE_TAIL); // len is zero 8232 movl(len, result); 8233 // Fallthru to tail compare 8234 } 8235 } 8236 // Compare 4-byte vectors 8237 andl(len, 0xfffffffc); // vector count (in bytes) 8238 jccb(Assembler::zero, COMPARE_CHAR); 8239 8240 lea(ary1, Address(ary1, len, Address::times_1)); 8241 negptr(len); 8242 8243 bind(COMPARE_VECTORS); 8244 movl(tmp1, Address(ary1, len, Address::times_1)); 8245 andl(tmp1, 0x80808080); 8246 jccb(Assembler::notZero, TRUE_LABEL); 8247 addptr(len, 4); 8248 jcc(Assembler::notZero, COMPARE_VECTORS); 8249 8250 // Compare trailing char (final 2 bytes), if any 8251 bind(COMPARE_CHAR); 8252 testl(result, 0x2); // tail char 8253 jccb(Assembler::zero, COMPARE_BYTE); 8254 load_unsigned_short(tmp1, Address(ary1, 0)); 8255 andl(tmp1, 0x00008080); 8256 jccb(Assembler::notZero, TRUE_LABEL); 8257 subptr(result, 2); 8258 lea(ary1, Address(ary1, 2)); 8259 8260 bind(COMPARE_BYTE); 8261 testl(result, 0x1); // tail byte 8262 jccb(Assembler::zero, FALSE_LABEL); 8263 load_unsigned_byte(tmp1, Address(ary1, 0)); 8264 andl(tmp1, 0x00000080); 8265 jccb(Assembler::notEqual, TRUE_LABEL); 8266 jmpb(FALSE_LABEL); 8267 8268 bind(TRUE_LABEL); 8269 movl(result, 1); // return true 8270 jmpb(DONE); 8271 8272 bind(FALSE_LABEL); 8273 xorl(result, result); // return false 8274 8275 // That's it 8276 bind(DONE); 8277 if (UseAVX >= 2 && UseSSE >= 2) { 8278 // clean upper bits of YMM registers 8279 vpxor(vec1, vec1); 8280 vpxor(vec2, vec2); 8281 } 8282 } 8283 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8284 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8285 Register limit, Register result, Register chr, 8286 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8287 ShortBranchVerifier sbv(this); 8288 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8289 8290 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8291 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8292 8293 if (is_array_equ) { 8294 // Check the input args 8295 cmpptr(ary1, ary2); 8296 jcc(Assembler::equal, TRUE_LABEL); 8297 8298 // Need additional checks for arrays_equals. 8299 testptr(ary1, ary1); 8300 jcc(Assembler::zero, FALSE_LABEL); 8301 testptr(ary2, ary2); 8302 jcc(Assembler::zero, FALSE_LABEL); 8303 8304 // Check the lengths 8305 movl(limit, Address(ary1, length_offset)); 8306 cmpl(limit, Address(ary2, length_offset)); 8307 jcc(Assembler::notEqual, FALSE_LABEL); 8308 } 8309 8310 // count == 0 8311 testl(limit, limit); 8312 jcc(Assembler::zero, TRUE_LABEL); 8313 8314 if (is_array_equ) { 8315 // Load array address 8316 lea(ary1, Address(ary1, base_offset)); 8317 lea(ary2, Address(ary2, base_offset)); 8318 } 8319 8320 if (is_array_equ && is_char) { 8321 // arrays_equals when used for char[]. 8322 shll(limit, 1); // byte count != 0 8323 } 8324 movl(result, limit); // copy 8325 8326 if (UseAVX >= 2) { 8327 // With AVX2, use 32-byte vector compare 8328 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8329 8330 // Compare 32-byte vectors 8331 andl(result, 0x0000001f); // tail count (in bytes) 8332 andl(limit, 0xffffffe0); // vector count (in bytes) 8333 jcc(Assembler::zero, COMPARE_TAIL); 8334 8335 lea(ary1, Address(ary1, limit, Address::times_1)); 8336 lea(ary2, Address(ary2, limit, Address::times_1)); 8337 negptr(limit); 8338 8339 bind(COMPARE_WIDE_VECTORS); 8340 8341 #ifdef _LP64 8342 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8343 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8344 8345 cmpl(limit, -64); 8346 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8347 8348 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8349 8350 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8351 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8352 kortestql(k7, k7); 8353 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8354 addptr(limit, 64); // update since we already compared at this addr 8355 cmpl(limit, -64); 8356 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8357 8358 // At this point we may still need to compare -limit+result bytes. 8359 // We could execute the next two instruction and just continue via non-wide path: 8360 // cmpl(limit, 0); 8361 // jcc(Assembler::equal, COMPARE_TAIL); // true 8362 // But since we stopped at the points ary{1,2}+limit which are 8363 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8364 // (|limit| <= 32 and result < 32), 8365 // we may just compare the last 64 bytes. 8366 // 8367 addptr(result, -64); // it is safe, bc we just came from this area 8368 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8369 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8370 kortestql(k7, k7); 8371 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8372 8373 jmp(TRUE_LABEL); 8374 8375 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8376 8377 }//if (VM_Version::supports_avx512vlbw()) 8378 #endif //_LP64 8379 8380 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8381 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8382 vpxor(vec1, vec2); 8383 8384 vptest(vec1, vec1); 8385 jcc(Assembler::notZero, FALSE_LABEL); 8386 addptr(limit, 32); 8387 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8388 8389 testl(result, result); 8390 jcc(Assembler::zero, TRUE_LABEL); 8391 8392 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8393 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8394 vpxor(vec1, vec2); 8395 8396 vptest(vec1, vec1); 8397 jccb(Assembler::notZero, FALSE_LABEL); 8398 jmpb(TRUE_LABEL); 8399 8400 bind(COMPARE_TAIL); // limit is zero 8401 movl(limit, result); 8402 // Fallthru to tail compare 8403 } else if (UseSSE42Intrinsics) { 8404 // With SSE4.2, use double quad vector compare 8405 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8406 8407 // Compare 16-byte vectors 8408 andl(result, 0x0000000f); // tail count (in bytes) 8409 andl(limit, 0xfffffff0); // vector count (in bytes) 8410 jcc(Assembler::zero, COMPARE_TAIL); 8411 8412 lea(ary1, Address(ary1, limit, Address::times_1)); 8413 lea(ary2, Address(ary2, limit, Address::times_1)); 8414 negptr(limit); 8415 8416 bind(COMPARE_WIDE_VECTORS); 8417 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8418 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8419 pxor(vec1, vec2); 8420 8421 ptest(vec1, vec1); 8422 jcc(Assembler::notZero, FALSE_LABEL); 8423 addptr(limit, 16); 8424 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8425 8426 testl(result, result); 8427 jcc(Assembler::zero, TRUE_LABEL); 8428 8429 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8430 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8431 pxor(vec1, vec2); 8432 8433 ptest(vec1, vec1); 8434 jccb(Assembler::notZero, FALSE_LABEL); 8435 jmpb(TRUE_LABEL); 8436 8437 bind(COMPARE_TAIL); // limit is zero 8438 movl(limit, result); 8439 // Fallthru to tail compare 8440 } 8441 8442 // Compare 4-byte vectors 8443 andl(limit, 0xfffffffc); // vector count (in bytes) 8444 jccb(Assembler::zero, COMPARE_CHAR); 8445 8446 lea(ary1, Address(ary1, limit, Address::times_1)); 8447 lea(ary2, Address(ary2, limit, Address::times_1)); 8448 negptr(limit); 8449 8450 bind(COMPARE_VECTORS); 8451 movl(chr, Address(ary1, limit, Address::times_1)); 8452 cmpl(chr, Address(ary2, limit, Address::times_1)); 8453 jccb(Assembler::notEqual, FALSE_LABEL); 8454 addptr(limit, 4); 8455 jcc(Assembler::notZero, COMPARE_VECTORS); 8456 8457 // Compare trailing char (final 2 bytes), if any 8458 bind(COMPARE_CHAR); 8459 testl(result, 0x2); // tail char 8460 jccb(Assembler::zero, COMPARE_BYTE); 8461 load_unsigned_short(chr, Address(ary1, 0)); 8462 load_unsigned_short(limit, Address(ary2, 0)); 8463 cmpl(chr, limit); 8464 jccb(Assembler::notEqual, FALSE_LABEL); 8465 8466 if (is_array_equ && is_char) { 8467 bind(COMPARE_BYTE); 8468 } else { 8469 lea(ary1, Address(ary1, 2)); 8470 lea(ary2, Address(ary2, 2)); 8471 8472 bind(COMPARE_BYTE); 8473 testl(result, 0x1); // tail byte 8474 jccb(Assembler::zero, TRUE_LABEL); 8475 load_unsigned_byte(chr, Address(ary1, 0)); 8476 load_unsigned_byte(limit, Address(ary2, 0)); 8477 cmpl(chr, limit); 8478 jccb(Assembler::notEqual, FALSE_LABEL); 8479 } 8480 bind(TRUE_LABEL); 8481 movl(result, 1); // return true 8482 jmpb(DONE); 8483 8484 bind(FALSE_LABEL); 8485 xorl(result, result); // return false 8486 8487 // That's it 8488 bind(DONE); 8489 if (UseAVX >= 2) { 8490 // clean upper bits of YMM registers 8491 vpxor(vec1, vec1); 8492 vpxor(vec2, vec2); 8493 } 8494 } 8495 8496 #endif 8497 8498 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8499 Register to, Register value, Register count, 8500 Register rtmp, XMMRegister xtmp) { 8501 ShortBranchVerifier sbv(this); 8502 assert_different_registers(to, value, count, rtmp); 8503 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8504 Label L_fill_2_bytes, L_fill_4_bytes; 8505 8506 int shift = -1; 8507 switch (t) { 8508 case T_BYTE: 8509 shift = 2; 8510 break; 8511 case T_SHORT: 8512 shift = 1; 8513 break; 8514 case T_INT: 8515 shift = 0; 8516 break; 8517 default: ShouldNotReachHere(); 8518 } 8519 8520 if (t == T_BYTE) { 8521 andl(value, 0xff); 8522 movl(rtmp, value); 8523 shll(rtmp, 8); 8524 orl(value, rtmp); 8525 } 8526 if (t == T_SHORT) { 8527 andl(value, 0xffff); 8528 } 8529 if (t == T_BYTE || t == T_SHORT) { 8530 movl(rtmp, value); 8531 shll(rtmp, 16); 8532 orl(value, rtmp); 8533 } 8534 8535 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8536 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8537 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8538 // align source address at 4 bytes address boundary 8539 if (t == T_BYTE) { 8540 // One byte misalignment happens only for byte arrays 8541 testptr(to, 1); 8542 jccb(Assembler::zero, L_skip_align1); 8543 movb(Address(to, 0), value); 8544 increment(to); 8545 decrement(count); 8546 BIND(L_skip_align1); 8547 } 8548 // Two bytes misalignment happens only for byte and short (char) arrays 8549 testptr(to, 2); 8550 jccb(Assembler::zero, L_skip_align2); 8551 movw(Address(to, 0), value); 8552 addptr(to, 2); 8553 subl(count, 1<<(shift-1)); 8554 BIND(L_skip_align2); 8555 } 8556 if (UseSSE < 2) { 8557 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8558 // Fill 32-byte chunks 8559 subl(count, 8 << shift); 8560 jcc(Assembler::less, L_check_fill_8_bytes); 8561 align(16); 8562 8563 BIND(L_fill_32_bytes_loop); 8564 8565 for (int i = 0; i < 32; i += 4) { 8566 movl(Address(to, i), value); 8567 } 8568 8569 addptr(to, 32); 8570 subl(count, 8 << shift); 8571 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8572 BIND(L_check_fill_8_bytes); 8573 addl(count, 8 << shift); 8574 jccb(Assembler::zero, L_exit); 8575 jmpb(L_fill_8_bytes); 8576 8577 // 8578 // length is too short, just fill qwords 8579 // 8580 BIND(L_fill_8_bytes_loop); 8581 movl(Address(to, 0), value); 8582 movl(Address(to, 4), value); 8583 addptr(to, 8); 8584 BIND(L_fill_8_bytes); 8585 subl(count, 1 << (shift + 1)); 8586 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8587 // fall through to fill 4 bytes 8588 } else { 8589 Label L_fill_32_bytes; 8590 if (!UseUnalignedLoadStores) { 8591 // align to 8 bytes, we know we are 4 byte aligned to start 8592 testptr(to, 4); 8593 jccb(Assembler::zero, L_fill_32_bytes); 8594 movl(Address(to, 0), value); 8595 addptr(to, 4); 8596 subl(count, 1<<shift); 8597 } 8598 BIND(L_fill_32_bytes); 8599 { 8600 assert( UseSSE >= 2, "supported cpu only" ); 8601 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8602 if (UseAVX > 2) { 8603 movl(rtmp, 0xffff); 8604 kmovwl(k1, rtmp); 8605 } 8606 movdl(xtmp, value); 8607 if (UseAVX > 2 && UseUnalignedLoadStores) { 8608 // Fill 64-byte chunks 8609 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8610 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8611 8612 subl(count, 16 << shift); 8613 jcc(Assembler::less, L_check_fill_32_bytes); 8614 align(16); 8615 8616 BIND(L_fill_64_bytes_loop); 8617 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8618 addptr(to, 64); 8619 subl(count, 16 << shift); 8620 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8621 8622 BIND(L_check_fill_32_bytes); 8623 addl(count, 8 << shift); 8624 jccb(Assembler::less, L_check_fill_8_bytes); 8625 vmovdqu(Address(to, 0), xtmp); 8626 addptr(to, 32); 8627 subl(count, 8 << shift); 8628 8629 BIND(L_check_fill_8_bytes); 8630 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8631 // Fill 64-byte chunks 8632 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8633 vpbroadcastd(xtmp, xtmp); 8634 8635 subl(count, 16 << shift); 8636 jcc(Assembler::less, L_check_fill_32_bytes); 8637 align(16); 8638 8639 BIND(L_fill_64_bytes_loop); 8640 vmovdqu(Address(to, 0), xtmp); 8641 vmovdqu(Address(to, 32), xtmp); 8642 addptr(to, 64); 8643 subl(count, 16 << shift); 8644 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8645 8646 BIND(L_check_fill_32_bytes); 8647 addl(count, 8 << shift); 8648 jccb(Assembler::less, L_check_fill_8_bytes); 8649 vmovdqu(Address(to, 0), xtmp); 8650 addptr(to, 32); 8651 subl(count, 8 << shift); 8652 8653 BIND(L_check_fill_8_bytes); 8654 // clean upper bits of YMM registers 8655 movdl(xtmp, value); 8656 pshufd(xtmp, xtmp, 0); 8657 } else { 8658 // Fill 32-byte chunks 8659 pshufd(xtmp, xtmp, 0); 8660 8661 subl(count, 8 << shift); 8662 jcc(Assembler::less, L_check_fill_8_bytes); 8663 align(16); 8664 8665 BIND(L_fill_32_bytes_loop); 8666 8667 if (UseUnalignedLoadStores) { 8668 movdqu(Address(to, 0), xtmp); 8669 movdqu(Address(to, 16), xtmp); 8670 } else { 8671 movq(Address(to, 0), xtmp); 8672 movq(Address(to, 8), xtmp); 8673 movq(Address(to, 16), xtmp); 8674 movq(Address(to, 24), xtmp); 8675 } 8676 8677 addptr(to, 32); 8678 subl(count, 8 << shift); 8679 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8680 8681 BIND(L_check_fill_8_bytes); 8682 } 8683 addl(count, 8 << shift); 8684 jccb(Assembler::zero, L_exit); 8685 jmpb(L_fill_8_bytes); 8686 8687 // 8688 // length is too short, just fill qwords 8689 // 8690 BIND(L_fill_8_bytes_loop); 8691 movq(Address(to, 0), xtmp); 8692 addptr(to, 8); 8693 BIND(L_fill_8_bytes); 8694 subl(count, 1 << (shift + 1)); 8695 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8696 } 8697 } 8698 // fill trailing 4 bytes 8699 BIND(L_fill_4_bytes); 8700 testl(count, 1<<shift); 8701 jccb(Assembler::zero, L_fill_2_bytes); 8702 movl(Address(to, 0), value); 8703 if (t == T_BYTE || t == T_SHORT) { 8704 addptr(to, 4); 8705 BIND(L_fill_2_bytes); 8706 // fill trailing 2 bytes 8707 testl(count, 1<<(shift-1)); 8708 jccb(Assembler::zero, L_fill_byte); 8709 movw(Address(to, 0), value); 8710 if (t == T_BYTE) { 8711 addptr(to, 2); 8712 BIND(L_fill_byte); 8713 // fill trailing byte 8714 testl(count, 1); 8715 jccb(Assembler::zero, L_exit); 8716 movb(Address(to, 0), value); 8717 } else { 8718 BIND(L_fill_byte); 8719 } 8720 } else { 8721 BIND(L_fill_2_bytes); 8722 } 8723 BIND(L_exit); 8724 } 8725 8726 // encode char[] to byte[] in ISO_8859_1 8727 //@HotSpotIntrinsicCandidate 8728 //private static int implEncodeISOArray(byte[] sa, int sp, 8729 //byte[] da, int dp, int len) { 8730 // int i = 0; 8731 // for (; i < len; i++) { 8732 // char c = StringUTF16.getChar(sa, sp++); 8733 // if (c > '\u00FF') 8734 // break; 8735 // da[dp++] = (byte)c; 8736 // } 8737 // return i; 8738 //} 8739 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8740 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8741 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8742 Register tmp5, Register result) { 8743 8744 // rsi: src 8745 // rdi: dst 8746 // rdx: len 8747 // rcx: tmp5 8748 // rax: result 8749 ShortBranchVerifier sbv(this); 8750 assert_different_registers(src, dst, len, tmp5, result); 8751 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8752 8753 // set result 8754 xorl(result, result); 8755 // check for zero length 8756 testl(len, len); 8757 jcc(Assembler::zero, L_done); 8758 8759 movl(result, len); 8760 8761 // Setup pointers 8762 lea(src, Address(src, len, Address::times_2)); // char[] 8763 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8764 negptr(len); 8765 8766 if (UseSSE42Intrinsics || UseAVX >= 2) { 8767 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8768 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8769 8770 if (UseAVX >= 2) { 8771 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8772 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8773 movdl(tmp1Reg, tmp5); 8774 vpbroadcastd(tmp1Reg, tmp1Reg); 8775 jmp(L_chars_32_check); 8776 8777 bind(L_copy_32_chars); 8778 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8779 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8780 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8781 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8782 jccb(Assembler::notZero, L_copy_32_chars_exit); 8783 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8784 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8785 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8786 8787 bind(L_chars_32_check); 8788 addptr(len, 32); 8789 jcc(Assembler::lessEqual, L_copy_32_chars); 8790 8791 bind(L_copy_32_chars_exit); 8792 subptr(len, 16); 8793 jccb(Assembler::greater, L_copy_16_chars_exit); 8794 8795 } else if (UseSSE42Intrinsics) { 8796 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8797 movdl(tmp1Reg, tmp5); 8798 pshufd(tmp1Reg, tmp1Reg, 0); 8799 jmpb(L_chars_16_check); 8800 } 8801 8802 bind(L_copy_16_chars); 8803 if (UseAVX >= 2) { 8804 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8805 vptest(tmp2Reg, tmp1Reg); 8806 jcc(Assembler::notZero, L_copy_16_chars_exit); 8807 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8808 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8809 } else { 8810 if (UseAVX > 0) { 8811 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8812 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8813 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8814 } else { 8815 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8816 por(tmp2Reg, tmp3Reg); 8817 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8818 por(tmp2Reg, tmp4Reg); 8819 } 8820 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8821 jccb(Assembler::notZero, L_copy_16_chars_exit); 8822 packuswb(tmp3Reg, tmp4Reg); 8823 } 8824 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8825 8826 bind(L_chars_16_check); 8827 addptr(len, 16); 8828 jcc(Assembler::lessEqual, L_copy_16_chars); 8829 8830 bind(L_copy_16_chars_exit); 8831 if (UseAVX >= 2) { 8832 // clean upper bits of YMM registers 8833 vpxor(tmp2Reg, tmp2Reg); 8834 vpxor(tmp3Reg, tmp3Reg); 8835 vpxor(tmp4Reg, tmp4Reg); 8836 movdl(tmp1Reg, tmp5); 8837 pshufd(tmp1Reg, tmp1Reg, 0); 8838 } 8839 subptr(len, 8); 8840 jccb(Assembler::greater, L_copy_8_chars_exit); 8841 8842 bind(L_copy_8_chars); 8843 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8844 ptest(tmp3Reg, tmp1Reg); 8845 jccb(Assembler::notZero, L_copy_8_chars_exit); 8846 packuswb(tmp3Reg, tmp1Reg); 8847 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8848 addptr(len, 8); 8849 jccb(Assembler::lessEqual, L_copy_8_chars); 8850 8851 bind(L_copy_8_chars_exit); 8852 subptr(len, 8); 8853 jccb(Assembler::zero, L_done); 8854 } 8855 8856 bind(L_copy_1_char); 8857 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8858 testl(tmp5, 0xff00); // check if Unicode char 8859 jccb(Assembler::notZero, L_copy_1_char_exit); 8860 movb(Address(dst, len, Address::times_1, 0), tmp5); 8861 addptr(len, 1); 8862 jccb(Assembler::less, L_copy_1_char); 8863 8864 bind(L_copy_1_char_exit); 8865 addptr(result, len); // len is negative count of not processed elements 8866 8867 bind(L_done); 8868 } 8869 8870 #ifdef _LP64 8871 /** 8872 * Helper for multiply_to_len(). 8873 */ 8874 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8875 addq(dest_lo, src1); 8876 adcq(dest_hi, 0); 8877 addq(dest_lo, src2); 8878 adcq(dest_hi, 0); 8879 } 8880 8881 /** 8882 * Multiply 64 bit by 64 bit first loop. 8883 */ 8884 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8885 Register y, Register y_idx, Register z, 8886 Register carry, Register product, 8887 Register idx, Register kdx) { 8888 // 8889 // jlong carry, x[], y[], z[]; 8890 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8891 // huge_128 product = y[idx] * x[xstart] + carry; 8892 // z[kdx] = (jlong)product; 8893 // carry = (jlong)(product >>> 64); 8894 // } 8895 // z[xstart] = carry; 8896 // 8897 8898 Label L_first_loop, L_first_loop_exit; 8899 Label L_one_x, L_one_y, L_multiply; 8900 8901 decrementl(xstart); 8902 jcc(Assembler::negative, L_one_x); 8903 8904 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8905 rorq(x_xstart, 32); // convert big-endian to little-endian 8906 8907 bind(L_first_loop); 8908 decrementl(idx); 8909 jcc(Assembler::negative, L_first_loop_exit); 8910 decrementl(idx); 8911 jcc(Assembler::negative, L_one_y); 8912 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8913 rorq(y_idx, 32); // convert big-endian to little-endian 8914 bind(L_multiply); 8915 movq(product, x_xstart); 8916 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 8917 addq(product, carry); 8918 adcq(rdx, 0); 8919 subl(kdx, 2); 8920 movl(Address(z, kdx, Address::times_4, 4), product); 8921 shrq(product, 32); 8922 movl(Address(z, kdx, Address::times_4, 0), product); 8923 movq(carry, rdx); 8924 jmp(L_first_loop); 8925 8926 bind(L_one_y); 8927 movl(y_idx, Address(y, 0)); 8928 jmp(L_multiply); 8929 8930 bind(L_one_x); 8931 movl(x_xstart, Address(x, 0)); 8932 jmp(L_first_loop); 8933 8934 bind(L_first_loop_exit); 8935 } 8936 8937 /** 8938 * Multiply 64 bit by 64 bit and add 128 bit. 8939 */ 8940 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 8941 Register yz_idx, Register idx, 8942 Register carry, Register product, int offset) { 8943 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 8944 // z[kdx] = (jlong)product; 8945 8946 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 8947 rorq(yz_idx, 32); // convert big-endian to little-endian 8948 movq(product, x_xstart); 8949 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 8950 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 8951 rorq(yz_idx, 32); // convert big-endian to little-endian 8952 8953 add2_with_carry(rdx, product, carry, yz_idx); 8954 8955 movl(Address(z, idx, Address::times_4, offset+4), product); 8956 shrq(product, 32); 8957 movl(Address(z, idx, Address::times_4, offset), product); 8958 8959 } 8960 8961 /** 8962 * Multiply 128 bit by 128 bit. Unrolled inner loop. 8963 */ 8964 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 8965 Register yz_idx, Register idx, Register jdx, 8966 Register carry, Register product, 8967 Register carry2) { 8968 // jlong carry, x[], y[], z[]; 8969 // int kdx = ystart+1; 8970 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 8971 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 8972 // z[kdx+idx+1] = (jlong)product; 8973 // jlong carry2 = (jlong)(product >>> 64); 8974 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 8975 // z[kdx+idx] = (jlong)product; 8976 // carry = (jlong)(product >>> 64); 8977 // } 8978 // idx += 2; 8979 // if (idx > 0) { 8980 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 8981 // z[kdx+idx] = (jlong)product; 8982 // carry = (jlong)(product >>> 64); 8983 // } 8984 // 8985 8986 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 8987 8988 movl(jdx, idx); 8989 andl(jdx, 0xFFFFFFFC); 8990 shrl(jdx, 2); 8991 8992 bind(L_third_loop); 8993 subl(jdx, 1); 8994 jcc(Assembler::negative, L_third_loop_exit); 8995 subl(idx, 4); 8996 8997 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 8998 movq(carry2, rdx); 8999 9000 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9001 movq(carry, rdx); 9002 jmp(L_third_loop); 9003 9004 bind (L_third_loop_exit); 9005 9006 andl (idx, 0x3); 9007 jcc(Assembler::zero, L_post_third_loop_done); 9008 9009 Label L_check_1; 9010 subl(idx, 2); 9011 jcc(Assembler::negative, L_check_1); 9012 9013 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9014 movq(carry, rdx); 9015 9016 bind (L_check_1); 9017 addl (idx, 0x2); 9018 andl (idx, 0x1); 9019 subl(idx, 1); 9020 jcc(Assembler::negative, L_post_third_loop_done); 9021 9022 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9023 movq(product, x_xstart); 9024 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9025 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9026 9027 add2_with_carry(rdx, product, yz_idx, carry); 9028 9029 movl(Address(z, idx, Address::times_4, 0), product); 9030 shrq(product, 32); 9031 9032 shlq(rdx, 32); 9033 orq(product, rdx); 9034 movq(carry, product); 9035 9036 bind(L_post_third_loop_done); 9037 } 9038 9039 /** 9040 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9041 * 9042 */ 9043 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9044 Register carry, Register carry2, 9045 Register idx, Register jdx, 9046 Register yz_idx1, Register yz_idx2, 9047 Register tmp, Register tmp3, Register tmp4) { 9048 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9049 9050 // jlong carry, x[], y[], z[]; 9051 // int kdx = ystart+1; 9052 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9053 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9054 // jlong carry2 = (jlong)(tmp3 >>> 64); 9055 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9056 // carry = (jlong)(tmp4 >>> 64); 9057 // z[kdx+idx+1] = (jlong)tmp3; 9058 // z[kdx+idx] = (jlong)tmp4; 9059 // } 9060 // idx += 2; 9061 // if (idx > 0) { 9062 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9063 // z[kdx+idx] = (jlong)yz_idx1; 9064 // carry = (jlong)(yz_idx1 >>> 64); 9065 // } 9066 // 9067 9068 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9069 9070 movl(jdx, idx); 9071 andl(jdx, 0xFFFFFFFC); 9072 shrl(jdx, 2); 9073 9074 bind(L_third_loop); 9075 subl(jdx, 1); 9076 jcc(Assembler::negative, L_third_loop_exit); 9077 subl(idx, 4); 9078 9079 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9080 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9081 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9082 rorxq(yz_idx2, yz_idx2, 32); 9083 9084 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9085 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9086 9087 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9088 rorxq(yz_idx1, yz_idx1, 32); 9089 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9090 rorxq(yz_idx2, yz_idx2, 32); 9091 9092 if (VM_Version::supports_adx()) { 9093 adcxq(tmp3, carry); 9094 adoxq(tmp3, yz_idx1); 9095 9096 adcxq(tmp4, tmp); 9097 adoxq(tmp4, yz_idx2); 9098 9099 movl(carry, 0); // does not affect flags 9100 adcxq(carry2, carry); 9101 adoxq(carry2, carry); 9102 } else { 9103 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9104 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9105 } 9106 movq(carry, carry2); 9107 9108 movl(Address(z, idx, Address::times_4, 12), tmp3); 9109 shrq(tmp3, 32); 9110 movl(Address(z, idx, Address::times_4, 8), tmp3); 9111 9112 movl(Address(z, idx, Address::times_4, 4), tmp4); 9113 shrq(tmp4, 32); 9114 movl(Address(z, idx, Address::times_4, 0), tmp4); 9115 9116 jmp(L_third_loop); 9117 9118 bind (L_third_loop_exit); 9119 9120 andl (idx, 0x3); 9121 jcc(Assembler::zero, L_post_third_loop_done); 9122 9123 Label L_check_1; 9124 subl(idx, 2); 9125 jcc(Assembler::negative, L_check_1); 9126 9127 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9128 rorxq(yz_idx1, yz_idx1, 32); 9129 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9130 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9131 rorxq(yz_idx2, yz_idx2, 32); 9132 9133 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9134 9135 movl(Address(z, idx, Address::times_4, 4), tmp3); 9136 shrq(tmp3, 32); 9137 movl(Address(z, idx, Address::times_4, 0), tmp3); 9138 movq(carry, tmp4); 9139 9140 bind (L_check_1); 9141 addl (idx, 0x2); 9142 andl (idx, 0x1); 9143 subl(idx, 1); 9144 jcc(Assembler::negative, L_post_third_loop_done); 9145 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9146 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9147 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9148 9149 add2_with_carry(carry2, tmp3, tmp4, carry); 9150 9151 movl(Address(z, idx, Address::times_4, 0), tmp3); 9152 shrq(tmp3, 32); 9153 9154 shlq(carry2, 32); 9155 orq(tmp3, carry2); 9156 movq(carry, tmp3); 9157 9158 bind(L_post_third_loop_done); 9159 } 9160 9161 /** 9162 * Code for BigInteger::multiplyToLen() instrinsic. 9163 * 9164 * rdi: x 9165 * rax: xlen 9166 * rsi: y 9167 * rcx: ylen 9168 * r8: z 9169 * r11: zlen 9170 * r12: tmp1 9171 * r13: tmp2 9172 * r14: tmp3 9173 * r15: tmp4 9174 * rbx: tmp5 9175 * 9176 */ 9177 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9178 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9179 ShortBranchVerifier sbv(this); 9180 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9181 9182 push(tmp1); 9183 push(tmp2); 9184 push(tmp3); 9185 push(tmp4); 9186 push(tmp5); 9187 9188 push(xlen); 9189 push(zlen); 9190 9191 const Register idx = tmp1; 9192 const Register kdx = tmp2; 9193 const Register xstart = tmp3; 9194 9195 const Register y_idx = tmp4; 9196 const Register carry = tmp5; 9197 const Register product = xlen; 9198 const Register x_xstart = zlen; // reuse register 9199 9200 // First Loop. 9201 // 9202 // final static long LONG_MASK = 0xffffffffL; 9203 // int xstart = xlen - 1; 9204 // int ystart = ylen - 1; 9205 // long carry = 0; 9206 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9207 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9208 // z[kdx] = (int)product; 9209 // carry = product >>> 32; 9210 // } 9211 // z[xstart] = (int)carry; 9212 // 9213 9214 movl(idx, ylen); // idx = ylen; 9215 movl(kdx, zlen); // kdx = xlen+ylen; 9216 xorq(carry, carry); // carry = 0; 9217 9218 Label L_done; 9219 9220 movl(xstart, xlen); 9221 decrementl(xstart); 9222 jcc(Assembler::negative, L_done); 9223 9224 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9225 9226 Label L_second_loop; 9227 testl(kdx, kdx); 9228 jcc(Assembler::zero, L_second_loop); 9229 9230 Label L_carry; 9231 subl(kdx, 1); 9232 jcc(Assembler::zero, L_carry); 9233 9234 movl(Address(z, kdx, Address::times_4, 0), carry); 9235 shrq(carry, 32); 9236 subl(kdx, 1); 9237 9238 bind(L_carry); 9239 movl(Address(z, kdx, Address::times_4, 0), carry); 9240 9241 // Second and third (nested) loops. 9242 // 9243 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9244 // carry = 0; 9245 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9246 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9247 // (z[k] & LONG_MASK) + carry; 9248 // z[k] = (int)product; 9249 // carry = product >>> 32; 9250 // } 9251 // z[i] = (int)carry; 9252 // } 9253 // 9254 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9255 9256 const Register jdx = tmp1; 9257 9258 bind(L_second_loop); 9259 xorl(carry, carry); // carry = 0; 9260 movl(jdx, ylen); // j = ystart+1 9261 9262 subl(xstart, 1); // i = xstart-1; 9263 jcc(Assembler::negative, L_done); 9264 9265 push (z); 9266 9267 Label L_last_x; 9268 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9269 subl(xstart, 1); // i = xstart-1; 9270 jcc(Assembler::negative, L_last_x); 9271 9272 if (UseBMI2Instructions) { 9273 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9274 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9275 } else { 9276 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9277 rorq(x_xstart, 32); // convert big-endian to little-endian 9278 } 9279 9280 Label L_third_loop_prologue; 9281 bind(L_third_loop_prologue); 9282 9283 push (x); 9284 push (xstart); 9285 push (ylen); 9286 9287 9288 if (UseBMI2Instructions) { 9289 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9290 } else { // !UseBMI2Instructions 9291 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9292 } 9293 9294 pop(ylen); 9295 pop(xlen); 9296 pop(x); 9297 pop(z); 9298 9299 movl(tmp3, xlen); 9300 addl(tmp3, 1); 9301 movl(Address(z, tmp3, Address::times_4, 0), carry); 9302 subl(tmp3, 1); 9303 jccb(Assembler::negative, L_done); 9304 9305 shrq(carry, 32); 9306 movl(Address(z, tmp3, Address::times_4, 0), carry); 9307 jmp(L_second_loop); 9308 9309 // Next infrequent code is moved outside loops. 9310 bind(L_last_x); 9311 if (UseBMI2Instructions) { 9312 movl(rdx, Address(x, 0)); 9313 } else { 9314 movl(x_xstart, Address(x, 0)); 9315 } 9316 jmp(L_third_loop_prologue); 9317 9318 bind(L_done); 9319 9320 pop(zlen); 9321 pop(xlen); 9322 9323 pop(tmp5); 9324 pop(tmp4); 9325 pop(tmp3); 9326 pop(tmp2); 9327 pop(tmp1); 9328 } 9329 9330 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9331 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9332 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9333 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9334 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9335 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9336 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9337 Label SAME_TILL_END, DONE; 9338 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9339 9340 //scale is in rcx in both Win64 and Unix 9341 ShortBranchVerifier sbv(this); 9342 9343 shlq(length); 9344 xorq(result, result); 9345 9346 if ((UseAVX > 2) && 9347 VM_Version::supports_avx512vlbw()) { 9348 set_vector_masking(); // opening of the stub context for programming mask registers 9349 cmpq(length, 64); 9350 jcc(Assembler::less, VECTOR32_TAIL); 9351 movq(tmp1, length); 9352 andq(tmp1, 0x3F); // tail count 9353 andq(length, ~(0x3F)); //vector count 9354 9355 bind(VECTOR64_LOOP); 9356 // AVX512 code to compare 64 byte vectors. 9357 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9358 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9359 kortestql(k7, k7); 9360 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9361 addq(result, 64); 9362 subq(length, 64); 9363 jccb(Assembler::notZero, VECTOR64_LOOP); 9364 9365 //bind(VECTOR64_TAIL); 9366 testq(tmp1, tmp1); 9367 jcc(Assembler::zero, SAME_TILL_END); 9368 9369 bind(VECTOR64_TAIL); 9370 // AVX512 code to compare upto 63 byte vectors. 9371 // Save k1 9372 kmovql(k3, k1); 9373 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9374 shlxq(tmp2, tmp2, tmp1); 9375 notq(tmp2); 9376 kmovql(k1, tmp2); 9377 9378 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9379 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9380 9381 ktestql(k7, k1); 9382 // Restore k1 9383 kmovql(k1, k3); 9384 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9385 9386 bind(VECTOR64_NOT_EQUAL); 9387 kmovql(tmp1, k7); 9388 notq(tmp1); 9389 tzcntq(tmp1, tmp1); 9390 addq(result, tmp1); 9391 shrq(result); 9392 jmp(DONE); 9393 bind(VECTOR32_TAIL); 9394 clear_vector_masking(); // closing of the stub context for programming mask registers 9395 } 9396 9397 cmpq(length, 8); 9398 jcc(Assembler::equal, VECTOR8_LOOP); 9399 jcc(Assembler::less, VECTOR4_TAIL); 9400 9401 if (UseAVX >= 2) { 9402 9403 cmpq(length, 16); 9404 jcc(Assembler::equal, VECTOR16_LOOP); 9405 jcc(Assembler::less, VECTOR8_LOOP); 9406 9407 cmpq(length, 32); 9408 jccb(Assembler::less, VECTOR16_TAIL); 9409 9410 subq(length, 32); 9411 bind(VECTOR32_LOOP); 9412 vmovdqu(rymm0, Address(obja, result)); 9413 vmovdqu(rymm1, Address(objb, result)); 9414 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9415 vptest(rymm2, rymm2); 9416 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9417 addq(result, 32); 9418 subq(length, 32); 9419 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9420 addq(length, 32); 9421 jcc(Assembler::equal, SAME_TILL_END); 9422 //falling through if less than 32 bytes left //close the branch here. 9423 9424 bind(VECTOR16_TAIL); 9425 cmpq(length, 16); 9426 jccb(Assembler::less, VECTOR8_TAIL); 9427 bind(VECTOR16_LOOP); 9428 movdqu(rymm0, Address(obja, result)); 9429 movdqu(rymm1, Address(objb, result)); 9430 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9431 ptest(rymm2, rymm2); 9432 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9433 addq(result, 16); 9434 subq(length, 16); 9435 jcc(Assembler::equal, SAME_TILL_END); 9436 //falling through if less than 16 bytes left 9437 } else {//regular intrinsics 9438 9439 cmpq(length, 16); 9440 jccb(Assembler::less, VECTOR8_TAIL); 9441 9442 subq(length, 16); 9443 bind(VECTOR16_LOOP); 9444 movdqu(rymm0, Address(obja, result)); 9445 movdqu(rymm1, Address(objb, result)); 9446 pxor(rymm0, rymm1); 9447 ptest(rymm0, rymm0); 9448 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9449 addq(result, 16); 9450 subq(length, 16); 9451 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9452 addq(length, 16); 9453 jcc(Assembler::equal, SAME_TILL_END); 9454 //falling through if less than 16 bytes left 9455 } 9456 9457 bind(VECTOR8_TAIL); 9458 cmpq(length, 8); 9459 jccb(Assembler::less, VECTOR4_TAIL); 9460 bind(VECTOR8_LOOP); 9461 movq(tmp1, Address(obja, result)); 9462 movq(tmp2, Address(objb, result)); 9463 xorq(tmp1, tmp2); 9464 testq(tmp1, tmp1); 9465 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9466 addq(result, 8); 9467 subq(length, 8); 9468 jcc(Assembler::equal, SAME_TILL_END); 9469 //falling through if less than 8 bytes left 9470 9471 bind(VECTOR4_TAIL); 9472 cmpq(length, 4); 9473 jccb(Assembler::less, BYTES_TAIL); 9474 bind(VECTOR4_LOOP); 9475 movl(tmp1, Address(obja, result)); 9476 xorl(tmp1, Address(objb, result)); 9477 testl(tmp1, tmp1); 9478 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9479 addq(result, 4); 9480 subq(length, 4); 9481 jcc(Assembler::equal, SAME_TILL_END); 9482 //falling through if less than 4 bytes left 9483 9484 bind(BYTES_TAIL); 9485 bind(BYTES_LOOP); 9486 load_unsigned_byte(tmp1, Address(obja, result)); 9487 load_unsigned_byte(tmp2, Address(objb, result)); 9488 xorl(tmp1, tmp2); 9489 testl(tmp1, tmp1); 9490 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9491 decq(length); 9492 jccb(Assembler::zero, SAME_TILL_END); 9493 incq(result); 9494 load_unsigned_byte(tmp1, Address(obja, result)); 9495 load_unsigned_byte(tmp2, Address(objb, result)); 9496 xorl(tmp1, tmp2); 9497 testl(tmp1, tmp1); 9498 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9499 decq(length); 9500 jccb(Assembler::zero, SAME_TILL_END); 9501 incq(result); 9502 load_unsigned_byte(tmp1, Address(obja, result)); 9503 load_unsigned_byte(tmp2, Address(objb, result)); 9504 xorl(tmp1, tmp2); 9505 testl(tmp1, tmp1); 9506 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9507 jmpb(SAME_TILL_END); 9508 9509 if (UseAVX >= 2) { 9510 bind(VECTOR32_NOT_EQUAL); 9511 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9512 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9513 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9514 vpmovmskb(tmp1, rymm0); 9515 bsfq(tmp1, tmp1); 9516 addq(result, tmp1); 9517 shrq(result); 9518 jmpb(DONE); 9519 } 9520 9521 bind(VECTOR16_NOT_EQUAL); 9522 if (UseAVX >= 2) { 9523 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9524 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9525 pxor(rymm0, rymm2); 9526 } else { 9527 pcmpeqb(rymm2, rymm2); 9528 pxor(rymm0, rymm1); 9529 pcmpeqb(rymm0, rymm1); 9530 pxor(rymm0, rymm2); 9531 } 9532 pmovmskb(tmp1, rymm0); 9533 bsfq(tmp1, tmp1); 9534 addq(result, tmp1); 9535 shrq(result); 9536 jmpb(DONE); 9537 9538 bind(VECTOR8_NOT_EQUAL); 9539 bind(VECTOR4_NOT_EQUAL); 9540 bsfq(tmp1, tmp1); 9541 shrq(tmp1, 3); 9542 addq(result, tmp1); 9543 bind(BYTES_NOT_EQUAL); 9544 shrq(result); 9545 jmpb(DONE); 9546 9547 bind(SAME_TILL_END); 9548 mov64(result, -1); 9549 9550 bind(DONE); 9551 } 9552 9553 //Helper functions for square_to_len() 9554 9555 /** 9556 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9557 * Preserves x and z and modifies rest of the registers. 9558 */ 9559 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9560 // Perform square and right shift by 1 9561 // Handle odd xlen case first, then for even xlen do the following 9562 // jlong carry = 0; 9563 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9564 // huge_128 product = x[j:j+1] * x[j:j+1]; 9565 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9566 // z[i+2:i+3] = (jlong)(product >>> 1); 9567 // carry = (jlong)product; 9568 // } 9569 9570 xorq(tmp5, tmp5); // carry 9571 xorq(rdxReg, rdxReg); 9572 xorl(tmp1, tmp1); // index for x 9573 xorl(tmp4, tmp4); // index for z 9574 9575 Label L_first_loop, L_first_loop_exit; 9576 9577 testl(xlen, 1); 9578 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9579 9580 // Square and right shift by 1 the odd element using 32 bit multiply 9581 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9582 imulq(raxReg, raxReg); 9583 shrq(raxReg, 1); 9584 adcq(tmp5, 0); 9585 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9586 incrementl(tmp1); 9587 addl(tmp4, 2); 9588 9589 // Square and right shift by 1 the rest using 64 bit multiply 9590 bind(L_first_loop); 9591 cmpptr(tmp1, xlen); 9592 jccb(Assembler::equal, L_first_loop_exit); 9593 9594 // Square 9595 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9596 rorq(raxReg, 32); // convert big-endian to little-endian 9597 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9598 9599 // Right shift by 1 and save carry 9600 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9601 rcrq(rdxReg, 1); 9602 rcrq(raxReg, 1); 9603 adcq(tmp5, 0); 9604 9605 // Store result in z 9606 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9607 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9608 9609 // Update indices for x and z 9610 addl(tmp1, 2); 9611 addl(tmp4, 4); 9612 jmp(L_first_loop); 9613 9614 bind(L_first_loop_exit); 9615 } 9616 9617 9618 /** 9619 * Perform the following multiply add operation using BMI2 instructions 9620 * carry:sum = sum + op1*op2 + carry 9621 * op2 should be in rdx 9622 * op2 is preserved, all other registers are modified 9623 */ 9624 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9625 // assert op2 is rdx 9626 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9627 addq(sum, carry); 9628 adcq(tmp2, 0); 9629 addq(sum, op1); 9630 adcq(tmp2, 0); 9631 movq(carry, tmp2); 9632 } 9633 9634 /** 9635 * Perform the following multiply add operation: 9636 * carry:sum = sum + op1*op2 + carry 9637 * Preserves op1, op2 and modifies rest of registers 9638 */ 9639 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9640 // rdx:rax = op1 * op2 9641 movq(raxReg, op2); 9642 mulq(op1); 9643 9644 // rdx:rax = sum + carry + rdx:rax 9645 addq(sum, carry); 9646 adcq(rdxReg, 0); 9647 addq(sum, raxReg); 9648 adcq(rdxReg, 0); 9649 9650 // carry:sum = rdx:sum 9651 movq(carry, rdxReg); 9652 } 9653 9654 /** 9655 * Add 64 bit long carry into z[] with carry propogation. 9656 * Preserves z and carry register values and modifies rest of registers. 9657 * 9658 */ 9659 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9660 Label L_fourth_loop, L_fourth_loop_exit; 9661 9662 movl(tmp1, 1); 9663 subl(zlen, 2); 9664 addq(Address(z, zlen, Address::times_4, 0), carry); 9665 9666 bind(L_fourth_loop); 9667 jccb(Assembler::carryClear, L_fourth_loop_exit); 9668 subl(zlen, 2); 9669 jccb(Assembler::negative, L_fourth_loop_exit); 9670 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9671 jmp(L_fourth_loop); 9672 bind(L_fourth_loop_exit); 9673 } 9674 9675 /** 9676 * Shift z[] left by 1 bit. 9677 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9678 * 9679 */ 9680 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9681 9682 Label L_fifth_loop, L_fifth_loop_exit; 9683 9684 // Fifth loop 9685 // Perform primitiveLeftShift(z, zlen, 1) 9686 9687 const Register prev_carry = tmp1; 9688 const Register new_carry = tmp4; 9689 const Register value = tmp2; 9690 const Register zidx = tmp3; 9691 9692 // int zidx, carry; 9693 // long value; 9694 // carry = 0; 9695 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9696 // (carry:value) = (z[i] << 1) | carry ; 9697 // z[i] = value; 9698 // } 9699 9700 movl(zidx, zlen); 9701 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9702 9703 bind(L_fifth_loop); 9704 decl(zidx); // Use decl to preserve carry flag 9705 decl(zidx); 9706 jccb(Assembler::negative, L_fifth_loop_exit); 9707 9708 if (UseBMI2Instructions) { 9709 movq(value, Address(z, zidx, Address::times_4, 0)); 9710 rclq(value, 1); 9711 rorxq(value, value, 32); 9712 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9713 } 9714 else { 9715 // clear new_carry 9716 xorl(new_carry, new_carry); 9717 9718 // Shift z[i] by 1, or in previous carry and save new carry 9719 movq(value, Address(z, zidx, Address::times_4, 0)); 9720 shlq(value, 1); 9721 adcl(new_carry, 0); 9722 9723 orq(value, prev_carry); 9724 rorq(value, 0x20); 9725 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9726 9727 // Set previous carry = new carry 9728 movl(prev_carry, new_carry); 9729 } 9730 jmp(L_fifth_loop); 9731 9732 bind(L_fifth_loop_exit); 9733 } 9734 9735 9736 /** 9737 * Code for BigInteger::squareToLen() intrinsic 9738 * 9739 * rdi: x 9740 * rsi: len 9741 * r8: z 9742 * rcx: zlen 9743 * r12: tmp1 9744 * r13: tmp2 9745 * r14: tmp3 9746 * r15: tmp4 9747 * rbx: tmp5 9748 * 9749 */ 9750 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9751 9752 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9753 push(tmp1); 9754 push(tmp2); 9755 push(tmp3); 9756 push(tmp4); 9757 push(tmp5); 9758 9759 // First loop 9760 // Store the squares, right shifted one bit (i.e., divided by 2). 9761 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9762 9763 // Add in off-diagonal sums. 9764 // 9765 // Second, third (nested) and fourth loops. 9766 // zlen +=2; 9767 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9768 // carry = 0; 9769 // long op2 = x[xidx:xidx+1]; 9770 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9771 // k -= 2; 9772 // long op1 = x[j:j+1]; 9773 // long sum = z[k:k+1]; 9774 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9775 // z[k:k+1] = sum; 9776 // } 9777 // add_one_64(z, k, carry, tmp_regs); 9778 // } 9779 9780 const Register carry = tmp5; 9781 const Register sum = tmp3; 9782 const Register op1 = tmp4; 9783 Register op2 = tmp2; 9784 9785 push(zlen); 9786 push(len); 9787 addl(zlen,2); 9788 bind(L_second_loop); 9789 xorq(carry, carry); 9790 subl(zlen, 4); 9791 subl(len, 2); 9792 push(zlen); 9793 push(len); 9794 cmpl(len, 0); 9795 jccb(Assembler::lessEqual, L_second_loop_exit); 9796 9797 // Multiply an array by one 64 bit long. 9798 if (UseBMI2Instructions) { 9799 op2 = rdxReg; 9800 movq(op2, Address(x, len, Address::times_4, 0)); 9801 rorxq(op2, op2, 32); 9802 } 9803 else { 9804 movq(op2, Address(x, len, Address::times_4, 0)); 9805 rorq(op2, 32); 9806 } 9807 9808 bind(L_third_loop); 9809 decrementl(len); 9810 jccb(Assembler::negative, L_third_loop_exit); 9811 decrementl(len); 9812 jccb(Assembler::negative, L_last_x); 9813 9814 movq(op1, Address(x, len, Address::times_4, 0)); 9815 rorq(op1, 32); 9816 9817 bind(L_multiply); 9818 subl(zlen, 2); 9819 movq(sum, Address(z, zlen, Address::times_4, 0)); 9820 9821 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9822 if (UseBMI2Instructions) { 9823 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9824 } 9825 else { 9826 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9827 } 9828 9829 movq(Address(z, zlen, Address::times_4, 0), sum); 9830 9831 jmp(L_third_loop); 9832 bind(L_third_loop_exit); 9833 9834 // Fourth loop 9835 // Add 64 bit long carry into z with carry propogation. 9836 // Uses offsetted zlen. 9837 add_one_64(z, zlen, carry, tmp1); 9838 9839 pop(len); 9840 pop(zlen); 9841 jmp(L_second_loop); 9842 9843 // Next infrequent code is moved outside loops. 9844 bind(L_last_x); 9845 movl(op1, Address(x, 0)); 9846 jmp(L_multiply); 9847 9848 bind(L_second_loop_exit); 9849 pop(len); 9850 pop(zlen); 9851 pop(len); 9852 pop(zlen); 9853 9854 // Fifth loop 9855 // Shift z left 1 bit. 9856 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9857 9858 // z[zlen-1] |= x[len-1] & 1; 9859 movl(tmp3, Address(x, len, Address::times_4, -4)); 9860 andl(tmp3, 1); 9861 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9862 9863 pop(tmp5); 9864 pop(tmp4); 9865 pop(tmp3); 9866 pop(tmp2); 9867 pop(tmp1); 9868 } 9869 9870 /** 9871 * Helper function for mul_add() 9872 * Multiply the in[] by int k and add to out[] starting at offset offs using 9873 * 128 bit by 32 bit multiply and return the carry in tmp5. 9874 * Only quad int aligned length of in[] is operated on in this function. 9875 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9876 * This function preserves out, in and k registers. 9877 * len and offset point to the appropriate index in "in" & "out" correspondingly 9878 * tmp5 has the carry. 9879 * other registers are temporary and are modified. 9880 * 9881 */ 9882 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9883 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9884 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9885 9886 Label L_first_loop, L_first_loop_exit; 9887 9888 movl(tmp1, len); 9889 shrl(tmp1, 2); 9890 9891 bind(L_first_loop); 9892 subl(tmp1, 1); 9893 jccb(Assembler::negative, L_first_loop_exit); 9894 9895 subl(len, 4); 9896 subl(offset, 4); 9897 9898 Register op2 = tmp2; 9899 const Register sum = tmp3; 9900 const Register op1 = tmp4; 9901 const Register carry = tmp5; 9902 9903 if (UseBMI2Instructions) { 9904 op2 = rdxReg; 9905 } 9906 9907 movq(op1, Address(in, len, Address::times_4, 8)); 9908 rorq(op1, 32); 9909 movq(sum, Address(out, offset, Address::times_4, 8)); 9910 rorq(sum, 32); 9911 if (UseBMI2Instructions) { 9912 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9913 } 9914 else { 9915 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9916 } 9917 // Store back in big endian from little endian 9918 rorq(sum, 0x20); 9919 movq(Address(out, offset, Address::times_4, 8), sum); 9920 9921 movq(op1, Address(in, len, Address::times_4, 0)); 9922 rorq(op1, 32); 9923 movq(sum, Address(out, offset, Address::times_4, 0)); 9924 rorq(sum, 32); 9925 if (UseBMI2Instructions) { 9926 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9927 } 9928 else { 9929 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9930 } 9931 // Store back in big endian from little endian 9932 rorq(sum, 0x20); 9933 movq(Address(out, offset, Address::times_4, 0), sum); 9934 9935 jmp(L_first_loop); 9936 bind(L_first_loop_exit); 9937 } 9938 9939 /** 9940 * Code for BigInteger::mulAdd() intrinsic 9941 * 9942 * rdi: out 9943 * rsi: in 9944 * r11: offs (out.length - offset) 9945 * rcx: len 9946 * r8: k 9947 * r12: tmp1 9948 * r13: tmp2 9949 * r14: tmp3 9950 * r15: tmp4 9951 * rbx: tmp5 9952 * Multiply the in[] by word k and add to out[], return the carry in rax 9953 */ 9954 void MacroAssembler::mul_add(Register out, Register in, Register offs, 9955 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 9956 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9957 9958 Label L_carry, L_last_in, L_done; 9959 9960 // carry = 0; 9961 // for (int j=len-1; j >= 0; j--) { 9962 // long product = (in[j] & LONG_MASK) * kLong + 9963 // (out[offs] & LONG_MASK) + carry; 9964 // out[offs--] = (int)product; 9965 // carry = product >>> 32; 9966 // } 9967 // 9968 push(tmp1); 9969 push(tmp2); 9970 push(tmp3); 9971 push(tmp4); 9972 push(tmp5); 9973 9974 Register op2 = tmp2; 9975 const Register sum = tmp3; 9976 const Register op1 = tmp4; 9977 const Register carry = tmp5; 9978 9979 if (UseBMI2Instructions) { 9980 op2 = rdxReg; 9981 movl(op2, k); 9982 } 9983 else { 9984 movl(op2, k); 9985 } 9986 9987 xorq(carry, carry); 9988 9989 //First loop 9990 9991 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 9992 //The carry is in tmp5 9993 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 9994 9995 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 9996 decrementl(len); 9997 jccb(Assembler::negative, L_carry); 9998 decrementl(len); 9999 jccb(Assembler::negative, L_last_in); 10000 10001 movq(op1, Address(in, len, Address::times_4, 0)); 10002 rorq(op1, 32); 10003 10004 subl(offs, 2); 10005 movq(sum, Address(out, offs, Address::times_4, 0)); 10006 rorq(sum, 32); 10007 10008 if (UseBMI2Instructions) { 10009 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10010 } 10011 else { 10012 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10013 } 10014 10015 // Store back in big endian from little endian 10016 rorq(sum, 0x20); 10017 movq(Address(out, offs, Address::times_4, 0), sum); 10018 10019 testl(len, len); 10020 jccb(Assembler::zero, L_carry); 10021 10022 //Multiply the last in[] entry, if any 10023 bind(L_last_in); 10024 movl(op1, Address(in, 0)); 10025 movl(sum, Address(out, offs, Address::times_4, -4)); 10026 10027 movl(raxReg, k); 10028 mull(op1); //tmp4 * eax -> edx:eax 10029 addl(sum, carry); 10030 adcl(rdxReg, 0); 10031 addl(sum, raxReg); 10032 adcl(rdxReg, 0); 10033 movl(carry, rdxReg); 10034 10035 movl(Address(out, offs, Address::times_4, -4), sum); 10036 10037 bind(L_carry); 10038 //return tmp5/carry as carry in rax 10039 movl(rax, carry); 10040 10041 bind(L_done); 10042 pop(tmp5); 10043 pop(tmp4); 10044 pop(tmp3); 10045 pop(tmp2); 10046 pop(tmp1); 10047 } 10048 #endif 10049 10050 /** 10051 * Emits code to update CRC-32 with a byte value according to constants in table 10052 * 10053 * @param [in,out]crc Register containing the crc. 10054 * @param [in]val Register containing the byte to fold into the CRC. 10055 * @param [in]table Register containing the table of crc constants. 10056 * 10057 * uint32_t crc; 10058 * val = crc_table[(val ^ crc) & 0xFF]; 10059 * crc = val ^ (crc >> 8); 10060 * 10061 */ 10062 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10063 xorl(val, crc); 10064 andl(val, 0xFF); 10065 shrl(crc, 8); // unsigned shift 10066 xorl(crc, Address(table, val, Address::times_4, 0)); 10067 } 10068 10069 /** 10070 * Fold 128-bit data chunk 10071 */ 10072 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10073 if (UseAVX > 0) { 10074 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10075 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10076 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10077 pxor(xcrc, xtmp); 10078 } else { 10079 movdqa(xtmp, xcrc); 10080 pclmulhdq(xtmp, xK); // [123:64] 10081 pclmulldq(xcrc, xK); // [63:0] 10082 pxor(xcrc, xtmp); 10083 movdqu(xtmp, Address(buf, offset)); 10084 pxor(xcrc, xtmp); 10085 } 10086 } 10087 10088 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10089 if (UseAVX > 0) { 10090 vpclmulhdq(xtmp, xK, xcrc); 10091 vpclmulldq(xcrc, xK, xcrc); 10092 pxor(xcrc, xbuf); 10093 pxor(xcrc, xtmp); 10094 } else { 10095 movdqa(xtmp, xcrc); 10096 pclmulhdq(xtmp, xK); 10097 pclmulldq(xcrc, xK); 10098 pxor(xcrc, xbuf); 10099 pxor(xcrc, xtmp); 10100 } 10101 } 10102 10103 /** 10104 * 8-bit folds to compute 32-bit CRC 10105 * 10106 * uint64_t xcrc; 10107 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10108 */ 10109 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10110 movdl(tmp, xcrc); 10111 andl(tmp, 0xFF); 10112 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10113 psrldq(xcrc, 1); // unsigned shift one byte 10114 pxor(xcrc, xtmp); 10115 } 10116 10117 /** 10118 * uint32_t crc; 10119 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10120 */ 10121 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10122 movl(tmp, crc); 10123 andl(tmp, 0xFF); 10124 shrl(crc, 8); 10125 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10126 } 10127 10128 /** 10129 * @param crc register containing existing CRC (32-bit) 10130 * @param buf register pointing to input byte buffer (byte*) 10131 * @param len register containing number of bytes 10132 * @param table register that will contain address of CRC table 10133 * @param tmp scratch register 10134 */ 10135 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10136 assert_different_registers(crc, buf, len, table, tmp, rax); 10137 10138 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10139 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10140 10141 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10142 // context for the registers used, where all instructions below are using 128-bit mode 10143 // On EVEX without VL and BW, these instructions will all be AVX. 10144 if (VM_Version::supports_avx512vlbw()) { 10145 movl(tmp, 0xffff); 10146 kmovwl(k1, tmp); 10147 } 10148 10149 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10150 notl(crc); // ~crc 10151 cmpl(len, 16); 10152 jcc(Assembler::less, L_tail); 10153 10154 // Align buffer to 16 bytes 10155 movl(tmp, buf); 10156 andl(tmp, 0xF); 10157 jccb(Assembler::zero, L_aligned); 10158 subl(tmp, 16); 10159 addl(len, tmp); 10160 10161 align(4); 10162 BIND(L_align_loop); 10163 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10164 update_byte_crc32(crc, rax, table); 10165 increment(buf); 10166 incrementl(tmp); 10167 jccb(Assembler::less, L_align_loop); 10168 10169 BIND(L_aligned); 10170 movl(tmp, len); // save 10171 shrl(len, 4); 10172 jcc(Assembler::zero, L_tail_restore); 10173 10174 // Fold crc into first bytes of vector 10175 movdqa(xmm1, Address(buf, 0)); 10176 movdl(rax, xmm1); 10177 xorl(crc, rax); 10178 if (VM_Version::supports_sse4_1()) { 10179 pinsrd(xmm1, crc, 0); 10180 } else { 10181 pinsrw(xmm1, crc, 0); 10182 shrl(crc, 16); 10183 pinsrw(xmm1, crc, 1); 10184 } 10185 addptr(buf, 16); 10186 subl(len, 4); // len > 0 10187 jcc(Assembler::less, L_fold_tail); 10188 10189 movdqa(xmm2, Address(buf, 0)); 10190 movdqa(xmm3, Address(buf, 16)); 10191 movdqa(xmm4, Address(buf, 32)); 10192 addptr(buf, 48); 10193 subl(len, 3); 10194 jcc(Assembler::lessEqual, L_fold_512b); 10195 10196 // Fold total 512 bits of polynomial on each iteration, 10197 // 128 bits per each of 4 parallel streams. 10198 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10199 10200 align(32); 10201 BIND(L_fold_512b_loop); 10202 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10203 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10204 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10205 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10206 addptr(buf, 64); 10207 subl(len, 4); 10208 jcc(Assembler::greater, L_fold_512b_loop); 10209 10210 // Fold 512 bits to 128 bits. 10211 BIND(L_fold_512b); 10212 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10213 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10214 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10215 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10216 10217 // Fold the rest of 128 bits data chunks 10218 BIND(L_fold_tail); 10219 addl(len, 3); 10220 jccb(Assembler::lessEqual, L_fold_128b); 10221 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10222 10223 BIND(L_fold_tail_loop); 10224 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10225 addptr(buf, 16); 10226 decrementl(len); 10227 jccb(Assembler::greater, L_fold_tail_loop); 10228 10229 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10230 BIND(L_fold_128b); 10231 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10232 if (UseAVX > 0) { 10233 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10234 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10235 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10236 } else { 10237 movdqa(xmm2, xmm0); 10238 pclmulqdq(xmm2, xmm1, 0x1); 10239 movdqa(xmm3, xmm0); 10240 pand(xmm3, xmm2); 10241 pclmulqdq(xmm0, xmm3, 0x1); 10242 } 10243 psrldq(xmm1, 8); 10244 psrldq(xmm2, 4); 10245 pxor(xmm0, xmm1); 10246 pxor(xmm0, xmm2); 10247 10248 // 8 8-bit folds to compute 32-bit CRC. 10249 for (int j = 0; j < 4; j++) { 10250 fold_8bit_crc32(xmm0, table, xmm1, rax); 10251 } 10252 movdl(crc, xmm0); // mov 32 bits to general register 10253 for (int j = 0; j < 4; j++) { 10254 fold_8bit_crc32(crc, table, rax); 10255 } 10256 10257 BIND(L_tail_restore); 10258 movl(len, tmp); // restore 10259 BIND(L_tail); 10260 andl(len, 0xf); 10261 jccb(Assembler::zero, L_exit); 10262 10263 // Fold the rest of bytes 10264 align(4); 10265 BIND(L_tail_loop); 10266 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10267 update_byte_crc32(crc, rax, table); 10268 increment(buf); 10269 decrementl(len); 10270 jccb(Assembler::greater, L_tail_loop); 10271 10272 BIND(L_exit); 10273 notl(crc); // ~c 10274 } 10275 10276 #ifdef _LP64 10277 // S. Gueron / Information Processing Letters 112 (2012) 184 10278 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10279 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10280 // Output: the 64-bit carry-less product of B * CONST 10281 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10282 Register tmp1, Register tmp2, Register tmp3) { 10283 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10284 if (n > 0) { 10285 addq(tmp3, n * 256 * 8); 10286 } 10287 // Q1 = TABLEExt[n][B & 0xFF]; 10288 movl(tmp1, in); 10289 andl(tmp1, 0x000000FF); 10290 shll(tmp1, 3); 10291 addq(tmp1, tmp3); 10292 movq(tmp1, Address(tmp1, 0)); 10293 10294 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10295 movl(tmp2, in); 10296 shrl(tmp2, 8); 10297 andl(tmp2, 0x000000FF); 10298 shll(tmp2, 3); 10299 addq(tmp2, tmp3); 10300 movq(tmp2, Address(tmp2, 0)); 10301 10302 shlq(tmp2, 8); 10303 xorq(tmp1, tmp2); 10304 10305 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10306 movl(tmp2, in); 10307 shrl(tmp2, 16); 10308 andl(tmp2, 0x000000FF); 10309 shll(tmp2, 3); 10310 addq(tmp2, tmp3); 10311 movq(tmp2, Address(tmp2, 0)); 10312 10313 shlq(tmp2, 16); 10314 xorq(tmp1, tmp2); 10315 10316 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10317 shrl(in, 24); 10318 andl(in, 0x000000FF); 10319 shll(in, 3); 10320 addq(in, tmp3); 10321 movq(in, Address(in, 0)); 10322 10323 shlq(in, 24); 10324 xorq(in, tmp1); 10325 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10326 } 10327 10328 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10329 Register in_out, 10330 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10331 XMMRegister w_xtmp2, 10332 Register tmp1, 10333 Register n_tmp2, Register n_tmp3) { 10334 if (is_pclmulqdq_supported) { 10335 movdl(w_xtmp1, in_out); // modified blindly 10336 10337 movl(tmp1, const_or_pre_comp_const_index); 10338 movdl(w_xtmp2, tmp1); 10339 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10340 10341 movdq(in_out, w_xtmp1); 10342 } else { 10343 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10344 } 10345 } 10346 10347 // Recombination Alternative 2: No bit-reflections 10348 // T1 = (CRC_A * U1) << 1 10349 // T2 = (CRC_B * U2) << 1 10350 // C1 = T1 >> 32 10351 // C2 = T2 >> 32 10352 // T1 = T1 & 0xFFFFFFFF 10353 // T2 = T2 & 0xFFFFFFFF 10354 // T1 = CRC32(0, T1) 10355 // T2 = CRC32(0, T2) 10356 // C1 = C1 ^ T1 10357 // C2 = C2 ^ T2 10358 // CRC = C1 ^ C2 ^ CRC_C 10359 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10360 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10361 Register tmp1, Register tmp2, 10362 Register n_tmp3) { 10363 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10364 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10365 shlq(in_out, 1); 10366 movl(tmp1, in_out); 10367 shrq(in_out, 32); 10368 xorl(tmp2, tmp2); 10369 crc32(tmp2, tmp1, 4); 10370 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10371 shlq(in1, 1); 10372 movl(tmp1, in1); 10373 shrq(in1, 32); 10374 xorl(tmp2, tmp2); 10375 crc32(tmp2, tmp1, 4); 10376 xorl(in1, tmp2); 10377 xorl(in_out, in1); 10378 xorl(in_out, in2); 10379 } 10380 10381 // Set N to predefined value 10382 // Subtract from a lenght of a buffer 10383 // execute in a loop: 10384 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10385 // for i = 1 to N do 10386 // CRC_A = CRC32(CRC_A, A[i]) 10387 // CRC_B = CRC32(CRC_B, B[i]) 10388 // CRC_C = CRC32(CRC_C, C[i]) 10389 // end for 10390 // Recombine 10391 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10392 Register in_out1, Register in_out2, Register in_out3, 10393 Register tmp1, Register tmp2, Register tmp3, 10394 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10395 Register tmp4, Register tmp5, 10396 Register n_tmp6) { 10397 Label L_processPartitions; 10398 Label L_processPartition; 10399 Label L_exit; 10400 10401 bind(L_processPartitions); 10402 cmpl(in_out1, 3 * size); 10403 jcc(Assembler::less, L_exit); 10404 xorl(tmp1, tmp1); 10405 xorl(tmp2, tmp2); 10406 movq(tmp3, in_out2); 10407 addq(tmp3, size); 10408 10409 bind(L_processPartition); 10410 crc32(in_out3, Address(in_out2, 0), 8); 10411 crc32(tmp1, Address(in_out2, size), 8); 10412 crc32(tmp2, Address(in_out2, size * 2), 8); 10413 addq(in_out2, 8); 10414 cmpq(in_out2, tmp3); 10415 jcc(Assembler::less, L_processPartition); 10416 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10417 w_xtmp1, w_xtmp2, w_xtmp3, 10418 tmp4, tmp5, 10419 n_tmp6); 10420 addq(in_out2, 2 * size); 10421 subl(in_out1, 3 * size); 10422 jmp(L_processPartitions); 10423 10424 bind(L_exit); 10425 } 10426 #else 10427 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10428 Register tmp1, Register tmp2, Register tmp3, 10429 XMMRegister xtmp1, XMMRegister xtmp2) { 10430 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10431 if (n > 0) { 10432 addl(tmp3, n * 256 * 8); 10433 } 10434 // Q1 = TABLEExt[n][B & 0xFF]; 10435 movl(tmp1, in_out); 10436 andl(tmp1, 0x000000FF); 10437 shll(tmp1, 3); 10438 addl(tmp1, tmp3); 10439 movq(xtmp1, Address(tmp1, 0)); 10440 10441 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10442 movl(tmp2, in_out); 10443 shrl(tmp2, 8); 10444 andl(tmp2, 0x000000FF); 10445 shll(tmp2, 3); 10446 addl(tmp2, tmp3); 10447 movq(xtmp2, Address(tmp2, 0)); 10448 10449 psllq(xtmp2, 8); 10450 pxor(xtmp1, xtmp2); 10451 10452 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10453 movl(tmp2, in_out); 10454 shrl(tmp2, 16); 10455 andl(tmp2, 0x000000FF); 10456 shll(tmp2, 3); 10457 addl(tmp2, tmp3); 10458 movq(xtmp2, Address(tmp2, 0)); 10459 10460 psllq(xtmp2, 16); 10461 pxor(xtmp1, xtmp2); 10462 10463 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10464 shrl(in_out, 24); 10465 andl(in_out, 0x000000FF); 10466 shll(in_out, 3); 10467 addl(in_out, tmp3); 10468 movq(xtmp2, Address(in_out, 0)); 10469 10470 psllq(xtmp2, 24); 10471 pxor(xtmp1, xtmp2); // Result in CXMM 10472 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10473 } 10474 10475 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10476 Register in_out, 10477 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10478 XMMRegister w_xtmp2, 10479 Register tmp1, 10480 Register n_tmp2, Register n_tmp3) { 10481 if (is_pclmulqdq_supported) { 10482 movdl(w_xtmp1, in_out); 10483 10484 movl(tmp1, const_or_pre_comp_const_index); 10485 movdl(w_xtmp2, tmp1); 10486 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10487 // Keep result in XMM since GPR is 32 bit in length 10488 } else { 10489 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10490 } 10491 } 10492 10493 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10494 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10495 Register tmp1, Register tmp2, 10496 Register n_tmp3) { 10497 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10498 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10499 10500 psllq(w_xtmp1, 1); 10501 movdl(tmp1, w_xtmp1); 10502 psrlq(w_xtmp1, 32); 10503 movdl(in_out, w_xtmp1); 10504 10505 xorl(tmp2, tmp2); 10506 crc32(tmp2, tmp1, 4); 10507 xorl(in_out, tmp2); 10508 10509 psllq(w_xtmp2, 1); 10510 movdl(tmp1, w_xtmp2); 10511 psrlq(w_xtmp2, 32); 10512 movdl(in1, w_xtmp2); 10513 10514 xorl(tmp2, tmp2); 10515 crc32(tmp2, tmp1, 4); 10516 xorl(in1, tmp2); 10517 xorl(in_out, in1); 10518 xorl(in_out, in2); 10519 } 10520 10521 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10522 Register in_out1, Register in_out2, Register in_out3, 10523 Register tmp1, Register tmp2, Register tmp3, 10524 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10525 Register tmp4, Register tmp5, 10526 Register n_tmp6) { 10527 Label L_processPartitions; 10528 Label L_processPartition; 10529 Label L_exit; 10530 10531 bind(L_processPartitions); 10532 cmpl(in_out1, 3 * size); 10533 jcc(Assembler::less, L_exit); 10534 xorl(tmp1, tmp1); 10535 xorl(tmp2, tmp2); 10536 movl(tmp3, in_out2); 10537 addl(tmp3, size); 10538 10539 bind(L_processPartition); 10540 crc32(in_out3, Address(in_out2, 0), 4); 10541 crc32(tmp1, Address(in_out2, size), 4); 10542 crc32(tmp2, Address(in_out2, size*2), 4); 10543 crc32(in_out3, Address(in_out2, 0+4), 4); 10544 crc32(tmp1, Address(in_out2, size+4), 4); 10545 crc32(tmp2, Address(in_out2, size*2+4), 4); 10546 addl(in_out2, 8); 10547 cmpl(in_out2, tmp3); 10548 jcc(Assembler::less, L_processPartition); 10549 10550 push(tmp3); 10551 push(in_out1); 10552 push(in_out2); 10553 tmp4 = tmp3; 10554 tmp5 = in_out1; 10555 n_tmp6 = in_out2; 10556 10557 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10558 w_xtmp1, w_xtmp2, w_xtmp3, 10559 tmp4, tmp5, 10560 n_tmp6); 10561 10562 pop(in_out2); 10563 pop(in_out1); 10564 pop(tmp3); 10565 10566 addl(in_out2, 2 * size); 10567 subl(in_out1, 3 * size); 10568 jmp(L_processPartitions); 10569 10570 bind(L_exit); 10571 } 10572 #endif //LP64 10573 10574 #ifdef _LP64 10575 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10576 // Input: A buffer I of L bytes. 10577 // Output: the CRC32C value of the buffer. 10578 // Notations: 10579 // Write L = 24N + r, with N = floor (L/24). 10580 // r = L mod 24 (0 <= r < 24). 10581 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10582 // N quadwords, and R consists of r bytes. 10583 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10584 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10585 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10586 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10587 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10588 Register tmp1, Register tmp2, Register tmp3, 10589 Register tmp4, Register tmp5, Register tmp6, 10590 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10591 bool is_pclmulqdq_supported) { 10592 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10593 Label L_wordByWord; 10594 Label L_byteByByteProlog; 10595 Label L_byteByByte; 10596 Label L_exit; 10597 10598 if (is_pclmulqdq_supported ) { 10599 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10600 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10601 10602 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10603 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10604 10605 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10606 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10607 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10608 } else { 10609 const_or_pre_comp_const_index[0] = 1; 10610 const_or_pre_comp_const_index[1] = 0; 10611 10612 const_or_pre_comp_const_index[2] = 3; 10613 const_or_pre_comp_const_index[3] = 2; 10614 10615 const_or_pre_comp_const_index[4] = 5; 10616 const_or_pre_comp_const_index[5] = 4; 10617 } 10618 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10619 in2, in1, in_out, 10620 tmp1, tmp2, tmp3, 10621 w_xtmp1, w_xtmp2, w_xtmp3, 10622 tmp4, tmp5, 10623 tmp6); 10624 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10625 in2, in1, in_out, 10626 tmp1, tmp2, tmp3, 10627 w_xtmp1, w_xtmp2, w_xtmp3, 10628 tmp4, tmp5, 10629 tmp6); 10630 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10631 in2, in1, in_out, 10632 tmp1, tmp2, tmp3, 10633 w_xtmp1, w_xtmp2, w_xtmp3, 10634 tmp4, tmp5, 10635 tmp6); 10636 movl(tmp1, in2); 10637 andl(tmp1, 0x00000007); 10638 negl(tmp1); 10639 addl(tmp1, in2); 10640 addq(tmp1, in1); 10641 10642 BIND(L_wordByWord); 10643 cmpq(in1, tmp1); 10644 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10645 crc32(in_out, Address(in1, 0), 4); 10646 addq(in1, 4); 10647 jmp(L_wordByWord); 10648 10649 BIND(L_byteByByteProlog); 10650 andl(in2, 0x00000007); 10651 movl(tmp2, 1); 10652 10653 BIND(L_byteByByte); 10654 cmpl(tmp2, in2); 10655 jccb(Assembler::greater, L_exit); 10656 crc32(in_out, Address(in1, 0), 1); 10657 incq(in1); 10658 incl(tmp2); 10659 jmp(L_byteByByte); 10660 10661 BIND(L_exit); 10662 } 10663 #else 10664 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10665 Register tmp1, Register tmp2, Register tmp3, 10666 Register tmp4, Register tmp5, Register tmp6, 10667 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10668 bool is_pclmulqdq_supported) { 10669 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10670 Label L_wordByWord; 10671 Label L_byteByByteProlog; 10672 Label L_byteByByte; 10673 Label L_exit; 10674 10675 if (is_pclmulqdq_supported) { 10676 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10677 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10678 10679 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10680 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10681 10682 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10683 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10684 } else { 10685 const_or_pre_comp_const_index[0] = 1; 10686 const_or_pre_comp_const_index[1] = 0; 10687 10688 const_or_pre_comp_const_index[2] = 3; 10689 const_or_pre_comp_const_index[3] = 2; 10690 10691 const_or_pre_comp_const_index[4] = 5; 10692 const_or_pre_comp_const_index[5] = 4; 10693 } 10694 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10695 in2, in1, in_out, 10696 tmp1, tmp2, tmp3, 10697 w_xtmp1, w_xtmp2, w_xtmp3, 10698 tmp4, tmp5, 10699 tmp6); 10700 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10701 in2, in1, in_out, 10702 tmp1, tmp2, tmp3, 10703 w_xtmp1, w_xtmp2, w_xtmp3, 10704 tmp4, tmp5, 10705 tmp6); 10706 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10707 in2, in1, in_out, 10708 tmp1, tmp2, tmp3, 10709 w_xtmp1, w_xtmp2, w_xtmp3, 10710 tmp4, tmp5, 10711 tmp6); 10712 movl(tmp1, in2); 10713 andl(tmp1, 0x00000007); 10714 negl(tmp1); 10715 addl(tmp1, in2); 10716 addl(tmp1, in1); 10717 10718 BIND(L_wordByWord); 10719 cmpl(in1, tmp1); 10720 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10721 crc32(in_out, Address(in1,0), 4); 10722 addl(in1, 4); 10723 jmp(L_wordByWord); 10724 10725 BIND(L_byteByByteProlog); 10726 andl(in2, 0x00000007); 10727 movl(tmp2, 1); 10728 10729 BIND(L_byteByByte); 10730 cmpl(tmp2, in2); 10731 jccb(Assembler::greater, L_exit); 10732 movb(tmp1, Address(in1, 0)); 10733 crc32(in_out, tmp1, 1); 10734 incl(in1); 10735 incl(tmp2); 10736 jmp(L_byteByByte); 10737 10738 BIND(L_exit); 10739 } 10740 #endif // LP64 10741 #undef BIND 10742 #undef BLOCK_COMMENT 10743 10744 // Compress char[] array to byte[]. 10745 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10746 // @HotSpotIntrinsicCandidate 10747 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10748 // for (int i = 0; i < len; i++) { 10749 // int c = src[srcOff++]; 10750 // if (c >>> 8 != 0) { 10751 // return 0; 10752 // } 10753 // dst[dstOff++] = (byte)c; 10754 // } 10755 // return len; 10756 // } 10757 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10758 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10759 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10760 Register tmp5, Register result) { 10761 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10762 10763 // rsi: src 10764 // rdi: dst 10765 // rdx: len 10766 // rcx: tmp5 10767 // rax: result 10768 10769 // rsi holds start addr of source char[] to be compressed 10770 // rdi holds start addr of destination byte[] 10771 // rdx holds length 10772 10773 assert(len != result, ""); 10774 10775 // save length for return 10776 push(len); 10777 10778 if ((UseAVX > 2) && // AVX512 10779 VM_Version::supports_avx512vlbw() && 10780 VM_Version::supports_bmi2()) { 10781 10782 set_vector_masking(); // opening of the stub context for programming mask registers 10783 10784 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero; 10785 10786 // alignement 10787 Label post_alignement; 10788 10789 // if length of the string is less than 16, handle it in an old fashioned 10790 // way 10791 testl(len, -32); 10792 jcc(Assembler::zero, below_threshold); 10793 10794 // First check whether a character is compressable ( <= 0xFF). 10795 // Create mask to test for Unicode chars inside zmm vector 10796 movl(result, 0x00FF); 10797 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10798 10799 // Save k1 10800 kmovql(k3, k1); 10801 10802 testl(len, -64); 10803 jcc(Assembler::zero, post_alignement); 10804 10805 movl(tmp5, dst); 10806 andl(tmp5, (32 - 1)); 10807 negl(tmp5); 10808 andl(tmp5, (32 - 1)); 10809 10810 // bail out when there is nothing to be done 10811 testl(tmp5, 0xFFFFFFFF); 10812 jcc(Assembler::zero, post_alignement); 10813 10814 // ~(~0 << len), where len is the # of remaining elements to process 10815 movl(result, 0xFFFFFFFF); 10816 shlxl(result, result, tmp5); 10817 notl(result); 10818 kmovdl(k1, result); 10819 10820 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10821 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10822 ktestd(k2, k1); 10823 jcc(Assembler::carryClear, restore_k1_return_zero); 10824 10825 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10826 10827 addptr(src, tmp5); 10828 addptr(src, tmp5); 10829 addptr(dst, tmp5); 10830 subl(len, tmp5); 10831 10832 bind(post_alignement); 10833 // end of alignement 10834 10835 movl(tmp5, len); 10836 andl(tmp5, (32 - 1)); // tail count (in chars) 10837 andl(len, ~(32 - 1)); // vector count (in chars) 10838 jcc(Assembler::zero, copy_loop_tail); 10839 10840 lea(src, Address(src, len, Address::times_2)); 10841 lea(dst, Address(dst, len, Address::times_1)); 10842 negptr(len); 10843 10844 bind(copy_32_loop); 10845 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10846 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10847 kortestdl(k2, k2); 10848 jcc(Assembler::carryClear, restore_k1_return_zero); 10849 10850 // All elements in current processed chunk are valid candidates for 10851 // compression. Write a truncated byte elements to the memory. 10852 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10853 addptr(len, 32); 10854 jcc(Assembler::notZero, copy_32_loop); 10855 10856 bind(copy_loop_tail); 10857 // bail out when there is nothing to be done 10858 testl(tmp5, 0xFFFFFFFF); 10859 // Restore k1 10860 kmovql(k1, k3); 10861 jcc(Assembler::zero, return_length); 10862 10863 movl(len, tmp5); 10864 10865 // ~(~0 << len), where len is the # of remaining elements to process 10866 movl(result, 0xFFFFFFFF); 10867 shlxl(result, result, len); 10868 notl(result); 10869 10870 kmovdl(k1, result); 10871 10872 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10873 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10874 ktestd(k2, k1); 10875 jcc(Assembler::carryClear, restore_k1_return_zero); 10876 10877 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10878 // Restore k1 10879 kmovql(k1, k3); 10880 jmp(return_length); 10881 10882 bind(restore_k1_return_zero); 10883 // Restore k1 10884 kmovql(k1, k3); 10885 jmp(return_zero); 10886 10887 clear_vector_masking(); // closing of the stub context for programming mask registers 10888 } 10889 if (UseSSE42Intrinsics) { 10890 Label copy_32_loop, copy_16, copy_tail; 10891 10892 bind(below_threshold); 10893 10894 movl(result, len); 10895 10896 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10897 10898 // vectored compression 10899 andl(len, 0xfffffff0); // vector count (in chars) 10900 andl(result, 0x0000000f); // tail count (in chars) 10901 testl(len, len); 10902 jccb(Assembler::zero, copy_16); 10903 10904 // compress 16 chars per iter 10905 movdl(tmp1Reg, tmp5); 10906 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10907 pxor(tmp4Reg, tmp4Reg); 10908 10909 lea(src, Address(src, len, Address::times_2)); 10910 lea(dst, Address(dst, len, Address::times_1)); 10911 negptr(len); 10912 10913 bind(copy_32_loop); 10914 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 10915 por(tmp4Reg, tmp2Reg); 10916 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 10917 por(tmp4Reg, tmp3Reg); 10918 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 10919 jcc(Assembler::notZero, return_zero); 10920 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 10921 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 10922 addptr(len, 16); 10923 jcc(Assembler::notZero, copy_32_loop); 10924 10925 // compress next vector of 8 chars (if any) 10926 bind(copy_16); 10927 movl(len, result); 10928 andl(len, 0xfffffff8); // vector count (in chars) 10929 andl(result, 0x00000007); // tail count (in chars) 10930 testl(len, len); 10931 jccb(Assembler::zero, copy_tail); 10932 10933 movdl(tmp1Reg, tmp5); 10934 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10935 pxor(tmp3Reg, tmp3Reg); 10936 10937 movdqu(tmp2Reg, Address(src, 0)); 10938 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 10939 jccb(Assembler::notZero, return_zero); 10940 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 10941 movq(Address(dst, 0), tmp2Reg); 10942 addptr(src, 16); 10943 addptr(dst, 8); 10944 10945 bind(copy_tail); 10946 movl(len, result); 10947 } 10948 // compress 1 char per iter 10949 testl(len, len); 10950 jccb(Assembler::zero, return_length); 10951 lea(src, Address(src, len, Address::times_2)); 10952 lea(dst, Address(dst, len, Address::times_1)); 10953 negptr(len); 10954 10955 bind(copy_chars_loop); 10956 load_unsigned_short(result, Address(src, len, Address::times_2)); 10957 testl(result, 0xff00); // check if Unicode char 10958 jccb(Assembler::notZero, return_zero); 10959 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 10960 increment(len); 10961 jcc(Assembler::notZero, copy_chars_loop); 10962 10963 // if compression succeeded, return length 10964 bind(return_length); 10965 pop(result); 10966 jmpb(done); 10967 10968 // if compression failed, return 0 10969 bind(return_zero); 10970 xorl(result, result); 10971 addptr(rsp, wordSize); 10972 10973 bind(done); 10974 } 10975 10976 // Inflate byte[] array to char[]. 10977 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 10978 // @HotSpotIntrinsicCandidate 10979 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 10980 // for (int i = 0; i < len; i++) { 10981 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 10982 // } 10983 // } 10984 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 10985 XMMRegister tmp1, Register tmp2) { 10986 Label copy_chars_loop, done, below_threshold; 10987 // rsi: src 10988 // rdi: dst 10989 // rdx: len 10990 // rcx: tmp2 10991 10992 // rsi holds start addr of source byte[] to be inflated 10993 // rdi holds start addr of destination char[] 10994 // rdx holds length 10995 assert_different_registers(src, dst, len, tmp2); 10996 10997 if ((UseAVX > 2) && // AVX512 10998 VM_Version::supports_avx512vlbw() && 10999 VM_Version::supports_bmi2()) { 11000 11001 set_vector_masking(); // opening of the stub context for programming mask registers 11002 11003 Label copy_32_loop, copy_tail; 11004 Register tmp3_aliased = len; 11005 11006 // if length of the string is less than 16, handle it in an old fashioned 11007 // way 11008 testl(len, -16); 11009 jcc(Assembler::zero, below_threshold); 11010 11011 // In order to use only one arithmetic operation for the main loop we use 11012 // this pre-calculation 11013 movl(tmp2, len); 11014 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11015 andl(len, -32); // vector count 11016 jccb(Assembler::zero, copy_tail); 11017 11018 lea(src, Address(src, len, Address::times_1)); 11019 lea(dst, Address(dst, len, Address::times_2)); 11020 negptr(len); 11021 11022 11023 // inflate 32 chars per iter 11024 bind(copy_32_loop); 11025 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11026 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11027 addptr(len, 32); 11028 jcc(Assembler::notZero, copy_32_loop); 11029 11030 bind(copy_tail); 11031 // bail out when there is nothing to be done 11032 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11033 jcc(Assembler::zero, done); 11034 11035 // Save k1 11036 kmovql(k2, k1); 11037 11038 // ~(~0 << length), where length is the # of remaining elements to process 11039 movl(tmp3_aliased, -1); 11040 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11041 notl(tmp3_aliased); 11042 kmovdl(k1, tmp3_aliased); 11043 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11044 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11045 11046 // Restore k1 11047 kmovql(k1, k2); 11048 jmp(done); 11049 11050 clear_vector_masking(); // closing of the stub context for programming mask registers 11051 } 11052 if (UseSSE42Intrinsics) { 11053 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11054 11055 movl(tmp2, len); 11056 11057 if (UseAVX > 1) { 11058 andl(tmp2, (16 - 1)); 11059 andl(len, -16); 11060 jccb(Assembler::zero, copy_new_tail); 11061 } else { 11062 andl(tmp2, 0x00000007); // tail count (in chars) 11063 andl(len, 0xfffffff8); // vector count (in chars) 11064 jccb(Assembler::zero, copy_tail); 11065 } 11066 11067 // vectored inflation 11068 lea(src, Address(src, len, Address::times_1)); 11069 lea(dst, Address(dst, len, Address::times_2)); 11070 negptr(len); 11071 11072 if (UseAVX > 1) { 11073 bind(copy_16_loop); 11074 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11075 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11076 addptr(len, 16); 11077 jcc(Assembler::notZero, copy_16_loop); 11078 11079 bind(below_threshold); 11080 bind(copy_new_tail); 11081 if ((UseAVX > 2) && 11082 VM_Version::supports_avx512vlbw() && 11083 VM_Version::supports_bmi2()) { 11084 movl(tmp2, len); 11085 } else { 11086 movl(len, tmp2); 11087 } 11088 andl(tmp2, 0x00000007); 11089 andl(len, 0xFFFFFFF8); 11090 jccb(Assembler::zero, copy_tail); 11091 11092 pmovzxbw(tmp1, Address(src, 0)); 11093 movdqu(Address(dst, 0), tmp1); 11094 addptr(src, 8); 11095 addptr(dst, 2 * 8); 11096 11097 jmp(copy_tail, true); 11098 } 11099 11100 // inflate 8 chars per iter 11101 bind(copy_8_loop); 11102 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11103 movdqu(Address(dst, len, Address::times_2), tmp1); 11104 addptr(len, 8); 11105 jcc(Assembler::notZero, copy_8_loop); 11106 11107 bind(copy_tail); 11108 movl(len, tmp2); 11109 11110 cmpl(len, 4); 11111 jccb(Assembler::less, copy_bytes); 11112 11113 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11114 pmovzxbw(tmp1, tmp1); 11115 movq(Address(dst, 0), tmp1); 11116 subptr(len, 4); 11117 addptr(src, 4); 11118 addptr(dst, 8); 11119 11120 bind(copy_bytes); 11121 } 11122 testl(len, len); 11123 jccb(Assembler::zero, done); 11124 lea(src, Address(src, len, Address::times_1)); 11125 lea(dst, Address(dst, len, Address::times_2)); 11126 negptr(len); 11127 11128 // inflate 1 char per iter 11129 bind(copy_chars_loop); 11130 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11131 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11132 increment(len); 11133 jcc(Assembler::notZero, copy_chars_loop); 11134 11135 bind(done); 11136 } 11137 11138 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11139 switch (cond) { 11140 // Note some conditions are synonyms for others 11141 case Assembler::zero: return Assembler::notZero; 11142 case Assembler::notZero: return Assembler::zero; 11143 case Assembler::less: return Assembler::greaterEqual; 11144 case Assembler::lessEqual: return Assembler::greater; 11145 case Assembler::greater: return Assembler::lessEqual; 11146 case Assembler::greaterEqual: return Assembler::less; 11147 case Assembler::below: return Assembler::aboveEqual; 11148 case Assembler::belowEqual: return Assembler::above; 11149 case Assembler::above: return Assembler::belowEqual; 11150 case Assembler::aboveEqual: return Assembler::below; 11151 case Assembler::overflow: return Assembler::noOverflow; 11152 case Assembler::noOverflow: return Assembler::overflow; 11153 case Assembler::negative: return Assembler::positive; 11154 case Assembler::positive: return Assembler::negative; 11155 case Assembler::parity: return Assembler::noParity; 11156 case Assembler::noParity: return Assembler::parity; 11157 } 11158 ShouldNotReachHere(); return Assembler::overflow; 11159 } 11160 11161 SkipIfEqual::SkipIfEqual( 11162 MacroAssembler* masm, const bool* flag_addr, bool value) { 11163 _masm = masm; 11164 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11165 _masm->jcc(Assembler::equal, _label); 11166 } 11167 11168 SkipIfEqual::~SkipIfEqual() { 11169 _masm->bind(_label); 11170 } 11171 11172 // 32-bit Windows has its own fast-path implementation 11173 // of get_thread 11174 #if !defined(WIN32) || defined(_LP64) 11175 11176 // This is simply a call to Thread::current() 11177 void MacroAssembler::get_thread(Register thread) { 11178 if (thread != rax) { 11179 push(rax); 11180 } 11181 LP64_ONLY(push(rdi);) 11182 LP64_ONLY(push(rsi);) 11183 push(rdx); 11184 push(rcx); 11185 #ifdef _LP64 11186 push(r8); 11187 push(r9); 11188 push(r10); 11189 push(r11); 11190 #endif 11191 11192 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11193 11194 #ifdef _LP64 11195 pop(r11); 11196 pop(r10); 11197 pop(r9); 11198 pop(r8); 11199 #endif 11200 pop(rcx); 11201 pop(rdx); 11202 LP64_ONLY(pop(rsi);) 11203 LP64_ONLY(pop(rdi);) 11204 if (thread != rax) { 11205 mov(thread, rax); 11206 pop(rax); 11207 } 11208 } 11209 11210 #endif