1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "vm_version_x86.hpp"
34
35
36 int VM_Version::_cpu;
37 int VM_Version::_model;
38 int VM_Version::_stepping;
39 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
40
41 // Address of instruction which causes SEGV
42 address VM_Version::_cpuinfo_segv_addr = 0;
43 // Address of instruction after the one which causes SEGV
44 address VM_Version::_cpuinfo_cont_addr = 0;
45
46 static BufferBlob* stub_blob;
47 static const int stub_size = 1000;
48
49 extern "C" {
50 typedef void (*get_cpu_info_stub_t)(void*);
51 }
52 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
53
54
55 class VM_Version_StubGenerator: public StubCodeGenerator {
56 public:
57
58 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
59
60 address generate_get_cpu_info() {
61 // Flags to test CPU type.
62 const uint32_t HS_EFL_AC = 0x40000;
63 const uint32_t HS_EFL_ID = 0x200000;
64 // Values for when we don't have a CPUID instruction.
65 const int CPU_FAMILY_SHIFT = 8;
66 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
67 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
68 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
69
70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
73
74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
75 # define __ _masm->
76
77 address start = __ pc();
78
79 //
80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
81 //
82 // LP64: rcx and rdx are first and second argument registers on windows
83
84 __ push(rbp);
85 #ifdef _LP64
86 __ mov(rbp, c_rarg0); // cpuid_info address
87 #else
88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
89 #endif
90 __ push(rbx);
91 __ push(rsi);
92 __ pushf(); // preserve rbx, and flags
93 __ pop(rax);
94 __ push(rax);
95 __ mov(rcx, rax);
96 //
97 // if we are unable to change the AC flag, we have a 386
98 //
99 __ xorl(rax, HS_EFL_AC);
100 __ push(rax);
101 __ popf();
102 __ pushf();
103 __ pop(rax);
104 __ cmpptr(rax, rcx);
105 __ jccb(Assembler::notEqual, detect_486);
106
107 __ movl(rax, CPU_FAMILY_386);
108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
109 __ jmp(done);
110
111 //
112 // If we are unable to change the ID flag, we have a 486 which does
113 // not support the "cpuid" instruction.
114 //
115 __ bind(detect_486);
116 __ mov(rax, rcx);
117 __ xorl(rax, HS_EFL_ID);
118 __ push(rax);
119 __ popf();
120 __ pushf();
121 __ pop(rax);
122 __ cmpptr(rcx, rax);
123 __ jccb(Assembler::notEqual, detect_586);
124
125 __ bind(cpu486);
126 __ movl(rax, CPU_FAMILY_486);
127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
128 __ jmp(done);
129
130 //
131 // At this point, we have a chip which supports the "cpuid" instruction
132 //
133 __ bind(detect_586);
134 __ xorl(rax, rax);
135 __ cpuid();
136 __ orl(rax, rax);
137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
138 // value of at least 1, we give up and
139 // assume a 486
140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
141 __ movl(Address(rsi, 0), rax);
142 __ movl(Address(rsi, 4), rbx);
143 __ movl(Address(rsi, 8), rcx);
144 __ movl(Address(rsi,12), rdx);
145
146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
147 __ jccb(Assembler::belowEqual, std_cpuid4);
148
149 //
150 // cpuid(0xB) Processor Topology
151 //
152 __ movl(rax, 0xb);
153 __ xorl(rcx, rcx); // Threads level
154 __ cpuid();
155
156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
157 __ movl(Address(rsi, 0), rax);
158 __ movl(Address(rsi, 4), rbx);
159 __ movl(Address(rsi, 8), rcx);
160 __ movl(Address(rsi,12), rdx);
161
162 __ movl(rax, 0xb);
163 __ movl(rcx, 1); // Cores level
164 __ cpuid();
165 __ push(rax);
166 __ andl(rax, 0x1f); // Determine if valid topology level
167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
168 __ andl(rax, 0xffff);
169 __ pop(rax);
170 __ jccb(Assembler::equal, std_cpuid4);
171
172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
173 __ movl(Address(rsi, 0), rax);
174 __ movl(Address(rsi, 4), rbx);
175 __ movl(Address(rsi, 8), rcx);
176 __ movl(Address(rsi,12), rdx);
177
178 __ movl(rax, 0xb);
179 __ movl(rcx, 2); // Packages level
180 __ cpuid();
181 __ push(rax);
182 __ andl(rax, 0x1f); // Determine if valid topology level
183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
184 __ andl(rax, 0xffff);
185 __ pop(rax);
186 __ jccb(Assembler::equal, std_cpuid4);
187
188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
189 __ movl(Address(rsi, 0), rax);
190 __ movl(Address(rsi, 4), rbx);
191 __ movl(Address(rsi, 8), rcx);
192 __ movl(Address(rsi,12), rdx);
193
194 //
195 // cpuid(0x4) Deterministic cache params
196 //
197 __ bind(std_cpuid4);
198 __ movl(rax, 4);
199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
200 __ jccb(Assembler::greater, std_cpuid1);
201
202 __ xorl(rcx, rcx); // L1 cache
203 __ cpuid();
204 __ push(rax);
205 __ andl(rax, 0x1f); // Determine if valid cache parameters used
206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
207 __ pop(rax);
208 __ jccb(Assembler::equal, std_cpuid1);
209
210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
211 __ movl(Address(rsi, 0), rax);
212 __ movl(Address(rsi, 4), rbx);
213 __ movl(Address(rsi, 8), rcx);
214 __ movl(Address(rsi,12), rdx);
215
216 //
217 // Standard cpuid(0x1)
218 //
219 __ bind(std_cpuid1);
220 __ movl(rax, 1);
221 __ cpuid();
222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
223 __ movl(Address(rsi, 0), rax);
224 __ movl(Address(rsi, 4), rbx);
225 __ movl(Address(rsi, 8), rcx);
226 __ movl(Address(rsi,12), rdx);
227
228 //
229 // Check if OS has enabled XGETBV instruction to access XCR0
230 // (OSXSAVE feature flag) and CPU supports AVX
231 //
232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
233 __ cmpl(rcx, 0x18000000);
234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
235
236 //
237 // XCR0, XFEATURE_ENABLED_MASK register
238 //
239 __ xorl(rcx, rcx); // zero for XCR0 register
240 __ xgetbv();
241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
242 __ movl(Address(rsi, 0), rax);
243 __ movl(Address(rsi, 4), rdx);
244
245 //
246 // cpuid(0x7) Structured Extended Features
247 //
248 __ bind(sef_cpuid);
249 __ movl(rax, 7);
250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
251 __ jccb(Assembler::greater, ext_cpuid);
252
253 __ xorl(rcx, rcx);
254 __ cpuid();
255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
256 __ movl(Address(rsi, 0), rax);
257 __ movl(Address(rsi, 4), rbx);
258
259 //
260 // Extended cpuid(0x80000000)
261 //
262 __ bind(ext_cpuid);
263 __ movl(rax, 0x80000000);
264 __ cpuid();
265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
266 __ jcc(Assembler::belowEqual, done);
267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
268 __ jccb(Assembler::belowEqual, ext_cpuid1);
269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
270 __ jccb(Assembler::belowEqual, ext_cpuid5);
271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid7);
273 //
274 // Extended cpuid(0x80000008)
275 //
276 __ movl(rax, 0x80000008);
277 __ cpuid();
278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
279 __ movl(Address(rsi, 0), rax);
280 __ movl(Address(rsi, 4), rbx);
281 __ movl(Address(rsi, 8), rcx);
282 __ movl(Address(rsi,12), rdx);
283
284 //
285 // Extended cpuid(0x80000007)
286 //
287 __ bind(ext_cpuid7);
288 __ movl(rax, 0x80000007);
289 __ cpuid();
290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
291 __ movl(Address(rsi, 0), rax);
292 __ movl(Address(rsi, 4), rbx);
293 __ movl(Address(rsi, 8), rcx);
294 __ movl(Address(rsi,12), rdx);
295
296 //
297 // Extended cpuid(0x80000005)
298 //
299 __ bind(ext_cpuid5);
300 __ movl(rax, 0x80000005);
301 __ cpuid();
302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
303 __ movl(Address(rsi, 0), rax);
304 __ movl(Address(rsi, 4), rbx);
305 __ movl(Address(rsi, 8), rcx);
306 __ movl(Address(rsi,12), rdx);
307
308 //
309 // Extended cpuid(0x80000001)
310 //
311 __ bind(ext_cpuid1);
312 __ movl(rax, 0x80000001);
313 __ cpuid();
314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
315 __ movl(Address(rsi, 0), rax);
316 __ movl(Address(rsi, 4), rbx);
317 __ movl(Address(rsi, 8), rcx);
318 __ movl(Address(rsi,12), rdx);
319
320 //
321 // Check if OS has enabled XGETBV instruction to access XCR0
322 // (OSXSAVE feature flag) and CPU supports AVX
323 //
324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
327 __ cmpl(rcx, 0x18000000);
328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
329
330 __ movl(rax, 0x6);
331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
332 __ cmpl(rax, 0x6);
333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
334
335 // we need to bridge farther than imm8, so we use this island as a thunk
336 __ bind(done);
337 __ jmp(wrapup);
338
339 __ bind(start_simd_check);
340 //
341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
342 // registers are not restored after a signal processing.
343 // Generate SEGV here (reference through NULL)
344 // and check upper YMM/ZMM bits after it.
345 //
346 intx saved_useavx = UseAVX;
347 intx saved_usesse = UseSSE;
348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
350 __ movl(rax, 0x10000);
351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
352 __ cmpl(rax, 0x10000);
353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
354 // check _cpuid_info.xem_xcr0_eax.bits.opmask
355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
357 __ movl(rax, 0xE0);
358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
359 __ cmpl(rax, 0xE0);
360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
361
362 // If UseAVX is unitialized or is set by the user to include EVEX
363 if (use_evex) {
364 // EVEX setup: run in lowest evex mode
365 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
366 UseAVX = 3;
367 UseSSE = 2;
368 #ifdef _WINDOWS
369 // xmm5-xmm15 are not preserved by caller on windows
370 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
371 __ subptr(rsp, 64);
372 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
373 #ifdef _LP64
374 __ subptr(rsp, 64);
375 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
376 __ subptr(rsp, 64);
377 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
378 #endif // _LP64
379 #endif // _WINDOWS
380
381 // load value into all 64 bytes of zmm7 register
382 __ movl(rcx, VM_Version::ymm_test_value());
383 __ movdl(xmm0, rcx);
384 __ movl(rcx, 0xffff);
385 __ kmovwl(k1, rcx);
386 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
387 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
388 #ifdef _LP64
389 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
390 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
391 #endif
392 VM_Version::clean_cpuFeatures();
393 __ jmp(save_restore_except);
394 }
395
396 __ bind(legacy_setup);
397 // AVX setup
398 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
399 UseAVX = 1;
400 UseSSE = 2;
401 #ifdef _WINDOWS
402 __ subptr(rsp, 32);
403 __ vmovdqu(Address(rsp, 0), xmm7);
404 #ifdef _LP64
405 __ subptr(rsp, 32);
406 __ vmovdqu(Address(rsp, 0), xmm8);
407 __ subptr(rsp, 32);
408 __ vmovdqu(Address(rsp, 0), xmm15);
409 #endif // _LP64
410 #endif // _WINDOWS
411
412 // load value into all 32 bytes of ymm7 register
413 __ movl(rcx, VM_Version::ymm_test_value());
414
415 __ movdl(xmm0, rcx);
416 __ pshufd(xmm0, xmm0, 0x00);
417 __ vinsertf128_high(xmm0, xmm0);
418 __ vmovdqu(xmm7, xmm0);
419 #ifdef _LP64
420 __ vmovdqu(xmm8, xmm0);
421 __ vmovdqu(xmm15, xmm0);
422 #endif
423 VM_Version::clean_cpuFeatures();
424
425 __ bind(save_restore_except);
426 __ xorl(rsi, rsi);
427 VM_Version::set_cpuinfo_segv_addr(__ pc());
428 // Generate SEGV
429 __ movl(rax, Address(rsi, 0));
430
431 VM_Version::set_cpuinfo_cont_addr(__ pc());
432 // Returns here after signal. Save xmm0 to check it later.
433
434 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
435 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
436 __ movl(rax, 0x10000);
437 __ andl(rax, Address(rsi, 4));
438 __ cmpl(rax, 0x10000);
439 __ jccb(Assembler::notEqual, legacy_save_restore);
440 // check _cpuid_info.xem_xcr0_eax.bits.opmask
441 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
442 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
443 __ movl(rax, 0xE0);
444 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
445 __ cmpl(rax, 0xE0);
446 __ jccb(Assembler::notEqual, legacy_save_restore);
447
448 // If UseAVX is unitialized or is set by the user to include EVEX
449 if (use_evex) {
450 // EVEX check: run in lowest evex mode
451 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
452 UseAVX = 3;
453 UseSSE = 2;
454 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
455 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
456 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
457 #ifdef _LP64
458 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
459 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
460 #endif
461
462 #ifdef _WINDOWS
463 #ifdef _LP64
464 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
465 __ addptr(rsp, 64);
466 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
467 __ addptr(rsp, 64);
468 #endif // _LP64
469 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
470 __ addptr(rsp, 64);
471 #endif // _WINDOWS
472 __ vzeroupper();
473 VM_Version::clean_cpuFeatures();
474 UseAVX = saved_useavx;
475 UseSSE = saved_usesse;
476 __ jmp(wrapup);
477 }
478
479 __ bind(legacy_save_restore);
480 // AVX check
481 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
482 UseAVX = 1;
483 UseSSE = 2;
484 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
485 __ vmovdqu(Address(rsi, 0), xmm0);
486 __ vmovdqu(Address(rsi, 32), xmm7);
487 #ifdef _LP64
488 __ vmovdqu(Address(rsi, 64), xmm8);
489 __ vmovdqu(Address(rsi, 96), xmm15);
490 #endif
491
492 #ifdef _WINDOWS
493 #ifdef _LP64
494 __ vmovdqu(xmm15, Address(rsp, 0));
495 __ addptr(rsp, 32);
496 __ vmovdqu(xmm8, Address(rsp, 0));
497 __ addptr(rsp, 32);
498 #endif // _LP64
499 __ vmovdqu(xmm7, Address(rsp, 0));
500 __ addptr(rsp, 32);
501 #endif // _WINDOWS
502 __ vzeroupper();
503 VM_Version::clean_cpuFeatures();
504 UseAVX = saved_useavx;
505 UseSSE = saved_usesse;
506
507 __ bind(wrapup);
508 __ popf();
509 __ pop(rsi);
510 __ pop(rbx);
511 __ pop(rbp);
512 __ ret(0);
513
514 # undef __
515
516 return start;
517 };
518 };
519
520 void VM_Version::get_processor_features() {
521
522 _cpu = 4; // 486 by default
523 _model = 0;
524 _stepping = 0;
525 _features = 0;
526 _logical_processors_per_package = 1;
527 // i486 internal cache is both I&D and has a 16-byte line size
528 _L1_data_cache_line_size = 16;
529
530 // Get raw processor info
531
532 get_cpu_info_stub(&_cpuid_info);
533
534 assert_is_initialized();
535 _cpu = extended_cpu_family();
536 _model = extended_cpu_model();
537 _stepping = cpu_stepping();
538
539 if (cpu_family() > 4) { // it supports CPUID
540 _features = feature_flags();
541 // Logical processors are only available on P4s and above,
542 // and only if hyperthreading is available.
543 _logical_processors_per_package = logical_processor_count();
544 _L1_data_cache_line_size = L1_line_size();
545 }
546
547 _supports_cx8 = supports_cmpxchg8();
548 // xchg and xadd instructions
549 _supports_atomic_getset4 = true;
550 _supports_atomic_getadd4 = true;
551 LP64_ONLY(_supports_atomic_getset8 = true);
552 LP64_ONLY(_supports_atomic_getadd8 = true);
553
554 #ifdef _LP64
555 // OS should support SSE for x64 and hardware should support at least SSE2.
556 if (!VM_Version::supports_sse2()) {
557 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
558 }
559 // in 64 bit the use of SSE2 is the minimum
560 if (UseSSE < 2) UseSSE = 2;
561 #endif
562
563 #ifdef AMD64
564 // flush_icache_stub have to be generated first.
565 // That is why Icache line size is hard coded in ICache class,
566 // see icache_x86.hpp. It is also the reason why we can't use
567 // clflush instruction in 32-bit VM since it could be running
568 // on CPU which does not support it.
569 //
570 // The only thing we can do is to verify that flushed
571 // ICache::line_size has correct value.
572 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
573 // clflush_size is size in quadwords (8 bytes).
574 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
575 #endif
576
577 // If the OS doesn't support SSE, we can't use this feature even if the HW does
578 if (!os::supports_sse())
579 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
580
581 if (UseSSE < 4) {
582 _features &= ~CPU_SSE4_1;
583 _features &= ~CPU_SSE4_2;
584 }
585
586 if (UseSSE < 3) {
587 _features &= ~CPU_SSE3;
588 _features &= ~CPU_SSSE3;
589 _features &= ~CPU_SSE4A;
590 }
591
592 if (UseSSE < 2)
593 _features &= ~CPU_SSE2;
594
595 if (UseSSE < 1)
596 _features &= ~CPU_SSE;
597
598 // first try initial setting and detect what we can support
599 if (UseAVX > 0) {
600 if (UseAVX > 2 && supports_evex()) {
601 UseAVX = 3;
602 } else if (UseAVX > 1 && supports_avx2()) {
603 UseAVX = 2;
604 } else if (UseAVX > 0 && supports_avx()) {
605 UseAVX = 1;
606 } else {
607 UseAVX = 0;
608 }
609 } else if (UseAVX < 0) {
610 UseAVX = 0;
611 }
612
613 if (UseAVX < 3) {
614 _features &= ~CPU_AVX512F;
615 _features &= ~CPU_AVX512DQ;
616 _features &= ~CPU_AVX512CD;
617 _features &= ~CPU_AVX512BW;
618 _features &= ~CPU_AVX512VL;
619 }
620
621 if (UseAVX < 2)
622 _features &= ~CPU_AVX2;
623
624 if (UseAVX < 1) {
625 _features &= ~CPU_AVX;
626 _features &= ~CPU_VZEROUPPER;
627 }
628
629 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
630 _features &= ~CPU_AES;
631
632 if (logical_processors_per_package() == 1) {
633 // HT processor could be installed on a system which doesn't support HT.
634 _features &= ~CPU_HT;
635 }
636
637 if( is_intel() ) { // Intel cpus specific settings
638 if ((cpu_family() == 0x06) &&
639 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
640 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
641 _features &= ~CPU_VZEROUPPER;
642 }
643 }
644
645 char buf[256];
646 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
647 cores_per_cpu(), threads_per_core(),
648 cpu_family(), _model, _stepping,
649 (supports_cmov() ? ", cmov" : ""),
650 (supports_cmpxchg8() ? ", cx8" : ""),
651 (supports_fxsr() ? ", fxsr" : ""),
652 (supports_mmx() ? ", mmx" : ""),
653 (supports_sse() ? ", sse" : ""),
654 (supports_sse2() ? ", sse2" : ""),
655 (supports_sse3() ? ", sse3" : ""),
656 (supports_ssse3()? ", ssse3": ""),
657 (supports_sse4_1() ? ", sse4.1" : ""),
658 (supports_sse4_2() ? ", sse4.2" : ""),
659 (supports_popcnt() ? ", popcnt" : ""),
660 (supports_avx() ? ", avx" : ""),
661 (supports_avx2() ? ", avx2" : ""),
662 (supports_aes() ? ", aes" : ""),
663 (supports_clmul() ? ", clmul" : ""),
664 (supports_erms() ? ", erms" : ""),
665 (supports_rtm() ? ", rtm" : ""),
666 (supports_mmx_ext() ? ", mmxext" : ""),
667 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
668 (supports_lzcnt() ? ", lzcnt": ""),
669 (supports_sse4a() ? ", sse4a": ""),
670 (supports_ht() ? ", ht": ""),
671 (supports_tsc() ? ", tsc": ""),
672 (supports_tscinv_bit() ? ", tscinvbit": ""),
673 (supports_tscinv() ? ", tscinv": ""),
674 (supports_bmi1() ? ", bmi1" : ""),
675 (supports_bmi2() ? ", bmi2" : ""),
676 (supports_adx() ? ", adx" : ""),
677 (supports_evex() ? ", evex" : ""),
678 (supports_sha() ? ", sha" : ""),
679 (supports_fma() ? ", fma" : ""));
680 _features_string = os::strdup(buf);
681
682 // UseSSE is set to the smaller of what hardware supports and what
683 // the command line requires. I.e., you cannot set UseSSE to 2 on
684 // older Pentiums which do not support it.
685 if (UseSSE > 4) UseSSE=4;
686 if (UseSSE < 0) UseSSE=0;
687 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
688 UseSSE = MIN2((intx)3,UseSSE);
689 if (!supports_sse3()) // Drop to 2 if no SSE3 support
690 UseSSE = MIN2((intx)2,UseSSE);
691 if (!supports_sse2()) // Drop to 1 if no SSE2 support
692 UseSSE = MIN2((intx)1,UseSSE);
693 if (!supports_sse ()) // Drop to 0 if no SSE support
694 UseSSE = 0;
695
696 // Use AES instructions if available.
697 if (supports_aes()) {
698 if (FLAG_IS_DEFAULT(UseAES)) {
699 FLAG_SET_DEFAULT(UseAES, true);
700 }
701 if (!UseAES) {
702 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
703 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
704 }
705 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
706 } else {
707 if (UseSSE > 2) {
708 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
709 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
710 }
711 } else {
712 // The AES intrinsic stubs require AES instruction support (of course)
713 // but also require sse3 mode or higher for instructions it use.
714 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
715 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
716 }
717 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
718 }
719
720 // --AES-CTR begins--
721 if (!UseAESIntrinsics) {
722 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
723 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
724 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
725 }
726 } else {
727 if(supports_sse4_1()) {
728 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
729 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
730 }
731 } else {
732 // The AES-CTR intrinsic stubs require AES instruction support (of course)
733 // but also require sse4.1 mode or higher for instructions it use.
734 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
735 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
736 }
737 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
738 }
739 }
740 // --AES-CTR ends--
741 }
742 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
743 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
744 warning("AES instructions are not available on this CPU");
745 FLAG_SET_DEFAULT(UseAES, false);
746 }
747 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
748 warning("AES intrinsics are not available on this CPU");
749 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
750 }
751 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
752 warning("AES-CTR intrinsics are not available on this CPU");
753 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
754 }
755 }
756
757 // Use CLMUL instructions if available.
758 if (supports_clmul()) {
759 if (FLAG_IS_DEFAULT(UseCLMUL)) {
760 UseCLMUL = true;
761 }
762 } else if (UseCLMUL) {
763 if (!FLAG_IS_DEFAULT(UseCLMUL))
764 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
765 FLAG_SET_DEFAULT(UseCLMUL, false);
766 }
767
768 if (UseCLMUL && (UseSSE > 2)) {
769 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
770 UseCRC32Intrinsics = true;
771 }
772 } else if (UseCRC32Intrinsics) {
773 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
774 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
775 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
776 }
777
778 if (supports_sse4_2()) {
779 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
780 UseCRC32CIntrinsics = true;
781 }
782 }
783 else if (UseCRC32CIntrinsics) {
784 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
785 warning("CRC32C intrinsics are not available on this CPU");
786 }
787 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
788 }
789
790 // GHASH/GCM intrinsics
791 if (UseCLMUL && (UseSSE > 2)) {
792 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
793 UseGHASHIntrinsics = true;
794 }
795 } else if (UseGHASHIntrinsics) {
796 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
797 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
798 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
799 }
800
801 if (supports_fma() && UseSSE >= 2) {
802 if (FLAG_IS_DEFAULT(UseFMA)) {
803 UseFMA = true;
804 }
805 } else if (UseFMA) {
806 warning("FMA instructions are not available on this CPU");
807 FLAG_SET_DEFAULT(UseFMA, false);
808 }
809
810 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
811 if (FLAG_IS_DEFAULT(UseSHA)) {
812 UseSHA = true;
813 }
814 } else if (UseSHA) {
815 warning("SHA instructions are not available on this CPU");
816 FLAG_SET_DEFAULT(UseSHA, false);
817 }
818
819 if (supports_sha() && UseSHA) {
820 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
821 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
822 }
823 } else if (UseSHA1Intrinsics) {
824 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
825 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
826 }
827
828 if (UseSHA) {
829 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
830 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
831 }
832 } else if (UseSHA256Intrinsics) {
833 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
834 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
835 }
836
837 if (UseSHA) {
838 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
839 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
840 }
841 } else if (UseSHA512Intrinsics) {
842 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
843 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
844 }
845
846 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
847 FLAG_SET_DEFAULT(UseSHA, false);
848 }
849
850 if (UseAdler32Intrinsics) {
851 warning("Adler32Intrinsics not available on this CPU.");
852 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
853 }
854
855 if (!supports_rtm() && UseRTMLocking) {
856 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
857 // setting during arguments processing. See use_biased_locking().
858 // VM_Version_init() is executed after UseBiasedLocking is used
859 // in Thread::allocate().
860 vm_exit_during_initialization("RTM instructions are not available on this CPU");
861 }
862
863 #if INCLUDE_RTM_OPT
864 if (UseRTMLocking) {
865 if (is_client_compilation_mode_vm()) {
866 // Only C2 does RTM locking optimization.
867 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
868 // setting during arguments processing. See use_biased_locking().
869 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
870 }
871 if (is_intel_family_core()) {
872 if ((_model == CPU_MODEL_HASWELL_E3) ||
873 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
874 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
875 // currently a collision between SKL and HSW_E3
876 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
877 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
878 } else {
879 warning("UseRTMLocking is only available as experimental option on this platform.");
880 }
881 }
882 }
883 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
884 // RTM locking should be used only for applications with
885 // high lock contention. For now we do not use it by default.
886 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
887 }
888 if (!is_power_of_2(RTMTotalCountIncrRate)) {
889 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
890 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
891 }
892 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
893 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
894 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
895 }
896 } else { // !UseRTMLocking
897 if (UseRTMForStackLocks) {
898 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
899 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
900 }
901 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
902 }
903 if (UseRTMDeopt) {
904 FLAG_SET_DEFAULT(UseRTMDeopt, false);
905 }
906 if (PrintPreciseRTMLockingStatistics) {
907 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
908 }
909 }
910 #else
911 if (UseRTMLocking) {
912 // Only C2 does RTM locking optimization.
913 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
914 // setting during arguments processing. See use_biased_locking().
915 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
916 }
917 #endif
918
919 #ifdef COMPILER2
920 if (UseFPUForSpilling) {
921 if (UseSSE < 2) {
922 // Only supported with SSE2+
923 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
924 }
925 }
926 #endif
927 #if defined(COMPILER2) || INCLUDE_JVMCI
928 if (MaxVectorSize > 0) {
929 if (!is_power_of_2(MaxVectorSize)) {
930 warning("MaxVectorSize must be a power of 2");
931 FLAG_SET_DEFAULT(MaxVectorSize, 64);
932 }
933 if (UseSSE < 2) {
934 // Vectors (in XMM) are only supported with SSE2+
935 if (MaxVectorSize > 0) {
936 if (!FLAG_IS_DEFAULT(MaxVectorSize))
937 warning("MaxVectorSize must be 0");
938 FLAG_SET_DEFAULT(MaxVectorSize, 0);
939 }
940 }
941 else if (UseAVX == 0 || !os_supports_avx_vectors()) {
942 // 32 bytes vectors (in YMM) are only supported with AVX+
943 if (MaxVectorSize > 16) {
944 if (!FLAG_IS_DEFAULT(MaxVectorSize))
945 warning("MaxVectorSize must be <= 16");
946 FLAG_SET_DEFAULT(MaxVectorSize, 16);
947 }
948 }
949 else if (UseAVX == 1 || UseAVX == 2) {
950 // 64 bytes vectors (in ZMM) are only supported with AVX 3
951 if (MaxVectorSize > 32) {
952 if (!FLAG_IS_DEFAULT(MaxVectorSize))
953 warning("MaxVectorSize must be <= 32");
954 FLAG_SET_DEFAULT(MaxVectorSize, 32);
955 }
956 }
957 else if (UseAVX > 2 ) {
958 if (MaxVectorSize > 64) {
959 if (!FLAG_IS_DEFAULT(MaxVectorSize))
960 warning("MaxVectorSize must be <= 64");
961 FLAG_SET_DEFAULT(MaxVectorSize, 64);
962 }
963 }
964 #if defined(COMPILER2) && defined(ASSERT)
965 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
966 tty->print_cr("State of YMM registers after signal handle:");
967 int nreg = 2 LP64_ONLY(+2);
968 const char* ymm_name[4] = {"0", "7", "8", "15"};
969 for (int i = 0; i < nreg; i++) {
970 tty->print("YMM%s:", ymm_name[i]);
971 for (int j = 7; j >=0; j--) {
972 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
973 }
974 tty->cr();
975 }
976 }
977 #endif // COMPILER2 && ASSERT
978 }
979 #endif // COMPILER2 || INCLUDE_JVMCI
980
981 #ifdef COMPILER2
982 #ifdef _LP64
983 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
984 UseMultiplyToLenIntrinsic = true;
985 }
986 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
987 UseSquareToLenIntrinsic = true;
988 }
989 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
990 UseMulAddIntrinsic = true;
991 }
992 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
993 UseMontgomeryMultiplyIntrinsic = true;
994 }
995 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
996 UseMontgomerySquareIntrinsic = true;
997 }
998 #else
999 if (UseMultiplyToLenIntrinsic) {
1000 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1001 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1002 }
1003 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1004 }
1005 if (UseMontgomeryMultiplyIntrinsic) {
1006 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1007 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1008 }
1009 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1010 }
1011 if (UseMontgomerySquareIntrinsic) {
1012 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1013 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1014 }
1015 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1016 }
1017 if (UseSquareToLenIntrinsic) {
1018 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1019 warning("squareToLen intrinsic is not available in 32-bit VM");
1020 }
1021 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1022 }
1023 if (UseMulAddIntrinsic) {
1024 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1025 warning("mulAdd intrinsic is not available in 32-bit VM");
1026 }
1027 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1028 }
1029 #endif
1030 #endif // COMPILER2
1031
1032 // On new cpus instructions which update whole XMM register should be used
1033 // to prevent partial register stall due to dependencies on high half.
1034 //
1035 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1036 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1037 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1038 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1039
1040 if( is_amd() ) { // AMD cpus specific settings
1041 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1042 // Use it on new AMD cpus starting from Opteron.
1043 UseAddressNop = true;
1044 }
1045 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1046 // Use it on new AMD cpus starting from Opteron.
1047 UseNewLongLShift = true;
1048 }
1049 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1050 if (supports_sse4a()) {
1051 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1052 } else {
1053 UseXmmLoadAndClearUpper = false;
1054 }
1055 }
1056 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1057 if( supports_sse4a() ) {
1058 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1059 } else {
1060 UseXmmRegToRegMoveAll = false;
1061 }
1062 }
1063 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1064 if( supports_sse4a() ) {
1065 UseXmmI2F = true;
1066 } else {
1067 UseXmmI2F = false;
1068 }
1069 }
1070 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1071 if( supports_sse4a() ) {
1072 UseXmmI2D = true;
1073 } else {
1074 UseXmmI2D = false;
1075 }
1076 }
1077 if (supports_sse4_2()) {
1078 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1079 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1080 }
1081 } else {
1082 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1083 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1084 }
1085 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1086 }
1087
1088 // some defaults for AMD family 15h
1089 if ( cpu_family() == 0x15 ) {
1090 // On family 15h processors default is no sw prefetch
1091 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1092 AllocatePrefetchStyle = 0;
1093 }
1094 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1095 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1096 AllocatePrefetchInstr = 3;
1097 }
1098 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1099 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1100 UseXMMForArrayCopy = true;
1101 }
1102 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1103 UseUnalignedLoadStores = true;
1104 }
1105 }
1106
1107 #ifdef COMPILER2
1108 if (MaxVectorSize > 16) {
1109 // Limit vectors size to 16 bytes on current AMD cpus.
1110 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1111 }
1112 #endif // COMPILER2
1113 }
1114
1115 if( is_intel() ) { // Intel cpus specific settings
1116 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1117 UseStoreImmI16 = false; // don't use it on Intel cpus
1118 }
1119 if( cpu_family() == 6 || cpu_family() == 15 ) {
1120 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1121 // Use it on all Intel cpus starting from PentiumPro
1122 UseAddressNop = true;
1123 }
1124 }
1125 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1126 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1127 }
1128 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1129 if( supports_sse3() ) {
1130 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1131 } else {
1132 UseXmmRegToRegMoveAll = false;
1133 }
1134 }
1135 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1136 #ifdef COMPILER2
1137 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1138 // For new Intel cpus do the next optimization:
1139 // don't align the beginning of a loop if there are enough instructions
1140 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1141 // in current fetch line (OptoLoopAlignment) or the padding
1142 // is big (> MaxLoopPad).
1143 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1144 // generated NOP instructions. 11 is the largest size of one
1145 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1146 MaxLoopPad = 11;
1147 }
1148 #endif // COMPILER2
1149 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1150 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1151 }
1152 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1153 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1154 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1155 }
1156 }
1157 if (supports_sse4_2()) {
1158 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1159 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1160 }
1161 } else {
1162 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1163 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1164 }
1165 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1166 }
1167 }
1168 if ((cpu_family() == 0x06) &&
1169 ((extended_cpu_model() == 0x36) || // Centerton
1170 (extended_cpu_model() == 0x37) || // Silvermont
1171 (extended_cpu_model() == 0x4D))) {
1172 #ifdef COMPILER2
1173 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1174 OptoScheduling = true;
1175 }
1176 #endif
1177 if (supports_sse4_2()) { // Silvermont
1178 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1179 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1180 }
1181 }
1182 }
1183 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1184 AllocatePrefetchInstr = 3;
1185 }
1186 }
1187
1188 #ifdef _LP64
1189 if (UseSSE42Intrinsics) {
1190 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1191 UseVectorizedMismatchIntrinsic = true;
1192 }
1193 } else if (UseVectorizedMismatchIntrinsic) {
1194 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1195 warning("vectorizedMismatch intrinsics are not available on this CPU");
1196 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1197 }
1198 #else
1199 if (UseVectorizedMismatchIntrinsic) {
1200 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1201 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1202 }
1203 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1204 }
1205 #endif // _LP64
1206
1207 // Use count leading zeros count instruction if available.
1208 if (supports_lzcnt()) {
1209 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1210 UseCountLeadingZerosInstruction = true;
1211 }
1212 } else if (UseCountLeadingZerosInstruction) {
1213 warning("lzcnt instruction is not available on this CPU");
1214 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1215 }
1216
1217 // Use count trailing zeros instruction if available
1218 if (supports_bmi1()) {
1219 // tzcnt does not require VEX prefix
1220 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1221 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1222 // Don't use tzcnt if BMI1 is switched off on command line.
1223 UseCountTrailingZerosInstruction = false;
1224 } else {
1225 UseCountTrailingZerosInstruction = true;
1226 }
1227 }
1228 } else if (UseCountTrailingZerosInstruction) {
1229 warning("tzcnt instruction is not available on this CPU");
1230 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1231 }
1232
1233 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1234 // VEX prefix is generated only when AVX > 0.
1235 if (supports_bmi1() && supports_avx()) {
1236 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1237 UseBMI1Instructions = true;
1238 }
1239 } else if (UseBMI1Instructions) {
1240 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1241 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1242 }
1243
1244 if (supports_bmi2() && supports_avx()) {
1245 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1246 UseBMI2Instructions = true;
1247 }
1248 } else if (UseBMI2Instructions) {
1249 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1250 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1251 }
1252
1253 // Use population count instruction if available.
1254 if (supports_popcnt()) {
1255 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1256 UsePopCountInstruction = true;
1257 }
1258 } else if (UsePopCountInstruction) {
1259 warning("POPCNT instruction is not available on this CPU");
1260 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1261 }
1262
1263 // Use fast-string operations if available.
1264 if (supports_erms()) {
1265 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1266 UseFastStosb = true;
1267 }
1268 } else if (UseFastStosb) {
1269 warning("fast-string operations are not available on this CPU");
1270 FLAG_SET_DEFAULT(UseFastStosb, false);
1271 }
1272
1273 #ifdef COMPILER2
1274 if (FLAG_IS_DEFAULT(AlignVector)) {
1275 // Modern processors allow misaligned memory operations for vectors.
1276 AlignVector = !UseUnalignedLoadStores;
1277 }
1278 #endif // COMPILER2
1279
1280 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1281 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1282
1283 // Allocation prefetch settings
1284 intx cache_line_size = prefetch_data_size();
1285 if( cache_line_size > AllocatePrefetchStepSize )
1286 AllocatePrefetchStepSize = cache_line_size;
1287
1288 AllocatePrefetchDistance = allocate_prefetch_distance();
1289 AllocatePrefetchStyle = allocate_prefetch_style();
1290
1291 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1292 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1293 #ifdef _LP64
1294 AllocatePrefetchDistance = 384;
1295 #else
1296 AllocatePrefetchDistance = 320;
1297 #endif
1298 }
1299 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1300 AllocatePrefetchDistance = 192;
1301 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
1302 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1303 }
1304 }
1305 #ifdef COMPILER2
1306 if (supports_sse4_2()) {
1307 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1308 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1309 }
1310 }
1311 #endif
1312 }
1313
1314 #ifdef _LP64
1315 // Prefetch settings
1316 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1317 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1318 PrefetchFieldsAhead = prefetch_fields_ahead();
1319 #endif
1320
1321 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1322 (cache_line_size > ContendedPaddingWidth))
1323 ContendedPaddingWidth = cache_line_size;
1324
1325 // This machine allows unaligned memory accesses
1326 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1327 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1328 }
1329
1330 #ifndef PRODUCT
1331 if (log_is_enabled(Info, os, cpu)) {
1332 outputStream* log = Log(os, cpu)::info_stream();
1333 log->print_cr("Logical CPUs per core: %u",
1334 logical_processors_per_package());
1335 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1336 log->print("UseSSE=%d", (int) UseSSE);
1337 if (UseAVX > 0) {
1338 log->print(" UseAVX=%d", (int) UseAVX);
1339 }
1340 if (UseAES) {
1341 log->print(" UseAES=1");
1342 }
1343 #ifdef COMPILER2
1344 if (MaxVectorSize > 0) {
1345 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1346 }
1347 #endif
1348 log->cr();
1349 log->print("Allocation");
1350 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1351 log->print_cr(": no prefetching");
1352 } else {
1353 log->print(" prefetching: ");
1354 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1355 log->print("PREFETCHW");
1356 } else if (UseSSE >= 1) {
1357 if (AllocatePrefetchInstr == 0) {
1358 log->print("PREFETCHNTA");
1359 } else if (AllocatePrefetchInstr == 1) {
1360 log->print("PREFETCHT0");
1361 } else if (AllocatePrefetchInstr == 2) {
1362 log->print("PREFETCHT2");
1363 } else if (AllocatePrefetchInstr == 3) {
1364 log->print("PREFETCHW");
1365 }
1366 }
1367 if (AllocatePrefetchLines > 1) {
1368 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1369 } else {
1370 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1371 }
1372 }
1373
1374 if (PrefetchCopyIntervalInBytes > 0) {
1375 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1376 }
1377 if (PrefetchScanIntervalInBytes > 0) {
1378 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1379 }
1380 if (PrefetchFieldsAhead > 0) {
1381 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1382 }
1383 if (ContendedPaddingWidth > 0) {
1384 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1385 }
1386 }
1387 #endif // !PRODUCT
1388 }
1389
1390 bool VM_Version::use_biased_locking() {
1391 #if INCLUDE_RTM_OPT
1392 // RTM locking is most useful when there is high lock contention and
1393 // low data contention. With high lock contention the lock is usually
1394 // inflated and biased locking is not suitable for that case.
1395 // RTM locking code requires that biased locking is off.
1396 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1397 // because it is used by Thread::allocate() which is called before
1398 // VM_Version::initialize().
1399 if (UseRTMLocking && UseBiasedLocking) {
1400 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1401 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1402 } else {
1403 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1404 UseBiasedLocking = false;
1405 }
1406 }
1407 #endif
1408 return UseBiasedLocking;
1409 }
1410
1411 void VM_Version::initialize() {
1412 ResourceMark rm;
1413 // Making this stub must be FIRST use of assembler
1414
1415 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1416 if (stub_blob == NULL) {
1417 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1418 }
1419 CodeBuffer c(stub_blob);
1420 VM_Version_StubGenerator g(&c);
1421 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1422 g.generate_get_cpu_info());
1423
1424 get_processor_features();
1425 }