1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 friend class VMStructs;
33 friend class JVMCIVMStructs;
34
35 public:
36 // cpuid result register layouts. These are all unions of a uint32_t
37 // (in case anyone wants access to the register as a whole) and a bitfield.
38
39 union StdCpuid1Eax {
40 uint32_t value;
41 struct {
42 uint32_t stepping : 4,
43 model : 4,
44 family : 4,
45 proc_type : 2,
46 : 2,
47 ext_model : 4,
48 ext_family : 8,
49 : 4;
50 } bits;
51 };
52
53 union StdCpuid1Ebx { // example, unused
54 uint32_t value;
55 struct {
56 uint32_t brand_id : 8,
57 clflush_size : 8,
58 threads_per_cpu : 8,
59 apic_id : 8;
60 } bits;
61 };
62
63 union StdCpuid1Ecx {
64 uint32_t value;
65 struct {
66 uint32_t sse3 : 1,
67 clmul : 1,
68 : 1,
69 monitor : 1,
70 : 1,
71 vmx : 1,
72 : 1,
73 est : 1,
74 : 1,
75 ssse3 : 1,
76 cid : 1,
77 : 1,
78 fma : 1,
79 cmpxchg16: 1,
80 : 4,
81 dca : 1,
82 sse4_1 : 1,
83 sse4_2 : 1,
84 : 2,
85 popcnt : 1,
86 : 1,
87 aes : 1,
88 : 1,
89 osxsave : 1,
90 avx : 1,
91 : 3;
92 } bits;
93 };
94
95 union StdCpuid1Edx {
96 uint32_t value;
97 struct {
98 uint32_t : 4,
99 tsc : 1,
100 : 3,
101 cmpxchg8 : 1,
102 : 6,
103 cmov : 1,
104 : 3,
105 clflush : 1,
106 : 3,
107 mmx : 1,
108 fxsr : 1,
109 sse : 1,
110 sse2 : 1,
111 : 1,
112 ht : 1,
113 : 3;
114 } bits;
115 };
116
117 union DcpCpuid4Eax {
118 uint32_t value;
119 struct {
120 uint32_t cache_type : 5,
121 : 21,
122 cores_per_cpu : 6;
123 } bits;
124 };
125
126 union DcpCpuid4Ebx {
127 uint32_t value;
128 struct {
129 uint32_t L1_line_size : 12,
130 partitions : 10,
131 associativity : 10;
132 } bits;
133 };
134
135 union TplCpuidBEbx {
136 uint32_t value;
137 struct {
138 uint32_t logical_cpus : 16,
139 : 16;
140 } bits;
141 };
142
143 union ExtCpuid1Ecx {
144 uint32_t value;
145 struct {
146 uint32_t LahfSahf : 1,
147 CmpLegacy : 1,
148 : 3,
149 lzcnt_intel : 1,
150 lzcnt : 1,
151 sse4a : 1,
152 misalignsse : 1,
153 prefetchw : 1,
154 : 22;
155 } bits;
156 };
157
158 union ExtCpuid1Edx {
159 uint32_t value;
160 struct {
161 uint32_t : 22,
162 mmx_amd : 1,
163 mmx : 1,
164 fxsr : 1,
165 : 4,
166 long_mode : 1,
167 tdnow2 : 1,
168 tdnow : 1;
169 } bits;
170 };
171
172 union ExtCpuid5Ex {
173 uint32_t value;
174 struct {
175 uint32_t L1_line_size : 8,
176 L1_tag_lines : 8,
177 L1_assoc : 8,
178 L1_size : 8;
179 } bits;
180 };
181
182 union ExtCpuid7Edx {
183 uint32_t value;
184 struct {
185 uint32_t : 8,
186 tsc_invariance : 1,
187 : 23;
188 } bits;
189 };
190
191 union ExtCpuid8Ecx {
192 uint32_t value;
193 struct {
194 uint32_t cores_per_cpu : 8,
195 : 24;
196 } bits;
197 };
198
199 union SefCpuid7Eax {
200 uint32_t value;
201 };
202
203 union SefCpuid7Ebx {
204 uint32_t value;
205 struct {
206 uint32_t fsgsbase : 1,
207 : 2,
208 bmi1 : 1,
209 : 1,
210 avx2 : 1,
211 : 2,
212 bmi2 : 1,
213 erms : 1,
214 : 1,
215 rtm : 1,
216 : 4,
217 avx512f : 1,
218 avx512dq : 1,
219 : 1,
220 adx : 1,
221 : 6,
222 avx512pf : 1,
223 avx512er : 1,
224 avx512cd : 1,
225 sha : 1,
226 avx512bw : 1,
227 avx512vl : 1;
228 } bits;
229 };
230
231 union XemXcr0Eax {
232 uint32_t value;
233 struct {
234 uint32_t x87 : 1,
235 sse : 1,
236 ymm : 1,
237 bndregs : 1,
238 bndcsr : 1,
239 opmask : 1,
240 zmm512 : 1,
241 zmm32 : 1,
242 : 24;
243 } bits;
244 };
245
246 protected:
247 static int _cpu;
248 static int _model;
249 static int _stepping;
250
251 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
252 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
253
254 enum Feature_Flag {
255 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
256 CPU_CMOV = (1 << 1),
257 CPU_FXSR = (1 << 2),
258 CPU_HT = (1 << 3),
259 CPU_MMX = (1 << 4),
260 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
261 // may not necessarily support other 3dnow instructions
262 CPU_SSE = (1 << 6),
263 CPU_SSE2 = (1 << 7),
264 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
265 CPU_SSSE3 = (1 << 9),
266 CPU_SSE4A = (1 << 10),
267 CPU_SSE4_1 = (1 << 11),
268 CPU_SSE4_2 = (1 << 12),
269 CPU_POPCNT = (1 << 13),
270 CPU_LZCNT = (1 << 14),
271 CPU_TSC = (1 << 15),
272 CPU_TSCINV = (1 << 16),
273 CPU_AVX = (1 << 17),
274 CPU_AVX2 = (1 << 18),
275 CPU_AES = (1 << 19),
276 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
277 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
278 CPU_BMI1 = (1 << 22),
279 CPU_BMI2 = (1 << 23),
280 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
281 CPU_ADX = (1 << 25),
282 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
283 CPU_AVX512DQ = (1 << 27),
284 CPU_AVX512PF = (1 << 28),
285 CPU_AVX512ER = (1 << 29),
286 CPU_AVX512CD = (1 << 30)
287 // Keeping sign bit 31 unassigned.
288 };
289
290 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
291 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
292 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
293 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
294 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
295
296 enum Extended_Family {
297 // AMD
298 CPU_FAMILY_AMD_11H = 0x11,
299 // Intel
300 CPU_FAMILY_INTEL_CORE = 6,
301 CPU_MODEL_NEHALEM = 0x1e,
302 CPU_MODEL_NEHALEM_EP = 0x1a,
303 CPU_MODEL_NEHALEM_EX = 0x2e,
304 CPU_MODEL_WESTMERE = 0x25,
305 CPU_MODEL_WESTMERE_EP = 0x2c,
306 CPU_MODEL_WESTMERE_EX = 0x2f,
307 CPU_MODEL_SANDYBRIDGE = 0x2a,
308 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
309 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
310 CPU_MODEL_HASWELL_E3 = 0x3c,
311 CPU_MODEL_HASWELL_E7 = 0x3f,
312 CPU_MODEL_BROADWELL = 0x3d,
313 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
314 };
315
316 // cpuid information block. All info derived from executing cpuid with
317 // various function numbers is stored here. Intel and AMD info is
318 // merged in this block: accessor methods disentangle it.
319 //
320 // The info block is laid out in subblocks of 4 dwords corresponding to
321 // eax, ebx, ecx and edx, whether or not they contain anything useful.
322 struct CpuidInfo {
323 // cpuid function 0
324 uint32_t std_max_function;
325 uint32_t std_vendor_name_0;
326 uint32_t std_vendor_name_1;
327 uint32_t std_vendor_name_2;
328
329 // cpuid function 1
330 StdCpuid1Eax std_cpuid1_eax;
331 StdCpuid1Ebx std_cpuid1_ebx;
332 StdCpuid1Ecx std_cpuid1_ecx;
333 StdCpuid1Edx std_cpuid1_edx;
334
335 // cpuid function 4 (deterministic cache parameters)
336 DcpCpuid4Eax dcp_cpuid4_eax;
337 DcpCpuid4Ebx dcp_cpuid4_ebx;
338 uint32_t dcp_cpuid4_ecx; // unused currently
339 uint32_t dcp_cpuid4_edx; // unused currently
340
341 // cpuid function 7 (structured extended features)
342 SefCpuid7Eax sef_cpuid7_eax;
343 SefCpuid7Ebx sef_cpuid7_ebx;
344 uint32_t sef_cpuid7_ecx; // unused currently
345 uint32_t sef_cpuid7_edx; // unused currently
346
347 // cpuid function 0xB (processor topology)
348 // ecx = 0
349 uint32_t tpl_cpuidB0_eax;
350 TplCpuidBEbx tpl_cpuidB0_ebx;
351 uint32_t tpl_cpuidB0_ecx; // unused currently
352 uint32_t tpl_cpuidB0_edx; // unused currently
353
354 // ecx = 1
355 uint32_t tpl_cpuidB1_eax;
356 TplCpuidBEbx tpl_cpuidB1_ebx;
357 uint32_t tpl_cpuidB1_ecx; // unused currently
358 uint32_t tpl_cpuidB1_edx; // unused currently
359
360 // ecx = 2
361 uint32_t tpl_cpuidB2_eax;
362 TplCpuidBEbx tpl_cpuidB2_ebx;
363 uint32_t tpl_cpuidB2_ecx; // unused currently
364 uint32_t tpl_cpuidB2_edx; // unused currently
365
366 // cpuid function 0x80000000 // example, unused
367 uint32_t ext_max_function;
368 uint32_t ext_vendor_name_0;
369 uint32_t ext_vendor_name_1;
370 uint32_t ext_vendor_name_2;
371
372 // cpuid function 0x80000001
373 uint32_t ext_cpuid1_eax; // reserved
374 uint32_t ext_cpuid1_ebx; // reserved
375 ExtCpuid1Ecx ext_cpuid1_ecx;
376 ExtCpuid1Edx ext_cpuid1_edx;
377
378 // cpuid functions 0x80000002 thru 0x80000004: example, unused
379 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
380 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
381 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
382
383 // cpuid function 0x80000005 // AMD L1, Intel reserved
384 uint32_t ext_cpuid5_eax; // unused currently
385 uint32_t ext_cpuid5_ebx; // reserved
386 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
387 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
388
389 // cpuid function 0x80000007
390 uint32_t ext_cpuid7_eax; // reserved
391 uint32_t ext_cpuid7_ebx; // reserved
392 uint32_t ext_cpuid7_ecx; // reserved
393 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
394
395 // cpuid function 0x80000008
396 uint32_t ext_cpuid8_eax; // unused currently
397 uint32_t ext_cpuid8_ebx; // reserved
398 ExtCpuid8Ecx ext_cpuid8_ecx;
399 uint32_t ext_cpuid8_edx; // reserved
400
401 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
402 XemXcr0Eax xem_xcr0_eax;
403 uint32_t xem_xcr0_edx; // reserved
404
405 // Space to save ymm registers after signal handle
406 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
407
408 // Space to save zmm registers after signal handle
409 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
410 };
411
412 // The actual cpuid info block
413 static CpuidInfo _cpuid_info;
414
415 // Extractors and predicates
416 static uint32_t extended_cpu_family() {
417 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
418 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
419 return result;
420 }
421
422 static uint32_t extended_cpu_model() {
423 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
424 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
425 return result;
426 }
427
428 static uint32_t cpu_stepping() {
429 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
430 return result;
431 }
432
433 static uint logical_processor_count() {
434 uint result = threads_per_core();
435 return result;
436 }
437
438 static uint64_t feature_flags() {
439 uint64_t result = 0;
440 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
441 result |= CPU_CX8;
442 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
443 result |= CPU_CMOV;
444 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
445 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
446 result |= CPU_FXSR;
447 // HT flag is set for multi-core processors also.
448 if (threads_per_core() > 1)
449 result |= CPU_HT;
450 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
451 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
452 result |= CPU_MMX;
453 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
454 result |= CPU_SSE;
455 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
456 result |= CPU_SSE2;
457 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
458 result |= CPU_SSE3;
459 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
460 result |= CPU_SSSE3;
461 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
462 result |= CPU_SSE4_1;
463 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
464 result |= CPU_SSE4_2;
465 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
466 result |= CPU_POPCNT;
467 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
468 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
469 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
470 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
471 result |= CPU_AVX;
472 result |= CPU_VZEROUPPER;
473 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
474 result |= CPU_AVX2;
475 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
476 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
477 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
478 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
479 result |= CPU_AVX512F;
480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
481 result |= CPU_AVX512CD;
482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
483 result |= CPU_AVX512DQ;
484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
485 result |= CPU_AVX512PF;
486 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
487 result |= CPU_AVX512ER;
488 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
489 result |= CPU_AVX512BW;
490 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
491 result |= CPU_AVX512VL;
492 }
493 }
494 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
495 result |= CPU_BMI1;
496 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
497 result |= CPU_TSC;
498 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
499 result |= CPU_TSCINV;
500 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
501 result |= CPU_AES;
502 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
503 result |= CPU_ERMS;
504 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
505 result |= CPU_CLMUL;
506 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
507 result |= CPU_RTM;
508
509 // AMD features.
510 if (is_amd()) {
511 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
512 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
513 result |= CPU_3DNOW_PREFETCH;
514 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
515 result |= CPU_LZCNT;
516 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
517 result |= CPU_SSE4A;
518 }
519 // Intel features.
520 if(is_intel()) {
521 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
522 result |= CPU_ADX;
523 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
524 result |= CPU_BMI2;
525 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
526 result |= CPU_SHA;
527 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
528 result |= CPU_LZCNT;
529 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
530 result |= CPU_FMA;
531 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
532 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
533 result |= CPU_3DNOW_PREFETCH;
534 }
535 }
536
537 return result;
538 }
539
540 static bool os_supports_avx_vectors() {
541 bool retVal = false;
542 if (supports_evex()) {
543 // Verify that OS save/restore all bits of EVEX registers
544 // during signal processing.
545 int nreg = 2 LP64_ONLY(+2);
546 retVal = true;
547 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
548 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
549 retVal = false;
550 break;
551 }
552 }
553 } else if (supports_avx()) {
554 // Verify that OS save/restore all bits of AVX registers
555 // during signal processing.
556 int nreg = 2 LP64_ONLY(+2);
557 retVal = true;
558 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
559 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
560 retVal = false;
561 break;
562 }
563 }
564 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
565 if (retVal == false) {
566 // Verify that OS save/restore all bits of EVEX registers
567 // during signal processing.
568 int nreg = 2 LP64_ONLY(+2);
569 retVal = true;
570 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
571 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
572 retVal = false;
573 break;
574 }
575 }
576 }
577 }
578 return retVal;
579 }
580
581 static void get_processor_features();
582
583 public:
584 // Offsets for cpuid asm stub
585 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
586 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
587 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
588 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
589 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
590 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
591 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
592 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
593 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
594 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
595 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
596 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
597 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
598 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
599
600 // The value used to check ymm register after signal handle
601 static int ymm_test_value() { return 0xCAFEBABE; }
602
603 static void get_cpu_info_wrapper();
604 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
605 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
606 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
607 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
608
609 static void clean_cpuFeatures() { _features = 0; }
610 static void set_avx_cpuFeatures() {
611 _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER );
612 if( is_intel() ) { // Intel cpus specific settings
613 if ((cpu_family() == 0x06) &&
614 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
615 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
616 _features &= ~CPU_VZEROUPPER;
617 }
618 }
619 }
620 static void set_evex_cpuFeatures() {
621 _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER );
622 if( is_intel() ) { // Intel cpus specific settings
623 if ((cpu_family() == 0x06) &&
624 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
625 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
626 _features &= ~CPU_VZEROUPPER;
627 }
628 }
629 }
630
631
632 // Initialization
633 static void initialize();
634
635 // Override Abstract_VM_Version implementation
636 static bool use_biased_locking();
637
638 // Asserts
639 static void assert_is_initialized() {
640 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
641 }
642
643 //
644 // Processor family:
645 // 3 - 386
646 // 4 - 486
647 // 5 - Pentium
648 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
649 // Pentium M, Core Solo, Core Duo, Core2 Duo
650 // family 6 model: 9, 13, 14, 15
651 // 0x0f - Pentium 4, Opteron
652 //
653 // Note: The cpu family should be used to select between
654 // instruction sequences which are valid on all Intel
655 // processors. Use the feature test functions below to
656 // determine whether a particular instruction is supported.
657 //
658 static int cpu_family() { return _cpu;}
659 static bool is_P6() { return cpu_family() >= 6; }
660 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
661 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
662
663 static bool supports_processor_topology() {
664 return (_cpuid_info.std_max_function >= 0xB) &&
665 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
666 // Some cpus have max cpuid >= 0xB but do not support processor topology.
667 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
668 }
669
670 static uint cores_per_cpu() {
671 uint result = 1;
672 if (is_intel()) {
673 bool supports_topology = supports_processor_topology();
674 if (supports_topology) {
675 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
676 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
677 }
678 if (!supports_topology || result == 0) {
679 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
680 }
681 } else if (is_amd()) {
682 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
683 }
684 return result;
685 }
686
687 static uint threads_per_core() {
688 uint result = 1;
689 if (is_intel() && supports_processor_topology()) {
690 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
691 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
692 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
693 cores_per_cpu();
694 }
695 return (result == 0 ? 1 : result);
696 }
697
698 static intx L1_line_size() {
699 intx result = 0;
700 if (is_intel()) {
701 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
702 } else if (is_amd()) {
703 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
704 }
705 if (result < 32) // not defined ?
706 result = 32; // 32 bytes by default on x86 and other x64
707 return result;
708 }
709
710 static intx prefetch_data_size() {
711 return L1_line_size();
712 }
713
714 //
715 // Feature identification
716 //
717 static bool supports_cpuid() { return _features != 0; }
718 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
719 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
720 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
721 static bool supports_ht() { return (_features & CPU_HT) != 0; }
722 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
723 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
724 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
725 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
726 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
727 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
728 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
729 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
730 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
731 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
732 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
733 static bool supports_aes() { return (_features & CPU_AES) != 0; }
734 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
735 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
736 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
737 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
738 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
739 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
740 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
741 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
742 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
743 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
744 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
745 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
746 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
747 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
748 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
749 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
750 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
751 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
752 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
753 static bool supports_fma() { return (_features & CPU_FMA) != 0; }
754 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
755
756 // Intel features
757 static bool is_intel_family_core() { return is_intel() &&
758 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
759
760 static bool is_intel_tsc_synched_at_init() {
761 if (is_intel_family_core()) {
762 uint32_t ext_model = extended_cpu_model();
763 if (ext_model == CPU_MODEL_NEHALEM_EP ||
764 ext_model == CPU_MODEL_WESTMERE_EP ||
765 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
766 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
767 // <= 2-socket invariant tsc support. EX versions are usually used
768 // in > 2-socket systems and likely don't synchronize tscs at
769 // initialization.
770 // Code that uses tsc values must be prepared for them to arbitrarily
771 // jump forward or backward.
772 return true;
773 }
774 }
775 return false;
776 }
777
778 // AMD features
779 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
780 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
781 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
782 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
783
784 static bool is_amd_Barcelona() { return is_amd() &&
785 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
786
787 // Intel and AMD newer cores support fast timestamps well
788 static bool supports_tscinv_bit() {
789 return (_features & CPU_TSCINV) != 0;
790 }
791 static bool supports_tscinv() {
792 return supports_tscinv_bit() &&
793 ( (is_amd() && !is_amd_Barcelona()) ||
794 is_intel_tsc_synched_at_init() );
795 }
796
797 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
798 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
799 supports_sse3() && _model != 0x1C; }
800
801 static bool supports_compare_and_exchange() { return true; }
802
803 static intx allocate_prefetch_distance() {
804 // This method should be called before allocate_prefetch_style().
805 //
806 // Hardware prefetching (distance/size in bytes):
807 // Pentium 3 - 64 / 32
808 // Pentium 4 - 256 / 128
809 // Athlon - 64 / 32 ????
810 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
811 // Core - 128 / 64
812 //
813 // Software prefetching (distance in bytes / instruction with best score):
814 // Pentium 3 - 128 / prefetchnta
815 // Pentium 4 - 512 / prefetchnta
816 // Athlon - 128 / prefetchnta
817 // Opteron - 256 / prefetchnta
818 // Core - 256 / prefetchnta
819 // It will be used only when AllocatePrefetchStyle > 0
820
821 intx count = AllocatePrefetchDistance;
822 if (count < 0) { // default ?
823 if (is_amd()) { // AMD
824 if (supports_sse2())
825 count = 256; // Opteron
826 else
827 count = 128; // Athlon
828 } else { // Intel
829 if (supports_sse2())
830 if (cpu_family() == 6) {
831 count = 256; // Pentium M, Core, Core2
832 } else {
833 count = 512; // Pentium 4
834 }
835 else
836 count = 128; // Pentium 3 (and all other old CPUs)
837 }
838 }
839 return count;
840 }
841 static intx allocate_prefetch_style() {
842 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
843 // Return 0 if AllocatePrefetchDistance was not defined.
844 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
845 }
846
847 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
848 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
849 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
850 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
851
852 // gc copy/scan is disabled if prefetchw isn't supported, because
853 // Prefetch::write emits an inlined prefetchw on Linux.
854 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
855 // The used prefetcht0 instruction works for both amd64 and em64t.
856 static intx prefetch_copy_interval_in_bytes() {
857 intx interval = PrefetchCopyIntervalInBytes;
858 return interval >= 0 ? interval : 576;
859 }
860 static intx prefetch_scan_interval_in_bytes() {
861 intx interval = PrefetchScanIntervalInBytes;
862 return interval >= 0 ? interval : 576;
863 }
864 static intx prefetch_fields_ahead() {
865 intx count = PrefetchFieldsAhead;
866 return count >= 0 ? count : 1;
867 }
868 static uint32_t get_xsave_header_lower_segment() {
869 return _cpuid_info.xem_xcr0_eax.value;
870 }
871 static uint32_t get_xsave_header_upper_segment() {
872 return _cpuid_info.xem_xcr0_edx;
873 }
874
875 // SSE2 and later processors implement a 'pause' instruction
876 // that can be used for efficient implementation of
877 // the intrinsic for java.lang.Thread.onSpinWait()
878 static bool supports_on_spin_wait() { return supports_sse2(); }
879 };
880
881 #endif // CPU_X86_VM_VM_VERSION_X86_HPP