1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [Op_RegI] = NULL;
78 idealreg2spillmask [Op_RegN] = NULL;
79 idealreg2spillmask [Op_RegL] = NULL;
80 idealreg2spillmask [Op_RegF] = NULL;
81 idealreg2spillmask [Op_RegD] = NULL;
82 idealreg2spillmask [Op_RegP] = NULL;
83 idealreg2spillmask [Op_VecS] = NULL;
84 idealreg2spillmask [Op_VecD] = NULL;
85 idealreg2spillmask [Op_VecX] = NULL;
86 idealreg2spillmask [Op_VecY] = NULL;
87 idealreg2spillmask [Op_VecZ] = NULL;
88 idealreg2spillmask [Op_RegFlags] = NULL;
89
90 idealreg2debugmask [Op_RegI] = NULL;
91 idealreg2debugmask [Op_RegN] = NULL;
92 idealreg2debugmask [Op_RegL] = NULL;
93 idealreg2debugmask [Op_RegF] = NULL;
94 idealreg2debugmask [Op_RegD] = NULL;
95 idealreg2debugmask [Op_RegP] = NULL;
96 idealreg2debugmask [Op_VecS] = NULL;
97 idealreg2debugmask [Op_VecD] = NULL;
98 idealreg2debugmask [Op_VecX] = NULL;
99 idealreg2debugmask [Op_VecY] = NULL;
100 idealreg2debugmask [Op_VecZ] = NULL;
101 idealreg2debugmask [Op_RegFlags] = NULL;
102
103 idealreg2mhdebugmask[Op_RegI] = NULL;
104 idealreg2mhdebugmask[Op_RegN] = NULL;
105 idealreg2mhdebugmask[Op_RegL] = NULL;
106 idealreg2mhdebugmask[Op_RegF] = NULL;
107 idealreg2mhdebugmask[Op_RegD] = NULL;
108 idealreg2mhdebugmask[Op_RegP] = NULL;
109 idealreg2mhdebugmask[Op_VecS] = NULL;
110 idealreg2mhdebugmask[Op_VecD] = NULL;
111 idealreg2mhdebugmask[Op_VecX] = NULL;
112 idealreg2mhdebugmask[Op_VecY] = NULL;
113 idealreg2mhdebugmask[Op_VecZ] = NULL;
114 idealreg2mhdebugmask[Op_RegFlags] = NULL;
115
116 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
117 }
118
119 //------------------------------warp_incoming_stk_arg------------------------
120 // This warps a VMReg into an OptoReg::Name
121 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
122 OptoReg::Name warped;
123 if( reg->is_stack() ) { // Stack slot argument?
124 warped = OptoReg::add(_old_SP, reg->reg2stack() );
125 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
126 if( warped >= _in_arg_limit )
127 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
128 if (!RegMask::can_represent_arg(warped)) {
129 // the compiler cannot represent this method's calling sequence
130 C->record_method_not_compilable("unsupported incoming calling sequence");
131 return OptoReg::Bad;
132 }
133 return warped;
134 }
135 return OptoReg::as_OptoReg(reg);
136 }
137
138 //---------------------------compute_old_SP------------------------------------
139 OptoReg::Name Compile::compute_old_SP() {
140 int fixed = fixed_slots();
141 int preserve = in_preserve_stack_slots();
142 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
143 }
144
145
146
147 #ifdef ASSERT
148 void Matcher::verify_new_nodes_only(Node* xroot) {
149 // Make sure that the new graph only references new nodes
150 ResourceMark rm;
151 Unique_Node_List worklist;
152 VectorSet visited(Thread::current()->resource_area());
153 worklist.push(xroot);
154 while (worklist.size() > 0) {
155 Node* n = worklist.pop();
156 visited <<= n->_idx;
157 assert(C->node_arena()->contains(n), "dead node");
158 for (uint j = 0; j < n->req(); j++) {
159 Node* in = n->in(j);
160 if (in != NULL) {
161 assert(C->node_arena()->contains(in), "dead node");
162 if (!visited.test(in->_idx)) {
163 worklist.push(in);
164 }
165 }
166 }
167 }
168 }
169 #endif
170
171
172 //---------------------------match---------------------------------------------
173 void Matcher::match( ) {
174 if( MaxLabelRootDepth < 100 ) { // Too small?
175 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
176 MaxLabelRootDepth = 100;
177 }
178 // One-time initialization of some register masks.
179 init_spill_mask( C->root()->in(1) );
180 _return_addr_mask = return_addr();
181 #ifdef _LP64
182 // Pointers take 2 slots in 64-bit land
183 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
184 #endif
185
186 // Map a Java-signature return type into return register-value
187 // machine registers for 0, 1 and 2 returned values.
188 const TypeTuple *range = C->tf()->range();
189 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
190 // Get ideal-register return type
191 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
192 // Get machine return register
193 uint sop = C->start()->Opcode();
194 OptoRegPair regs = return_value(ireg, false);
195
196 // And mask for same
197 _return_value_mask = RegMask(regs.first());
198 if( OptoReg::is_valid(regs.second()) )
199 _return_value_mask.Insert(regs.second());
200 }
201
202 // ---------------
203 // Frame Layout
204
205 // Need the method signature to determine the incoming argument types,
206 // because the types determine which registers the incoming arguments are
207 // in, and this affects the matched code.
208 const TypeTuple *domain = C->tf()->domain();
209 uint argcnt = domain->cnt() - TypeFunc::Parms;
210 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
211 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
212 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
213 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
214 uint i;
215 for( i = 0; i<argcnt; i++ ) {
216 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
217 }
218
219 // Pass array of ideal registers and length to USER code (from the AD file)
220 // that will convert this to an array of register numbers.
221 const StartNode *start = C->start();
222 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
223 #ifdef ASSERT
224 // Sanity check users' calling convention. Real handy while trying to
225 // get the initial port correct.
226 { for (uint i = 0; i<argcnt; i++) {
227 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
228 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
229 _parm_regs[i].set_bad();
230 continue;
231 }
232 VMReg parm_reg = vm_parm_regs[i].first();
233 assert(parm_reg->is_valid(), "invalid arg?");
234 if (parm_reg->is_reg()) {
235 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
236 assert(can_be_java_arg(opto_parm_reg) ||
237 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
238 opto_parm_reg == inline_cache_reg(),
239 "parameters in register must be preserved by runtime stubs");
240 }
241 for (uint j = 0; j < i; j++) {
242 assert(parm_reg != vm_parm_regs[j].first(),
243 "calling conv. must produce distinct regs");
244 }
245 }
246 }
247 #endif
248
249 // Do some initial frame layout.
250
251 // Compute the old incoming SP (may be called FP) as
252 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
253 _old_SP = C->compute_old_SP();
254 assert( is_even(_old_SP), "must be even" );
255
256 // Compute highest incoming stack argument as
257 // _old_SP + out_preserve_stack_slots + incoming argument size.
258 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
259 assert( is_even(_in_arg_limit), "out_preserve must be even" );
260 for( i = 0; i < argcnt; i++ ) {
261 // Permit args to have no register
262 _calling_convention_mask[i].Clear();
263 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
264 continue;
265 }
266 // calling_convention returns stack arguments as a count of
267 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
268 // the allocators point of view, taking into account all the
269 // preserve area, locks & pad2.
270
271 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
272 if( OptoReg::is_valid(reg1))
273 _calling_convention_mask[i].Insert(reg1);
274
275 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
276 if( OptoReg::is_valid(reg2))
277 _calling_convention_mask[i].Insert(reg2);
278
279 // Saved biased stack-slot register number
280 _parm_regs[i].set_pair(reg2, reg1);
281 }
282
283 // Finally, make sure the incoming arguments take up an even number of
284 // words, in case the arguments or locals need to contain doubleword stack
285 // slots. The rest of the system assumes that stack slot pairs (in
286 // particular, in the spill area) which look aligned will in fact be
287 // aligned relative to the stack pointer in the target machine. Double
288 // stack slots will always be allocated aligned.
289 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
290
291 // Compute highest outgoing stack argument as
292 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
293 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
294 assert( is_even(_out_arg_limit), "out_preserve must be even" );
295
296 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
297 // the compiler cannot represent this method's calling sequence
298 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
299 }
300
301 if (C->failing()) return; // bailed out on incoming arg failure
302
303 // ---------------
304 // Collect roots of matcher trees. Every node for which
305 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
306 // can be a valid interior of some tree.
307 find_shared( C->root() );
308 find_shared( C->top() );
309
310 C->print_method(PHASE_BEFORE_MATCHING);
311
312 // Create new ideal node ConP #NULL even if it does exist in old space
313 // to avoid false sharing if the corresponding mach node is not used.
314 // The corresponding mach node is only used in rare cases for derived
315 // pointers.
316 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
317
318 // Swap out to old-space; emptying new-space
319 Arena *old = C->node_arena()->move_contents(C->old_arena());
320
321 // Save debug and profile information for nodes in old space:
322 _old_node_note_array = C->node_note_array();
323 if (_old_node_note_array != NULL) {
324 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
325 (C->comp_arena(), _old_node_note_array->length(),
326 0, NULL));
327 }
328
329 // Pre-size the new_node table to avoid the need for range checks.
330 grow_new_node_array(C->unique());
331
332 // Reset node counter so MachNodes start with _idx at 0
333 int live_nodes = C->live_nodes();
334 C->set_unique(0);
335 C->reset_dead_node_list();
336
337 // Recursively match trees from old space into new space.
338 // Correct leaves of new-space Nodes; they point to old-space.
339 _visited.Clear(); // Clear visit bits for xform call
340 C->set_cached_top_node(xform( C->top(), live_nodes ));
341 if (!C->failing()) {
342 Node* xroot = xform( C->root(), 1 );
343 if (xroot == NULL) {
344 Matcher::soft_match_failure(); // recursive matching process failed
345 C->record_method_not_compilable("instruction match failed");
346 } else {
347 // During matching shared constants were attached to C->root()
348 // because xroot wasn't available yet, so transfer the uses to
349 // the xroot.
350 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
351 Node* n = C->root()->fast_out(j);
352 if (C->node_arena()->contains(n)) {
353 assert(n->in(0) == C->root(), "should be control user");
354 n->set_req(0, xroot);
355 --j;
356 --jmax;
357 }
358 }
359
360 // Generate new mach node for ConP #NULL
361 assert(new_ideal_null != NULL, "sanity");
362 _mach_null = match_tree(new_ideal_null);
363 // Don't set control, it will confuse GCM since there are no uses.
364 // The control will be set when this node is used first time
365 // in find_base_for_derived().
366 assert(_mach_null != NULL, "");
367
368 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
369
370 #ifdef ASSERT
371 verify_new_nodes_only(xroot);
372 #endif
373 }
374 }
375 if (C->top() == NULL || C->root() == NULL) {
376 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
377 }
378 if (C->failing()) {
379 // delete old;
380 old->destruct_contents();
381 return;
382 }
383 assert( C->top(), "" );
384 assert( C->root(), "" );
385 validate_null_checks();
386
387 // Now smoke old-space
388 NOT_DEBUG( old->destruct_contents() );
389
390 // ------------------------
391 // Set up save-on-entry registers
392 Fixup_Save_On_Entry( );
393 }
394
395
396 //------------------------------Fixup_Save_On_Entry----------------------------
397 // The stated purpose of this routine is to take care of save-on-entry
398 // registers. However, the overall goal of the Match phase is to convert into
399 // machine-specific instructions which have RegMasks to guide allocation.
400 // So what this procedure really does is put a valid RegMask on each input
401 // to the machine-specific variations of all Return, TailCall and Halt
402 // instructions. It also adds edgs to define the save-on-entry values (and of
403 // course gives them a mask).
404
405 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
406 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
407 // Do all the pre-defined register masks
408 rms[TypeFunc::Control ] = RegMask::Empty;
409 rms[TypeFunc::I_O ] = RegMask::Empty;
410 rms[TypeFunc::Memory ] = RegMask::Empty;
411 rms[TypeFunc::ReturnAdr] = ret_adr;
412 rms[TypeFunc::FramePtr ] = fp;
413 return rms;
414 }
415
416 //---------------------------init_first_stack_mask-----------------------------
417 // Create the initial stack mask used by values spilling to the stack.
418 // Disallow any debug info in outgoing argument areas by setting the
419 // initial mask accordingly.
420 void Matcher::init_first_stack_mask() {
421
422 // Allocate storage for spill masks as masks for the appropriate load type.
423 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
424
425 idealreg2spillmask [Op_RegN] = &rms[0];
426 idealreg2spillmask [Op_RegI] = &rms[1];
427 idealreg2spillmask [Op_RegL] = &rms[2];
428 idealreg2spillmask [Op_RegF] = &rms[3];
429 idealreg2spillmask [Op_RegD] = &rms[4];
430 idealreg2spillmask [Op_RegP] = &rms[5];
431
432 idealreg2debugmask [Op_RegN] = &rms[6];
433 idealreg2debugmask [Op_RegI] = &rms[7];
434 idealreg2debugmask [Op_RegL] = &rms[8];
435 idealreg2debugmask [Op_RegF] = &rms[9];
436 idealreg2debugmask [Op_RegD] = &rms[10];
437 idealreg2debugmask [Op_RegP] = &rms[11];
438
439 idealreg2mhdebugmask[Op_RegN] = &rms[12];
440 idealreg2mhdebugmask[Op_RegI] = &rms[13];
441 idealreg2mhdebugmask[Op_RegL] = &rms[14];
442 idealreg2mhdebugmask[Op_RegF] = &rms[15];
443 idealreg2mhdebugmask[Op_RegD] = &rms[16];
444 idealreg2mhdebugmask[Op_RegP] = &rms[17];
445
446 idealreg2spillmask [Op_VecS] = &rms[18];
447 idealreg2spillmask [Op_VecD] = &rms[19];
448 idealreg2spillmask [Op_VecX] = &rms[20];
449 idealreg2spillmask [Op_VecY] = &rms[21];
450 idealreg2spillmask [Op_VecZ] = &rms[22];
451
452 OptoReg::Name i;
453
454 // At first, start with the empty mask
455 C->FIRST_STACK_mask().Clear();
456
457 // Add in the incoming argument area
458 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
459 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
460 C->FIRST_STACK_mask().Insert(i);
461 }
462 // Add in all bits past the outgoing argument area
463 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
464 "must be able to represent all call arguments in reg mask");
465 OptoReg::Name init = _out_arg_limit;
466 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
467 C->FIRST_STACK_mask().Insert(i);
468 }
469 // Finally, set the "infinite stack" bit.
470 C->FIRST_STACK_mask().set_AllStack();
471
472 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
473 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
474 // Keep spill masks aligned.
475 aligned_stack_mask.clear_to_pairs();
476 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
477
478 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
479 #ifdef _LP64
480 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
481 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
482 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
483 #else
484 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
485 #endif
486 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
487 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
488 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
489 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
490 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
491 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
492 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
493 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
494
495 if (Matcher::vector_size_supported(T_BYTE,4)) {
496 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
497 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
498 }
499 if (Matcher::vector_size_supported(T_FLOAT,2)) {
500 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
501 // RA guarantees such alignment since it is needed for Double and Long values.
502 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
503 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
504 }
505 if (Matcher::vector_size_supported(T_FLOAT,4)) {
506 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
507 //
508 // RA can use input arguments stack slots for spills but until RA
509 // we don't know frame size and offset of input arg stack slots.
510 //
511 // Exclude last input arg stack slots to avoid spilling vectors there
512 // otherwise vector spills could stomp over stack slots in caller frame.
513 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
514 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
515 aligned_stack_mask.Remove(in);
516 in = OptoReg::add(in, -1);
517 }
518 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
519 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
520 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
521 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
522 }
523 if (Matcher::vector_size_supported(T_FLOAT,8)) {
524 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
525 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
526 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
527 aligned_stack_mask.Remove(in);
528 in = OptoReg::add(in, -1);
529 }
530 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
531 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
532 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
533 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
534 }
535 if (Matcher::vector_size_supported(T_FLOAT,16)) {
536 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
537 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
538 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
539 aligned_stack_mask.Remove(in);
540 in = OptoReg::add(in, -1);
541 }
542 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
543 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
544 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
545 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
546 }
547 if (UseFPUForSpilling) {
548 // This mask logic assumes that the spill operations are
549 // symmetric and that the registers involved are the same size.
550 // On sparc for instance we may have to use 64 bit moves will
551 // kill 2 registers when used with F0-F31.
552 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
554 #ifdef _LP64
555 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
556 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
557 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
558 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
559 #else
560 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
561 #ifdef ARM
562 // ARM has support for moving 64bit values between a pair of
563 // integer registers and a double register
564 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
565 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
566 #endif
567 #endif
568 }
569
570 // Make up debug masks. Any spill slot plus callee-save registers.
571 // Caller-save registers are assumed to be trashable by the various
572 // inline-cache fixup routines.
573 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
574 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
575 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
576 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
577 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
578 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
579
580 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
581 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
582 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
583 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
584 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
585 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
586
587 // Prevent stub compilations from attempting to reference
588 // callee-saved registers from debug info
589 bool exclude_soe = !Compile::current()->is_method_compilation();
590
591 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
592 // registers the caller has to save do not work
593 if( _register_save_policy[i] == 'C' ||
594 _register_save_policy[i] == 'A' ||
595 (_register_save_policy[i] == 'E' && exclude_soe) ) {
596 idealreg2debugmask [Op_RegN]->Remove(i);
597 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
598 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
599 idealreg2debugmask [Op_RegF]->Remove(i); // masks
600 idealreg2debugmask [Op_RegD]->Remove(i);
601 idealreg2debugmask [Op_RegP]->Remove(i);
602
603 idealreg2mhdebugmask[Op_RegN]->Remove(i);
604 idealreg2mhdebugmask[Op_RegI]->Remove(i);
605 idealreg2mhdebugmask[Op_RegL]->Remove(i);
606 idealreg2mhdebugmask[Op_RegF]->Remove(i);
607 idealreg2mhdebugmask[Op_RegD]->Remove(i);
608 idealreg2mhdebugmask[Op_RegP]->Remove(i);
609 }
610 }
611
612 // Subtract the register we use to save the SP for MethodHandle
613 // invokes to from the debug mask.
614 const RegMask save_mask = method_handle_invoke_SP_save_mask();
615 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
618 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
619 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
620 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
621 }
622
623 //---------------------------is_save_on_entry----------------------------------
624 bool Matcher::is_save_on_entry( int reg ) {
625 return
626 _register_save_policy[reg] == 'E' ||
627 _register_save_policy[reg] == 'A' || // Save-on-entry register?
628 // Also save argument registers in the trampolining stubs
629 (C->save_argument_registers() && is_spillable_arg(reg));
630 }
631
632 //---------------------------Fixup_Save_On_Entry-------------------------------
633 void Matcher::Fixup_Save_On_Entry( ) {
634 init_first_stack_mask();
635
636 Node *root = C->root(); // Short name for root
637 // Count number of save-on-entry registers.
638 uint soe_cnt = number_of_saved_registers();
639 uint i;
640
641 // Find the procedure Start Node
642 StartNode *start = C->start();
643 assert( start, "Expect a start node" );
644
645 // Save argument registers in the trampolining stubs
646 if( C->save_argument_registers() )
647 for( i = 0; i < _last_Mach_Reg; i++ )
648 if( is_spillable_arg(i) )
649 soe_cnt++;
650
651 // Input RegMask array shared by all Returns.
652 // The type for doubles and longs has a count of 2, but
653 // there is only 1 returned value
654 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
655 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
656 // Returns have 0 or 1 returned values depending on call signature.
657 // Return register is specified by return_value in the AD file.
658 if (ret_edge_cnt > TypeFunc::Parms)
659 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
660
661 // Input RegMask array shared by all Rethrows.
662 uint reth_edge_cnt = TypeFunc::Parms+1;
663 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
664 // Rethrow takes exception oop only, but in the argument 0 slot.
665 OptoReg::Name reg = find_receiver(false);
666 if (reg >= 0) {
667 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
668 #ifdef _LP64
669 // Need two slots for ptrs in 64-bit land
670 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
671 #endif
672 }
673
674 // Input RegMask array shared by all TailCalls
675 uint tail_call_edge_cnt = TypeFunc::Parms+2;
676 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
677
678 // Input RegMask array shared by all TailJumps
679 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
680 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
681
682 // TailCalls have 2 returned values (target & moop), whose masks come
683 // from the usual MachNode/MachOper mechanism. Find a sample
684 // TailCall to extract these masks and put the correct masks into
685 // the tail_call_rms array.
686 for( i=1; i < root->req(); i++ ) {
687 MachReturnNode *m = root->in(i)->as_MachReturn();
688 if( m->ideal_Opcode() == Op_TailCall ) {
689 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
690 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
691 break;
692 }
693 }
694
695 // TailJumps have 2 returned values (target & ex_oop), whose masks come
696 // from the usual MachNode/MachOper mechanism. Find a sample
697 // TailJump to extract these masks and put the correct masks into
698 // the tail_jump_rms array.
699 for( i=1; i < root->req(); i++ ) {
700 MachReturnNode *m = root->in(i)->as_MachReturn();
701 if( m->ideal_Opcode() == Op_TailJump ) {
702 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
703 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
704 break;
705 }
706 }
707
708 // Input RegMask array shared by all Halts
709 uint halt_edge_cnt = TypeFunc::Parms;
710 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
711
712 // Capture the return input masks into each exit flavor
713 for( i=1; i < root->req(); i++ ) {
714 MachReturnNode *exit = root->in(i)->as_MachReturn();
715 switch( exit->ideal_Opcode() ) {
716 case Op_Return : exit->_in_rms = ret_rms; break;
717 case Op_Rethrow : exit->_in_rms = reth_rms; break;
718 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
719 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
720 case Op_Halt : exit->_in_rms = halt_rms; break;
721 default : ShouldNotReachHere();
722 }
723 }
724
725 // Next unused projection number from Start.
726 int proj_cnt = C->tf()->domain()->cnt();
727
728 // Do all the save-on-entry registers. Make projections from Start for
729 // them, and give them a use at the exit points. To the allocator, they
730 // look like incoming register arguments.
731 for( i = 0; i < _last_Mach_Reg; i++ ) {
732 if( is_save_on_entry(i) ) {
733
734 // Add the save-on-entry to the mask array
735 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
736 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
737 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
738 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
739 // Halts need the SOE registers, but only in the stack as debug info.
740 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
741 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
742
743 Node *mproj;
744
745 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
746 // into a single RegD.
747 if( (i&1) == 0 &&
748 _register_save_type[i ] == Op_RegF &&
749 _register_save_type[i+1] == Op_RegF &&
750 is_save_on_entry(i+1) ) {
751 // Add other bit for double
752 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
753 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
754 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
755 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
756 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
757 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
758 proj_cnt += 2; // Skip 2 for doubles
759 }
760 else if( (i&1) == 1 && // Else check for high half of double
761 _register_save_type[i-1] == Op_RegF &&
762 _register_save_type[i ] == Op_RegF &&
763 is_save_on_entry(i-1) ) {
764 ret_rms [ ret_edge_cnt] = RegMask::Empty;
765 reth_rms [ reth_edge_cnt] = RegMask::Empty;
766 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
767 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
768 halt_rms [ halt_edge_cnt] = RegMask::Empty;
769 mproj = C->top();
770 }
771 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
772 // into a single RegL.
773 else if( (i&1) == 0 &&
774 _register_save_type[i ] == Op_RegI &&
775 _register_save_type[i+1] == Op_RegI &&
776 is_save_on_entry(i+1) ) {
777 // Add other bit for long
778 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
779 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
780 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
781 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
782 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
783 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
784 proj_cnt += 2; // Skip 2 for longs
785 }
786 else if( (i&1) == 1 && // Else check for high half of long
787 _register_save_type[i-1] == Op_RegI &&
788 _register_save_type[i ] == Op_RegI &&
789 is_save_on_entry(i-1) ) {
790 ret_rms [ ret_edge_cnt] = RegMask::Empty;
791 reth_rms [ reth_edge_cnt] = RegMask::Empty;
792 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
793 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
794 halt_rms [ halt_edge_cnt] = RegMask::Empty;
795 mproj = C->top();
796 } else {
797 // Make a projection for it off the Start
798 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
799 }
800
801 ret_edge_cnt ++;
802 reth_edge_cnt ++;
803 tail_call_edge_cnt ++;
804 tail_jump_edge_cnt ++;
805 halt_edge_cnt ++;
806
807 // Add a use of the SOE register to all exit paths
808 for( uint j=1; j < root->req(); j++ )
809 root->in(j)->add_req(mproj);
810 } // End of if a save-on-entry register
811 } // End of for all machine registers
812 }
813
814 //------------------------------init_spill_mask--------------------------------
815 void Matcher::init_spill_mask( Node *ret ) {
816 if( idealreg2regmask[Op_RegI] ) return; // One time only init
817
818 OptoReg::c_frame_pointer = c_frame_pointer();
819 c_frame_ptr_mask = c_frame_pointer();
820 #ifdef _LP64
821 // pointers are twice as big
822 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
823 #endif
824
825 // Start at OptoReg::stack0()
826 STACK_ONLY_mask.Clear();
827 OptoReg::Name init = OptoReg::stack2reg(0);
828 // STACK_ONLY_mask is all stack bits
829 OptoReg::Name i;
830 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
831 STACK_ONLY_mask.Insert(i);
832 // Also set the "infinite stack" bit.
833 STACK_ONLY_mask.set_AllStack();
834
835 // Copy the register names over into the shared world
836 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
837 // SharedInfo::regName[i] = regName[i];
838 // Handy RegMasks per machine register
839 mreg2regmask[i].Insert(i);
840 }
841
842 // Grab the Frame Pointer
843 Node *fp = ret->in(TypeFunc::FramePtr);
844 Node *mem = ret->in(TypeFunc::Memory);
845 const TypePtr* atp = TypePtr::BOTTOM;
846 // Share frame pointer while making spill ops
847 set_shared(fp);
848
849 // Compute generic short-offset Loads
850 #ifdef _LP64
851 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
852 #endif
853 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
854 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
855 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
856 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
857 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
858 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
859 spillD != NULL && spillP != NULL, "");
860 // Get the ADLC notion of the right regmask, for each basic type.
861 #ifdef _LP64
862 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
863 #endif
864 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
865 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
866 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
867 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
868 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
869
870 // Vector regmasks.
871 if (Matcher::vector_size_supported(T_BYTE,4)) {
872 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
873 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
874 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
875 }
876 if (Matcher::vector_size_supported(T_FLOAT,2)) {
877 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
878 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
879 }
880 if (Matcher::vector_size_supported(T_FLOAT,4)) {
881 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
882 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
883 }
884 if (Matcher::vector_size_supported(T_FLOAT,8)) {
885 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
886 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
887 }
888 if (Matcher::vector_size_supported(T_FLOAT,16)) {
889 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
890 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
891 }
892 }
893
894 #ifdef ASSERT
895 static void match_alias_type(Compile* C, Node* n, Node* m) {
896 if (!VerifyAliases) return; // do not go looking for trouble by default
897 const TypePtr* nat = n->adr_type();
898 const TypePtr* mat = m->adr_type();
899 int nidx = C->get_alias_index(nat);
900 int midx = C->get_alias_index(mat);
901 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
902 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
903 for (uint i = 1; i < n->req(); i++) {
904 Node* n1 = n->in(i);
905 const TypePtr* n1at = n1->adr_type();
906 if (n1at != NULL) {
907 nat = n1at;
908 nidx = C->get_alias_index(n1at);
909 }
910 }
911 }
912 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
913 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
914 switch (n->Opcode()) {
915 case Op_PrefetchAllocation:
916 nidx = Compile::AliasIdxRaw;
917 nat = TypeRawPtr::BOTTOM;
918 break;
919 }
920 }
921 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
922 switch (n->Opcode()) {
923 case Op_ClearArray:
924 midx = Compile::AliasIdxRaw;
925 mat = TypeRawPtr::BOTTOM;
926 break;
927 }
928 }
929 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
930 switch (n->Opcode()) {
931 case Op_Return:
932 case Op_Rethrow:
933 case Op_Halt:
934 case Op_TailCall:
935 case Op_TailJump:
936 nidx = Compile::AliasIdxBot;
937 nat = TypePtr::BOTTOM;
938 break;
939 }
940 }
941 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
942 switch (n->Opcode()) {
943 case Op_StrComp:
944 case Op_StrEquals:
945 case Op_StrIndexOf:
946 case Op_StrIndexOfChar:
947 case Op_AryEq:
948 case Op_HasNegatives:
949 case Op_MemBarVolatile:
950 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
951 case Op_StrInflatedCopy:
952 case Op_StrCompressedCopy:
953 case Op_OnSpinWait:
954 case Op_EncodeISOArray:
955 nidx = Compile::AliasIdxTop;
956 nat = NULL;
957 break;
958 }
959 }
960 if (nidx != midx) {
961 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
962 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
963 n->dump();
964 m->dump();
965 }
966 assert(C->subsume_loads() && C->must_alias(nat, midx),
967 "must not lose alias info when matching");
968 }
969 }
970 #endif
971
972 //------------------------------xform------------------------------------------
973 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
974 // Node in new-space. Given a new-space Node, recursively walk his children.
975 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
976 Node *Matcher::xform( Node *n, int max_stack ) {
977 // Use one stack to keep both: child's node/state and parent's node/index
978 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
979 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
980
981 while (mstack.is_nonempty()) {
982 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
983 if (C->failing()) return NULL;
984 n = mstack.node(); // Leave node on stack
985 Node_State nstate = mstack.state();
986 if (nstate == Visit) {
987 mstack.set_state(Post_Visit);
988 Node *oldn = n;
989 // Old-space or new-space check
990 if (!C->node_arena()->contains(n)) {
991 // Old space!
992 Node* m;
993 if (has_new_node(n)) { // Not yet Label/Reduced
994 m = new_node(n);
995 } else {
996 if (!is_dontcare(n)) { // Matcher can match this guy
997 // Calls match special. They match alone with no children.
998 // Their children, the incoming arguments, match normally.
999 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1000 if (C->failing()) return NULL;
1001 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1002 } else { // Nothing the matcher cares about
1003 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1004 // Convert to machine-dependent projection
1005 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1006 #ifdef ASSERT
1007 _new2old_map.map(m->_idx, n);
1008 #endif
1009 if (m->in(0) != NULL) // m might be top
1010 collect_null_checks(m, n);
1011 } else { // Else just a regular 'ol guy
1012 m = n->clone(); // So just clone into new-space
1013 #ifdef ASSERT
1014 _new2old_map.map(m->_idx, n);
1015 #endif
1016 // Def-Use edges will be added incrementally as Uses
1017 // of this node are matched.
1018 assert(m->outcnt() == 0, "no Uses of this clone yet");
1019 }
1020 }
1021
1022 set_new_node(n, m); // Map old to new
1023 if (_old_node_note_array != NULL) {
1024 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1025 n->_idx);
1026 C->set_node_notes_at(m->_idx, nn);
1027 }
1028 debug_only(match_alias_type(C, n, m));
1029 }
1030 n = m; // n is now a new-space node
1031 mstack.set_node(n);
1032 }
1033
1034 // New space!
1035 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1036
1037 int i;
1038 // Put precedence edges on stack first (match them last).
1039 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1040 Node *m = oldn->in(i);
1041 if (m == NULL) break;
1042 // set -1 to call add_prec() instead of set_req() during Step1
1043 mstack.push(m, Visit, n, -1);
1044 }
1045
1046 // Handle precedence edges for interior nodes
1047 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1048 Node *m = n->in(i);
1049 if (m == NULL || C->node_arena()->contains(m)) continue;
1050 n->rm_prec(i);
1051 // set -1 to call add_prec() instead of set_req() during Step1
1052 mstack.push(m, Visit, n, -1);
1053 }
1054
1055 // For constant debug info, I'd rather have unmatched constants.
1056 int cnt = n->req();
1057 JVMState* jvms = n->jvms();
1058 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1059
1060 // Now do only debug info. Clone constants rather than matching.
1061 // Constants are represented directly in the debug info without
1062 // the need for executable machine instructions.
1063 // Monitor boxes are also represented directly.
1064 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1065 Node *m = n->in(i); // Get input
1066 int op = m->Opcode();
1067 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1068 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1069 op == Op_ConF || op == Op_ConD || op == Op_ConL
1070 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1071 ) {
1072 m = m->clone();
1073 #ifdef ASSERT
1074 _new2old_map.map(m->_idx, n);
1075 #endif
1076 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1077 mstack.push(m->in(0), Visit, m, 0);
1078 } else {
1079 mstack.push(m, Visit, n, i);
1080 }
1081 }
1082
1083 // And now walk his children, and convert his inputs to new-space.
1084 for( ; i >= 0; --i ) { // For all normal inputs do
1085 Node *m = n->in(i); // Get input
1086 if(m != NULL)
1087 mstack.push(m, Visit, n, i);
1088 }
1089
1090 }
1091 else if (nstate == Post_Visit) {
1092 // Set xformed input
1093 Node *p = mstack.parent();
1094 if (p != NULL) { // root doesn't have parent
1095 int i = (int)mstack.index();
1096 if (i >= 0)
1097 p->set_req(i, n); // required input
1098 else if (i == -1)
1099 p->add_prec(n); // precedence input
1100 else
1101 ShouldNotReachHere();
1102 }
1103 mstack.pop(); // remove processed node from stack
1104 }
1105 else {
1106 ShouldNotReachHere();
1107 }
1108 } // while (mstack.is_nonempty())
1109 return n; // Return new-space Node
1110 }
1111
1112 //------------------------------warp_outgoing_stk_arg------------------------
1113 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1114 // Convert outgoing argument location to a pre-biased stack offset
1115 if (reg->is_stack()) {
1116 OptoReg::Name warped = reg->reg2stack();
1117 // Adjust the stack slot offset to be the register number used
1118 // by the allocator.
1119 warped = OptoReg::add(begin_out_arg_area, warped);
1120 // Keep track of the largest numbered stack slot used for an arg.
1121 // Largest used slot per call-site indicates the amount of stack
1122 // that is killed by the call.
1123 if( warped >= out_arg_limit_per_call )
1124 out_arg_limit_per_call = OptoReg::add(warped,1);
1125 if (!RegMask::can_represent_arg(warped)) {
1126 C->record_method_not_compilable("unsupported calling sequence");
1127 return OptoReg::Bad;
1128 }
1129 return warped;
1130 }
1131 return OptoReg::as_OptoReg(reg);
1132 }
1133
1134
1135 //------------------------------match_sfpt-------------------------------------
1136 // Helper function to match call instructions. Calls match special.
1137 // They match alone with no children. Their children, the incoming
1138 // arguments, match normally.
1139 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1140 MachSafePointNode *msfpt = NULL;
1141 MachCallNode *mcall = NULL;
1142 uint cnt;
1143 // Split out case for SafePoint vs Call
1144 CallNode *call;
1145 const TypeTuple *domain;
1146 ciMethod* method = NULL;
1147 bool is_method_handle_invoke = false; // for special kill effects
1148 if( sfpt->is_Call() ) {
1149 call = sfpt->as_Call();
1150 domain = call->tf()->domain();
1151 cnt = domain->cnt();
1152
1153 // Match just the call, nothing else
1154 MachNode *m = match_tree(call);
1155 if (C->failing()) return NULL;
1156 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1157
1158 // Copy data from the Ideal SafePoint to the machine version
1159 mcall = m->as_MachCall();
1160
1161 mcall->set_tf( call->tf());
1162 mcall->set_entry_point(call->entry_point());
1163 mcall->set_cnt( call->cnt());
1164
1165 if( mcall->is_MachCallJava() ) {
1166 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1167 const CallJavaNode *call_java = call->as_CallJava();
1168 method = call_java->method();
1169 mcall_java->_method = method;
1170 mcall_java->_bci = call_java->_bci;
1171 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1172 is_method_handle_invoke = call_java->is_method_handle_invoke();
1173 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1174 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1175 if (is_method_handle_invoke) {
1176 C->set_has_method_handle_invokes(true);
1177 }
1178 if( mcall_java->is_MachCallStaticJava() )
1179 mcall_java->as_MachCallStaticJava()->_name =
1180 call_java->as_CallStaticJava()->_name;
1181 if( mcall_java->is_MachCallDynamicJava() )
1182 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1183 call_java->as_CallDynamicJava()->_vtable_index;
1184 }
1185 else if( mcall->is_MachCallRuntime() ) {
1186 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1187 }
1188 msfpt = mcall;
1189 }
1190 // This is a non-call safepoint
1191 else {
1192 call = NULL;
1193 domain = NULL;
1194 MachNode *mn = match_tree(sfpt);
1195 if (C->failing()) return NULL;
1196 msfpt = mn->as_MachSafePoint();
1197 cnt = TypeFunc::Parms;
1198 }
1199
1200 // Advertise the correct memory effects (for anti-dependence computation).
1201 msfpt->set_adr_type(sfpt->adr_type());
1202
1203 // Allocate a private array of RegMasks. These RegMasks are not shared.
1204 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1205 // Empty them all.
1206 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1207
1208 // Do all the pre-defined non-Empty register masks
1209 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1210 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1211
1212 // Place first outgoing argument can possibly be put.
1213 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1214 assert( is_even(begin_out_arg_area), "" );
1215 // Compute max outgoing register number per call site.
1216 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1217 // Calls to C may hammer extra stack slots above and beyond any arguments.
1218 // These are usually backing store for register arguments for varargs.
1219 if( call != NULL && call->is_CallRuntime() )
1220 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1221
1222
1223 // Do the normal argument list (parameters) register masks
1224 int argcnt = cnt - TypeFunc::Parms;
1225 if( argcnt > 0 ) { // Skip it all if we have no args
1226 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1227 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1228 int i;
1229 for( i = 0; i < argcnt; i++ ) {
1230 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1231 }
1232 // V-call to pick proper calling convention
1233 call->calling_convention( sig_bt, parm_regs, argcnt );
1234
1235 #ifdef ASSERT
1236 // Sanity check users' calling convention. Really handy during
1237 // the initial porting effort. Fairly expensive otherwise.
1238 { for (int i = 0; i<argcnt; i++) {
1239 if( !parm_regs[i].first()->is_valid() &&
1240 !parm_regs[i].second()->is_valid() ) continue;
1241 VMReg reg1 = parm_regs[i].first();
1242 VMReg reg2 = parm_regs[i].second();
1243 for (int j = 0; j < i; j++) {
1244 if( !parm_regs[j].first()->is_valid() &&
1245 !parm_regs[j].second()->is_valid() ) continue;
1246 VMReg reg3 = parm_regs[j].first();
1247 VMReg reg4 = parm_regs[j].second();
1248 if( !reg1->is_valid() ) {
1249 assert( !reg2->is_valid(), "valid halvsies" );
1250 } else if( !reg3->is_valid() ) {
1251 assert( !reg4->is_valid(), "valid halvsies" );
1252 } else {
1253 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1254 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1255 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1256 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1257 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1258 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1259 }
1260 }
1261 }
1262 }
1263 #endif
1264
1265 // Visit each argument. Compute its outgoing register mask.
1266 // Return results now can have 2 bits returned.
1267 // Compute max over all outgoing arguments both per call-site
1268 // and over the entire method.
1269 for( i = 0; i < argcnt; i++ ) {
1270 // Address of incoming argument mask to fill in
1271 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1272 if( !parm_regs[i].first()->is_valid() &&
1273 !parm_regs[i].second()->is_valid() ) {
1274 continue; // Avoid Halves
1275 }
1276 // Grab first register, adjust stack slots and insert in mask.
1277 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1278 if (OptoReg::is_valid(reg1))
1279 rm->Insert( reg1 );
1280 // Grab second register (if any), adjust stack slots and insert in mask.
1281 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1282 if (OptoReg::is_valid(reg2))
1283 rm->Insert( reg2 );
1284 } // End of for all arguments
1285
1286 // Compute number of stack slots needed to restore stack in case of
1287 // Pascal-style argument popping.
1288 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1289 }
1290
1291 // Compute the max stack slot killed by any call. These will not be
1292 // available for debug info, and will be used to adjust FIRST_STACK_mask
1293 // after all call sites have been visited.
1294 if( _out_arg_limit < out_arg_limit_per_call)
1295 _out_arg_limit = out_arg_limit_per_call;
1296
1297 if (mcall) {
1298 // Kill the outgoing argument area, including any non-argument holes and
1299 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1300 // Since the max-per-method covers the max-per-call-site and debug info
1301 // is excluded on the max-per-method basis, debug info cannot land in
1302 // this killed area.
1303 uint r_cnt = mcall->tf()->range()->cnt();
1304 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1305 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1306 C->record_method_not_compilable("unsupported outgoing calling sequence");
1307 } else {
1308 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1309 proj->_rout.Insert(OptoReg::Name(i));
1310 }
1311 if (proj->_rout.is_NotEmpty()) {
1312 push_projection(proj);
1313 }
1314 }
1315 // Transfer the safepoint information from the call to the mcall
1316 // Move the JVMState list
1317 msfpt->set_jvms(sfpt->jvms());
1318 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1319 jvms->set_map(sfpt);
1320 }
1321
1322 // Debug inputs begin just after the last incoming parameter
1323 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1324 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1325
1326 // Move the OopMap
1327 msfpt->_oop_map = sfpt->_oop_map;
1328
1329 // Add additional edges.
1330 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1331 // For these calls we can not add MachConstantBase in expand(), as the
1332 // ins are not complete then.
1333 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1334 if (msfpt->jvms() &&
1335 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1336 // We added an edge before jvms, so we must adapt the position of the ins.
1337 msfpt->jvms()->adapt_position(+1);
1338 }
1339 }
1340
1341 // Registers killed by the call are set in the local scheduling pass
1342 // of Global Code Motion.
1343 return msfpt;
1344 }
1345
1346 //---------------------------match_tree----------------------------------------
1347 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1348 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1349 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1350 // a Load's result RegMask for memoization in idealreg2regmask[]
1351 MachNode *Matcher::match_tree( const Node *n ) {
1352 assert( n->Opcode() != Op_Phi, "cannot match" );
1353 assert( !n->is_block_start(), "cannot match" );
1354 // Set the mark for all locally allocated State objects.
1355 // When this call returns, the _states_arena arena will be reset
1356 // freeing all State objects.
1357 ResourceMark rm( &_states_arena );
1358
1359 LabelRootDepth = 0;
1360
1361 // StoreNodes require their Memory input to match any LoadNodes
1362 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1363 #ifdef ASSERT
1364 Node* save_mem_node = _mem_node;
1365 _mem_node = n->is_Store() ? (Node*)n : NULL;
1366 #endif
1367 // State object for root node of match tree
1368 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1369 State *s = new (&_states_arena) State;
1370 s->_kids[0] = NULL;
1371 s->_kids[1] = NULL;
1372 s->_leaf = (Node*)n;
1373 // Label the input tree, allocating labels from top-level arena
1374 Label_Root( n, s, n->in(0), mem );
1375 if (C->failing()) return NULL;
1376
1377 // The minimum cost match for the whole tree is found at the root State
1378 uint mincost = max_juint;
1379 uint cost = max_juint;
1380 uint i;
1381 for( i = 0; i < NUM_OPERANDS; i++ ) {
1382 if( s->valid(i) && // valid entry and
1383 s->_cost[i] < cost && // low cost and
1384 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1385 cost = s->_cost[mincost=i];
1386 }
1387 if (mincost == max_juint) {
1388 #ifndef PRODUCT
1389 tty->print("No matching rule for:");
1390 s->dump();
1391 #endif
1392 Matcher::soft_match_failure();
1393 return NULL;
1394 }
1395 // Reduce input tree based upon the state labels to machine Nodes
1396 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1397 #ifdef ASSERT
1398 _old2new_map.map(n->_idx, m);
1399 _new2old_map.map(m->_idx, (Node*)n);
1400 #endif
1401
1402 // Add any Matcher-ignored edges
1403 uint cnt = n->req();
1404 uint start = 1;
1405 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1406 if( n->is_AddP() ) {
1407 assert( mem == (Node*)1, "" );
1408 start = AddPNode::Base+1;
1409 }
1410 for( i = start; i < cnt; i++ ) {
1411 if( !n->match_edge(i) ) {
1412 if( i < m->req() )
1413 m->ins_req( i, n->in(i) );
1414 else
1415 m->add_req( n->in(i) );
1416 }
1417 }
1418
1419 debug_only( _mem_node = save_mem_node; )
1420 return m;
1421 }
1422
1423
1424 //------------------------------match_into_reg---------------------------------
1425 // Choose to either match this Node in a register or part of the current
1426 // match tree. Return true for requiring a register and false for matching
1427 // as part of the current match tree.
1428 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1429
1430 const Type *t = m->bottom_type();
1431
1432 if (t->singleton()) {
1433 // Never force constants into registers. Allow them to match as
1434 // constants or registers. Copies of the same value will share
1435 // the same register. See find_shared_node.
1436 return false;
1437 } else { // Not a constant
1438 // Stop recursion if they have different Controls.
1439 Node* m_control = m->in(0);
1440 // Control of load's memory can post-dominates load's control.
1441 // So use it since load can't float above its memory.
1442 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1443 if (control && m_control && control != m_control && control != mem_control) {
1444
1445 // Actually, we can live with the most conservative control we
1446 // find, if it post-dominates the others. This allows us to
1447 // pick up load/op/store trees where the load can float a little
1448 // above the store.
1449 Node *x = control;
1450 const uint max_scan = 6; // Arbitrary scan cutoff
1451 uint j;
1452 for (j=0; j<max_scan; j++) {
1453 if (x->is_Region()) // Bail out at merge points
1454 return true;
1455 x = x->in(0);
1456 if (x == m_control) // Does 'control' post-dominate
1457 break; // m->in(0)? If so, we can use it
1458 if (x == mem_control) // Does 'control' post-dominate
1459 break; // mem_control? If so, we can use it
1460 }
1461 if (j == max_scan) // No post-domination before scan end?
1462 return true; // Then break the match tree up
1463 }
1464 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1465 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1466 // These are commonly used in address expressions and can
1467 // efficiently fold into them on X64 in some cases.
1468 return false;
1469 }
1470 }
1471
1472 // Not forceable cloning. If shared, put it into a register.
1473 return shared;
1474 }
1475
1476
1477 //------------------------------Instruction Selection--------------------------
1478 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1479 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1480 // things the Matcher does not match (e.g., Memory), and things with different
1481 // Controls (hence forced into different blocks). We pass in the Control
1482 // selected for this entire State tree.
1483
1484 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1485 // Store and the Load must have identical Memories (as well as identical
1486 // pointers). Since the Matcher does not have anything for Memory (and
1487 // does not handle DAGs), I have to match the Memory input myself. If the
1488 // Tree root is a Store, I require all Loads to have the identical memory.
1489 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1490 // Since Label_Root is a recursive function, its possible that we might run
1491 // out of stack space. See bugs 6272980 & 6227033 for more info.
1492 LabelRootDepth++;
1493 if (LabelRootDepth > MaxLabelRootDepth) {
1494 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1495 return NULL;
1496 }
1497 uint care = 0; // Edges matcher cares about
1498 uint cnt = n->req();
1499 uint i = 0;
1500
1501 // Examine children for memory state
1502 // Can only subsume a child into your match-tree if that child's memory state
1503 // is not modified along the path to another input.
1504 // It is unsafe even if the other inputs are separate roots.
1505 Node *input_mem = NULL;
1506 for( i = 1; i < cnt; i++ ) {
1507 if( !n->match_edge(i) ) continue;
1508 Node *m = n->in(i); // Get ith input
1509 assert( m, "expect non-null children" );
1510 if( m->is_Load() ) {
1511 if( input_mem == NULL ) {
1512 input_mem = m->in(MemNode::Memory);
1513 } else if( input_mem != m->in(MemNode::Memory) ) {
1514 input_mem = NodeSentinel;
1515 }
1516 }
1517 }
1518
1519 for( i = 1; i < cnt; i++ ){// For my children
1520 if( !n->match_edge(i) ) continue;
1521 Node *m = n->in(i); // Get ith input
1522 // Allocate states out of a private arena
1523 State *s = new (&_states_arena) State;
1524 svec->_kids[care++] = s;
1525 assert( care <= 2, "binary only for now" );
1526
1527 // Recursively label the State tree.
1528 s->_kids[0] = NULL;
1529 s->_kids[1] = NULL;
1530 s->_leaf = m;
1531
1532 // Check for leaves of the State Tree; things that cannot be a part of
1533 // the current tree. If it finds any, that value is matched as a
1534 // register operand. If not, then the normal matching is used.
1535 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1536 //
1537 // Stop recursion if this is LoadNode and the root of this tree is a
1538 // StoreNode and the load & store have different memories.
1539 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1540 // Can NOT include the match of a subtree when its memory state
1541 // is used by any of the other subtrees
1542 (input_mem == NodeSentinel) ) {
1543 // Print when we exclude matching due to different memory states at input-loads
1544 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1545 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1546 tty->print_cr("invalid input_mem");
1547 }
1548 // Switch to a register-only opcode; this value must be in a register
1549 // and cannot be subsumed as part of a larger instruction.
1550 s->DFA( m->ideal_reg(), m );
1551
1552 } else {
1553 // If match tree has no control and we do, adopt it for entire tree
1554 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1555 control = m->in(0); // Pick up control
1556 // Else match as a normal part of the match tree.
1557 control = Label_Root(m,s,control,mem);
1558 if (C->failing()) return NULL;
1559 }
1560 }
1561
1562
1563 // Call DFA to match this node, and return
1564 svec->DFA( n->Opcode(), n );
1565
1566 #ifdef ASSERT
1567 uint x;
1568 for( x = 0; x < _LAST_MACH_OPER; x++ )
1569 if( svec->valid(x) )
1570 break;
1571
1572 if (x >= _LAST_MACH_OPER) {
1573 n->dump();
1574 svec->dump();
1575 assert( false, "bad AD file" );
1576 }
1577 #endif
1578 return control;
1579 }
1580
1581
1582 // Con nodes reduced using the same rule can share their MachNode
1583 // which reduces the number of copies of a constant in the final
1584 // program. The register allocator is free to split uses later to
1585 // split live ranges.
1586 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1587 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1588
1589 // See if this Con has already been reduced using this rule.
1590 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1591 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1592 if (last != NULL && rule == last->rule()) {
1593 // Don't expect control change for DecodeN
1594 if (leaf->is_DecodeNarrowPtr())
1595 return last;
1596 // Get the new space root.
1597 Node* xroot = new_node(C->root());
1598 if (xroot == NULL) {
1599 // This shouldn't happen give the order of matching.
1600 return NULL;
1601 }
1602
1603 // Shared constants need to have their control be root so they
1604 // can be scheduled properly.
1605 Node* control = last->in(0);
1606 if (control != xroot) {
1607 if (control == NULL || control == C->root()) {
1608 last->set_req(0, xroot);
1609 } else {
1610 assert(false, "unexpected control");
1611 return NULL;
1612 }
1613 }
1614 return last;
1615 }
1616 return NULL;
1617 }
1618
1619
1620 //------------------------------ReduceInst-------------------------------------
1621 // Reduce a State tree (with given Control) into a tree of MachNodes.
1622 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1623 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1624 // Each MachNode has a number of complicated MachOper operands; each
1625 // MachOper also covers a further tree of Ideal Nodes.
1626
1627 // The root of the Ideal match tree is always an instruction, so we enter
1628 // the recursion here. After building the MachNode, we need to recurse
1629 // the tree checking for these cases:
1630 // (1) Child is an instruction -
1631 // Build the instruction (recursively), add it as an edge.
1632 // Build a simple operand (register) to hold the result of the instruction.
1633 // (2) Child is an interior part of an instruction -
1634 // Skip over it (do nothing)
1635 // (3) Child is the start of a operand -
1636 // Build the operand, place it inside the instruction
1637 // Call ReduceOper.
1638 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1639 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1640
1641 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1642 if (shared_node != NULL) {
1643 return shared_node;
1644 }
1645
1646 // Build the object to represent this state & prepare for recursive calls
1647 MachNode *mach = s->MachNodeGenerator(rule);
1648 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1649 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1650 Node *leaf = s->_leaf;
1651 // Check for instruction or instruction chain rule
1652 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1653 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1654 "duplicating node that's already been matched");
1655 // Instruction
1656 mach->add_req( leaf->in(0) ); // Set initial control
1657 // Reduce interior of complex instruction
1658 ReduceInst_Interior( s, rule, mem, mach, 1 );
1659 } else {
1660 // Instruction chain rules are data-dependent on their inputs
1661 mach->add_req(0); // Set initial control to none
1662 ReduceInst_Chain_Rule( s, rule, mem, mach );
1663 }
1664
1665 // If a Memory was used, insert a Memory edge
1666 if( mem != (Node*)1 ) {
1667 mach->ins_req(MemNode::Memory,mem);
1668 #ifdef ASSERT
1669 // Verify adr type after matching memory operation
1670 const MachOper* oper = mach->memory_operand();
1671 if (oper != NULL && oper != (MachOper*)-1) {
1672 // It has a unique memory operand. Find corresponding ideal mem node.
1673 Node* m = NULL;
1674 if (leaf->is_Mem()) {
1675 m = leaf;
1676 } else {
1677 m = _mem_node;
1678 assert(m != NULL && m->is_Mem(), "expecting memory node");
1679 }
1680 const Type* mach_at = mach->adr_type();
1681 // DecodeN node consumed by an address may have different type
1682 // then its input. Don't compare types for such case.
1683 if (m->adr_type() != mach_at &&
1684 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1685 m->in(MemNode::Address)->is_AddP() &&
1686 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1687 m->in(MemNode::Address)->is_AddP() &&
1688 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1689 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1690 mach_at = m->adr_type();
1691 }
1692 if (m->adr_type() != mach_at) {
1693 m->dump();
1694 tty->print_cr("mach:");
1695 mach->dump(1);
1696 }
1697 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1698 }
1699 #endif
1700 }
1701
1702 // If the _leaf is an AddP, insert the base edge
1703 if (leaf->is_AddP()) {
1704 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1705 }
1706
1707 uint number_of_projections_prior = number_of_projections();
1708
1709 // Perform any 1-to-many expansions required
1710 MachNode *ex = mach->Expand(s, _projection_list, mem);
1711 if (ex != mach) {
1712 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1713 if( ex->in(1)->is_Con() )
1714 ex->in(1)->set_req(0, C->root());
1715 // Remove old node from the graph
1716 for( uint i=0; i<mach->req(); i++ ) {
1717 mach->set_req(i,NULL);
1718 }
1719 #ifdef ASSERT
1720 _new2old_map.map(ex->_idx, s->_leaf);
1721 #endif
1722 }
1723
1724 // PhaseChaitin::fixup_spills will sometimes generate spill code
1725 // via the matcher. By the time, nodes have been wired into the CFG,
1726 // and any further nodes generated by expand rules will be left hanging
1727 // in space, and will not get emitted as output code. Catch this.
1728 // Also, catch any new register allocation constraints ("projections")
1729 // generated belatedly during spill code generation.
1730 if (_allocation_started) {
1731 guarantee(ex == mach, "no expand rules during spill generation");
1732 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1733 }
1734
1735 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1736 // Record the con for sharing
1737 _shared_nodes.map(leaf->_idx, ex);
1738 }
1739
1740 return ex;
1741 }
1742
1743 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1744 for (uint i = n->req(); i < n->len(); i++) {
1745 if (n->in(i) != NULL) {
1746 mach->add_prec(n->in(i));
1747 }
1748 }
1749 }
1750
1751 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1752 // 'op' is what I am expecting to receive
1753 int op = _leftOp[rule];
1754 // Operand type to catch childs result
1755 // This is what my child will give me.
1756 int opnd_class_instance = s->_rule[op];
1757 // Choose between operand class or not.
1758 // This is what I will receive.
1759 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1760 // New rule for child. Chase operand classes to get the actual rule.
1761 int newrule = s->_rule[catch_op];
1762
1763 if( newrule < NUM_OPERANDS ) {
1764 // Chain from operand or operand class, may be output of shared node
1765 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1766 "Bad AD file: Instruction chain rule must chain from operand");
1767 // Insert operand into array of operands for this instruction
1768 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1769
1770 ReduceOper( s, newrule, mem, mach );
1771 } else {
1772 // Chain from the result of an instruction
1773 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1774 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1775 Node *mem1 = (Node*)1;
1776 debug_only(Node *save_mem_node = _mem_node;)
1777 mach->add_req( ReduceInst(s, newrule, mem1) );
1778 debug_only(_mem_node = save_mem_node;)
1779 }
1780 return;
1781 }
1782
1783
1784 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1785 handle_precedence_edges(s->_leaf, mach);
1786
1787 if( s->_leaf->is_Load() ) {
1788 Node *mem2 = s->_leaf->in(MemNode::Memory);
1789 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1790 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1791 mem = mem2;
1792 }
1793 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1794 if( mach->in(0) == NULL )
1795 mach->set_req(0, s->_leaf->in(0));
1796 }
1797
1798 // Now recursively walk the state tree & add operand list.
1799 for( uint i=0; i<2; i++ ) { // binary tree
1800 State *newstate = s->_kids[i];
1801 if( newstate == NULL ) break; // Might only have 1 child
1802 // 'op' is what I am expecting to receive
1803 int op;
1804 if( i == 0 ) {
1805 op = _leftOp[rule];
1806 } else {
1807 op = _rightOp[rule];
1808 }
1809 // Operand type to catch childs result
1810 // This is what my child will give me.
1811 int opnd_class_instance = newstate->_rule[op];
1812 // Choose between operand class or not.
1813 // This is what I will receive.
1814 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1815 // New rule for child. Chase operand classes to get the actual rule.
1816 int newrule = newstate->_rule[catch_op];
1817
1818 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1819 // Operand/operandClass
1820 // Insert operand into array of operands for this instruction
1821 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1822 ReduceOper( newstate, newrule, mem, mach );
1823
1824 } else { // Child is internal operand or new instruction
1825 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1826 // internal operand --> call ReduceInst_Interior
1827 // Interior of complex instruction. Do nothing but recurse.
1828 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1829 } else {
1830 // instruction --> call build operand( ) to catch result
1831 // --> ReduceInst( newrule )
1832 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1833 Node *mem1 = (Node*)1;
1834 debug_only(Node *save_mem_node = _mem_node;)
1835 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1836 debug_only(_mem_node = save_mem_node;)
1837 }
1838 }
1839 assert( mach->_opnds[num_opnds-1], "" );
1840 }
1841 return num_opnds;
1842 }
1843
1844 // This routine walks the interior of possible complex operands.
1845 // At each point we check our children in the match tree:
1846 // (1) No children -
1847 // We are a leaf; add _leaf field as an input to the MachNode
1848 // (2) Child is an internal operand -
1849 // Skip over it ( do nothing )
1850 // (3) Child is an instruction -
1851 // Call ReduceInst recursively and
1852 // and instruction as an input to the MachNode
1853 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1854 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1855 State *kid = s->_kids[0];
1856 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1857
1858 // Leaf? And not subsumed?
1859 if( kid == NULL && !_swallowed[rule] ) {
1860 mach->add_req( s->_leaf ); // Add leaf pointer
1861 return; // Bail out
1862 }
1863
1864 if( s->_leaf->is_Load() ) {
1865 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1866 mem = s->_leaf->in(MemNode::Memory);
1867 debug_only(_mem_node = s->_leaf;)
1868 }
1869
1870 handle_precedence_edges(s->_leaf, mach);
1871
1872 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1873 if( !mach->in(0) )
1874 mach->set_req(0,s->_leaf->in(0));
1875 else {
1876 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1877 }
1878 }
1879
1880 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1881 int newrule;
1882 if( i == 0)
1883 newrule = kid->_rule[_leftOp[rule]];
1884 else
1885 newrule = kid->_rule[_rightOp[rule]];
1886
1887 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1888 // Internal operand; recurse but do nothing else
1889 ReduceOper( kid, newrule, mem, mach );
1890
1891 } else { // Child is a new instruction
1892 // Reduce the instruction, and add a direct pointer from this
1893 // machine instruction to the newly reduced one.
1894 Node *mem1 = (Node*)1;
1895 debug_only(Node *save_mem_node = _mem_node;)
1896 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1897 debug_only(_mem_node = save_mem_node;)
1898 }
1899 }
1900 }
1901
1902
1903 // -------------------------------------------------------------------------
1904 // Java-Java calling convention
1905 // (what you use when Java calls Java)
1906
1907 //------------------------------find_receiver----------------------------------
1908 // For a given signature, return the OptoReg for parameter 0.
1909 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1910 VMRegPair regs;
1911 BasicType sig_bt = T_OBJECT;
1912 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1913 // Return argument 0 register. In the LP64 build pointers
1914 // take 2 registers, but the VM wants only the 'main' name.
1915 return OptoReg::as_OptoReg(regs.first());
1916 }
1917
1918 // This function identifies sub-graphs in which a 'load' node is
1919 // input to two different nodes, and such that it can be matched
1920 // with BMI instructions like blsi, blsr, etc.
1921 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1922 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1923 // refers to the same node.
1924 #ifdef X86
1925 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1926 // This is a temporary solution until we make DAGs expressible in ADL.
1927 template<typename ConType>
1928 class FusedPatternMatcher {
1929 Node* _op1_node;
1930 Node* _mop_node;
1931 int _con_op;
1932
1933 static int match_next(Node* n, int next_op, int next_op_idx) {
1934 if (n->in(1) == NULL || n->in(2) == NULL) {
1935 return -1;
1936 }
1937
1938 if (next_op_idx == -1) { // n is commutative, try rotations
1939 if (n->in(1)->Opcode() == next_op) {
1940 return 1;
1941 } else if (n->in(2)->Opcode() == next_op) {
1942 return 2;
1943 }
1944 } else {
1945 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1946 if (n->in(next_op_idx)->Opcode() == next_op) {
1947 return next_op_idx;
1948 }
1949 }
1950 return -1;
1951 }
1952 public:
1953 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1954 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1955
1956 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1957 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1958 typename ConType::NativeType con_value) {
1959 if (_op1_node->Opcode() != op1) {
1960 return false;
1961 }
1962 if (_mop_node->outcnt() > 2) {
1963 return false;
1964 }
1965 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1966 if (op1_op2_idx == -1) {
1967 return false;
1968 }
1969 // Memory operation must be the other edge
1970 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1971
1972 // Check that the mop node is really what we want
1973 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1974 Node *op2_node = _op1_node->in(op1_op2_idx);
1975 if (op2_node->outcnt() > 1) {
1976 return false;
1977 }
1978 assert(op2_node->Opcode() == op2, "Should be");
1979 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1980 if (op2_con_idx == -1) {
1981 return false;
1982 }
1983 // Memory operation must be the other edge
1984 int op2_mop_idx = (op2_con_idx & 1) + 1;
1985 // Check that the memory operation is the same node
1986 if (op2_node->in(op2_mop_idx) == _mop_node) {
1987 // Now check the constant
1988 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1989 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1990 return true;
1991 }
1992 }
1993 }
1994 return false;
1995 }
1996 };
1997
1998
1999 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2000 if (n != NULL && m != NULL) {
2001 if (m->Opcode() == Op_LoadI) {
2002 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2003 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2004 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2005 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2006 } else if (m->Opcode() == Op_LoadL) {
2007 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2008 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2009 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2010 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2011 }
2012 }
2013 return false;
2014 }
2015 #endif // X86
2016
2017 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2018 Node *off = m->in(AddPNode::Offset);
2019 if (off->is_Con()) {
2020 address_visited.test_set(m->_idx); // Flag as address_visited
2021 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2022 // Clone X+offset as it also folds into most addressing expressions
2023 mstack.push(off, Visit);
2024 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2025 return true;
2026 }
2027 return false;
2028 }
2029
2030 // A method-klass-holder may be passed in the inline_cache_reg
2031 // and then expanded into the inline_cache_reg and a method_oop register
2032 // defined in ad_<arch>.cpp
2033
2034 //------------------------------find_shared------------------------------------
2035 // Set bits if Node is shared or otherwise a root
2036 void Matcher::find_shared( Node *n ) {
2037 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2038 MStack mstack(C->live_nodes() * 2);
2039 // Mark nodes as address_visited if they are inputs to an address expression
2040 VectorSet address_visited(Thread::current()->resource_area());
2041 mstack.push(n, Visit); // Don't need to pre-visit root node
2042 while (mstack.is_nonempty()) {
2043 n = mstack.node(); // Leave node on stack
2044 Node_State nstate = mstack.state();
2045 uint nop = n->Opcode();
2046 if (nstate == Pre_Visit) {
2047 if (address_visited.test(n->_idx)) { // Visited in address already?
2048 // Flag as visited and shared now.
2049 set_visited(n);
2050 }
2051 if (is_visited(n)) { // Visited already?
2052 // Node is shared and has no reason to clone. Flag it as shared.
2053 // This causes it to match into a register for the sharing.
2054 set_shared(n); // Flag as shared and
2055 mstack.pop(); // remove node from stack
2056 continue;
2057 }
2058 nstate = Visit; // Not already visited; so visit now
2059 }
2060 if (nstate == Visit) {
2061 mstack.set_state(Post_Visit);
2062 set_visited(n); // Flag as visited now
2063 bool mem_op = false;
2064
2065 switch( nop ) { // Handle some opcodes special
2066 case Op_Phi: // Treat Phis as shared roots
2067 case Op_Parm:
2068 case Op_Proj: // All handled specially during matching
2069 case Op_SafePointScalarObject:
2070 set_shared(n);
2071 set_dontcare(n);
2072 break;
2073 case Op_If:
2074 case Op_CountedLoopEnd:
2075 mstack.set_state(Alt_Post_Visit); // Alternative way
2076 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2077 // with matching cmp/branch in 1 instruction. The Matcher needs the
2078 // Bool and CmpX side-by-side, because it can only get at constants
2079 // that are at the leaves of Match trees, and the Bool's condition acts
2080 // as a constant here.
2081 mstack.push(n->in(1), Visit); // Clone the Bool
2082 mstack.push(n->in(0), Pre_Visit); // Visit control input
2083 continue; // while (mstack.is_nonempty())
2084 case Op_ConvI2D: // These forms efficiently match with a prior
2085 case Op_ConvI2F: // Load but not a following Store
2086 if( n->in(1)->is_Load() && // Prior load
2087 n->outcnt() == 1 && // Not already shared
2088 n->unique_out()->is_Store() ) // Following store
2089 set_shared(n); // Force it to be a root
2090 break;
2091 case Op_ReverseBytesI:
2092 case Op_ReverseBytesL:
2093 if( n->in(1)->is_Load() && // Prior load
2094 n->outcnt() == 1 ) // Not already shared
2095 set_shared(n); // Force it to be a root
2096 break;
2097 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2098 case Op_IfFalse:
2099 case Op_IfTrue:
2100 case Op_MachProj:
2101 case Op_MergeMem:
2102 case Op_Catch:
2103 case Op_CatchProj:
2104 case Op_CProj:
2105 case Op_JumpProj:
2106 case Op_JProj:
2107 case Op_NeverBranch:
2108 set_dontcare(n);
2109 break;
2110 case Op_Jump:
2111 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2112 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2113 continue; // while (mstack.is_nonempty())
2114 case Op_StrComp:
2115 case Op_StrEquals:
2116 case Op_StrIndexOf:
2117 case Op_StrIndexOfChar:
2118 case Op_AryEq:
2119 case Op_HasNegatives:
2120 case Op_StrInflatedCopy:
2121 case Op_StrCompressedCopy:
2122 case Op_EncodeISOArray:
2123 case Op_FmaD:
2124 case Op_FmaF:
2125 set_shared(n); // Force result into register (it will be anyways)
2126 break;
2127 case Op_ConP: { // Convert pointers above the centerline to NUL
2128 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2129 const TypePtr* tp = tn->type()->is_ptr();
2130 if (tp->_ptr == TypePtr::AnyNull) {
2131 tn->set_type(TypePtr::NULL_PTR);
2132 }
2133 break;
2134 }
2135 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2136 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2137 const TypePtr* tp = tn->type()->make_ptr();
2138 if (tp && tp->_ptr == TypePtr::AnyNull) {
2139 tn->set_type(TypeNarrowOop::NULL_PTR);
2140 }
2141 break;
2142 }
2143 case Op_Binary: // These are introduced in the Post_Visit state.
2144 ShouldNotReachHere();
2145 break;
2146 case Op_ClearArray:
2147 case Op_SafePoint:
2148 mem_op = true;
2149 break;
2150 default:
2151 if( n->is_Store() ) {
2152 // Do match stores, despite no ideal reg
2153 mem_op = true;
2154 break;
2155 }
2156 if( n->is_Mem() ) { // Loads and LoadStores
2157 mem_op = true;
2158 // Loads must be root of match tree due to prior load conflict
2159 if( C->subsume_loads() == false )
2160 set_shared(n);
2161 }
2162 // Fall into default case
2163 if( !n->ideal_reg() )
2164 set_dontcare(n); // Unmatchable Nodes
2165 } // end_switch
2166
2167 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2168 Node *m = n->in(i); // Get ith input
2169 if (m == NULL) continue; // Ignore NULLs
2170 uint mop = m->Opcode();
2171
2172 // Must clone all producers of flags, or we will not match correctly.
2173 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2174 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2175 // are also there, so we may match a float-branch to int-flags and
2176 // expect the allocator to haul the flags from the int-side to the
2177 // fp-side. No can do.
2178 if( _must_clone[mop] ) {
2179 mstack.push(m, Visit);
2180 continue; // for(int i = ...)
2181 }
2182
2183 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2184 // Bases used in addresses must be shared but since
2185 // they are shared through a DecodeN they may appear
2186 // to have a single use so force sharing here.
2187 set_shared(m->in(AddPNode::Base)->in(1));
2188 }
2189
2190 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2191 #ifdef X86
2192 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2193 mstack.push(m, Visit);
2194 continue;
2195 }
2196 #endif
2197
2198 // Clone addressing expressions as they are "free" in memory access instructions
2199 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2200 // When there are other uses besides address expressions
2201 // put it on stack and mark as shared.
2202 !is_visited(m)) {
2203 // Some inputs for address expression are not put on stack
2204 // to avoid marking them as shared and forcing them into register
2205 // if they are used only in address expressions.
2206 // But they should be marked as shared if there are other uses
2207 // besides address expressions.
2208
2209 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2210 continue;
2211 }
2212 } // if( mem_op &&
2213 mstack.push(m, Pre_Visit);
2214 } // for(int i = ...)
2215 }
2216 else if (nstate == Alt_Post_Visit) {
2217 mstack.pop(); // Remove node from stack
2218 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2219 // shared and all users of the Bool need to move the Cmp in parallel.
2220 // This leaves both the Bool and the If pointing at the Cmp. To
2221 // prevent the Matcher from trying to Match the Cmp along both paths
2222 // BoolNode::match_edge always returns a zero.
2223
2224 // We reorder the Op_If in a pre-order manner, so we can visit without
2225 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2226 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2227 }
2228 else if (nstate == Post_Visit) {
2229 mstack.pop(); // Remove node from stack
2230
2231 // Now hack a few special opcodes
2232 switch( n->Opcode() ) { // Handle some opcodes special
2233 case Op_StorePConditional:
2234 case Op_StoreIConditional:
2235 case Op_StoreLConditional:
2236 case Op_CompareAndExchangeB:
2237 case Op_CompareAndExchangeS:
2238 case Op_CompareAndExchangeI:
2239 case Op_CompareAndExchangeL:
2240 case Op_CompareAndExchangeP:
2241 case Op_CompareAndExchangeN:
2242 case Op_WeakCompareAndSwapB:
2243 case Op_WeakCompareAndSwapS:
2244 case Op_WeakCompareAndSwapI:
2245 case Op_WeakCompareAndSwapL:
2246 case Op_WeakCompareAndSwapP:
2247 case Op_WeakCompareAndSwapN:
2248 case Op_CompareAndSwapB:
2249 case Op_CompareAndSwapS:
2250 case Op_CompareAndSwapI:
2251 case Op_CompareAndSwapL:
2252 case Op_CompareAndSwapP:
2253 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2254 Node *newval = n->in(MemNode::ValueIn );
2255 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2256 Node *pair = new BinaryNode( oldval, newval );
2257 n->set_req(MemNode::ValueIn,pair);
2258 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2259 break;
2260 }
2261 case Op_CMoveD: // Convert trinary to binary-tree
2262 case Op_CMoveF:
2263 case Op_CMoveI:
2264 case Op_CMoveL:
2265 case Op_CMoveN:
2266 case Op_CMoveP:
2267 case Op_CMoveVD: {
2268 // Restructure into a binary tree for Matching. It's possible that
2269 // we could move this code up next to the graph reshaping for IfNodes
2270 // or vice-versa, but I do not want to debug this for Ladybird.
2271 // 10/2/2000 CNC.
2272 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2273 n->set_req(1,pair1);
2274 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2275 n->set_req(2,pair2);
2276 n->del_req(3);
2277 break;
2278 }
2279 case Op_LoopLimit: {
2280 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2281 n->set_req(1,pair1);
2282 n->set_req(2,n->in(3));
2283 n->del_req(3);
2284 break;
2285 }
2286 case Op_StrEquals:
2287 case Op_StrIndexOfChar: {
2288 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2289 n->set_req(2,pair1);
2290 n->set_req(3,n->in(4));
2291 n->del_req(4);
2292 break;
2293 }
2294 case Op_StrComp:
2295 case Op_StrIndexOf: {
2296 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2297 n->set_req(2,pair1);
2298 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2299 n->set_req(3,pair2);
2300 n->del_req(5);
2301 n->del_req(4);
2302 break;
2303 }
2304 case Op_StrCompressedCopy:
2305 case Op_StrInflatedCopy:
2306 case Op_EncodeISOArray: {
2307 // Restructure into a binary tree for Matching.
2308 Node* pair = new BinaryNode(n->in(3), n->in(4));
2309 n->set_req(3, pair);
2310 n->del_req(4);
2311 break;
2312 }
2313 case Op_FmaD:
2314 case Op_FmaF: {
2315 // Restructure into a binary tree for Matching.
2316 Node* pair = new BinaryNode(n->in(1), n->in(2));
2317 n->set_req(2, pair);
2318 n->set_req(1, n->in(3));
2319 n->del_req(3);
2320 break;
2321 }
2322 default:
2323 break;
2324 }
2325 }
2326 else {
2327 ShouldNotReachHere();
2328 }
2329 } // end of while (mstack.is_nonempty())
2330 }
2331
2332 #ifdef ASSERT
2333 // machine-independent root to machine-dependent root
2334 void Matcher::dump_old2new_map() {
2335 _old2new_map.dump();
2336 }
2337 #endif
2338
2339 //---------------------------collect_null_checks-------------------------------
2340 // Find null checks in the ideal graph; write a machine-specific node for
2341 // it. Used by later implicit-null-check handling. Actually collects
2342 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2343 // value being tested.
2344 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2345 Node *iff = proj->in(0);
2346 if( iff->Opcode() == Op_If ) {
2347 // During matching If's have Bool & Cmp side-by-side
2348 BoolNode *b = iff->in(1)->as_Bool();
2349 Node *cmp = iff->in(2);
2350 int opc = cmp->Opcode();
2351 if (opc != Op_CmpP && opc != Op_CmpN) return;
2352
2353 const Type* ct = cmp->in(2)->bottom_type();
2354 if (ct == TypePtr::NULL_PTR ||
2355 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2356
2357 bool push_it = false;
2358 if( proj->Opcode() == Op_IfTrue ) {
2359 #ifndef PRODUCT
2360 extern int all_null_checks_found;
2361 all_null_checks_found++;
2362 #endif
2363 if( b->_test._test == BoolTest::ne ) {
2364 push_it = true;
2365 }
2366 } else {
2367 assert( proj->Opcode() == Op_IfFalse, "" );
2368 if( b->_test._test == BoolTest::eq ) {
2369 push_it = true;
2370 }
2371 }
2372 if( push_it ) {
2373 _null_check_tests.push(proj);
2374 Node* val = cmp->in(1);
2375 #ifdef _LP64
2376 if (val->bottom_type()->isa_narrowoop() &&
2377 !Matcher::narrow_oop_use_complex_address()) {
2378 //
2379 // Look for DecodeN node which should be pinned to orig_proj.
2380 // On platforms (Sparc) which can not handle 2 adds
2381 // in addressing mode we have to keep a DecodeN node and
2382 // use it to do implicit NULL check in address.
2383 //
2384 // DecodeN node was pinned to non-null path (orig_proj) during
2385 // CastPP transformation in final_graph_reshaping_impl().
2386 //
2387 uint cnt = orig_proj->outcnt();
2388 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2389 Node* d = orig_proj->raw_out(i);
2390 if (d->is_DecodeN() && d->in(1) == val) {
2391 val = d;
2392 val->set_req(0, NULL); // Unpin now.
2393 // Mark this as special case to distinguish from
2394 // a regular case: CmpP(DecodeN, NULL).
2395 val = (Node*)(((intptr_t)val) | 1);
2396 break;
2397 }
2398 }
2399 }
2400 #endif
2401 _null_check_tests.push(val);
2402 }
2403 }
2404 }
2405 }
2406
2407 //---------------------------validate_null_checks------------------------------
2408 // Its possible that the value being NULL checked is not the root of a match
2409 // tree. If so, I cannot use the value in an implicit null check.
2410 void Matcher::validate_null_checks( ) {
2411 uint cnt = _null_check_tests.size();
2412 for( uint i=0; i < cnt; i+=2 ) {
2413 Node *test = _null_check_tests[i];
2414 Node *val = _null_check_tests[i+1];
2415 bool is_decoden = ((intptr_t)val) & 1;
2416 val = (Node*)(((intptr_t)val) & ~1);
2417 if (has_new_node(val)) {
2418 Node* new_val = new_node(val);
2419 if (is_decoden) {
2420 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2421 // Note: new_val may have a control edge if
2422 // the original ideal node DecodeN was matched before
2423 // it was unpinned in Matcher::collect_null_checks().
2424 // Unpin the mach node and mark it.
2425 new_val->set_req(0, NULL);
2426 new_val = (Node*)(((intptr_t)new_val) | 1);
2427 }
2428 // Is a match-tree root, so replace with the matched value
2429 _null_check_tests.map(i+1, new_val);
2430 } else {
2431 // Yank from candidate list
2432 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2433 _null_check_tests.map(i,_null_check_tests[--cnt]);
2434 _null_check_tests.pop();
2435 _null_check_tests.pop();
2436 i-=2;
2437 }
2438 }
2439 }
2440
2441 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2442 // atomic instruction acting as a store_load barrier without any
2443 // intervening volatile load, and thus we don't need a barrier here.
2444 // We retain the Node to act as a compiler ordering barrier.
2445 bool Matcher::post_store_load_barrier(const Node* vmb) {
2446 Compile* C = Compile::current();
2447 assert(vmb->is_MemBar(), "");
2448 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2449 const MemBarNode* membar = vmb->as_MemBar();
2450
2451 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2452 Node* ctrl = NULL;
2453 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2454 Node* p = membar->fast_out(i);
2455 assert(p->is_Proj(), "only projections here");
2456 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2457 !C->node_arena()->contains(p)) { // Unmatched old-space only
2458 ctrl = p;
2459 break;
2460 }
2461 }
2462 assert((ctrl != NULL), "missing control projection");
2463
2464 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2465 Node *x = ctrl->fast_out(j);
2466 int xop = x->Opcode();
2467
2468 // We don't need current barrier if we see another or a lock
2469 // before seeing volatile load.
2470 //
2471 // Op_Fastunlock previously appeared in the Op_* list below.
2472 // With the advent of 1-0 lock operations we're no longer guaranteed
2473 // that a monitor exit operation contains a serializing instruction.
2474
2475 if (xop == Op_MemBarVolatile ||
2476 xop == Op_CompareAndExchangeB ||
2477 xop == Op_CompareAndExchangeS ||
2478 xop == Op_CompareAndExchangeI ||
2479 xop == Op_CompareAndExchangeL ||
2480 xop == Op_CompareAndExchangeP ||
2481 xop == Op_CompareAndExchangeN ||
2482 xop == Op_WeakCompareAndSwapB ||
2483 xop == Op_WeakCompareAndSwapS ||
2484 xop == Op_WeakCompareAndSwapL ||
2485 xop == Op_WeakCompareAndSwapP ||
2486 xop == Op_WeakCompareAndSwapN ||
2487 xop == Op_WeakCompareAndSwapI ||
2488 xop == Op_CompareAndSwapB ||
2489 xop == Op_CompareAndSwapS ||
2490 xop == Op_CompareAndSwapL ||
2491 xop == Op_CompareAndSwapP ||
2492 xop == Op_CompareAndSwapN ||
2493 xop == Op_CompareAndSwapI) {
2494 return true;
2495 }
2496
2497 // Op_FastLock previously appeared in the Op_* list above.
2498 // With biased locking we're no longer guaranteed that a monitor
2499 // enter operation contains a serializing instruction.
2500 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2501 return true;
2502 }
2503
2504 if (x->is_MemBar()) {
2505 // We must retain this membar if there is an upcoming volatile
2506 // load, which will be followed by acquire membar.
2507 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2508 return false;
2509 } else {
2510 // For other kinds of barriers, check by pretending we
2511 // are them, and seeing if we can be removed.
2512 return post_store_load_barrier(x->as_MemBar());
2513 }
2514 }
2515
2516 // probably not necessary to check for these
2517 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2518 return false;
2519 }
2520 }
2521 return false;
2522 }
2523
2524 // Check whether node n is a branch to an uncommon trap that we could
2525 // optimize as test with very high branch costs in case of going to
2526 // the uncommon trap. The code must be able to be recompiled to use
2527 // a cheaper test.
2528 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2529 // Don't do it for natives, adapters, or runtime stubs
2530 Compile *C = Compile::current();
2531 if (!C->is_method_compilation()) return false;
2532
2533 assert(n->is_If(), "You should only call this on if nodes.");
2534 IfNode *ifn = n->as_If();
2535
2536 Node *ifFalse = NULL;
2537 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2538 if (ifn->fast_out(i)->is_IfFalse()) {
2539 ifFalse = ifn->fast_out(i);
2540 break;
2541 }
2542 }
2543 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2544
2545 Node *reg = ifFalse;
2546 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2547 // Alternatively use visited set? Seems too expensive.
2548 while (reg != NULL && cnt > 0) {
2549 CallNode *call = NULL;
2550 RegionNode *nxt_reg = NULL;
2551 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2552 Node *o = reg->fast_out(i);
2553 if (o->is_Call()) {
2554 call = o->as_Call();
2555 }
2556 if (o->is_Region()) {
2557 nxt_reg = o->as_Region();
2558 }
2559 }
2560
2561 if (call &&
2562 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2563 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2564 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2565 jint tr_con = trtype->is_int()->get_con();
2566 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2567 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2568 assert((int)reason < (int)BitsPerInt, "recode bit map");
2569
2570 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2571 && action != Deoptimization::Action_none) {
2572 // This uncommon trap is sure to recompile, eventually.
2573 // When that happens, C->too_many_traps will prevent
2574 // this transformation from happening again.
2575 return true;
2576 }
2577 }
2578 }
2579
2580 reg = nxt_reg;
2581 cnt--;
2582 }
2583
2584 return false;
2585 }
2586
2587 //=============================================================================
2588 //---------------------------State---------------------------------------------
2589 State::State(void) {
2590 #ifdef ASSERT
2591 _id = 0;
2592 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2593 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2594 //memset(_cost, -1, sizeof(_cost));
2595 //memset(_rule, -1, sizeof(_rule));
2596 #endif
2597 memset(_valid, 0, sizeof(_valid));
2598 }
2599
2600 #ifdef ASSERT
2601 State::~State() {
2602 _id = 99;
2603 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2604 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2605 memset(_cost, -3, sizeof(_cost));
2606 memset(_rule, -3, sizeof(_rule));
2607 }
2608 #endif
2609
2610 #ifndef PRODUCT
2611 //---------------------------dump----------------------------------------------
2612 void State::dump() {
2613 tty->print("\n");
2614 dump(0);
2615 }
2616
2617 void State::dump(int depth) {
2618 for( int j = 0; j < depth; j++ )
2619 tty->print(" ");
2620 tty->print("--N: ");
2621 _leaf->dump();
2622 uint i;
2623 for( i = 0; i < _LAST_MACH_OPER; i++ )
2624 // Check for valid entry
2625 if( valid(i) ) {
2626 for( int j = 0; j < depth; j++ )
2627 tty->print(" ");
2628 assert(_cost[i] != max_juint, "cost must be a valid value");
2629 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2630 tty->print_cr("%s %d %s",
2631 ruleName[i], _cost[i], ruleName[_rule[i]] );
2632 }
2633 tty->cr();
2634
2635 for( i=0; i<2; i++ )
2636 if( _kids[i] )
2637 _kids[i]->dump(depth+1);
2638 }
2639 #endif