1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "memory/allocation.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "opto/ad.hpp" 29 #include "opto/addnode.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/idealGraphPrinter.hpp" 32 #include "opto/matcher.hpp" 33 #include "opto/memnode.hpp" 34 #include "opto/movenode.hpp" 35 #include "opto/opcodes.hpp" 36 #include "opto/regmask.hpp" 37 #include "opto/rootnode.hpp" 38 #include "opto/runtime.hpp" 39 #include "opto/type.hpp" 40 #include "opto/vectornode.hpp" 41 #include "runtime/os.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 44 OptoReg::Name OptoReg::c_frame_pointer; 45 46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 47 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 48 RegMask Matcher::STACK_ONLY_mask; 49 RegMask Matcher::c_frame_ptr_mask; 50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 52 53 //---------------------------Matcher------------------------------------------- 54 Matcher::Matcher() 55 : PhaseTransform( Phase::Ins_Select ), 56 #ifdef ASSERT 57 _old2new_map(C->comp_arena()), 58 _new2old_map(C->comp_arena()), 59 #endif 60 _shared_nodes(C->comp_arena()), 61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 62 _swallowed(swallowed), 63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 64 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 65 _must_clone(must_clone), 66 _register_save_policy(register_save_policy), 67 _c_reg_save_policy(c_reg_save_policy), 68 _register_save_type(register_save_type), 69 _ruleName(ruleName), 70 _allocation_started(false), 71 _states_arena(Chunk::medium_size), 72 _visited(&_states_arena), 73 _shared(&_states_arena), 74 _dontcare(&_states_arena) { 75 C->set_matcher(this); 76 77 idealreg2spillmask [Op_RegI] = NULL; 78 idealreg2spillmask [Op_RegN] = NULL; 79 idealreg2spillmask [Op_RegL] = NULL; 80 idealreg2spillmask [Op_RegF] = NULL; 81 idealreg2spillmask [Op_RegD] = NULL; 82 idealreg2spillmask [Op_RegP] = NULL; 83 idealreg2spillmask [Op_VecS] = NULL; 84 idealreg2spillmask [Op_VecD] = NULL; 85 idealreg2spillmask [Op_VecX] = NULL; 86 idealreg2spillmask [Op_VecY] = NULL; 87 idealreg2spillmask [Op_VecZ] = NULL; 88 idealreg2spillmask [Op_RegFlags] = NULL; 89 90 idealreg2debugmask [Op_RegI] = NULL; 91 idealreg2debugmask [Op_RegN] = NULL; 92 idealreg2debugmask [Op_RegL] = NULL; 93 idealreg2debugmask [Op_RegF] = NULL; 94 idealreg2debugmask [Op_RegD] = NULL; 95 idealreg2debugmask [Op_RegP] = NULL; 96 idealreg2debugmask [Op_VecS] = NULL; 97 idealreg2debugmask [Op_VecD] = NULL; 98 idealreg2debugmask [Op_VecX] = NULL; 99 idealreg2debugmask [Op_VecY] = NULL; 100 idealreg2debugmask [Op_VecZ] = NULL; 101 idealreg2debugmask [Op_RegFlags] = NULL; 102 103 idealreg2mhdebugmask[Op_RegI] = NULL; 104 idealreg2mhdebugmask[Op_RegN] = NULL; 105 idealreg2mhdebugmask[Op_RegL] = NULL; 106 idealreg2mhdebugmask[Op_RegF] = NULL; 107 idealreg2mhdebugmask[Op_RegD] = NULL; 108 idealreg2mhdebugmask[Op_RegP] = NULL; 109 idealreg2mhdebugmask[Op_VecS] = NULL; 110 idealreg2mhdebugmask[Op_VecD] = NULL; 111 idealreg2mhdebugmask[Op_VecX] = NULL; 112 idealreg2mhdebugmask[Op_VecY] = NULL; 113 idealreg2mhdebugmask[Op_VecZ] = NULL; 114 idealreg2mhdebugmask[Op_RegFlags] = NULL; 115 116 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 117 } 118 119 //------------------------------warp_incoming_stk_arg------------------------ 120 // This warps a VMReg into an OptoReg::Name 121 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 122 OptoReg::Name warped; 123 if( reg->is_stack() ) { // Stack slot argument? 124 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 125 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 126 if( warped >= _in_arg_limit ) 127 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 128 if (!RegMask::can_represent_arg(warped)) { 129 // the compiler cannot represent this method's calling sequence 130 C->record_method_not_compilable("unsupported incoming calling sequence"); 131 return OptoReg::Bad; 132 } 133 return warped; 134 } 135 return OptoReg::as_OptoReg(reg); 136 } 137 138 //---------------------------compute_old_SP------------------------------------ 139 OptoReg::Name Compile::compute_old_SP() { 140 int fixed = fixed_slots(); 141 int preserve = in_preserve_stack_slots(); 142 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots())); 143 } 144 145 146 147 #ifdef ASSERT 148 void Matcher::verify_new_nodes_only(Node* xroot) { 149 // Make sure that the new graph only references new nodes 150 ResourceMark rm; 151 Unique_Node_List worklist; 152 VectorSet visited(Thread::current()->resource_area()); 153 worklist.push(xroot); 154 while (worklist.size() > 0) { 155 Node* n = worklist.pop(); 156 visited <<= n->_idx; 157 assert(C->node_arena()->contains(n), "dead node"); 158 for (uint j = 0; j < n->req(); j++) { 159 Node* in = n->in(j); 160 if (in != NULL) { 161 assert(C->node_arena()->contains(in), "dead node"); 162 if (!visited.test(in->_idx)) { 163 worklist.push(in); 164 } 165 } 166 } 167 } 168 } 169 #endif 170 171 172 //---------------------------match--------------------------------------------- 173 void Matcher::match( ) { 174 if( MaxLabelRootDepth < 100 ) { // Too small? 175 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 176 MaxLabelRootDepth = 100; 177 } 178 // One-time initialization of some register masks. 179 init_spill_mask( C->root()->in(1) ); 180 _return_addr_mask = return_addr(); 181 #ifdef _LP64 182 // Pointers take 2 slots in 64-bit land 183 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 184 #endif 185 186 // Map a Java-signature return type into return register-value 187 // machine registers for 0, 1 and 2 returned values. 188 const TypeTuple *range = C->tf()->range(); 189 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 190 // Get ideal-register return type 191 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 192 // Get machine return register 193 uint sop = C->start()->Opcode(); 194 OptoRegPair regs = return_value(ireg, false); 195 196 // And mask for same 197 _return_value_mask = RegMask(regs.first()); 198 if( OptoReg::is_valid(regs.second()) ) 199 _return_value_mask.Insert(regs.second()); 200 } 201 202 // --------------- 203 // Frame Layout 204 205 // Need the method signature to determine the incoming argument types, 206 // because the types determine which registers the incoming arguments are 207 // in, and this affects the matched code. 208 const TypeTuple *domain = C->tf()->domain(); 209 uint argcnt = domain->cnt() - TypeFunc::Parms; 210 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 211 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 212 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 213 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 214 uint i; 215 for( i = 0; i<argcnt; i++ ) { 216 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 217 } 218 219 // Pass array of ideal registers and length to USER code (from the AD file) 220 // that will convert this to an array of register numbers. 221 const StartNode *start = C->start(); 222 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 223 #ifdef ASSERT 224 // Sanity check users' calling convention. Real handy while trying to 225 // get the initial port correct. 226 { for (uint i = 0; i<argcnt; i++) { 227 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 228 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 229 _parm_regs[i].set_bad(); 230 continue; 231 } 232 VMReg parm_reg = vm_parm_regs[i].first(); 233 assert(parm_reg->is_valid(), "invalid arg?"); 234 if (parm_reg->is_reg()) { 235 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 236 assert(can_be_java_arg(opto_parm_reg) || 237 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 238 opto_parm_reg == inline_cache_reg(), 239 "parameters in register must be preserved by runtime stubs"); 240 } 241 for (uint j = 0; j < i; j++) { 242 assert(parm_reg != vm_parm_regs[j].first(), 243 "calling conv. must produce distinct regs"); 244 } 245 } 246 } 247 #endif 248 249 // Do some initial frame layout. 250 251 // Compute the old incoming SP (may be called FP) as 252 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 253 _old_SP = C->compute_old_SP(); 254 assert( is_even(_old_SP), "must be even" ); 255 256 // Compute highest incoming stack argument as 257 // _old_SP + out_preserve_stack_slots + incoming argument size. 258 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 259 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 260 for( i = 0; i < argcnt; i++ ) { 261 // Permit args to have no register 262 _calling_convention_mask[i].Clear(); 263 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 264 continue; 265 } 266 // calling_convention returns stack arguments as a count of 267 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 268 // the allocators point of view, taking into account all the 269 // preserve area, locks & pad2. 270 271 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 272 if( OptoReg::is_valid(reg1)) 273 _calling_convention_mask[i].Insert(reg1); 274 275 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 276 if( OptoReg::is_valid(reg2)) 277 _calling_convention_mask[i].Insert(reg2); 278 279 // Saved biased stack-slot register number 280 _parm_regs[i].set_pair(reg2, reg1); 281 } 282 283 // Finally, make sure the incoming arguments take up an even number of 284 // words, in case the arguments or locals need to contain doubleword stack 285 // slots. The rest of the system assumes that stack slot pairs (in 286 // particular, in the spill area) which look aligned will in fact be 287 // aligned relative to the stack pointer in the target machine. Double 288 // stack slots will always be allocated aligned. 289 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong)); 290 291 // Compute highest outgoing stack argument as 292 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 293 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 294 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 295 296 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 297 // the compiler cannot represent this method's calling sequence 298 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 299 } 300 301 if (C->failing()) return; // bailed out on incoming arg failure 302 303 // --------------- 304 // Collect roots of matcher trees. Every node for which 305 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 306 // can be a valid interior of some tree. 307 find_shared( C->root() ); 308 find_shared( C->top() ); 309 310 C->print_method(PHASE_BEFORE_MATCHING); 311 312 // Create new ideal node ConP #NULL even if it does exist in old space 313 // to avoid false sharing if the corresponding mach node is not used. 314 // The corresponding mach node is only used in rare cases for derived 315 // pointers. 316 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 317 318 // Swap out to old-space; emptying new-space 319 Arena *old = C->node_arena()->move_contents(C->old_arena()); 320 321 // Save debug and profile information for nodes in old space: 322 _old_node_note_array = C->node_note_array(); 323 if (_old_node_note_array != NULL) { 324 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 325 (C->comp_arena(), _old_node_note_array->length(), 326 0, NULL)); 327 } 328 329 // Pre-size the new_node table to avoid the need for range checks. 330 grow_new_node_array(C->unique()); 331 332 // Reset node counter so MachNodes start with _idx at 0 333 int live_nodes = C->live_nodes(); 334 C->set_unique(0); 335 C->reset_dead_node_list(); 336 337 // Recursively match trees from old space into new space. 338 // Correct leaves of new-space Nodes; they point to old-space. 339 _visited.Clear(); // Clear visit bits for xform call 340 C->set_cached_top_node(xform( C->top(), live_nodes )); 341 if (!C->failing()) { 342 Node* xroot = xform( C->root(), 1 ); 343 if (xroot == NULL) { 344 Matcher::soft_match_failure(); // recursive matching process failed 345 C->record_method_not_compilable("instruction match failed"); 346 } else { 347 // During matching shared constants were attached to C->root() 348 // because xroot wasn't available yet, so transfer the uses to 349 // the xroot. 350 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 351 Node* n = C->root()->fast_out(j); 352 if (C->node_arena()->contains(n)) { 353 assert(n->in(0) == C->root(), "should be control user"); 354 n->set_req(0, xroot); 355 --j; 356 --jmax; 357 } 358 } 359 360 // Generate new mach node for ConP #NULL 361 assert(new_ideal_null != NULL, "sanity"); 362 _mach_null = match_tree(new_ideal_null); 363 // Don't set control, it will confuse GCM since there are no uses. 364 // The control will be set when this node is used first time 365 // in find_base_for_derived(). 366 assert(_mach_null != NULL, ""); 367 368 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 369 370 #ifdef ASSERT 371 verify_new_nodes_only(xroot); 372 #endif 373 } 374 } 375 if (C->top() == NULL || C->root() == NULL) { 376 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 377 } 378 if (C->failing()) { 379 // delete old; 380 old->destruct_contents(); 381 return; 382 } 383 assert( C->top(), "" ); 384 assert( C->root(), "" ); 385 validate_null_checks(); 386 387 // Now smoke old-space 388 NOT_DEBUG( old->destruct_contents() ); 389 390 // ------------------------ 391 // Set up save-on-entry registers 392 Fixup_Save_On_Entry( ); 393 } 394 395 396 //------------------------------Fixup_Save_On_Entry---------------------------- 397 // The stated purpose of this routine is to take care of save-on-entry 398 // registers. However, the overall goal of the Match phase is to convert into 399 // machine-specific instructions which have RegMasks to guide allocation. 400 // So what this procedure really does is put a valid RegMask on each input 401 // to the machine-specific variations of all Return, TailCall and Halt 402 // instructions. It also adds edgs to define the save-on-entry values (and of 403 // course gives them a mask). 404 405 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 406 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 407 // Do all the pre-defined register masks 408 rms[TypeFunc::Control ] = RegMask::Empty; 409 rms[TypeFunc::I_O ] = RegMask::Empty; 410 rms[TypeFunc::Memory ] = RegMask::Empty; 411 rms[TypeFunc::ReturnAdr] = ret_adr; 412 rms[TypeFunc::FramePtr ] = fp; 413 return rms; 414 } 415 416 //---------------------------init_first_stack_mask----------------------------- 417 // Create the initial stack mask used by values spilling to the stack. 418 // Disallow any debug info in outgoing argument areas by setting the 419 // initial mask accordingly. 420 void Matcher::init_first_stack_mask() { 421 422 // Allocate storage for spill masks as masks for the appropriate load type. 423 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); 424 425 idealreg2spillmask [Op_RegN] = &rms[0]; 426 idealreg2spillmask [Op_RegI] = &rms[1]; 427 idealreg2spillmask [Op_RegL] = &rms[2]; 428 idealreg2spillmask [Op_RegF] = &rms[3]; 429 idealreg2spillmask [Op_RegD] = &rms[4]; 430 idealreg2spillmask [Op_RegP] = &rms[5]; 431 432 idealreg2debugmask [Op_RegN] = &rms[6]; 433 idealreg2debugmask [Op_RegI] = &rms[7]; 434 idealreg2debugmask [Op_RegL] = &rms[8]; 435 idealreg2debugmask [Op_RegF] = &rms[9]; 436 idealreg2debugmask [Op_RegD] = &rms[10]; 437 idealreg2debugmask [Op_RegP] = &rms[11]; 438 439 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 440 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 441 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 442 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 443 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 444 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 445 446 idealreg2spillmask [Op_VecS] = &rms[18]; 447 idealreg2spillmask [Op_VecD] = &rms[19]; 448 idealreg2spillmask [Op_VecX] = &rms[20]; 449 idealreg2spillmask [Op_VecY] = &rms[21]; 450 idealreg2spillmask [Op_VecZ] = &rms[22]; 451 452 OptoReg::Name i; 453 454 // At first, start with the empty mask 455 C->FIRST_STACK_mask().Clear(); 456 457 // Add in the incoming argument area 458 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 459 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 460 C->FIRST_STACK_mask().Insert(i); 461 } 462 // Add in all bits past the outgoing argument area 463 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 464 "must be able to represent all call arguments in reg mask"); 465 OptoReg::Name init = _out_arg_limit; 466 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 467 C->FIRST_STACK_mask().Insert(i); 468 } 469 // Finally, set the "infinite stack" bit. 470 C->FIRST_STACK_mask().set_AllStack(); 471 472 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 473 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 474 // Keep spill masks aligned. 475 aligned_stack_mask.clear_to_pairs(); 476 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 477 478 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 479 #ifdef _LP64 480 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 481 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 482 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 483 #else 484 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 485 #endif 486 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 487 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 488 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 489 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 490 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 491 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 492 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 493 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 494 495 if (Matcher::vector_size_supported(T_BYTE,4)) { 496 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 497 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 498 } 499 if (Matcher::vector_size_supported(T_FLOAT,2)) { 500 // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 501 // RA guarantees such alignment since it is needed for Double and Long values. 502 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 503 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 504 } 505 if (Matcher::vector_size_supported(T_FLOAT,4)) { 506 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 507 // 508 // RA can use input arguments stack slots for spills but until RA 509 // we don't know frame size and offset of input arg stack slots. 510 // 511 // Exclude last input arg stack slots to avoid spilling vectors there 512 // otherwise vector spills could stomp over stack slots in caller frame. 513 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 514 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 515 aligned_stack_mask.Remove(in); 516 in = OptoReg::add(in, -1); 517 } 518 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 519 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 520 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 521 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 522 } 523 if (Matcher::vector_size_supported(T_FLOAT,8)) { 524 // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 525 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 526 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 527 aligned_stack_mask.Remove(in); 528 in = OptoReg::add(in, -1); 529 } 530 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 531 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 532 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 533 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 534 } 535 if (Matcher::vector_size_supported(T_FLOAT,16)) { 536 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 537 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 538 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 539 aligned_stack_mask.Remove(in); 540 in = OptoReg::add(in, -1); 541 } 542 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 543 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 544 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 545 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 546 } 547 if (UseFPUForSpilling) { 548 // This mask logic assumes that the spill operations are 549 // symmetric and that the registers involved are the same size. 550 // On sparc for instance we may have to use 64 bit moves will 551 // kill 2 registers when used with F0-F31. 552 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 553 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 554 #ifdef _LP64 555 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 556 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 557 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 558 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 559 #else 560 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 561 #ifdef ARM 562 // ARM has support for moving 64bit values between a pair of 563 // integer registers and a double register 564 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 565 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 566 #endif 567 #endif 568 } 569 570 // Make up debug masks. Any spill slot plus callee-save registers. 571 // Caller-save registers are assumed to be trashable by the various 572 // inline-cache fixup routines. 573 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 574 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 575 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 576 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 577 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 578 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 579 580 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 581 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 582 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 583 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 584 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 585 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 586 587 // Prevent stub compilations from attempting to reference 588 // callee-saved registers from debug info 589 bool exclude_soe = !Compile::current()->is_method_compilation(); 590 591 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 592 // registers the caller has to save do not work 593 if( _register_save_policy[i] == 'C' || 594 _register_save_policy[i] == 'A' || 595 (_register_save_policy[i] == 'E' && exclude_soe) ) { 596 idealreg2debugmask [Op_RegN]->Remove(i); 597 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 598 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 599 idealreg2debugmask [Op_RegF]->Remove(i); // masks 600 idealreg2debugmask [Op_RegD]->Remove(i); 601 idealreg2debugmask [Op_RegP]->Remove(i); 602 603 idealreg2mhdebugmask[Op_RegN]->Remove(i); 604 idealreg2mhdebugmask[Op_RegI]->Remove(i); 605 idealreg2mhdebugmask[Op_RegL]->Remove(i); 606 idealreg2mhdebugmask[Op_RegF]->Remove(i); 607 idealreg2mhdebugmask[Op_RegD]->Remove(i); 608 idealreg2mhdebugmask[Op_RegP]->Remove(i); 609 } 610 } 611 612 // Subtract the register we use to save the SP for MethodHandle 613 // invokes to from the debug mask. 614 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 615 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 616 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 617 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 618 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 619 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 620 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 621 } 622 623 //---------------------------is_save_on_entry---------------------------------- 624 bool Matcher::is_save_on_entry( int reg ) { 625 return 626 _register_save_policy[reg] == 'E' || 627 _register_save_policy[reg] == 'A' || // Save-on-entry register? 628 // Also save argument registers in the trampolining stubs 629 (C->save_argument_registers() && is_spillable_arg(reg)); 630 } 631 632 //---------------------------Fixup_Save_On_Entry------------------------------- 633 void Matcher::Fixup_Save_On_Entry( ) { 634 init_first_stack_mask(); 635 636 Node *root = C->root(); // Short name for root 637 // Count number of save-on-entry registers. 638 uint soe_cnt = number_of_saved_registers(); 639 uint i; 640 641 // Find the procedure Start Node 642 StartNode *start = C->start(); 643 assert( start, "Expect a start node" ); 644 645 // Save argument registers in the trampolining stubs 646 if( C->save_argument_registers() ) 647 for( i = 0; i < _last_Mach_Reg; i++ ) 648 if( is_spillable_arg(i) ) 649 soe_cnt++; 650 651 // Input RegMask array shared by all Returns. 652 // The type for doubles and longs has a count of 2, but 653 // there is only 1 returned value 654 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 655 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 656 // Returns have 0 or 1 returned values depending on call signature. 657 // Return register is specified by return_value in the AD file. 658 if (ret_edge_cnt > TypeFunc::Parms) 659 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 660 661 // Input RegMask array shared by all Rethrows. 662 uint reth_edge_cnt = TypeFunc::Parms+1; 663 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 664 // Rethrow takes exception oop only, but in the argument 0 slot. 665 OptoReg::Name reg = find_receiver(false); 666 if (reg >= 0) { 667 reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 668 #ifdef _LP64 669 // Need two slots for ptrs in 64-bit land 670 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 671 #endif 672 } 673 674 // Input RegMask array shared by all TailCalls 675 uint tail_call_edge_cnt = TypeFunc::Parms+2; 676 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 677 678 // Input RegMask array shared by all TailJumps 679 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 680 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 681 682 // TailCalls have 2 returned values (target & moop), whose masks come 683 // from the usual MachNode/MachOper mechanism. Find a sample 684 // TailCall to extract these masks and put the correct masks into 685 // the tail_call_rms array. 686 for( i=1; i < root->req(); i++ ) { 687 MachReturnNode *m = root->in(i)->as_MachReturn(); 688 if( m->ideal_Opcode() == Op_TailCall ) { 689 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 690 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 691 break; 692 } 693 } 694 695 // TailJumps have 2 returned values (target & ex_oop), whose masks come 696 // from the usual MachNode/MachOper mechanism. Find a sample 697 // TailJump to extract these masks and put the correct masks into 698 // the tail_jump_rms array. 699 for( i=1; i < root->req(); i++ ) { 700 MachReturnNode *m = root->in(i)->as_MachReturn(); 701 if( m->ideal_Opcode() == Op_TailJump ) { 702 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 703 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 704 break; 705 } 706 } 707 708 // Input RegMask array shared by all Halts 709 uint halt_edge_cnt = TypeFunc::Parms; 710 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 711 712 // Capture the return input masks into each exit flavor 713 for( i=1; i < root->req(); i++ ) { 714 MachReturnNode *exit = root->in(i)->as_MachReturn(); 715 switch( exit->ideal_Opcode() ) { 716 case Op_Return : exit->_in_rms = ret_rms; break; 717 case Op_Rethrow : exit->_in_rms = reth_rms; break; 718 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 719 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 720 case Op_Halt : exit->_in_rms = halt_rms; break; 721 default : ShouldNotReachHere(); 722 } 723 } 724 725 // Next unused projection number from Start. 726 int proj_cnt = C->tf()->domain()->cnt(); 727 728 // Do all the save-on-entry registers. Make projections from Start for 729 // them, and give them a use at the exit points. To the allocator, they 730 // look like incoming register arguments. 731 for( i = 0; i < _last_Mach_Reg; i++ ) { 732 if( is_save_on_entry(i) ) { 733 734 // Add the save-on-entry to the mask array 735 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 736 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 737 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 738 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 739 // Halts need the SOE registers, but only in the stack as debug info. 740 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 741 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 742 743 Node *mproj; 744 745 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 746 // into a single RegD. 747 if( (i&1) == 0 && 748 _register_save_type[i ] == Op_RegF && 749 _register_save_type[i+1] == Op_RegF && 750 is_save_on_entry(i+1) ) { 751 // Add other bit for double 752 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 753 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 754 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 755 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 756 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 757 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 758 proj_cnt += 2; // Skip 2 for doubles 759 } 760 else if( (i&1) == 1 && // Else check for high half of double 761 _register_save_type[i-1] == Op_RegF && 762 _register_save_type[i ] == Op_RegF && 763 is_save_on_entry(i-1) ) { 764 ret_rms [ ret_edge_cnt] = RegMask::Empty; 765 reth_rms [ reth_edge_cnt] = RegMask::Empty; 766 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 767 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 768 halt_rms [ halt_edge_cnt] = RegMask::Empty; 769 mproj = C->top(); 770 } 771 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 772 // into a single RegL. 773 else if( (i&1) == 0 && 774 _register_save_type[i ] == Op_RegI && 775 _register_save_type[i+1] == Op_RegI && 776 is_save_on_entry(i+1) ) { 777 // Add other bit for long 778 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 779 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 780 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 781 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 782 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 783 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 784 proj_cnt += 2; // Skip 2 for longs 785 } 786 else if( (i&1) == 1 && // Else check for high half of long 787 _register_save_type[i-1] == Op_RegI && 788 _register_save_type[i ] == Op_RegI && 789 is_save_on_entry(i-1) ) { 790 ret_rms [ ret_edge_cnt] = RegMask::Empty; 791 reth_rms [ reth_edge_cnt] = RegMask::Empty; 792 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 793 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 794 halt_rms [ halt_edge_cnt] = RegMask::Empty; 795 mproj = C->top(); 796 } else { 797 // Make a projection for it off the Start 798 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 799 } 800 801 ret_edge_cnt ++; 802 reth_edge_cnt ++; 803 tail_call_edge_cnt ++; 804 tail_jump_edge_cnt ++; 805 halt_edge_cnt ++; 806 807 // Add a use of the SOE register to all exit paths 808 for( uint j=1; j < root->req(); j++ ) 809 root->in(j)->add_req(mproj); 810 } // End of if a save-on-entry register 811 } // End of for all machine registers 812 } 813 814 //------------------------------init_spill_mask-------------------------------- 815 void Matcher::init_spill_mask( Node *ret ) { 816 if( idealreg2regmask[Op_RegI] ) return; // One time only init 817 818 OptoReg::c_frame_pointer = c_frame_pointer(); 819 c_frame_ptr_mask = c_frame_pointer(); 820 #ifdef _LP64 821 // pointers are twice as big 822 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 823 #endif 824 825 // Start at OptoReg::stack0() 826 STACK_ONLY_mask.Clear(); 827 OptoReg::Name init = OptoReg::stack2reg(0); 828 // STACK_ONLY_mask is all stack bits 829 OptoReg::Name i; 830 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 831 STACK_ONLY_mask.Insert(i); 832 // Also set the "infinite stack" bit. 833 STACK_ONLY_mask.set_AllStack(); 834 835 // Copy the register names over into the shared world 836 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 837 // SharedInfo::regName[i] = regName[i]; 838 // Handy RegMasks per machine register 839 mreg2regmask[i].Insert(i); 840 } 841 842 // Grab the Frame Pointer 843 Node *fp = ret->in(TypeFunc::FramePtr); 844 Node *mem = ret->in(TypeFunc::Memory); 845 const TypePtr* atp = TypePtr::BOTTOM; 846 // Share frame pointer while making spill ops 847 set_shared(fp); 848 849 // Compute generic short-offset Loads 850 #ifdef _LP64 851 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 852 #endif 853 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered)); 854 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false)); 855 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered)); 856 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered)); 857 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 858 assert(spillI != NULL && spillL != NULL && spillF != NULL && 859 spillD != NULL && spillP != NULL, ""); 860 // Get the ADLC notion of the right regmask, for each basic type. 861 #ifdef _LP64 862 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 863 #endif 864 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 865 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 866 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 867 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 868 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 869 870 // Vector regmasks. 871 if (Matcher::vector_size_supported(T_BYTE,4)) { 872 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 873 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 874 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 875 } 876 if (Matcher::vector_size_supported(T_FLOAT,2)) { 877 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 878 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 879 } 880 if (Matcher::vector_size_supported(T_FLOAT,4)) { 881 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 882 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 883 } 884 if (Matcher::vector_size_supported(T_FLOAT,8)) { 885 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 886 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 887 } 888 if (Matcher::vector_size_supported(T_FLOAT,16)) { 889 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ)); 890 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask(); 891 } 892 } 893 894 #ifdef ASSERT 895 static void match_alias_type(Compile* C, Node* n, Node* m) { 896 if (!VerifyAliases) return; // do not go looking for trouble by default 897 const TypePtr* nat = n->adr_type(); 898 const TypePtr* mat = m->adr_type(); 899 int nidx = C->get_alias_index(nat); 900 int midx = C->get_alias_index(mat); 901 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 902 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 903 for (uint i = 1; i < n->req(); i++) { 904 Node* n1 = n->in(i); 905 const TypePtr* n1at = n1->adr_type(); 906 if (n1at != NULL) { 907 nat = n1at; 908 nidx = C->get_alias_index(n1at); 909 } 910 } 911 } 912 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 913 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 914 switch (n->Opcode()) { 915 case Op_PrefetchAllocation: 916 nidx = Compile::AliasIdxRaw; 917 nat = TypeRawPtr::BOTTOM; 918 break; 919 } 920 } 921 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 922 switch (n->Opcode()) { 923 case Op_ClearArray: 924 midx = Compile::AliasIdxRaw; 925 mat = TypeRawPtr::BOTTOM; 926 break; 927 } 928 } 929 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 930 switch (n->Opcode()) { 931 case Op_Return: 932 case Op_Rethrow: 933 case Op_Halt: 934 case Op_TailCall: 935 case Op_TailJump: 936 nidx = Compile::AliasIdxBot; 937 nat = TypePtr::BOTTOM; 938 break; 939 } 940 } 941 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 942 switch (n->Opcode()) { 943 case Op_StrComp: 944 case Op_StrEquals: 945 case Op_StrIndexOf: 946 case Op_StrIndexOfChar: 947 case Op_AryEq: 948 case Op_HasNegatives: 949 case Op_MemBarVolatile: 950 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 951 case Op_StrInflatedCopy: 952 case Op_StrCompressedCopy: 953 case Op_OnSpinWait: 954 case Op_EncodeISOArray: 955 nidx = Compile::AliasIdxTop; 956 nat = NULL; 957 break; 958 } 959 } 960 if (nidx != midx) { 961 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 962 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 963 n->dump(); 964 m->dump(); 965 } 966 assert(C->subsume_loads() && C->must_alias(nat, midx), 967 "must not lose alias info when matching"); 968 } 969 } 970 #endif 971 972 //------------------------------xform------------------------------------------ 973 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine 974 // Node in new-space. Given a new-space Node, recursively walk his children. 975 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 976 Node *Matcher::xform( Node *n, int max_stack ) { 977 // Use one stack to keep both: child's node/state and parent's node/index 978 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 979 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 980 while (mstack.is_nonempty()) { 981 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 982 if (C->failing()) return NULL; 983 n = mstack.node(); // Leave node on stack 984 Node_State nstate = mstack.state(); 985 if (nstate == Visit) { 986 mstack.set_state(Post_Visit); 987 Node *oldn = n; 988 // Old-space or new-space check 989 if (!C->node_arena()->contains(n)) { 990 // Old space! 991 Node* m; 992 if (has_new_node(n)) { // Not yet Label/Reduced 993 m = new_node(n); 994 } else { 995 if (!is_dontcare(n)) { // Matcher can match this guy 996 // Calls match special. They match alone with no children. 997 // Their children, the incoming arguments, match normally. 998 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 999 if (C->failing()) return NULL; 1000 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1001 } else { // Nothing the matcher cares about 1002 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections? 1003 // Convert to machine-dependent projection 1004 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1005 #ifdef ASSERT 1006 _new2old_map.map(m->_idx, n); 1007 #endif 1008 if (m->in(0) != NULL) // m might be top 1009 collect_null_checks(m, n); 1010 } else { // Else just a regular 'ol guy 1011 m = n->clone(); // So just clone into new-space 1012 #ifdef ASSERT 1013 _new2old_map.map(m->_idx, n); 1014 #endif 1015 // Def-Use edges will be added incrementally as Uses 1016 // of this node are matched. 1017 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1018 } 1019 } 1020 1021 set_new_node(n, m); // Map old to new 1022 if (_old_node_note_array != NULL) { 1023 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1024 n->_idx); 1025 C->set_node_notes_at(m->_idx, nn); 1026 } 1027 debug_only(match_alias_type(C, n, m)); 1028 } 1029 n = m; // n is now a new-space node 1030 mstack.set_node(n); 1031 } 1032 1033 // New space! 1034 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1035 1036 int i; 1037 // Put precedence edges on stack first (match them last). 1038 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1039 Node *m = oldn->in(i); 1040 if (m == NULL) break; 1041 // set -1 to call add_prec() instead of set_req() during Step1 1042 mstack.push(m, Visit, n, -1); 1043 } 1044 1045 // Handle precedence edges for interior nodes 1046 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1047 Node *m = n->in(i); 1048 if (m == NULL || C->node_arena()->contains(m)) continue; 1049 n->rm_prec(i); 1050 // set -1 to call add_prec() instead of set_req() during Step1 1051 mstack.push(m, Visit, n, -1); 1052 } 1053 1054 // For constant debug info, I'd rather have unmatched constants. 1055 int cnt = n->req(); 1056 JVMState* jvms = n->jvms(); 1057 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1058 1059 // Now do only debug info. Clone constants rather than matching. 1060 // Constants are represented directly in the debug info without 1061 // the need for executable machine instructions. 1062 // Monitor boxes are also represented directly. 1063 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1064 Node *m = n->in(i); // Get input 1065 int op = m->Opcode(); 1066 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1067 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1068 op == Op_ConF || op == Op_ConD || op == Op_ConL 1069 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1070 ) { 1071 m = m->clone(); 1072 #ifdef ASSERT 1073 _new2old_map.map(m->_idx, n); 1074 #endif 1075 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1076 mstack.push(m->in(0), Visit, m, 0); 1077 } else { 1078 mstack.push(m, Visit, n, i); 1079 } 1080 } 1081 1082 // And now walk his children, and convert his inputs to new-space. 1083 for( ; i >= 0; --i ) { // For all normal inputs do 1084 Node *m = n->in(i); // Get input 1085 if(m != NULL) 1086 mstack.push(m, Visit, n, i); 1087 } 1088 1089 } 1090 else if (nstate == Post_Visit) { 1091 // Set xformed input 1092 Node *p = mstack.parent(); 1093 if (p != NULL) { // root doesn't have parent 1094 int i = (int)mstack.index(); 1095 if (i >= 0) 1096 p->set_req(i, n); // required input 1097 else if (i == -1) 1098 p->add_prec(n); // precedence input 1099 else 1100 ShouldNotReachHere(); 1101 } 1102 mstack.pop(); // remove processed node from stack 1103 } 1104 else { 1105 ShouldNotReachHere(); 1106 } 1107 } // while (mstack.is_nonempty()) 1108 return n; // Return new-space Node 1109 } 1110 1111 //------------------------------warp_outgoing_stk_arg------------------------ 1112 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1113 // Convert outgoing argument location to a pre-biased stack offset 1114 if (reg->is_stack()) { 1115 OptoReg::Name warped = reg->reg2stack(); 1116 // Adjust the stack slot offset to be the register number used 1117 // by the allocator. 1118 warped = OptoReg::add(begin_out_arg_area, warped); 1119 // Keep track of the largest numbered stack slot used for an arg. 1120 // Largest used slot per call-site indicates the amount of stack 1121 // that is killed by the call. 1122 if( warped >= out_arg_limit_per_call ) 1123 out_arg_limit_per_call = OptoReg::add(warped,1); 1124 if (!RegMask::can_represent_arg(warped)) { 1125 C->record_method_not_compilable("unsupported calling sequence"); 1126 return OptoReg::Bad; 1127 } 1128 return warped; 1129 } 1130 return OptoReg::as_OptoReg(reg); 1131 } 1132 1133 1134 //------------------------------match_sfpt------------------------------------- 1135 // Helper function to match call instructions. Calls match special. 1136 // They match alone with no children. Their children, the incoming 1137 // arguments, match normally. 1138 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1139 MachSafePointNode *msfpt = NULL; 1140 MachCallNode *mcall = NULL; 1141 uint cnt; 1142 // Split out case for SafePoint vs Call 1143 CallNode *call; 1144 const TypeTuple *domain; 1145 ciMethod* method = NULL; 1146 bool is_method_handle_invoke = false; // for special kill effects 1147 if( sfpt->is_Call() ) { 1148 call = sfpt->as_Call(); 1149 domain = call->tf()->domain(); 1150 cnt = domain->cnt(); 1151 1152 // Match just the call, nothing else 1153 MachNode *m = match_tree(call); 1154 if (C->failing()) return NULL; 1155 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1156 1157 // Copy data from the Ideal SafePoint to the machine version 1158 mcall = m->as_MachCall(); 1159 1160 mcall->set_tf( call->tf()); 1161 mcall->set_entry_point(call->entry_point()); 1162 mcall->set_cnt( call->cnt()); 1163 1164 if( mcall->is_MachCallJava() ) { 1165 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1166 const CallJavaNode *call_java = call->as_CallJava(); 1167 method = call_java->method(); 1168 mcall_java->_method = method; 1169 mcall_java->_bci = call_java->_bci; 1170 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1171 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1172 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1173 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1174 if (is_method_handle_invoke) { 1175 C->set_has_method_handle_invokes(true); 1176 } 1177 if( mcall_java->is_MachCallStaticJava() ) 1178 mcall_java->as_MachCallStaticJava()->_name = 1179 call_java->as_CallStaticJava()->_name; 1180 if( mcall_java->is_MachCallDynamicJava() ) 1181 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1182 call_java->as_CallDynamicJava()->_vtable_index; 1183 } 1184 else if( mcall->is_MachCallRuntime() ) { 1185 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1186 } 1187 msfpt = mcall; 1188 } 1189 // This is a non-call safepoint 1190 else { 1191 call = NULL; 1192 domain = NULL; 1193 MachNode *mn = match_tree(sfpt); 1194 if (C->failing()) return NULL; 1195 msfpt = mn->as_MachSafePoint(); 1196 cnt = TypeFunc::Parms; 1197 } 1198 1199 // Advertise the correct memory effects (for anti-dependence computation). 1200 msfpt->set_adr_type(sfpt->adr_type()); 1201 1202 // Allocate a private array of RegMasks. These RegMasks are not shared. 1203 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1204 // Empty them all. 1205 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); 1206 1207 // Do all the pre-defined non-Empty register masks 1208 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1209 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1210 1211 // Place first outgoing argument can possibly be put. 1212 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1213 assert( is_even(begin_out_arg_area), "" ); 1214 // Compute max outgoing register number per call site. 1215 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1216 // Calls to C may hammer extra stack slots above and beyond any arguments. 1217 // These are usually backing store for register arguments for varargs. 1218 if( call != NULL && call->is_CallRuntime() ) 1219 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1220 1221 1222 // Do the normal argument list (parameters) register masks 1223 int argcnt = cnt - TypeFunc::Parms; 1224 if( argcnt > 0 ) { // Skip it all if we have no args 1225 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1226 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1227 int i; 1228 for( i = 0; i < argcnt; i++ ) { 1229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1230 } 1231 // V-call to pick proper calling convention 1232 call->calling_convention( sig_bt, parm_regs, argcnt ); 1233 1234 #ifdef ASSERT 1235 // Sanity check users' calling convention. Really handy during 1236 // the initial porting effort. Fairly expensive otherwise. 1237 { for (int i = 0; i<argcnt; i++) { 1238 if( !parm_regs[i].first()->is_valid() && 1239 !parm_regs[i].second()->is_valid() ) continue; 1240 VMReg reg1 = parm_regs[i].first(); 1241 VMReg reg2 = parm_regs[i].second(); 1242 for (int j = 0; j < i; j++) { 1243 if( !parm_regs[j].first()->is_valid() && 1244 !parm_regs[j].second()->is_valid() ) continue; 1245 VMReg reg3 = parm_regs[j].first(); 1246 VMReg reg4 = parm_regs[j].second(); 1247 if( !reg1->is_valid() ) { 1248 assert( !reg2->is_valid(), "valid halvsies" ); 1249 } else if( !reg3->is_valid() ) { 1250 assert( !reg4->is_valid(), "valid halvsies" ); 1251 } else { 1252 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1253 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1254 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1255 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1256 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1257 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1258 } 1259 } 1260 } 1261 } 1262 #endif 1263 1264 // Visit each argument. Compute its outgoing register mask. 1265 // Return results now can have 2 bits returned. 1266 // Compute max over all outgoing arguments both per call-site 1267 // and over the entire method. 1268 for( i = 0; i < argcnt; i++ ) { 1269 // Address of incoming argument mask to fill in 1270 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1271 if( !parm_regs[i].first()->is_valid() && 1272 !parm_regs[i].second()->is_valid() ) { 1273 continue; // Avoid Halves 1274 } 1275 // Grab first register, adjust stack slots and insert in mask. 1276 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1277 if (OptoReg::is_valid(reg1)) 1278 rm->Insert( reg1 ); 1279 // Grab second register (if any), adjust stack slots and insert in mask. 1280 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1281 if (OptoReg::is_valid(reg2)) 1282 rm->Insert( reg2 ); 1283 } // End of for all arguments 1284 1285 // Compute number of stack slots needed to restore stack in case of 1286 // Pascal-style argument popping. 1287 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1288 } 1289 1290 // Compute the max stack slot killed by any call. These will not be 1291 // available for debug info, and will be used to adjust FIRST_STACK_mask 1292 // after all call sites have been visited. 1293 if( _out_arg_limit < out_arg_limit_per_call) 1294 _out_arg_limit = out_arg_limit_per_call; 1295 1296 if (mcall) { 1297 // Kill the outgoing argument area, including any non-argument holes and 1298 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1299 // Since the max-per-method covers the max-per-call-site and debug info 1300 // is excluded on the max-per-method basis, debug info cannot land in 1301 // this killed area. 1302 uint r_cnt = mcall->tf()->range()->cnt(); 1303 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1304 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1305 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1306 } else { 1307 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1308 proj->_rout.Insert(OptoReg::Name(i)); 1309 } 1310 if (proj->_rout.is_NotEmpty()) { 1311 push_projection(proj); 1312 } 1313 } 1314 // Transfer the safepoint information from the call to the mcall 1315 // Move the JVMState list 1316 msfpt->set_jvms(sfpt->jvms()); 1317 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1318 jvms->set_map(sfpt); 1319 } 1320 1321 // Debug inputs begin just after the last incoming parameter 1322 assert((mcall == NULL) || (mcall->jvms() == NULL) || 1323 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), ""); 1324 1325 // Move the OopMap 1326 msfpt->_oop_map = sfpt->_oop_map; 1327 1328 // Add additional edges. 1329 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1330 // For these calls we can not add MachConstantBase in expand(), as the 1331 // ins are not complete then. 1332 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1333 if (msfpt->jvms() && 1334 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1335 // We added an edge before jvms, so we must adapt the position of the ins. 1336 msfpt->jvms()->adapt_position(+1); 1337 } 1338 } 1339 1340 // Registers killed by the call are set in the local scheduling pass 1341 // of Global Code Motion. 1342 return msfpt; 1343 } 1344 1345 //---------------------------match_tree---------------------------------------- 1346 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1347 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1348 // making GotoNodes while building the CFG and in init_spill_mask() to identify 1349 // a Load's result RegMask for memoization in idealreg2regmask[] 1350 MachNode *Matcher::match_tree( const Node *n ) { 1351 assert( n->Opcode() != Op_Phi, "cannot match" ); 1352 assert( !n->is_block_start(), "cannot match" ); 1353 // Set the mark for all locally allocated State objects. 1354 // When this call returns, the _states_arena arena will be reset 1355 // freeing all State objects. 1356 ResourceMark rm( &_states_arena ); 1357 1358 LabelRootDepth = 0; 1359 1360 // StoreNodes require their Memory input to match any LoadNodes 1361 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1362 #ifdef ASSERT 1363 Node* save_mem_node = _mem_node; 1364 _mem_node = n->is_Store() ? (Node*)n : NULL; 1365 #endif 1366 // State object for root node of match tree 1367 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1368 State *s = new (&_states_arena) State; 1369 s->_kids[0] = NULL; 1370 s->_kids[1] = NULL; 1371 s->_leaf = (Node*)n; 1372 // Label the input tree, allocating labels from top-level arena 1373 Label_Root( n, s, n->in(0), mem ); 1374 if (C->failing()) return NULL; 1375 1376 // The minimum cost match for the whole tree is found at the root State 1377 uint mincost = max_juint; 1378 uint cost = max_juint; 1379 uint i; 1380 for( i = 0; i < NUM_OPERANDS; i++ ) { 1381 if( s->valid(i) && // valid entry and 1382 s->_cost[i] < cost && // low cost and 1383 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1384 cost = s->_cost[mincost=i]; 1385 } 1386 if (mincost == max_juint) { 1387 #ifndef PRODUCT 1388 tty->print("No matching rule for:"); 1389 s->dump(); 1390 #endif 1391 Matcher::soft_match_failure(); 1392 return NULL; 1393 } 1394 // Reduce input tree based upon the state labels to machine Nodes 1395 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1396 #ifdef ASSERT 1397 _old2new_map.map(n->_idx, m); 1398 _new2old_map.map(m->_idx, (Node*)n); 1399 #endif 1400 1401 // Add any Matcher-ignored edges 1402 uint cnt = n->req(); 1403 uint start = 1; 1404 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1405 if( n->is_AddP() ) { 1406 assert( mem == (Node*)1, "" ); 1407 start = AddPNode::Base+1; 1408 } 1409 for( i = start; i < cnt; i++ ) { 1410 if( !n->match_edge(i) ) { 1411 if( i < m->req() ) 1412 m->ins_req( i, n->in(i) ); 1413 else 1414 m->add_req( n->in(i) ); 1415 } 1416 } 1417 1418 debug_only( _mem_node = save_mem_node; ) 1419 return m; 1420 } 1421 1422 1423 //------------------------------match_into_reg--------------------------------- 1424 // Choose to either match this Node in a register or part of the current 1425 // match tree. Return true for requiring a register and false for matching 1426 // as part of the current match tree. 1427 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1428 1429 const Type *t = m->bottom_type(); 1430 1431 if (t->singleton()) { 1432 // Never force constants into registers. Allow them to match as 1433 // constants or registers. Copies of the same value will share 1434 // the same register. See find_shared_node. 1435 return false; 1436 } else { // Not a constant 1437 // Stop recursion if they have different Controls. 1438 Node* m_control = m->in(0); 1439 // Control of load's memory can post-dominates load's control. 1440 // So use it since load can't float above its memory. 1441 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1442 if (control && m_control && control != m_control && control != mem_control) { 1443 1444 // Actually, we can live with the most conservative control we 1445 // find, if it post-dominates the others. This allows us to 1446 // pick up load/op/store trees where the load can float a little 1447 // above the store. 1448 Node *x = control; 1449 const uint max_scan = 6; // Arbitrary scan cutoff 1450 uint j; 1451 for (j=0; j<max_scan; j++) { 1452 if (x->is_Region()) // Bail out at merge points 1453 return true; 1454 x = x->in(0); 1455 if (x == m_control) // Does 'control' post-dominate 1456 break; // m->in(0)? If so, we can use it 1457 if (x == mem_control) // Does 'control' post-dominate 1458 break; // mem_control? If so, we can use it 1459 } 1460 if (j == max_scan) // No post-domination before scan end? 1461 return true; // Then break the match tree up 1462 } 1463 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1464 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1465 // These are commonly used in address expressions and can 1466 // efficiently fold into them on X64 in some cases. 1467 return false; 1468 } 1469 } 1470 1471 // Not forceable cloning. If shared, put it into a register. 1472 return shared; 1473 } 1474 1475 1476 //------------------------------Instruction Selection-------------------------- 1477 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1478 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1479 // things the Matcher does not match (e.g., Memory), and things with different 1480 // Controls (hence forced into different blocks). We pass in the Control 1481 // selected for this entire State tree. 1482 1483 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1484 // Store and the Load must have identical Memories (as well as identical 1485 // pointers). Since the Matcher does not have anything for Memory (and 1486 // does not handle DAGs), I have to match the Memory input myself. If the 1487 // Tree root is a Store, I require all Loads to have the identical memory. 1488 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1489 // Since Label_Root is a recursive function, its possible that we might run 1490 // out of stack space. See bugs 6272980 & 6227033 for more info. 1491 LabelRootDepth++; 1492 if (LabelRootDepth > MaxLabelRootDepth) { 1493 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1494 return NULL; 1495 } 1496 uint care = 0; // Edges matcher cares about 1497 uint cnt = n->req(); 1498 uint i = 0; 1499 1500 // Examine children for memory state 1501 // Can only subsume a child into your match-tree if that child's memory state 1502 // is not modified along the path to another input. 1503 // It is unsafe even if the other inputs are separate roots. 1504 Node *input_mem = NULL; 1505 for( i = 1; i < cnt; i++ ) { 1506 if( !n->match_edge(i) ) continue; 1507 Node *m = n->in(i); // Get ith input 1508 assert( m, "expect non-null children" ); 1509 if( m->is_Load() ) { 1510 if( input_mem == NULL ) { 1511 input_mem = m->in(MemNode::Memory); 1512 } else if( input_mem != m->in(MemNode::Memory) ) { 1513 input_mem = NodeSentinel; 1514 } 1515 } 1516 } 1517 1518 for( i = 1; i < cnt; i++ ){// For my children 1519 if( !n->match_edge(i) ) continue; 1520 Node *m = n->in(i); // Get ith input 1521 // Allocate states out of a private arena 1522 State *s = new (&_states_arena) State; 1523 svec->_kids[care++] = s; 1524 assert( care <= 2, "binary only for now" ); 1525 1526 // Recursively label the State tree. 1527 s->_kids[0] = NULL; 1528 s->_kids[1] = NULL; 1529 s->_leaf = m; 1530 1531 // Check for leaves of the State Tree; things that cannot be a part of 1532 // the current tree. If it finds any, that value is matched as a 1533 // register operand. If not, then the normal matching is used. 1534 if( match_into_reg(n, m, control, i, is_shared(m)) || 1535 // 1536 // Stop recursion if this is LoadNode and the root of this tree is a 1537 // StoreNode and the load & store have different memories. 1538 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1539 // Can NOT include the match of a subtree when its memory state 1540 // is used by any of the other subtrees 1541 (input_mem == NodeSentinel) ) { 1542 // Print when we exclude matching due to different memory states at input-loads 1543 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1544 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1545 tty->print_cr("invalid input_mem"); 1546 } 1547 // Switch to a register-only opcode; this value must be in a register 1548 // and cannot be subsumed as part of a larger instruction. 1549 s->DFA( m->ideal_reg(), m ); 1550 1551 } else { 1552 // If match tree has no control and we do, adopt it for entire tree 1553 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1554 control = m->in(0); // Pick up control 1555 // Else match as a normal part of the match tree. 1556 control = Label_Root(m,s,control,mem); 1557 if (C->failing()) return NULL; 1558 } 1559 } 1560 1561 1562 // Call DFA to match this node, and return 1563 svec->DFA( n->Opcode(), n ); 1564 1565 #ifdef ASSERT 1566 uint x; 1567 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1568 if( svec->valid(x) ) 1569 break; 1570 1571 if (x >= _LAST_MACH_OPER) { 1572 n->dump(); 1573 svec->dump(); 1574 assert( false, "bad AD file" ); 1575 } 1576 #endif 1577 return control; 1578 } 1579 1580 1581 // Con nodes reduced using the same rule can share their MachNode 1582 // which reduces the number of copies of a constant in the final 1583 // program. The register allocator is free to split uses later to 1584 // split live ranges. 1585 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1586 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1587 1588 // See if this Con has already been reduced using this rule. 1589 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1590 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1591 if (last != NULL && rule == last->rule()) { 1592 // Don't expect control change for DecodeN 1593 if (leaf->is_DecodeNarrowPtr()) 1594 return last; 1595 // Get the new space root. 1596 Node* xroot = new_node(C->root()); 1597 if (xroot == NULL) { 1598 // This shouldn't happen give the order of matching. 1599 return NULL; 1600 } 1601 1602 // Shared constants need to have their control be root so they 1603 // can be scheduled properly. 1604 Node* control = last->in(0); 1605 if (control != xroot) { 1606 if (control == NULL || control == C->root()) { 1607 last->set_req(0, xroot); 1608 } else { 1609 assert(false, "unexpected control"); 1610 return NULL; 1611 } 1612 } 1613 return last; 1614 } 1615 return NULL; 1616 } 1617 1618 1619 //------------------------------ReduceInst------------------------------------- 1620 // Reduce a State tree (with given Control) into a tree of MachNodes. 1621 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1622 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1623 // Each MachNode has a number of complicated MachOper operands; each 1624 // MachOper also covers a further tree of Ideal Nodes. 1625 1626 // The root of the Ideal match tree is always an instruction, so we enter 1627 // the recursion here. After building the MachNode, we need to recurse 1628 // the tree checking for these cases: 1629 // (1) Child is an instruction - 1630 // Build the instruction (recursively), add it as an edge. 1631 // Build a simple operand (register) to hold the result of the instruction. 1632 // (2) Child is an interior part of an instruction - 1633 // Skip over it (do nothing) 1634 // (3) Child is the start of a operand - 1635 // Build the operand, place it inside the instruction 1636 // Call ReduceOper. 1637 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1638 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1639 1640 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1641 if (shared_node != NULL) { 1642 return shared_node; 1643 } 1644 1645 // Build the object to represent this state & prepare for recursive calls 1646 MachNode *mach = s->MachNodeGenerator(rule); 1647 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1648 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1649 Node *leaf = s->_leaf; 1650 // Check for instruction or instruction chain rule 1651 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1652 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1653 "duplicating node that's already been matched"); 1654 // Instruction 1655 mach->add_req( leaf->in(0) ); // Set initial control 1656 // Reduce interior of complex instruction 1657 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1658 } else { 1659 // Instruction chain rules are data-dependent on their inputs 1660 mach->add_req(0); // Set initial control to none 1661 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1662 } 1663 1664 // If a Memory was used, insert a Memory edge 1665 if( mem != (Node*)1 ) { 1666 mach->ins_req(MemNode::Memory,mem); 1667 #ifdef ASSERT 1668 // Verify adr type after matching memory operation 1669 const MachOper* oper = mach->memory_operand(); 1670 if (oper != NULL && oper != (MachOper*)-1) { 1671 // It has a unique memory operand. Find corresponding ideal mem node. 1672 Node* m = NULL; 1673 if (leaf->is_Mem()) { 1674 m = leaf; 1675 } else { 1676 m = _mem_node; 1677 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1678 } 1679 const Type* mach_at = mach->adr_type(); 1680 // DecodeN node consumed by an address may have different type 1681 // then its input. Don't compare types for such case. 1682 if (m->adr_type() != mach_at && 1683 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1684 m->in(MemNode::Address)->is_AddP() && 1685 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() || 1686 m->in(MemNode::Address)->is_AddP() && 1687 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1688 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) { 1689 mach_at = m->adr_type(); 1690 } 1691 if (m->adr_type() != mach_at) { 1692 m->dump(); 1693 tty->print_cr("mach:"); 1694 mach->dump(1); 1695 } 1696 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1697 } 1698 #endif 1699 } 1700 1701 // If the _leaf is an AddP, insert the base edge 1702 if (leaf->is_AddP()) { 1703 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1704 } 1705 1706 uint number_of_projections_prior = number_of_projections(); 1707 1708 // Perform any 1-to-many expansions required 1709 MachNode *ex = mach->Expand(s, _projection_list, mem); 1710 if (ex != mach) { 1711 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1712 if( ex->in(1)->is_Con() ) 1713 ex->in(1)->set_req(0, C->root()); 1714 // Remove old node from the graph 1715 for( uint i=0; i<mach->req(); i++ ) { 1716 mach->set_req(i,NULL); 1717 } 1718 #ifdef ASSERT 1719 _new2old_map.map(ex->_idx, s->_leaf); 1720 #endif 1721 } 1722 1723 // PhaseChaitin::fixup_spills will sometimes generate spill code 1724 // via the matcher. By the time, nodes have been wired into the CFG, 1725 // and any further nodes generated by expand rules will be left hanging 1726 // in space, and will not get emitted as output code. Catch this. 1727 // Also, catch any new register allocation constraints ("projections") 1728 // generated belatedly during spill code generation. 1729 if (_allocation_started) { 1730 guarantee(ex == mach, "no expand rules during spill generation"); 1731 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1732 } 1733 1734 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1735 // Record the con for sharing 1736 _shared_nodes.map(leaf->_idx, ex); 1737 } 1738 1739 return ex; 1740 } 1741 1742 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1743 for (uint i = n->req(); i < n->len(); i++) { 1744 if (n->in(i) != NULL) { 1745 mach->add_prec(n->in(i)); 1746 } 1747 } 1748 } 1749 1750 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1751 // 'op' is what I am expecting to receive 1752 int op = _leftOp[rule]; 1753 // Operand type to catch childs result 1754 // This is what my child will give me. 1755 int opnd_class_instance = s->_rule[op]; 1756 // Choose between operand class or not. 1757 // This is what I will receive. 1758 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1759 // New rule for child. Chase operand classes to get the actual rule. 1760 int newrule = s->_rule[catch_op]; 1761 1762 if( newrule < NUM_OPERANDS ) { 1763 // Chain from operand or operand class, may be output of shared node 1764 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1765 "Bad AD file: Instruction chain rule must chain from operand"); 1766 // Insert operand into array of operands for this instruction 1767 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1768 1769 ReduceOper( s, newrule, mem, mach ); 1770 } else { 1771 // Chain from the result of an instruction 1772 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1773 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1774 Node *mem1 = (Node*)1; 1775 debug_only(Node *save_mem_node = _mem_node;) 1776 mach->add_req( ReduceInst(s, newrule, mem1) ); 1777 debug_only(_mem_node = save_mem_node;) 1778 } 1779 return; 1780 } 1781 1782 1783 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1784 handle_precedence_edges(s->_leaf, mach); 1785 1786 if( s->_leaf->is_Load() ) { 1787 Node *mem2 = s->_leaf->in(MemNode::Memory); 1788 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1789 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1790 mem = mem2; 1791 } 1792 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1793 if( mach->in(0) == NULL ) 1794 mach->set_req(0, s->_leaf->in(0)); 1795 } 1796 1797 // Now recursively walk the state tree & add operand list. 1798 for( uint i=0; i<2; i++ ) { // binary tree 1799 State *newstate = s->_kids[i]; 1800 if( newstate == NULL ) break; // Might only have 1 child 1801 // 'op' is what I am expecting to receive 1802 int op; 1803 if( i == 0 ) { 1804 op = _leftOp[rule]; 1805 } else { 1806 op = _rightOp[rule]; 1807 } 1808 // Operand type to catch childs result 1809 // This is what my child will give me. 1810 int opnd_class_instance = newstate->_rule[op]; 1811 // Choose between operand class or not. 1812 // This is what I will receive. 1813 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1814 // New rule for child. Chase operand classes to get the actual rule. 1815 int newrule = newstate->_rule[catch_op]; 1816 1817 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1818 // Operand/operandClass 1819 // Insert operand into array of operands for this instruction 1820 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 1821 ReduceOper( newstate, newrule, mem, mach ); 1822 1823 } else { // Child is internal operand or new instruction 1824 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1825 // internal operand --> call ReduceInst_Interior 1826 // Interior of complex instruction. Do nothing but recurse. 1827 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1828 } else { 1829 // instruction --> call build operand( ) to catch result 1830 // --> ReduceInst( newrule ) 1831 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 1832 Node *mem1 = (Node*)1; 1833 debug_only(Node *save_mem_node = _mem_node;) 1834 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1835 debug_only(_mem_node = save_mem_node;) 1836 } 1837 } 1838 assert( mach->_opnds[num_opnds-1], "" ); 1839 } 1840 return num_opnds; 1841 } 1842 1843 // This routine walks the interior of possible complex operands. 1844 // At each point we check our children in the match tree: 1845 // (1) No children - 1846 // We are a leaf; add _leaf field as an input to the MachNode 1847 // (2) Child is an internal operand - 1848 // Skip over it ( do nothing ) 1849 // (3) Child is an instruction - 1850 // Call ReduceInst recursively and 1851 // and instruction as an input to the MachNode 1852 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1853 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1854 State *kid = s->_kids[0]; 1855 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1856 1857 // Leaf? And not subsumed? 1858 if( kid == NULL && !_swallowed[rule] ) { 1859 mach->add_req( s->_leaf ); // Add leaf pointer 1860 return; // Bail out 1861 } 1862 1863 if( s->_leaf->is_Load() ) { 1864 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1865 mem = s->_leaf->in(MemNode::Memory); 1866 debug_only(_mem_node = s->_leaf;) 1867 } 1868 1869 handle_precedence_edges(s->_leaf, mach); 1870 1871 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1872 if( !mach->in(0) ) 1873 mach->set_req(0,s->_leaf->in(0)); 1874 else { 1875 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1876 } 1877 } 1878 1879 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1880 int newrule; 1881 if( i == 0) 1882 newrule = kid->_rule[_leftOp[rule]]; 1883 else 1884 newrule = kid->_rule[_rightOp[rule]]; 1885 1886 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1887 // Internal operand; recurse but do nothing else 1888 ReduceOper( kid, newrule, mem, mach ); 1889 1890 } else { // Child is a new instruction 1891 // Reduce the instruction, and add a direct pointer from this 1892 // machine instruction to the newly reduced one. 1893 Node *mem1 = (Node*)1; 1894 debug_only(Node *save_mem_node = _mem_node;) 1895 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1896 debug_only(_mem_node = save_mem_node;) 1897 } 1898 } 1899 } 1900 1901 1902 // ------------------------------------------------------------------------- 1903 // Java-Java calling convention 1904 // (what you use when Java calls Java) 1905 1906 //------------------------------find_receiver---------------------------------- 1907 // For a given signature, return the OptoReg for parameter 0. 1908 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1909 VMRegPair regs; 1910 BasicType sig_bt = T_OBJECT; 1911 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1912 // Return argument 0 register. In the LP64 build pointers 1913 // take 2 registers, but the VM wants only the 'main' name. 1914 return OptoReg::as_OptoReg(regs.first()); 1915 } 1916 1917 // This function identifies sub-graphs in which a 'load' node is 1918 // input to two different nodes, and such that it can be matched 1919 // with BMI instructions like blsi, blsr, etc. 1920 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32. 1921 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL* 1922 // refers to the same node. 1923 #ifdef X86 1924 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop) 1925 // This is a temporary solution until we make DAGs expressible in ADL. 1926 template<typename ConType> 1927 class FusedPatternMatcher { 1928 Node* _op1_node; 1929 Node* _mop_node; 1930 int _con_op; 1931 1932 static int match_next(Node* n, int next_op, int next_op_idx) { 1933 if (n->in(1) == NULL || n->in(2) == NULL) { 1934 return -1; 1935 } 1936 1937 if (next_op_idx == -1) { // n is commutative, try rotations 1938 if (n->in(1)->Opcode() == next_op) { 1939 return 1; 1940 } else if (n->in(2)->Opcode() == next_op) { 1941 return 2; 1942 } 1943 } else { 1944 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index"); 1945 if (n->in(next_op_idx)->Opcode() == next_op) { 1946 return next_op_idx; 1947 } 1948 } 1949 return -1; 1950 } 1951 public: 1952 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) : 1953 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { } 1954 1955 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative 1956 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative 1957 typename ConType::NativeType con_value) { 1958 if (_op1_node->Opcode() != op1) { 1959 return false; 1960 } 1961 if (_mop_node->outcnt() > 2) { 1962 return false; 1963 } 1964 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx); 1965 if (op1_op2_idx == -1) { 1966 return false; 1967 } 1968 // Memory operation must be the other edge 1969 int op1_mop_idx = (op1_op2_idx & 1) + 1; 1970 1971 // Check that the mop node is really what we want 1972 if (_op1_node->in(op1_mop_idx) == _mop_node) { 1973 Node *op2_node = _op1_node->in(op1_op2_idx); 1974 if (op2_node->outcnt() > 1) { 1975 return false; 1976 } 1977 assert(op2_node->Opcode() == op2, "Should be"); 1978 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx); 1979 if (op2_con_idx == -1) { 1980 return false; 1981 } 1982 // Memory operation must be the other edge 1983 int op2_mop_idx = (op2_con_idx & 1) + 1; 1984 // Check that the memory operation is the same node 1985 if (op2_node->in(op2_mop_idx) == _mop_node) { 1986 // Now check the constant 1987 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type(); 1988 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) { 1989 return true; 1990 } 1991 } 1992 } 1993 return false; 1994 } 1995 }; 1996 1997 1998 bool Matcher::is_bmi_pattern(Node *n, Node *m) { 1999 if (n != NULL && m != NULL) { 2000 if (m->Opcode() == Op_LoadI) { 2001 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI); 2002 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) || 2003 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) || 2004 bmii.match(Op_XorI, -1, Op_AddI, -1, -1); 2005 } else if (m->Opcode() == Op_LoadL) { 2006 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL); 2007 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) || 2008 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) || 2009 bmil.match(Op_XorL, -1, Op_AddL, -1, -1); 2010 } 2011 } 2012 return false; 2013 } 2014 #endif // X86 2015 2016 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2017 Node *off = m->in(AddPNode::Offset); 2018 if (off->is_Con()) { 2019 address_visited.test_set(m->_idx); // Flag as address_visited 2020 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2021 // Clone X+offset as it also folds into most addressing expressions 2022 mstack.push(off, Visit); 2023 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2024 return true; 2025 } 2026 return false; 2027 } 2028 2029 // A method-klass-holder may be passed in the inline_cache_reg 2030 // and then expanded into the inline_cache_reg and a method_oop register 2031 // defined in ad_<arch>.cpp 2032 2033 //------------------------------find_shared------------------------------------ 2034 // Set bits if Node is shared or otherwise a root 2035 void Matcher::find_shared( Node *n ) { 2036 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2037 MStack mstack(C->live_nodes() * 2); 2038 // Mark nodes as address_visited if they are inputs to an address expression 2039 VectorSet address_visited(Thread::current()->resource_area()); 2040 mstack.push(n, Visit); // Don't need to pre-visit root node 2041 while (mstack.is_nonempty()) { 2042 n = mstack.node(); // Leave node on stack 2043 Node_State nstate = mstack.state(); 2044 uint nop = n->Opcode(); 2045 if (nstate == Pre_Visit) { 2046 if (address_visited.test(n->_idx)) { // Visited in address already? 2047 // Flag as visited and shared now. 2048 set_visited(n); 2049 } 2050 if (is_visited(n)) { // Visited already? 2051 // Node is shared and has no reason to clone. Flag it as shared. 2052 // This causes it to match into a register for the sharing. 2053 set_shared(n); // Flag as shared and 2054 mstack.pop(); // remove node from stack 2055 continue; 2056 } 2057 nstate = Visit; // Not already visited; so visit now 2058 } 2059 if (nstate == Visit) { 2060 mstack.set_state(Post_Visit); 2061 set_visited(n); // Flag as visited now 2062 bool mem_op = false; 2063 2064 switch( nop ) { // Handle some opcodes special 2065 case Op_Phi: // Treat Phis as shared roots 2066 case Op_Parm: 2067 case Op_Proj: // All handled specially during matching 2068 case Op_SafePointScalarObject: 2069 set_shared(n); 2070 set_dontcare(n); 2071 break; 2072 case Op_If: 2073 case Op_CountedLoopEnd: 2074 mstack.set_state(Alt_Post_Visit); // Alternative way 2075 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2076 // with matching cmp/branch in 1 instruction. The Matcher needs the 2077 // Bool and CmpX side-by-side, because it can only get at constants 2078 // that are at the leaves of Match trees, and the Bool's condition acts 2079 // as a constant here. 2080 mstack.push(n->in(1), Visit); // Clone the Bool 2081 mstack.push(n->in(0), Pre_Visit); // Visit control input 2082 continue; // while (mstack.is_nonempty()) 2083 case Op_ConvI2D: // These forms efficiently match with a prior 2084 case Op_ConvI2F: // Load but not a following Store 2085 if( n->in(1)->is_Load() && // Prior load 2086 n->outcnt() == 1 && // Not already shared 2087 n->unique_out()->is_Store() ) // Following store 2088 set_shared(n); // Force it to be a root 2089 break; 2090 case Op_ReverseBytesI: 2091 case Op_ReverseBytesL: 2092 if( n->in(1)->is_Load() && // Prior load 2093 n->outcnt() == 1 ) // Not already shared 2094 set_shared(n); // Force it to be a root 2095 break; 2096 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 2097 case Op_IfFalse: 2098 case Op_IfTrue: 2099 case Op_MachProj: 2100 case Op_MergeMem: 2101 case Op_Catch: 2102 case Op_CatchProj: 2103 case Op_CProj: 2104 case Op_JumpProj: 2105 case Op_JProj: 2106 case Op_NeverBranch: 2107 set_dontcare(n); 2108 break; 2109 case Op_Jump: 2110 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2111 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2112 continue; // while (mstack.is_nonempty()) 2113 case Op_StrComp: 2114 case Op_StrEquals: 2115 case Op_StrIndexOf: 2116 case Op_StrIndexOfChar: 2117 case Op_AryEq: 2118 case Op_HasNegatives: 2119 case Op_StrInflatedCopy: 2120 case Op_StrCompressedCopy: 2121 case Op_EncodeISOArray: 2122 case Op_FmaD: 2123 case Op_FmaF: 2124 case Op_FmaVD: 2125 case Op_FmaVF: 2126 set_shared(n); // Force result into register (it will be anyways) 2127 break; 2128 case Op_ConP: { // Convert pointers above the centerline to NUL 2129 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2130 const TypePtr* tp = tn->type()->is_ptr(); 2131 if (tp->_ptr == TypePtr::AnyNull) { 2132 tn->set_type(TypePtr::NULL_PTR); 2133 } 2134 break; 2135 } 2136 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2137 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2138 const TypePtr* tp = tn->type()->make_ptr(); 2139 if (tp && tp->_ptr == TypePtr::AnyNull) { 2140 tn->set_type(TypeNarrowOop::NULL_PTR); 2141 } 2142 break; 2143 } 2144 case Op_Binary: // These are introduced in the Post_Visit state. 2145 ShouldNotReachHere(); 2146 break; 2147 case Op_ClearArray: 2148 case Op_SafePoint: 2149 mem_op = true; 2150 break; 2151 default: 2152 if( n->is_Store() ) { 2153 // Do match stores, despite no ideal reg 2154 mem_op = true; 2155 break; 2156 } 2157 if( n->is_Mem() ) { // Loads and LoadStores 2158 mem_op = true; 2159 // Loads must be root of match tree due to prior load conflict 2160 if( C->subsume_loads() == false ) 2161 set_shared(n); 2162 } 2163 // Fall into default case 2164 if( !n->ideal_reg() ) 2165 set_dontcare(n); // Unmatchable Nodes 2166 } // end_switch 2167 2168 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2169 Node *m = n->in(i); // Get ith input 2170 if (m == NULL) continue; // Ignore NULLs 2171 uint mop = m->Opcode(); 2172 2173 // Must clone all producers of flags, or we will not match correctly. 2174 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2175 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2176 // are also there, so we may match a float-branch to int-flags and 2177 // expect the allocator to haul the flags from the int-side to the 2178 // fp-side. No can do. 2179 if( _must_clone[mop] ) { 2180 mstack.push(m, Visit); 2181 continue; // for(int i = ...) 2182 } 2183 2184 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { 2185 // Bases used in addresses must be shared but since 2186 // they are shared through a DecodeN they may appear 2187 // to have a single use so force sharing here. 2188 set_shared(m->in(AddPNode::Base)->in(1)); 2189 } 2190 2191 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node. 2192 #ifdef X86 2193 if (UseBMI1Instructions && is_bmi_pattern(n, m)) { 2194 mstack.push(m, Visit); 2195 continue; 2196 } 2197 #endif 2198 2199 // Clone addressing expressions as they are "free" in memory access instructions 2200 if (mem_op && i == MemNode::Address && mop == Op_AddP && 2201 // When there are other uses besides address expressions 2202 // put it on stack and mark as shared. 2203 !is_visited(m)) { 2204 // Some inputs for address expression are not put on stack 2205 // to avoid marking them as shared and forcing them into register 2206 // if they are used only in address expressions. 2207 // But they should be marked as shared if there are other uses 2208 // besides address expressions. 2209 2210 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2211 continue; 2212 } 2213 } // if( mem_op && 2214 mstack.push(m, Pre_Visit); 2215 } // for(int i = ...) 2216 } 2217 else if (nstate == Alt_Post_Visit) { 2218 mstack.pop(); // Remove node from stack 2219 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2220 // shared and all users of the Bool need to move the Cmp in parallel. 2221 // This leaves both the Bool and the If pointing at the Cmp. To 2222 // prevent the Matcher from trying to Match the Cmp along both paths 2223 // BoolNode::match_edge always returns a zero. 2224 2225 // We reorder the Op_If in a pre-order manner, so we can visit without 2226 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2227 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2228 } 2229 else if (nstate == Post_Visit) { 2230 mstack.pop(); // Remove node from stack 2231 2232 // Now hack a few special opcodes 2233 switch( n->Opcode() ) { // Handle some opcodes special 2234 case Op_StorePConditional: 2235 case Op_StoreIConditional: 2236 case Op_StoreLConditional: 2237 case Op_CompareAndExchangeB: 2238 case Op_CompareAndExchangeS: 2239 case Op_CompareAndExchangeI: 2240 case Op_CompareAndExchangeL: 2241 case Op_CompareAndExchangeP: 2242 case Op_CompareAndExchangeN: 2243 case Op_WeakCompareAndSwapB: 2244 case Op_WeakCompareAndSwapS: 2245 case Op_WeakCompareAndSwapI: 2246 case Op_WeakCompareAndSwapL: 2247 case Op_WeakCompareAndSwapP: 2248 case Op_WeakCompareAndSwapN: 2249 case Op_CompareAndSwapB: 2250 case Op_CompareAndSwapS: 2251 case Op_CompareAndSwapI: 2252 case Op_CompareAndSwapL: 2253 case Op_CompareAndSwapP: 2254 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2255 Node *newval = n->in(MemNode::ValueIn ); 2256 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2257 Node *pair = new BinaryNode( oldval, newval ); 2258 n->set_req(MemNode::ValueIn,pair); 2259 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2260 break; 2261 } 2262 case Op_CMoveD: // Convert trinary to binary-tree 2263 case Op_CMoveF: 2264 case Op_CMoveI: 2265 case Op_CMoveL: 2266 case Op_CMoveN: 2267 case Op_CMoveP: 2268 case Op_CMoveVD: { 2269 // Restructure into a binary tree for Matching. It's possible that 2270 // we could move this code up next to the graph reshaping for IfNodes 2271 // or vice-versa, but I do not want to debug this for Ladybird. 2272 // 10/2/2000 CNC. 2273 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1)); 2274 n->set_req(1,pair1); 2275 Node *pair2 = new BinaryNode(n->in(2),n->in(3)); 2276 n->set_req(2,pair2); 2277 n->del_req(3); 2278 break; 2279 } 2280 case Op_LoopLimit: { 2281 Node *pair1 = new BinaryNode(n->in(1),n->in(2)); 2282 n->set_req(1,pair1); 2283 n->set_req(2,n->in(3)); 2284 n->del_req(3); 2285 break; 2286 } 2287 case Op_StrEquals: 2288 case Op_StrIndexOfChar: { 2289 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2290 n->set_req(2,pair1); 2291 n->set_req(3,n->in(4)); 2292 n->del_req(4); 2293 break; 2294 } 2295 case Op_StrComp: 2296 case Op_StrIndexOf: { 2297 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2298 n->set_req(2,pair1); 2299 Node *pair2 = new BinaryNode(n->in(4),n->in(5)); 2300 n->set_req(3,pair2); 2301 n->del_req(5); 2302 n->del_req(4); 2303 break; 2304 } 2305 case Op_StrCompressedCopy: 2306 case Op_StrInflatedCopy: 2307 case Op_EncodeISOArray: { 2308 // Restructure into a binary tree for Matching. 2309 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2310 n->set_req(3, pair); 2311 n->del_req(4); 2312 break; 2313 } 2314 case Op_FmaD: 2315 case Op_FmaF: 2316 case Op_FmaVD: 2317 case Op_FmaVF: { 2318 // Restructure into a binary tree for Matching. 2319 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2320 n->set_req(2, pair); 2321 n->set_req(1, n->in(3)); 2322 n->del_req(3); 2323 break; 2324 } 2325 default: 2326 break; 2327 } 2328 } 2329 else { 2330 ShouldNotReachHere(); 2331 } 2332 } // end of while (mstack.is_nonempty()) 2333 } 2334 2335 #ifdef ASSERT 2336 // machine-independent root to machine-dependent root 2337 void Matcher::dump_old2new_map() { 2338 _old2new_map.dump(); 2339 } 2340 #endif 2341 2342 //---------------------------collect_null_checks------------------------------- 2343 // Find null checks in the ideal graph; write a machine-specific node for 2344 // it. Used by later implicit-null-check handling. Actually collects 2345 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2346 // value being tested. 2347 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2348 Node *iff = proj->in(0); 2349 if( iff->Opcode() == Op_If ) { 2350 // During matching If's have Bool & Cmp side-by-side 2351 BoolNode *b = iff->in(1)->as_Bool(); 2352 Node *cmp = iff->in(2); 2353 int opc = cmp->Opcode(); 2354 if (opc != Op_CmpP && opc != Op_CmpN) return; 2355 2356 const Type* ct = cmp->in(2)->bottom_type(); 2357 if (ct == TypePtr::NULL_PTR || 2358 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2359 2360 bool push_it = false; 2361 if( proj->Opcode() == Op_IfTrue ) { 2362 #ifndef PRODUCT 2363 extern int all_null_checks_found; 2364 all_null_checks_found++; 2365 #endif 2366 if( b->_test._test == BoolTest::ne ) { 2367 push_it = true; 2368 } 2369 } else { 2370 assert( proj->Opcode() == Op_IfFalse, "" ); 2371 if( b->_test._test == BoolTest::eq ) { 2372 push_it = true; 2373 } 2374 } 2375 if( push_it ) { 2376 _null_check_tests.push(proj); 2377 Node* val = cmp->in(1); 2378 #ifdef _LP64 2379 if (val->bottom_type()->isa_narrowoop() && 2380 !Matcher::narrow_oop_use_complex_address()) { 2381 // 2382 // Look for DecodeN node which should be pinned to orig_proj. 2383 // On platforms (Sparc) which can not handle 2 adds 2384 // in addressing mode we have to keep a DecodeN node and 2385 // use it to do implicit NULL check in address. 2386 // 2387 // DecodeN node was pinned to non-null path (orig_proj) during 2388 // CastPP transformation in final_graph_reshaping_impl(). 2389 // 2390 uint cnt = orig_proj->outcnt(); 2391 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2392 Node* d = orig_proj->raw_out(i); 2393 if (d->is_DecodeN() && d->in(1) == val) { 2394 val = d; 2395 val->set_req(0, NULL); // Unpin now. 2396 // Mark this as special case to distinguish from 2397 // a regular case: CmpP(DecodeN, NULL). 2398 val = (Node*)(((intptr_t)val) | 1); 2399 break; 2400 } 2401 } 2402 } 2403 #endif 2404 _null_check_tests.push(val); 2405 } 2406 } 2407 } 2408 } 2409 2410 //---------------------------validate_null_checks------------------------------ 2411 // Its possible that the value being NULL checked is not the root of a match 2412 // tree. If so, I cannot use the value in an implicit null check. 2413 void Matcher::validate_null_checks( ) { 2414 uint cnt = _null_check_tests.size(); 2415 for( uint i=0; i < cnt; i+=2 ) { 2416 Node *test = _null_check_tests[i]; 2417 Node *val = _null_check_tests[i+1]; 2418 bool is_decoden = ((intptr_t)val) & 1; 2419 val = (Node*)(((intptr_t)val) & ~1); 2420 if (has_new_node(val)) { 2421 Node* new_val = new_node(val); 2422 if (is_decoden) { 2423 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2424 // Note: new_val may have a control edge if 2425 // the original ideal node DecodeN was matched before 2426 // it was unpinned in Matcher::collect_null_checks(). 2427 // Unpin the mach node and mark it. 2428 new_val->set_req(0, NULL); 2429 new_val = (Node*)(((intptr_t)new_val) | 1); 2430 } 2431 // Is a match-tree root, so replace with the matched value 2432 _null_check_tests.map(i+1, new_val); 2433 } else { 2434 // Yank from candidate list 2435 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2436 _null_check_tests.map(i,_null_check_tests[--cnt]); 2437 _null_check_tests.pop(); 2438 _null_check_tests.pop(); 2439 i-=2; 2440 } 2441 } 2442 } 2443 2444 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2445 // atomic instruction acting as a store_load barrier without any 2446 // intervening volatile load, and thus we don't need a barrier here. 2447 // We retain the Node to act as a compiler ordering barrier. 2448 bool Matcher::post_store_load_barrier(const Node* vmb) { 2449 Compile* C = Compile::current(); 2450 assert(vmb->is_MemBar(), ""); 2451 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2452 const MemBarNode* membar = vmb->as_MemBar(); 2453 2454 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2455 Node* ctrl = NULL; 2456 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2457 Node* p = membar->fast_out(i); 2458 assert(p->is_Proj(), "only projections here"); 2459 if ((p->as_Proj()->_con == TypeFunc::Control) && 2460 !C->node_arena()->contains(p)) { // Unmatched old-space only 2461 ctrl = p; 2462 break; 2463 } 2464 } 2465 assert((ctrl != NULL), "missing control projection"); 2466 2467 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2468 Node *x = ctrl->fast_out(j); 2469 int xop = x->Opcode(); 2470 2471 // We don't need current barrier if we see another or a lock 2472 // before seeing volatile load. 2473 // 2474 // Op_Fastunlock previously appeared in the Op_* list below. 2475 // With the advent of 1-0 lock operations we're no longer guaranteed 2476 // that a monitor exit operation contains a serializing instruction. 2477 2478 if (xop == Op_MemBarVolatile || 2479 xop == Op_CompareAndExchangeB || 2480 xop == Op_CompareAndExchangeS || 2481 xop == Op_CompareAndExchangeI || 2482 xop == Op_CompareAndExchangeL || 2483 xop == Op_CompareAndExchangeP || 2484 xop == Op_CompareAndExchangeN || 2485 xop == Op_WeakCompareAndSwapB || 2486 xop == Op_WeakCompareAndSwapS || 2487 xop == Op_WeakCompareAndSwapL || 2488 xop == Op_WeakCompareAndSwapP || 2489 xop == Op_WeakCompareAndSwapN || 2490 xop == Op_WeakCompareAndSwapI || 2491 xop == Op_CompareAndSwapB || 2492 xop == Op_CompareAndSwapS || 2493 xop == Op_CompareAndSwapL || 2494 xop == Op_CompareAndSwapP || 2495 xop == Op_CompareAndSwapN || 2496 xop == Op_CompareAndSwapI) { 2497 return true; 2498 } 2499 2500 // Op_FastLock previously appeared in the Op_* list above. 2501 // With biased locking we're no longer guaranteed that a monitor 2502 // enter operation contains a serializing instruction. 2503 if ((xop == Op_FastLock) && !UseBiasedLocking) { 2504 return true; 2505 } 2506 2507 if (x->is_MemBar()) { 2508 // We must retain this membar if there is an upcoming volatile 2509 // load, which will be followed by acquire membar. 2510 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2511 return false; 2512 } else { 2513 // For other kinds of barriers, check by pretending we 2514 // are them, and seeing if we can be removed. 2515 return post_store_load_barrier(x->as_MemBar()); 2516 } 2517 } 2518 2519 // probably not necessary to check for these 2520 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2521 return false; 2522 } 2523 } 2524 return false; 2525 } 2526 2527 // Check whether node n is a branch to an uncommon trap that we could 2528 // optimize as test with very high branch costs in case of going to 2529 // the uncommon trap. The code must be able to be recompiled to use 2530 // a cheaper test. 2531 bool Matcher::branches_to_uncommon_trap(const Node *n) { 2532 // Don't do it for natives, adapters, or runtime stubs 2533 Compile *C = Compile::current(); 2534 if (!C->is_method_compilation()) return false; 2535 2536 assert(n->is_If(), "You should only call this on if nodes."); 2537 IfNode *ifn = n->as_If(); 2538 2539 Node *ifFalse = NULL; 2540 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2541 if (ifn->fast_out(i)->is_IfFalse()) { 2542 ifFalse = ifn->fast_out(i); 2543 break; 2544 } 2545 } 2546 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2547 2548 Node *reg = ifFalse; 2549 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2550 // Alternatively use visited set? Seems too expensive. 2551 while (reg != NULL && cnt > 0) { 2552 CallNode *call = NULL; 2553 RegionNode *nxt_reg = NULL; 2554 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2555 Node *o = reg->fast_out(i); 2556 if (o->is_Call()) { 2557 call = o->as_Call(); 2558 } 2559 if (o->is_Region()) { 2560 nxt_reg = o->as_Region(); 2561 } 2562 } 2563 2564 if (call && 2565 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2566 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2567 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2568 jint tr_con = trtype->is_int()->get_con(); 2569 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2570 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2571 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2572 2573 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 2574 && action != Deoptimization::Action_none) { 2575 // This uncommon trap is sure to recompile, eventually. 2576 // When that happens, C->too_many_traps will prevent 2577 // this transformation from happening again. 2578 return true; 2579 } 2580 } 2581 } 2582 2583 reg = nxt_reg; 2584 cnt--; 2585 } 2586 2587 return false; 2588 } 2589 2590 //============================================================================= 2591 //---------------------------State--------------------------------------------- 2592 State::State(void) { 2593 #ifdef ASSERT 2594 _id = 0; 2595 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2596 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2597 //memset(_cost, -1, sizeof(_cost)); 2598 //memset(_rule, -1, sizeof(_rule)); 2599 #endif 2600 memset(_valid, 0, sizeof(_valid)); 2601 } 2602 2603 #ifdef ASSERT 2604 State::~State() { 2605 _id = 99; 2606 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2607 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2608 memset(_cost, -3, sizeof(_cost)); 2609 memset(_rule, -3, sizeof(_rule)); 2610 } 2611 #endif 2612 2613 #ifndef PRODUCT 2614 //---------------------------dump---------------------------------------------- 2615 void State::dump() { 2616 tty->print("\n"); 2617 dump(0); 2618 } 2619 2620 void State::dump(int depth) { 2621 for( int j = 0; j < depth; j++ ) 2622 tty->print(" "); 2623 tty->print("--N: "); 2624 _leaf->dump(); 2625 uint i; 2626 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2627 // Check for valid entry 2628 if( valid(i) ) { 2629 for( int j = 0; j < depth; j++ ) 2630 tty->print(" "); 2631 assert(_cost[i] != max_juint, "cost must be a valid value"); 2632 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2633 tty->print_cr("%s %d %s", 2634 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2635 } 2636 tty->cr(); 2637 2638 for( i=0; i<2; i++ ) 2639 if( _kids[i] ) 2640 _kids[i]->dump(depth+1); 2641 } 2642 #endif