1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableModRefBS.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/interfaceSupport.hpp" 35 #include "runtime/objectMonitor.hpp" 36 #include "runtime/os.hpp" 37 #include "runtime/sharedRuntime.hpp" 38 #include "runtime/stubRoutines.hpp" 39 #include "utilities/macros.hpp" 40 #if INCLUDE_ALL_GCS 41 #include "gc/g1/g1CollectedHeap.inline.hpp" 42 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 43 #include "gc/g1/heapRegion.hpp" 44 #endif // INCLUDE_ALL_GCS 45 46 #ifdef PRODUCT 47 #define BLOCK_COMMENT(str) /* nothing */ 48 #define STOP(error) stop(error) 49 #else 50 #define BLOCK_COMMENT(str) block_comment(str) 51 #define STOP(error) block_comment(error); stop(error) 52 #endif 53 54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 55 // Implementation of AddressLiteral 56 57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 59 // -----------------Table 4.5 -------------------- // 60 16, 32, 64, // EVEX_FV(0) 61 4, 4, 4, // EVEX_FV(1) - with Evex.b 62 16, 32, 64, // EVEX_FV(2) - with Evex.w 63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 64 8, 16, 32, // EVEX_HV(0) 65 4, 4, 4, // EVEX_HV(1) - with Evex.b 66 // -----------------Table 4.6 -------------------- // 67 16, 32, 64, // EVEX_FVM(0) 68 1, 1, 1, // EVEX_T1S(0) 69 2, 2, 2, // EVEX_T1S(1) 70 4, 4, 4, // EVEX_T1S(2) 71 8, 8, 8, // EVEX_T1S(3) 72 4, 4, 4, // EVEX_T1F(0) 73 8, 8, 8, // EVEX_T1F(1) 74 8, 8, 8, // EVEX_T2(0) 75 0, 16, 16, // EVEX_T2(1) 76 0, 16, 16, // EVEX_T4(0) 77 0, 0, 32, // EVEX_T4(1) 78 0, 0, 32, // EVEX_T8(0) 79 8, 16, 32, // EVEX_HVM(0) 80 4, 8, 16, // EVEX_QVM(0) 81 2, 4, 8, // EVEX_OVM(0) 82 16, 16, 16, // EVEX_M128(0) 83 8, 32, 64, // EVEX_DUP(0) 84 0, 0, 0 // EVEX_NTUP 85 }; 86 87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 88 _is_lval = false; 89 _target = target; 90 switch (rtype) { 91 case relocInfo::oop_type: 92 case relocInfo::metadata_type: 93 // Oops are a special case. Normally they would be their own section 94 // but in cases like icBuffer they are literals in the code stream that 95 // we don't have a section for. We use none so that we get a literal address 96 // which is always patchable. 97 break; 98 case relocInfo::external_word_type: 99 _rspec = external_word_Relocation::spec(target); 100 break; 101 case relocInfo::internal_word_type: 102 _rspec = internal_word_Relocation::spec(target); 103 break; 104 case relocInfo::opt_virtual_call_type: 105 _rspec = opt_virtual_call_Relocation::spec(); 106 break; 107 case relocInfo::static_call_type: 108 _rspec = static_call_Relocation::spec(); 109 break; 110 case relocInfo::runtime_call_type: 111 _rspec = runtime_call_Relocation::spec(); 112 break; 113 case relocInfo::poll_type: 114 case relocInfo::poll_return_type: 115 _rspec = Relocation::spec_simple(rtype); 116 break; 117 case relocInfo::none: 118 break; 119 default: 120 ShouldNotReachHere(); 121 break; 122 } 123 } 124 125 // Implementation of Address 126 127 #ifdef _LP64 128 129 Address Address::make_array(ArrayAddress adr) { 130 // Not implementable on 64bit machines 131 // Should have been handled higher up the call chain. 132 ShouldNotReachHere(); 133 return Address(); 134 } 135 136 // exceedingly dangerous constructor 137 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 138 _base = noreg; 139 _index = noreg; 140 _scale = no_scale; 141 _disp = disp; 142 switch (rtype) { 143 case relocInfo::external_word_type: 144 _rspec = external_word_Relocation::spec(loc); 145 break; 146 case relocInfo::internal_word_type: 147 _rspec = internal_word_Relocation::spec(loc); 148 break; 149 case relocInfo::runtime_call_type: 150 // HMM 151 _rspec = runtime_call_Relocation::spec(); 152 break; 153 case relocInfo::poll_type: 154 case relocInfo::poll_return_type: 155 _rspec = Relocation::spec_simple(rtype); 156 break; 157 case relocInfo::none: 158 break; 159 default: 160 ShouldNotReachHere(); 161 } 162 } 163 #else // LP64 164 165 Address Address::make_array(ArrayAddress adr) { 166 AddressLiteral base = adr.base(); 167 Address index = adr.index(); 168 assert(index._disp == 0, "must not have disp"); // maybe it can? 169 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 170 array._rspec = base._rspec; 171 return array; 172 } 173 174 // exceedingly dangerous constructor 175 Address::Address(address loc, RelocationHolder spec) { 176 _base = noreg; 177 _index = noreg; 178 _scale = no_scale; 179 _disp = (intptr_t) loc; 180 _rspec = spec; 181 } 182 183 #endif // _LP64 184 185 186 187 // Convert the raw encoding form into the form expected by the constructor for 188 // Address. An index of 4 (rsp) corresponds to having no index, so convert 189 // that to noreg for the Address constructor. 190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 191 RelocationHolder rspec; 192 if (disp_reloc != relocInfo::none) { 193 rspec = Relocation::spec_simple(disp_reloc); 194 } 195 bool valid_index = index != rsp->encoding(); 196 if (valid_index) { 197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 198 madr._rspec = rspec; 199 return madr; 200 } else { 201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 202 madr._rspec = rspec; 203 return madr; 204 } 205 } 206 207 // Implementation of Assembler 208 209 int AbstractAssembler::code_fill_byte() { 210 return (u_char)'\xF4'; // hlt 211 } 212 213 // make this go away someday 214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 215 if (rtype == relocInfo::none) 216 emit_int32(data); 217 else 218 emit_data(data, Relocation::spec_simple(rtype), format); 219 } 220 221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 222 assert(imm_operand == 0, "default format must be immediate in this file"); 223 assert(inst_mark() != NULL, "must be inside InstructionMark"); 224 if (rspec.type() != relocInfo::none) { 225 #ifdef ASSERT 226 check_relocation(rspec, format); 227 #endif 228 // Do not use AbstractAssembler::relocate, which is not intended for 229 // embedded words. Instead, relocate to the enclosing instruction. 230 231 // hack. call32 is too wide for mask so use disp32 232 if (format == call32_operand) 233 code_section()->relocate(inst_mark(), rspec, disp32_operand); 234 else 235 code_section()->relocate(inst_mark(), rspec, format); 236 } 237 emit_int32(data); 238 } 239 240 static int encode(Register r) { 241 int enc = r->encoding(); 242 if (enc >= 8) { 243 enc -= 8; 244 } 245 return enc; 246 } 247 248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 249 assert(dst->has_byte_register(), "must have byte register"); 250 assert(isByte(op1) && isByte(op2), "wrong opcode"); 251 assert(isByte(imm8), "not a byte"); 252 assert((op1 & 0x01) == 0, "should be 8bit operation"); 253 emit_int8(op1); 254 emit_int8(op2 | encode(dst)); 255 emit_int8(imm8); 256 } 257 258 259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 260 assert(isByte(op1) && isByte(op2), "wrong opcode"); 261 assert((op1 & 0x01) == 1, "should be 32bit operation"); 262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 263 if (is8bit(imm32)) { 264 emit_int8(op1 | 0x02); // set sign bit 265 emit_int8(op2 | encode(dst)); 266 emit_int8(imm32 & 0xFF); 267 } else { 268 emit_int8(op1); 269 emit_int8(op2 | encode(dst)); 270 emit_int32(imm32); 271 } 272 } 273 274 // Force generation of a 4 byte immediate value even if it fits into 8bit 275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 276 assert(isByte(op1) && isByte(op2), "wrong opcode"); 277 assert((op1 & 0x01) == 1, "should be 32bit operation"); 278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 279 emit_int8(op1); 280 emit_int8(op2 | encode(dst)); 281 emit_int32(imm32); 282 } 283 284 // immediate-to-memory forms 285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 286 assert((op1 & 0x01) == 1, "should be 32bit operation"); 287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 288 if (is8bit(imm32)) { 289 emit_int8(op1 | 0x02); // set sign bit 290 emit_operand(rm, adr, 1); 291 emit_int8(imm32 & 0xFF); 292 } else { 293 emit_int8(op1); 294 emit_operand(rm, adr, 4); 295 emit_int32(imm32); 296 } 297 } 298 299 300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 301 assert(isByte(op1) && isByte(op2), "wrong opcode"); 302 emit_int8(op1); 303 emit_int8(op2 | encode(dst) << 3 | encode(src)); 304 } 305 306 307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 309 int mod_idx = 0; 310 // We will test if the displacement fits the compressed format and if so 311 // apply the compression to the displacment iff the result is8bit. 312 if (VM_Version::supports_evex() && is_evex_inst) { 313 switch (cur_tuple_type) { 314 case EVEX_FV: 315 if ((cur_encoding & VEX_W) == VEX_W) { 316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 317 } else { 318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 319 } 320 break; 321 322 case EVEX_HV: 323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 324 break; 325 326 case EVEX_FVM: 327 break; 328 329 case EVEX_T1S: 330 switch (in_size_in_bits) { 331 case EVEX_8bit: 332 break; 333 334 case EVEX_16bit: 335 mod_idx = 1; 336 break; 337 338 case EVEX_32bit: 339 mod_idx = 2; 340 break; 341 342 case EVEX_64bit: 343 mod_idx = 3; 344 break; 345 } 346 break; 347 348 case EVEX_T1F: 349 case EVEX_T2: 350 case EVEX_T4: 351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 352 break; 353 354 case EVEX_T8: 355 break; 356 357 case EVEX_HVM: 358 break; 359 360 case EVEX_QVM: 361 break; 362 363 case EVEX_OVM: 364 break; 365 366 case EVEX_M128: 367 break; 368 369 case EVEX_DUP: 370 break; 371 372 default: 373 assert(0, "no valid evex tuple_table entry"); 374 break; 375 } 376 377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 379 if ((disp % disp_factor) == 0) { 380 int new_disp = disp / disp_factor; 381 if ((-0x80 <= new_disp && new_disp < 0x80)) { 382 disp = new_disp; 383 } 384 } else { 385 return false; 386 } 387 } 388 } 389 return (-0x80 <= disp && disp < 0x80); 390 } 391 392 393 bool Assembler::emit_compressed_disp_byte(int &disp) { 394 int mod_idx = 0; 395 // We will test if the displacement fits the compressed format and if so 396 // apply the compression to the displacment iff the result is8bit. 397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { 398 int evex_encoding = _attributes->get_evex_encoding(); 399 int tuple_type = _attributes->get_tuple_type(); 400 switch (tuple_type) { 401 case EVEX_FV: 402 if ((evex_encoding & VEX_W) == VEX_W) { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 404 } else { 405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 406 } 407 break; 408 409 case EVEX_HV: 410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 411 break; 412 413 case EVEX_FVM: 414 break; 415 416 case EVEX_T1S: 417 switch (_attributes->get_input_size()) { 418 case EVEX_8bit: 419 break; 420 421 case EVEX_16bit: 422 mod_idx = 1; 423 break; 424 425 case EVEX_32bit: 426 mod_idx = 2; 427 break; 428 429 case EVEX_64bit: 430 mod_idx = 3; 431 break; 432 } 433 break; 434 435 case EVEX_T1F: 436 case EVEX_T2: 437 case EVEX_T4: 438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; 439 break; 440 441 case EVEX_T8: 442 break; 443 444 case EVEX_HVM: 445 break; 446 447 case EVEX_QVM: 448 break; 449 450 case EVEX_OVM: 451 break; 452 453 case EVEX_M128: 454 break; 455 456 case EVEX_DUP: 457 break; 458 459 default: 460 assert(0, "no valid evex tuple_table entry"); 461 break; 462 } 463 464 int vector_len = _attributes->get_vector_len(); 465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; 467 if ((disp % disp_factor) == 0) { 468 int new_disp = disp / disp_factor; 469 if (is8bit(new_disp)) { 470 disp = new_disp; 471 } 472 } else { 473 return false; 474 } 475 } 476 } 477 return is8bit(disp); 478 } 479 480 481 void Assembler::emit_operand(Register reg, Register base, Register index, 482 Address::ScaleFactor scale, int disp, 483 RelocationHolder const& rspec, 484 int rip_relative_correction) { 485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 486 487 // Encode the registers as needed in the fields they are used in 488 489 int regenc = encode(reg) << 3; 490 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 491 int baseenc = base->is_valid() ? encode(base) : 0; 492 493 if (base->is_valid()) { 494 if (index->is_valid()) { 495 assert(scale != Address::no_scale, "inconsistent address"); 496 // [base + index*scale + disp] 497 if (disp == 0 && rtype == relocInfo::none && 498 base != rbp LP64_ONLY(&& base != r13)) { 499 // [base + index*scale] 500 // [00 reg 100][ss index base] 501 assert(index != rsp, "illegal addressing mode"); 502 emit_int8(0x04 | regenc); 503 emit_int8(scale << 6 | indexenc | baseenc); 504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 505 // [base + index*scale + imm8] 506 // [01 reg 100][ss index base] imm8 507 assert(index != rsp, "illegal addressing mode"); 508 emit_int8(0x44 | regenc); 509 emit_int8(scale << 6 | indexenc | baseenc); 510 emit_int8(disp & 0xFF); 511 } else { 512 // [base + index*scale + disp32] 513 // [10 reg 100][ss index base] disp32 514 assert(index != rsp, "illegal addressing mode"); 515 emit_int8(0x84 | regenc); 516 emit_int8(scale << 6 | indexenc | baseenc); 517 emit_data(disp, rspec, disp32_operand); 518 } 519 } else if (base == rsp LP64_ONLY(|| base == r12)) { 520 // [rsp + disp] 521 if (disp == 0 && rtype == relocInfo::none) { 522 // [rsp] 523 // [00 reg 100][00 100 100] 524 emit_int8(0x04 | regenc); 525 emit_int8(0x24); 526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 527 // [rsp + imm8] 528 // [01 reg 100][00 100 100] disp8 529 emit_int8(0x44 | regenc); 530 emit_int8(0x24); 531 emit_int8(disp & 0xFF); 532 } else { 533 // [rsp + imm32] 534 // [10 reg 100][00 100 100] disp32 535 emit_int8(0x84 | regenc); 536 emit_int8(0x24); 537 emit_data(disp, rspec, disp32_operand); 538 } 539 } else { 540 // [base + disp] 541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 542 if (disp == 0 && rtype == relocInfo::none && 543 base != rbp LP64_ONLY(&& base != r13)) { 544 // [base] 545 // [00 reg base] 546 emit_int8(0x00 | regenc | baseenc); 547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 548 // [base + disp8] 549 // [01 reg base] disp8 550 emit_int8(0x40 | regenc | baseenc); 551 emit_int8(disp & 0xFF); 552 } else { 553 // [base + disp32] 554 // [10 reg base] disp32 555 emit_int8(0x80 | regenc | baseenc); 556 emit_data(disp, rspec, disp32_operand); 557 } 558 } 559 } else { 560 if (index->is_valid()) { 561 assert(scale != Address::no_scale, "inconsistent address"); 562 // [index*scale + disp] 563 // [00 reg 100][ss index 101] disp32 564 assert(index != rsp, "illegal addressing mode"); 565 emit_int8(0x04 | regenc); 566 emit_int8(scale << 6 | indexenc | 0x05); 567 emit_data(disp, rspec, disp32_operand); 568 } else if (rtype != relocInfo::none ) { 569 // [disp] (64bit) RIP-RELATIVE (32bit) abs 570 // [00 000 101] disp32 571 572 emit_int8(0x05 | regenc); 573 // Note that the RIP-rel. correction applies to the generated 574 // disp field, but _not_ to the target address in the rspec. 575 576 // disp was created by converting the target address minus the pc 577 // at the start of the instruction. That needs more correction here. 578 // intptr_t disp = target - next_ip; 579 assert(inst_mark() != NULL, "must be inside InstructionMark"); 580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 581 int64_t adjusted = disp; 582 // Do rip-rel adjustment for 64bit 583 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 584 assert(is_simm32(adjusted), 585 "must be 32bit offset (RIP relative address)"); 586 emit_data((int32_t) adjusted, rspec, disp32_operand); 587 588 } else { 589 // 32bit never did this, did everything as the rip-rel/disp code above 590 // [disp] ABSOLUTE 591 // [00 reg 100][00 100 101] disp32 592 emit_int8(0x04 | regenc); 593 emit_int8(0x25); 594 emit_data(disp, rspec, disp32_operand); 595 } 596 } 597 } 598 599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 600 Address::ScaleFactor scale, int disp, 601 RelocationHolder const& rspec) { 602 if (UseAVX > 2) { 603 int xreg_enc = reg->encoding(); 604 if (xreg_enc > 15) { 605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 606 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 607 return; 608 } 609 } 610 emit_operand((Register)reg, base, index, scale, disp, rspec); 611 } 612 613 // Secret local extension to Assembler::WhichOperand: 614 #define end_pc_operand (_WhichOperand_limit) 615 616 address Assembler::locate_operand(address inst, WhichOperand which) { 617 // Decode the given instruction, and return the address of 618 // an embedded 32-bit operand word. 619 620 // If "which" is disp32_operand, selects the displacement portion 621 // of an effective address specifier. 622 // If "which" is imm64_operand, selects the trailing immediate constant. 623 // If "which" is call32_operand, selects the displacement of a call or jump. 624 // Caller is responsible for ensuring that there is such an operand, 625 // and that it is 32/64 bits wide. 626 627 // If "which" is end_pc_operand, find the end of the instruction. 628 629 address ip = inst; 630 bool is_64bit = false; 631 632 debug_only(bool has_disp32 = false); 633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 634 635 again_after_prefix: 636 switch (0xFF & *ip++) { 637 638 // These convenience macros generate groups of "case" labels for the switch. 639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 641 case (x)+4: case (x)+5: case (x)+6: case (x)+7 642 #define REP16(x) REP8((x)+0): \ 643 case REP8((x)+8) 644 645 case CS_segment: 646 case SS_segment: 647 case DS_segment: 648 case ES_segment: 649 case FS_segment: 650 case GS_segment: 651 // Seems dubious 652 LP64_ONLY(assert(false, "shouldn't have that prefix")); 653 assert(ip == inst+1, "only one prefix allowed"); 654 goto again_after_prefix; 655 656 case 0x67: 657 case REX: 658 case REX_B: 659 case REX_X: 660 case REX_XB: 661 case REX_R: 662 case REX_RB: 663 case REX_RX: 664 case REX_RXB: 665 NOT_LP64(assert(false, "64bit prefixes")); 666 goto again_after_prefix; 667 668 case REX_W: 669 case REX_WB: 670 case REX_WX: 671 case REX_WXB: 672 case REX_WR: 673 case REX_WRB: 674 case REX_WRX: 675 case REX_WRXB: 676 NOT_LP64(assert(false, "64bit prefixes")); 677 is_64bit = true; 678 goto again_after_prefix; 679 680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 681 case 0x88: // movb a, r 682 case 0x89: // movl a, r 683 case 0x8A: // movb r, a 684 case 0x8B: // movl r, a 685 case 0x8F: // popl a 686 debug_only(has_disp32 = true); 687 break; 688 689 case 0x68: // pushq #32 690 if (which == end_pc_operand) { 691 return ip + 4; 692 } 693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 694 return ip; // not produced by emit_operand 695 696 case 0x66: // movw ... (size prefix) 697 again_after_size_prefix2: 698 switch (0xFF & *ip++) { 699 case REX: 700 case REX_B: 701 case REX_X: 702 case REX_XB: 703 case REX_R: 704 case REX_RB: 705 case REX_RX: 706 case REX_RXB: 707 case REX_W: 708 case REX_WB: 709 case REX_WX: 710 case REX_WXB: 711 case REX_WR: 712 case REX_WRB: 713 case REX_WRX: 714 case REX_WRXB: 715 NOT_LP64(assert(false, "64bit prefix found")); 716 goto again_after_size_prefix2; 717 case 0x8B: // movw r, a 718 case 0x89: // movw a, r 719 debug_only(has_disp32 = true); 720 break; 721 case 0xC7: // movw a, #16 722 debug_only(has_disp32 = true); 723 tail_size = 2; // the imm16 724 break; 725 case 0x0F: // several SSE/SSE2 variants 726 ip--; // reparse the 0x0F 727 goto again_after_prefix; 728 default: 729 ShouldNotReachHere(); 730 } 731 break; 732 733 case REP8(0xB8): // movl/q r, #32/#64(oop?) 734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 735 // these asserts are somewhat nonsensical 736 #ifndef _LP64 737 assert(which == imm_operand || which == disp32_operand, 738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 739 #else 740 assert((which == call32_operand || which == imm_operand) && is_64bit || 741 which == narrow_oop_operand && !is_64bit, 742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 743 #endif // _LP64 744 return ip; 745 746 case 0x69: // imul r, a, #32 747 case 0xC7: // movl a, #32(oop?) 748 tail_size = 4; 749 debug_only(has_disp32 = true); // has both kinds of operands! 750 break; 751 752 case 0x0F: // movx..., etc. 753 switch (0xFF & *ip++) { 754 case 0x3A: // pcmpestri 755 tail_size = 1; 756 case 0x38: // ptest, pmovzxbw 757 ip++; // skip opcode 758 debug_only(has_disp32 = true); // has both kinds of operands! 759 break; 760 761 case 0x70: // pshufd r, r/a, #8 762 debug_only(has_disp32 = true); // has both kinds of operands! 763 case 0x73: // psrldq r, #8 764 tail_size = 1; 765 break; 766 767 case 0x12: // movlps 768 case 0x28: // movaps 769 case 0x2E: // ucomiss 770 case 0x2F: // comiss 771 case 0x54: // andps 772 case 0x55: // andnps 773 case 0x56: // orps 774 case 0x57: // xorps 775 case 0x58: // addpd 776 case 0x59: // mulpd 777 case 0x6E: // movd 778 case 0x7E: // movd 779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 780 case 0xFE: // paddd 781 debug_only(has_disp32 = true); 782 break; 783 784 case 0xAD: // shrd r, a, %cl 785 case 0xAF: // imul r, a 786 case 0xBE: // movsbl r, a (movsxb) 787 case 0xBF: // movswl r, a (movsxw) 788 case 0xB6: // movzbl r, a (movzxb) 789 case 0xB7: // movzwl r, a (movzxw) 790 case REP16(0x40): // cmovl cc, r, a 791 case 0xB0: // cmpxchgb 792 case 0xB1: // cmpxchg 793 case 0xC1: // xaddl 794 case 0xC7: // cmpxchg8 795 case REP16(0x90): // setcc a 796 debug_only(has_disp32 = true); 797 // fall out of the switch to decode the address 798 break; 799 800 case 0xC4: // pinsrw r, a, #8 801 debug_only(has_disp32 = true); 802 case 0xC5: // pextrw r, r, #8 803 tail_size = 1; // the imm8 804 break; 805 806 case 0xAC: // shrd r, a, #8 807 debug_only(has_disp32 = true); 808 tail_size = 1; // the imm8 809 break; 810 811 case REP16(0x80): // jcc rdisp32 812 if (which == end_pc_operand) return ip + 4; 813 assert(which == call32_operand, "jcc has no disp32 or imm"); 814 return ip; 815 default: 816 ShouldNotReachHere(); 817 } 818 break; 819 820 case 0x81: // addl a, #32; addl r, #32 821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 822 // on 32bit in the case of cmpl, the imm might be an oop 823 tail_size = 4; 824 debug_only(has_disp32 = true); // has both kinds of operands! 825 break; 826 827 case 0x83: // addl a, #8; addl r, #8 828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 829 debug_only(has_disp32 = true); // has both kinds of operands! 830 tail_size = 1; 831 break; 832 833 case 0x9B: 834 switch (0xFF & *ip++) { 835 case 0xD9: // fnstcw a 836 debug_only(has_disp32 = true); 837 break; 838 default: 839 ShouldNotReachHere(); 840 } 841 break; 842 843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 844 case REP4(0x10): // adc... 845 case REP4(0x20): // and... 846 case REP4(0x30): // xor... 847 case REP4(0x08): // or... 848 case REP4(0x18): // sbb... 849 case REP4(0x28): // sub... 850 case 0xF7: // mull a 851 case 0x8D: // lea r, a 852 case 0x87: // xchg r, a 853 case REP4(0x38): // cmp... 854 case 0x85: // test r, a 855 debug_only(has_disp32 = true); // has both kinds of operands! 856 break; 857 858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 859 case 0xC6: // movb a, #8 860 case 0x80: // cmpb a, #8 861 case 0x6B: // imul r, a, #8 862 debug_only(has_disp32 = true); // has both kinds of operands! 863 tail_size = 1; // the imm8 864 break; 865 866 case 0xC4: // VEX_3bytes 867 case 0xC5: // VEX_2bytes 868 assert((UseAVX > 0), "shouldn't have VEX prefix"); 869 assert(ip == inst+1, "no prefixes allowed"); 870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 871 // but they have prefix 0x0F and processed when 0x0F processed above. 872 // 873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 874 // instructions (these instructions are not supported in 64-bit mode). 875 // To distinguish them bits [7:6] are set in the VEX second byte since 876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 877 // those VEX bits REX and vvvv bits are inverted. 878 // 879 // Fortunately C2 doesn't generate these instructions so we don't need 880 // to check for them in product version. 881 882 // Check second byte 883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 884 885 int vex_opcode; 886 // First byte 887 if ((0xFF & *inst) == VEX_3bytes) { 888 vex_opcode = VEX_OPCODE_MASK & *ip; 889 ip++; // third byte 890 is_64bit = ((VEX_W & *ip) == VEX_W); 891 } else { 892 vex_opcode = VEX_OPCODE_0F; 893 } 894 ip++; // opcode 895 // To find the end of instruction (which == end_pc_operand). 896 switch (vex_opcode) { 897 case VEX_OPCODE_0F: 898 switch (0xFF & *ip) { 899 case 0x70: // pshufd r, r/a, #8 900 case 0x71: // ps[rl|ra|ll]w r, #8 901 case 0x72: // ps[rl|ra|ll]d r, #8 902 case 0x73: // ps[rl|ra|ll]q r, #8 903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 904 case 0xC4: // pinsrw r, r, r/a, #8 905 case 0xC5: // pextrw r/a, r, #8 906 case 0xC6: // shufp[s|d] r, r, r/a, #8 907 tail_size = 1; // the imm8 908 break; 909 } 910 break; 911 case VEX_OPCODE_0F_3A: 912 tail_size = 1; 913 break; 914 } 915 ip++; // skip opcode 916 debug_only(has_disp32 = true); // has both kinds of operands! 917 break; 918 919 case 0x62: // EVEX_4bytes 920 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix"); 921 assert(ip == inst+1, "no prefixes allowed"); 922 // no EVEX collisions, all instructions that have 0x62 opcodes 923 // have EVEX versions and are subopcodes of 0x66 924 ip++; // skip P0 and exmaine W in P1 925 is_64bit = ((VEX_W & *ip) == VEX_W); 926 ip++; // move to P2 927 ip++; // skip P2, move to opcode 928 // To find the end of instruction (which == end_pc_operand). 929 switch (0xFF & *ip) { 930 case 0x22: // pinsrd r, r/a, #8 931 case 0x61: // pcmpestri r, r/a, #8 932 case 0x70: // pshufd r, r/a, #8 933 case 0x73: // psrldq r, #8 934 tail_size = 1; // the imm8 935 break; 936 default: 937 break; 938 } 939 ip++; // skip opcode 940 debug_only(has_disp32 = true); // has both kinds of operands! 941 break; 942 943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 946 case 0xDD: // fld_d a; fst_d a; fstp_d a 947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 948 case 0xDF: // fild_d a; fistp_d a 949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 952 debug_only(has_disp32 = true); 953 break; 954 955 case 0xE8: // call rdisp32 956 case 0xE9: // jmp rdisp32 957 if (which == end_pc_operand) return ip + 4; 958 assert(which == call32_operand, "call has no disp32 or imm"); 959 return ip; 960 961 case 0xF0: // Lock 962 assert(os::is_MP(), "only on MP"); 963 goto again_after_prefix; 964 965 case 0xF3: // For SSE 966 case 0xF2: // For SSE2 967 switch (0xFF & *ip++) { 968 case REX: 969 case REX_B: 970 case REX_X: 971 case REX_XB: 972 case REX_R: 973 case REX_RB: 974 case REX_RX: 975 case REX_RXB: 976 case REX_W: 977 case REX_WB: 978 case REX_WX: 979 case REX_WXB: 980 case REX_WR: 981 case REX_WRB: 982 case REX_WRX: 983 case REX_WRXB: 984 NOT_LP64(assert(false, "found 64bit prefix")); 985 ip++; 986 default: 987 ip++; 988 } 989 debug_only(has_disp32 = true); // has both kinds of operands! 990 break; 991 992 default: 993 ShouldNotReachHere(); 994 995 #undef REP8 996 #undef REP16 997 } 998 999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 1000 #ifdef _LP64 1001 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 1002 #else 1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 1005 #endif // LP64 1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 1007 1008 // parse the output of emit_operand 1009 int op2 = 0xFF & *ip++; 1010 int base = op2 & 0x07; 1011 int op3 = -1; 1012 const int b100 = 4; 1013 const int b101 = 5; 1014 if (base == b100 && (op2 >> 6) != 3) { 1015 op3 = 0xFF & *ip++; 1016 base = op3 & 0x07; // refetch the base 1017 } 1018 // now ip points at the disp (if any) 1019 1020 switch (op2 >> 6) { 1021 case 0: 1022 // [00 reg 100][ss index base] 1023 // [00 reg 100][00 100 esp] 1024 // [00 reg base] 1025 // [00 reg 100][ss index 101][disp32] 1026 // [00 reg 101] [disp32] 1027 1028 if (base == b101) { 1029 if (which == disp32_operand) 1030 return ip; // caller wants the disp32 1031 ip += 4; // skip the disp32 1032 } 1033 break; 1034 1035 case 1: 1036 // [01 reg 100][ss index base][disp8] 1037 // [01 reg 100][00 100 esp][disp8] 1038 // [01 reg base] [disp8] 1039 ip += 1; // skip the disp8 1040 break; 1041 1042 case 2: 1043 // [10 reg 100][ss index base][disp32] 1044 // [10 reg 100][00 100 esp][disp32] 1045 // [10 reg base] [disp32] 1046 if (which == disp32_operand) 1047 return ip; // caller wants the disp32 1048 ip += 4; // skip the disp32 1049 break; 1050 1051 case 3: 1052 // [11 reg base] (not a memory addressing mode) 1053 break; 1054 } 1055 1056 if (which == end_pc_operand) { 1057 return ip + tail_size; 1058 } 1059 1060 #ifdef _LP64 1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1062 #else 1063 assert(which == imm_operand, "instruction has only an imm field"); 1064 #endif // LP64 1065 return ip; 1066 } 1067 1068 address Assembler::locate_next_instruction(address inst) { 1069 // Secretly share code with locate_operand: 1070 return locate_operand(inst, end_pc_operand); 1071 } 1072 1073 1074 #ifdef ASSERT 1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1076 address inst = inst_mark(); 1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1078 address opnd; 1079 1080 Relocation* r = rspec.reloc(); 1081 if (r->type() == relocInfo::none) { 1082 return; 1083 } else if (r->is_call() || format == call32_operand) { 1084 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1085 opnd = locate_operand(inst, call32_operand); 1086 } else if (r->is_data()) { 1087 assert(format == imm_operand || format == disp32_operand 1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1089 opnd = locate_operand(inst, (WhichOperand)format); 1090 } else { 1091 assert(format == imm_operand, "cannot specify a format"); 1092 return; 1093 } 1094 assert(opnd == pc(), "must put operand where relocs can find it"); 1095 } 1096 #endif // ASSERT 1097 1098 void Assembler::emit_operand32(Register reg, Address adr) { 1099 assert(reg->encoding() < 8, "no extended registers"); 1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1102 adr._rspec); 1103 } 1104 1105 void Assembler::emit_operand(Register reg, Address adr, 1106 int rip_relative_correction) { 1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1108 adr._rspec, 1109 rip_relative_correction); 1110 } 1111 1112 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1114 adr._rspec); 1115 } 1116 1117 // MMX operations 1118 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1121 } 1122 1123 // work around gcc (3.2.1-7a) bug 1124 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1127 } 1128 1129 1130 void Assembler::emit_farith(int b1, int b2, int i) { 1131 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1132 assert(0 <= i && i < 8, "illegal stack offset"); 1133 emit_int8(b1); 1134 emit_int8(b2 + i); 1135 } 1136 1137 1138 // Now the Assembler instructions (identical for 32/64 bits) 1139 1140 void Assembler::adcl(Address dst, int32_t imm32) { 1141 InstructionMark im(this); 1142 prefix(dst); 1143 emit_arith_operand(0x81, rdx, dst, imm32); 1144 } 1145 1146 void Assembler::adcl(Address dst, Register src) { 1147 InstructionMark im(this); 1148 prefix(dst, src); 1149 emit_int8(0x11); 1150 emit_operand(src, dst); 1151 } 1152 1153 void Assembler::adcl(Register dst, int32_t imm32) { 1154 prefix(dst); 1155 emit_arith(0x81, 0xD0, dst, imm32); 1156 } 1157 1158 void Assembler::adcl(Register dst, Address src) { 1159 InstructionMark im(this); 1160 prefix(src, dst); 1161 emit_int8(0x13); 1162 emit_operand(dst, src); 1163 } 1164 1165 void Assembler::adcl(Register dst, Register src) { 1166 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1167 emit_arith(0x13, 0xC0, dst, src); 1168 } 1169 1170 void Assembler::addl(Address dst, int32_t imm32) { 1171 InstructionMark im(this); 1172 prefix(dst); 1173 emit_arith_operand(0x81, rax, dst, imm32); 1174 } 1175 1176 void Assembler::addb(Address dst, int imm8) { 1177 InstructionMark im(this); 1178 prefix(dst); 1179 emit_int8((unsigned char)0x80); 1180 emit_operand(rax, dst, 1); 1181 emit_int8(imm8); 1182 } 1183 1184 void Assembler::addw(Address dst, int imm16) { 1185 InstructionMark im(this); 1186 emit_int8(0x66); 1187 prefix(dst); 1188 emit_int8((unsigned char)0x81); 1189 emit_operand(rax, dst, 2); 1190 emit_int16(imm16); 1191 } 1192 1193 void Assembler::addl(Address dst, Register src) { 1194 InstructionMark im(this); 1195 prefix(dst, src); 1196 emit_int8(0x01); 1197 emit_operand(src, dst); 1198 } 1199 1200 void Assembler::addl(Register dst, int32_t imm32) { 1201 prefix(dst); 1202 emit_arith(0x81, 0xC0, dst, imm32); 1203 } 1204 1205 void Assembler::addl(Register dst, Address src) { 1206 InstructionMark im(this); 1207 prefix(src, dst); 1208 emit_int8(0x03); 1209 emit_operand(dst, src); 1210 } 1211 1212 void Assembler::addl(Register dst, Register src) { 1213 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1214 emit_arith(0x03, 0xC0, dst, src); 1215 } 1216 1217 void Assembler::addr_nop_4() { 1218 assert(UseAddressNop, "no CPU support"); 1219 // 4 bytes: NOP DWORD PTR [EAX+0] 1220 emit_int8(0x0F); 1221 emit_int8(0x1F); 1222 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1223 emit_int8(0); // 8-bits offset (1 byte) 1224 } 1225 1226 void Assembler::addr_nop_5() { 1227 assert(UseAddressNop, "no CPU support"); 1228 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1229 emit_int8(0x0F); 1230 emit_int8(0x1F); 1231 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1232 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1233 emit_int8(0); // 8-bits offset (1 byte) 1234 } 1235 1236 void Assembler::addr_nop_7() { 1237 assert(UseAddressNop, "no CPU support"); 1238 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1239 emit_int8(0x0F); 1240 emit_int8(0x1F); 1241 emit_int8((unsigned char)0x80); 1242 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1243 emit_int32(0); // 32-bits offset (4 bytes) 1244 } 1245 1246 void Assembler::addr_nop_8() { 1247 assert(UseAddressNop, "no CPU support"); 1248 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1249 emit_int8(0x0F); 1250 emit_int8(0x1F); 1251 emit_int8((unsigned char)0x84); 1252 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1253 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1254 emit_int32(0); // 32-bits offset (4 bytes) 1255 } 1256 1257 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1258 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1259 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1260 attributes.set_rex_vex_w_reverted(); 1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1262 emit_int8(0x58); 1263 emit_int8((unsigned char)(0xC0 | encode)); 1264 } 1265 1266 void Assembler::addsd(XMMRegister dst, Address src) { 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1268 InstructionMark im(this); 1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1271 attributes.set_rex_vex_w_reverted(); 1272 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1273 emit_int8(0x58); 1274 emit_operand(dst, src); 1275 } 1276 1277 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1278 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1281 emit_int8(0x58); 1282 emit_int8((unsigned char)(0xC0 | encode)); 1283 } 1284 1285 void Assembler::addss(XMMRegister dst, Address src) { 1286 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1287 InstructionMark im(this); 1288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1289 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1290 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1291 emit_int8(0x58); 1292 emit_operand(dst, src); 1293 } 1294 1295 void Assembler::aesdec(XMMRegister dst, Address src) { 1296 assert(VM_Version::supports_aes(), ""); 1297 InstructionMark im(this); 1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1300 emit_int8((unsigned char)0xDE); 1301 emit_operand(dst, src); 1302 } 1303 1304 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1305 assert(VM_Version::supports_aes(), ""); 1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1308 emit_int8((unsigned char)0xDE); 1309 emit_int8(0xC0 | encode); 1310 } 1311 1312 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1313 assert(VM_Version::supports_aes(), ""); 1314 InstructionMark im(this); 1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1317 emit_int8((unsigned char)0xDF); 1318 emit_operand(dst, src); 1319 } 1320 1321 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1322 assert(VM_Version::supports_aes(), ""); 1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1325 emit_int8((unsigned char)0xDF); 1326 emit_int8((unsigned char)(0xC0 | encode)); 1327 } 1328 1329 void Assembler::aesenc(XMMRegister dst, Address src) { 1330 assert(VM_Version::supports_aes(), ""); 1331 InstructionMark im(this); 1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1334 emit_int8((unsigned char)0xDC); 1335 emit_operand(dst, src); 1336 } 1337 1338 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1339 assert(VM_Version::supports_aes(), ""); 1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1342 emit_int8((unsigned char)0xDC); 1343 emit_int8(0xC0 | encode); 1344 } 1345 1346 void Assembler::aesenclast(XMMRegister dst, Address src) { 1347 assert(VM_Version::supports_aes(), ""); 1348 InstructionMark im(this); 1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1350 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1351 emit_int8((unsigned char)0xDD); 1352 emit_operand(dst, src); 1353 } 1354 1355 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1356 assert(VM_Version::supports_aes(), ""); 1357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1358 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1359 emit_int8((unsigned char)0xDD); 1360 emit_int8((unsigned char)(0xC0 | encode)); 1361 } 1362 1363 void Assembler::andl(Address dst, int32_t imm32) { 1364 InstructionMark im(this); 1365 prefix(dst); 1366 emit_int8((unsigned char)0x81); 1367 emit_operand(rsp, dst, 4); 1368 emit_int32(imm32); 1369 } 1370 1371 void Assembler::andl(Register dst, int32_t imm32) { 1372 prefix(dst); 1373 emit_arith(0x81, 0xE0, dst, imm32); 1374 } 1375 1376 void Assembler::andl(Register dst, Address src) { 1377 InstructionMark im(this); 1378 prefix(src, dst); 1379 emit_int8(0x23); 1380 emit_operand(dst, src); 1381 } 1382 1383 void Assembler::andl(Register dst, Register src) { 1384 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1385 emit_arith(0x23, 0xC0, dst, src); 1386 } 1387 1388 void Assembler::andnl(Register dst, Register src1, Register src2) { 1389 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1391 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1392 emit_int8((unsigned char)0xF2); 1393 emit_int8((unsigned char)(0xC0 | encode)); 1394 } 1395 1396 void Assembler::andnl(Register dst, Register src1, Address src2) { 1397 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1398 InstructionMark im(this); 1399 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1400 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1401 emit_int8((unsigned char)0xF2); 1402 emit_operand(dst, src2); 1403 } 1404 1405 void Assembler::bsfl(Register dst, Register src) { 1406 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1407 emit_int8(0x0F); 1408 emit_int8((unsigned char)0xBC); 1409 emit_int8((unsigned char)(0xC0 | encode)); 1410 } 1411 1412 void Assembler::bsrl(Register dst, Register src) { 1413 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1414 emit_int8(0x0F); 1415 emit_int8((unsigned char)0xBD); 1416 emit_int8((unsigned char)(0xC0 | encode)); 1417 } 1418 1419 void Assembler::bswapl(Register reg) { // bswap 1420 int encode = prefix_and_encode(reg->encoding()); 1421 emit_int8(0x0F); 1422 emit_int8((unsigned char)(0xC8 | encode)); 1423 } 1424 1425 void Assembler::blsil(Register dst, Register src) { 1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1428 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1429 emit_int8((unsigned char)0xF3); 1430 emit_int8((unsigned char)(0xC0 | encode)); 1431 } 1432 1433 void Assembler::blsil(Register dst, Address src) { 1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1435 InstructionMark im(this); 1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1437 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1438 emit_int8((unsigned char)0xF3); 1439 emit_operand(rbx, src); 1440 } 1441 1442 void Assembler::blsmskl(Register dst, Register src) { 1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1445 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1446 emit_int8((unsigned char)0xF3); 1447 emit_int8((unsigned char)(0xC0 | encode)); 1448 } 1449 1450 void Assembler::blsmskl(Register dst, Address src) { 1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1452 InstructionMark im(this); 1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1454 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1455 emit_int8((unsigned char)0xF3); 1456 emit_operand(rdx, src); 1457 } 1458 1459 void Assembler::blsrl(Register dst, Register src) { 1460 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1461 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1462 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1463 emit_int8((unsigned char)0xF3); 1464 emit_int8((unsigned char)(0xC0 | encode)); 1465 } 1466 1467 void Assembler::blsrl(Register dst, Address src) { 1468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1469 InstructionMark im(this); 1470 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1471 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1472 emit_int8((unsigned char)0xF3); 1473 emit_operand(rcx, src); 1474 } 1475 1476 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1477 // suspect disp32 is always good 1478 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1479 1480 if (L.is_bound()) { 1481 const int long_size = 5; 1482 int offs = (int)( target(L) - pc() ); 1483 assert(offs <= 0, "assembler error"); 1484 InstructionMark im(this); 1485 // 1110 1000 #32-bit disp 1486 emit_int8((unsigned char)0xE8); 1487 emit_data(offs - long_size, rtype, operand); 1488 } else { 1489 InstructionMark im(this); 1490 // 1110 1000 #32-bit disp 1491 L.add_patch_at(code(), locator()); 1492 1493 emit_int8((unsigned char)0xE8); 1494 emit_data(int(0), rtype, operand); 1495 } 1496 } 1497 1498 void Assembler::call(Register dst) { 1499 int encode = prefix_and_encode(dst->encoding()); 1500 emit_int8((unsigned char)0xFF); 1501 emit_int8((unsigned char)(0xD0 | encode)); 1502 } 1503 1504 1505 void Assembler::call(Address adr) { 1506 InstructionMark im(this); 1507 prefix(adr); 1508 emit_int8((unsigned char)0xFF); 1509 emit_operand(rdx, adr); 1510 } 1511 1512 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1513 assert(entry != NULL, "call most probably wrong"); 1514 InstructionMark im(this); 1515 emit_int8((unsigned char)0xE8); 1516 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1517 assert(is_simm32(disp), "must be 32bit offset (call2)"); 1518 // Technically, should use call32_operand, but this format is 1519 // implied by the fact that we're emitting a call instruction. 1520 1521 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1522 emit_data((int) disp, rspec, operand); 1523 } 1524 1525 void Assembler::cdql() { 1526 emit_int8((unsigned char)0x99); 1527 } 1528 1529 void Assembler::cld() { 1530 emit_int8((unsigned char)0xFC); 1531 } 1532 1533 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1534 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1535 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1536 emit_int8(0x0F); 1537 emit_int8(0x40 | cc); 1538 emit_int8((unsigned char)(0xC0 | encode)); 1539 } 1540 1541 1542 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1543 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1544 prefix(src, dst); 1545 emit_int8(0x0F); 1546 emit_int8(0x40 | cc); 1547 emit_operand(dst, src); 1548 } 1549 1550 void Assembler::cmpb(Address dst, int imm8) { 1551 InstructionMark im(this); 1552 prefix(dst); 1553 emit_int8((unsigned char)0x80); 1554 emit_operand(rdi, dst, 1); 1555 emit_int8(imm8); 1556 } 1557 1558 void Assembler::cmpl(Address dst, int32_t imm32) { 1559 InstructionMark im(this); 1560 prefix(dst); 1561 emit_int8((unsigned char)0x81); 1562 emit_operand(rdi, dst, 4); 1563 emit_int32(imm32); 1564 } 1565 1566 void Assembler::cmpl(Register dst, int32_t imm32) { 1567 prefix(dst); 1568 emit_arith(0x81, 0xF8, dst, imm32); 1569 } 1570 1571 void Assembler::cmpl(Register dst, Register src) { 1572 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1573 emit_arith(0x3B, 0xC0, dst, src); 1574 } 1575 1576 void Assembler::cmpl(Register dst, Address src) { 1577 InstructionMark im(this); 1578 prefix(src, dst); 1579 emit_int8((unsigned char)0x3B); 1580 emit_operand(dst, src); 1581 } 1582 1583 void Assembler::cmpw(Address dst, int imm16) { 1584 InstructionMark im(this); 1585 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1586 emit_int8(0x66); 1587 emit_int8((unsigned char)0x81); 1588 emit_operand(rdi, dst, 2); 1589 emit_int16(imm16); 1590 } 1591 1592 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1593 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1594 // The ZF is set if the compared values were equal, and cleared otherwise. 1595 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1596 InstructionMark im(this); 1597 prefix(adr, reg); 1598 emit_int8(0x0F); 1599 emit_int8((unsigned char)0xB1); 1600 emit_operand(reg, adr); 1601 } 1602 1603 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1604 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1605 // The ZF is set if the compared values were equal, and cleared otherwise. 1606 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1607 InstructionMark im(this); 1608 prefix(adr, reg, true); 1609 emit_int8(0x0F); 1610 emit_int8((unsigned char)0xB0); 1611 emit_operand(reg, adr); 1612 } 1613 1614 void Assembler::comisd(XMMRegister dst, Address src) { 1615 // NOTE: dbx seems to decode this as comiss even though the 1616 // 0x66 is there. Strangly ucomisd comes out correct 1617 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1618 InstructionMark im(this); 1619 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; 1620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1621 attributes.set_rex_vex_w_reverted(); 1622 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1623 emit_int8(0x2F); 1624 emit_operand(dst, src); 1625 } 1626 1627 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1629 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1630 attributes.set_rex_vex_w_reverted(); 1631 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1632 emit_int8(0x2F); 1633 emit_int8((unsigned char)(0xC0 | encode)); 1634 } 1635 1636 void Assembler::comiss(XMMRegister dst, Address src) { 1637 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1638 InstructionMark im(this); 1639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1640 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1641 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1642 emit_int8(0x2F); 1643 emit_operand(dst, src); 1644 } 1645 1646 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1647 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1649 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1650 emit_int8(0x2F); 1651 emit_int8((unsigned char)(0xC0 | encode)); 1652 } 1653 1654 void Assembler::cpuid() { 1655 emit_int8(0x0F); 1656 emit_int8((unsigned char)0xA2); 1657 } 1658 1659 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented 1660 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v 1661 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - 1662 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - 1663 // 1664 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v 1665 // 1666 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v 1667 // 1668 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v 1669 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { 1670 assert(VM_Version::supports_sse4_2(), ""); 1671 int8_t w = 0x01; 1672 Prefix p = Prefix_EMPTY; 1673 1674 emit_int8((int8_t)0xF2); 1675 switch (sizeInBytes) { 1676 case 1: 1677 w = 0; 1678 break; 1679 case 2: 1680 case 4: 1681 break; 1682 LP64_ONLY(case 8:) 1683 // This instruction is not valid in 32 bits 1684 // Note: 1685 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf 1686 // 1687 // Page B - 72 Vol. 2C says 1688 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 1689 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m 1690 // F0!!! 1691 // while 3 - 208 Vol. 2A 1692 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. 1693 // 1694 // the 0 on a last bit is reserved for a different flavor of this instruction : 1695 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. 1696 p = REX_W; 1697 break; 1698 default: 1699 assert(0, "Unsupported value for a sizeInBytes argument"); 1700 break; 1701 } 1702 LP64_ONLY(prefix(crc, v, p);) 1703 emit_int8((int8_t)0x0F); 1704 emit_int8(0x38); 1705 emit_int8((int8_t)(0xF0 | w)); 1706 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); 1707 } 1708 1709 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { 1710 assert(VM_Version::supports_sse4_2(), ""); 1711 InstructionMark im(this); 1712 int8_t w = 0x01; 1713 Prefix p = Prefix_EMPTY; 1714 1715 emit_int8((int8_t)0xF2); 1716 switch (sizeInBytes) { 1717 case 1: 1718 w = 0; 1719 break; 1720 case 2: 1721 case 4: 1722 break; 1723 LP64_ONLY(case 8:) 1724 // This instruction is not valid in 32 bits 1725 p = REX_W; 1726 break; 1727 default: 1728 assert(0, "Unsupported value for a sizeInBytes argument"); 1729 break; 1730 } 1731 LP64_ONLY(prefix(crc, adr, p);) 1732 emit_int8((int8_t)0x0F); 1733 emit_int8(0x38); 1734 emit_int8((int8_t)(0xF0 | w)); 1735 emit_operand(crc, adr); 1736 } 1737 1738 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1739 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1740 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1741 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1742 emit_int8((unsigned char)0xE6); 1743 emit_int8((unsigned char)(0xC0 | encode)); 1744 } 1745 1746 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1747 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1749 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1750 emit_int8(0x5B); 1751 emit_int8((unsigned char)(0xC0 | encode)); 1752 } 1753 1754 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1756 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1757 attributes.set_rex_vex_w_reverted(); 1758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1759 emit_int8(0x5A); 1760 emit_int8((unsigned char)(0xC0 | encode)); 1761 } 1762 1763 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1764 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1765 InstructionMark im(this); 1766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1768 attributes.set_rex_vex_w_reverted(); 1769 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1770 emit_int8(0x5A); 1771 emit_operand(dst, src); 1772 } 1773 1774 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1775 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1777 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1778 emit_int8(0x2A); 1779 emit_int8((unsigned char)(0xC0 | encode)); 1780 } 1781 1782 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1784 InstructionMark im(this); 1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1788 emit_int8(0x2A); 1789 emit_operand(dst, src); 1790 } 1791 1792 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1793 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1795 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1796 emit_int8(0x2A); 1797 emit_int8((unsigned char)(0xC0 | encode)); 1798 } 1799 1800 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1801 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1802 InstructionMark im(this); 1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1806 emit_int8(0x2A); 1807 emit_operand(dst, src); 1808 } 1809 1810 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 1811 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1814 emit_int8(0x2A); 1815 emit_int8((unsigned char)(0xC0 | encode)); 1816 } 1817 1818 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1822 emit_int8(0x5A); 1823 emit_int8((unsigned char)(0xC0 | encode)); 1824 } 1825 1826 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1828 InstructionMark im(this); 1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1832 emit_int8(0x5A); 1833 emit_operand(dst, src); 1834 } 1835 1836 1837 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1840 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1841 emit_int8(0x2C); 1842 emit_int8((unsigned char)(0xC0 | encode)); 1843 } 1844 1845 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1846 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1848 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1849 emit_int8(0x2C); 1850 emit_int8((unsigned char)(0xC0 | encode)); 1851 } 1852 1853 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { 1854 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1855 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 1856 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1857 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1858 emit_int8((unsigned char)0xE6); 1859 emit_int8((unsigned char)(0xC0 | encode)); 1860 } 1861 1862 void Assembler::decl(Address dst) { 1863 // Don't use it directly. Use MacroAssembler::decrement() instead. 1864 InstructionMark im(this); 1865 prefix(dst); 1866 emit_int8((unsigned char)0xFF); 1867 emit_operand(rcx, dst); 1868 } 1869 1870 void Assembler::divsd(XMMRegister dst, Address src) { 1871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1872 InstructionMark im(this); 1873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1875 attributes.set_rex_vex_w_reverted(); 1876 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1877 emit_int8(0x5E); 1878 emit_operand(dst, src); 1879 } 1880 1881 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1884 attributes.set_rex_vex_w_reverted(); 1885 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1886 emit_int8(0x5E); 1887 emit_int8((unsigned char)(0xC0 | encode)); 1888 } 1889 1890 void Assembler::divss(XMMRegister dst, Address src) { 1891 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1892 InstructionMark im(this); 1893 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1895 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1896 emit_int8(0x5E); 1897 emit_operand(dst, src); 1898 } 1899 1900 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1904 emit_int8(0x5E); 1905 emit_int8((unsigned char)(0xC0 | encode)); 1906 } 1907 1908 void Assembler::emms() { 1909 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1910 emit_int8(0x0F); 1911 emit_int8(0x77); 1912 } 1913 1914 void Assembler::hlt() { 1915 emit_int8((unsigned char)0xF4); 1916 } 1917 1918 void Assembler::idivl(Register src) { 1919 int encode = prefix_and_encode(src->encoding()); 1920 emit_int8((unsigned char)0xF7); 1921 emit_int8((unsigned char)(0xF8 | encode)); 1922 } 1923 1924 void Assembler::divl(Register src) { // Unsigned 1925 int encode = prefix_and_encode(src->encoding()); 1926 emit_int8((unsigned char)0xF7); 1927 emit_int8((unsigned char)(0xF0 | encode)); 1928 } 1929 1930 void Assembler::imull(Register src) { 1931 int encode = prefix_and_encode(src->encoding()); 1932 emit_int8((unsigned char)0xF7); 1933 emit_int8((unsigned char)(0xE8 | encode)); 1934 } 1935 1936 void Assembler::imull(Register dst, Register src) { 1937 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1938 emit_int8(0x0F); 1939 emit_int8((unsigned char)0xAF); 1940 emit_int8((unsigned char)(0xC0 | encode)); 1941 } 1942 1943 1944 void Assembler::imull(Register dst, Register src, int value) { 1945 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1946 if (is8bit(value)) { 1947 emit_int8(0x6B); 1948 emit_int8((unsigned char)(0xC0 | encode)); 1949 emit_int8(value & 0xFF); 1950 } else { 1951 emit_int8(0x69); 1952 emit_int8((unsigned char)(0xC0 | encode)); 1953 emit_int32(value); 1954 } 1955 } 1956 1957 void Assembler::imull(Register dst, Address src) { 1958 InstructionMark im(this); 1959 prefix(src, dst); 1960 emit_int8(0x0F); 1961 emit_int8((unsigned char) 0xAF); 1962 emit_operand(dst, src); 1963 } 1964 1965 1966 void Assembler::incl(Address dst) { 1967 // Don't use it directly. Use MacroAssembler::increment() instead. 1968 InstructionMark im(this); 1969 prefix(dst); 1970 emit_int8((unsigned char)0xFF); 1971 emit_operand(rax, dst); 1972 } 1973 1974 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 1975 InstructionMark im(this); 1976 assert((0 <= cc) && (cc < 16), "illegal cc"); 1977 if (L.is_bound()) { 1978 address dst = target(L); 1979 assert(dst != NULL, "jcc most probably wrong"); 1980 1981 const int short_size = 2; 1982 const int long_size = 6; 1983 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 1984 if (maybe_short && is8bit(offs - short_size)) { 1985 // 0111 tttn #8-bit disp 1986 emit_int8(0x70 | cc); 1987 emit_int8((offs - short_size) & 0xFF); 1988 } else { 1989 // 0000 1111 1000 tttn #32-bit disp 1990 assert(is_simm32(offs - long_size), 1991 "must be 32bit offset (call4)"); 1992 emit_int8(0x0F); 1993 emit_int8((unsigned char)(0x80 | cc)); 1994 emit_int32(offs - long_size); 1995 } 1996 } else { 1997 // Note: could eliminate cond. jumps to this jump if condition 1998 // is the same however, seems to be rather unlikely case. 1999 // Note: use jccb() if label to be bound is very close to get 2000 // an 8-bit displacement 2001 L.add_patch_at(code(), locator()); 2002 emit_int8(0x0F); 2003 emit_int8((unsigned char)(0x80 | cc)); 2004 emit_int32(0); 2005 } 2006 } 2007 2008 void Assembler::jccb(Condition cc, Label& L) { 2009 if (L.is_bound()) { 2010 const int short_size = 2; 2011 address entry = target(L); 2012 #ifdef ASSERT 2013 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2014 intptr_t delta = short_branch_delta(); 2015 if (delta != 0) { 2016 dist += (dist < 0 ? (-delta) :delta); 2017 } 2018 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2019 #endif 2020 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 2021 // 0111 tttn #8-bit disp 2022 emit_int8(0x70 | cc); 2023 emit_int8((offs - short_size) & 0xFF); 2024 } else { 2025 InstructionMark im(this); 2026 L.add_patch_at(code(), locator()); 2027 emit_int8(0x70 | cc); 2028 emit_int8(0); 2029 } 2030 } 2031 2032 void Assembler::jmp(Address adr) { 2033 InstructionMark im(this); 2034 prefix(adr); 2035 emit_int8((unsigned char)0xFF); 2036 emit_operand(rsp, adr); 2037 } 2038 2039 void Assembler::jmp(Label& L, bool maybe_short) { 2040 if (L.is_bound()) { 2041 address entry = target(L); 2042 assert(entry != NULL, "jmp most probably wrong"); 2043 InstructionMark im(this); 2044 const int short_size = 2; 2045 const int long_size = 5; 2046 intptr_t offs = entry - pc(); 2047 if (maybe_short && is8bit(offs - short_size)) { 2048 emit_int8((unsigned char)0xEB); 2049 emit_int8((offs - short_size) & 0xFF); 2050 } else { 2051 emit_int8((unsigned char)0xE9); 2052 emit_int32(offs - long_size); 2053 } 2054 } else { 2055 // By default, forward jumps are always 32-bit displacements, since 2056 // we can't yet know where the label will be bound. If you're sure that 2057 // the forward jump will not run beyond 256 bytes, use jmpb to 2058 // force an 8-bit displacement. 2059 InstructionMark im(this); 2060 L.add_patch_at(code(), locator()); 2061 emit_int8((unsigned char)0xE9); 2062 emit_int32(0); 2063 } 2064 } 2065 2066 void Assembler::jmp(Register entry) { 2067 int encode = prefix_and_encode(entry->encoding()); 2068 emit_int8((unsigned char)0xFF); 2069 emit_int8((unsigned char)(0xE0 | encode)); 2070 } 2071 2072 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 2073 InstructionMark im(this); 2074 emit_int8((unsigned char)0xE9); 2075 assert(dest != NULL, "must have a target"); 2076 intptr_t disp = dest - (pc() + sizeof(int32_t)); 2077 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 2078 emit_data(disp, rspec.reloc(), call32_operand); 2079 } 2080 2081 void Assembler::jmpb(Label& L) { 2082 if (L.is_bound()) { 2083 const int short_size = 2; 2084 address entry = target(L); 2085 assert(entry != NULL, "jmp most probably wrong"); 2086 #ifdef ASSERT 2087 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2088 intptr_t delta = short_branch_delta(); 2089 if (delta != 0) { 2090 dist += (dist < 0 ? (-delta) :delta); 2091 } 2092 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2093 #endif 2094 intptr_t offs = entry - pc(); 2095 emit_int8((unsigned char)0xEB); 2096 emit_int8((offs - short_size) & 0xFF); 2097 } else { 2098 InstructionMark im(this); 2099 L.add_patch_at(code(), locator()); 2100 emit_int8((unsigned char)0xEB); 2101 emit_int8(0); 2102 } 2103 } 2104 2105 void Assembler::ldmxcsr( Address src) { 2106 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2107 InstructionMark im(this); 2108 prefix(src); 2109 emit_int8(0x0F); 2110 emit_int8((unsigned char)0xAE); 2111 emit_operand(as_Register(2), src); 2112 } 2113 2114 void Assembler::leal(Register dst, Address src) { 2115 InstructionMark im(this); 2116 #ifdef _LP64 2117 emit_int8(0x67); // addr32 2118 prefix(src, dst); 2119 #endif // LP64 2120 emit_int8((unsigned char)0x8D); 2121 emit_operand(dst, src); 2122 } 2123 2124 void Assembler::lfence() { 2125 emit_int8(0x0F); 2126 emit_int8((unsigned char)0xAE); 2127 emit_int8((unsigned char)0xE8); 2128 } 2129 2130 void Assembler::lock() { 2131 emit_int8((unsigned char)0xF0); 2132 } 2133 2134 void Assembler::lzcntl(Register dst, Register src) { 2135 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 2136 emit_int8((unsigned char)0xF3); 2137 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2138 emit_int8(0x0F); 2139 emit_int8((unsigned char)0xBD); 2140 emit_int8((unsigned char)(0xC0 | encode)); 2141 } 2142 2143 // Emit mfence instruction 2144 void Assembler::mfence() { 2145 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2146 emit_int8(0x0F); 2147 emit_int8((unsigned char)0xAE); 2148 emit_int8((unsigned char)0xF0); 2149 } 2150 2151 void Assembler::mov(Register dst, Register src) { 2152 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2153 } 2154 2155 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 2156 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2157 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2159 attributes.set_rex_vex_w_reverted(); 2160 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2161 emit_int8(0x28); 2162 emit_int8((unsigned char)(0xC0 | encode)); 2163 } 2164 2165 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2166 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2167 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2168 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2169 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2170 emit_int8(0x28); 2171 emit_int8((unsigned char)(0xC0 | encode)); 2172 } 2173 2174 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2175 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2177 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2178 emit_int8(0x16); 2179 emit_int8((unsigned char)(0xC0 | encode)); 2180 } 2181 2182 void Assembler::movb(Register dst, Address src) { 2183 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2184 InstructionMark im(this); 2185 prefix(src, dst, true); 2186 emit_int8((unsigned char)0x8A); 2187 emit_operand(dst, src); 2188 } 2189 2190 void Assembler::movddup(XMMRegister dst, XMMRegister src) { 2191 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 2192 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2193 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2194 attributes.set_rex_vex_w_reverted(); 2195 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2196 emit_int8(0x12); 2197 emit_int8(0xC0 | encode); 2198 } 2199 2200 void Assembler::kmovbl(KRegister dst, Register src) { 2201 assert(VM_Version::supports_avx512dq(), ""); 2202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2203 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2204 emit_int8((unsigned char)0x92); 2205 emit_int8((unsigned char)(0xC0 | encode)); 2206 } 2207 2208 void Assembler::kmovbl(Register dst, KRegister src) { 2209 assert(VM_Version::supports_avx512dq(), ""); 2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2212 emit_int8((unsigned char)0x93); 2213 emit_int8((unsigned char)(0xC0 | encode)); 2214 } 2215 2216 void Assembler::kmovwl(KRegister dst, Register src) { 2217 assert(VM_Version::supports_evex(), ""); 2218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2219 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2220 emit_int8((unsigned char)0x92); 2221 emit_int8((unsigned char)(0xC0 | encode)); 2222 } 2223 2224 void Assembler::kmovwl(Register dst, KRegister src) { 2225 assert(VM_Version::supports_evex(), ""); 2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2228 emit_int8((unsigned char)0x93); 2229 emit_int8((unsigned char)(0xC0 | encode)); 2230 } 2231 2232 void Assembler::kmovwl(KRegister dst, Address src) { 2233 assert(VM_Version::supports_evex(), ""); 2234 InstructionMark im(this); 2235 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2236 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2237 emit_int8((unsigned char)0x90); 2238 emit_operand((Register)dst, src); 2239 } 2240 2241 void Assembler::kmovdl(KRegister dst, Register src) { 2242 assert(VM_Version::supports_avx512bw(), ""); 2243 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2244 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2245 emit_int8((unsigned char)0x92); 2246 emit_int8((unsigned char)(0xC0 | encode)); 2247 } 2248 2249 void Assembler::kmovdl(Register dst, KRegister src) { 2250 assert(VM_Version::supports_avx512bw(), ""); 2251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2252 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2253 emit_int8((unsigned char)0x93); 2254 emit_int8((unsigned char)(0xC0 | encode)); 2255 } 2256 2257 void Assembler::kmovql(KRegister dst, KRegister src) { 2258 assert(VM_Version::supports_avx512bw(), ""); 2259 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2260 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2261 emit_int8((unsigned char)0x90); 2262 emit_int8((unsigned char)(0xC0 | encode)); 2263 } 2264 2265 void Assembler::kmovql(KRegister dst, Address src) { 2266 assert(VM_Version::supports_avx512bw(), ""); 2267 InstructionMark im(this); 2268 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2269 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2270 emit_int8((unsigned char)0x90); 2271 emit_operand((Register)dst, src); 2272 } 2273 2274 void Assembler::kmovql(Address dst, KRegister src) { 2275 assert(VM_Version::supports_avx512bw(), ""); 2276 InstructionMark im(this); 2277 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2278 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2279 emit_int8((unsigned char)0x90); 2280 emit_operand((Register)src, dst); 2281 } 2282 2283 void Assembler::kmovql(KRegister dst, Register src) { 2284 assert(VM_Version::supports_avx512bw(), ""); 2285 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2286 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2287 emit_int8((unsigned char)0x92); 2288 emit_int8((unsigned char)(0xC0 | encode)); 2289 } 2290 2291 void Assembler::kmovql(Register dst, KRegister src) { 2292 assert(VM_Version::supports_avx512bw(), ""); 2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2295 emit_int8((unsigned char)0x93); 2296 emit_int8((unsigned char)(0xC0 | encode)); 2297 } 2298 2299 void Assembler::knotwl(KRegister dst, KRegister src) { 2300 assert(VM_Version::supports_evex(), ""); 2301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2302 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2303 emit_int8((unsigned char)0x44); 2304 emit_int8((unsigned char)(0xC0 | encode)); 2305 } 2306 2307 // This instruction produces ZF or CF flags 2308 void Assembler::kortestbl(KRegister src1, KRegister src2) { 2309 assert(VM_Version::supports_avx512dq(), ""); 2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2311 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2312 emit_int8((unsigned char)0x98); 2313 emit_int8((unsigned char)(0xC0 | encode)); 2314 } 2315 2316 // This instruction produces ZF or CF flags 2317 void Assembler::kortestwl(KRegister src1, KRegister src2) { 2318 assert(VM_Version::supports_evex(), ""); 2319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2320 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2321 emit_int8((unsigned char)0x98); 2322 emit_int8((unsigned char)(0xC0 | encode)); 2323 } 2324 2325 // This instruction produces ZF or CF flags 2326 void Assembler::kortestdl(KRegister src1, KRegister src2) { 2327 assert(VM_Version::supports_avx512bw(), ""); 2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2329 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2330 emit_int8((unsigned char)0x98); 2331 emit_int8((unsigned char)(0xC0 | encode)); 2332 } 2333 2334 // This instruction produces ZF or CF flags 2335 void Assembler::kortestql(KRegister src1, KRegister src2) { 2336 assert(VM_Version::supports_avx512bw(), ""); 2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2338 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2339 emit_int8((unsigned char)0x98); 2340 emit_int8((unsigned char)(0xC0 | encode)); 2341 } 2342 2343 // This instruction produces ZF or CF flags 2344 void Assembler::ktestql(KRegister src1, KRegister src2) { 2345 assert(VM_Version::supports_avx512bw(), ""); 2346 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2347 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2348 emit_int8((unsigned char)0x99); 2349 emit_int8((unsigned char)(0xC0 | encode)); 2350 } 2351 2352 void Assembler::ktestq(KRegister src1, KRegister src2) { 2353 assert(VM_Version::supports_avx512bw(), ""); 2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2356 emit_int8((unsigned char)0x99); 2357 emit_int8((unsigned char)(0xC0 | encode)); 2358 } 2359 2360 void Assembler::ktestd(KRegister src1, KRegister src2) { 2361 assert(VM_Version::supports_avx512bw(), ""); 2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2364 emit_int8((unsigned char)0x99); 2365 emit_int8((unsigned char)(0xC0 | encode)); 2366 } 2367 2368 void Assembler::movb(Address dst, int imm8) { 2369 InstructionMark im(this); 2370 prefix(dst); 2371 emit_int8((unsigned char)0xC6); 2372 emit_operand(rax, dst, 1); 2373 emit_int8(imm8); 2374 } 2375 2376 2377 void Assembler::movb(Address dst, Register src) { 2378 assert(src->has_byte_register(), "must have byte register"); 2379 InstructionMark im(this); 2380 prefix(dst, src, true); 2381 emit_int8((unsigned char)0x88); 2382 emit_operand(src, dst); 2383 } 2384 2385 void Assembler::movdl(XMMRegister dst, Register src) { 2386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2387 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2388 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2389 emit_int8(0x6E); 2390 emit_int8((unsigned char)(0xC0 | encode)); 2391 } 2392 2393 void Assembler::movdl(Register dst, XMMRegister src) { 2394 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2396 // swap src/dst to get correct prefix 2397 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2398 emit_int8(0x7E); 2399 emit_int8((unsigned char)(0xC0 | encode)); 2400 } 2401 2402 void Assembler::movdl(XMMRegister dst, Address src) { 2403 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2404 InstructionMark im(this); 2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2406 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2407 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2408 emit_int8(0x6E); 2409 emit_operand(dst, src); 2410 } 2411 2412 void Assembler::movdl(Address dst, XMMRegister src) { 2413 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2414 InstructionMark im(this); 2415 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2416 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2417 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2418 emit_int8(0x7E); 2419 emit_operand(src, dst); 2420 } 2421 2422 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2423 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2424 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2425 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2426 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2427 emit_int8(0x6F); 2428 emit_int8((unsigned char)(0xC0 | encode)); 2429 } 2430 2431 void Assembler::movdqa(XMMRegister dst, Address src) { 2432 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2433 InstructionMark im(this); 2434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2435 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2436 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2437 emit_int8(0x6F); 2438 emit_operand(dst, src); 2439 } 2440 2441 void Assembler::movdqu(XMMRegister dst, Address src) { 2442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2443 InstructionMark im(this); 2444 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2445 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2446 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2447 emit_int8(0x6F); 2448 emit_operand(dst, src); 2449 } 2450 2451 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2454 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2455 emit_int8(0x6F); 2456 emit_int8((unsigned char)(0xC0 | encode)); 2457 } 2458 2459 void Assembler::movdqu(Address dst, XMMRegister src) { 2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2461 InstructionMark im(this); 2462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2463 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2464 attributes.reset_is_clear_context(); 2465 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2466 emit_int8(0x7F); 2467 emit_operand(src, dst); 2468 } 2469 2470 // Move Unaligned 256bit Vector 2471 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2472 assert(UseAVX > 0, ""); 2473 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2474 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2475 emit_int8(0x6F); 2476 emit_int8((unsigned char)(0xC0 | encode)); 2477 } 2478 2479 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2480 assert(UseAVX > 0, ""); 2481 InstructionMark im(this); 2482 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2483 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2484 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2485 emit_int8(0x6F); 2486 emit_operand(dst, src); 2487 } 2488 2489 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2490 assert(UseAVX > 0, ""); 2491 InstructionMark im(this); 2492 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2493 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2494 attributes.reset_is_clear_context(); 2495 // swap src<->dst for encoding 2496 assert(src != xnoreg, "sanity"); 2497 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2498 emit_int8(0x7F); 2499 emit_operand(src, dst); 2500 } 2501 2502 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2503 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { 2504 assert(VM_Version::supports_evex(), ""); 2505 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2506 attributes.set_is_evex_instruction(); 2507 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2508 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2509 emit_int8(0x6F); 2510 emit_int8((unsigned char)(0xC0 | encode)); 2511 } 2512 2513 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) { 2514 assert(VM_Version::supports_evex(), ""); 2515 InstructionMark im(this); 2516 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2517 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2518 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2519 attributes.set_is_evex_instruction(); 2520 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2521 emit_int8(0x6F); 2522 emit_operand(dst, src); 2523 } 2524 2525 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) { 2526 assert(VM_Version::supports_evex(), ""); 2527 assert(src != xnoreg, "sanity"); 2528 InstructionMark im(this); 2529 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2530 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2531 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2532 attributes.set_is_evex_instruction(); 2533 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2534 emit_int8(0x7F); 2535 emit_operand(src, dst); 2536 } 2537 2538 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2539 assert(VM_Version::supports_avx512vlbw(), ""); 2540 assert(is_vector_masking(), ""); // For stub code use only 2541 InstructionMark im(this); 2542 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2543 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2544 attributes.set_embedded_opmask_register_specifier(mask); 2545 attributes.set_is_evex_instruction(); 2546 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2547 emit_int8(0x6F); 2548 emit_operand(dst, src); 2549 } 2550 2551 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { 2552 assert(VM_Version::supports_evex(), ""); 2553 InstructionMark im(this); 2554 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2555 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2556 attributes.set_is_evex_instruction(); 2557 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2558 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2559 emit_int8(0x6F); 2560 emit_operand(dst, src); 2561 } 2562 2563 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2564 assert(is_vector_masking(), ""); 2565 assert(VM_Version::supports_avx512vlbw(), ""); 2566 InstructionMark im(this); 2567 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2569 attributes.set_embedded_opmask_register_specifier(mask); 2570 attributes.set_is_evex_instruction(); 2571 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2572 emit_int8(0x6F); 2573 emit_operand(dst, src); 2574 } 2575 2576 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) { 2577 assert(VM_Version::supports_evex(), ""); 2578 assert(src != xnoreg, "sanity"); 2579 InstructionMark im(this); 2580 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2581 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2582 attributes.set_is_evex_instruction(); 2583 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2584 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2585 emit_int8(0x7F); 2586 emit_operand(src, dst); 2587 } 2588 2589 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) { 2590 assert(VM_Version::supports_avx512vlbw(), ""); 2591 assert(src != xnoreg, "sanity"); 2592 InstructionMark im(this); 2593 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2594 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2595 attributes.reset_is_clear_context(); 2596 attributes.set_embedded_opmask_register_specifier(mask); 2597 attributes.set_is_evex_instruction(); 2598 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2599 emit_int8(0x7F); 2600 emit_operand(src, dst); 2601 } 2602 2603 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { 2604 assert(VM_Version::supports_evex(), ""); 2605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2606 attributes.set_is_evex_instruction(); 2607 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2608 emit_int8(0x6F); 2609 emit_int8((unsigned char)(0xC0 | encode)); 2610 } 2611 2612 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { 2613 assert(VM_Version::supports_evex(), ""); 2614 InstructionMark im(this); 2615 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true); 2616 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2617 attributes.set_is_evex_instruction(); 2618 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2619 emit_int8(0x6F); 2620 emit_operand(dst, src); 2621 } 2622 2623 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { 2624 assert(VM_Version::supports_evex(), ""); 2625 assert(src != xnoreg, "sanity"); 2626 InstructionMark im(this); 2627 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2628 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2629 attributes.reset_is_clear_context(); 2630 attributes.set_is_evex_instruction(); 2631 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2632 emit_int8(0x7F); 2633 emit_operand(src, dst); 2634 } 2635 2636 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { 2637 assert(VM_Version::supports_evex(), ""); 2638 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2639 attributes.set_is_evex_instruction(); 2640 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2641 emit_int8(0x6F); 2642 emit_int8((unsigned char)(0xC0 | encode)); 2643 } 2644 2645 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { 2646 assert(VM_Version::supports_evex(), ""); 2647 InstructionMark im(this); 2648 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2649 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2650 attributes.set_is_evex_instruction(); 2651 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2652 emit_int8(0x6F); 2653 emit_operand(dst, src); 2654 } 2655 2656 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { 2657 assert(VM_Version::supports_evex(), ""); 2658 assert(src != xnoreg, "sanity"); 2659 InstructionMark im(this); 2660 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2661 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2662 attributes.reset_is_clear_context(); 2663 attributes.set_is_evex_instruction(); 2664 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2665 emit_int8(0x7F); 2666 emit_operand(src, dst); 2667 } 2668 2669 // Uses zero extension on 64bit 2670 2671 void Assembler::movl(Register dst, int32_t imm32) { 2672 int encode = prefix_and_encode(dst->encoding()); 2673 emit_int8((unsigned char)(0xB8 | encode)); 2674 emit_int32(imm32); 2675 } 2676 2677 void Assembler::movl(Register dst, Register src) { 2678 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2679 emit_int8((unsigned char)0x8B); 2680 emit_int8((unsigned char)(0xC0 | encode)); 2681 } 2682 2683 void Assembler::movl(Register dst, Address src) { 2684 InstructionMark im(this); 2685 prefix(src, dst); 2686 emit_int8((unsigned char)0x8B); 2687 emit_operand(dst, src); 2688 } 2689 2690 void Assembler::movl(Address dst, int32_t imm32) { 2691 InstructionMark im(this); 2692 prefix(dst); 2693 emit_int8((unsigned char)0xC7); 2694 emit_operand(rax, dst, 4); 2695 emit_int32(imm32); 2696 } 2697 2698 void Assembler::movl(Address dst, Register src) { 2699 InstructionMark im(this); 2700 prefix(dst, src); 2701 emit_int8((unsigned char)0x89); 2702 emit_operand(src, dst); 2703 } 2704 2705 // New cpus require to use movsd and movss to avoid partial register stall 2706 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2707 // The selection is done in MacroAssembler::movdbl() and movflt(). 2708 void Assembler::movlpd(XMMRegister dst, Address src) { 2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2710 InstructionMark im(this); 2711 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2712 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2713 attributes.set_rex_vex_w_reverted(); 2714 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2715 emit_int8(0x12); 2716 emit_operand(dst, src); 2717 } 2718 2719 void Assembler::movq( MMXRegister dst, Address src ) { 2720 assert( VM_Version::supports_mmx(), "" ); 2721 emit_int8(0x0F); 2722 emit_int8(0x6F); 2723 emit_operand(dst, src); 2724 } 2725 2726 void Assembler::movq( Address dst, MMXRegister src ) { 2727 assert( VM_Version::supports_mmx(), "" ); 2728 emit_int8(0x0F); 2729 emit_int8(0x7F); 2730 // workaround gcc (3.2.1-7a) bug 2731 // In that version of gcc with only an emit_operand(MMX, Address) 2732 // gcc will tail jump and try and reverse the parameters completely 2733 // obliterating dst in the process. By having a version available 2734 // that doesn't need to swap the args at the tail jump the bug is 2735 // avoided. 2736 emit_operand(dst, src); 2737 } 2738 2739 void Assembler::movq(XMMRegister dst, Address src) { 2740 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2741 InstructionMark im(this); 2742 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2743 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2744 attributes.set_rex_vex_w_reverted(); 2745 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2746 emit_int8(0x7E); 2747 emit_operand(dst, src); 2748 } 2749 2750 void Assembler::movq(Address dst, XMMRegister src) { 2751 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2752 InstructionMark im(this); 2753 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2754 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2755 attributes.set_rex_vex_w_reverted(); 2756 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2757 emit_int8((unsigned char)0xD6); 2758 emit_operand(src, dst); 2759 } 2760 2761 void Assembler::movsbl(Register dst, Address src) { // movsxb 2762 InstructionMark im(this); 2763 prefix(src, dst); 2764 emit_int8(0x0F); 2765 emit_int8((unsigned char)0xBE); 2766 emit_operand(dst, src); 2767 } 2768 2769 void Assembler::movsbl(Register dst, Register src) { // movsxb 2770 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2771 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2772 emit_int8(0x0F); 2773 emit_int8((unsigned char)0xBE); 2774 emit_int8((unsigned char)(0xC0 | encode)); 2775 } 2776 2777 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2778 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2779 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2780 attributes.set_rex_vex_w_reverted(); 2781 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2782 emit_int8(0x10); 2783 emit_int8((unsigned char)(0xC0 | encode)); 2784 } 2785 2786 void Assembler::movsd(XMMRegister dst, Address src) { 2787 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2788 InstructionMark im(this); 2789 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2790 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2791 attributes.set_rex_vex_w_reverted(); 2792 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2793 emit_int8(0x10); 2794 emit_operand(dst, src); 2795 } 2796 2797 void Assembler::movsd(Address dst, XMMRegister src) { 2798 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2799 InstructionMark im(this); 2800 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2801 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2802 attributes.reset_is_clear_context(); 2803 attributes.set_rex_vex_w_reverted(); 2804 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2805 emit_int8(0x11); 2806 emit_operand(src, dst); 2807 } 2808 2809 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2810 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2812 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2813 emit_int8(0x10); 2814 emit_int8((unsigned char)(0xC0 | encode)); 2815 } 2816 2817 void Assembler::movss(XMMRegister dst, Address src) { 2818 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2819 InstructionMark im(this); 2820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2822 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2823 emit_int8(0x10); 2824 emit_operand(dst, src); 2825 } 2826 2827 void Assembler::movss(Address dst, XMMRegister src) { 2828 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2829 InstructionMark im(this); 2830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2831 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2832 attributes.reset_is_clear_context(); 2833 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2834 emit_int8(0x11); 2835 emit_operand(src, dst); 2836 } 2837 2838 void Assembler::movswl(Register dst, Address src) { // movsxw 2839 InstructionMark im(this); 2840 prefix(src, dst); 2841 emit_int8(0x0F); 2842 emit_int8((unsigned char)0xBF); 2843 emit_operand(dst, src); 2844 } 2845 2846 void Assembler::movswl(Register dst, Register src) { // movsxw 2847 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2848 emit_int8(0x0F); 2849 emit_int8((unsigned char)0xBF); 2850 emit_int8((unsigned char)(0xC0 | encode)); 2851 } 2852 2853 void Assembler::movw(Address dst, int imm16) { 2854 InstructionMark im(this); 2855 2856 emit_int8(0x66); // switch to 16-bit mode 2857 prefix(dst); 2858 emit_int8((unsigned char)0xC7); 2859 emit_operand(rax, dst, 2); 2860 emit_int16(imm16); 2861 } 2862 2863 void Assembler::movw(Register dst, Address src) { 2864 InstructionMark im(this); 2865 emit_int8(0x66); 2866 prefix(src, dst); 2867 emit_int8((unsigned char)0x8B); 2868 emit_operand(dst, src); 2869 } 2870 2871 void Assembler::movw(Address dst, Register src) { 2872 InstructionMark im(this); 2873 emit_int8(0x66); 2874 prefix(dst, src); 2875 emit_int8((unsigned char)0x89); 2876 emit_operand(src, dst); 2877 } 2878 2879 void Assembler::movzbl(Register dst, Address src) { // movzxb 2880 InstructionMark im(this); 2881 prefix(src, dst); 2882 emit_int8(0x0F); 2883 emit_int8((unsigned char)0xB6); 2884 emit_operand(dst, src); 2885 } 2886 2887 void Assembler::movzbl(Register dst, Register src) { // movzxb 2888 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2889 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2890 emit_int8(0x0F); 2891 emit_int8((unsigned char)0xB6); 2892 emit_int8(0xC0 | encode); 2893 } 2894 2895 void Assembler::movzwl(Register dst, Address src) { // movzxw 2896 InstructionMark im(this); 2897 prefix(src, dst); 2898 emit_int8(0x0F); 2899 emit_int8((unsigned char)0xB7); 2900 emit_operand(dst, src); 2901 } 2902 2903 void Assembler::movzwl(Register dst, Register src) { // movzxw 2904 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2905 emit_int8(0x0F); 2906 emit_int8((unsigned char)0xB7); 2907 emit_int8(0xC0 | encode); 2908 } 2909 2910 void Assembler::mull(Address src) { 2911 InstructionMark im(this); 2912 prefix(src); 2913 emit_int8((unsigned char)0xF7); 2914 emit_operand(rsp, src); 2915 } 2916 2917 void Assembler::mull(Register src) { 2918 int encode = prefix_and_encode(src->encoding()); 2919 emit_int8((unsigned char)0xF7); 2920 emit_int8((unsigned char)(0xE0 | encode)); 2921 } 2922 2923 void Assembler::mulsd(XMMRegister dst, Address src) { 2924 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2925 InstructionMark im(this); 2926 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2927 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2928 attributes.set_rex_vex_w_reverted(); 2929 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2930 emit_int8(0x59); 2931 emit_operand(dst, src); 2932 } 2933 2934 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2935 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2936 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2937 attributes.set_rex_vex_w_reverted(); 2938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2939 emit_int8(0x59); 2940 emit_int8((unsigned char)(0xC0 | encode)); 2941 } 2942 2943 void Assembler::mulss(XMMRegister dst, Address src) { 2944 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2945 InstructionMark im(this); 2946 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2947 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2948 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2949 emit_int8(0x59); 2950 emit_operand(dst, src); 2951 } 2952 2953 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 2954 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2955 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2956 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2957 emit_int8(0x59); 2958 emit_int8((unsigned char)(0xC0 | encode)); 2959 } 2960 2961 void Assembler::negl(Register dst) { 2962 int encode = prefix_and_encode(dst->encoding()); 2963 emit_int8((unsigned char)0xF7); 2964 emit_int8((unsigned char)(0xD8 | encode)); 2965 } 2966 2967 void Assembler::nop(int i) { 2968 #ifdef ASSERT 2969 assert(i > 0, " "); 2970 // The fancy nops aren't currently recognized by debuggers making it a 2971 // pain to disassemble code while debugging. If asserts are on clearly 2972 // speed is not an issue so simply use the single byte traditional nop 2973 // to do alignment. 2974 2975 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 2976 return; 2977 2978 #endif // ASSERT 2979 2980 if (UseAddressNop && VM_Version::is_intel()) { 2981 // 2982 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 2983 // 1: 0x90 2984 // 2: 0x66 0x90 2985 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2986 // 4: 0x0F 0x1F 0x40 0x00 2987 // 5: 0x0F 0x1F 0x44 0x00 0x00 2988 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2989 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2990 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2991 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2992 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2993 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2994 2995 // The rest coding is Intel specific - don't use consecutive address nops 2996 2997 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2998 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2999 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3000 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3001 3002 while(i >= 15) { 3003 // For Intel don't generate consecutive addess nops (mix with regular nops) 3004 i -= 15; 3005 emit_int8(0x66); // size prefix 3006 emit_int8(0x66); // size prefix 3007 emit_int8(0x66); // size prefix 3008 addr_nop_8(); 3009 emit_int8(0x66); // size prefix 3010 emit_int8(0x66); // size prefix 3011 emit_int8(0x66); // size prefix 3012 emit_int8((unsigned char)0x90); 3013 // nop 3014 } 3015 switch (i) { 3016 case 14: 3017 emit_int8(0x66); // size prefix 3018 case 13: 3019 emit_int8(0x66); // size prefix 3020 case 12: 3021 addr_nop_8(); 3022 emit_int8(0x66); // size prefix 3023 emit_int8(0x66); // size prefix 3024 emit_int8(0x66); // size prefix 3025 emit_int8((unsigned char)0x90); 3026 // nop 3027 break; 3028 case 11: 3029 emit_int8(0x66); // size prefix 3030 case 10: 3031 emit_int8(0x66); // size prefix 3032 case 9: 3033 emit_int8(0x66); // size prefix 3034 case 8: 3035 addr_nop_8(); 3036 break; 3037 case 7: 3038 addr_nop_7(); 3039 break; 3040 case 6: 3041 emit_int8(0x66); // size prefix 3042 case 5: 3043 addr_nop_5(); 3044 break; 3045 case 4: 3046 addr_nop_4(); 3047 break; 3048 case 3: 3049 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3050 emit_int8(0x66); // size prefix 3051 case 2: 3052 emit_int8(0x66); // size prefix 3053 case 1: 3054 emit_int8((unsigned char)0x90); 3055 // nop 3056 break; 3057 default: 3058 assert(i == 0, " "); 3059 } 3060 return; 3061 } 3062 if (UseAddressNop && VM_Version::is_amd()) { 3063 // 3064 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 3065 // 1: 0x90 3066 // 2: 0x66 0x90 3067 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3068 // 4: 0x0F 0x1F 0x40 0x00 3069 // 5: 0x0F 0x1F 0x44 0x00 0x00 3070 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3071 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3072 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3073 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3074 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3075 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3076 3077 // The rest coding is AMD specific - use consecutive address nops 3078 3079 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3080 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3081 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3082 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3083 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3084 // Size prefixes (0x66) are added for larger sizes 3085 3086 while(i >= 22) { 3087 i -= 11; 3088 emit_int8(0x66); // size prefix 3089 emit_int8(0x66); // size prefix 3090 emit_int8(0x66); // size prefix 3091 addr_nop_8(); 3092 } 3093 // Generate first nop for size between 21-12 3094 switch (i) { 3095 case 21: 3096 i -= 1; 3097 emit_int8(0x66); // size prefix 3098 case 20: 3099 case 19: 3100 i -= 1; 3101 emit_int8(0x66); // size prefix 3102 case 18: 3103 case 17: 3104 i -= 1; 3105 emit_int8(0x66); // size prefix 3106 case 16: 3107 case 15: 3108 i -= 8; 3109 addr_nop_8(); 3110 break; 3111 case 14: 3112 case 13: 3113 i -= 7; 3114 addr_nop_7(); 3115 break; 3116 case 12: 3117 i -= 6; 3118 emit_int8(0x66); // size prefix 3119 addr_nop_5(); 3120 break; 3121 default: 3122 assert(i < 12, " "); 3123 } 3124 3125 // Generate second nop for size between 11-1 3126 switch (i) { 3127 case 11: 3128 emit_int8(0x66); // size prefix 3129 case 10: 3130 emit_int8(0x66); // size prefix 3131 case 9: 3132 emit_int8(0x66); // size prefix 3133 case 8: 3134 addr_nop_8(); 3135 break; 3136 case 7: 3137 addr_nop_7(); 3138 break; 3139 case 6: 3140 emit_int8(0x66); // size prefix 3141 case 5: 3142 addr_nop_5(); 3143 break; 3144 case 4: 3145 addr_nop_4(); 3146 break; 3147 case 3: 3148 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3149 emit_int8(0x66); // size prefix 3150 case 2: 3151 emit_int8(0x66); // size prefix 3152 case 1: 3153 emit_int8((unsigned char)0x90); 3154 // nop 3155 break; 3156 default: 3157 assert(i == 0, " "); 3158 } 3159 return; 3160 } 3161 3162 // Using nops with size prefixes "0x66 0x90". 3163 // From AMD Optimization Guide: 3164 // 1: 0x90 3165 // 2: 0x66 0x90 3166 // 3: 0x66 0x66 0x90 3167 // 4: 0x66 0x66 0x66 0x90 3168 // 5: 0x66 0x66 0x90 0x66 0x90 3169 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 3170 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 3171 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 3172 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3173 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3174 // 3175 while(i > 12) { 3176 i -= 4; 3177 emit_int8(0x66); // size prefix 3178 emit_int8(0x66); 3179 emit_int8(0x66); 3180 emit_int8((unsigned char)0x90); 3181 // nop 3182 } 3183 // 1 - 12 nops 3184 if(i > 8) { 3185 if(i > 9) { 3186 i -= 1; 3187 emit_int8(0x66); 3188 } 3189 i -= 3; 3190 emit_int8(0x66); 3191 emit_int8(0x66); 3192 emit_int8((unsigned char)0x90); 3193 } 3194 // 1 - 8 nops 3195 if(i > 4) { 3196 if(i > 6) { 3197 i -= 1; 3198 emit_int8(0x66); 3199 } 3200 i -= 3; 3201 emit_int8(0x66); 3202 emit_int8(0x66); 3203 emit_int8((unsigned char)0x90); 3204 } 3205 switch (i) { 3206 case 4: 3207 emit_int8(0x66); 3208 case 3: 3209 emit_int8(0x66); 3210 case 2: 3211 emit_int8(0x66); 3212 case 1: 3213 emit_int8((unsigned char)0x90); 3214 break; 3215 default: 3216 assert(i == 0, " "); 3217 } 3218 } 3219 3220 void Assembler::notl(Register dst) { 3221 int encode = prefix_and_encode(dst->encoding()); 3222 emit_int8((unsigned char)0xF7); 3223 emit_int8((unsigned char)(0xD0 | encode)); 3224 } 3225 3226 void Assembler::orl(Address dst, int32_t imm32) { 3227 InstructionMark im(this); 3228 prefix(dst); 3229 emit_arith_operand(0x81, rcx, dst, imm32); 3230 } 3231 3232 void Assembler::orl(Register dst, int32_t imm32) { 3233 prefix(dst); 3234 emit_arith(0x81, 0xC8, dst, imm32); 3235 } 3236 3237 void Assembler::orl(Register dst, Address src) { 3238 InstructionMark im(this); 3239 prefix(src, dst); 3240 emit_int8(0x0B); 3241 emit_operand(dst, src); 3242 } 3243 3244 void Assembler::orl(Register dst, Register src) { 3245 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3246 emit_arith(0x0B, 0xC0, dst, src); 3247 } 3248 3249 void Assembler::orl(Address dst, Register src) { 3250 InstructionMark im(this); 3251 prefix(dst, src); 3252 emit_int8(0x09); 3253 emit_operand(src, dst); 3254 } 3255 3256 void Assembler::packuswb(XMMRegister dst, Address src) { 3257 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3258 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3259 InstructionMark im(this); 3260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3261 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3262 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3263 emit_int8(0x67); 3264 emit_operand(dst, src); 3265 } 3266 3267 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 3268 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3271 emit_int8(0x67); 3272 emit_int8((unsigned char)(0xC0 | encode)); 3273 } 3274 3275 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3276 assert(UseAVX > 0, "some form of AVX must be enabled"); 3277 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3278 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3279 emit_int8(0x67); 3280 emit_int8((unsigned char)(0xC0 | encode)); 3281 } 3282 3283 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 3284 assert(VM_Version::supports_avx2(), ""); 3285 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3286 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3287 emit_int8(0x00); 3288 emit_int8(0xC0 | encode); 3289 emit_int8(imm8); 3290 } 3291 3292 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3293 assert(VM_Version::supports_avx2(), ""); 3294 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3296 emit_int8(0x46); 3297 emit_int8(0xC0 | encode); 3298 emit_int8(imm8); 3299 } 3300 3301 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3302 assert(VM_Version::supports_avx(), ""); 3303 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3304 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3305 emit_int8(0x06); 3306 emit_int8(0xC0 | encode); 3307 emit_int8(imm8); 3308 } 3309 3310 3311 void Assembler::pause() { 3312 emit_int8((unsigned char)0xF3); 3313 emit_int8((unsigned char)0x90); 3314 } 3315 3316 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3317 assert(VM_Version::supports_sse4_2(), ""); 3318 InstructionMark im(this); 3319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3320 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3321 emit_int8(0x61); 3322 emit_operand(dst, src); 3323 emit_int8(imm8); 3324 } 3325 3326 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3327 assert(VM_Version::supports_sse4_2(), ""); 3328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3329 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3330 emit_int8(0x61); 3331 emit_int8((unsigned char)(0xC0 | encode)); 3332 emit_int8(imm8); 3333 } 3334 3335 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3336 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3337 assert(VM_Version::supports_sse2(), ""); 3338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3340 emit_int8(0x74); 3341 emit_int8((unsigned char)(0xC0 | encode)); 3342 } 3343 3344 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3345 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3346 assert(VM_Version::supports_avx(), ""); 3347 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3349 emit_int8(0x74); 3350 emit_int8((unsigned char)(0xC0 | encode)); 3351 } 3352 3353 // In this context, kdst is written the mask used to process the equal components 3354 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3355 assert(VM_Version::supports_avx512bw(), ""); 3356 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3357 attributes.set_is_evex_instruction(); 3358 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3359 emit_int8(0x74); 3360 emit_int8((unsigned char)(0xC0 | encode)); 3361 } 3362 3363 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3364 assert(VM_Version::supports_avx512vlbw(), ""); 3365 InstructionMark im(this); 3366 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3368 attributes.set_is_evex_instruction(); 3369 int dst_enc = kdst->encoding(); 3370 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3371 emit_int8(0x64); 3372 emit_operand(as_Register(dst_enc), src); 3373 } 3374 3375 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3376 assert(is_vector_masking(), ""); 3377 assert(VM_Version::supports_avx512vlbw(), ""); 3378 InstructionMark im(this); 3379 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3380 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3381 attributes.reset_is_clear_context(); 3382 attributes.set_embedded_opmask_register_specifier(mask); 3383 attributes.set_is_evex_instruction(); 3384 int dst_enc = kdst->encoding(); 3385 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3386 emit_int8(0x64); 3387 emit_operand(as_Register(dst_enc), src); 3388 } 3389 3390 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3391 assert(VM_Version::supports_avx512vlbw(), ""); 3392 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3393 attributes.set_is_evex_instruction(); 3394 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3395 emit_int8(0x3E); 3396 emit_int8((unsigned char)(0xC0 | encode)); 3397 emit_int8(vcc); 3398 } 3399 3400 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3401 assert(is_vector_masking(), ""); 3402 assert(VM_Version::supports_avx512vlbw(), ""); 3403 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3404 attributes.reset_is_clear_context(); 3405 attributes.set_embedded_opmask_register_specifier(mask); 3406 attributes.set_is_evex_instruction(); 3407 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3408 emit_int8(0x3E); 3409 emit_int8((unsigned char)(0xC0 | encode)); 3410 emit_int8(vcc); 3411 } 3412 3413 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { 3414 assert(VM_Version::supports_avx512vlbw(), ""); 3415 InstructionMark im(this); 3416 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3417 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3418 attributes.set_is_evex_instruction(); 3419 int dst_enc = kdst->encoding(); 3420 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3421 emit_int8(0x3E); 3422 emit_operand(as_Register(dst_enc), src); 3423 emit_int8(vcc); 3424 } 3425 3426 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3427 assert(VM_Version::supports_avx512bw(), ""); 3428 InstructionMark im(this); 3429 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3430 attributes.set_is_evex_instruction(); 3431 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3432 int dst_enc = kdst->encoding(); 3433 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3434 emit_int8(0x74); 3435 emit_operand(as_Register(dst_enc), src); 3436 } 3437 3438 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3439 assert(VM_Version::supports_avx512vlbw(), ""); 3440 assert(is_vector_masking(), ""); // For stub code use only 3441 InstructionMark im(this); 3442 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false); 3443 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3444 attributes.reset_is_clear_context(); 3445 attributes.set_embedded_opmask_register_specifier(mask); 3446 attributes.set_is_evex_instruction(); 3447 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3448 emit_int8(0x74); 3449 emit_operand(as_Register(kdst->encoding()), src); 3450 } 3451 3452 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3453 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3454 assert(VM_Version::supports_sse2(), ""); 3455 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3456 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3457 emit_int8(0x75); 3458 emit_int8((unsigned char)(0xC0 | encode)); 3459 } 3460 3461 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3462 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3463 assert(VM_Version::supports_avx(), ""); 3464 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3465 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3466 emit_int8(0x75); 3467 emit_int8((unsigned char)(0xC0 | encode)); 3468 } 3469 3470 // In this context, kdst is written the mask used to process the equal components 3471 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3472 assert(VM_Version::supports_avx512bw(), ""); 3473 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3474 attributes.set_is_evex_instruction(); 3475 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3476 emit_int8(0x75); 3477 emit_int8((unsigned char)(0xC0 | encode)); 3478 } 3479 3480 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3481 assert(VM_Version::supports_avx512bw(), ""); 3482 InstructionMark im(this); 3483 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3484 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3485 attributes.set_is_evex_instruction(); 3486 int dst_enc = kdst->encoding(); 3487 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3488 emit_int8(0x75); 3489 emit_operand(as_Register(dst_enc), src); 3490 } 3491 3492 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3493 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { 3494 assert(VM_Version::supports_sse2(), ""); 3495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3496 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3497 emit_int8(0x76); 3498 emit_int8((unsigned char)(0xC0 | encode)); 3499 } 3500 3501 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3502 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3503 assert(VM_Version::supports_avx(), ""); 3504 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3505 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3506 emit_int8(0x76); 3507 emit_int8((unsigned char)(0xC0 | encode)); 3508 } 3509 3510 // In this context, kdst is written the mask used to process the equal components 3511 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3512 assert(VM_Version::supports_evex(), ""); 3513 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3514 attributes.set_is_evex_instruction(); 3515 attributes.reset_is_clear_context(); 3516 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3517 emit_int8(0x76); 3518 emit_int8((unsigned char)(0xC0 | encode)); 3519 } 3520 3521 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3522 assert(VM_Version::supports_evex(), ""); 3523 InstructionMark im(this); 3524 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3525 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3526 attributes.reset_is_clear_context(); 3527 attributes.set_is_evex_instruction(); 3528 int dst_enc = kdst->encoding(); 3529 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3530 emit_int8(0x76); 3531 emit_operand(as_Register(dst_enc), src); 3532 } 3533 3534 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3535 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { 3536 assert(VM_Version::supports_sse4_1(), ""); 3537 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3538 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3539 emit_int8(0x29); 3540 emit_int8((unsigned char)(0xC0 | encode)); 3541 } 3542 3543 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3544 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3545 assert(VM_Version::supports_avx(), ""); 3546 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3547 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3548 emit_int8(0x29); 3549 emit_int8((unsigned char)(0xC0 | encode)); 3550 } 3551 3552 // In this context, kdst is written the mask used to process the equal components 3553 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3554 assert(VM_Version::supports_evex(), ""); 3555 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3556 attributes.reset_is_clear_context(); 3557 attributes.set_is_evex_instruction(); 3558 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3559 emit_int8(0x29); 3560 emit_int8((unsigned char)(0xC0 | encode)); 3561 } 3562 3563 // In this context, kdst is written the mask used to process the equal components 3564 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3565 assert(VM_Version::supports_evex(), ""); 3566 InstructionMark im(this); 3567 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3568 attributes.reset_is_clear_context(); 3569 attributes.set_is_evex_instruction(); 3570 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 3571 int dst_enc = kdst->encoding(); 3572 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3573 emit_int8(0x29); 3574 emit_operand(as_Register(dst_enc), src); 3575 } 3576 3577 void Assembler::pmovmskb(Register dst, XMMRegister src) { 3578 assert(VM_Version::supports_sse2(), ""); 3579 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3580 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3581 emit_int8((unsigned char)0xD7); 3582 emit_int8((unsigned char)(0xC0 | encode)); 3583 } 3584 3585 void Assembler::vpmovmskb(Register dst, XMMRegister src) { 3586 assert(VM_Version::supports_avx2(), ""); 3587 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3588 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3589 emit_int8((unsigned char)0xD7); 3590 emit_int8((unsigned char)(0xC0 | encode)); 3591 } 3592 3593 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 3594 assert(VM_Version::supports_sse4_1(), ""); 3595 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3596 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3597 emit_int8(0x16); 3598 emit_int8((unsigned char)(0xC0 | encode)); 3599 emit_int8(imm8); 3600 } 3601 3602 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { 3603 assert(VM_Version::supports_sse4_1(), ""); 3604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3605 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3606 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3607 emit_int8(0x16); 3608 emit_operand(src, dst); 3609 emit_int8(imm8); 3610 } 3611 3612 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 3613 assert(VM_Version::supports_sse4_1(), ""); 3614 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3615 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3616 emit_int8(0x16); 3617 emit_int8((unsigned char)(0xC0 | encode)); 3618 emit_int8(imm8); 3619 } 3620 3621 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { 3622 assert(VM_Version::supports_sse4_1(), ""); 3623 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3624 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3625 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3626 emit_int8(0x16); 3627 emit_operand(src, dst); 3628 emit_int8(imm8); 3629 } 3630 3631 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { 3632 assert(VM_Version::supports_sse2(), ""); 3633 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3634 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3635 emit_int8((unsigned char)0xC5); 3636 emit_int8((unsigned char)(0xC0 | encode)); 3637 emit_int8(imm8); 3638 } 3639 3640 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { 3641 assert(VM_Version::supports_sse4_1(), ""); 3642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3643 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3644 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3645 emit_int8((unsigned char)0x15); 3646 emit_operand(src, dst); 3647 emit_int8(imm8); 3648 } 3649 3650 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { 3651 assert(VM_Version::supports_sse4_1(), ""); 3652 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3653 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3654 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3655 emit_int8(0x14); 3656 emit_operand(src, dst); 3657 emit_int8(imm8); 3658 } 3659 3660 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 3661 assert(VM_Version::supports_sse4_1(), ""); 3662 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3663 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3664 emit_int8(0x22); 3665 emit_int8((unsigned char)(0xC0 | encode)); 3666 emit_int8(imm8); 3667 } 3668 3669 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { 3670 assert(VM_Version::supports_sse4_1(), ""); 3671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3672 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3673 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3674 emit_int8(0x22); 3675 emit_operand(dst,src); 3676 emit_int8(imm8); 3677 } 3678 3679 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 3680 assert(VM_Version::supports_sse4_1(), ""); 3681 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3682 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3683 emit_int8(0x22); 3684 emit_int8((unsigned char)(0xC0 | encode)); 3685 emit_int8(imm8); 3686 } 3687 3688 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { 3689 assert(VM_Version::supports_sse4_1(), ""); 3690 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3692 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3693 emit_int8(0x22); 3694 emit_operand(dst, src); 3695 emit_int8(imm8); 3696 } 3697 3698 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { 3699 assert(VM_Version::supports_sse2(), ""); 3700 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3701 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3702 emit_int8((unsigned char)0xC4); 3703 emit_int8((unsigned char)(0xC0 | encode)); 3704 emit_int8(imm8); 3705 } 3706 3707 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { 3708 assert(VM_Version::supports_sse2(), ""); 3709 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3710 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3711 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3712 emit_int8((unsigned char)0xC4); 3713 emit_operand(dst, src); 3714 emit_int8(imm8); 3715 } 3716 3717 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { 3718 assert(VM_Version::supports_sse4_1(), ""); 3719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3720 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3721 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3722 emit_int8(0x20); 3723 emit_operand(dst, src); 3724 emit_int8(imm8); 3725 } 3726 3727 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 3728 assert(VM_Version::supports_sse4_1(), ""); 3729 InstructionMark im(this); 3730 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3731 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3732 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3733 emit_int8(0x30); 3734 emit_operand(dst, src); 3735 } 3736 3737 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3738 assert(VM_Version::supports_sse4_1(), ""); 3739 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3740 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3741 emit_int8(0x30); 3742 emit_int8((unsigned char)(0xC0 | encode)); 3743 } 3744 3745 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3746 assert(VM_Version::supports_avx(), ""); 3747 InstructionMark im(this); 3748 assert(dst != xnoreg, "sanity"); 3749 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3750 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3751 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3752 emit_int8(0x30); 3753 emit_operand(dst, src); 3754 } 3755 3756 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 3757 assert(is_vector_masking(), ""); 3758 assert(VM_Version::supports_avx512vlbw(), ""); 3759 assert(dst != xnoreg, "sanity"); 3760 InstructionMark im(this); 3761 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3762 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3763 attributes.set_embedded_opmask_register_specifier(mask); 3764 attributes.set_is_evex_instruction(); 3765 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3766 emit_int8(0x30); 3767 emit_operand(dst, src); 3768 } 3769 3770 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { 3771 assert(VM_Version::supports_avx512vlbw(), ""); 3772 assert(src != xnoreg, "sanity"); 3773 InstructionMark im(this); 3774 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3775 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3776 attributes.set_is_evex_instruction(); 3777 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3778 emit_int8(0x30); 3779 emit_operand(src, dst); 3780 } 3781 3782 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { 3783 assert(is_vector_masking(), ""); 3784 assert(VM_Version::supports_avx512vlbw(), ""); 3785 assert(src != xnoreg, "sanity"); 3786 InstructionMark im(this); 3787 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3788 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3789 attributes.reset_is_clear_context(); 3790 attributes.set_embedded_opmask_register_specifier(mask); 3791 attributes.set_is_evex_instruction(); 3792 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3793 emit_int8(0x30); 3794 emit_operand(src, dst); 3795 } 3796 3797 // generic 3798 void Assembler::pop(Register dst) { 3799 int encode = prefix_and_encode(dst->encoding()); 3800 emit_int8(0x58 | encode); 3801 } 3802 3803 void Assembler::popcntl(Register dst, Address src) { 3804 assert(VM_Version::supports_popcnt(), "must support"); 3805 InstructionMark im(this); 3806 emit_int8((unsigned char)0xF3); 3807 prefix(src, dst); 3808 emit_int8(0x0F); 3809 emit_int8((unsigned char)0xB8); 3810 emit_operand(dst, src); 3811 } 3812 3813 void Assembler::popcntl(Register dst, Register src) { 3814 assert(VM_Version::supports_popcnt(), "must support"); 3815 emit_int8((unsigned char)0xF3); 3816 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3817 emit_int8(0x0F); 3818 emit_int8((unsigned char)0xB8); 3819 emit_int8((unsigned char)(0xC0 | encode)); 3820 } 3821 3822 void Assembler::popf() { 3823 emit_int8((unsigned char)0x9D); 3824 } 3825 3826 #ifndef _LP64 // no 32bit push/pop on amd64 3827 void Assembler::popl(Address dst) { 3828 // NOTE: this will adjust stack by 8byte on 64bits 3829 InstructionMark im(this); 3830 prefix(dst); 3831 emit_int8((unsigned char)0x8F); 3832 emit_operand(rax, dst); 3833 } 3834 #endif 3835 3836 void Assembler::prefetch_prefix(Address src) { 3837 prefix(src); 3838 emit_int8(0x0F); 3839 } 3840 3841 void Assembler::prefetchnta(Address src) { 3842 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3843 InstructionMark im(this); 3844 prefetch_prefix(src); 3845 emit_int8(0x18); 3846 emit_operand(rax, src); // 0, src 3847 } 3848 3849 void Assembler::prefetchr(Address src) { 3850 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3851 InstructionMark im(this); 3852 prefetch_prefix(src); 3853 emit_int8(0x0D); 3854 emit_operand(rax, src); // 0, src 3855 } 3856 3857 void Assembler::prefetcht0(Address src) { 3858 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3859 InstructionMark im(this); 3860 prefetch_prefix(src); 3861 emit_int8(0x18); 3862 emit_operand(rcx, src); // 1, src 3863 } 3864 3865 void Assembler::prefetcht1(Address src) { 3866 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3867 InstructionMark im(this); 3868 prefetch_prefix(src); 3869 emit_int8(0x18); 3870 emit_operand(rdx, src); // 2, src 3871 } 3872 3873 void Assembler::prefetcht2(Address src) { 3874 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3875 InstructionMark im(this); 3876 prefetch_prefix(src); 3877 emit_int8(0x18); 3878 emit_operand(rbx, src); // 3, src 3879 } 3880 3881 void Assembler::prefetchw(Address src) { 3882 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3883 InstructionMark im(this); 3884 prefetch_prefix(src); 3885 emit_int8(0x0D); 3886 emit_operand(rcx, src); // 1, src 3887 } 3888 3889 void Assembler::prefix(Prefix p) { 3890 emit_int8(p); 3891 } 3892 3893 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 3894 assert(VM_Version::supports_ssse3(), ""); 3895 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3897 emit_int8(0x00); 3898 emit_int8((unsigned char)(0xC0 | encode)); 3899 } 3900 3901 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3902 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3903 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3904 0, ""); 3905 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3906 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3907 emit_int8(0x00); 3908 emit_int8((unsigned char)(0xC0 | encode)); 3909 } 3910 3911 void Assembler::pshufb(XMMRegister dst, Address src) { 3912 assert(VM_Version::supports_ssse3(), ""); 3913 InstructionMark im(this); 3914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3915 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3916 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3917 emit_int8(0x00); 3918 emit_operand(dst, src); 3919 } 3920 3921 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 3922 assert(isByte(mode), "invalid value"); 3923 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3924 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 3925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3926 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3927 emit_int8(0x70); 3928 emit_int8((unsigned char)(0xC0 | encode)); 3929 emit_int8(mode & 0xFF); 3930 } 3931 3932 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { 3933 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3934 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3935 0, ""); 3936 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3937 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3938 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3939 emit_int8(0x70); 3940 emit_int8((unsigned char)(0xC0 | encode)); 3941 emit_int8(mode & 0xFF); 3942 } 3943 3944 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 3945 assert(isByte(mode), "invalid value"); 3946 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3947 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3948 InstructionMark im(this); 3949 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3950 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3951 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3952 emit_int8(0x70); 3953 emit_operand(dst, src); 3954 emit_int8(mode & 0xFF); 3955 } 3956 3957 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3958 assert(isByte(mode), "invalid value"); 3959 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3961 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3962 emit_int8(0x70); 3963 emit_int8((unsigned char)(0xC0 | encode)); 3964 emit_int8(mode & 0xFF); 3965 } 3966 3967 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 3968 assert(isByte(mode), "invalid value"); 3969 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3970 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3971 InstructionMark im(this); 3972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3973 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3974 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3975 emit_int8(0x70); 3976 emit_operand(dst, src); 3977 emit_int8(mode & 0xFF); 3978 } 3979 3980 void Assembler::psrldq(XMMRegister dst, int shift) { 3981 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 3982 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3983 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3984 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3985 emit_int8(0x73); 3986 emit_int8((unsigned char)(0xC0 | encode)); 3987 emit_int8(shift); 3988 } 3989 3990 void Assembler::pslldq(XMMRegister dst, int shift) { 3991 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 3992 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3993 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3994 // XMM7 is for /7 encoding: 66 0F 73 /7 ib 3995 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3996 emit_int8(0x73); 3997 emit_int8((unsigned char)(0xC0 | encode)); 3998 emit_int8(shift); 3999 } 4000 4001 void Assembler::ptest(XMMRegister dst, Address src) { 4002 assert(VM_Version::supports_sse4_1(), ""); 4003 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4004 InstructionMark im(this); 4005 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4006 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4007 emit_int8(0x17); 4008 emit_operand(dst, src); 4009 } 4010 4011 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 4012 assert(VM_Version::supports_sse4_1(), ""); 4013 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4014 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4015 emit_int8(0x17); 4016 emit_int8((unsigned char)(0xC0 | encode)); 4017 } 4018 4019 void Assembler::vptest(XMMRegister dst, Address src) { 4020 assert(VM_Version::supports_avx(), ""); 4021 InstructionMark im(this); 4022 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4023 assert(dst != xnoreg, "sanity"); 4024 // swap src<->dst for encoding 4025 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4026 emit_int8(0x17); 4027 emit_operand(dst, src); 4028 } 4029 4030 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 4031 assert(VM_Version::supports_avx(), ""); 4032 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4033 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4034 emit_int8(0x17); 4035 emit_int8((unsigned char)(0xC0 | encode)); 4036 } 4037 4038 void Assembler::punpcklbw(XMMRegister dst, Address src) { 4039 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4040 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4041 InstructionMark im(this); 4042 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4043 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4044 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4045 emit_int8(0x60); 4046 emit_operand(dst, src); 4047 } 4048 4049 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4050 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4052 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4053 emit_int8(0x60); 4054 emit_int8((unsigned char)(0xC0 | encode)); 4055 } 4056 4057 void Assembler::punpckldq(XMMRegister dst, Address src) { 4058 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4059 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4060 InstructionMark im(this); 4061 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4062 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4063 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4064 emit_int8(0x62); 4065 emit_operand(dst, src); 4066 } 4067 4068 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 4069 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4070 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4072 emit_int8(0x62); 4073 emit_int8((unsigned char)(0xC0 | encode)); 4074 } 4075 4076 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 4077 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4078 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4079 attributes.set_rex_vex_w_reverted(); 4080 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4081 emit_int8(0x6C); 4082 emit_int8((unsigned char)(0xC0 | encode)); 4083 } 4084 4085 void Assembler::push(int32_t imm32) { 4086 // in 64bits we push 64bits onto the stack but only 4087 // take a 32bit immediate 4088 emit_int8(0x68); 4089 emit_int32(imm32); 4090 } 4091 4092 void Assembler::push(Register src) { 4093 int encode = prefix_and_encode(src->encoding()); 4094 4095 emit_int8(0x50 | encode); 4096 } 4097 4098 void Assembler::pushf() { 4099 emit_int8((unsigned char)0x9C); 4100 } 4101 4102 #ifndef _LP64 // no 32bit push/pop on amd64 4103 void Assembler::pushl(Address src) { 4104 // Note this will push 64bit on 64bit 4105 InstructionMark im(this); 4106 prefix(src); 4107 emit_int8((unsigned char)0xFF); 4108 emit_operand(rsi, src); 4109 } 4110 #endif 4111 4112 void Assembler::rcll(Register dst, int imm8) { 4113 assert(isShiftCount(imm8), "illegal shift count"); 4114 int encode = prefix_and_encode(dst->encoding()); 4115 if (imm8 == 1) { 4116 emit_int8((unsigned char)0xD1); 4117 emit_int8((unsigned char)(0xD0 | encode)); 4118 } else { 4119 emit_int8((unsigned char)0xC1); 4120 emit_int8((unsigned char)0xD0 | encode); 4121 emit_int8(imm8); 4122 } 4123 } 4124 4125 void Assembler::rcpps(XMMRegister dst, XMMRegister src) { 4126 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4127 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4128 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4129 emit_int8(0x53); 4130 emit_int8((unsigned char)(0xC0 | encode)); 4131 } 4132 4133 void Assembler::rcpss(XMMRegister dst, XMMRegister src) { 4134 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4135 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4136 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4137 emit_int8(0x53); 4138 emit_int8((unsigned char)(0xC0 | encode)); 4139 } 4140 4141 void Assembler::rdtsc() { 4142 emit_int8((unsigned char)0x0F); 4143 emit_int8((unsigned char)0x31); 4144 } 4145 4146 // copies data from [esi] to [edi] using rcx pointer sized words 4147 // generic 4148 void Assembler::rep_mov() { 4149 emit_int8((unsigned char)0xF3); 4150 // MOVSQ 4151 LP64_ONLY(prefix(REX_W)); 4152 emit_int8((unsigned char)0xA5); 4153 } 4154 4155 // sets rcx bytes with rax, value at [edi] 4156 void Assembler::rep_stosb() { 4157 emit_int8((unsigned char)0xF3); // REP 4158 LP64_ONLY(prefix(REX_W)); 4159 emit_int8((unsigned char)0xAA); // STOSB 4160 } 4161 4162 // sets rcx pointer sized words with rax, value at [edi] 4163 // generic 4164 void Assembler::rep_stos() { 4165 emit_int8((unsigned char)0xF3); // REP 4166 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 4167 emit_int8((unsigned char)0xAB); 4168 } 4169 4170 // scans rcx pointer sized words at [edi] for occurance of rax, 4171 // generic 4172 void Assembler::repne_scan() { // repne_scan 4173 emit_int8((unsigned char)0xF2); 4174 // SCASQ 4175 LP64_ONLY(prefix(REX_W)); 4176 emit_int8((unsigned char)0xAF); 4177 } 4178 4179 #ifdef _LP64 4180 // scans rcx 4 byte words at [edi] for occurance of rax, 4181 // generic 4182 void Assembler::repne_scanl() { // repne_scan 4183 emit_int8((unsigned char)0xF2); 4184 // SCASL 4185 emit_int8((unsigned char)0xAF); 4186 } 4187 #endif 4188 4189 void Assembler::ret(int imm16) { 4190 if (imm16 == 0) { 4191 emit_int8((unsigned char)0xC3); 4192 } else { 4193 emit_int8((unsigned char)0xC2); 4194 emit_int16(imm16); 4195 } 4196 } 4197 4198 void Assembler::sahf() { 4199 #ifdef _LP64 4200 // Not supported in 64bit mode 4201 ShouldNotReachHere(); 4202 #endif 4203 emit_int8((unsigned char)0x9E); 4204 } 4205 4206 void Assembler::sarl(Register dst, int imm8) { 4207 int encode = prefix_and_encode(dst->encoding()); 4208 assert(isShiftCount(imm8), "illegal shift count"); 4209 if (imm8 == 1) { 4210 emit_int8((unsigned char)0xD1); 4211 emit_int8((unsigned char)(0xF8 | encode)); 4212 } else { 4213 emit_int8((unsigned char)0xC1); 4214 emit_int8((unsigned char)(0xF8 | encode)); 4215 emit_int8(imm8); 4216 } 4217 } 4218 4219 void Assembler::sarl(Register dst) { 4220 int encode = prefix_and_encode(dst->encoding()); 4221 emit_int8((unsigned char)0xD3); 4222 emit_int8((unsigned char)(0xF8 | encode)); 4223 } 4224 4225 void Assembler::sbbl(Address dst, int32_t imm32) { 4226 InstructionMark im(this); 4227 prefix(dst); 4228 emit_arith_operand(0x81, rbx, dst, imm32); 4229 } 4230 4231 void Assembler::sbbl(Register dst, int32_t imm32) { 4232 prefix(dst); 4233 emit_arith(0x81, 0xD8, dst, imm32); 4234 } 4235 4236 4237 void Assembler::sbbl(Register dst, Address src) { 4238 InstructionMark im(this); 4239 prefix(src, dst); 4240 emit_int8(0x1B); 4241 emit_operand(dst, src); 4242 } 4243 4244 void Assembler::sbbl(Register dst, Register src) { 4245 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4246 emit_arith(0x1B, 0xC0, dst, src); 4247 } 4248 4249 void Assembler::setb(Condition cc, Register dst) { 4250 assert(0 <= cc && cc < 16, "illegal cc"); 4251 int encode = prefix_and_encode(dst->encoding(), true); 4252 emit_int8(0x0F); 4253 emit_int8((unsigned char)0x90 | cc); 4254 emit_int8((unsigned char)(0xC0 | encode)); 4255 } 4256 4257 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { 4258 assert(VM_Version::supports_ssse3(), ""); 4259 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false); 4260 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4261 emit_int8((unsigned char)0x0F); 4262 emit_int8((unsigned char)(0xC0 | encode)); 4263 emit_int8(imm8); 4264 } 4265 4266 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4267 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4268 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4269 0, ""); 4270 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 4271 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4272 emit_int8((unsigned char)0x0F); 4273 emit_int8((unsigned char)(0xC0 | encode)); 4274 emit_int8(imm8); 4275 } 4276 4277 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { 4278 assert(VM_Version::supports_sse4_1(), ""); 4279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4281 emit_int8((unsigned char)0x0E); 4282 emit_int8((unsigned char)(0xC0 | encode)); 4283 emit_int8(imm8); 4284 } 4285 4286 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { 4287 assert(VM_Version::supports_sha(), ""); 4288 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false); 4289 emit_int8((unsigned char)0xCC); 4290 emit_int8((unsigned char)(0xC0 | encode)); 4291 emit_int8((unsigned char)imm8); 4292 } 4293 4294 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { 4295 assert(VM_Version::supports_sha(), ""); 4296 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4297 emit_int8((unsigned char)0xC8); 4298 emit_int8((unsigned char)(0xC0 | encode)); 4299 } 4300 4301 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { 4302 assert(VM_Version::supports_sha(), ""); 4303 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4304 emit_int8((unsigned char)0xC9); 4305 emit_int8((unsigned char)(0xC0 | encode)); 4306 } 4307 4308 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { 4309 assert(VM_Version::supports_sha(), ""); 4310 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4311 emit_int8((unsigned char)0xCA); 4312 emit_int8((unsigned char)(0xC0 | encode)); 4313 } 4314 4315 // xmm0 is implicit additional source to this instruction. 4316 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { 4317 assert(VM_Version::supports_sha(), ""); 4318 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4319 emit_int8((unsigned char)0xCB); 4320 emit_int8((unsigned char)(0xC0 | encode)); 4321 } 4322 4323 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { 4324 assert(VM_Version::supports_sha(), ""); 4325 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4326 emit_int8((unsigned char)0xCC); 4327 emit_int8((unsigned char)(0xC0 | encode)); 4328 } 4329 4330 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { 4331 assert(VM_Version::supports_sha(), ""); 4332 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4333 emit_int8((unsigned char)0xCD); 4334 emit_int8((unsigned char)(0xC0 | encode)); 4335 } 4336 4337 4338 void Assembler::shll(Register dst, int imm8) { 4339 assert(isShiftCount(imm8), "illegal shift count"); 4340 int encode = prefix_and_encode(dst->encoding()); 4341 if (imm8 == 1 ) { 4342 emit_int8((unsigned char)0xD1); 4343 emit_int8((unsigned char)(0xE0 | encode)); 4344 } else { 4345 emit_int8((unsigned char)0xC1); 4346 emit_int8((unsigned char)(0xE0 | encode)); 4347 emit_int8(imm8); 4348 } 4349 } 4350 4351 void Assembler::shll(Register dst) { 4352 int encode = prefix_and_encode(dst->encoding()); 4353 emit_int8((unsigned char)0xD3); 4354 emit_int8((unsigned char)(0xE0 | encode)); 4355 } 4356 4357 void Assembler::shrl(Register dst, int imm8) { 4358 assert(isShiftCount(imm8), "illegal shift count"); 4359 int encode = prefix_and_encode(dst->encoding()); 4360 emit_int8((unsigned char)0xC1); 4361 emit_int8((unsigned char)(0xE8 | encode)); 4362 emit_int8(imm8); 4363 } 4364 4365 void Assembler::shrl(Register dst) { 4366 int encode = prefix_and_encode(dst->encoding()); 4367 emit_int8((unsigned char)0xD3); 4368 emit_int8((unsigned char)(0xE8 | encode)); 4369 } 4370 4371 // copies a single word from [esi] to [edi] 4372 void Assembler::smovl() { 4373 emit_int8((unsigned char)0xA5); 4374 } 4375 4376 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 4377 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4378 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4379 attributes.set_rex_vex_w_reverted(); 4380 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4381 emit_int8(0x51); 4382 emit_int8((unsigned char)(0xC0 | encode)); 4383 } 4384 4385 void Assembler::sqrtsd(XMMRegister dst, Address src) { 4386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4387 InstructionMark im(this); 4388 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4389 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4390 attributes.set_rex_vex_w_reverted(); 4391 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4392 emit_int8(0x51); 4393 emit_operand(dst, src); 4394 } 4395 4396 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 4397 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4399 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4400 emit_int8(0x51); 4401 emit_int8((unsigned char)(0xC0 | encode)); 4402 } 4403 4404 void Assembler::std() { 4405 emit_int8((unsigned char)0xFD); 4406 } 4407 4408 void Assembler::sqrtss(XMMRegister dst, Address src) { 4409 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4410 InstructionMark im(this); 4411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4412 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4413 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4414 emit_int8(0x51); 4415 emit_operand(dst, src); 4416 } 4417 4418 void Assembler::stmxcsr( Address dst) { 4419 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4420 InstructionMark im(this); 4421 prefix(dst); 4422 emit_int8(0x0F); 4423 emit_int8((unsigned char)0xAE); 4424 emit_operand(as_Register(3), dst); 4425 } 4426 4427 void Assembler::subl(Address dst, int32_t imm32) { 4428 InstructionMark im(this); 4429 prefix(dst); 4430 emit_arith_operand(0x81, rbp, dst, imm32); 4431 } 4432 4433 void Assembler::subl(Address dst, Register src) { 4434 InstructionMark im(this); 4435 prefix(dst, src); 4436 emit_int8(0x29); 4437 emit_operand(src, dst); 4438 } 4439 4440 void Assembler::subl(Register dst, int32_t imm32) { 4441 prefix(dst); 4442 emit_arith(0x81, 0xE8, dst, imm32); 4443 } 4444 4445 // Force generation of a 4 byte immediate value even if it fits into 8bit 4446 void Assembler::subl_imm32(Register dst, int32_t imm32) { 4447 prefix(dst); 4448 emit_arith_imm32(0x81, 0xE8, dst, imm32); 4449 } 4450 4451 void Assembler::subl(Register dst, Address src) { 4452 InstructionMark im(this); 4453 prefix(src, dst); 4454 emit_int8(0x2B); 4455 emit_operand(dst, src); 4456 } 4457 4458 void Assembler::subl(Register dst, Register src) { 4459 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4460 emit_arith(0x2B, 0xC0, dst, src); 4461 } 4462 4463 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 4464 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4465 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4466 attributes.set_rex_vex_w_reverted(); 4467 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4468 emit_int8(0x5C); 4469 emit_int8((unsigned char)(0xC0 | encode)); 4470 } 4471 4472 void Assembler::subsd(XMMRegister dst, Address src) { 4473 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4474 InstructionMark im(this); 4475 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4476 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4477 attributes.set_rex_vex_w_reverted(); 4478 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4479 emit_int8(0x5C); 4480 emit_operand(dst, src); 4481 } 4482 4483 void Assembler::subss(XMMRegister dst, XMMRegister src) { 4484 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4485 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false); 4486 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4487 emit_int8(0x5C); 4488 emit_int8((unsigned char)(0xC0 | encode)); 4489 } 4490 4491 void Assembler::subss(XMMRegister dst, Address src) { 4492 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4493 InstructionMark im(this); 4494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4495 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4496 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4497 emit_int8(0x5C); 4498 emit_operand(dst, src); 4499 } 4500 4501 void Assembler::testb(Register dst, int imm8) { 4502 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 4503 (void) prefix_and_encode(dst->encoding(), true); 4504 emit_arith_b(0xF6, 0xC0, dst, imm8); 4505 } 4506 4507 void Assembler::testb(Address dst, int imm8) { 4508 InstructionMark im(this); 4509 prefix(dst); 4510 emit_int8((unsigned char)0xF6); 4511 emit_operand(rax, dst, 1); 4512 emit_int8(imm8); 4513 } 4514 4515 void Assembler::testl(Register dst, int32_t imm32) { 4516 // not using emit_arith because test 4517 // doesn't support sign-extension of 4518 // 8bit operands 4519 int encode = dst->encoding(); 4520 if (encode == 0) { 4521 emit_int8((unsigned char)0xA9); 4522 } else { 4523 encode = prefix_and_encode(encode); 4524 emit_int8((unsigned char)0xF7); 4525 emit_int8((unsigned char)(0xC0 | encode)); 4526 } 4527 emit_int32(imm32); 4528 } 4529 4530 void Assembler::testl(Register dst, Register src) { 4531 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4532 emit_arith(0x85, 0xC0, dst, src); 4533 } 4534 4535 void Assembler::testl(Register dst, Address src) { 4536 InstructionMark im(this); 4537 prefix(src, dst); 4538 emit_int8((unsigned char)0x85); 4539 emit_operand(dst, src); 4540 } 4541 4542 void Assembler::tzcntl(Register dst, Register src) { 4543 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4544 emit_int8((unsigned char)0xF3); 4545 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4546 emit_int8(0x0F); 4547 emit_int8((unsigned char)0xBC); 4548 emit_int8((unsigned char)0xC0 | encode); 4549 } 4550 4551 void Assembler::tzcntq(Register dst, Register src) { 4552 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4553 emit_int8((unsigned char)0xF3); 4554 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4555 emit_int8(0x0F); 4556 emit_int8((unsigned char)0xBC); 4557 emit_int8((unsigned char)(0xC0 | encode)); 4558 } 4559 4560 void Assembler::ucomisd(XMMRegister dst, Address src) { 4561 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4562 InstructionMark im(this); 4563 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4564 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4565 attributes.set_rex_vex_w_reverted(); 4566 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4567 emit_int8(0x2E); 4568 emit_operand(dst, src); 4569 } 4570 4571 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 4572 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4573 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4574 attributes.set_rex_vex_w_reverted(); 4575 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4576 emit_int8(0x2E); 4577 emit_int8((unsigned char)(0xC0 | encode)); 4578 } 4579 4580 void Assembler::ucomiss(XMMRegister dst, Address src) { 4581 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4582 InstructionMark im(this); 4583 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4584 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4585 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4586 emit_int8(0x2E); 4587 emit_operand(dst, src); 4588 } 4589 4590 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 4591 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4592 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4593 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4594 emit_int8(0x2E); 4595 emit_int8((unsigned char)(0xC0 | encode)); 4596 } 4597 4598 void Assembler::xabort(int8_t imm8) { 4599 emit_int8((unsigned char)0xC6); 4600 emit_int8((unsigned char)0xF8); 4601 emit_int8((unsigned char)(imm8 & 0xFF)); 4602 } 4603 4604 void Assembler::xaddb(Address dst, Register src) { 4605 InstructionMark im(this); 4606 prefix(dst, src, true); 4607 emit_int8(0x0F); 4608 emit_int8((unsigned char)0xC0); 4609 emit_operand(src, dst); 4610 } 4611 4612 void Assembler::xaddw(Address dst, Register src) { 4613 InstructionMark im(this); 4614 emit_int8(0x66); 4615 prefix(dst, src); 4616 emit_int8(0x0F); 4617 emit_int8((unsigned char)0xC1); 4618 emit_operand(src, dst); 4619 } 4620 4621 void Assembler::xaddl(Address dst, Register src) { 4622 InstructionMark im(this); 4623 prefix(dst, src); 4624 emit_int8(0x0F); 4625 emit_int8((unsigned char)0xC1); 4626 emit_operand(src, dst); 4627 } 4628 4629 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 4630 InstructionMark im(this); 4631 relocate(rtype); 4632 if (abort.is_bound()) { 4633 address entry = target(abort); 4634 assert(entry != NULL, "abort entry NULL"); 4635 intptr_t offset = entry - pc(); 4636 emit_int8((unsigned char)0xC7); 4637 emit_int8((unsigned char)0xF8); 4638 emit_int32(offset - 6); // 2 opcode + 4 address 4639 } else { 4640 abort.add_patch_at(code(), locator()); 4641 emit_int8((unsigned char)0xC7); 4642 emit_int8((unsigned char)0xF8); 4643 emit_int32(0); 4644 } 4645 } 4646 4647 void Assembler::xchgb(Register dst, Address src) { // xchg 4648 InstructionMark im(this); 4649 prefix(src, dst, true); 4650 emit_int8((unsigned char)0x86); 4651 emit_operand(dst, src); 4652 } 4653 4654 void Assembler::xchgw(Register dst, Address src) { // xchg 4655 InstructionMark im(this); 4656 emit_int8(0x66); 4657 prefix(src, dst); 4658 emit_int8((unsigned char)0x87); 4659 emit_operand(dst, src); 4660 } 4661 4662 void Assembler::xchgl(Register dst, Address src) { // xchg 4663 InstructionMark im(this); 4664 prefix(src, dst); 4665 emit_int8((unsigned char)0x87); 4666 emit_operand(dst, src); 4667 } 4668 4669 void Assembler::xchgl(Register dst, Register src) { 4670 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4671 emit_int8((unsigned char)0x87); 4672 emit_int8((unsigned char)(0xC0 | encode)); 4673 } 4674 4675 void Assembler::xend() { 4676 emit_int8((unsigned char)0x0F); 4677 emit_int8((unsigned char)0x01); 4678 emit_int8((unsigned char)0xD5); 4679 } 4680 4681 void Assembler::xgetbv() { 4682 emit_int8(0x0F); 4683 emit_int8(0x01); 4684 emit_int8((unsigned char)0xD0); 4685 } 4686 4687 void Assembler::xorl(Register dst, int32_t imm32) { 4688 prefix(dst); 4689 emit_arith(0x81, 0xF0, dst, imm32); 4690 } 4691 4692 void Assembler::xorl(Register dst, Address src) { 4693 InstructionMark im(this); 4694 prefix(src, dst); 4695 emit_int8(0x33); 4696 emit_operand(dst, src); 4697 } 4698 4699 void Assembler::xorl(Register dst, Register src) { 4700 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4701 emit_arith(0x33, 0xC0, dst, src); 4702 } 4703 4704 void Assembler::xorb(Register dst, Address src) { 4705 InstructionMark im(this); 4706 prefix(src, dst); 4707 emit_int8(0x32); 4708 emit_operand(dst, src); 4709 } 4710 4711 // AVX 3-operands scalar float-point arithmetic instructions 4712 4713 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 4714 assert(VM_Version::supports_avx(), ""); 4715 InstructionMark im(this); 4716 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4717 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4718 attributes.set_rex_vex_w_reverted(); 4719 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4720 emit_int8(0x58); 4721 emit_operand(dst, src); 4722 } 4723 4724 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4725 assert(VM_Version::supports_avx(), ""); 4726 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4727 attributes.set_rex_vex_w_reverted(); 4728 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4729 emit_int8(0x58); 4730 emit_int8((unsigned char)(0xC0 | encode)); 4731 } 4732 4733 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 4734 assert(VM_Version::supports_avx(), ""); 4735 InstructionMark im(this); 4736 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4737 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4738 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4739 emit_int8(0x58); 4740 emit_operand(dst, src); 4741 } 4742 4743 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4744 assert(VM_Version::supports_avx(), ""); 4745 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4746 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4747 emit_int8(0x58); 4748 emit_int8((unsigned char)(0xC0 | encode)); 4749 } 4750 4751 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 4752 assert(VM_Version::supports_avx(), ""); 4753 InstructionMark im(this); 4754 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4756 attributes.set_rex_vex_w_reverted(); 4757 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4758 emit_int8(0x5E); 4759 emit_operand(dst, src); 4760 } 4761 4762 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4763 assert(VM_Version::supports_avx(), ""); 4764 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4765 attributes.set_rex_vex_w_reverted(); 4766 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4767 emit_int8(0x5E); 4768 emit_int8((unsigned char)(0xC0 | encode)); 4769 } 4770 4771 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 4772 assert(VM_Version::supports_avx(), ""); 4773 InstructionMark im(this); 4774 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4775 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4776 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4777 emit_int8(0x5E); 4778 emit_operand(dst, src); 4779 } 4780 4781 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4782 assert(VM_Version::supports_avx(), ""); 4783 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4784 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4785 emit_int8(0x5E); 4786 emit_int8((unsigned char)(0xC0 | encode)); 4787 } 4788 4789 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 4790 assert(VM_Version::supports_fma(), ""); 4791 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4792 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4793 emit_int8((unsigned char)0xB9); 4794 emit_int8((unsigned char)(0xC0 | encode)); 4795 } 4796 4797 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 4798 assert(VM_Version::supports_fma(), ""); 4799 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4800 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4801 emit_int8((unsigned char)0xB9); 4802 emit_int8((unsigned char)(0xC0 | encode)); 4803 } 4804 4805 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 4806 assert(VM_Version::supports_avx(), ""); 4807 InstructionMark im(this); 4808 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4809 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4810 attributes.set_rex_vex_w_reverted(); 4811 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4812 emit_int8(0x59); 4813 emit_operand(dst, src); 4814 } 4815 4816 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4817 assert(VM_Version::supports_avx(), ""); 4818 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4819 attributes.set_rex_vex_w_reverted(); 4820 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4821 emit_int8(0x59); 4822 emit_int8((unsigned char)(0xC0 | encode)); 4823 } 4824 4825 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 4826 assert(VM_Version::supports_avx(), ""); 4827 InstructionMark im(this); 4828 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4829 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4830 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4831 emit_int8(0x59); 4832 emit_operand(dst, src); 4833 } 4834 4835 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4836 assert(VM_Version::supports_avx(), ""); 4837 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4838 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4839 emit_int8(0x59); 4840 emit_int8((unsigned char)(0xC0 | encode)); 4841 } 4842 4843 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 4844 assert(VM_Version::supports_avx(), ""); 4845 InstructionMark im(this); 4846 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4847 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4848 attributes.set_rex_vex_w_reverted(); 4849 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4850 emit_int8(0x5C); 4851 emit_operand(dst, src); 4852 } 4853 4854 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4855 assert(VM_Version::supports_avx(), ""); 4856 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4857 attributes.set_rex_vex_w_reverted(); 4858 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4859 emit_int8(0x5C); 4860 emit_int8((unsigned char)(0xC0 | encode)); 4861 } 4862 4863 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 4864 assert(VM_Version::supports_avx(), ""); 4865 InstructionMark im(this); 4866 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4867 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4868 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4869 emit_int8(0x5C); 4870 emit_operand(dst, src); 4871 } 4872 4873 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4874 assert(VM_Version::supports_avx(), ""); 4875 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4876 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4877 emit_int8(0x5C); 4878 emit_int8((unsigned char)(0xC0 | encode)); 4879 } 4880 4881 //====================VECTOR ARITHMETIC===================================== 4882 4883 // Float-point vector arithmetic 4884 4885 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 4886 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4887 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4888 attributes.set_rex_vex_w_reverted(); 4889 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4890 emit_int8(0x58); 4891 emit_int8((unsigned char)(0xC0 | encode)); 4892 } 4893 4894 void Assembler::addpd(XMMRegister dst, Address src) { 4895 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4896 InstructionMark im(this); 4897 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4898 attributes.set_rex_vex_w_reverted(); 4899 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4900 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4901 emit_int8(0x58); 4902 emit_operand(dst, src); 4903 } 4904 4905 4906 void Assembler::addps(XMMRegister dst, XMMRegister src) { 4907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4908 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4909 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4910 emit_int8(0x58); 4911 emit_int8((unsigned char)(0xC0 | encode)); 4912 } 4913 4914 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4915 assert(VM_Version::supports_avx(), ""); 4916 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4917 attributes.set_rex_vex_w_reverted(); 4918 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4919 emit_int8(0x58); 4920 emit_int8((unsigned char)(0xC0 | encode)); 4921 } 4922 4923 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4924 assert(VM_Version::supports_avx(), ""); 4925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4926 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4927 emit_int8(0x58); 4928 emit_int8((unsigned char)(0xC0 | encode)); 4929 } 4930 4931 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4932 assert(VM_Version::supports_avx(), ""); 4933 InstructionMark im(this); 4934 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4935 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4936 attributes.set_rex_vex_w_reverted(); 4937 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4938 emit_int8(0x58); 4939 emit_operand(dst, src); 4940 } 4941 4942 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4943 assert(VM_Version::supports_avx(), ""); 4944 InstructionMark im(this); 4945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4946 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4947 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4948 emit_int8(0x58); 4949 emit_operand(dst, src); 4950 } 4951 4952 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 4953 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4954 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4955 attributes.set_rex_vex_w_reverted(); 4956 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4957 emit_int8(0x5C); 4958 emit_int8((unsigned char)(0xC0 | encode)); 4959 } 4960 4961 void Assembler::subps(XMMRegister dst, XMMRegister src) { 4962 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4963 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4964 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4965 emit_int8(0x5C); 4966 emit_int8((unsigned char)(0xC0 | encode)); 4967 } 4968 4969 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4970 assert(VM_Version::supports_avx(), ""); 4971 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4972 attributes.set_rex_vex_w_reverted(); 4973 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4974 emit_int8(0x5C); 4975 emit_int8((unsigned char)(0xC0 | encode)); 4976 } 4977 4978 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4979 assert(VM_Version::supports_avx(), ""); 4980 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4981 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4982 emit_int8(0x5C); 4983 emit_int8((unsigned char)(0xC0 | encode)); 4984 } 4985 4986 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4987 assert(VM_Version::supports_avx(), ""); 4988 InstructionMark im(this); 4989 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4990 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4991 attributes.set_rex_vex_w_reverted(); 4992 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4993 emit_int8(0x5C); 4994 emit_operand(dst, src); 4995 } 4996 4997 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4998 assert(VM_Version::supports_avx(), ""); 4999 InstructionMark im(this); 5000 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5001 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5002 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5003 emit_int8(0x5C); 5004 emit_operand(dst, src); 5005 } 5006 5007 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 5008 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5009 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5010 attributes.set_rex_vex_w_reverted(); 5011 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5012 emit_int8(0x59); 5013 emit_int8((unsigned char)(0xC0 | encode)); 5014 } 5015 5016 void Assembler::mulpd(XMMRegister dst, Address src) { 5017 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5018 InstructionMark im(this); 5019 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5020 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5021 attributes.set_rex_vex_w_reverted(); 5022 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5023 emit_int8(0x59); 5024 emit_operand(dst, src); 5025 } 5026 5027 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 5028 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5029 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5031 emit_int8(0x59); 5032 emit_int8((unsigned char)(0xC0 | encode)); 5033 } 5034 5035 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5036 assert(VM_Version::supports_avx(), ""); 5037 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5038 attributes.set_rex_vex_w_reverted(); 5039 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5040 emit_int8(0x59); 5041 emit_int8((unsigned char)(0xC0 | encode)); 5042 } 5043 5044 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5045 assert(VM_Version::supports_avx(), ""); 5046 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5047 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5048 emit_int8(0x59); 5049 emit_int8((unsigned char)(0xC0 | encode)); 5050 } 5051 5052 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5053 assert(VM_Version::supports_avx(), ""); 5054 InstructionMark im(this); 5055 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5056 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5057 attributes.set_rex_vex_w_reverted(); 5058 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5059 emit_int8(0x59); 5060 emit_operand(dst, src); 5061 } 5062 5063 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5064 assert(VM_Version::supports_avx(), ""); 5065 InstructionMark im(this); 5066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5067 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5069 emit_int8(0x59); 5070 emit_operand(dst, src); 5071 } 5072 5073 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5074 assert(VM_Version::supports_fma(), ""); 5075 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5076 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5077 emit_int8((unsigned char)0xB8); 5078 emit_int8((unsigned char)(0xC0 | encode)); 5079 } 5080 5081 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5082 assert(VM_Version::supports_fma(), ""); 5083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5084 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5085 emit_int8((unsigned char)0xB8); 5086 emit_int8((unsigned char)(0xC0 | encode)); 5087 } 5088 5089 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5090 assert(VM_Version::supports_fma(), ""); 5091 InstructionMark im(this); 5092 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5093 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5094 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5095 emit_int8((unsigned char)0xB8); 5096 emit_operand(dst, src2); 5097 } 5098 5099 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5100 assert(VM_Version::supports_fma(), ""); 5101 InstructionMark im(this); 5102 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5103 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5104 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5105 emit_int8((unsigned char)0xB8); 5106 emit_operand(dst, src2); 5107 } 5108 5109 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 5110 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5111 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5112 attributes.set_rex_vex_w_reverted(); 5113 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5114 emit_int8(0x5E); 5115 emit_int8((unsigned char)(0xC0 | encode)); 5116 } 5117 5118 void Assembler::divps(XMMRegister dst, XMMRegister src) { 5119 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5121 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5122 emit_int8(0x5E); 5123 emit_int8((unsigned char)(0xC0 | encode)); 5124 } 5125 5126 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5127 assert(VM_Version::supports_avx(), ""); 5128 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5129 attributes.set_rex_vex_w_reverted(); 5130 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5131 emit_int8(0x5E); 5132 emit_int8((unsigned char)(0xC0 | encode)); 5133 } 5134 5135 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5136 assert(VM_Version::supports_avx(), ""); 5137 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5138 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5139 emit_int8(0x5E); 5140 emit_int8((unsigned char)(0xC0 | encode)); 5141 } 5142 5143 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5144 assert(VM_Version::supports_avx(), ""); 5145 InstructionMark im(this); 5146 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5147 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5148 attributes.set_rex_vex_w_reverted(); 5149 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5150 emit_int8(0x5E); 5151 emit_operand(dst, src); 5152 } 5153 5154 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5155 assert(VM_Version::supports_avx(), ""); 5156 InstructionMark im(this); 5157 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5158 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5159 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5160 emit_int8(0x5E); 5161 emit_operand(dst, src); 5162 } 5163 5164 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { 5165 assert(VM_Version::supports_avx(), ""); 5166 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5167 attributes.set_rex_vex_w_reverted(); 5168 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5169 emit_int8(0x51); 5170 emit_int8((unsigned char)(0xC0 | encode)); 5171 } 5172 5173 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { 5174 assert(VM_Version::supports_avx(), ""); 5175 InstructionMark im(this); 5176 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5177 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5178 attributes.set_rex_vex_w_reverted(); 5179 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5180 emit_int8(0x51); 5181 emit_operand(dst, src); 5182 } 5183 5184 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 5185 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5186 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5187 attributes.set_rex_vex_w_reverted(); 5188 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5189 emit_int8(0x54); 5190 emit_int8((unsigned char)(0xC0 | encode)); 5191 } 5192 5193 void Assembler::andps(XMMRegister dst, XMMRegister src) { 5194 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5195 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5196 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5197 emit_int8(0x54); 5198 emit_int8((unsigned char)(0xC0 | encode)); 5199 } 5200 5201 void Assembler::andps(XMMRegister dst, Address src) { 5202 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5203 InstructionMark im(this); 5204 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5205 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5206 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5207 emit_int8(0x54); 5208 emit_operand(dst, src); 5209 } 5210 5211 void Assembler::andpd(XMMRegister dst, Address src) { 5212 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5213 InstructionMark im(this); 5214 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5215 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5216 attributes.set_rex_vex_w_reverted(); 5217 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5218 emit_int8(0x54); 5219 emit_operand(dst, src); 5220 } 5221 5222 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5223 assert(VM_Version::supports_avx(), ""); 5224 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5225 attributes.set_rex_vex_w_reverted(); 5226 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5227 emit_int8(0x54); 5228 emit_int8((unsigned char)(0xC0 | encode)); 5229 } 5230 5231 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5232 assert(VM_Version::supports_avx(), ""); 5233 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5234 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5235 emit_int8(0x54); 5236 emit_int8((unsigned char)(0xC0 | encode)); 5237 } 5238 5239 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5240 assert(VM_Version::supports_avx(), ""); 5241 InstructionMark im(this); 5242 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5243 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5244 attributes.set_rex_vex_w_reverted(); 5245 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5246 emit_int8(0x54); 5247 emit_operand(dst, src); 5248 } 5249 5250 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5251 assert(VM_Version::supports_avx(), ""); 5252 InstructionMark im(this); 5253 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5254 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5255 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5256 emit_int8(0x54); 5257 emit_operand(dst, src); 5258 } 5259 5260 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { 5261 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5262 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5263 attributes.set_rex_vex_w_reverted(); 5264 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5265 emit_int8(0x15); 5266 emit_int8((unsigned char)(0xC0 | encode)); 5267 } 5268 5269 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { 5270 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5271 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5272 attributes.set_rex_vex_w_reverted(); 5273 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5274 emit_int8(0x14); 5275 emit_int8((unsigned char)(0xC0 | encode)); 5276 } 5277 5278 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 5279 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5280 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5281 attributes.set_rex_vex_w_reverted(); 5282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5283 emit_int8(0x57); 5284 emit_int8((unsigned char)(0xC0 | encode)); 5285 } 5286 5287 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 5288 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5291 emit_int8(0x57); 5292 emit_int8((unsigned char)(0xC0 | encode)); 5293 } 5294 5295 void Assembler::xorpd(XMMRegister dst, Address src) { 5296 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5297 InstructionMark im(this); 5298 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5299 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5300 attributes.set_rex_vex_w_reverted(); 5301 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5302 emit_int8(0x57); 5303 emit_operand(dst, src); 5304 } 5305 5306 void Assembler::xorps(XMMRegister dst, Address src) { 5307 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5308 InstructionMark im(this); 5309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5310 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5311 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5312 emit_int8(0x57); 5313 emit_operand(dst, src); 5314 } 5315 5316 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5317 assert(VM_Version::supports_avx(), ""); 5318 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5319 attributes.set_rex_vex_w_reverted(); 5320 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5321 emit_int8(0x57); 5322 emit_int8((unsigned char)(0xC0 | encode)); 5323 } 5324 5325 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5326 assert(VM_Version::supports_avx(), ""); 5327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5328 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5329 emit_int8(0x57); 5330 emit_int8((unsigned char)(0xC0 | encode)); 5331 } 5332 5333 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5334 assert(VM_Version::supports_avx(), ""); 5335 InstructionMark im(this); 5336 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5337 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5338 attributes.set_rex_vex_w_reverted(); 5339 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5340 emit_int8(0x57); 5341 emit_operand(dst, src); 5342 } 5343 5344 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5345 assert(VM_Version::supports_avx(), ""); 5346 InstructionMark im(this); 5347 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5348 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5349 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5350 emit_int8(0x57); 5351 emit_operand(dst, src); 5352 } 5353 5354 // Integer vector arithmetic 5355 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5356 assert(VM_Version::supports_avx() && (vector_len == 0) || 5357 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5360 emit_int8(0x01); 5361 emit_int8((unsigned char)(0xC0 | encode)); 5362 } 5363 5364 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5365 assert(VM_Version::supports_avx() && (vector_len == 0) || 5366 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5367 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5368 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5369 emit_int8(0x02); 5370 emit_int8((unsigned char)(0xC0 | encode)); 5371 } 5372 5373 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 5374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5377 emit_int8((unsigned char)0xFC); 5378 emit_int8((unsigned char)(0xC0 | encode)); 5379 } 5380 5381 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 5382 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5383 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5385 emit_int8((unsigned char)0xFD); 5386 emit_int8((unsigned char)(0xC0 | encode)); 5387 } 5388 5389 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 5390 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5391 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5392 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5393 emit_int8((unsigned char)0xFE); 5394 emit_int8((unsigned char)(0xC0 | encode)); 5395 } 5396 5397 void Assembler::paddd(XMMRegister dst, Address src) { 5398 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5399 InstructionMark im(this); 5400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5401 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5402 emit_int8((unsigned char)0xFE); 5403 emit_operand(dst, src); 5404 } 5405 5406 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 5407 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5408 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5409 attributes.set_rex_vex_w_reverted(); 5410 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5411 emit_int8((unsigned char)0xD4); 5412 emit_int8((unsigned char)(0xC0 | encode)); 5413 } 5414 5415 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 5416 assert(VM_Version::supports_sse3(), ""); 5417 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5418 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5419 emit_int8(0x01); 5420 emit_int8((unsigned char)(0xC0 | encode)); 5421 } 5422 5423 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 5424 assert(VM_Version::supports_sse3(), ""); 5425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5426 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5427 emit_int8(0x02); 5428 emit_int8((unsigned char)(0xC0 | encode)); 5429 } 5430 5431 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5432 assert(UseAVX > 0, "requires some form of AVX"); 5433 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5434 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5435 emit_int8((unsigned char)0xFC); 5436 emit_int8((unsigned char)(0xC0 | encode)); 5437 } 5438 5439 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5440 assert(UseAVX > 0, "requires some form of AVX"); 5441 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5442 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5443 emit_int8((unsigned char)0xFD); 5444 emit_int8((unsigned char)(0xC0 | encode)); 5445 } 5446 5447 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5448 assert(UseAVX > 0, "requires some form of AVX"); 5449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5450 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5451 emit_int8((unsigned char)0xFE); 5452 emit_int8((unsigned char)(0xC0 | encode)); 5453 } 5454 5455 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5456 assert(UseAVX > 0, "requires some form of AVX"); 5457 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5458 attributes.set_rex_vex_w_reverted(); 5459 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5460 emit_int8((unsigned char)0xD4); 5461 emit_int8((unsigned char)(0xC0 | encode)); 5462 } 5463 5464 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5465 assert(UseAVX > 0, "requires some form of AVX"); 5466 InstructionMark im(this); 5467 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5468 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5469 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5470 emit_int8((unsigned char)0xFC); 5471 emit_operand(dst, src); 5472 } 5473 5474 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5475 assert(UseAVX > 0, "requires some form of AVX"); 5476 InstructionMark im(this); 5477 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5478 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5479 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5480 emit_int8((unsigned char)0xFD); 5481 emit_operand(dst, src); 5482 } 5483 5484 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5485 assert(UseAVX > 0, "requires some form of AVX"); 5486 InstructionMark im(this); 5487 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5488 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5489 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5490 emit_int8((unsigned char)0xFE); 5491 emit_operand(dst, src); 5492 } 5493 5494 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5495 assert(UseAVX > 0, "requires some form of AVX"); 5496 InstructionMark im(this); 5497 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5498 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5499 attributes.set_rex_vex_w_reverted(); 5500 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5501 emit_int8((unsigned char)0xD4); 5502 emit_operand(dst, src); 5503 } 5504 5505 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 5506 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5507 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5508 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5509 emit_int8((unsigned char)0xF8); 5510 emit_int8((unsigned char)(0xC0 | encode)); 5511 } 5512 5513 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 5514 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5515 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5516 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5517 emit_int8((unsigned char)0xF9); 5518 emit_int8((unsigned char)(0xC0 | encode)); 5519 } 5520 5521 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 5522 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5523 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5524 emit_int8((unsigned char)0xFA); 5525 emit_int8((unsigned char)(0xC0 | encode)); 5526 } 5527 5528 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 5529 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5530 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5531 attributes.set_rex_vex_w_reverted(); 5532 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5533 emit_int8((unsigned char)0xFB); 5534 emit_int8((unsigned char)(0xC0 | encode)); 5535 } 5536 5537 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5538 assert(UseAVX > 0, "requires some form of AVX"); 5539 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5540 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5541 emit_int8((unsigned char)0xF8); 5542 emit_int8((unsigned char)(0xC0 | encode)); 5543 } 5544 5545 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5546 assert(UseAVX > 0, "requires some form of AVX"); 5547 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5548 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5549 emit_int8((unsigned char)0xF9); 5550 emit_int8((unsigned char)(0xC0 | encode)); 5551 } 5552 5553 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5554 assert(UseAVX > 0, "requires some form of AVX"); 5555 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5557 emit_int8((unsigned char)0xFA); 5558 emit_int8((unsigned char)(0xC0 | encode)); 5559 } 5560 5561 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5562 assert(UseAVX > 0, "requires some form of AVX"); 5563 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5564 attributes.set_rex_vex_w_reverted(); 5565 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5566 emit_int8((unsigned char)0xFB); 5567 emit_int8((unsigned char)(0xC0 | encode)); 5568 } 5569 5570 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5571 assert(UseAVX > 0, "requires some form of AVX"); 5572 InstructionMark im(this); 5573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5575 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5576 emit_int8((unsigned char)0xF8); 5577 emit_operand(dst, src); 5578 } 5579 5580 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5581 assert(UseAVX > 0, "requires some form of AVX"); 5582 InstructionMark im(this); 5583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5585 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5586 emit_int8((unsigned char)0xF9); 5587 emit_operand(dst, src); 5588 } 5589 5590 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5591 assert(UseAVX > 0, "requires some form of AVX"); 5592 InstructionMark im(this); 5593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5594 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5595 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5596 emit_int8((unsigned char)0xFA); 5597 emit_operand(dst, src); 5598 } 5599 5600 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5601 assert(UseAVX > 0, "requires some form of AVX"); 5602 InstructionMark im(this); 5603 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5604 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5605 attributes.set_rex_vex_w_reverted(); 5606 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5607 emit_int8((unsigned char)0xFB); 5608 emit_operand(dst, src); 5609 } 5610 5611 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 5612 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5613 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5614 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5615 emit_int8((unsigned char)0xD5); 5616 emit_int8((unsigned char)(0xC0 | encode)); 5617 } 5618 5619 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 5620 assert(VM_Version::supports_sse4_1(), ""); 5621 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5622 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5623 emit_int8(0x40); 5624 emit_int8((unsigned char)(0xC0 | encode)); 5625 } 5626 5627 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5628 assert(UseAVX > 0, "requires some form of AVX"); 5629 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5630 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5631 emit_int8((unsigned char)0xD5); 5632 emit_int8((unsigned char)(0xC0 | encode)); 5633 } 5634 5635 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5636 assert(UseAVX > 0, "requires some form of AVX"); 5637 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5638 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5639 emit_int8(0x40); 5640 emit_int8((unsigned char)(0xC0 | encode)); 5641 } 5642 5643 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5644 assert(UseAVX > 2, "requires some form of EVEX"); 5645 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5646 attributes.set_is_evex_instruction(); 5647 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5648 emit_int8(0x40); 5649 emit_int8((unsigned char)(0xC0 | encode)); 5650 } 5651 5652 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5653 assert(UseAVX > 0, "requires some form of AVX"); 5654 InstructionMark im(this); 5655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5657 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5658 emit_int8((unsigned char)0xD5); 5659 emit_operand(dst, src); 5660 } 5661 5662 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5663 assert(UseAVX > 0, "requires some form of AVX"); 5664 InstructionMark im(this); 5665 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5666 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5667 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5668 emit_int8(0x40); 5669 emit_operand(dst, src); 5670 } 5671 5672 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5673 assert(UseAVX > 2, "requires some form of EVEX"); 5674 InstructionMark im(this); 5675 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5676 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5677 attributes.set_is_evex_instruction(); 5678 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5679 emit_int8(0x40); 5680 emit_operand(dst, src); 5681 } 5682 5683 // Shift packed integers left by specified number of bits. 5684 void Assembler::psllw(XMMRegister dst, int shift) { 5685 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5687 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5688 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5689 emit_int8(0x71); 5690 emit_int8((unsigned char)(0xC0 | encode)); 5691 emit_int8(shift & 0xFF); 5692 } 5693 5694 void Assembler::pslld(XMMRegister dst, int shift) { 5695 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5697 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5698 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5699 emit_int8(0x72); 5700 emit_int8((unsigned char)(0xC0 | encode)); 5701 emit_int8(shift & 0xFF); 5702 } 5703 5704 void Assembler::psllq(XMMRegister dst, int shift) { 5705 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5706 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5707 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5708 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5709 emit_int8(0x73); 5710 emit_int8((unsigned char)(0xC0 | encode)); 5711 emit_int8(shift & 0xFF); 5712 } 5713 5714 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 5715 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5717 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5718 emit_int8((unsigned char)0xF1); 5719 emit_int8((unsigned char)(0xC0 | encode)); 5720 } 5721 5722 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 5723 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5725 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5726 emit_int8((unsigned char)0xF2); 5727 emit_int8((unsigned char)(0xC0 | encode)); 5728 } 5729 5730 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 5731 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5732 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5733 attributes.set_rex_vex_w_reverted(); 5734 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5735 emit_int8((unsigned char)0xF3); 5736 emit_int8((unsigned char)(0xC0 | encode)); 5737 } 5738 5739 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5740 assert(UseAVX > 0, "requires some form of AVX"); 5741 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5742 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5743 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5744 emit_int8(0x71); 5745 emit_int8((unsigned char)(0xC0 | encode)); 5746 emit_int8(shift & 0xFF); 5747 } 5748 5749 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5750 assert(UseAVX > 0, "requires some form of AVX"); 5751 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5752 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5753 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5754 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5755 emit_int8(0x72); 5756 emit_int8((unsigned char)(0xC0 | encode)); 5757 emit_int8(shift & 0xFF); 5758 } 5759 5760 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5761 assert(UseAVX > 0, "requires some form of AVX"); 5762 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5763 attributes.set_rex_vex_w_reverted(); 5764 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5765 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5766 emit_int8(0x73); 5767 emit_int8((unsigned char)(0xC0 | encode)); 5768 emit_int8(shift & 0xFF); 5769 } 5770 5771 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5772 assert(UseAVX > 0, "requires some form of AVX"); 5773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5774 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5775 emit_int8((unsigned char)0xF1); 5776 emit_int8((unsigned char)(0xC0 | encode)); 5777 } 5778 5779 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5780 assert(UseAVX > 0, "requires some form of AVX"); 5781 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5782 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5783 emit_int8((unsigned char)0xF2); 5784 emit_int8((unsigned char)(0xC0 | encode)); 5785 } 5786 5787 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5788 assert(UseAVX > 0, "requires some form of AVX"); 5789 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5790 attributes.set_rex_vex_w_reverted(); 5791 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5792 emit_int8((unsigned char)0xF3); 5793 emit_int8((unsigned char)(0xC0 | encode)); 5794 } 5795 5796 // Shift packed integers logically right by specified number of bits. 5797 void Assembler::psrlw(XMMRegister dst, int shift) { 5798 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5799 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5800 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5801 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5802 emit_int8(0x71); 5803 emit_int8((unsigned char)(0xC0 | encode)); 5804 emit_int8(shift & 0xFF); 5805 } 5806 5807 void Assembler::psrld(XMMRegister dst, int shift) { 5808 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5809 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5810 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5811 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5812 emit_int8(0x72); 5813 emit_int8((unsigned char)(0xC0 | encode)); 5814 emit_int8(shift & 0xFF); 5815 } 5816 5817 void Assembler::psrlq(XMMRegister dst, int shift) { 5818 // Do not confuse it with psrldq SSE2 instruction which 5819 // shifts 128 bit value in xmm register by number of bytes. 5820 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5821 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5822 attributes.set_rex_vex_w_reverted(); 5823 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5824 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5825 emit_int8(0x73); 5826 emit_int8((unsigned char)(0xC0 | encode)); 5827 emit_int8(shift & 0xFF); 5828 } 5829 5830 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 5831 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5832 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5833 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5834 emit_int8((unsigned char)0xD1); 5835 emit_int8((unsigned char)(0xC0 | encode)); 5836 } 5837 5838 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 5839 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5841 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5842 emit_int8((unsigned char)0xD2); 5843 emit_int8((unsigned char)(0xC0 | encode)); 5844 } 5845 5846 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 5847 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5849 attributes.set_rex_vex_w_reverted(); 5850 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5851 emit_int8((unsigned char)0xD3); 5852 emit_int8((unsigned char)(0xC0 | encode)); 5853 } 5854 5855 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5856 assert(UseAVX > 0, "requires some form of AVX"); 5857 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5858 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5859 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5860 emit_int8(0x71); 5861 emit_int8((unsigned char)(0xC0 | encode)); 5862 emit_int8(shift & 0xFF); 5863 } 5864 5865 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5866 assert(UseAVX > 0, "requires some form of AVX"); 5867 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5868 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5869 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5870 emit_int8(0x72); 5871 emit_int8((unsigned char)(0xC0 | encode)); 5872 emit_int8(shift & 0xFF); 5873 } 5874 5875 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5876 assert(UseAVX > 0, "requires some form of AVX"); 5877 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5878 attributes.set_rex_vex_w_reverted(); 5879 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5880 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5881 emit_int8(0x73); 5882 emit_int8((unsigned char)(0xC0 | encode)); 5883 emit_int8(shift & 0xFF); 5884 } 5885 5886 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5887 assert(UseAVX > 0, "requires some form of AVX"); 5888 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5889 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5890 emit_int8((unsigned char)0xD1); 5891 emit_int8((unsigned char)(0xC0 | encode)); 5892 } 5893 5894 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5895 assert(UseAVX > 0, "requires some form of AVX"); 5896 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5897 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5898 emit_int8((unsigned char)0xD2); 5899 emit_int8((unsigned char)(0xC0 | encode)); 5900 } 5901 5902 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5903 assert(UseAVX > 0, "requires some form of AVX"); 5904 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5905 attributes.set_rex_vex_w_reverted(); 5906 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5907 emit_int8((unsigned char)0xD3); 5908 emit_int8((unsigned char)(0xC0 | encode)); 5909 } 5910 5911 // Shift packed integers arithmetically right by specified number of bits. 5912 void Assembler::psraw(XMMRegister dst, int shift) { 5913 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5915 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5916 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5917 emit_int8(0x71); 5918 emit_int8((unsigned char)(0xC0 | encode)); 5919 emit_int8(shift & 0xFF); 5920 } 5921 5922 void Assembler::psrad(XMMRegister dst, int shift) { 5923 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5924 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5925 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 5926 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5927 emit_int8(0x72); 5928 emit_int8((unsigned char)(0xC0 | encode)); 5929 emit_int8(shift & 0xFF); 5930 } 5931 5932 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 5933 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5934 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5935 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5936 emit_int8((unsigned char)0xE1); 5937 emit_int8((unsigned char)(0xC0 | encode)); 5938 } 5939 5940 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 5941 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5943 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5944 emit_int8((unsigned char)0xE2); 5945 emit_int8((unsigned char)(0xC0 | encode)); 5946 } 5947 5948 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5949 assert(UseAVX > 0, "requires some form of AVX"); 5950 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5951 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5952 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5953 emit_int8(0x71); 5954 emit_int8((unsigned char)(0xC0 | encode)); 5955 emit_int8(shift & 0xFF); 5956 } 5957 5958 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5959 assert(UseAVX > 0, "requires some form of AVX"); 5960 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5961 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5962 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5963 emit_int8(0x72); 5964 emit_int8((unsigned char)(0xC0 | encode)); 5965 emit_int8(shift & 0xFF); 5966 } 5967 5968 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5969 assert(UseAVX > 0, "requires some form of AVX"); 5970 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5971 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5972 emit_int8((unsigned char)0xE1); 5973 emit_int8((unsigned char)(0xC0 | encode)); 5974 } 5975 5976 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5977 assert(UseAVX > 0, "requires some form of AVX"); 5978 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5979 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5980 emit_int8((unsigned char)0xE2); 5981 emit_int8((unsigned char)(0xC0 | encode)); 5982 } 5983 5984 5985 // logical operations packed integers 5986 void Assembler::pand(XMMRegister dst, XMMRegister src) { 5987 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5988 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5989 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5990 emit_int8((unsigned char)0xDB); 5991 emit_int8((unsigned char)(0xC0 | encode)); 5992 } 5993 5994 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5995 assert(UseAVX > 0, "requires some form of AVX"); 5996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5997 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5998 emit_int8((unsigned char)0xDB); 5999 emit_int8((unsigned char)(0xC0 | encode)); 6000 } 6001 6002 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6003 assert(UseAVX > 0, "requires some form of AVX"); 6004 InstructionMark im(this); 6005 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6006 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6007 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6008 emit_int8((unsigned char)0xDB); 6009 emit_operand(dst, src); 6010 } 6011 6012 void Assembler::pandn(XMMRegister dst, XMMRegister src) { 6013 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6014 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6015 attributes.set_rex_vex_w_reverted(); 6016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6017 emit_int8((unsigned char)0xDF); 6018 emit_int8((unsigned char)(0xC0 | encode)); 6019 } 6020 6021 void Assembler::por(XMMRegister dst, XMMRegister src) { 6022 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6023 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6024 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6025 emit_int8((unsigned char)0xEB); 6026 emit_int8((unsigned char)(0xC0 | encode)); 6027 } 6028 6029 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6030 assert(UseAVX > 0, "requires some form of AVX"); 6031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6032 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6033 emit_int8((unsigned char)0xEB); 6034 emit_int8((unsigned char)(0xC0 | encode)); 6035 } 6036 6037 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6038 assert(UseAVX > 0, "requires some form of AVX"); 6039 InstructionMark im(this); 6040 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6041 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6042 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6043 emit_int8((unsigned char)0xEB); 6044 emit_operand(dst, src); 6045 } 6046 6047 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 6048 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6050 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6051 emit_int8((unsigned char)0xEF); 6052 emit_int8((unsigned char)(0xC0 | encode)); 6053 } 6054 6055 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6056 assert(UseAVX > 0, "requires some form of AVX"); 6057 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6058 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6059 emit_int8((unsigned char)0xEF); 6060 emit_int8((unsigned char)(0xC0 | encode)); 6061 } 6062 6063 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6064 assert(UseAVX > 0, "requires some form of AVX"); 6065 InstructionMark im(this); 6066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6067 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6069 emit_int8((unsigned char)0xEF); 6070 emit_operand(dst, src); 6071 } 6072 6073 6074 // vinserti forms 6075 6076 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6077 assert(VM_Version::supports_avx2(), ""); 6078 assert(imm8 <= 0x01, "imm8: %u", imm8); 6079 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6080 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6081 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6082 emit_int8(0x38); 6083 emit_int8((unsigned char)(0xC0 | encode)); 6084 // 0x00 - insert into lower 128 bits 6085 // 0x01 - insert into upper 128 bits 6086 emit_int8(imm8 & 0x01); 6087 } 6088 6089 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6090 assert(VM_Version::supports_avx2(), ""); 6091 assert(dst != xnoreg, "sanity"); 6092 assert(imm8 <= 0x01, "imm8: %u", imm8); 6093 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6094 InstructionMark im(this); 6095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6096 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6097 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6098 emit_int8(0x38); 6099 emit_operand(dst, src); 6100 // 0x00 - insert into lower 128 bits 6101 // 0x01 - insert into upper 128 bits 6102 emit_int8(imm8 & 0x01); 6103 } 6104 6105 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6106 assert(VM_Version::supports_evex(), ""); 6107 assert(imm8 <= 0x03, "imm8: %u", imm8); 6108 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6109 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6110 emit_int8(0x38); 6111 emit_int8((unsigned char)(0xC0 | encode)); 6112 // 0x00 - insert into q0 128 bits (0..127) 6113 // 0x01 - insert into q1 128 bits (128..255) 6114 // 0x02 - insert into q2 128 bits (256..383) 6115 // 0x03 - insert into q3 128 bits (384..511) 6116 emit_int8(imm8 & 0x03); 6117 } 6118 6119 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6120 assert(VM_Version::supports_avx(), ""); 6121 assert(dst != xnoreg, "sanity"); 6122 assert(imm8 <= 0x03, "imm8: %u", imm8); 6123 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6124 InstructionMark im(this); 6125 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6126 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6127 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6128 emit_int8(0x18); 6129 emit_operand(dst, src); 6130 // 0x00 - insert into q0 128 bits (0..127) 6131 // 0x01 - insert into q1 128 bits (128..255) 6132 // 0x02 - insert into q2 128 bits (256..383) 6133 // 0x03 - insert into q3 128 bits (384..511) 6134 emit_int8(imm8 & 0x03); 6135 } 6136 6137 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6138 assert(VM_Version::supports_evex(), ""); 6139 assert(imm8 <= 0x01, "imm8: %u", imm8); 6140 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6141 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6142 emit_int8(0x38); 6143 emit_int8((unsigned char)(0xC0 | encode)); 6144 // 0x00 - insert into lower 256 bits 6145 // 0x01 - insert into upper 256 bits 6146 emit_int8(imm8 & 0x01); 6147 } 6148 6149 6150 // vinsertf forms 6151 6152 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6153 assert(VM_Version::supports_avx(), ""); 6154 assert(imm8 <= 0x01, "imm8: %u", imm8); 6155 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6156 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6157 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6158 emit_int8(0x18); 6159 emit_int8((unsigned char)(0xC0 | encode)); 6160 // 0x00 - insert into lower 128 bits 6161 // 0x01 - insert into upper 128 bits 6162 emit_int8(imm8 & 0x01); 6163 } 6164 6165 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6166 assert(VM_Version::supports_avx(), ""); 6167 assert(dst != xnoreg, "sanity"); 6168 assert(imm8 <= 0x01, "imm8: %u", imm8); 6169 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6170 InstructionMark im(this); 6171 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6172 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6173 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6174 emit_int8(0x18); 6175 emit_operand(dst, src); 6176 // 0x00 - insert into lower 128 bits 6177 // 0x01 - insert into upper 128 bits 6178 emit_int8(imm8 & 0x01); 6179 } 6180 6181 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6182 assert(VM_Version::supports_evex(), ""); 6183 assert(imm8 <= 0x03, "imm8: %u", imm8); 6184 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6185 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6186 emit_int8(0x18); 6187 emit_int8((unsigned char)(0xC0 | encode)); 6188 // 0x00 - insert into q0 128 bits (0..127) 6189 // 0x01 - insert into q1 128 bits (128..255) 6190 // 0x02 - insert into q2 128 bits (256..383) 6191 // 0x03 - insert into q3 128 bits (384..511) 6192 emit_int8(imm8 & 0x03); 6193 } 6194 6195 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6196 assert(VM_Version::supports_avx(), ""); 6197 assert(dst != xnoreg, "sanity"); 6198 assert(imm8 <= 0x03, "imm8: %u", imm8); 6199 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6200 InstructionMark im(this); 6201 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6202 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6203 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6204 emit_int8(0x18); 6205 emit_operand(dst, src); 6206 // 0x00 - insert into q0 128 bits (0..127) 6207 // 0x01 - insert into q1 128 bits (128..255) 6208 // 0x02 - insert into q2 128 bits (256..383) 6209 // 0x03 - insert into q3 128 bits (384..511) 6210 emit_int8(imm8 & 0x03); 6211 } 6212 6213 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6214 assert(VM_Version::supports_evex(), ""); 6215 assert(imm8 <= 0x01, "imm8: %u", imm8); 6216 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6217 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6218 emit_int8(0x1A); 6219 emit_int8((unsigned char)(0xC0 | encode)); 6220 // 0x00 - insert into lower 256 bits 6221 // 0x01 - insert into upper 256 bits 6222 emit_int8(imm8 & 0x01); 6223 } 6224 6225 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6226 assert(VM_Version::supports_evex(), ""); 6227 assert(dst != xnoreg, "sanity"); 6228 assert(imm8 <= 0x01, "imm8: %u", imm8); 6229 InstructionMark im(this); 6230 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6231 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6232 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6233 emit_int8(0x1A); 6234 emit_operand(dst, src); 6235 // 0x00 - insert into lower 256 bits 6236 // 0x01 - insert into upper 256 bits 6237 emit_int8(imm8 & 0x01); 6238 } 6239 6240 6241 // vextracti forms 6242 6243 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6244 assert(VM_Version::supports_avx(), ""); 6245 assert(imm8 <= 0x01, "imm8: %u", imm8); 6246 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6247 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6248 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6249 emit_int8(0x39); 6250 emit_int8((unsigned char)(0xC0 | encode)); 6251 // 0x00 - extract from lower 128 bits 6252 // 0x01 - extract from upper 128 bits 6253 emit_int8(imm8 & 0x01); 6254 } 6255 6256 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 6257 assert(VM_Version::supports_avx2(), ""); 6258 assert(src != xnoreg, "sanity"); 6259 assert(imm8 <= 0x01, "imm8: %u", imm8); 6260 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6261 InstructionMark im(this); 6262 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6263 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6264 attributes.reset_is_clear_context(); 6265 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6266 emit_int8(0x39); 6267 emit_operand(src, dst); 6268 // 0x00 - extract from lower 128 bits 6269 // 0x01 - extract from upper 128 bits 6270 emit_int8(imm8 & 0x01); 6271 } 6272 6273 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6274 assert(VM_Version::supports_avx(), ""); 6275 assert(imm8 <= 0x03, "imm8: %u", imm8); 6276 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6277 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6278 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6279 emit_int8(0x39); 6280 emit_int8((unsigned char)(0xC0 | encode)); 6281 // 0x00 - extract from bits 127:0 6282 // 0x01 - extract from bits 255:128 6283 // 0x02 - extract from bits 383:256 6284 // 0x03 - extract from bits 511:384 6285 emit_int8(imm8 & 0x03); 6286 } 6287 6288 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { 6289 assert(VM_Version::supports_evex(), ""); 6290 assert(src != xnoreg, "sanity"); 6291 assert(imm8 <= 0x03, "imm8: %u", imm8); 6292 InstructionMark im(this); 6293 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6294 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6295 attributes.reset_is_clear_context(); 6296 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6297 emit_int8(0x39); 6298 emit_operand(src, dst); 6299 // 0x00 - extract from bits 127:0 6300 // 0x01 - extract from bits 255:128 6301 // 0x02 - extract from bits 383:256 6302 // 0x03 - extract from bits 511:384 6303 emit_int8(imm8 & 0x03); 6304 } 6305 6306 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6307 assert(VM_Version::supports_avx512dq(), ""); 6308 assert(imm8 <= 0x03, "imm8: %u", imm8); 6309 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6310 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6311 emit_int8(0x39); 6312 emit_int8((unsigned char)(0xC0 | encode)); 6313 // 0x00 - extract from bits 127:0 6314 // 0x01 - extract from bits 255:128 6315 // 0x02 - extract from bits 383:256 6316 // 0x03 - extract from bits 511:384 6317 emit_int8(imm8 & 0x03); 6318 } 6319 6320 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6321 assert(VM_Version::supports_evex(), ""); 6322 assert(imm8 <= 0x01, "imm8: %u", imm8); 6323 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6324 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6325 emit_int8(0x3B); 6326 emit_int8((unsigned char)(0xC0 | encode)); 6327 // 0x00 - extract from lower 256 bits 6328 // 0x01 - extract from upper 256 bits 6329 emit_int8(imm8 & 0x01); 6330 } 6331 6332 6333 // vextractf forms 6334 6335 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6336 assert(VM_Version::supports_avx(), ""); 6337 assert(imm8 <= 0x01, "imm8: %u", imm8); 6338 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6339 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6340 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6341 emit_int8(0x19); 6342 emit_int8((unsigned char)(0xC0 | encode)); 6343 // 0x00 - extract from lower 128 bits 6344 // 0x01 - extract from upper 128 bits 6345 emit_int8(imm8 & 0x01); 6346 } 6347 6348 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { 6349 assert(VM_Version::supports_avx(), ""); 6350 assert(src != xnoreg, "sanity"); 6351 assert(imm8 <= 0x01, "imm8: %u", imm8); 6352 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6353 InstructionMark im(this); 6354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6355 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6356 attributes.reset_is_clear_context(); 6357 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6358 emit_int8(0x19); 6359 emit_operand(src, dst); 6360 // 0x00 - extract from lower 128 bits 6361 // 0x01 - extract from upper 128 bits 6362 emit_int8(imm8 & 0x01); 6363 } 6364 6365 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6366 assert(VM_Version::supports_avx(), ""); 6367 assert(imm8 <= 0x03, "imm8: %u", imm8); 6368 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6369 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6370 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6371 emit_int8(0x19); 6372 emit_int8((unsigned char)(0xC0 | encode)); 6373 // 0x00 - extract from bits 127:0 6374 // 0x01 - extract from bits 255:128 6375 // 0x02 - extract from bits 383:256 6376 // 0x03 - extract from bits 511:384 6377 emit_int8(imm8 & 0x03); 6378 } 6379 6380 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { 6381 assert(VM_Version::supports_evex(), ""); 6382 assert(src != xnoreg, "sanity"); 6383 assert(imm8 <= 0x03, "imm8: %u", imm8); 6384 InstructionMark im(this); 6385 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6386 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6387 attributes.reset_is_clear_context(); 6388 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6389 emit_int8(0x19); 6390 emit_operand(src, dst); 6391 // 0x00 - extract from bits 127:0 6392 // 0x01 - extract from bits 255:128 6393 // 0x02 - extract from bits 383:256 6394 // 0x03 - extract from bits 511:384 6395 emit_int8(imm8 & 0x03); 6396 } 6397 6398 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6399 assert(VM_Version::supports_avx512dq(), ""); 6400 assert(imm8 <= 0x03, "imm8: %u", imm8); 6401 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6402 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6403 emit_int8(0x19); 6404 emit_int8((unsigned char)(0xC0 | encode)); 6405 // 0x00 - extract from bits 127:0 6406 // 0x01 - extract from bits 255:128 6407 // 0x02 - extract from bits 383:256 6408 // 0x03 - extract from bits 511:384 6409 emit_int8(imm8 & 0x03); 6410 } 6411 6412 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6413 assert(VM_Version::supports_evex(), ""); 6414 assert(imm8 <= 0x01, "imm8: %u", imm8); 6415 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6416 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6417 emit_int8(0x1B); 6418 emit_int8((unsigned char)(0xC0 | encode)); 6419 // 0x00 - extract from lower 256 bits 6420 // 0x01 - extract from upper 256 bits 6421 emit_int8(imm8 & 0x01); 6422 } 6423 6424 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { 6425 assert(VM_Version::supports_evex(), ""); 6426 assert(src != xnoreg, "sanity"); 6427 assert(imm8 <= 0x01, "imm8: %u", imm8); 6428 InstructionMark im(this); 6429 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6430 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); 6431 attributes.reset_is_clear_context(); 6432 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6433 emit_int8(0x1B); 6434 emit_operand(src, dst); 6435 // 0x00 - extract from lower 256 bits 6436 // 0x01 - extract from upper 256 bits 6437 emit_int8(imm8 & 0x01); 6438 } 6439 6440 6441 // legacy word/dword replicate 6442 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 6443 assert(VM_Version::supports_avx2(), ""); 6444 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6445 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6446 emit_int8(0x79); 6447 emit_int8((unsigned char)(0xC0 | encode)); 6448 } 6449 6450 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { 6451 assert(VM_Version::supports_avx2(), ""); 6452 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6453 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6454 emit_int8(0x58); 6455 emit_int8((unsigned char)(0xC0 | encode)); 6456 } 6457 6458 6459 // xmm/mem sourced byte/word/dword/qword replicate 6460 6461 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6462 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { 6463 assert(VM_Version::supports_evex(), ""); 6464 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6465 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6466 emit_int8(0x78); 6467 emit_int8((unsigned char)(0xC0 | encode)); 6468 } 6469 6470 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) { 6471 assert(VM_Version::supports_evex(), ""); 6472 assert(dst != xnoreg, "sanity"); 6473 InstructionMark im(this); 6474 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6475 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 6476 // swap src<->dst for encoding 6477 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6478 emit_int8(0x78); 6479 emit_operand(dst, src); 6480 } 6481 6482 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6483 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 6484 assert(VM_Version::supports_evex(), ""); 6485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6486 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6487 emit_int8(0x79); 6488 emit_int8((unsigned char)(0xC0 | encode)); 6489 } 6490 6491 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) { 6492 assert(VM_Version::supports_evex(), ""); 6493 assert(dst != xnoreg, "sanity"); 6494 InstructionMark im(this); 6495 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6496 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 6497 // swap src<->dst for encoding 6498 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6499 emit_int8(0x79); 6500 emit_operand(dst, src); 6501 } 6502 6503 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6504 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 6505 assert(VM_Version::supports_evex(), ""); 6506 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6507 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6508 emit_int8(0x58); 6509 emit_int8((unsigned char)(0xC0 | encode)); 6510 } 6511 6512 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) { 6513 assert(VM_Version::supports_evex(), ""); 6514 assert(dst != xnoreg, "sanity"); 6515 InstructionMark im(this); 6516 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6517 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6518 // swap src<->dst for encoding 6519 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6520 emit_int8(0x58); 6521 emit_operand(dst, src); 6522 } 6523 6524 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6525 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { 6526 assert(VM_Version::supports_evex(), ""); 6527 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6528 attributes.set_rex_vex_w_reverted(); 6529 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6530 emit_int8(0x59); 6531 emit_int8((unsigned char)(0xC0 | encode)); 6532 } 6533 6534 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) { 6535 assert(VM_Version::supports_evex(), ""); 6536 assert(dst != xnoreg, "sanity"); 6537 InstructionMark im(this); 6538 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6539 attributes.set_rex_vex_w_reverted(); 6540 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6541 // swap src<->dst for encoding 6542 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6543 emit_int8(0x59); 6544 emit_operand(dst, src); 6545 } 6546 6547 6548 // scalar single/double precision replicate 6549 6550 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL 6551 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { 6552 assert(VM_Version::supports_evex(), ""); 6553 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6554 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6555 emit_int8(0x18); 6556 emit_int8((unsigned char)(0xC0 | encode)); 6557 } 6558 6559 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) { 6560 assert(VM_Version::supports_evex(), ""); 6561 assert(dst != xnoreg, "sanity"); 6562 InstructionMark im(this); 6563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6564 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6565 // swap src<->dst for encoding 6566 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6567 emit_int8(0x18); 6568 emit_operand(dst, src); 6569 } 6570 6571 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL 6572 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { 6573 assert(VM_Version::supports_evex(), ""); 6574 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6575 attributes.set_rex_vex_w_reverted(); 6576 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6577 emit_int8(0x19); 6578 emit_int8((unsigned char)(0xC0 | encode)); 6579 } 6580 6581 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) { 6582 assert(VM_Version::supports_evex(), ""); 6583 assert(dst != xnoreg, "sanity"); 6584 InstructionMark im(this); 6585 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6586 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6587 attributes.set_rex_vex_w_reverted(); 6588 // swap src<->dst for encoding 6589 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6590 emit_int8(0x19); 6591 emit_operand(dst, src); 6592 } 6593 6594 6595 // gpr source broadcast forms 6596 6597 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6598 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { 6599 assert(VM_Version::supports_evex(), ""); 6600 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6601 attributes.set_is_evex_instruction(); 6602 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6603 emit_int8(0x7A); 6604 emit_int8((unsigned char)(0xC0 | encode)); 6605 } 6606 6607 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6608 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { 6609 assert(VM_Version::supports_evex(), ""); 6610 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6611 attributes.set_is_evex_instruction(); 6612 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6613 emit_int8(0x7B); 6614 emit_int8((unsigned char)(0xC0 | encode)); 6615 } 6616 6617 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6618 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { 6619 assert(VM_Version::supports_evex(), ""); 6620 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6621 attributes.set_is_evex_instruction(); 6622 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6623 emit_int8(0x7C); 6624 emit_int8((unsigned char)(0xC0 | encode)); 6625 } 6626 6627 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6628 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { 6629 assert(VM_Version::supports_evex(), ""); 6630 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6631 attributes.set_is_evex_instruction(); 6632 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6633 emit_int8(0x7C); 6634 emit_int8((unsigned char)(0xC0 | encode)); 6635 } 6636 6637 6638 // Carry-Less Multiplication Quadword 6639 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 6640 assert(VM_Version::supports_clmul(), ""); 6641 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6642 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6643 emit_int8(0x44); 6644 emit_int8((unsigned char)(0xC0 | encode)); 6645 emit_int8((unsigned char)mask); 6646 } 6647 6648 // Carry-Less Multiplication Quadword 6649 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 6650 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 6651 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6652 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6653 emit_int8(0x44); 6654 emit_int8((unsigned char)(0xC0 | encode)); 6655 emit_int8((unsigned char)mask); 6656 } 6657 6658 void Assembler::vzeroupper() { 6659 assert(VM_Version::supports_avx(), ""); 6660 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6661 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 6662 emit_int8(0x77); 6663 } 6664 6665 #ifndef _LP64 6666 // 32bit only pieces of the assembler 6667 6668 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 6669 // NO PREFIX AS NEVER 64BIT 6670 InstructionMark im(this); 6671 emit_int8((unsigned char)0x81); 6672 emit_int8((unsigned char)(0xF8 | src1->encoding())); 6673 emit_data(imm32, rspec, 0); 6674 } 6675 6676 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 6677 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 6678 InstructionMark im(this); 6679 emit_int8((unsigned char)0x81); 6680 emit_operand(rdi, src1); 6681 emit_data(imm32, rspec, 0); 6682 } 6683 6684 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 6685 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 6686 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 6687 void Assembler::cmpxchg8(Address adr) { 6688 InstructionMark im(this); 6689 emit_int8(0x0F); 6690 emit_int8((unsigned char)0xC7); 6691 emit_operand(rcx, adr); 6692 } 6693 6694 void Assembler::decl(Register dst) { 6695 // Don't use it directly. Use MacroAssembler::decrementl() instead. 6696 emit_int8(0x48 | dst->encoding()); 6697 } 6698 6699 #endif // _LP64 6700 6701 // 64bit typically doesn't use the x87 but needs to for the trig funcs 6702 6703 void Assembler::fabs() { 6704 emit_int8((unsigned char)0xD9); 6705 emit_int8((unsigned char)0xE1); 6706 } 6707 6708 void Assembler::fadd(int i) { 6709 emit_farith(0xD8, 0xC0, i); 6710 } 6711 6712 void Assembler::fadd_d(Address src) { 6713 InstructionMark im(this); 6714 emit_int8((unsigned char)0xDC); 6715 emit_operand32(rax, src); 6716 } 6717 6718 void Assembler::fadd_s(Address src) { 6719 InstructionMark im(this); 6720 emit_int8((unsigned char)0xD8); 6721 emit_operand32(rax, src); 6722 } 6723 6724 void Assembler::fadda(int i) { 6725 emit_farith(0xDC, 0xC0, i); 6726 } 6727 6728 void Assembler::faddp(int i) { 6729 emit_farith(0xDE, 0xC0, i); 6730 } 6731 6732 void Assembler::fchs() { 6733 emit_int8((unsigned char)0xD9); 6734 emit_int8((unsigned char)0xE0); 6735 } 6736 6737 void Assembler::fcom(int i) { 6738 emit_farith(0xD8, 0xD0, i); 6739 } 6740 6741 void Assembler::fcomp(int i) { 6742 emit_farith(0xD8, 0xD8, i); 6743 } 6744 6745 void Assembler::fcomp_d(Address src) { 6746 InstructionMark im(this); 6747 emit_int8((unsigned char)0xDC); 6748 emit_operand32(rbx, src); 6749 } 6750 6751 void Assembler::fcomp_s(Address src) { 6752 InstructionMark im(this); 6753 emit_int8((unsigned char)0xD8); 6754 emit_operand32(rbx, src); 6755 } 6756 6757 void Assembler::fcompp() { 6758 emit_int8((unsigned char)0xDE); 6759 emit_int8((unsigned char)0xD9); 6760 } 6761 6762 void Assembler::fcos() { 6763 emit_int8((unsigned char)0xD9); 6764 emit_int8((unsigned char)0xFF); 6765 } 6766 6767 void Assembler::fdecstp() { 6768 emit_int8((unsigned char)0xD9); 6769 emit_int8((unsigned char)0xF6); 6770 } 6771 6772 void Assembler::fdiv(int i) { 6773 emit_farith(0xD8, 0xF0, i); 6774 } 6775 6776 void Assembler::fdiv_d(Address src) { 6777 InstructionMark im(this); 6778 emit_int8((unsigned char)0xDC); 6779 emit_operand32(rsi, src); 6780 } 6781 6782 void Assembler::fdiv_s(Address src) { 6783 InstructionMark im(this); 6784 emit_int8((unsigned char)0xD8); 6785 emit_operand32(rsi, src); 6786 } 6787 6788 void Assembler::fdiva(int i) { 6789 emit_farith(0xDC, 0xF8, i); 6790 } 6791 6792 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 6793 // is erroneous for some of the floating-point instructions below. 6794 6795 void Assembler::fdivp(int i) { 6796 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 6797 } 6798 6799 void Assembler::fdivr(int i) { 6800 emit_farith(0xD8, 0xF8, i); 6801 } 6802 6803 void Assembler::fdivr_d(Address src) { 6804 InstructionMark im(this); 6805 emit_int8((unsigned char)0xDC); 6806 emit_operand32(rdi, src); 6807 } 6808 6809 void Assembler::fdivr_s(Address src) { 6810 InstructionMark im(this); 6811 emit_int8((unsigned char)0xD8); 6812 emit_operand32(rdi, src); 6813 } 6814 6815 void Assembler::fdivra(int i) { 6816 emit_farith(0xDC, 0xF0, i); 6817 } 6818 6819 void Assembler::fdivrp(int i) { 6820 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 6821 } 6822 6823 void Assembler::ffree(int i) { 6824 emit_farith(0xDD, 0xC0, i); 6825 } 6826 6827 void Assembler::fild_d(Address adr) { 6828 InstructionMark im(this); 6829 emit_int8((unsigned char)0xDF); 6830 emit_operand32(rbp, adr); 6831 } 6832 6833 void Assembler::fild_s(Address adr) { 6834 InstructionMark im(this); 6835 emit_int8((unsigned char)0xDB); 6836 emit_operand32(rax, adr); 6837 } 6838 6839 void Assembler::fincstp() { 6840 emit_int8((unsigned char)0xD9); 6841 emit_int8((unsigned char)0xF7); 6842 } 6843 6844 void Assembler::finit() { 6845 emit_int8((unsigned char)0x9B); 6846 emit_int8((unsigned char)0xDB); 6847 emit_int8((unsigned char)0xE3); 6848 } 6849 6850 void Assembler::fist_s(Address adr) { 6851 InstructionMark im(this); 6852 emit_int8((unsigned char)0xDB); 6853 emit_operand32(rdx, adr); 6854 } 6855 6856 void Assembler::fistp_d(Address adr) { 6857 InstructionMark im(this); 6858 emit_int8((unsigned char)0xDF); 6859 emit_operand32(rdi, adr); 6860 } 6861 6862 void Assembler::fistp_s(Address adr) { 6863 InstructionMark im(this); 6864 emit_int8((unsigned char)0xDB); 6865 emit_operand32(rbx, adr); 6866 } 6867 6868 void Assembler::fld1() { 6869 emit_int8((unsigned char)0xD9); 6870 emit_int8((unsigned char)0xE8); 6871 } 6872 6873 void Assembler::fld_d(Address adr) { 6874 InstructionMark im(this); 6875 emit_int8((unsigned char)0xDD); 6876 emit_operand32(rax, adr); 6877 } 6878 6879 void Assembler::fld_s(Address adr) { 6880 InstructionMark im(this); 6881 emit_int8((unsigned char)0xD9); 6882 emit_operand32(rax, adr); 6883 } 6884 6885 6886 void Assembler::fld_s(int index) { 6887 emit_farith(0xD9, 0xC0, index); 6888 } 6889 6890 void Assembler::fld_x(Address adr) { 6891 InstructionMark im(this); 6892 emit_int8((unsigned char)0xDB); 6893 emit_operand32(rbp, adr); 6894 } 6895 6896 void Assembler::fldcw(Address src) { 6897 InstructionMark im(this); 6898 emit_int8((unsigned char)0xD9); 6899 emit_operand32(rbp, src); 6900 } 6901 6902 void Assembler::fldenv(Address src) { 6903 InstructionMark im(this); 6904 emit_int8((unsigned char)0xD9); 6905 emit_operand32(rsp, src); 6906 } 6907 6908 void Assembler::fldlg2() { 6909 emit_int8((unsigned char)0xD9); 6910 emit_int8((unsigned char)0xEC); 6911 } 6912 6913 void Assembler::fldln2() { 6914 emit_int8((unsigned char)0xD9); 6915 emit_int8((unsigned char)0xED); 6916 } 6917 6918 void Assembler::fldz() { 6919 emit_int8((unsigned char)0xD9); 6920 emit_int8((unsigned char)0xEE); 6921 } 6922 6923 void Assembler::flog() { 6924 fldln2(); 6925 fxch(); 6926 fyl2x(); 6927 } 6928 6929 void Assembler::flog10() { 6930 fldlg2(); 6931 fxch(); 6932 fyl2x(); 6933 } 6934 6935 void Assembler::fmul(int i) { 6936 emit_farith(0xD8, 0xC8, i); 6937 } 6938 6939 void Assembler::fmul_d(Address src) { 6940 InstructionMark im(this); 6941 emit_int8((unsigned char)0xDC); 6942 emit_operand32(rcx, src); 6943 } 6944 6945 void Assembler::fmul_s(Address src) { 6946 InstructionMark im(this); 6947 emit_int8((unsigned char)0xD8); 6948 emit_operand32(rcx, src); 6949 } 6950 6951 void Assembler::fmula(int i) { 6952 emit_farith(0xDC, 0xC8, i); 6953 } 6954 6955 void Assembler::fmulp(int i) { 6956 emit_farith(0xDE, 0xC8, i); 6957 } 6958 6959 void Assembler::fnsave(Address dst) { 6960 InstructionMark im(this); 6961 emit_int8((unsigned char)0xDD); 6962 emit_operand32(rsi, dst); 6963 } 6964 6965 void Assembler::fnstcw(Address src) { 6966 InstructionMark im(this); 6967 emit_int8((unsigned char)0x9B); 6968 emit_int8((unsigned char)0xD9); 6969 emit_operand32(rdi, src); 6970 } 6971 6972 void Assembler::fnstsw_ax() { 6973 emit_int8((unsigned char)0xDF); 6974 emit_int8((unsigned char)0xE0); 6975 } 6976 6977 void Assembler::fprem() { 6978 emit_int8((unsigned char)0xD9); 6979 emit_int8((unsigned char)0xF8); 6980 } 6981 6982 void Assembler::fprem1() { 6983 emit_int8((unsigned char)0xD9); 6984 emit_int8((unsigned char)0xF5); 6985 } 6986 6987 void Assembler::frstor(Address src) { 6988 InstructionMark im(this); 6989 emit_int8((unsigned char)0xDD); 6990 emit_operand32(rsp, src); 6991 } 6992 6993 void Assembler::fsin() { 6994 emit_int8((unsigned char)0xD9); 6995 emit_int8((unsigned char)0xFE); 6996 } 6997 6998 void Assembler::fsqrt() { 6999 emit_int8((unsigned char)0xD9); 7000 emit_int8((unsigned char)0xFA); 7001 } 7002 7003 void Assembler::fst_d(Address adr) { 7004 InstructionMark im(this); 7005 emit_int8((unsigned char)0xDD); 7006 emit_operand32(rdx, adr); 7007 } 7008 7009 void Assembler::fst_s(Address adr) { 7010 InstructionMark im(this); 7011 emit_int8((unsigned char)0xD9); 7012 emit_operand32(rdx, adr); 7013 } 7014 7015 void Assembler::fstp_d(Address adr) { 7016 InstructionMark im(this); 7017 emit_int8((unsigned char)0xDD); 7018 emit_operand32(rbx, adr); 7019 } 7020 7021 void Assembler::fstp_d(int index) { 7022 emit_farith(0xDD, 0xD8, index); 7023 } 7024 7025 void Assembler::fstp_s(Address adr) { 7026 InstructionMark im(this); 7027 emit_int8((unsigned char)0xD9); 7028 emit_operand32(rbx, adr); 7029 } 7030 7031 void Assembler::fstp_x(Address adr) { 7032 InstructionMark im(this); 7033 emit_int8((unsigned char)0xDB); 7034 emit_operand32(rdi, adr); 7035 } 7036 7037 void Assembler::fsub(int i) { 7038 emit_farith(0xD8, 0xE0, i); 7039 } 7040 7041 void Assembler::fsub_d(Address src) { 7042 InstructionMark im(this); 7043 emit_int8((unsigned char)0xDC); 7044 emit_operand32(rsp, src); 7045 } 7046 7047 void Assembler::fsub_s(Address src) { 7048 InstructionMark im(this); 7049 emit_int8((unsigned char)0xD8); 7050 emit_operand32(rsp, src); 7051 } 7052 7053 void Assembler::fsuba(int i) { 7054 emit_farith(0xDC, 0xE8, i); 7055 } 7056 7057 void Assembler::fsubp(int i) { 7058 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 7059 } 7060 7061 void Assembler::fsubr(int i) { 7062 emit_farith(0xD8, 0xE8, i); 7063 } 7064 7065 void Assembler::fsubr_d(Address src) { 7066 InstructionMark im(this); 7067 emit_int8((unsigned char)0xDC); 7068 emit_operand32(rbp, src); 7069 } 7070 7071 void Assembler::fsubr_s(Address src) { 7072 InstructionMark im(this); 7073 emit_int8((unsigned char)0xD8); 7074 emit_operand32(rbp, src); 7075 } 7076 7077 void Assembler::fsubra(int i) { 7078 emit_farith(0xDC, 0xE0, i); 7079 } 7080 7081 void Assembler::fsubrp(int i) { 7082 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 7083 } 7084 7085 void Assembler::ftan() { 7086 emit_int8((unsigned char)0xD9); 7087 emit_int8((unsigned char)0xF2); 7088 emit_int8((unsigned char)0xDD); 7089 emit_int8((unsigned char)0xD8); 7090 } 7091 7092 void Assembler::ftst() { 7093 emit_int8((unsigned char)0xD9); 7094 emit_int8((unsigned char)0xE4); 7095 } 7096 7097 void Assembler::fucomi(int i) { 7098 // make sure the instruction is supported (introduced for P6, together with cmov) 7099 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7100 emit_farith(0xDB, 0xE8, i); 7101 } 7102 7103 void Assembler::fucomip(int i) { 7104 // make sure the instruction is supported (introduced for P6, together with cmov) 7105 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7106 emit_farith(0xDF, 0xE8, i); 7107 } 7108 7109 void Assembler::fwait() { 7110 emit_int8((unsigned char)0x9B); 7111 } 7112 7113 void Assembler::fxch(int i) { 7114 emit_farith(0xD9, 0xC8, i); 7115 } 7116 7117 void Assembler::fyl2x() { 7118 emit_int8((unsigned char)0xD9); 7119 emit_int8((unsigned char)0xF1); 7120 } 7121 7122 void Assembler::frndint() { 7123 emit_int8((unsigned char)0xD9); 7124 emit_int8((unsigned char)0xFC); 7125 } 7126 7127 void Assembler::f2xm1() { 7128 emit_int8((unsigned char)0xD9); 7129 emit_int8((unsigned char)0xF0); 7130 } 7131 7132 void Assembler::fldl2e() { 7133 emit_int8((unsigned char)0xD9); 7134 emit_int8((unsigned char)0xEA); 7135 } 7136 7137 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 7138 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 7139 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 7140 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 7141 7142 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 7143 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7144 if (pre > 0) { 7145 emit_int8(simd_pre[pre]); 7146 } 7147 if (rex_w) { 7148 prefixq(adr, xreg); 7149 } else { 7150 prefix(adr, xreg); 7151 } 7152 if (opc > 0) { 7153 emit_int8(0x0F); 7154 int opc2 = simd_opc[opc]; 7155 if (opc2 > 0) { 7156 emit_int8(opc2); 7157 } 7158 } 7159 } 7160 7161 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7162 if (pre > 0) { 7163 emit_int8(simd_pre[pre]); 7164 } 7165 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); 7166 if (opc > 0) { 7167 emit_int8(0x0F); 7168 int opc2 = simd_opc[opc]; 7169 if (opc2 > 0) { 7170 emit_int8(opc2); 7171 } 7172 } 7173 return encode; 7174 } 7175 7176 7177 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { 7178 int vector_len = _attributes->get_vector_len(); 7179 bool vex_w = _attributes->is_rex_vex_w(); 7180 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 7181 prefix(VEX_3bytes); 7182 7183 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 7184 byte1 = (~byte1) & 0xE0; 7185 byte1 |= opc; 7186 emit_int8(byte1); 7187 7188 int byte2 = ((~nds_enc) & 0xf) << 3; 7189 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 7190 emit_int8(byte2); 7191 } else { 7192 prefix(VEX_2bytes); 7193 7194 int byte1 = vex_r ? VEX_R : 0; 7195 byte1 = (~byte1) & 0x80; 7196 byte1 |= ((~nds_enc) & 0xf) << 3; 7197 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 7198 emit_int8(byte1); 7199 } 7200 } 7201 7202 // This is a 4 byte encoding 7203 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ 7204 // EVEX 0x62 prefix 7205 prefix(EVEX_4bytes); 7206 bool vex_w = _attributes->is_rex_vex_w(); 7207 int evex_encoding = (vex_w ? VEX_W : 0); 7208 // EVEX.b is not currently used for broadcast of single element or data rounding modes 7209 _attributes->set_evex_encoding(evex_encoding); 7210 7211 // P0: byte 2, initialized to RXBR`00mm 7212 // instead of not'd 7213 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 7214 byte2 = (~byte2) & 0xF0; 7215 // confine opc opcode extensions in mm bits to lower two bits 7216 // of form {0F, 0F_38, 0F_3A} 7217 byte2 |= opc; 7218 emit_int8(byte2); 7219 7220 // P1: byte 3 as Wvvvv1pp 7221 int byte3 = ((~nds_enc) & 0xf) << 3; 7222 // p[10] is always 1 7223 byte3 |= EVEX_F; 7224 byte3 |= (vex_w & 1) << 7; 7225 // confine pre opcode extensions in pp bits to lower two bits 7226 // of form {66, F3, F2} 7227 byte3 |= pre; 7228 emit_int8(byte3); 7229 7230 // P2: byte 4 as zL'Lbv'aaa 7231 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now) 7232 int byte4 = (_attributes->is_no_reg_mask()) ? 7233 0 : 7234 _attributes->get_embedded_opmask_register_specifier(); 7235 // EVEX.v` for extending EVEX.vvvv or VIDX 7236 byte4 |= (evex_v ? 0: EVEX_V); 7237 // third EXEC.b for broadcast actions 7238 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); 7239 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 7240 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; 7241 // last is EVEX.z for zero/merge actions 7242 if (_attributes->is_no_reg_mask() == false) { 7243 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); 7244 } 7245 emit_int8(byte4); 7246 } 7247 7248 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7249 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0; 7250 bool vex_b = adr.base_needs_rex(); 7251 bool vex_x = adr.index_needs_rex(); 7252 set_attributes(attributes); 7253 attributes->set_current_assembler(this); 7254 7255 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7256 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7257 switch (attributes->get_vector_len()) { 7258 case AVX_128bit: 7259 case AVX_256bit: 7260 attributes->set_is_legacy_mode(); 7261 break; 7262 } 7263 } 7264 7265 // For pure EVEX check and see if this instruction 7266 // is allowed in legacy mode and has resources which will 7267 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7268 // else that field is set when we encode to EVEX 7269 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7270 !_is_managed && !attributes->is_evex_instruction()) { 7271 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7272 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7273 if (check_register_bank) { 7274 // check nds_enc and xreg_enc for upper bank usage 7275 if (nds_enc < 16 && xreg_enc < 16) { 7276 attributes->set_is_legacy_mode(); 7277 } 7278 } else { 7279 attributes->set_is_legacy_mode(); 7280 } 7281 } 7282 } 7283 7284 _is_managed = false; 7285 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7286 { 7287 bool evex_r = (xreg_enc >= 16); 7288 bool evex_v = (nds_enc >= 16); 7289 attributes->set_is_evex_instruction(); 7290 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7291 } else { 7292 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7293 attributes->set_rex_vex_w(false); 7294 } 7295 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7296 } 7297 } 7298 7299 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7300 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0; 7301 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0; 7302 bool vex_x = false; 7303 set_attributes(attributes); 7304 attributes->set_current_assembler(this); 7305 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7306 7307 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7308 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7309 switch (attributes->get_vector_len()) { 7310 case AVX_128bit: 7311 case AVX_256bit: 7312 if (check_register_bank) { 7313 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) { 7314 // up propagate arithmetic instructions to meet RA requirements 7315 attributes->set_vector_len(AVX_512bit); 7316 } else { 7317 attributes->set_is_legacy_mode(); 7318 } 7319 } else { 7320 attributes->set_is_legacy_mode(); 7321 } 7322 break; 7323 } 7324 } 7325 7326 // For pure EVEX check and see if this instruction 7327 // is allowed in legacy mode and has resources which will 7328 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7329 // else that field is set when we encode to EVEX 7330 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7331 !_is_managed && !attributes->is_evex_instruction()) { 7332 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7333 if (check_register_bank) { 7334 // check dst_enc, nds_enc and src_enc for upper bank usage 7335 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) { 7336 attributes->set_is_legacy_mode(); 7337 } 7338 } else { 7339 attributes->set_is_legacy_mode(); 7340 } 7341 } 7342 } 7343 7344 _is_managed = false; 7345 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7346 { 7347 bool evex_r = (dst_enc >= 16); 7348 bool evex_v = (nds_enc >= 16); 7349 // can use vex_x as bank extender on rm encoding 7350 vex_x = (src_enc >= 16); 7351 attributes->set_is_evex_instruction(); 7352 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7353 } else { 7354 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7355 attributes->set_rex_vex_w(false); 7356 } 7357 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7358 } 7359 7360 // return modrm byte components for operands 7361 return (((dst_enc & 7) << 3) | (src_enc & 7)); 7362 } 7363 7364 7365 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 7366 VexOpcode opc, InstructionAttr *attributes) { 7367 if (UseAVX > 0) { 7368 int xreg_enc = xreg->encoding(); 7369 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7370 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); 7371 } else { 7372 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 7373 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); 7374 } 7375 } 7376 7377 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 7378 VexOpcode opc, InstructionAttr *attributes) { 7379 int dst_enc = dst->encoding(); 7380 int src_enc = src->encoding(); 7381 if (UseAVX > 0) { 7382 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7383 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); 7384 } else { 7385 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 7386 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); 7387 } 7388 } 7389 7390 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 7391 assert(VM_Version::supports_avx(), ""); 7392 assert(!VM_Version::supports_evex(), ""); 7393 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7394 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 7395 emit_int8((unsigned char)0xC2); 7396 emit_int8((unsigned char)(0xC0 | encode)); 7397 emit_int8((unsigned char)(0xF & cop)); 7398 } 7399 7400 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 7401 assert(VM_Version::supports_avx(), ""); 7402 assert(!VM_Version::supports_evex(), ""); 7403 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7404 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7405 emit_int8((unsigned char)0x4B); 7406 emit_int8((unsigned char)(0xC0 | encode)); 7407 int src2_enc = src2->encoding(); 7408 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 7409 } 7410 7411 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 7412 assert(VM_Version::supports_avx2(), ""); 7413 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7414 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7415 emit_int8((unsigned char)0x02); 7416 emit_int8((unsigned char)(0xC0 | encode)); 7417 emit_int8((unsigned char)imm8); 7418 } 7419 7420 void Assembler::shlxl(Register dst, Register src1, Register src2) { 7421 assert(VM_Version::supports_bmi2(), ""); 7422 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7423 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7424 emit_int8((unsigned char)0xF7); 7425 emit_int8((unsigned char)(0xC0 | encode)); 7426 } 7427 7428 void Assembler::shlxq(Register dst, Register src1, Register src2) { 7429 assert(VM_Version::supports_bmi2(), ""); 7430 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7431 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7432 emit_int8((unsigned char)0xF7); 7433 emit_int8((unsigned char)(0xC0 | encode)); 7434 } 7435 7436 #ifndef _LP64 7437 7438 void Assembler::incl(Register dst) { 7439 // Don't use it directly. Use MacroAssembler::incrementl() instead. 7440 emit_int8(0x40 | dst->encoding()); 7441 } 7442 7443 void Assembler::lea(Register dst, Address src) { 7444 leal(dst, src); 7445 } 7446 7447 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 7448 InstructionMark im(this); 7449 emit_int8((unsigned char)0xC7); 7450 emit_operand(rax, dst); 7451 emit_data((int)imm32, rspec, 0); 7452 } 7453 7454 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 7455 InstructionMark im(this); 7456 int encode = prefix_and_encode(dst->encoding()); 7457 emit_int8((unsigned char)(0xB8 | encode)); 7458 emit_data((int)imm32, rspec, 0); 7459 } 7460 7461 void Assembler::popa() { // 32bit 7462 emit_int8(0x61); 7463 } 7464 7465 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 7466 InstructionMark im(this); 7467 emit_int8(0x68); 7468 emit_data(imm32, rspec, 0); 7469 } 7470 7471 void Assembler::pusha() { // 32bit 7472 emit_int8(0x60); 7473 } 7474 7475 void Assembler::set_byte_if_not_zero(Register dst) { 7476 emit_int8(0x0F); 7477 emit_int8((unsigned char)0x95); 7478 emit_int8((unsigned char)(0xE0 | dst->encoding())); 7479 } 7480 7481 void Assembler::shldl(Register dst, Register src) { 7482 emit_int8(0x0F); 7483 emit_int8((unsigned char)0xA5); 7484 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7485 } 7486 7487 // 0F A4 / r ib 7488 void Assembler::shldl(Register dst, Register src, int8_t imm8) { 7489 emit_int8(0x0F); 7490 emit_int8((unsigned char)0xA4); 7491 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7492 emit_int8(imm8); 7493 } 7494 7495 void Assembler::shrdl(Register dst, Register src) { 7496 emit_int8(0x0F); 7497 emit_int8((unsigned char)0xAD); 7498 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7499 } 7500 7501 #else // LP64 7502 7503 void Assembler::set_byte_if_not_zero(Register dst) { 7504 int enc = prefix_and_encode(dst->encoding(), true); 7505 emit_int8(0x0F); 7506 emit_int8((unsigned char)0x95); 7507 emit_int8((unsigned char)(0xE0 | enc)); 7508 } 7509 7510 // 64bit only pieces of the assembler 7511 // This should only be used by 64bit instructions that can use rip-relative 7512 // it cannot be used by instructions that want an immediate value. 7513 7514 bool Assembler::reachable(AddressLiteral adr) { 7515 int64_t disp; 7516 // None will force a 64bit literal to the code stream. Likely a placeholder 7517 // for something that will be patched later and we need to certain it will 7518 // always be reachable. 7519 if (adr.reloc() == relocInfo::none) { 7520 return false; 7521 } 7522 if (adr.reloc() == relocInfo::internal_word_type) { 7523 // This should be rip relative and easily reachable. 7524 return true; 7525 } 7526 if (adr.reloc() == relocInfo::virtual_call_type || 7527 adr.reloc() == relocInfo::opt_virtual_call_type || 7528 adr.reloc() == relocInfo::static_call_type || 7529 adr.reloc() == relocInfo::static_stub_type ) { 7530 // This should be rip relative within the code cache and easily 7531 // reachable until we get huge code caches. (At which point 7532 // ic code is going to have issues). 7533 return true; 7534 } 7535 if (adr.reloc() != relocInfo::external_word_type && 7536 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 7537 adr.reloc() != relocInfo::poll_type && // relocs to identify them 7538 adr.reloc() != relocInfo::runtime_call_type ) { 7539 return false; 7540 } 7541 7542 // Stress the correction code 7543 if (ForceUnreachable) { 7544 // Must be runtimecall reloc, see if it is in the codecache 7545 // Flipping stuff in the codecache to be unreachable causes issues 7546 // with things like inline caches where the additional instructions 7547 // are not handled. 7548 if (CodeCache::find_blob(adr._target) == NULL) { 7549 return false; 7550 } 7551 } 7552 // For external_word_type/runtime_call_type if it is reachable from where we 7553 // are now (possibly a temp buffer) and where we might end up 7554 // anywhere in the codeCache then we are always reachable. 7555 // This would have to change if we ever save/restore shared code 7556 // to be more pessimistic. 7557 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 7558 if (!is_simm32(disp)) return false; 7559 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 7560 if (!is_simm32(disp)) return false; 7561 7562 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 7563 7564 // Because rip relative is a disp + address_of_next_instruction and we 7565 // don't know the value of address_of_next_instruction we apply a fudge factor 7566 // to make sure we will be ok no matter the size of the instruction we get placed into. 7567 // We don't have to fudge the checks above here because they are already worst case. 7568 7569 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 7570 // + 4 because better safe than sorry. 7571 const int fudge = 12 + 4; 7572 if (disp < 0) { 7573 disp -= fudge; 7574 } else { 7575 disp += fudge; 7576 } 7577 return is_simm32(disp); 7578 } 7579 7580 // Check if the polling page is not reachable from the code cache using rip-relative 7581 // addressing. 7582 bool Assembler::is_polling_page_far() { 7583 intptr_t addr = (intptr_t)os::get_polling_page(); 7584 return ForceUnreachable || 7585 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 7586 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 7587 } 7588 7589 void Assembler::emit_data64(jlong data, 7590 relocInfo::relocType rtype, 7591 int format) { 7592 if (rtype == relocInfo::none) { 7593 emit_int64(data); 7594 } else { 7595 emit_data64(data, Relocation::spec_simple(rtype), format); 7596 } 7597 } 7598 7599 void Assembler::emit_data64(jlong data, 7600 RelocationHolder const& rspec, 7601 int format) { 7602 assert(imm_operand == 0, "default format must be immediate in this file"); 7603 assert(imm_operand == format, "must be immediate"); 7604 assert(inst_mark() != NULL, "must be inside InstructionMark"); 7605 // Do not use AbstractAssembler::relocate, which is not intended for 7606 // embedded words. Instead, relocate to the enclosing instruction. 7607 code_section()->relocate(inst_mark(), rspec, format); 7608 #ifdef ASSERT 7609 check_relocation(rspec, format); 7610 #endif 7611 emit_int64(data); 7612 } 7613 7614 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 7615 if (reg_enc >= 8) { 7616 prefix(REX_B); 7617 reg_enc -= 8; 7618 } else if (byteinst && reg_enc >= 4) { 7619 prefix(REX); 7620 } 7621 return reg_enc; 7622 } 7623 7624 int Assembler::prefixq_and_encode(int reg_enc) { 7625 if (reg_enc < 8) { 7626 prefix(REX_W); 7627 } else { 7628 prefix(REX_WB); 7629 reg_enc -= 8; 7630 } 7631 return reg_enc; 7632 } 7633 7634 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { 7635 if (dst_enc < 8) { 7636 if (src_enc >= 8) { 7637 prefix(REX_B); 7638 src_enc -= 8; 7639 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { 7640 prefix(REX); 7641 } 7642 } else { 7643 if (src_enc < 8) { 7644 prefix(REX_R); 7645 } else { 7646 prefix(REX_RB); 7647 src_enc -= 8; 7648 } 7649 dst_enc -= 8; 7650 } 7651 return dst_enc << 3 | src_enc; 7652 } 7653 7654 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 7655 if (dst_enc < 8) { 7656 if (src_enc < 8) { 7657 prefix(REX_W); 7658 } else { 7659 prefix(REX_WB); 7660 src_enc -= 8; 7661 } 7662 } else { 7663 if (src_enc < 8) { 7664 prefix(REX_WR); 7665 } else { 7666 prefix(REX_WRB); 7667 src_enc -= 8; 7668 } 7669 dst_enc -= 8; 7670 } 7671 return dst_enc << 3 | src_enc; 7672 } 7673 7674 void Assembler::prefix(Register reg) { 7675 if (reg->encoding() >= 8) { 7676 prefix(REX_B); 7677 } 7678 } 7679 7680 void Assembler::prefix(Register dst, Register src, Prefix p) { 7681 if (src->encoding() >= 8) { 7682 p = (Prefix)(p | REX_B); 7683 } 7684 if (dst->encoding() >= 8) { 7685 p = (Prefix)( p | REX_R); 7686 } 7687 if (p != Prefix_EMPTY) { 7688 // do not generate an empty prefix 7689 prefix(p); 7690 } 7691 } 7692 7693 void Assembler::prefix(Register dst, Address adr, Prefix p) { 7694 if (adr.base_needs_rex()) { 7695 if (adr.index_needs_rex()) { 7696 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7697 } else { 7698 prefix(REX_B); 7699 } 7700 } else { 7701 if (adr.index_needs_rex()) { 7702 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7703 } 7704 } 7705 if (dst->encoding() >= 8) { 7706 p = (Prefix)(p | REX_R); 7707 } 7708 if (p != Prefix_EMPTY) { 7709 // do not generate an empty prefix 7710 prefix(p); 7711 } 7712 } 7713 7714 void Assembler::prefix(Address adr) { 7715 if (adr.base_needs_rex()) { 7716 if (adr.index_needs_rex()) { 7717 prefix(REX_XB); 7718 } else { 7719 prefix(REX_B); 7720 } 7721 } else { 7722 if (adr.index_needs_rex()) { 7723 prefix(REX_X); 7724 } 7725 } 7726 } 7727 7728 void Assembler::prefixq(Address adr) { 7729 if (adr.base_needs_rex()) { 7730 if (adr.index_needs_rex()) { 7731 prefix(REX_WXB); 7732 } else { 7733 prefix(REX_WB); 7734 } 7735 } else { 7736 if (adr.index_needs_rex()) { 7737 prefix(REX_WX); 7738 } else { 7739 prefix(REX_W); 7740 } 7741 } 7742 } 7743 7744 7745 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 7746 if (reg->encoding() < 8) { 7747 if (adr.base_needs_rex()) { 7748 if (adr.index_needs_rex()) { 7749 prefix(REX_XB); 7750 } else { 7751 prefix(REX_B); 7752 } 7753 } else { 7754 if (adr.index_needs_rex()) { 7755 prefix(REX_X); 7756 } else if (byteinst && reg->encoding() >= 4 ) { 7757 prefix(REX); 7758 } 7759 } 7760 } else { 7761 if (adr.base_needs_rex()) { 7762 if (adr.index_needs_rex()) { 7763 prefix(REX_RXB); 7764 } else { 7765 prefix(REX_RB); 7766 } 7767 } else { 7768 if (adr.index_needs_rex()) { 7769 prefix(REX_RX); 7770 } else { 7771 prefix(REX_R); 7772 } 7773 } 7774 } 7775 } 7776 7777 void Assembler::prefixq(Address adr, Register src) { 7778 if (src->encoding() < 8) { 7779 if (adr.base_needs_rex()) { 7780 if (adr.index_needs_rex()) { 7781 prefix(REX_WXB); 7782 } else { 7783 prefix(REX_WB); 7784 } 7785 } else { 7786 if (adr.index_needs_rex()) { 7787 prefix(REX_WX); 7788 } else { 7789 prefix(REX_W); 7790 } 7791 } 7792 } else { 7793 if (adr.base_needs_rex()) { 7794 if (adr.index_needs_rex()) { 7795 prefix(REX_WRXB); 7796 } else { 7797 prefix(REX_WRB); 7798 } 7799 } else { 7800 if (adr.index_needs_rex()) { 7801 prefix(REX_WRX); 7802 } else { 7803 prefix(REX_WR); 7804 } 7805 } 7806 } 7807 } 7808 7809 void Assembler::prefix(Address adr, XMMRegister reg) { 7810 if (reg->encoding() < 8) { 7811 if (adr.base_needs_rex()) { 7812 if (adr.index_needs_rex()) { 7813 prefix(REX_XB); 7814 } else { 7815 prefix(REX_B); 7816 } 7817 } else { 7818 if (adr.index_needs_rex()) { 7819 prefix(REX_X); 7820 } 7821 } 7822 } else { 7823 if (adr.base_needs_rex()) { 7824 if (adr.index_needs_rex()) { 7825 prefix(REX_RXB); 7826 } else { 7827 prefix(REX_RB); 7828 } 7829 } else { 7830 if (adr.index_needs_rex()) { 7831 prefix(REX_RX); 7832 } else { 7833 prefix(REX_R); 7834 } 7835 } 7836 } 7837 } 7838 7839 void Assembler::prefixq(Address adr, XMMRegister src) { 7840 if (src->encoding() < 8) { 7841 if (adr.base_needs_rex()) { 7842 if (adr.index_needs_rex()) { 7843 prefix(REX_WXB); 7844 } else { 7845 prefix(REX_WB); 7846 } 7847 } else { 7848 if (adr.index_needs_rex()) { 7849 prefix(REX_WX); 7850 } else { 7851 prefix(REX_W); 7852 } 7853 } 7854 } else { 7855 if (adr.base_needs_rex()) { 7856 if (adr.index_needs_rex()) { 7857 prefix(REX_WRXB); 7858 } else { 7859 prefix(REX_WRB); 7860 } 7861 } else { 7862 if (adr.index_needs_rex()) { 7863 prefix(REX_WRX); 7864 } else { 7865 prefix(REX_WR); 7866 } 7867 } 7868 } 7869 } 7870 7871 void Assembler::adcq(Register dst, int32_t imm32) { 7872 (void) prefixq_and_encode(dst->encoding()); 7873 emit_arith(0x81, 0xD0, dst, imm32); 7874 } 7875 7876 void Assembler::adcq(Register dst, Address src) { 7877 InstructionMark im(this); 7878 prefixq(src, dst); 7879 emit_int8(0x13); 7880 emit_operand(dst, src); 7881 } 7882 7883 void Assembler::adcq(Register dst, Register src) { 7884 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7885 emit_arith(0x13, 0xC0, dst, src); 7886 } 7887 7888 void Assembler::addq(Address dst, int32_t imm32) { 7889 InstructionMark im(this); 7890 prefixq(dst); 7891 emit_arith_operand(0x81, rax, dst,imm32); 7892 } 7893 7894 void Assembler::addq(Address dst, Register src) { 7895 InstructionMark im(this); 7896 prefixq(dst, src); 7897 emit_int8(0x01); 7898 emit_operand(src, dst); 7899 } 7900 7901 void Assembler::addq(Register dst, int32_t imm32) { 7902 (void) prefixq_and_encode(dst->encoding()); 7903 emit_arith(0x81, 0xC0, dst, imm32); 7904 } 7905 7906 void Assembler::addq(Register dst, Address src) { 7907 InstructionMark im(this); 7908 prefixq(src, dst); 7909 emit_int8(0x03); 7910 emit_operand(dst, src); 7911 } 7912 7913 void Assembler::addq(Register dst, Register src) { 7914 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7915 emit_arith(0x03, 0xC0, dst, src); 7916 } 7917 7918 void Assembler::adcxq(Register dst, Register src) { 7919 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7920 emit_int8((unsigned char)0x66); 7921 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7922 emit_int8(0x0F); 7923 emit_int8(0x38); 7924 emit_int8((unsigned char)0xF6); 7925 emit_int8((unsigned char)(0xC0 | encode)); 7926 } 7927 7928 void Assembler::adoxq(Register dst, Register src) { 7929 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7930 emit_int8((unsigned char)0xF3); 7931 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7932 emit_int8(0x0F); 7933 emit_int8(0x38); 7934 emit_int8((unsigned char)0xF6); 7935 emit_int8((unsigned char)(0xC0 | encode)); 7936 } 7937 7938 void Assembler::andq(Address dst, int32_t imm32) { 7939 InstructionMark im(this); 7940 prefixq(dst); 7941 emit_int8((unsigned char)0x81); 7942 emit_operand(rsp, dst, 4); 7943 emit_int32(imm32); 7944 } 7945 7946 void Assembler::andq(Register dst, int32_t imm32) { 7947 (void) prefixq_and_encode(dst->encoding()); 7948 emit_arith(0x81, 0xE0, dst, imm32); 7949 } 7950 7951 void Assembler::andq(Register dst, Address src) { 7952 InstructionMark im(this); 7953 prefixq(src, dst); 7954 emit_int8(0x23); 7955 emit_operand(dst, src); 7956 } 7957 7958 void Assembler::andq(Register dst, Register src) { 7959 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7960 emit_arith(0x23, 0xC0, dst, src); 7961 } 7962 7963 void Assembler::andnq(Register dst, Register src1, Register src2) { 7964 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7965 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7966 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7967 emit_int8((unsigned char)0xF2); 7968 emit_int8((unsigned char)(0xC0 | encode)); 7969 } 7970 7971 void Assembler::andnq(Register dst, Register src1, Address src2) { 7972 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7973 InstructionMark im(this); 7974 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7975 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7976 emit_int8((unsigned char)0xF2); 7977 emit_operand(dst, src2); 7978 } 7979 7980 void Assembler::bsfq(Register dst, Register src) { 7981 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7982 emit_int8(0x0F); 7983 emit_int8((unsigned char)0xBC); 7984 emit_int8((unsigned char)(0xC0 | encode)); 7985 } 7986 7987 void Assembler::bsrq(Register dst, Register src) { 7988 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7989 emit_int8(0x0F); 7990 emit_int8((unsigned char)0xBD); 7991 emit_int8((unsigned char)(0xC0 | encode)); 7992 } 7993 7994 void Assembler::bswapq(Register reg) { 7995 int encode = prefixq_and_encode(reg->encoding()); 7996 emit_int8(0x0F); 7997 emit_int8((unsigned char)(0xC8 | encode)); 7998 } 7999 8000 void Assembler::blsiq(Register dst, Register src) { 8001 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8002 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8003 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8004 emit_int8((unsigned char)0xF3); 8005 emit_int8((unsigned char)(0xC0 | encode)); 8006 } 8007 8008 void Assembler::blsiq(Register dst, Address src) { 8009 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8010 InstructionMark im(this); 8011 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8012 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8013 emit_int8((unsigned char)0xF3); 8014 emit_operand(rbx, src); 8015 } 8016 8017 void Assembler::blsmskq(Register dst, Register src) { 8018 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8019 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8020 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8021 emit_int8((unsigned char)0xF3); 8022 emit_int8((unsigned char)(0xC0 | encode)); 8023 } 8024 8025 void Assembler::blsmskq(Register dst, Address src) { 8026 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8027 InstructionMark im(this); 8028 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8029 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8030 emit_int8((unsigned char)0xF3); 8031 emit_operand(rdx, src); 8032 } 8033 8034 void Assembler::blsrq(Register dst, Register src) { 8035 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8036 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8037 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8038 emit_int8((unsigned char)0xF3); 8039 emit_int8((unsigned char)(0xC0 | encode)); 8040 } 8041 8042 void Assembler::blsrq(Register dst, Address src) { 8043 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8044 InstructionMark im(this); 8045 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8046 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8047 emit_int8((unsigned char)0xF3); 8048 emit_operand(rcx, src); 8049 } 8050 8051 void Assembler::cdqq() { 8052 prefix(REX_W); 8053 emit_int8((unsigned char)0x99); 8054 } 8055 8056 void Assembler::clflush(Address adr) { 8057 prefix(adr); 8058 emit_int8(0x0F); 8059 emit_int8((unsigned char)0xAE); 8060 emit_operand(rdi, adr); 8061 } 8062 8063 void Assembler::cmovq(Condition cc, Register dst, Register src) { 8064 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8065 emit_int8(0x0F); 8066 emit_int8(0x40 | cc); 8067 emit_int8((unsigned char)(0xC0 | encode)); 8068 } 8069 8070 void Assembler::cmovq(Condition cc, Register dst, Address src) { 8071 InstructionMark im(this); 8072 prefixq(src, dst); 8073 emit_int8(0x0F); 8074 emit_int8(0x40 | cc); 8075 emit_operand(dst, src); 8076 } 8077 8078 void Assembler::cmpq(Address dst, int32_t imm32) { 8079 InstructionMark im(this); 8080 prefixq(dst); 8081 emit_int8((unsigned char)0x81); 8082 emit_operand(rdi, dst, 4); 8083 emit_int32(imm32); 8084 } 8085 8086 void Assembler::cmpq(Register dst, int32_t imm32) { 8087 (void) prefixq_and_encode(dst->encoding()); 8088 emit_arith(0x81, 0xF8, dst, imm32); 8089 } 8090 8091 void Assembler::cmpq(Address dst, Register src) { 8092 InstructionMark im(this); 8093 prefixq(dst, src); 8094 emit_int8(0x3B); 8095 emit_operand(src, dst); 8096 } 8097 8098 void Assembler::cmpq(Register dst, Register src) { 8099 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8100 emit_arith(0x3B, 0xC0, dst, src); 8101 } 8102 8103 void Assembler::cmpq(Register dst, Address src) { 8104 InstructionMark im(this); 8105 prefixq(src, dst); 8106 emit_int8(0x3B); 8107 emit_operand(dst, src); 8108 } 8109 8110 void Assembler::cmpxchgq(Register reg, Address adr) { 8111 InstructionMark im(this); 8112 prefixq(adr, reg); 8113 emit_int8(0x0F); 8114 emit_int8((unsigned char)0xB1); 8115 emit_operand(reg, adr); 8116 } 8117 8118 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 8119 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8120 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8121 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8122 emit_int8(0x2A); 8123 emit_int8((unsigned char)(0xC0 | encode)); 8124 } 8125 8126 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 8127 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8128 InstructionMark im(this); 8129 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8130 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8131 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8132 emit_int8(0x2A); 8133 emit_operand(dst, src); 8134 } 8135 8136 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 8137 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8138 InstructionMark im(this); 8139 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8140 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8141 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8142 emit_int8(0x2A); 8143 emit_operand(dst, src); 8144 } 8145 8146 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 8147 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8148 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8149 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8150 emit_int8(0x2C); 8151 emit_int8((unsigned char)(0xC0 | encode)); 8152 } 8153 8154 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 8155 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8156 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8157 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8158 emit_int8(0x2C); 8159 emit_int8((unsigned char)(0xC0 | encode)); 8160 } 8161 8162 void Assembler::decl(Register dst) { 8163 // Don't use it directly. Use MacroAssembler::decrementl() instead. 8164 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 8165 int encode = prefix_and_encode(dst->encoding()); 8166 emit_int8((unsigned char)0xFF); 8167 emit_int8((unsigned char)(0xC8 | encode)); 8168 } 8169 8170 void Assembler::decq(Register dst) { 8171 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8172 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8173 int encode = prefixq_and_encode(dst->encoding()); 8174 emit_int8((unsigned char)0xFF); 8175 emit_int8(0xC8 | encode); 8176 } 8177 8178 void Assembler::decq(Address dst) { 8179 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8180 InstructionMark im(this); 8181 prefixq(dst); 8182 emit_int8((unsigned char)0xFF); 8183 emit_operand(rcx, dst); 8184 } 8185 8186 void Assembler::fxrstor(Address src) { 8187 prefixq(src); 8188 emit_int8(0x0F); 8189 emit_int8((unsigned char)0xAE); 8190 emit_operand(as_Register(1), src); 8191 } 8192 8193 void Assembler::xrstor(Address src) { 8194 prefixq(src); 8195 emit_int8(0x0F); 8196 emit_int8((unsigned char)0xAE); 8197 emit_operand(as_Register(5), src); 8198 } 8199 8200 void Assembler::fxsave(Address dst) { 8201 prefixq(dst); 8202 emit_int8(0x0F); 8203 emit_int8((unsigned char)0xAE); 8204 emit_operand(as_Register(0), dst); 8205 } 8206 8207 void Assembler::xsave(Address dst) { 8208 prefixq(dst); 8209 emit_int8(0x0F); 8210 emit_int8((unsigned char)0xAE); 8211 emit_operand(as_Register(4), dst); 8212 } 8213 8214 void Assembler::idivq(Register src) { 8215 int encode = prefixq_and_encode(src->encoding()); 8216 emit_int8((unsigned char)0xF7); 8217 emit_int8((unsigned char)(0xF8 | encode)); 8218 } 8219 8220 void Assembler::imulq(Register dst, Register src) { 8221 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8222 emit_int8(0x0F); 8223 emit_int8((unsigned char)0xAF); 8224 emit_int8((unsigned char)(0xC0 | encode)); 8225 } 8226 8227 void Assembler::imulq(Register dst, Register src, int value) { 8228 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8229 if (is8bit(value)) { 8230 emit_int8(0x6B); 8231 emit_int8((unsigned char)(0xC0 | encode)); 8232 emit_int8(value & 0xFF); 8233 } else { 8234 emit_int8(0x69); 8235 emit_int8((unsigned char)(0xC0 | encode)); 8236 emit_int32(value); 8237 } 8238 } 8239 8240 void Assembler::imulq(Register dst, Address src) { 8241 InstructionMark im(this); 8242 prefixq(src, dst); 8243 emit_int8(0x0F); 8244 emit_int8((unsigned char) 0xAF); 8245 emit_operand(dst, src); 8246 } 8247 8248 void Assembler::incl(Register dst) { 8249 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8250 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8251 int encode = prefix_and_encode(dst->encoding()); 8252 emit_int8((unsigned char)0xFF); 8253 emit_int8((unsigned char)(0xC0 | encode)); 8254 } 8255 8256 void Assembler::incq(Register dst) { 8257 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8258 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8259 int encode = prefixq_and_encode(dst->encoding()); 8260 emit_int8((unsigned char)0xFF); 8261 emit_int8((unsigned char)(0xC0 | encode)); 8262 } 8263 8264 void Assembler::incq(Address dst) { 8265 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8266 InstructionMark im(this); 8267 prefixq(dst); 8268 emit_int8((unsigned char)0xFF); 8269 emit_operand(rax, dst); 8270 } 8271 8272 void Assembler::lea(Register dst, Address src) { 8273 leaq(dst, src); 8274 } 8275 8276 void Assembler::leaq(Register dst, Address src) { 8277 InstructionMark im(this); 8278 prefixq(src, dst); 8279 emit_int8((unsigned char)0x8D); 8280 emit_operand(dst, src); 8281 } 8282 8283 void Assembler::mov64(Register dst, int64_t imm64) { 8284 InstructionMark im(this); 8285 int encode = prefixq_and_encode(dst->encoding()); 8286 emit_int8((unsigned char)(0xB8 | encode)); 8287 emit_int64(imm64); 8288 } 8289 8290 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 8291 InstructionMark im(this); 8292 int encode = prefixq_and_encode(dst->encoding()); 8293 emit_int8(0xB8 | encode); 8294 emit_data64(imm64, rspec); 8295 } 8296 8297 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8298 InstructionMark im(this); 8299 int encode = prefix_and_encode(dst->encoding()); 8300 emit_int8((unsigned char)(0xB8 | encode)); 8301 emit_data((int)imm32, rspec, narrow_oop_operand); 8302 } 8303 8304 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8305 InstructionMark im(this); 8306 prefix(dst); 8307 emit_int8((unsigned char)0xC7); 8308 emit_operand(rax, dst, 4); 8309 emit_data((int)imm32, rspec, narrow_oop_operand); 8310 } 8311 8312 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 8313 InstructionMark im(this); 8314 int encode = prefix_and_encode(src1->encoding()); 8315 emit_int8((unsigned char)0x81); 8316 emit_int8((unsigned char)(0xF8 | encode)); 8317 emit_data((int)imm32, rspec, narrow_oop_operand); 8318 } 8319 8320 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 8321 InstructionMark im(this); 8322 prefix(src1); 8323 emit_int8((unsigned char)0x81); 8324 emit_operand(rax, src1, 4); 8325 emit_data((int)imm32, rspec, narrow_oop_operand); 8326 } 8327 8328 void Assembler::lzcntq(Register dst, Register src) { 8329 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 8330 emit_int8((unsigned char)0xF3); 8331 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8332 emit_int8(0x0F); 8333 emit_int8((unsigned char)0xBD); 8334 emit_int8((unsigned char)(0xC0 | encode)); 8335 } 8336 8337 void Assembler::movdq(XMMRegister dst, Register src) { 8338 // table D-1 says MMX/SSE2 8339 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8340 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8341 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8342 emit_int8(0x6E); 8343 emit_int8((unsigned char)(0xC0 | encode)); 8344 } 8345 8346 void Assembler::movdq(Register dst, XMMRegister src) { 8347 // table D-1 says MMX/SSE2 8348 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8349 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8350 // swap src/dst to get correct prefix 8351 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8352 emit_int8(0x7E); 8353 emit_int8((unsigned char)(0xC0 | encode)); 8354 } 8355 8356 void Assembler::movq(Register dst, Register src) { 8357 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8358 emit_int8((unsigned char)0x8B); 8359 emit_int8((unsigned char)(0xC0 | encode)); 8360 } 8361 8362 void Assembler::movq(Register dst, Address src) { 8363 InstructionMark im(this); 8364 prefixq(src, dst); 8365 emit_int8((unsigned char)0x8B); 8366 emit_operand(dst, src); 8367 } 8368 8369 void Assembler::movq(Address dst, Register src) { 8370 InstructionMark im(this); 8371 prefixq(dst, src); 8372 emit_int8((unsigned char)0x89); 8373 emit_operand(src, dst); 8374 } 8375 8376 void Assembler::movsbq(Register dst, Address src) { 8377 InstructionMark im(this); 8378 prefixq(src, dst); 8379 emit_int8(0x0F); 8380 emit_int8((unsigned char)0xBE); 8381 emit_operand(dst, src); 8382 } 8383 8384 void Assembler::movsbq(Register dst, Register src) { 8385 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8386 emit_int8(0x0F); 8387 emit_int8((unsigned char)0xBE); 8388 emit_int8((unsigned char)(0xC0 | encode)); 8389 } 8390 8391 void Assembler::movslq(Register dst, int32_t imm32) { 8392 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 8393 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 8394 // as a result we shouldn't use until tested at runtime... 8395 ShouldNotReachHere(); 8396 InstructionMark im(this); 8397 int encode = prefixq_and_encode(dst->encoding()); 8398 emit_int8((unsigned char)(0xC7 | encode)); 8399 emit_int32(imm32); 8400 } 8401 8402 void Assembler::movslq(Address dst, int32_t imm32) { 8403 assert(is_simm32(imm32), "lost bits"); 8404 InstructionMark im(this); 8405 prefixq(dst); 8406 emit_int8((unsigned char)0xC7); 8407 emit_operand(rax, dst, 4); 8408 emit_int32(imm32); 8409 } 8410 8411 void Assembler::movslq(Register dst, Address src) { 8412 InstructionMark im(this); 8413 prefixq(src, dst); 8414 emit_int8(0x63); 8415 emit_operand(dst, src); 8416 } 8417 8418 void Assembler::movslq(Register dst, Register src) { 8419 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8420 emit_int8(0x63); 8421 emit_int8((unsigned char)(0xC0 | encode)); 8422 } 8423 8424 void Assembler::movswq(Register dst, Address src) { 8425 InstructionMark im(this); 8426 prefixq(src, dst); 8427 emit_int8(0x0F); 8428 emit_int8((unsigned char)0xBF); 8429 emit_operand(dst, src); 8430 } 8431 8432 void Assembler::movswq(Register dst, Register src) { 8433 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8434 emit_int8((unsigned char)0x0F); 8435 emit_int8((unsigned char)0xBF); 8436 emit_int8((unsigned char)(0xC0 | encode)); 8437 } 8438 8439 void Assembler::movzbq(Register dst, Address src) { 8440 InstructionMark im(this); 8441 prefixq(src, dst); 8442 emit_int8((unsigned char)0x0F); 8443 emit_int8((unsigned char)0xB6); 8444 emit_operand(dst, src); 8445 } 8446 8447 void Assembler::movzbq(Register dst, Register src) { 8448 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8449 emit_int8(0x0F); 8450 emit_int8((unsigned char)0xB6); 8451 emit_int8(0xC0 | encode); 8452 } 8453 8454 void Assembler::movzwq(Register dst, Address src) { 8455 InstructionMark im(this); 8456 prefixq(src, dst); 8457 emit_int8((unsigned char)0x0F); 8458 emit_int8((unsigned char)0xB7); 8459 emit_operand(dst, src); 8460 } 8461 8462 void Assembler::movzwq(Register dst, Register src) { 8463 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8464 emit_int8((unsigned char)0x0F); 8465 emit_int8((unsigned char)0xB7); 8466 emit_int8((unsigned char)(0xC0 | encode)); 8467 } 8468 8469 void Assembler::mulq(Address src) { 8470 InstructionMark im(this); 8471 prefixq(src); 8472 emit_int8((unsigned char)0xF7); 8473 emit_operand(rsp, src); 8474 } 8475 8476 void Assembler::mulq(Register src) { 8477 int encode = prefixq_and_encode(src->encoding()); 8478 emit_int8((unsigned char)0xF7); 8479 emit_int8((unsigned char)(0xE0 | encode)); 8480 } 8481 8482 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 8483 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8484 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8485 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); 8486 emit_int8((unsigned char)0xF6); 8487 emit_int8((unsigned char)(0xC0 | encode)); 8488 } 8489 8490 void Assembler::negq(Register dst) { 8491 int encode = prefixq_and_encode(dst->encoding()); 8492 emit_int8((unsigned char)0xF7); 8493 emit_int8((unsigned char)(0xD8 | encode)); 8494 } 8495 8496 void Assembler::notq(Register dst) { 8497 int encode = prefixq_and_encode(dst->encoding()); 8498 emit_int8((unsigned char)0xF7); 8499 emit_int8((unsigned char)(0xD0 | encode)); 8500 } 8501 8502 void Assembler::orq(Address dst, int32_t imm32) { 8503 InstructionMark im(this); 8504 prefixq(dst); 8505 emit_int8((unsigned char)0x81); 8506 emit_operand(rcx, dst, 4); 8507 emit_int32(imm32); 8508 } 8509 8510 void Assembler::orq(Register dst, int32_t imm32) { 8511 (void) prefixq_and_encode(dst->encoding()); 8512 emit_arith(0x81, 0xC8, dst, imm32); 8513 } 8514 8515 void Assembler::orq(Register dst, Address src) { 8516 InstructionMark im(this); 8517 prefixq(src, dst); 8518 emit_int8(0x0B); 8519 emit_operand(dst, src); 8520 } 8521 8522 void Assembler::orq(Register dst, Register src) { 8523 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8524 emit_arith(0x0B, 0xC0, dst, src); 8525 } 8526 8527 void Assembler::popa() { // 64bit 8528 movq(r15, Address(rsp, 0)); 8529 movq(r14, Address(rsp, wordSize)); 8530 movq(r13, Address(rsp, 2 * wordSize)); 8531 movq(r12, Address(rsp, 3 * wordSize)); 8532 movq(r11, Address(rsp, 4 * wordSize)); 8533 movq(r10, Address(rsp, 5 * wordSize)); 8534 movq(r9, Address(rsp, 6 * wordSize)); 8535 movq(r8, Address(rsp, 7 * wordSize)); 8536 movq(rdi, Address(rsp, 8 * wordSize)); 8537 movq(rsi, Address(rsp, 9 * wordSize)); 8538 movq(rbp, Address(rsp, 10 * wordSize)); 8539 // skip rsp 8540 movq(rbx, Address(rsp, 12 * wordSize)); 8541 movq(rdx, Address(rsp, 13 * wordSize)); 8542 movq(rcx, Address(rsp, 14 * wordSize)); 8543 movq(rax, Address(rsp, 15 * wordSize)); 8544 8545 addq(rsp, 16 * wordSize); 8546 } 8547 8548 void Assembler::popcntq(Register dst, Address src) { 8549 assert(VM_Version::supports_popcnt(), "must support"); 8550 InstructionMark im(this); 8551 emit_int8((unsigned char)0xF3); 8552 prefixq(src, dst); 8553 emit_int8((unsigned char)0x0F); 8554 emit_int8((unsigned char)0xB8); 8555 emit_operand(dst, src); 8556 } 8557 8558 void Assembler::popcntq(Register dst, Register src) { 8559 assert(VM_Version::supports_popcnt(), "must support"); 8560 emit_int8((unsigned char)0xF3); 8561 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8562 emit_int8((unsigned char)0x0F); 8563 emit_int8((unsigned char)0xB8); 8564 emit_int8((unsigned char)(0xC0 | encode)); 8565 } 8566 8567 void Assembler::popq(Address dst) { 8568 InstructionMark im(this); 8569 prefixq(dst); 8570 emit_int8((unsigned char)0x8F); 8571 emit_operand(rax, dst); 8572 } 8573 8574 void Assembler::pusha() { // 64bit 8575 // we have to store original rsp. ABI says that 128 bytes 8576 // below rsp are local scratch. 8577 movq(Address(rsp, -5 * wordSize), rsp); 8578 8579 subq(rsp, 16 * wordSize); 8580 8581 movq(Address(rsp, 15 * wordSize), rax); 8582 movq(Address(rsp, 14 * wordSize), rcx); 8583 movq(Address(rsp, 13 * wordSize), rdx); 8584 movq(Address(rsp, 12 * wordSize), rbx); 8585 // skip rsp 8586 movq(Address(rsp, 10 * wordSize), rbp); 8587 movq(Address(rsp, 9 * wordSize), rsi); 8588 movq(Address(rsp, 8 * wordSize), rdi); 8589 movq(Address(rsp, 7 * wordSize), r8); 8590 movq(Address(rsp, 6 * wordSize), r9); 8591 movq(Address(rsp, 5 * wordSize), r10); 8592 movq(Address(rsp, 4 * wordSize), r11); 8593 movq(Address(rsp, 3 * wordSize), r12); 8594 movq(Address(rsp, 2 * wordSize), r13); 8595 movq(Address(rsp, wordSize), r14); 8596 movq(Address(rsp, 0), r15); 8597 } 8598 8599 void Assembler::pushq(Address src) { 8600 InstructionMark im(this); 8601 prefixq(src); 8602 emit_int8((unsigned char)0xFF); 8603 emit_operand(rsi, src); 8604 } 8605 8606 void Assembler::rclq(Register dst, int imm8) { 8607 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8608 int encode = prefixq_and_encode(dst->encoding()); 8609 if (imm8 == 1) { 8610 emit_int8((unsigned char)0xD1); 8611 emit_int8((unsigned char)(0xD0 | encode)); 8612 } else { 8613 emit_int8((unsigned char)0xC1); 8614 emit_int8((unsigned char)(0xD0 | encode)); 8615 emit_int8(imm8); 8616 } 8617 } 8618 8619 void Assembler::rcrq(Register dst, int imm8) { 8620 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8621 int encode = prefixq_and_encode(dst->encoding()); 8622 if (imm8 == 1) { 8623 emit_int8((unsigned char)0xD1); 8624 emit_int8((unsigned char)(0xD8 | encode)); 8625 } else { 8626 emit_int8((unsigned char)0xC1); 8627 emit_int8((unsigned char)(0xD8 | encode)); 8628 emit_int8(imm8); 8629 } 8630 } 8631 8632 void Assembler::rorq(Register dst, int imm8) { 8633 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8634 int encode = prefixq_and_encode(dst->encoding()); 8635 if (imm8 == 1) { 8636 emit_int8((unsigned char)0xD1); 8637 emit_int8((unsigned char)(0xC8 | encode)); 8638 } else { 8639 emit_int8((unsigned char)0xC1); 8640 emit_int8((unsigned char)(0xc8 | encode)); 8641 emit_int8(imm8); 8642 } 8643 } 8644 8645 void Assembler::rorxq(Register dst, Register src, int imm8) { 8646 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8647 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8648 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8649 emit_int8((unsigned char)0xF0); 8650 emit_int8((unsigned char)(0xC0 | encode)); 8651 emit_int8(imm8); 8652 } 8653 8654 void Assembler::rorxd(Register dst, Register src, int imm8) { 8655 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8656 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8657 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8658 emit_int8((unsigned char)0xF0); 8659 emit_int8((unsigned char)(0xC0 | encode)); 8660 emit_int8(imm8); 8661 } 8662 8663 void Assembler::sarq(Register dst, int imm8) { 8664 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8665 int encode = prefixq_and_encode(dst->encoding()); 8666 if (imm8 == 1) { 8667 emit_int8((unsigned char)0xD1); 8668 emit_int8((unsigned char)(0xF8 | encode)); 8669 } else { 8670 emit_int8((unsigned char)0xC1); 8671 emit_int8((unsigned char)(0xF8 | encode)); 8672 emit_int8(imm8); 8673 } 8674 } 8675 8676 void Assembler::sarq(Register dst) { 8677 int encode = prefixq_and_encode(dst->encoding()); 8678 emit_int8((unsigned char)0xD3); 8679 emit_int8((unsigned char)(0xF8 | encode)); 8680 } 8681 8682 void Assembler::sbbq(Address dst, int32_t imm32) { 8683 InstructionMark im(this); 8684 prefixq(dst); 8685 emit_arith_operand(0x81, rbx, dst, imm32); 8686 } 8687 8688 void Assembler::sbbq(Register dst, int32_t imm32) { 8689 (void) prefixq_and_encode(dst->encoding()); 8690 emit_arith(0x81, 0xD8, dst, imm32); 8691 } 8692 8693 void Assembler::sbbq(Register dst, Address src) { 8694 InstructionMark im(this); 8695 prefixq(src, dst); 8696 emit_int8(0x1B); 8697 emit_operand(dst, src); 8698 } 8699 8700 void Assembler::sbbq(Register dst, Register src) { 8701 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8702 emit_arith(0x1B, 0xC0, dst, src); 8703 } 8704 8705 void Assembler::shlq(Register dst, int imm8) { 8706 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8707 int encode = prefixq_and_encode(dst->encoding()); 8708 if (imm8 == 1) { 8709 emit_int8((unsigned char)0xD1); 8710 emit_int8((unsigned char)(0xE0 | encode)); 8711 } else { 8712 emit_int8((unsigned char)0xC1); 8713 emit_int8((unsigned char)(0xE0 | encode)); 8714 emit_int8(imm8); 8715 } 8716 } 8717 8718 void Assembler::shlq(Register dst) { 8719 int encode = prefixq_and_encode(dst->encoding()); 8720 emit_int8((unsigned char)0xD3); 8721 emit_int8((unsigned char)(0xE0 | encode)); 8722 } 8723 8724 void Assembler::shrq(Register dst, int imm8) { 8725 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8726 int encode = prefixq_and_encode(dst->encoding()); 8727 emit_int8((unsigned char)0xC1); 8728 emit_int8((unsigned char)(0xE8 | encode)); 8729 emit_int8(imm8); 8730 } 8731 8732 void Assembler::shrq(Register dst) { 8733 int encode = prefixq_and_encode(dst->encoding()); 8734 emit_int8((unsigned char)0xD3); 8735 emit_int8(0xE8 | encode); 8736 } 8737 8738 void Assembler::subq(Address dst, int32_t imm32) { 8739 InstructionMark im(this); 8740 prefixq(dst); 8741 emit_arith_operand(0x81, rbp, dst, imm32); 8742 } 8743 8744 void Assembler::subq(Address dst, Register src) { 8745 InstructionMark im(this); 8746 prefixq(dst, src); 8747 emit_int8(0x29); 8748 emit_operand(src, dst); 8749 } 8750 8751 void Assembler::subq(Register dst, int32_t imm32) { 8752 (void) prefixq_and_encode(dst->encoding()); 8753 emit_arith(0x81, 0xE8, dst, imm32); 8754 } 8755 8756 // Force generation of a 4 byte immediate value even if it fits into 8bit 8757 void Assembler::subq_imm32(Register dst, int32_t imm32) { 8758 (void) prefixq_and_encode(dst->encoding()); 8759 emit_arith_imm32(0x81, 0xE8, dst, imm32); 8760 } 8761 8762 void Assembler::subq(Register dst, Address src) { 8763 InstructionMark im(this); 8764 prefixq(src, dst); 8765 emit_int8(0x2B); 8766 emit_operand(dst, src); 8767 } 8768 8769 void Assembler::subq(Register dst, Register src) { 8770 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8771 emit_arith(0x2B, 0xC0, dst, src); 8772 } 8773 8774 void Assembler::testq(Register dst, int32_t imm32) { 8775 // not using emit_arith because test 8776 // doesn't support sign-extension of 8777 // 8bit operands 8778 int encode = dst->encoding(); 8779 if (encode == 0) { 8780 prefix(REX_W); 8781 emit_int8((unsigned char)0xA9); 8782 } else { 8783 encode = prefixq_and_encode(encode); 8784 emit_int8((unsigned char)0xF7); 8785 emit_int8((unsigned char)(0xC0 | encode)); 8786 } 8787 emit_int32(imm32); 8788 } 8789 8790 void Assembler::testq(Register dst, Register src) { 8791 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8792 emit_arith(0x85, 0xC0, dst, src); 8793 } 8794 8795 void Assembler::xaddq(Address dst, Register src) { 8796 InstructionMark im(this); 8797 prefixq(dst, src); 8798 emit_int8(0x0F); 8799 emit_int8((unsigned char)0xC1); 8800 emit_operand(src, dst); 8801 } 8802 8803 void Assembler::xchgq(Register dst, Address src) { 8804 InstructionMark im(this); 8805 prefixq(src, dst); 8806 emit_int8((unsigned char)0x87); 8807 emit_operand(dst, src); 8808 } 8809 8810 void Assembler::xchgq(Register dst, Register src) { 8811 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8812 emit_int8((unsigned char)0x87); 8813 emit_int8((unsigned char)(0xc0 | encode)); 8814 } 8815 8816 void Assembler::xorq(Register dst, Register src) { 8817 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8818 emit_arith(0x33, 0xC0, dst, src); 8819 } 8820 8821 void Assembler::xorq(Register dst, Address src) { 8822 InstructionMark im(this); 8823 prefixq(src, dst); 8824 emit_int8(0x33); 8825 emit_operand(dst, src); 8826 } 8827 8828 #endif // !LP64