hotspot Sdiff src/cpu/x86/vm

src/cpu/x86/vm/assembler_x86.cpp

5053   assert(VM_Version::supports_avx(), "");
5054   InstructionMark im(this);
5055   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5056   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5057   attributes.set_rex_vex_w_reverted();
5058   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5059   emit_int8(0x59);
5060   emit_operand(dst, src);
5061 }
5062 
5063 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5064   assert(VM_Version::supports_avx(), "");
5065   InstructionMark im(this);
5066   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5067   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5068   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5069   emit_int8(0x59);
5070   emit_operand(dst, src);
5071 }
5072 




































5073 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5074   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5075   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5076   attributes.set_rex_vex_w_reverted();
5077   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5078   emit_int8(0x5E);
5079   emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081 
5082 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5083   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5084   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5085   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5086   emit_int8(0x5E);
5087   emit_int8((unsigned char)(0xC0 | encode));
5088 }
5089 
5090 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5091   assert(VM_Version::supports_avx(), "");
5092   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);

5053   assert(VM_Version::supports_avx(), "");
5054   InstructionMark im(this);
5055   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5056   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5057   attributes.set_rex_vex_w_reverted();
5058   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5059   emit_int8(0x59);
5060   emit_operand(dst, src);
5061 }
5062 
5063 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5064   assert(VM_Version::supports_avx(), "");
5065   InstructionMark im(this);
5066   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5067   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5068   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5069   emit_int8(0x59);
5070   emit_operand(dst, src);
5071 }
5072 
5073 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5074   assert(VM_Version::supports_fma(), "");
5075   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5076   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5077   emit_int8((unsigned char)0xB8);
5078   emit_int8((unsigned char)(0xC0 | encode));
5079 }
5080 
5081 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5082   assert(VM_Version::supports_fma(), "");
5083   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5084   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5085   emit_int8((unsigned char)0xB8);
5086   emit_int8((unsigned char)(0xC0 | encode));
5087 }
5088 
5089 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5090   assert(VM_Version::supports_fma(), "");
5091   InstructionMark im(this);
5092   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5093   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5094   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5095   emit_int8((unsigned char)0xB8);
5096   emit_operand(dst, src2);
5097 }
5098 
5099 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5100   assert(VM_Version::supports_fma(), "");
5101   InstructionMark im(this);
5102   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5103   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5104   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5105   emit_int8((unsigned char)0xB8);
5106   emit_operand(dst, src2);
5107 }
5108 
5109 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5110   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5111   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5112   attributes.set_rex_vex_w_reverted();
5113   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5114   emit_int8(0x5E);
5115   emit_int8((unsigned char)(0xC0 | encode));
5116 }
5117 
5118 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5119   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5120   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5121   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5122   emit_int8(0x5E);
5123   emit_int8((unsigned char)(0xC0 | encode));
5124 }
5125 
5126 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5127   assert(VM_Version::supports_avx(), "");
5128   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);

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