1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "vm_version_x86.hpp"
34
35
36 int VM_Version::_cpu;
37 int VM_Version::_model;
38 int VM_Version::_stepping;
39 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
40
41 // Address of instruction which causes SEGV
42 address VM_Version::_cpuinfo_segv_addr = 0;
43 // Address of instruction after the one which causes SEGV
44 address VM_Version::_cpuinfo_cont_addr = 0;
45
46 static BufferBlob* stub_blob;
47 static const int stub_size = 1000;
48
49 extern "C" {
50 typedef void (*get_cpu_info_stub_t)(void*);
51 }
52 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
53
54
55 class VM_Version_StubGenerator: public StubCodeGenerator {
56 public:
57
58 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
59
60 address generate_get_cpu_info() {
61 // Flags to test CPU type.
62 const uint32_t HS_EFL_AC = 0x40000;
63 const uint32_t HS_EFL_ID = 0x200000;
64 // Values for when we don't have a CPUID instruction.
65 const int CPU_FAMILY_SHIFT = 8;
66 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
67 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
68 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
69
70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
73
74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
75 # define __ _masm->
76
77 address start = __ pc();
78
79 //
80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
81 //
82 // LP64: rcx and rdx are first and second argument registers on windows
83
84 __ push(rbp);
85 #ifdef _LP64
86 __ mov(rbp, c_rarg0); // cpuid_info address
87 #else
88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
89 #endif
90 __ push(rbx);
91 __ push(rsi);
92 __ pushf(); // preserve rbx, and flags
93 __ pop(rax);
94 __ push(rax);
95 __ mov(rcx, rax);
96 //
97 // if we are unable to change the AC flag, we have a 386
98 //
99 __ xorl(rax, HS_EFL_AC);
100 __ push(rax);
101 __ popf();
102 __ pushf();
103 __ pop(rax);
104 __ cmpptr(rax, rcx);
105 __ jccb(Assembler::notEqual, detect_486);
106
107 __ movl(rax, CPU_FAMILY_386);
108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
109 __ jmp(done);
110
111 //
112 // If we are unable to change the ID flag, we have a 486 which does
113 // not support the "cpuid" instruction.
114 //
115 __ bind(detect_486);
116 __ mov(rax, rcx);
117 __ xorl(rax, HS_EFL_ID);
118 __ push(rax);
119 __ popf();
120 __ pushf();
121 __ pop(rax);
122 __ cmpptr(rcx, rax);
123 __ jccb(Assembler::notEqual, detect_586);
124
125 __ bind(cpu486);
126 __ movl(rax, CPU_FAMILY_486);
127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
128 __ jmp(done);
129
130 //
131 // At this point, we have a chip which supports the "cpuid" instruction
132 //
133 __ bind(detect_586);
134 __ xorl(rax, rax);
135 __ cpuid();
136 __ orl(rax, rax);
137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
138 // value of at least 1, we give up and
139 // assume a 486
140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
141 __ movl(Address(rsi, 0), rax);
142 __ movl(Address(rsi, 4), rbx);
143 __ movl(Address(rsi, 8), rcx);
144 __ movl(Address(rsi,12), rdx);
145
146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
147 __ jccb(Assembler::belowEqual, std_cpuid4);
148
149 //
150 // cpuid(0xB) Processor Topology
151 //
152 __ movl(rax, 0xb);
153 __ xorl(rcx, rcx); // Threads level
154 __ cpuid();
155
156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
157 __ movl(Address(rsi, 0), rax);
158 __ movl(Address(rsi, 4), rbx);
159 __ movl(Address(rsi, 8), rcx);
160 __ movl(Address(rsi,12), rdx);
161
162 __ movl(rax, 0xb);
163 __ movl(rcx, 1); // Cores level
164 __ cpuid();
165 __ push(rax);
166 __ andl(rax, 0x1f); // Determine if valid topology level
167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
168 __ andl(rax, 0xffff);
169 __ pop(rax);
170 __ jccb(Assembler::equal, std_cpuid4);
171
172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
173 __ movl(Address(rsi, 0), rax);
174 __ movl(Address(rsi, 4), rbx);
175 __ movl(Address(rsi, 8), rcx);
176 __ movl(Address(rsi,12), rdx);
177
178 __ movl(rax, 0xb);
179 __ movl(rcx, 2); // Packages level
180 __ cpuid();
181 __ push(rax);
182 __ andl(rax, 0x1f); // Determine if valid topology level
183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
184 __ andl(rax, 0xffff);
185 __ pop(rax);
186 __ jccb(Assembler::equal, std_cpuid4);
187
188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
189 __ movl(Address(rsi, 0), rax);
190 __ movl(Address(rsi, 4), rbx);
191 __ movl(Address(rsi, 8), rcx);
192 __ movl(Address(rsi,12), rdx);
193
194 //
195 // cpuid(0x4) Deterministic cache params
196 //
197 __ bind(std_cpuid4);
198 __ movl(rax, 4);
199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
200 __ jccb(Assembler::greater, std_cpuid1);
201
202 __ xorl(rcx, rcx); // L1 cache
203 __ cpuid();
204 __ push(rax);
205 __ andl(rax, 0x1f); // Determine if valid cache parameters used
206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
207 __ pop(rax);
208 __ jccb(Assembler::equal, std_cpuid1);
209
210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
211 __ movl(Address(rsi, 0), rax);
212 __ movl(Address(rsi, 4), rbx);
213 __ movl(Address(rsi, 8), rcx);
214 __ movl(Address(rsi,12), rdx);
215
216 //
217 // Standard cpuid(0x1)
218 //
219 __ bind(std_cpuid1);
220 __ movl(rax, 1);
221 __ cpuid();
222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
223 __ movl(Address(rsi, 0), rax);
224 __ movl(Address(rsi, 4), rbx);
225 __ movl(Address(rsi, 8), rcx);
226 __ movl(Address(rsi,12), rdx);
227
228 //
229 // Check if OS has enabled XGETBV instruction to access XCR0
230 // (OSXSAVE feature flag) and CPU supports AVX
231 //
232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
233 __ cmpl(rcx, 0x18000000);
234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
235
236 //
237 // XCR0, XFEATURE_ENABLED_MASK register
238 //
239 __ xorl(rcx, rcx); // zero for XCR0 register
240 __ xgetbv();
241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
242 __ movl(Address(rsi, 0), rax);
243 __ movl(Address(rsi, 4), rdx);
244
245 //
246 // cpuid(0x7) Structured Extended Features
247 //
248 __ bind(sef_cpuid);
249 __ movl(rax, 7);
250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
251 __ jccb(Assembler::greater, ext_cpuid);
252
253 __ xorl(rcx, rcx);
254 __ cpuid();
255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
256 __ movl(Address(rsi, 0), rax);
257 __ movl(Address(rsi, 4), rbx);
258
259 //
260 // Extended cpuid(0x80000000)
261 //
262 __ bind(ext_cpuid);
263 __ movl(rax, 0x80000000);
264 __ cpuid();
265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
266 __ jcc(Assembler::belowEqual, done);
267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
268 __ jccb(Assembler::belowEqual, ext_cpuid1);
269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
270 __ jccb(Assembler::belowEqual, ext_cpuid5);
271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid7);
273 //
274 // Extended cpuid(0x80000008)
275 //
276 __ movl(rax, 0x80000008);
277 __ cpuid();
278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
279 __ movl(Address(rsi, 0), rax);
280 __ movl(Address(rsi, 4), rbx);
281 __ movl(Address(rsi, 8), rcx);
282 __ movl(Address(rsi,12), rdx);
283
284 //
285 // Extended cpuid(0x80000007)
286 //
287 __ bind(ext_cpuid7);
288 __ movl(rax, 0x80000007);
289 __ cpuid();
290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
291 __ movl(Address(rsi, 0), rax);
292 __ movl(Address(rsi, 4), rbx);
293 __ movl(Address(rsi, 8), rcx);
294 __ movl(Address(rsi,12), rdx);
295
296 //
297 // Extended cpuid(0x80000005)
298 //
299 __ bind(ext_cpuid5);
300 __ movl(rax, 0x80000005);
301 __ cpuid();
302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
303 __ movl(Address(rsi, 0), rax);
304 __ movl(Address(rsi, 4), rbx);
305 __ movl(Address(rsi, 8), rcx);
306 __ movl(Address(rsi,12), rdx);
307
308 //
309 // Extended cpuid(0x80000001)
310 //
311 __ bind(ext_cpuid1);
312 __ movl(rax, 0x80000001);
313 __ cpuid();
314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
315 __ movl(Address(rsi, 0), rax);
316 __ movl(Address(rsi, 4), rbx);
317 __ movl(Address(rsi, 8), rcx);
318 __ movl(Address(rsi,12), rdx);
319
320 //
321 // Check if OS has enabled XGETBV instruction to access XCR0
322 // (OSXSAVE feature flag) and CPU supports AVX
323 //
324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
327 __ cmpl(rcx, 0x18000000);
328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
329
330 __ movl(rax, 0x6);
331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
332 __ cmpl(rax, 0x6);
333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
334
335 // we need to bridge farther than imm8, so we use this island as a thunk
336 __ bind(done);
337 __ jmp(wrapup);
338
339 __ bind(start_simd_check);
340 //
341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
342 // registers are not restored after a signal processing.
343 // Generate SEGV here (reference through NULL)
344 // and check upper YMM/ZMM bits after it.
345 //
346 intx saved_useavx = UseAVX;
347 intx saved_usesse = UseSSE;
348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
350 __ movl(rax, 0x10000);
351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
352 __ cmpl(rax, 0x10000);
353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
354 // check _cpuid_info.xem_xcr0_eax.bits.opmask
355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
357 __ movl(rax, 0xE0);
358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
359 __ cmpl(rax, 0xE0);
360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
361
362 // If UseAVX is unitialized or is set by the user to include EVEX
363 if (use_evex) {
364 // EVEX setup: run in lowest evex mode
365 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
366 UseAVX = 3;
367 UseSSE = 2;
368 #ifdef _WINDOWS
369 // xmm5-xmm15 are not preserved by caller on windows
370 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
371 __ subptr(rsp, 64);
372 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
373 #ifdef _LP64
374 __ subptr(rsp, 64);
375 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
376 __ subptr(rsp, 64);
377 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
378 #endif // _LP64
379 #endif // _WINDOWS
380
381 // load value into all 64 bytes of zmm7 register
382 __ movl(rcx, VM_Version::ymm_test_value());
383 __ movdl(xmm0, rcx);
384 __ movl(rcx, 0xffff);
385 __ kmovwl(k1, rcx);
386 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
387 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
388 #ifdef _LP64
389 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
390 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
391 #endif
392 VM_Version::clean_cpuFeatures();
393 __ jmp(save_restore_except);
394 }
395
396 __ bind(legacy_setup);
397 // AVX setup
398 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
399 UseAVX = 1;
400 UseSSE = 2;
401 #ifdef _WINDOWS
402 __ subptr(rsp, 32);
403 __ vmovdqu(Address(rsp, 0), xmm7);
404 #ifdef _LP64
405 __ subptr(rsp, 32);
406 __ vmovdqu(Address(rsp, 0), xmm8);
407 __ subptr(rsp, 32);
408 __ vmovdqu(Address(rsp, 0), xmm15);
409 #endif // _LP64
410 #endif // _WINDOWS
411
412 // load value into all 32 bytes of ymm7 register
413 __ movl(rcx, VM_Version::ymm_test_value());
414
415 __ movdl(xmm0, rcx);
416 __ pshufd(xmm0, xmm0, 0x00);
417 __ vinsertf128_high(xmm0, xmm0);
418 __ vmovdqu(xmm7, xmm0);
419 #ifdef _LP64
420 __ vmovdqu(xmm8, xmm0);
421 __ vmovdqu(xmm15, xmm0);
422 #endif
423 VM_Version::clean_cpuFeatures();
424
425 __ bind(save_restore_except);
426 __ xorl(rsi, rsi);
427 VM_Version::set_cpuinfo_segv_addr(__ pc());
428 // Generate SEGV
429 __ movl(rax, Address(rsi, 0));
430
431 VM_Version::set_cpuinfo_cont_addr(__ pc());
432 // Returns here after signal. Save xmm0 to check it later.
433
434 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
435 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
436 __ movl(rax, 0x10000);
437 __ andl(rax, Address(rsi, 4));
438 __ cmpl(rax, 0x10000);
439 __ jccb(Assembler::notEqual, legacy_save_restore);
440 // check _cpuid_info.xem_xcr0_eax.bits.opmask
441 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
442 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
443 __ movl(rax, 0xE0);
444 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
445 __ cmpl(rax, 0xE0);
446 __ jccb(Assembler::notEqual, legacy_save_restore);
447
448 // If UseAVX is unitialized or is set by the user to include EVEX
449 if (use_evex) {
450 // EVEX check: run in lowest evex mode
451 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
452 UseAVX = 3;
453 UseSSE = 2;
454 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
455 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
456 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
457 #ifdef _LP64
458 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
459 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
460 #endif
461
462 #ifdef _WINDOWS
463 #ifdef _LP64
464 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
465 __ addptr(rsp, 64);
466 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
467 __ addptr(rsp, 64);
468 #endif // _LP64
469 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
470 __ addptr(rsp, 64);
471 #endif // _WINDOWS
472 VM_Version::clean_cpuFeatures();
473 UseAVX = saved_useavx;
474 UseSSE = saved_usesse;
475 __ jmp(wrapup);
476 }
477
478 __ bind(legacy_save_restore);
479 // AVX check
480 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
481 UseAVX = 1;
482 UseSSE = 2;
483 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
484 __ vmovdqu(Address(rsi, 0), xmm0);
485 __ vmovdqu(Address(rsi, 32), xmm7);
486 #ifdef _LP64
487 __ vmovdqu(Address(rsi, 64), xmm8);
488 __ vmovdqu(Address(rsi, 96), xmm15);
489 #endif
490
491 #ifdef _WINDOWS
492 #ifdef _LP64
493 __ vmovdqu(xmm15, Address(rsp, 0));
494 __ addptr(rsp, 32);
495 __ vmovdqu(xmm8, Address(rsp, 0));
496 __ addptr(rsp, 32);
497 #endif // _LP64
498 __ vmovdqu(xmm7, Address(rsp, 0));
499 __ addptr(rsp, 32);
500 #endif // _WINDOWS
501 VM_Version::clean_cpuFeatures();
502 UseAVX = saved_useavx;
503 UseSSE = saved_usesse;
504
505 __ bind(wrapup);
506 __ popf();
507 __ pop(rsi);
508 __ pop(rbx);
509 __ pop(rbp);
510 __ ret(0);
511
512 # undef __
513
514 return start;
515 };
516 };
517
518 void VM_Version::get_processor_features() {
519
520 _cpu = 4; // 486 by default
521 _model = 0;
522 _stepping = 0;
523 _features = 0;
524 _logical_processors_per_package = 1;
525 // i486 internal cache is both I&D and has a 16-byte line size
526 _L1_data_cache_line_size = 16;
527
528 // Get raw processor info
529
530 get_cpu_info_stub(&_cpuid_info);
531
532 assert_is_initialized();
533 _cpu = extended_cpu_family();
534 _model = extended_cpu_model();
535 _stepping = cpu_stepping();
536
537 if (cpu_family() > 4) { // it supports CPUID
538 _features = feature_flags();
539 // Logical processors are only available on P4s and above,
540 // and only if hyperthreading is available.
541 _logical_processors_per_package = logical_processor_count();
542 _L1_data_cache_line_size = L1_line_size();
543 }
544
545 _supports_cx8 = supports_cmpxchg8();
546 // xchg and xadd instructions
547 _supports_atomic_getset4 = true;
548 _supports_atomic_getadd4 = true;
549 LP64_ONLY(_supports_atomic_getset8 = true);
550 LP64_ONLY(_supports_atomic_getadd8 = true);
551
552 #ifdef _LP64
553 // OS should support SSE for x64 and hardware should support at least SSE2.
554 if (!VM_Version::supports_sse2()) {
555 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
556 }
557 // in 64 bit the use of SSE2 is the minimum
558 if (UseSSE < 2) UseSSE = 2;
559 #endif
560
561 #ifdef AMD64
562 // flush_icache_stub have to be generated first.
563 // That is why Icache line size is hard coded in ICache class,
564 // see icache_x86.hpp. It is also the reason why we can't use
565 // clflush instruction in 32-bit VM since it could be running
566 // on CPU which does not support it.
567 //
568 // The only thing we can do is to verify that flushed
569 // ICache::line_size has correct value.
570 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
571 // clflush_size is size in quadwords (8 bytes).
572 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
573 #endif
574
575 // If the OS doesn't support SSE, we can't use this feature even if the HW does
576 if (!os::supports_sse())
577 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
578
579 if (UseSSE < 4) {
580 _features &= ~CPU_SSE4_1;
581 _features &= ~CPU_SSE4_2;
582 }
583
584 if (UseSSE < 3) {
585 _features &= ~CPU_SSE3;
586 _features &= ~CPU_SSSE3;
587 _features &= ~CPU_SSE4A;
588 }
589
590 if (UseSSE < 2)
591 _features &= ~CPU_SSE2;
592
593 if (UseSSE < 1)
594 _features &= ~CPU_SSE;
595
596 // first try initial setting and detect what we can support
597 if (UseAVX > 0) {
598 if (UseAVX > 2 && supports_evex()) {
599 UseAVX = 3;
600 } else if (UseAVX > 1 && supports_avx2()) {
601 UseAVX = 2;
602 } else if (UseAVX > 0 && supports_avx()) {
603 UseAVX = 1;
604 } else {
605 UseAVX = 0;
606 }
607 } else if (UseAVX < 0) {
608 UseAVX = 0;
609 }
610
611 if (UseAVX < 3) {
612 _features &= ~CPU_AVX512F;
613 _features &= ~CPU_AVX512DQ;
614 _features &= ~CPU_AVX512CD;
615 _features &= ~CPU_AVX512BW;
616 _features &= ~CPU_AVX512VL;
617 }
618
619 if (UseAVX < 2)
620 _features &= ~CPU_AVX2;
621
622 if (UseAVX < 1)
623 _features &= ~CPU_AVX;
624
625 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
626 _features &= ~CPU_AES;
627
628 if (logical_processors_per_package() == 1) {
629 // HT processor could be installed on a system which doesn't support HT.
630 _features &= ~CPU_HT;
631 }
632
633 char buf[256];
634 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
635 cores_per_cpu(), threads_per_core(),
636 cpu_family(), _model, _stepping,
637 (supports_cmov() ? ", cmov" : ""),
638 (supports_cmpxchg8() ? ", cx8" : ""),
639 (supports_fxsr() ? ", fxsr" : ""),
640 (supports_mmx() ? ", mmx" : ""),
641 (supports_sse() ? ", sse" : ""),
642 (supports_sse2() ? ", sse2" : ""),
643 (supports_sse3() ? ", sse3" : ""),
644 (supports_ssse3()? ", ssse3": ""),
645 (supports_sse4_1() ? ", sse4.1" : ""),
646 (supports_sse4_2() ? ", sse4.2" : ""),
647 (supports_popcnt() ? ", popcnt" : ""),
648 (supports_avx() ? ", avx" : ""),
649 (supports_avx2() ? ", avx2" : ""),
650 (supports_aes() ? ", aes" : ""),
651 (supports_clmul() ? ", clmul" : ""),
652 (supports_erms() ? ", erms" : ""),
653 (supports_rtm() ? ", rtm" : ""),
654 (supports_mmx_ext() ? ", mmxext" : ""),
655 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
656 (supports_lzcnt() ? ", lzcnt": ""),
657 (supports_sse4a() ? ", sse4a": ""),
658 (supports_ht() ? ", ht": ""),
659 (supports_tsc() ? ", tsc": ""),
660 (supports_tscinv_bit() ? ", tscinvbit": ""),
661 (supports_tscinv() ? ", tscinv": ""),
662 (supports_bmi1() ? ", bmi1" : ""),
663 (supports_bmi2() ? ", bmi2" : ""),
664 (supports_adx() ? ", adx" : ""),
665 (supports_evex() ? ", evex" : ""),
666 (supports_sha() ? ", sha" : ""),
667 (supports_fma() ? ", fma" : ""));
668 _features_string = os::strdup(buf);
669
670 // UseSSE is set to the smaller of what hardware supports and what
671 // the command line requires. I.e., you cannot set UseSSE to 2 on
672 // older Pentiums which do not support it.
673 if (UseSSE > 4) UseSSE=4;
674 if (UseSSE < 0) UseSSE=0;
675 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
676 UseSSE = MIN2((intx)3,UseSSE);
677 if (!supports_sse3()) // Drop to 2 if no SSE3 support
678 UseSSE = MIN2((intx)2,UseSSE);
679 if (!supports_sse2()) // Drop to 1 if no SSE2 support
680 UseSSE = MIN2((intx)1,UseSSE);
681 if (!supports_sse ()) // Drop to 0 if no SSE support
682 UseSSE = 0;
683
684 // Use AES instructions if available.
685 if (supports_aes()) {
686 if (FLAG_IS_DEFAULT(UseAES)) {
687 FLAG_SET_DEFAULT(UseAES, true);
688 }
689 if (!UseAES) {
690 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
691 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
692 }
693 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
694 } else {
695 if (UseSSE > 2) {
696 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
697 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
698 }
699 } else {
700 // The AES intrinsic stubs require AES instruction support (of course)
701 // but also require sse3 mode or higher for instructions it use.
702 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
703 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
704 }
705 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
706 }
707
708 // --AES-CTR begins--
709 if (!UseAESIntrinsics) {
710 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
711 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
712 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
713 }
714 } else {
715 if(supports_sse4_1()) {
716 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
717 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
718 }
719 } else {
720 // The AES-CTR intrinsic stubs require AES instruction support (of course)
721 // but also require sse4.1 mode or higher for instructions it use.
722 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
723 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
724 }
725 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
726 }
727 }
728 // --AES-CTR ends--
729 }
730 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
731 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
732 warning("AES instructions are not available on this CPU");
733 FLAG_SET_DEFAULT(UseAES, false);
734 }
735 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
736 warning("AES intrinsics are not available on this CPU");
737 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
738 }
739 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
740 warning("AES-CTR intrinsics are not available on this CPU");
741 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
742 }
743 }
744
745 // Use CLMUL instructions if available.
746 if (supports_clmul()) {
747 if (FLAG_IS_DEFAULT(UseCLMUL)) {
748 UseCLMUL = true;
749 }
750 } else if (UseCLMUL) {
751 if (!FLAG_IS_DEFAULT(UseCLMUL))
752 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
753 FLAG_SET_DEFAULT(UseCLMUL, false);
754 }
755
756 if (UseCLMUL && (UseSSE > 2)) {
757 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
758 UseCRC32Intrinsics = true;
759 }
760 } else if (UseCRC32Intrinsics) {
761 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
762 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
763 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
764 }
765
766 if (supports_sse4_2()) {
767 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
768 UseCRC32CIntrinsics = true;
769 }
770 }
771 else if (UseCRC32CIntrinsics) {
772 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
773 warning("CRC32C intrinsics are not available on this CPU");
774 }
775 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
776 }
777
778 // GHASH/GCM intrinsics
779 if (UseCLMUL && (UseSSE > 2)) {
780 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
781 UseGHASHIntrinsics = true;
782 }
783 } else if (UseGHASHIntrinsics) {
784 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
785 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
786 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
787 }
788
789 if (supports_fma() && UseSSE >= 2) {
790 if (FLAG_IS_DEFAULT(UseFMA)) {
791 UseFMA = true;
792 }
793 } else if (UseFMA) {
794 warning("FMA instructions are not available on this CPU");
795 FLAG_SET_DEFAULT(UseFMA, false);
796 }
797
798 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
799 if (FLAG_IS_DEFAULT(UseSHA)) {
800 UseSHA = true;
801 }
802 } else if (UseSHA) {
803 warning("SHA instructions are not available on this CPU");
804 FLAG_SET_DEFAULT(UseSHA, false);
805 }
806
807 if (supports_sha() && UseSHA) {
808 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
809 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
810 }
811 } else if (UseSHA1Intrinsics) {
812 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
813 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
814 }
815
816 if (UseSHA) {
817 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
818 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
819 }
820 } else if (UseSHA256Intrinsics) {
821 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
822 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
823 }
824
825 if (UseSHA) {
826 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
827 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
828 }
829 } else if (UseSHA512Intrinsics) {
830 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
831 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
832 }
833
834 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
835 FLAG_SET_DEFAULT(UseSHA, false);
836 }
837
838 if (UseAdler32Intrinsics) {
839 warning("Adler32Intrinsics not available on this CPU.");
840 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
841 }
842
843 if (!supports_rtm() && UseRTMLocking) {
844 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
845 // setting during arguments processing. See use_biased_locking().
846 // VM_Version_init() is executed after UseBiasedLocking is used
847 // in Thread::allocate().
848 vm_exit_during_initialization("RTM instructions are not available on this CPU");
849 }
850
851 #if INCLUDE_RTM_OPT
852 if (UseRTMLocking) {
853 if (is_client_compilation_mode_vm()) {
854 // Only C2 does RTM locking optimization.
855 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
856 // setting during arguments processing. See use_biased_locking().
857 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
858 }
859 if (is_intel_family_core()) {
860 if ((_model == CPU_MODEL_HASWELL_E3) ||
861 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
862 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
863 // currently a collision between SKL and HSW_E3
864 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
865 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
866 } else {
867 warning("UseRTMLocking is only available as experimental option on this platform.");
868 }
869 }
870 }
871 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
872 // RTM locking should be used only for applications with
873 // high lock contention. For now we do not use it by default.
874 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
875 }
876 if (!is_power_of_2(RTMTotalCountIncrRate)) {
877 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
878 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
879 }
880 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
881 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
882 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
883 }
884 } else { // !UseRTMLocking
885 if (UseRTMForStackLocks) {
886 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
887 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
888 }
889 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
890 }
891 if (UseRTMDeopt) {
892 FLAG_SET_DEFAULT(UseRTMDeopt, false);
893 }
894 if (PrintPreciseRTMLockingStatistics) {
895 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
896 }
897 }
898 #else
899 if (UseRTMLocking) {
900 // Only C2 does RTM locking optimization.
901 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
902 // setting during arguments processing. See use_biased_locking().
903 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
904 }
905 #endif
906
907 #ifdef COMPILER2
908 if (UseFPUForSpilling) {
909 if (UseSSE < 2) {
910 // Only supported with SSE2+
911 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
912 }
913 }
914 #endif
915 #if defined(COMPILER2) || INCLUDE_JVMCI
916 if (MaxVectorSize > 0) {
917 if (!is_power_of_2(MaxVectorSize)) {
918 warning("MaxVectorSize must be a power of 2");
919 FLAG_SET_DEFAULT(MaxVectorSize, 64);
920 }
921 if (MaxVectorSize > 64) {
922 FLAG_SET_DEFAULT(MaxVectorSize, 64);
923 }
924 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
925 // 32 bytes vectors (in YMM) are only supported with AVX+
926 FLAG_SET_DEFAULT(MaxVectorSize, 16);
927 }
928 if (UseSSE < 2) {
929 // Vectors (in XMM) are only supported with SSE2+
930 FLAG_SET_DEFAULT(MaxVectorSize, 0);
931 }
932 #if defined(COMPILER2) && defined(ASSERT)
933 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
934 tty->print_cr("State of YMM registers after signal handle:");
935 int nreg = 2 LP64_ONLY(+2);
936 const char* ymm_name[4] = {"0", "7", "8", "15"};
937 for (int i = 0; i < nreg; i++) {
938 tty->print("YMM%s:", ymm_name[i]);
939 for (int j = 7; j >=0; j--) {
940 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
941 }
942 tty->cr();
943 }
944 }
945 #endif // COMPILER2 && ASSERT
946 }
947 #endif // COMPILER2 || INCLUDE_JVMCI
948
949 #ifdef COMPILER2
950 #ifdef _LP64
951 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
952 UseMultiplyToLenIntrinsic = true;
953 }
954 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
955 UseSquareToLenIntrinsic = true;
956 }
957 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
958 UseMulAddIntrinsic = true;
959 }
960 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
961 UseMontgomeryMultiplyIntrinsic = true;
962 }
963 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
964 UseMontgomerySquareIntrinsic = true;
965 }
966 #else
967 if (UseMultiplyToLenIntrinsic) {
968 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
969 warning("multiplyToLen intrinsic is not available in 32-bit VM");
970 }
971 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
972 }
973 if (UseMontgomeryMultiplyIntrinsic) {
974 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
975 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
976 }
977 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
978 }
979 if (UseMontgomerySquareIntrinsic) {
980 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
981 warning("montgomerySquare intrinsic is not available in 32-bit VM");
982 }
983 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
984 }
985 if (UseSquareToLenIntrinsic) {
986 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
987 warning("squareToLen intrinsic is not available in 32-bit VM");
988 }
989 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
990 }
991 if (UseMulAddIntrinsic) {
992 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
993 warning("mulAdd intrinsic is not available in 32-bit VM");
994 }
995 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
996 }
997 #endif
998 #endif // COMPILER2
999
1000 // On new cpus instructions which update whole XMM register should be used
1001 // to prevent partial register stall due to dependencies on high half.
1002 //
1003 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1004 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1005 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1006 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1007
1008 if( is_amd() ) { // AMD cpus specific settings
1009 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1010 // Use it on new AMD cpus starting from Opteron.
1011 UseAddressNop = true;
1012 }
1013 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1014 // Use it on new AMD cpus starting from Opteron.
1015 UseNewLongLShift = true;
1016 }
1017 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1018 if (supports_sse4a()) {
1019 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1020 } else {
1021 UseXmmLoadAndClearUpper = false;
1022 }
1023 }
1024 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1025 if( supports_sse4a() ) {
1026 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1027 } else {
1028 UseXmmRegToRegMoveAll = false;
1029 }
1030 }
1031 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1032 if( supports_sse4a() ) {
1033 UseXmmI2F = true;
1034 } else {
1035 UseXmmI2F = false;
1036 }
1037 }
1038 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1039 if( supports_sse4a() ) {
1040 UseXmmI2D = true;
1041 } else {
1042 UseXmmI2D = false;
1043 }
1044 }
1045 if (supports_sse4_2()) {
1046 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1047 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1048 }
1049 } else {
1050 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1051 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1052 }
1053 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1054 }
1055
1056 // some defaults for AMD family 15h
1057 if ( cpu_family() == 0x15 ) {
1058 // On family 15h processors default is no sw prefetch
1059 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1060 AllocatePrefetchStyle = 0;
1061 }
1062 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1063 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1064 AllocatePrefetchInstr = 3;
1065 }
1066 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1067 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1068 UseXMMForArrayCopy = true;
1069 }
1070 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1071 UseUnalignedLoadStores = true;
1072 }
1073 }
1074
1075 #ifdef COMPILER2
1076 if (MaxVectorSize > 16) {
1077 // Limit vectors size to 16 bytes on current AMD cpus.
1078 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1079 }
1080 #endif // COMPILER2
1081 }
1082
1083 if( is_intel() ) { // Intel cpus specific settings
1084 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1085 UseStoreImmI16 = false; // don't use it on Intel cpus
1086 }
1087 if( cpu_family() == 6 || cpu_family() == 15 ) {
1088 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1089 // Use it on all Intel cpus starting from PentiumPro
1090 UseAddressNop = true;
1091 }
1092 }
1093 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1094 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1095 }
1096 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1097 if( supports_sse3() ) {
1098 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1099 } else {
1100 UseXmmRegToRegMoveAll = false;
1101 }
1102 }
1103 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1104 #ifdef COMPILER2
1105 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1106 // For new Intel cpus do the next optimization:
1107 // don't align the beginning of a loop if there are enough instructions
1108 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1109 // in current fetch line (OptoLoopAlignment) or the padding
1110 // is big (> MaxLoopPad).
1111 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1112 // generated NOP instructions. 11 is the largest size of one
1113 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1114 MaxLoopPad = 11;
1115 }
1116 #endif // COMPILER2
1117 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1118 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1119 }
1120 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1121 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1122 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1123 }
1124 }
1125 if (supports_sse4_2()) {
1126 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1127 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1128 }
1129 } else {
1130 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1131 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1132 }
1133 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1134 }
1135 }
1136 if ((cpu_family() == 0x06) &&
1137 ((extended_cpu_model() == 0x36) || // Centerton
1138 (extended_cpu_model() == 0x37) || // Silvermont
1139 (extended_cpu_model() == 0x4D))) {
1140 #ifdef COMPILER2
1141 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1142 OptoScheduling = true;
1143 }
1144 #endif
1145 if (supports_sse4_2()) { // Silvermont
1146 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1147 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1148 }
1149 }
1150 }
1151 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1152 AllocatePrefetchInstr = 3;
1153 }
1154 }
1155
1156 #ifdef _LP64
1157 if (UseSSE42Intrinsics) {
1158 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1159 UseVectorizedMismatchIntrinsic = true;
1160 }
1161 } else if (UseVectorizedMismatchIntrinsic) {
1162 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1163 warning("vectorizedMismatch intrinsics are not available on this CPU");
1164 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1165 }
1166 #else
1167 if (UseVectorizedMismatchIntrinsic) {
1168 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1169 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1170 }
1171 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1172 }
1173 #endif // _LP64
1174
1175 // Use count leading zeros count instruction if available.
1176 if (supports_lzcnt()) {
1177 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1178 UseCountLeadingZerosInstruction = true;
1179 }
1180 } else if (UseCountLeadingZerosInstruction) {
1181 warning("lzcnt instruction is not available on this CPU");
1182 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1183 }
1184
1185 // Use count trailing zeros instruction if available
1186 if (supports_bmi1()) {
1187 // tzcnt does not require VEX prefix
1188 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1189 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1190 // Don't use tzcnt if BMI1 is switched off on command line.
1191 UseCountTrailingZerosInstruction = false;
1192 } else {
1193 UseCountTrailingZerosInstruction = true;
1194 }
1195 }
1196 } else if (UseCountTrailingZerosInstruction) {
1197 warning("tzcnt instruction is not available on this CPU");
1198 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1199 }
1200
1201 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1202 // VEX prefix is generated only when AVX > 0.
1203 if (supports_bmi1() && supports_avx()) {
1204 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1205 UseBMI1Instructions = true;
1206 }
1207 } else if (UseBMI1Instructions) {
1208 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1209 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1210 }
1211
1212 if (supports_bmi2() && supports_avx()) {
1213 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1214 UseBMI2Instructions = true;
1215 }
1216 } else if (UseBMI2Instructions) {
1217 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1218 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1219 }
1220
1221 // Use population count instruction if available.
1222 if (supports_popcnt()) {
1223 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1224 UsePopCountInstruction = true;
1225 }
1226 } else if (UsePopCountInstruction) {
1227 warning("POPCNT instruction is not available on this CPU");
1228 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1229 }
1230
1231 // Use fast-string operations if available.
1232 if (supports_erms()) {
1233 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1234 UseFastStosb = true;
1235 }
1236 } else if (UseFastStosb) {
1237 warning("fast-string operations are not available on this CPU");
1238 FLAG_SET_DEFAULT(UseFastStosb, false);
1239 }
1240
1241 #ifdef COMPILER2
1242 if (FLAG_IS_DEFAULT(AlignVector)) {
1243 // Modern processors allow misaligned memory operations for vectors.
1244 AlignVector = !UseUnalignedLoadStores;
1245 }
1246 #endif // COMPILER2
1247
1248 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1249 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1250
1251 // Allocation prefetch settings
1252 intx cache_line_size = prefetch_data_size();
1253 if( cache_line_size > AllocatePrefetchStepSize )
1254 AllocatePrefetchStepSize = cache_line_size;
1255
1256 AllocatePrefetchDistance = allocate_prefetch_distance();
1257 AllocatePrefetchStyle = allocate_prefetch_style();
1258
1259 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1260 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1261 #ifdef _LP64
1262 AllocatePrefetchDistance = 384;
1263 #else
1264 AllocatePrefetchDistance = 320;
1265 #endif
1266 }
1267 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1268 AllocatePrefetchDistance = 192;
1269 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
1270 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1271 }
1272 }
1273 #ifdef COMPILER2
1274 if (supports_sse4_2()) {
1275 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1276 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1277 }
1278 }
1279 #endif
1280 }
1281
1282 #ifdef _LP64
1283 // Prefetch settings
1284 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1285 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1286 PrefetchFieldsAhead = prefetch_fields_ahead();
1287 #endif
1288
1289 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1290 (cache_line_size > ContendedPaddingWidth))
1291 ContendedPaddingWidth = cache_line_size;
1292
1293 // This machine allows unaligned memory accesses
1294 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1295 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1296 }
1297
1298 #ifndef PRODUCT
1299 if (log_is_enabled(Info, os, cpu)) {
1300 outputStream* log = Log(os, cpu)::info_stream();
1301 log->print_cr("Logical CPUs per core: %u",
1302 logical_processors_per_package());
1303 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1304 log->print("UseSSE=%d", (int) UseSSE);
1305 if (UseAVX > 0) {
1306 log->print(" UseAVX=%d", (int) UseAVX);
1307 }
1308 if (UseAES) {
1309 log->print(" UseAES=1");
1310 }
1311 #ifdef COMPILER2
1312 if (MaxVectorSize > 0) {
1313 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1314 }
1315 #endif
1316 log->cr();
1317 log->print("Allocation");
1318 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1319 log->print_cr(": no prefetching");
1320 } else {
1321 log->print(" prefetching: ");
1322 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1323 log->print("PREFETCHW");
1324 } else if (UseSSE >= 1) {
1325 if (AllocatePrefetchInstr == 0) {
1326 log->print("PREFETCHNTA");
1327 } else if (AllocatePrefetchInstr == 1) {
1328 log->print("PREFETCHT0");
1329 } else if (AllocatePrefetchInstr == 2) {
1330 log->print("PREFETCHT2");
1331 } else if (AllocatePrefetchInstr == 3) {
1332 log->print("PREFETCHW");
1333 }
1334 }
1335 if (AllocatePrefetchLines > 1) {
1336 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1337 } else {
1338 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1339 }
1340 }
1341
1342 if (PrefetchCopyIntervalInBytes > 0) {
1343 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1344 }
1345 if (PrefetchScanIntervalInBytes > 0) {
1346 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1347 }
1348 if (PrefetchFieldsAhead > 0) {
1349 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1350 }
1351 if (ContendedPaddingWidth > 0) {
1352 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1353 }
1354 }
1355 #endif // !PRODUCT
1356 }
1357
1358 bool VM_Version::use_biased_locking() {
1359 #if INCLUDE_RTM_OPT
1360 // RTM locking is most useful when there is high lock contention and
1361 // low data contention. With high lock contention the lock is usually
1362 // inflated and biased locking is not suitable for that case.
1363 // RTM locking code requires that biased locking is off.
1364 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1365 // because it is used by Thread::allocate() which is called before
1366 // VM_Version::initialize().
1367 if (UseRTMLocking && UseBiasedLocking) {
1368 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1369 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1370 } else {
1371 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1372 UseBiasedLocking = false;
1373 }
1374 }
1375 #endif
1376 return UseBiasedLocking;
1377 }
1378
1379 void VM_Version::initialize() {
1380 ResourceMark rm;
1381 // Making this stub must be FIRST use of assembler
1382
1383 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1384 if (stub_blob == NULL) {
1385 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1386 }
1387 CodeBuffer c(stub_blob);
1388 VM_Version_StubGenerator g(&c);
1389 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1390 g.generate_get_cpu_info());
1391
1392 get_processor_features();
1393 }